[PATCH 1/9] ARM: pxa: add clk_set_rate()

[PATCH 1/9] ARM: pxa: add clk_set_rate()

[Haojian Zhuang]

Since there're mulitple clock rates in some device controllers, enable
clk_set_rate() for this usage.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/clock.c |   15 +++++++++++++++
 arch/arm/mach-mmp/clock.h |    1 +
 arch/arm/mach-pxa/clock.c |   15 +++++++++++++++
 arch/arm/mach-pxa/clock.h |    1 +
 4 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
index 886e056..7c6f95f 100644
--- a/arch/arm/mach-mmp/clock.c
+++ b/arch/arm/mach-mmp/clock.c
@@ -88,3 +88,18 @@ unsigned long clk_get_rate(struct clk *clk)
 	return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long flags;
+	int ret = -EINVAL;
+
+	if (clk->ops->setrate) {
+		spin_lock_irqsave(&clocks_lock, flags);
+		ret = clk->ops->setrate(clk, rate);
+		spin_unlock_irqrestore(&clocks_lock, flags);
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
index 9b027d7..3143e99 100644
--- a/arch/arm/mach-mmp/clock.h
+++ b/arch/arm/mach-mmp/clock.h
@@ -12,6 +12,7 @@ struct clkops {
 	void			(*enable)(struct clk *);
 	void			(*disable)(struct clk *);
 	unsigned long		(*getrate)(struct clk *);
+	int			(*setrate)(struct clk *, unsigned long);
 };
 
 struct clk {
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index d515222..4d46610 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -53,6 +53,21 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long flags;
+	int ret = -EINVAL;
+
+	if (clk->ops->setrate) {
+		spin_lock_irqsave(&clocks_lock, flags);
+		ret = clk->ops->setrate(clk, rate);
+		spin_unlock_irqrestore(&clocks_lock, flags);
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
 void clk_dummy_enable(struct clk *clk)
 {
 }
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index f9f349a..7373853 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -5,6 +5,7 @@ struct clkops {
 	void			(*enable)(struct clk *);
 	void			(*disable)(struct clk *);
 	unsigned long		(*getrate)(struct clk *);
+	int			(*setrate)(struct clk *, unsigned long);
 };
 
 struct clk {
-- 
1.5.6.5

[PATCH 2/9] ARM: pxa: enable sparsemem in saarb

[Haojian Zhuang]

Make sparsemem to support 512MB low memory with two banks in SAARB.

Change-Id: I1688dde366b5f3b13b48b7167bf6b88afc4f9a92
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-pxa/Kconfig               |    1 +
 arch/arm/mach-pxa/include/mach/memory.h |   36 ++++++++++++++++++++++++++++++-
 2 files changed, 36 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 2fc9f94..e8615ee 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -53,6 +53,7 @@ config MACH_SAAR
 config MACH_SAARB
 	bool "PXA955 Handheld Platform (aka SAARB)"
 	select CPU_PXA955
+	select ARCH_SPARSEMEM_ENABLE
 
 comment "Third Party Dev Platforms (sorted by vendor name)"
 
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index 92361a6..9a3f265 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -3,6 +3,7 @@
  *
  * Author:	Nicolas Pitre
  * Copyright:	(C) 2001 MontaVista Software Inc.
+ * Copyright:	(C) 2010 Marvell Semiconductor Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -27,4 +28,37 @@ void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes);
 #define MAX_DMA_ADDRESS		(PAGE_OFFSET + SZ_64M)
 #endif
 
-#endif
+
+#ifdef CONFIG_SPARSEMEM
+
+#if defined(CONFIG_MACH_SAARB) || defined(CONFIG_MACH_SAARB_MG1)
+/*
+ * There're two DRAM banks in PXA955 Saarb board.
+ *
+ * The macros below define sections with 256MB size and a non-linear virtual to
+ * physical mapping:
+ *
+ * node 0: 0x80000000-0x8fffffff -> 0xc0000000-0xcfffffff
+ * node 1: 0xc0000000-0xcfffffff -> 0xd0000000-0xdfffffff
+ *
+ * Since DRAM can be wrapped, 0xa0000000 equals to 0x80000000.
+ */
+#define MAX_PHYSMEM_BITS	32
+#define SECTION_SIZE_BITS	28
+
+/* bank page offsets */
+#define BANK_PAGE_OFFSET	(PAGE_OFFSET + 0x10000000)
+
+#define __phys_to_virt(phys)						\
+	((phys) >= 0xc0000000 ? (phys) - 0xc0000000 + BANK_PAGE_OFFSET :\
+	 (phys) >= 0xa0000000 ? (phys) - 0xa0000000 + PAGE_OFFSET :	\
+	 (phys) - 0x80000000 + PAGE_OFFSET)				\
+
+#define __virt_to_phys(virt)						\
+	((virt) >= BANK_PAGE_OFFSET ? (virt) - BANK_PAGE_OFFSET + 0xc0000000 :\
+	 (virt) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
+#endif	/* CONFIG_MACH_SAARB || CONFIG_MACH_SAARB_MG1 */
+
+#endif	/* CONFIG_SPARSEMEM */
+
+#endif	/* __ASM_ARCH_MEMORY_H */
-- 
1.5.6.5

[PATCH 3/9] ARM: mmp: remove redundant macro definition in mfp

[Haojian Zhuang]

There're two layers in MFP implementation. One is MFP layer that is logical
pin setting. And the other is MFPR layer that is physical register setting.

MFP drive setting is different between PXA168 and PXA910. But the difference
was stored in logical layer, not physical layer. And some unnecessary macro
definition were added for ARCH_MMP.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/include/mach/mfp-mmp2.h   |    7 +----
 arch/arm/mach-mmp/include/mach/mfp-pxa168.h |    7 +----
 arch/arm/mach-mmp/include/mach/mfp-pxa910.h |    7 +----
 arch/arm/mach-mmp/include/mach/mfp.h        |   34 ---------------------------
 arch/arm/mach-mmp/mmp2.c                    |    2 +-
 arch/arm/mach-mmp/pxa168.c                  |    2 +-
 arch/arm/mach-mmp/pxa910.c                  |    2 +-
 arch/arm/plat-pxa/include/plat/mfp.h        |    4 +++
 arch/arm/plat-pxa/mfp.c                     |   22 +++++++++++++++-
 9 files changed, 30 insertions(+), 57 deletions(-)
 delete mode 100644 arch/arm/mach-mmp/include/mach/mfp.h

diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
index 4ad3862..c66eaea 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
@@ -1,12 +1,7 @@
 #ifndef __ASM_MACH_MFP_MMP2_H
 #define __ASM_MACH_MFP_MMP2_H
 
-#include <mach/mfp.h>
-
-#define MFP_DRIVE_VERY_SLOW	(0x0 << 13)
-#define MFP_DRIVE_SLOW		(0x2 << 13)
-#define MFP_DRIVE_MEDIUM	(0x4 << 13)
-#define MFP_DRIVE_FAST		(0x6 << 13)
+#include <plat/mfp.h>
 
 /* GPIO */
 #define GPIO0_GPIO	MFP_CFG(GPIO0, AF0)
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index 4621067..4aadbea 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -1,12 +1,7 @@
 #ifndef __ASM_MACH_MFP_PXA168_H
 #define __ASM_MACH_MFP_PXA168_H
 
-#include <mach/mfp.h>
-
-#define MFP_DRIVE_VERY_SLOW	(0x0 << 13)
-#define MFP_DRIVE_SLOW		(0x1 << 13)
-#define MFP_DRIVE_MEDIUM	(0x2 << 13)
-#define MFP_DRIVE_FAST		(0x3 << 13)
+#include <plat/mfp.h>
 
 /* GPIO */
 #define GPIO0_GPIO		MFP_CFG(GPIO0, AF5)
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
index fbd7ee8..f5d33be 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
@@ -1,12 +1,7 @@
 #ifndef __ASM_MACH_MFP_PXA910_H
 #define __ASM_MACH_MFP_PXA910_H
 
-#include <mach/mfp.h>
-
-#define MFP_DRIVE_VERY_SLOW	(0x0 << 13)
-#define MFP_DRIVE_SLOW		(0x2 << 13)
-#define MFP_DRIVE_MEDIUM	(0x4 << 13)
-#define MFP_DRIVE_FAST		(0x6 << 13)
+#include <plat/mfp.h>
 
 /* UART2 */
 #define GPIO47_UART2_RXD	MFP_CFG(GPIO47, AF6)
diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h
deleted file mode 100644
index 62e510e..0000000
--- a/arch/arm/mach-mmp/include/mach/mfp.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __ASM_MACH_MFP_H
-#define __ASM_MACH_MFP_H
-
-#include <plat/mfp.h>
-
-/*
- * NOTE: the MFPR register bit definitions on PXA168 processor lines are a
- * bit different from those on PXA3xx.  Bit [7:10] are now reserved, which
- * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
- *
- * To cope with this difference and re-use the pxa3xx mfp code as much as
- * possible, we make the following compromise:
- *
- * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
- * 2. DRIVE strength definitions redefined to include the reserved bit
- *    - the reserved bit differs between pxa168 and pxa910, and the
- *      MFP_DRIVE_* macros are individually defined in mfp-pxa{168,910}.h
- * 3. Override MFP_CFG() and MFP_CFG_DRV()
- * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
- */
-
-#undef MFP_CFG
-#undef MFP_CFG_DRV
-#undef MFP_CFG_LPM
-#undef MFP_CFG_X
-#undef MFP_CFG_DEFAULT
-
-#define MFP_CFG(pin, af)		\
-	(MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
-
-#define MFP_CFG_DRV(pin, af, drv)	\
-	(MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
-
-#endif /* __ASM_MACH_MFP_H */
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 8e6c3ac..14e6a23 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -24,10 +24,10 @@
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/dma.h>
-#include <mach/mfp.h>
 #include <mach/gpio.h>
 #include <mach/devices.h>
 #include <mach/mmp2.h>
+#include <plat/mfp.h>
 
 #include "common.h"
 #include "clock.h"
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 72b4e76..34df2b1 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -24,7 +24,7 @@
 #include <mach/gpio.h>
 #include <mach/dma.h>
 #include <mach/devices.h>
-#include <mach/mfp.h>
+#include <plat/mfp.h>
 
 #include "common.h"
 #include "clock.h"
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 8f92ccd..93b3b25 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -22,8 +22,8 @@
 #include <mach/irqs.h>
 #include <mach/gpio.h>
 #include <mach/dma.h>
-#include <mach/mfp.h>
 #include <mach/devices.h>
+#include <plat/mfp.h>
 
 #include "common.h"
 #include "clock.h"
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
index 75f6564..b7dde0c 100644
--- a/arch/arm/plat-pxa/include/plat/mfp.h
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -378,6 +378,10 @@ typedef unsigned long mfp_cfg_t;
 #define MFP_DS13X		(0x7 << 13)
 #define MFP_DS_MASK		(0x7 << 13)
 #define MFP_DS(x)		(((x) >> 13) & 0x7)
+#define MFP_VERY_SLOW		MFP_DS01X
+#define MFP_SLOW		MFP_DS02X
+#define MFP_MEDIUM		MFP_DS03X
+#define MFP_FAST		MFP_DS04X
 
 #define MFP_LPM_DEFAULT		(0x0 << 16)
 #define MFP_LPM_DRIVE_LOW	(0x1 << 16)
diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c
index a9aa5ad..d335551 100644
--- a/arch/arm/plat-pxa/mfp.c
+++ b/arch/arm/plat-pxa/mfp.c
@@ -19,6 +19,10 @@
 #include <linux/io.h>
 #include <linux/sysdev.h>
 
+#ifdef CONFIG_ARCH_MMP
+#include <mach/cputype.h>
+#endif
+
 #include <plat/mfp.h>
 
 #define MFPR_SIZE	(PAGE_SIZE)
@@ -165,8 +169,14 @@ static inline void __mfp_config_lpm(struct mfp_pin *p)
 void mfp_config(unsigned long *mfp_cfgs, int num)
 {
 	unsigned long flags;
-	int i;
-
+	int i, drv_b11 = 0, no_lpm = 0;
+
+#ifdef CONFIG_ARCH_MMP
+	if (cpu_is_pxa910() || cpu_is_mmp2())
+		drv_b11 = 1;
+	if (cpu_is_pxa168() || cpu_is_pxa910())
+		no_lpm = 1;
+#endif
 	spin_lock_irqsave(&mfp_spin_lock, flags);
 
 	for (i = 0; i < num; i++, mfp_cfgs++) {
@@ -183,6 +193,10 @@ void mfp_config(unsigned long *mfp_cfgs, int num)
 		lpm = MFP_LPM_STATE(c);
 		edge = MFP_LPM_EDGE(c);
 		pull = MFP_PULL(c);
+		if (drv_b11)
+			drv = drv << 1;
+		if (no_lpm)
+			lpm = 0;
 
 		/* run-mode pull settings will conflict with MFPR bits of
 		 * low power mode state,  calculate mfpr_run and mfpr_lpm
@@ -272,6 +286,10 @@ void mfp_config_lpm(void)
 	struct mfp_pin *p = &mfp_table[0];
 	int pin;
 
+#ifdef CONFIG_ARCH_MMP
+	if (cpu_is_pxa168() || cpu_is_pxa910())
+		return;
+#endif
 	for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
 		__mfp_config_lpm(p);
 }
-- 
1.5.6.5

[PATCH 4/9] ARM: pxa: use gpio reset

[Haojian Zhuang]

Watchdog reset will clear RTC and some configuration registers. GPIO reset
doesn't have this impact. So replace watchdog reset by gpio reset.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h |    8 ++++++++
 arch/arm/mach-pxa/reset.c                    |   16 ++++++++++++----
 2 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index e4fb466..28bc2a9 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -37,6 +37,14 @@
 #define PVCR		__REG(0x40F50100)	/* Power Manager Voltage Change Control Register */
 #define PCMD(x)		__REG(0x40F50110 + ((x) << 2))
 
+#define PMCR_BIE	(1 << 0)		/* Interrupt Enable for nBATT_FAULT */
+#define PMCR_BIS	(1 << 1)		/* Interrupt Status for nBATT_FAULT */
+#define PMCR_TIE	(1 << 10)		/* Interrupt Enable for XScale Core Frequency Change */
+#define PMCR_TIS	(1 << 11)		/* Interrupt Status for XScale Core Frequency Change */
+#define PMCR_VIE	(1 << 12)		/* Interrupt Enable for VCC_APPS and VCC_SRAM Voltage Change */
+#define PMCR_VIS	(1 << 13)		/* Interrupt Status for VCC_APPS and VCC_SRAM Voltage Change */
+#define PMCR_SWGR	(1 << 31)		/* Software GPIO Reset */
+
 /*
  * Slave Power Managment Unit
  */
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 01e9d64..611d537 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -12,6 +12,7 @@
 
 #include <mach/regs-ost.h>
 #include <mach/reset.h>
+#include <mach/pxa3xx-regs.h>
 
 unsigned int reset_status;
 EXPORT_SYMBOL(reset_status);
@@ -75,10 +76,17 @@ static void do_gpio_reset(void)
 
 static void do_hw_reset(void)
 {
-	/* Initialize the watchdog and let it fire */
-	OWER = OWER_WME;
-	OSSR = OSSR_M3;
-	OSMR3 = OSCR + 368640;	/* ... in 100 ms */
+	if (cpu_is_pxa3xx() || cpu_is_pxa95x()) {
+		/* GPIO reset that is defined in silicons */
+		PSPR = 0x5c014000;
+		PMCR = (PMCR & (PMCR_BIE | PMCR_TIE | PMCR_VIE))
+			| PMCR_SWGR;
+	} else {
+		/* Initialize the watchdog and let it fire */
+		OWER = OWER_WME;
+		OSSR = OSSR_M3;
+		OSMR3 = OSCR + 368640;	/* ... in 100 ms */
+	}
 }
 
 void arch_reset(char mode, const char *cmd)
-- 
1.5.6.5

[PATCH 5/9] ARM: mmp: set correct uart according to board

[Haojian Zhuang]

UART3 is the default console in jasper, brownstone and avengers lite.

Change-Id: Iacfe665cc0e20a47d50e0b2ad8724097f28e7d2c
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/include/mach/debug-macro.S |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index 7e2ebd3..b353785 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -14,8 +14,14 @@
 		.macro	addruart, rp, rv
 		ldr	\rp, =APB_PHYS_BASE		@ physical
 		ldr	\rv, =APB_VIRT_BASE		@ virtual
+#if defined(CONFIG_MACH_BROWNSTONE) || defined(CONFIG_MACH_MARVELL_JASPER) \
+	|| defined(CONFIG_MACH_AVENGERS_LITE)
+		orr	\rp, \rp, #0x00018000
+		orr	\rv, \rv, #0x00018000
+#else
 		orr	\rp, \rp, #0x00017000
 		orr	\rv, \rv, #0x00017000
+#endif
 		.endm
 
 #define UART_SHIFT	2
-- 
1.5.6.5

[PATCH 6/9] ARM: mmp: update the reset implementation

[Haojian Zhuang]

Both PXA910 and MMP2 need watchdog reset, so add these features.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/Makefile                   |    2 +-
 arch/arm/mach-mmp/include/mach/regs-mpmu.h   |   52 +++++++++++++
 arch/arm/mach-mmp/include/mach/regs-timers.h |    2 +
 arch/arm/mach-mmp/include/mach/system.h      |    8 +--
 arch/arm/mach-mmp/reset.c                    |  100 ++++++++++++++++++++++++++
 5 files changed, 156 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/mach-mmp/include/mach/regs-mpmu.h
 create mode 100644 arch/arm/mach-mmp/reset.c

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 5c68382..6043f31 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,7 +2,7 @@
 # Makefile for Marvell's PXA168 processors line
 #
 
-obj-y				+= common.o clock.o devices.o time.o
+obj-y				+= common.o clock.o devices.o time.o reset.o
 
 # SoC support
 obj-$(CONFIG_CPU_PXA168)	+= pxa168.o irq-pxa168.o
diff --git a/arch/arm/mach-mmp/include/mach/regs-mpmu.h b/arch/arm/mach-mmp/include/mach/regs-mpmu.h
new file mode 100644
index 0000000..e2fdc4e
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-mpmu.h
@@ -0,0 +1,52 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/regs-mpmu.h
+ *
+ *   Main Power Management Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_MPMU_H
+#define __ASM_MACH_REGS_MPMU_H
+
+#include <mach/addr-map.h>
+
+#define MPMU_VIRT_BASE		(APB_VIRT_BASE + 0x50000)
+#define MPMU_REG(off)		(MPMU_VIRT_BASE + (off))
+
+#define MPMU_CPCR		MPMU_REG(0x0000)
+#define MPMU_FCCR		MPMU_REG(0x0008)
+#define MPMU_POCR		MPMU_REG(0x000c)
+#define MPMU_POSR		MPMU_REG(0x0010)
+#define MPMU_SUCCR		MPMU_REG(0x0014)
+#define MPMU_VRCR		MPMU_REG(0x0018)
+#define MPMU_OHCR		MPMU_REG(0x001c)
+#define MPMU_CPRR		MPMU_REG(0x0020)
+#define MPMU_CCGR		MPMU_REG(0x0024)
+#define MPMU_GPCR		MPMU_REG(0x0030)
+#define MPMU_PLL2CR		MPMU_REG(0x0034)
+#define MPMU_SCCR		MPMU_REG(0x0038)
+#define MPMU_ISCCRX0		MPMU_REG(0x0040)
+#define MPMU_ISCCRX1		MPMU_REG(0x0044)
+#define MPMU_CWUCRM		MPMU_REG(0x004c)
+#define MPMU_PLL1_REG1		MPMU_REG(0x0050)
+#define MPMU_PLL1_REG2		MPMU_REG(0x0054)
+#define MPMU_PLL1_SSC		MPMU_REG(0x0058)
+#define MPMU_PLL2_REG1		MPMU_REG(0x0060)
+#define MPMU_PLL2_REG2		MPMU_REG(0x0064)
+#define MPMU_PLL2_SSC		MPMU_REG(0x0068)
+#define MPMU_SD_ROT_WAKE_CLR	MPMU_REG(0x007c)
+#define MPMU_PLL2_CTRL1		MPMU_REG(0x0414)
+#define MPMU_TS			MPMU_REG(0x0080)
+#define MPMU_WDTPCR		MPMU_REG(0x0200)
+#define MPMU_APCR		MPMU_REG(0x1000)
+#define MPMU_APSR		MPMU_REG(0x1004)
+#define MPMU_APRR		MPMU_REG(0x1020)
+#define MPMU_ACGR		MPMU_REG(0x1024)
+#define MPMU_ARSR		MPMU_REG(0x1028)
+#define MPMU_AWUCRS		MPMU_REG(0x1048)
+#define MPMU_AWUCRM		MPMU_REG(0x104c)
+
+#endif /* __ASM_MACH_REGS_MPMU_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-timers.h b/arch/arm/mach-mmp/include/mach/regs-timers.h
index 45589fe..17f56fe 100644
--- a/arch/arm/mach-mmp/include/mach/regs-timers.h
+++ b/arch/arm/mach-mmp/include/mach/regs-timers.h
@@ -15,6 +15,8 @@
 
 #define TIMERS1_VIRT_BASE	(APB_VIRT_BASE + 0x14000)
 #define TIMERS2_VIRT_BASE	(APB_VIRT_BASE + 0x16000)
+#define CP_TIMERS2_VIRT_BASE	(APB_VIRT_BASE + 0x80000)
+#define MMP2_TIMERS2_VIRT_BASE	(APB_VIRT_BASE + 0x80000)
 
 #define TMR_CCR		(0x0000)
 #define TMR_TN_MM(n, m)	(0x0004 + ((n) << 3) + (((n) + (m)) << 2))
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
index 1a8a25e..31e15cf 100644
--- a/arch/arm/mach-mmp/include/mach/system.h
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -16,11 +16,5 @@ static inline void arch_idle(void)
 	cpu_do_idle();
 }
 
-static inline void arch_reset(char mode, const char *cmd)
-{
-	if (cpu_is_pxa168())
-		cpu_reset(0xffff0000);
-	else
-		cpu_reset(0);
-}
+extern void arch_reset(char mode, const char *cmd);
 #endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/reset.c b/arch/arm/mach-mmp/reset.c
new file mode 100644
index 0000000..57fa65e
--- /dev/null
+++ b/arch/arm/mach-mmp/reset.c
@@ -0,0 +1,100 @@
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <mach/regs-mpmu.h>
+#include <mach/regs-timers.h>
+#include <mach/cputype.h>
+#include <linux/delay.h>
+
+#define REG_RTC_BR0     	(APB_VIRT_BASE + 0x010014)
+
+#define MPMU_APRR_CPR   	(1 << 0)
+#define MPMU_APRR_WDTR  	(1 << 4)
+#define MPMU_CPRR_DSPR  	(1 << 2)
+#define MPMU_CPRR_BBR   	(1 << 3)
+
+static void do_wdt_reset(const char *cmd)
+{
+	unsigned int reg, backup;
+	unsigned int watchdog_virt_base;
+	int i;
+	int match = 0, count = 0;
+
+	if (cpu_is_pxa910())
+		watchdog_virt_base = CP_TIMERS2_VIRT_BASE;
+	else if (cpu_is_pxa168())
+		watchdog_virt_base = TIMERS1_VIRT_BASE;
+	else if (cpu_is_mmp2())
+		watchdog_virt_base = MMP2_TIMERS2_VIRT_BASE;
+	else
+		return;
+
+	/* reset/enable WDT clock */
+	writel(0x7, MPMU_WDTPCR);
+	readl(MPMU_WDTPCR);
+	writel(0x3, MPMU_WDTPCR);
+	readl(MPMU_WDTPCR);
+
+	if (cpu_is_pxa910()) {
+		/* stores recovery flag into RTC register */
+		if (cmd && !strcmp(cmd, "recovery")) {
+			for (i = 0, backup = 0; i < 4; i++) {
+				backup <<= 8;
+				backup |= *(cmd + i);
+			}
+			do {
+				writel(backup, REG_RTC_BR0);
+			} while (readl(REG_RTC_BR0) != backup);
+		}
+	}
+
+	/* enable WDT reset */
+	writel(0xbaba, watchdog_virt_base + TMR_WFAR);
+	writel(0xeb10, watchdog_virt_base + TMR_WSAR);
+	writel(0x3, watchdog_virt_base + TMR_WMER);
+
+	if (cpu_is_pxa910()) {
+		/*hold CP first */
+		reg = readl(MPMU_APRR) | MPMU_APRR_CPR;
+		writel(reg, MPMU_APRR);
+		udelay(10);
+		/*CP reset MSA */
+		reg = readl(MPMU_CPRR) | MPMU_CPRR_DSPR | MPMU_CPRR_BBR;
+		writel(reg, MPMU_CPRR);
+		udelay(10);
+	}
+	/* negate hardware reset to the WDT after system reset */
+	reg = readl(MPMU_APRR) | MPMU_APRR_WDTR;
+	writel(reg, MPMU_APRR);
+
+	/* clear previous WDT status */
+	writel(0xbaba, watchdog_virt_base + TMR_WFAR);
+	writel(0xeb10, watchdog_virt_base + TMR_WSAR);
+	writel(0, watchdog_virt_base + TMR_WSR);
+
+	match = readl(watchdog_virt_base + TMR_WMR);
+	count = readl(watchdog_virt_base + TMR_WVR);
+
+	if (match - count > 0x20) {
+		/* set match counter */
+		writel(0xbaba, watchdog_virt_base + TMR_WFAR);
+		writel(0xeb10, watchdog_virt_base + TMR_WSAR);
+		writel(0x20 + count, watchdog_virt_base + TMR_WMR);
+	}
+}
+
+void arch_reset(char mode, const char *cmd)
+{
+	switch (mode) {
+	case 's':
+		/* Jump into ROM */
+		if (cpu_is_pxa168()) {
+			cpu_reset(0xffff0000);
+			break;
+		}
+	case 'w':
+	default:
+		do_wdt_reset(cmd);
+		break;
+	}
+}
-- 
1.5.6.5

[PATCH 7/9] ARM: pxa: align NR_BUILTIN_GPIO with GPIO interrupt number

[Haojian Zhuang]

Avoid to mismatch between NR_BUILTIN_GPIO and GPIO interrupt number

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-pxa/include/mach/gpio.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
index b024a8b..48ef925 100644
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -99,7 +99,7 @@
 #define GAFR(x)		GPIO_REG(0x54 + (((x) & 0x70) >> 2))
 
 
-#define NR_BUILTIN_GPIO 128
+#define NR_BUILTIN_GPIO		PXA_GPIO_IRQ_NUM
 
 #define gpio_to_bank(gpio)	((gpio) >> 5)
 #define gpio_to_irq(gpio)	IRQ_GPIO(gpio)
-- 
1.5.6.5

[PATCH 8/9] ARM: mmp: align NR_BUILTIN_GPIO with gpio interrupt number

[Haojian Zhuang]

Avoid to mismatch between NR_BUILTIN_GPIO and gpio interrupt number.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/include/mach/gpio.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
index ee8b02e..7bfb827 100644
--- a/arch/arm/mach-mmp/include/mach/gpio.h
+++ b/arch/arm/mach-mmp/include/mach/gpio.h
@@ -10,7 +10,7 @@
 #define BANK_OFF(n)	(((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 #define GPIO_REG(x)	(*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
 
-#define NR_BUILTIN_GPIO	(192)
+#define NR_BUILTIN_GPIO		IRQ_GPIO_NUM
 
 #define gpio_to_bank(gpio)	((gpio) >> 5)
 #define gpio_to_irq(gpio)	(IRQ_GPIO_START + (gpio))
-- 
1.5.6.5

[PATCH 9/9] ARM: mmp: enable max7312 gpio expander in dkb

[Haojian Zhuang]

Support max7312 gpio expander in TTC DKB.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/ttc_dkb.c |   31 ++++++++++++++++++++++++++++++-
 1 files changed, 30 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index e411039..9d3ef01 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -15,17 +15,29 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/onenand.h>
 #include <linux/interrupt.h>
+#include <linux/i2c/pca953x.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <mach/addr-map.h>
+#include <mach/gpio.h>
 #include <mach/mfp-pxa910.h>
 #include <mach/pxa910.h>
 
 #include "common.h"
 
-#define TTCDKB_NR_IRQS		(IRQ_BOARD_START + 24)
+#define TTCDKB_GPIO_EXT0(x)	(NR_BUILTIN_GPIO + ((x < 0) ? 0 :	\
+				((x < 16) ? x : 15)))
+#define TTCDKB_GPIO_EXT1(x)	(NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 :	\
+				((x < 16) ? x : 15)))
+
+/*
+ * 16 board interrupts -- MAX7312 GPIO expander
+ * 16 board interrupts -- PCA9575 GPIO expander
+ * 24 board interrupts -- 88PM860x PMIC
+ */
+#define TTCDKB_NR_IRQS		(IRQ_BOARD_START + 16 + 16 + 24)
 
 static unsigned long ttc_dkb_pin_config[] __initdata = {
 	/* UART2 */
@@ -113,6 +125,22 @@ static struct platform_device *ttc_dkb_devices[] = {
 	&ttc_dkb_device_onenand,
 };
 
+static struct pca953x_platform_data max7312_data[] = {
+	{
+		.gpio_base	= TTCDKB_GPIO_EXT0(0),
+		.irq_base	= IRQ_BOARD_START,
+	},
+};
+
+static struct i2c_board_info ttc_dkb_i2c_info[] = {
+	{
+		.type		= "max7312",
+		.addr		= 0x23,
+		.irq		= IRQ_GPIO(80),
+		.platform_data	= &max7312_data,
+	},
+};
+
 static void __init ttc_dkb_init(void)
 {
 	mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
@@ -121,6 +149,7 @@ static void __init ttc_dkb_init(void)
 	pxa910_add_uart(1);
 
 	/* off-chip devices */
+	pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
 	platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
 }
 
-- 
1.5.6.5

[PATCH 9/9] ARM: mmp: enable max7312 gpio expander in dkb

[Russell King - ARM Linux]

On Fri, Apr 01, 2011 at 10:39:28AM +0800, Haojian Zhuang wrote:
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/flash.h>
>  #include <mach/addr-map.h>
> +#include <mach/gpio.h>

linux/gpio.h

[PATCH 9/9] ARM: mmp: enable max7312 gpio expander in dkb

[Eric Miao]

On Sat, Apr 2, 2011 at 2:36 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Fri, Apr 01, 2011 at 10:39:28AM +0800, Haojian Zhuang wrote:
>> ?#include <asm/mach-types.h>
>> ?#include <asm/mach/arch.h>
>> ?#include <asm/mach/flash.h>
>> ?#include <mach/addr-map.h>
>> +#include <mach/gpio.h>
>
> linux/gpio.h
>

Applied with the above change.

[PATCH 4/9] ARM: pxa: use gpio reset

[Russell King - ARM Linux]

On Fri, Apr 01, 2011 at 10:39:23AM +0800, Haojian Zhuang wrote:
> Watchdog reset will clear RTC and some configuration registers. GPIO reset
> doesn't have this impact. So replace watchdog reset by gpio reset.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
> ---
>  arch/arm/mach-pxa/include/mach/pxa3xx-regs.h |    8 ++++++++
>  arch/arm/mach-pxa/reset.c                    |   16 ++++++++++++----
>  2 files changed, 20 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
> index e4fb466..28bc2a9 100644
> --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
> +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
> @@ -37,6 +37,14 @@
>  #define PVCR		__REG(0x40F50100)	/* Power Manager Voltage Change Control Register */
>  #define PCMD(x)		__REG(0x40F50110 + ((x) << 2))
>  
> +#define PMCR_BIE	(1 << 0)		/* Interrupt Enable for nBATT_FAULT */
> +#define PMCR_BIS	(1 << 1)		/* Interrupt Status for nBATT_FAULT */
> +#define PMCR_TIE	(1 << 10)		/* Interrupt Enable for XScale Core Frequency Change */
> +#define PMCR_TIS	(1 << 11)		/* Interrupt Status for XScale Core Frequency Change */
> +#define PMCR_VIE	(1 << 12)		/* Interrupt Enable for VCC_APPS and VCC_SRAM Voltage Change */
> +#define PMCR_VIS	(1 << 13)		/* Interrupt Status for VCC_APPS and VCC_SRAM Voltage Change */
> +#define PMCR_SWGR	(1 << 31)		/* Software GPIO Reset */
> +
>  /*
>   * Slave Power Managment Unit
>   */
> diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
> index 01e9d64..611d537 100644
> --- a/arch/arm/mach-pxa/reset.c
> +++ b/arch/arm/mach-pxa/reset.c
> @@ -12,6 +12,7 @@
>  
>  #include <mach/regs-ost.h>
>  #include <mach/reset.h>
> +#include <mach/pxa3xx-regs.h>
>  
>  unsigned int reset_status;
>  EXPORT_SYMBOL(reset_status);
> @@ -75,10 +76,17 @@ static void do_gpio_reset(void)
>  
>  static void do_hw_reset(void)
>  {
> -	/* Initialize the watchdog and let it fire */
> -	OWER = OWER_WME;
> -	OSSR = OSSR_M3;
> -	OSMR3 = OSCR + 368640;	/* ... in 100 ms */
> +	if (cpu_is_pxa3xx() || cpu_is_pxa95x()) {
> +		/* GPIO reset that is defined in silicons */
> +		PSPR = 0x5c014000;
> +		PMCR = (PMCR & (PMCR_BIE | PMCR_TIE | PMCR_VIE))
> +			| PMCR_SWGR;
> +	} else {
> +		/* Initialize the watchdog and let it fire */
> +		OWER = OWER_WME;
> +		OSSR = OSSR_M3;
> +		OSMR3 = OSCR + 368640;	/* ... in 100 ms */
> +	}
>  }

Why not separate the above into two functions - do_wd_reset() and
do_gpio_reset(), and have the selection of which is to be used in
the initialization path?

[PATCH 4/9] ARM: pxa: use gpio reset

[Igor Grinberg]

Hi Haojian,

On 04/01/11 05:39, Haojian Zhuang wrote:

> Watchdog reset will clear RTC and some configuration registers. GPIO reset
> doesn't have this impact. So replace watchdog reset by gpio reset.

It is also preserves the memory controller configuration registers
and puts the external DDR into self refresh.

> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
> ---
>  arch/arm/mach-pxa/include/mach/pxa3xx-regs.h |    8 ++++++++
>  arch/arm/mach-pxa/reset.c                    |   16 ++++++++++++----
>  2 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
> index e4fb466..28bc2a9 100644
> --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
> +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
> @@ -37,6 +37,14 @@
>  #define PVCR		__REG(0x40F50100)	/* Power Manager Voltage Change Control Register */
>  #define PCMD(x)		__REG(0x40F50110 + ((x) << 2))
>  
> +#define PMCR_BIE	(1 << 0)		/* Interrupt Enable for nBATT_FAULT */
> +#define PMCR_BIS	(1 << 1)		/* Interrupt Status for nBATT_FAULT */
> +#define PMCR_TIE	(1 << 10)		/* Interrupt Enable for XScale Core Frequency Change */
> +#define PMCR_TIS	(1 << 11)		/* Interrupt Status for XScale Core Frequency Change */
> +#define PMCR_VIE	(1 << 12)		/* Interrupt Enable for VCC_APPS and VCC_SRAM Voltage Change */
> +#define PMCR_VIS	(1 << 13)		/* Interrupt Status for VCC_APPS and VCC_SRAM Voltage Change */
> +#define PMCR_SWGR	(1 << 31)		/* Software GPIO Reset */
> +

Here, there is no real need in longer then 80 characters lines.

>  /*
>   * Slave Power Managment Unit
>   */
> diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
> index 01e9d64..611d537 100644
> --- a/arch/arm/mach-pxa/reset.c
> +++ b/arch/arm/mach-pxa/reset.c
> @@ -12,6 +12,7 @@
>  
>  #include <mach/regs-ost.h>
>  #include <mach/reset.h>
> +#include <mach/pxa3xx-regs.h>
>  
>  unsigned int reset_status;
>  EXPORT_SYMBOL(reset_status);
> @@ -75,10 +76,17 @@ static void do_gpio_reset(void)
>  
>  static void do_hw_reset(void)
>  {
> -	/* Initialize the watchdog and let it fire */
> -	OWER = OWER_WME;
> -	OSSR = OSSR_M3;
> -	OSMR3 = OSCR + 368640;	/* ... in 100 ms */
> +	if (cpu_is_pxa3xx() || cpu_is_pxa95x()) {
> +		/* GPIO reset that is defined in silicons */
> +		PSPR = 0x5c014000;
> +		PMCR = (PMCR & (PMCR_BIE | PMCR_TIE | PMCR_VIE))
> +			| PMCR_SWGR;
> +	} else {
> +		/* Initialize the watchdog and let it fire */
> +		OWER = OWER_WME;
> +		OSSR = OSSR_M3;
> +		OSMR3 = OSCR + 368640;	/* ... in 100 ms */
> +	}
>  }
>  

This affects all PXA3xx based platforms and boards...
I still haven't had a chance to test this (probably in a couple of days I will),
but given that the memory controller (and the DDR) is affected by this patch,
we'd better give it a good test as it can bring issues on existing platforms
which relay on the WD reset.


-- 
Regards,
Igor.

[PATCH 3/9] ARM: mmp: remove redundant macro definition in mfp

[Eric Miao]

On Fri, Apr 1, 2011 at 10:39 AM, Haojian Zhuang
<haojian.zhuang@marvell.com> wrote:
> There're two layers in MFP implementation. One is MFP layer that is logical
> pin setting. And the other is MFPR layer that is physical register setting.
>
> MFP drive setting is different between PXA168 and PXA910. But the difference
> was stored in logical layer, not physical layer. And some unnecessary macro
> definition were added for ARCH_MMP.

The implementation is indeed a bit complicated, yet I don't see the
change here is necessary so far.

The MFPR bit definitions for pxa168/910 and mmp2 are basically
following the pxa3xx's.

And definitions like DRIVE_SLOW, DRIVE_VERY_SLOW are really
pxa168/910, mmp2 specific. And it's no equivalent to DS01X, DS02X
..., which is more pxa3xx specific.

BTW, does the existing code cause any bug/limitation?

>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
> ---
> ?arch/arm/mach-mmp/include/mach/mfp-mmp2.h ? | ? ?7 +----
> ?arch/arm/mach-mmp/include/mach/mfp-pxa168.h | ? ?7 +----
> ?arch/arm/mach-mmp/include/mach/mfp-pxa910.h | ? ?7 +----
> ?arch/arm/mach-mmp/include/mach/mfp.h ? ? ? ?| ? 34 ---------------------------
> ?arch/arm/mach-mmp/mmp2.c ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
> ?arch/arm/mach-mmp/pxa168.c ? ? ? ? ? ? ? ? ?| ? ?2 +-
> ?arch/arm/mach-mmp/pxa910.c ? ? ? ? ? ? ? ? ?| ? ?2 +-
> ?arch/arm/plat-pxa/include/plat/mfp.h ? ? ? ?| ? ?4 +++
> ?arch/arm/plat-pxa/mfp.c ? ? ? ? ? ? ? ? ? ? | ? 22 +++++++++++++++-
> ?9 files changed, 30 insertions(+), 57 deletions(-)
> ?delete mode 100644 arch/arm/mach-mmp/include/mach/mfp.h
>
> diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
> index 4ad3862..c66eaea 100644
> --- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
> +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
> @@ -1,12 +1,7 @@
> ?#ifndef __ASM_MACH_MFP_MMP2_H
> ?#define __ASM_MACH_MFP_MMP2_H
>
> -#include <mach/mfp.h>
> -
> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
> -#define MFP_DRIVE_SLOW ? ? ? ? (0x2 << 13)
> -#define MFP_DRIVE_MEDIUM ? ? ? (0x4 << 13)
> -#define MFP_DRIVE_FAST ? ? ? ? (0x6 << 13)
> +#include <plat/mfp.h>
>
> ?/* GPIO */
> ?#define GPIO0_GPIO ? ? MFP_CFG(GPIO0, AF0)
> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
> index 4621067..4aadbea 100644
> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
> @@ -1,12 +1,7 @@
> ?#ifndef __ASM_MACH_MFP_PXA168_H
> ?#define __ASM_MACH_MFP_PXA168_H
>
> -#include <mach/mfp.h>
> -
> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
> -#define MFP_DRIVE_SLOW ? ? ? ? (0x1 << 13)
> -#define MFP_DRIVE_MEDIUM ? ? ? (0x2 << 13)
> -#define MFP_DRIVE_FAST ? ? ? ? (0x3 << 13)
> +#include <plat/mfp.h>
>
> ?/* GPIO */
> ?#define GPIO0_GPIO ? ? ? ? ? ? MFP_CFG(GPIO0, AF5)
> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
> index fbd7ee8..f5d33be 100644
> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
> @@ -1,12 +1,7 @@
> ?#ifndef __ASM_MACH_MFP_PXA910_H
> ?#define __ASM_MACH_MFP_PXA910_H
>
> -#include <mach/mfp.h>
> -
> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
> -#define MFP_DRIVE_SLOW ? ? ? ? (0x2 << 13)
> -#define MFP_DRIVE_MEDIUM ? ? ? (0x4 << 13)
> -#define MFP_DRIVE_FAST ? ? ? ? (0x6 << 13)
> +#include <plat/mfp.h>
>
> ?/* UART2 */
> ?#define GPIO47_UART2_RXD ? ? ? MFP_CFG(GPIO47, AF6)
> diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h
> deleted file mode 100644
> index 62e510e..0000000
> --- a/arch/arm/mach-mmp/include/mach/mfp.h
> +++ /dev/null
> @@ -1,34 +0,0 @@
> -#ifndef __ASM_MACH_MFP_H
> -#define __ASM_MACH_MFP_H
> -
> -#include <plat/mfp.h>
> -
> -/*
> - * NOTE: the MFPR register bit definitions on PXA168 processor lines are a
> - * bit different from those on PXA3xx. ?Bit [7:10] are now reserved, which
> - * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
> - *
> - * To cope with this difference and re-use the pxa3xx mfp code as much as
> - * possible, we make the following compromise:
> - *
> - * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
> - * 2. DRIVE strength definitions redefined to include the reserved bit
> - * ? ?- the reserved bit differs between pxa168 and pxa910, and the
> - * ? ? ?MFP_DRIVE_* macros are individually defined in mfp-pxa{168,910}.h
> - * 3. Override MFP_CFG() and MFP_CFG_DRV()
> - * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
> - */
> -
> -#undef MFP_CFG
> -#undef MFP_CFG_DRV
> -#undef MFP_CFG_LPM
> -#undef MFP_CFG_X
> -#undef MFP_CFG_DEFAULT
> -
> -#define MFP_CFG(pin, af) ? ? ? ? ? ? ? \
> - ? ? ? (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
> -
> -#define MFP_CFG_DRV(pin, af, drv) ? ? ?\
> - ? ? ? (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
> -
> -#endif /* __ASM_MACH_MFP_H */
> diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
> index 8e6c3ac..14e6a23 100644
> --- a/arch/arm/mach-mmp/mmp2.c
> +++ b/arch/arm/mach-mmp/mmp2.c
> @@ -24,10 +24,10 @@
> ?#include <mach/cputype.h>
> ?#include <mach/irqs.h>
> ?#include <mach/dma.h>
> -#include <mach/mfp.h>
> ?#include <mach/gpio.h>
> ?#include <mach/devices.h>
> ?#include <mach/mmp2.h>
> +#include <plat/mfp.h>
>
> ?#include "common.h"
> ?#include "clock.h"
> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
> index 72b4e76..34df2b1 100644
> --- a/arch/arm/mach-mmp/pxa168.c
> +++ b/arch/arm/mach-mmp/pxa168.c
> @@ -24,7 +24,7 @@
> ?#include <mach/gpio.h>
> ?#include <mach/dma.h>
> ?#include <mach/devices.h>
> -#include <mach/mfp.h>
> +#include <plat/mfp.h>
>
> ?#include "common.h"
> ?#include "clock.h"
> diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
> index 8f92ccd..93b3b25 100644
> --- a/arch/arm/mach-mmp/pxa910.c
> +++ b/arch/arm/mach-mmp/pxa910.c
> @@ -22,8 +22,8 @@
> ?#include <mach/irqs.h>
> ?#include <mach/gpio.h>
> ?#include <mach/dma.h>
> -#include <mach/mfp.h>
> ?#include <mach/devices.h>
> +#include <plat/mfp.h>
>
> ?#include "common.h"
> ?#include "clock.h"
> diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
> index 75f6564..b7dde0c 100644
> --- a/arch/arm/plat-pxa/include/plat/mfp.h
> +++ b/arch/arm/plat-pxa/include/plat/mfp.h
> @@ -378,6 +378,10 @@ typedef unsigned long mfp_cfg_t;
> ?#define MFP_DS13X ? ? ? ? ? ? ?(0x7 << 13)
> ?#define MFP_DS_MASK ? ? ? ? ? ?(0x7 << 13)
> ?#define MFP_DS(x) ? ? ? ? ? ? ?(((x) >> 13) & 0x7)
> +#define MFP_VERY_SLOW ? ? ? ? ?MFP_DS01X
> +#define MFP_SLOW ? ? ? ? ? ? ? MFP_DS02X
> +#define MFP_MEDIUM ? ? ? ? ? ? MFP_DS03X
> +#define MFP_FAST ? ? ? ? ? ? ? MFP_DS04X
>
> ?#define MFP_LPM_DEFAULT ? ? ? ? ? ? ? ?(0x0 << 16)
> ?#define MFP_LPM_DRIVE_LOW ? ? ?(0x1 << 16)
> diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c
> index a9aa5ad..d335551 100644
> --- a/arch/arm/plat-pxa/mfp.c
> +++ b/arch/arm/plat-pxa/mfp.c
> @@ -19,6 +19,10 @@
> ?#include <linux/io.h>
> ?#include <linux/sysdev.h>
>
> +#ifdef CONFIG_ARCH_MMP
> +#include <mach/cputype.h>
> +#endif
> +
> ?#include <plat/mfp.h>
>
> ?#define MFPR_SIZE ? ? ?(PAGE_SIZE)
> @@ -165,8 +169,14 @@ static inline void __mfp_config_lpm(struct mfp_pin *p)
> ?void mfp_config(unsigned long *mfp_cfgs, int num)
> ?{
> ? ? ? ?unsigned long flags;
> - ? ? ? int i;
> -
> + ? ? ? int i, drv_b11 = 0, no_lpm = 0;
> +
> +#ifdef CONFIG_ARCH_MMP
> + ? ? ? if (cpu_is_pxa910() || cpu_is_mmp2())
> + ? ? ? ? ? ? ? drv_b11 = 1;
> + ? ? ? if (cpu_is_pxa168() || cpu_is_pxa910())
> + ? ? ? ? ? ? ? no_lpm = 1;
> +#endif
> ? ? ? ?spin_lock_irqsave(&mfp_spin_lock, flags);
>
> ? ? ? ?for (i = 0; i < num; i++, mfp_cfgs++) {
> @@ -183,6 +193,10 @@ void mfp_config(unsigned long *mfp_cfgs, int num)
> ? ? ? ? ? ? ? ?lpm = MFP_LPM_STATE(c);
> ? ? ? ? ? ? ? ?edge = MFP_LPM_EDGE(c);
> ? ? ? ? ? ? ? ?pull = MFP_PULL(c);
> + ? ? ? ? ? ? ? if (drv_b11)
> + ? ? ? ? ? ? ? ? ? ? ? drv = drv << 1;
> + ? ? ? ? ? ? ? if (no_lpm)
> + ? ? ? ? ? ? ? ? ? ? ? lpm = 0;
>
> ? ? ? ? ? ? ? ?/* run-mode pull settings will conflict with MFPR bits of
> ? ? ? ? ? ? ? ? * low power mode state, ?calculate mfpr_run and mfpr_lpm
> @@ -272,6 +286,10 @@ void mfp_config_lpm(void)
> ? ? ? ?struct mfp_pin *p = &mfp_table[0];
> ? ? ? ?int pin;
>
> +#ifdef CONFIG_ARCH_MMP
> + ? ? ? if (cpu_is_pxa168() || cpu_is_pxa910())
> + ? ? ? ? ? ? ? return;
> +#endif
> ? ? ? ?for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
> ? ? ? ? ? ? ? ?__mfp_config_lpm(p);
> ?}
> --
> 1.5.6.5
>
>

[PATCH 3/9] ARM: mmp: remove redundant macro definition in mfp

[Haojian Zhuang]

>-----Original Message-----
>From: Eric Miao [mailto:eric.y.miao at gmail.com]
>Sent: 2011?4?1? 12:51 PM
>To: Haojian Zhuang
>Cc: linux at arm.linux.org.uk; linux-arm-kernel at lists.infradead.org
>Subject: Re: [PATCH 3/9] ARM: mmp: remove redundant macro definition in
>mfp
>
>On Fri, Apr 1, 2011 at 10:39 AM, Haojian Zhuang
><haojian.zhuang@marvell.com> wrote:
>> There're two layers in MFP implementation. One is MFP layer that is
>logical
>> pin setting. And the other is MFPR layer that is physical register
>setting.
>>
>> MFP drive setting is different between PXA168 and PXA910. But the
>difference
>> was stored in logical layer, not physical layer. And some unnecessary
>macro
>> definition were added for ARCH_MMP.
>
>The implementation is indeed a bit complicated, yet I don't see the
>change here is necessary so far.
>
>The MFPR bit definitions for pxa168/910 and mmp2 are basically
>following the pxa3xx's.
>
>And definitions like DRIVE_SLOW, DRIVE_VERY_SLOW are really
>pxa168/910, mmp2 specific. And it's no equivalent to DS01X, DS02X
>..., which is more pxa3xx specific.
>
>BTW, does the existing code cause any bug/limitation?
>
Yes, there's some limitation in existing code since it's for pxa3xx. For example, driver strength is bit[12..10] in PXA3xx. In PXA955/910/MMP2, it's bit[12..11]. In PXA168, it's bit[11..10]. And there's no sleep mode in PXA168. Sleep mode bit is different in PXA910.

>>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
>> ---
>> ?arch/arm/mach-mmp/include/mach/mfp-mmp2.h ? | ? ?7 +----
>> ?arch/arm/mach-mmp/include/mach/mfp-pxa168.h | ? ?7 +----
>> ?arch/arm/mach-mmp/include/mach/mfp-pxa910.h | ? ?7 +----
>> ?arch/arm/mach-mmp/include/mach/mfp.h ? ? ? ?| ? 34 ------------------
>---------
>> ?arch/arm/mach-mmp/mmp2.c ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
>> ?arch/arm/mach-mmp/pxa168.c ? ? ? ? ? ? ? ? ?| ? ?2 +-
>> ?arch/arm/mach-mmp/pxa910.c ? ? ? ? ? ? ? ? ?| ? ?2 +-
>> ?arch/arm/plat-pxa/include/plat/mfp.h ? ? ? ?| ? ?4 +++
>> ?arch/arm/plat-pxa/mfp.c ? ? ? ? ? ? ? ? ? ? | ? 22 +++++++++++++++-
>> ?9 files changed, 30 insertions(+), 57 deletions(-)
>> ?delete mode 100644 arch/arm/mach-mmp/include/mach/mfp.h
>>
>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>> index 4ad3862..c66eaea 100644
>> --- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>> +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>> @@ -1,12 +1,7 @@
>> ?#ifndef __ASM_MACH_MFP_MMP2_H
>> ?#define __ASM_MACH_MFP_MMP2_H
>>
>> -#include <mach/mfp.h>
>> -
>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x2 << 13)
>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x4 << 13)
>> -#define MFP_DRIVE_FAST ? ? ? ? (0x6 << 13)
>> +#include <plat/mfp.h>
>>
>> ?/* GPIO */
>> ?#define GPIO0_GPIO ? ? MFP_CFG(GPIO0, AF0)
>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>> index 4621067..4aadbea 100644
>> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>> @@ -1,12 +1,7 @@
>> ?#ifndef __ASM_MACH_MFP_PXA168_H
>> ?#define __ASM_MACH_MFP_PXA168_H
>>
>> -#include <mach/mfp.h>
>> -
>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x1 << 13)
>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x2 << 13)
>> -#define MFP_DRIVE_FAST ? ? ? ? (0x3 << 13)
>> +#include <plat/mfp.h>
>>
>> ?/* GPIO */
>> ?#define GPIO0_GPIO ? ? ? ? ? ? MFP_CFG(GPIO0, AF5)
>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>> index fbd7ee8..f5d33be 100644
>> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>> @@ -1,12 +1,7 @@
>> ?#ifndef __ASM_MACH_MFP_PXA910_H
>> ?#define __ASM_MACH_MFP_PXA910_H
>>
>> -#include <mach/mfp.h>
>> -
>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x2 << 13)
>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x4 << 13)
>> -#define MFP_DRIVE_FAST ? ? ? ? (0x6 << 13)
>> +#include <plat/mfp.h>
>>
>> ?/* UART2 */
>> ?#define GPIO47_UART2_RXD ? ? ? MFP_CFG(GPIO47, AF6)
>> diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-
>mmp/include/mach/mfp.h
>> deleted file mode 100644
>> index 62e510e..0000000
>> --- a/arch/arm/mach-mmp/include/mach/mfp.h
>> +++ /dev/null
>> @@ -1,34 +0,0 @@
>> -#ifndef __ASM_MACH_MFP_H
>> -#define __ASM_MACH_MFP_H
>> -
>> -#include <plat/mfp.h>
>> -
>> -/*
>> - * NOTE: the MFPR register bit definitions on PXA168 processor lines
>are a
>> - * bit different from those on PXA3xx. ?Bit [7:10] are now reserved,
>which
>> - * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
>> - *
>> - * To cope with this difference and re-use the pxa3xx mfp code as
>much as
>> - * possible, we make the following compromise:
>> - *
>> - * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
>> - * 2. DRIVE strength definitions redefined to include the reserved
>bit
>> - * ? ?- the reserved bit differs between pxa168 and pxa910, and the
>> - * ? ? ?MFP_DRIVE_* macros are individually defined in mfp-
>pxa{168,910}.h
>> - * 3. Override MFP_CFG() and MFP_CFG_DRV()
>> - * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
>> - */
>> -
>> -#undef MFP_CFG
>> -#undef MFP_CFG_DRV
>> -#undef MFP_CFG_LPM
>> -#undef MFP_CFG_X
>> -#undef MFP_CFG_DEFAULT
>> -
>> -#define MFP_CFG(pin, af) ? ? ? ? ? ? ? \
>> - ? ? ? (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af |
>MFP_DRIVE_MEDIUM)
>> -
>> -#define MFP_CFG_DRV(pin, af, drv) ? ? ?\
>> - ? ? ? (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af |
>MFP_DRIVE_##drv)
>> -
>> -#endif /* __ASM_MACH_MFP_H */
>> diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
>> index 8e6c3ac..14e6a23 100644
>> --- a/arch/arm/mach-mmp/mmp2.c
>> +++ b/arch/arm/mach-mmp/mmp2.c
>> @@ -24,10 +24,10 @@
>> ?#include <mach/cputype.h>
>> ?#include <mach/irqs.h>
>> ?#include <mach/dma.h>
>> -#include <mach/mfp.h>
>> ?#include <mach/gpio.h>
>> ?#include <mach/devices.h>
>> ?#include <mach/mmp2.h>
>> +#include <plat/mfp.h>
>>
>> ?#include "common.h"
>> ?#include "clock.h"
>> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
>> index 72b4e76..34df2b1 100644
>> --- a/arch/arm/mach-mmp/pxa168.c
>> +++ b/arch/arm/mach-mmp/pxa168.c
>> @@ -24,7 +24,7 @@
>> ?#include <mach/gpio.h>
>> ?#include <mach/dma.h>
>> ?#include <mach/devices.h>
>> -#include <mach/mfp.h>
>> +#include <plat/mfp.h>
>>
>> ?#include "common.h"
>> ?#include "clock.h"
>> diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
>> index 8f92ccd..93b3b25 100644
>> --- a/arch/arm/mach-mmp/pxa910.c
>> +++ b/arch/arm/mach-mmp/pxa910.c
>> @@ -22,8 +22,8 @@
>> ?#include <mach/irqs.h>
>> ?#include <mach/gpio.h>
>> ?#include <mach/dma.h>
>> -#include <mach/mfp.h>
>> ?#include <mach/devices.h>
>> +#include <plat/mfp.h>
>>
>> ?#include "common.h"
>> ?#include "clock.h"
>> diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-
>pxa/include/plat/mfp.h
>> index 75f6564..b7dde0c 100644
>> --- a/arch/arm/plat-pxa/include/plat/mfp.h
>> +++ b/arch/arm/plat-pxa/include/plat/mfp.h
>> @@ -378,6 +378,10 @@ typedef unsigned long mfp_cfg_t;
>> ?#define MFP_DS13X ? ? ? ? ? ? ?(0x7 << 13)
>> ?#define MFP_DS_MASK ? ? ? ? ? ?(0x7 << 13)
>> ?#define MFP_DS(x) ? ? ? ? ? ? ?(((x) >> 13) & 0x7)
>> +#define MFP_VERY_SLOW ? ? ? ? ?MFP_DS01X
>> +#define MFP_SLOW ? ? ? ? ? ? ? MFP_DS02X
>> +#define MFP_MEDIUM ? ? ? ? ? ? MFP_DS03X
>> +#define MFP_FAST ? ? ? ? ? ? ? MFP_DS04X
>>
>> ?#define MFP_LPM_DEFAULT ? ? ? ? ? ? ? ?(0x0 << 16)
>> ?#define MFP_LPM_DRIVE_LOW ? ? ?(0x1 << 16)
>> diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c
>> index a9aa5ad..d335551 100644
>> --- a/arch/arm/plat-pxa/mfp.c
>> +++ b/arch/arm/plat-pxa/mfp.c
>> @@ -19,6 +19,10 @@
>> ?#include <linux/io.h>
>> ?#include <linux/sysdev.h>
>>
>> +#ifdef CONFIG_ARCH_MMP
>> +#include <mach/cputype.h>
>> +#endif
>> +
>> ?#include <plat/mfp.h>
>>
>> ?#define MFPR_SIZE ? ? ?(PAGE_SIZE)
>> @@ -165,8 +169,14 @@ static inline void __mfp_config_lpm(struct
>mfp_pin *p)
>> ?void mfp_config(unsigned long *mfp_cfgs, int num)
>> ?{
>> ? ? ? ?unsigned long flags;
>> - ? ? ? int i;
>> -
>> + ? ? ? int i, drv_b11 = 0, no_lpm = 0;
>> +
>> +#ifdef CONFIG_ARCH_MMP
>> + ? ? ? if (cpu_is_pxa910() || cpu_is_mmp2())
>> + ? ? ? ? ? ? ? drv_b11 = 1;
>> + ? ? ? if (cpu_is_pxa168() || cpu_is_pxa910())
>> + ? ? ? ? ? ? ? no_lpm = 1;
>> +#endif
>> ? ? ? ?spin_lock_irqsave(&mfp_spin_lock, flags);
>>
>> ? ? ? ?for (i = 0; i < num; i++, mfp_cfgs++) {
>> @@ -183,6 +193,10 @@ void mfp_config(unsigned long *mfp_cfgs, int num)
>> ? ? ? ? ? ? ? ?lpm = MFP_LPM_STATE(c);
>> ? ? ? ? ? ? ? ?edge = MFP_LPM_EDGE(c);
>> ? ? ? ? ? ? ? ?pull = MFP_PULL(c);
>> + ? ? ? ? ? ? ? if (drv_b11)
>> + ? ? ? ? ? ? ? ? ? ? ? drv = drv << 1;
>> + ? ? ? ? ? ? ? if (no_lpm)
>> + ? ? ? ? ? ? ? ? ? ? ? lpm = 0;
>>
>> ? ? ? ? ? ? ? ?/* run-mode pull settings will conflict with MFPR bits
>of
>> ? ? ? ? ? ? ? ? * low power mode state, ?calculate mfpr_run and
>mfpr_lpm
>> @@ -272,6 +286,10 @@ void mfp_config_lpm(void)
>> ? ? ? ?struct mfp_pin *p = &mfp_table[0];
>> ? ? ? ?int pin;
>>
>> +#ifdef CONFIG_ARCH_MMP
>> + ? ? ? if (cpu_is_pxa168() || cpu_is_pxa910())
>> + ? ? ? ? ? ? ? return;
>> +#endif
>> ? ? ? ?for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
>> ? ? ? ? ? ? ? ?__mfp_config_lpm(p);
>> ?}
>> --
>> 1.5.6.5
>>
>>

[PATCH 3/9] ARM: mmp: remove redundant macro definition in mfp

[Eric Miao]

On Fri, Apr 1, 2011 at 1:09 PM, Haojian Zhuang <hzhuang1@marvell.com> wrote:
>
>
>>-----Original Message-----
>>From: Eric Miao [mailto:eric.y.miao at gmail.com]
>>Sent: 2011?4?1? 12:51 PM
>>To: Haojian Zhuang
>>Cc: linux at arm.linux.org.uk; linux-arm-kernel at lists.infradead.org
>>Subject: Re: [PATCH 3/9] ARM: mmp: remove redundant macro definition in
>>mfp
>>
>>On Fri, Apr 1, 2011 at 10:39 AM, Haojian Zhuang
>><haojian.zhuang@marvell.com> wrote:
>>> There're two layers in MFP implementation. One is MFP layer that is
>>logical
>>> pin setting. And the other is MFPR layer that is physical register
>>setting.
>>>
>>> MFP drive setting is different between PXA168 and PXA910. But the
>>difference
>>> was stored in logical layer, not physical layer. And some unnecessary
>>macro
>>> definition were added for ARCH_MMP.
>>
>>The implementation is indeed a bit complicated, yet I don't see the
>>change here is necessary so far.
>>
>>The MFPR bit definitions for pxa168/910 and mmp2 are basically
>>following the pxa3xx's.
>>
>>And definitions like DRIVE_SLOW, DRIVE_VERY_SLOW are really
>>pxa168/910, mmp2 specific. And it's no equivalent to DS01X, DS02X
>>..., which is more pxa3xx specific.
>>
>>BTW, does the existing code cause any bug/limitation?
>>
> Yes, there's some limitation in existing code since it's for pxa3xx. For example, driver strength is bit[12..10] in PXA3xx. In PXA955/910/MMP2, it's bit[12..11]. In PXA168, it's bit[11..10].

This can be covered by definitions of DRIVE_SLOW, DRIVE_FAST, and
it's transparent to the API usage.

> And there's no sleep mode in PXA168.

Thus there will be no MFP_LPM_* usage in pxa168 board file.

> Sleep mode bit is different in PXA910.

Example, like?

>
>>>
>>> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
>>> ---
>>> ?arch/arm/mach-mmp/include/mach/mfp-mmp2.h ? | ? ?7 +----
>>> ?arch/arm/mach-mmp/include/mach/mfp-pxa168.h | ? ?7 +----
>>> ?arch/arm/mach-mmp/include/mach/mfp-pxa910.h | ? ?7 +----
>>> ?arch/arm/mach-mmp/include/mach/mfp.h ? ? ? ?| ? 34 ------------------
>>---------
>>> ?arch/arm/mach-mmp/mmp2.c ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
>>> ?arch/arm/mach-mmp/pxa168.c ? ? ? ? ? ? ? ? ?| ? ?2 +-
>>> ?arch/arm/mach-mmp/pxa910.c ? ? ? ? ? ? ? ? ?| ? ?2 +-
>>> ?arch/arm/plat-pxa/include/plat/mfp.h ? ? ? ?| ? ?4 +++
>>> ?arch/arm/plat-pxa/mfp.c ? ? ? ? ? ? ? ? ? ? | ? 22 +++++++++++++++-
>>> ?9 files changed, 30 insertions(+), 57 deletions(-)
>>> ?delete mode 100644 arch/arm/mach-mmp/include/mach/mfp.h
>>>
>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>> index 4ad3862..c66eaea 100644
>>> --- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>> +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>> @@ -1,12 +1,7 @@
>>> ?#ifndef __ASM_MACH_MFP_MMP2_H
>>> ?#define __ASM_MACH_MFP_MMP2_H
>>>
>>> -#include <mach/mfp.h>
>>> -
>>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x2 << 13)
>>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x4 << 13)
>>> -#define MFP_DRIVE_FAST ? ? ? ? (0x6 << 13)
>>> +#include <plat/mfp.h>
>>>
>>> ?/* GPIO */
>>> ?#define GPIO0_GPIO ? ? MFP_CFG(GPIO0, AF0)
>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>> index 4621067..4aadbea 100644
>>> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>> @@ -1,12 +1,7 @@
>>> ?#ifndef __ASM_MACH_MFP_PXA168_H
>>> ?#define __ASM_MACH_MFP_PXA168_H
>>>
>>> -#include <mach/mfp.h>
>>> -
>>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x1 << 13)
>>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x2 << 13)
>>> -#define MFP_DRIVE_FAST ? ? ? ? (0x3 << 13)
>>> +#include <plat/mfp.h>
>>>
>>> ?/* GPIO */
>>> ?#define GPIO0_GPIO ? ? ? ? ? ? MFP_CFG(GPIO0, AF5)
>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>> index fbd7ee8..f5d33be 100644
>>> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>> @@ -1,12 +1,7 @@
>>> ?#ifndef __ASM_MACH_MFP_PXA910_H
>>> ?#define __ASM_MACH_MFP_PXA910_H
>>>
>>> -#include <mach/mfp.h>
>>> -
>>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x2 << 13)
>>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x4 << 13)
>>> -#define MFP_DRIVE_FAST ? ? ? ? (0x6 << 13)
>>> +#include <plat/mfp.h>
>>>
>>> ?/* UART2 */
>>> ?#define GPIO47_UART2_RXD ? ? ? MFP_CFG(GPIO47, AF6)
>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-
>>mmp/include/mach/mfp.h
>>> deleted file mode 100644
>>> index 62e510e..0000000
>>> --- a/arch/arm/mach-mmp/include/mach/mfp.h
>>> +++ /dev/null
>>> @@ -1,34 +0,0 @@
>>> -#ifndef __ASM_MACH_MFP_H
>>> -#define __ASM_MACH_MFP_H
>>> -
>>> -#include <plat/mfp.h>
>>> -
>>> -/*
>>> - * NOTE: the MFPR register bit definitions on PXA168 processor lines
>>are a
>>> - * bit different from those on PXA3xx. ?Bit [7:10] are now reserved,
>>which
>>> - * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
>>> - *
>>> - * To cope with this difference and re-use the pxa3xx mfp code as
>>much as
>>> - * possible, we make the following compromise:
>>> - *
>>> - * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
>>> - * 2. DRIVE strength definitions redefined to include the reserved
>>bit
>>> - * ? ?- the reserved bit differs between pxa168 and pxa910, and the
>>> - * ? ? ?MFP_DRIVE_* macros are individually defined in mfp-
>>pxa{168,910}.h
>>> - * 3. Override MFP_CFG() and MFP_CFG_DRV()
>>> - * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
>>> - */
>>> -
>>> -#undef MFP_CFG
>>> -#undef MFP_CFG_DRV
>>> -#undef MFP_CFG_LPM
>>> -#undef MFP_CFG_X
>>> -#undef MFP_CFG_DEFAULT
>>> -
>>> -#define MFP_CFG(pin, af) ? ? ? ? ? ? ? \
>>> - ? ? ? (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af |
>>MFP_DRIVE_MEDIUM)
>>> -
>>> -#define MFP_CFG_DRV(pin, af, drv) ? ? ?\
>>> - ? ? ? (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af |
>>MFP_DRIVE_##drv)
>>> -
>>> -#endif /* __ASM_MACH_MFP_H */
>>> diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
>>> index 8e6c3ac..14e6a23 100644
>>> --- a/arch/arm/mach-mmp/mmp2.c
>>> +++ b/arch/arm/mach-mmp/mmp2.c
>>> @@ -24,10 +24,10 @@
>>> ?#include <mach/cputype.h>
>>> ?#include <mach/irqs.h>
>>> ?#include <mach/dma.h>
>>> -#include <mach/mfp.h>
>>> ?#include <mach/gpio.h>
>>> ?#include <mach/devices.h>
>>> ?#include <mach/mmp2.h>
>>> +#include <plat/mfp.h>
>>>
>>> ?#include "common.h"
>>> ?#include "clock.h"
>>> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
>>> index 72b4e76..34df2b1 100644
>>> --- a/arch/arm/mach-mmp/pxa168.c
>>> +++ b/arch/arm/mach-mmp/pxa168.c
>>> @@ -24,7 +24,7 @@
>>> ?#include <mach/gpio.h>
>>> ?#include <mach/dma.h>
>>> ?#include <mach/devices.h>
>>> -#include <mach/mfp.h>
>>> +#include <plat/mfp.h>
>>>
>>> ?#include "common.h"
>>> ?#include "clock.h"
>>> diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
>>> index 8f92ccd..93b3b25 100644
>>> --- a/arch/arm/mach-mmp/pxa910.c
>>> +++ b/arch/arm/mach-mmp/pxa910.c
>>> @@ -22,8 +22,8 @@
>>> ?#include <mach/irqs.h>
>>> ?#include <mach/gpio.h>
>>> ?#include <mach/dma.h>
>>> -#include <mach/mfp.h>
>>> ?#include <mach/devices.h>
>>> +#include <plat/mfp.h>
>>>
>>> ?#include "common.h"
>>> ?#include "clock.h"
>>> diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-
>>pxa/include/plat/mfp.h
>>> index 75f6564..b7dde0c 100644
>>> --- a/arch/arm/plat-pxa/include/plat/mfp.h
>>> +++ b/arch/arm/plat-pxa/include/plat/mfp.h
>>> @@ -378,6 +378,10 @@ typedef unsigned long mfp_cfg_t;
>>> ?#define MFP_DS13X ? ? ? ? ? ? ?(0x7 << 13)
>>> ?#define MFP_DS_MASK ? ? ? ? ? ?(0x7 << 13)
>>> ?#define MFP_DS(x) ? ? ? ? ? ? ?(((x) >> 13) & 0x7)
>>> +#define MFP_VERY_SLOW ? ? ? ? ?MFP_DS01X
>>> +#define MFP_SLOW ? ? ? ? ? ? ? MFP_DS02X
>>> +#define MFP_MEDIUM ? ? ? ? ? ? MFP_DS03X
>>> +#define MFP_FAST ? ? ? ? ? ? ? MFP_DS04X
>>>
>>> ?#define MFP_LPM_DEFAULT ? ? ? ? ? ? ? ?(0x0 << 16)
>>> ?#define MFP_LPM_DRIVE_LOW ? ? ?(0x1 << 16)
>>> diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c
>>> index a9aa5ad..d335551 100644
>>> --- a/arch/arm/plat-pxa/mfp.c
>>> +++ b/arch/arm/plat-pxa/mfp.c
>>> @@ -19,6 +19,10 @@
>>> ?#include <linux/io.h>
>>> ?#include <linux/sysdev.h>
>>>
>>> +#ifdef CONFIG_ARCH_MMP
>>> +#include <mach/cputype.h>
>>> +#endif
>>> +
>>> ?#include <plat/mfp.h>
>>>
>>> ?#define MFPR_SIZE ? ? ?(PAGE_SIZE)
>>> @@ -165,8 +169,14 @@ static inline void __mfp_config_lpm(struct
>>mfp_pin *p)
>>> ?void mfp_config(unsigned long *mfp_cfgs, int num)
>>> ?{
>>> ? ? ? ?unsigned long flags;
>>> - ? ? ? int i;
>>> -
>>> + ? ? ? int i, drv_b11 = 0, no_lpm = 0;
>>> +
>>> +#ifdef CONFIG_ARCH_MMP
>>> + ? ? ? if (cpu_is_pxa910() || cpu_is_mmp2())
>>> + ? ? ? ? ? ? ? drv_b11 = 1;
>>> + ? ? ? if (cpu_is_pxa168() || cpu_is_pxa910())
>>> + ? ? ? ? ? ? ? no_lpm = 1;
>>> +#endif
>>> ? ? ? ?spin_lock_irqsave(&mfp_spin_lock, flags);
>>>
>>> ? ? ? ?for (i = 0; i < num; i++, mfp_cfgs++) {
>>> @@ -183,6 +193,10 @@ void mfp_config(unsigned long *mfp_cfgs, int num)
>>> ? ? ? ? ? ? ? ?lpm = MFP_LPM_STATE(c);
>>> ? ? ? ? ? ? ? ?edge = MFP_LPM_EDGE(c);
>>> ? ? ? ? ? ? ? ?pull = MFP_PULL(c);
>>> + ? ? ? ? ? ? ? if (drv_b11)
>>> + ? ? ? ? ? ? ? ? ? ? ? drv = drv << 1;
>>> + ? ? ? ? ? ? ? if (no_lpm)
>>> + ? ? ? ? ? ? ? ? ? ? ? lpm = 0;
>>>
>>> ? ? ? ? ? ? ? ?/* run-mode pull settings will conflict with MFPR bits
>>of
>>> ? ? ? ? ? ? ? ? * low power mode state, ?calculate mfpr_run and
>>mfpr_lpm
>>> @@ -272,6 +286,10 @@ void mfp_config_lpm(void)
>>> ? ? ? ?struct mfp_pin *p = &mfp_table[0];
>>> ? ? ? ?int pin;
>>>
>>> +#ifdef CONFIG_ARCH_MMP
>>> + ? ? ? if (cpu_is_pxa168() || cpu_is_pxa910())
>>> + ? ? ? ? ? ? ? return;
>>> +#endif
>>> ? ? ? ?for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
>>> ? ? ? ? ? ? ? ?__mfp_config_lpm(p);
>>> ?}
>>> --
>>> 1.5.6.5
>>>
>>>
>

[PATCH 3/9] ARM: mmp: remove redundant macro definition in mfp

[Haojian Zhuang]

>-----Original Message-----
>From: Eric Miao [mailto:eric.y.miao at gmail.com]
>Sent: 2011?4?1? 1:31 PM
>To: Haojian Zhuang
>Cc: linux at arm.linux.org.uk; linux-arm-kernel at lists.infradead.org
>Subject: Re: [PATCH 3/9] ARM: mmp: remove redundant macro definition in
>mfp
>
>On Fri, Apr 1, 2011 at 1:09 PM, Haojian Zhuang <hzhuang1@marvell.com>
>wrote:
>>
>>
>>>-----Original Message-----
>>>From: Eric Miao [mailto:eric.y.miao at gmail.com]
>>>Sent: 2011?4?1? 12:51 PM
>>>To: Haojian Zhuang
>>>Cc: linux at arm.linux.org.uk; linux-arm-kernel at lists.infradead.org
>>>Subject: Re: [PATCH 3/9] ARM: mmp: remove redundant macro definition
>in
>>>mfp
>>>
>>>On Fri, Apr 1, 2011 at 10:39 AM, Haojian Zhuang
>>><haojian.zhuang@marvell.com> wrote:
>>>> There're two layers in MFP implementation. One is MFP layer that is
>>>logical
>>>> pin setting. And the other is MFPR layer that is physical register
>>>setting.
>>>>
>>>> MFP drive setting is different between PXA168 and PXA910. But the
>>>difference
>>>> was stored in logical layer, not physical layer. And some
>unnecessary
>>>macro
>>>> definition were added for ARCH_MMP.
>>>
>>>The implementation is indeed a bit complicated, yet I don't see the
>>>change here is necessary so far.
>>>
>>>The MFPR bit definitions for pxa168/910 and mmp2 are basically
>>>following the pxa3xx's.
>>>
>>>And definitions like DRIVE_SLOW, DRIVE_VERY_SLOW are really
>>>pxa168/910, mmp2 specific. And it's no equivalent to DS01X, DS02X
>>>..., which is more pxa3xx specific.
>>>
>>>BTW, does the existing code cause any bug/limitation?
>>>
>> Yes, there's some limitation in existing code since it's for pxa3xx.
>For example, driver strength is bit[12..10] in PXA3xx. In
>PXA955/910/MMP2, it's bit[12..11]. In PXA168, it's bit[11..10].
>
>This can be covered by definitions of DRIVE_SLOW, DRIVE_FAST, and
>it's transparent to the API usage.
>
But driver strength are different in logical layer for different SoCs. Actually it's hard reading and caused some error before.
As my understanding, difference can only exists in physical layer. Logical layer should keep consistent.

>> And there's no sleep mode in PXA168.
>
>Thus there will be no MFP_LPM_* usage in pxa168 board file.
>
It was touched in mfpr_lpm. Since LPM_INPUT is used by default. Those bits should not be touched if no requirement. I can use MFPR_FLOAT by default, so no_lpm can be avoided.

>> Sleep mode bit is different in PXA910.
>
>Example, like?
>
Bit 7 should be always on in PXA910.
>>
>>>>
>>>> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
>>>> ---
>>>> ?arch/arm/mach-mmp/include/mach/mfp-mmp2.h ? | ? ?7 +----
>>>> ?arch/arm/mach-mmp/include/mach/mfp-pxa168.h | ? ?7 +----
>>>> ?arch/arm/mach-mmp/include/mach/mfp-pxa910.h | ? ?7 +----
>>>> ?arch/arm/mach-mmp/include/mach/mfp.h ? ? ? ?| ? 34 ----------------
>--
>>>---------
>>>> ?arch/arm/mach-mmp/mmp2.c ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
>>>> ?arch/arm/mach-mmp/pxa168.c ? ? ? ? ? ? ? ? ?| ? ?2 +-
>>>> ?arch/arm/mach-mmp/pxa910.c ? ? ? ? ? ? ? ? ?| ? ?2 +-
>>>> ?arch/arm/plat-pxa/include/plat/mfp.h ? ? ? ?| ? ?4 +++
>>>> ?arch/arm/plat-pxa/mfp.c ? ? ? ? ? ? ? ? ? ? | ? 22 +++++++++++++++-
>>>> ?9 files changed, 30 insertions(+), 57 deletions(-)
>>>> ?delete mode 100644 arch/arm/mach-mmp/include/mach/mfp.h
>>>>
>>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>>b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>>> index 4ad3862..c66eaea 100644
>>>> --- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>>> +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>>> @@ -1,12 +1,7 @@
>>>> ?#ifndef __ASM_MACH_MFP_MMP2_H
>>>> ?#define __ASM_MACH_MFP_MMP2_H
>>>>
>>>> -#include <mach/mfp.h>
>>>> -
>>>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>>>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x2 << 13)
>>>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x4 << 13)
>>>> -#define MFP_DRIVE_FAST ? ? ? ? (0x6 << 13)
>>>> +#include <plat/mfp.h>
>>>>
>>>> ?/* GPIO */
>>>> ?#define GPIO0_GPIO ? ? MFP_CFG(GPIO0, AF0)
>>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>>b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>>> index 4621067..4aadbea 100644
>>>> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>>> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>>> @@ -1,12 +1,7 @@
>>>> ?#ifndef __ASM_MACH_MFP_PXA168_H
>>>> ?#define __ASM_MACH_MFP_PXA168_H
>>>>
>>>> -#include <mach/mfp.h>
>>>> -
>>>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>>>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x1 << 13)
>>>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x2 << 13)
>>>> -#define MFP_DRIVE_FAST ? ? ? ? (0x3 << 13)
>>>> +#include <plat/mfp.h>
>>>>
>>>> ?/* GPIO */
>>>> ?#define GPIO0_GPIO ? ? ? ? ? ? MFP_CFG(GPIO0, AF5)
>>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>>b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>>> index fbd7ee8..f5d33be 100644
>>>> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>>> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>>> @@ -1,12 +1,7 @@
>>>> ?#ifndef __ASM_MACH_MFP_PXA910_H
>>>> ?#define __ASM_MACH_MFP_PXA910_H
>>>>
>>>> -#include <mach/mfp.h>
>>>> -
>>>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>>>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x2 << 13)
>>>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x4 << 13)
>>>> -#define MFP_DRIVE_FAST ? ? ? ? (0x6 << 13)
>>>> +#include <plat/mfp.h>
>>>>
>>>> ?/* UART2 */
>>>> ?#define GPIO47_UART2_RXD ? ? ? MFP_CFG(GPIO47, AF6)
>>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-
>>>mmp/include/mach/mfp.h
>>>> deleted file mode 100644
>>>> index 62e510e..0000000
>>>> --- a/arch/arm/mach-mmp/include/mach/mfp.h
>>>> +++ /dev/null
>>>> @@ -1,34 +0,0 @@
>>>> -#ifndef __ASM_MACH_MFP_H
>>>> -#define __ASM_MACH_MFP_H
>>>> -
>>>> -#include <plat/mfp.h>
>>>> -
>>>> -/*
>>>> - * NOTE: the MFPR register bit definitions on PXA168 processor
>lines
>>>are a
>>>> - * bit different from those on PXA3xx. ?Bit [7:10] are now reserved,
>>>which
>>>> - * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
>>>> - *
>>>> - * To cope with this difference and re-use the pxa3xx mfp code as
>>>much as
>>>> - * possible, we make the following compromise:
>>>> - *
>>>> - * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
>>>> - * 2. DRIVE strength definitions redefined to include the reserved
>>>bit
>>>> - * ? ?- the reserved bit differs between pxa168 and pxa910, and the
>>>> - * ? ? ?MFP_DRIVE_* macros are individually defined in mfp-
>>>pxa{168,910}.h
>>>> - * 3. Override MFP_CFG() and MFP_CFG_DRV()
>>>> - * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
>>>> - */
>>>> -
>>>> -#undef MFP_CFG
>>>> -#undef MFP_CFG_DRV
>>>> -#undef MFP_CFG_LPM
>>>> -#undef MFP_CFG_X
>>>> -#undef MFP_CFG_DEFAULT
>>>> -
>>>> -#define MFP_CFG(pin, af) ? ? ? ? ? ? ? \
>>>> - ? ? ? (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af |
>>>MFP_DRIVE_MEDIUM)
>>>> -
>>>> -#define MFP_CFG_DRV(pin, af, drv) ? ? ?\
>>>> - ? ? ? (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af |
>>>MFP_DRIVE_##drv)
>>>> -
>>>> -#endif /* __ASM_MACH_MFP_H */
>>>> diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
>>>> index 8e6c3ac..14e6a23 100644
>>>> --- a/arch/arm/mach-mmp/mmp2.c
>>>> +++ b/arch/arm/mach-mmp/mmp2.c
>>>> @@ -24,10 +24,10 @@
>>>> ?#include <mach/cputype.h>
>>>> ?#include <mach/irqs.h>
>>>> ?#include <mach/dma.h>
>>>> -#include <mach/mfp.h>
>>>> ?#include <mach/gpio.h>
>>>> ?#include <mach/devices.h>
>>>> ?#include <mach/mmp2.h>
>>>> +#include <plat/mfp.h>
>>>>
>>>> ?#include "common.h"
>>>> ?#include "clock.h"
>>>> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
>>>> index 72b4e76..34df2b1 100644
>>>> --- a/arch/arm/mach-mmp/pxa168.c
>>>> +++ b/arch/arm/mach-mmp/pxa168.c
>>>> @@ -24,7 +24,7 @@
>>>> ?#include <mach/gpio.h>
>>>> ?#include <mach/dma.h>
>>>> ?#include <mach/devices.h>
>>>> -#include <mach/mfp.h>
>>>> +#include <plat/mfp.h>
>>>>
>>>> ?#include "common.h"
>>>> ?#include "clock.h"
>>>> diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
>>>> index 8f92ccd..93b3b25 100644
>>>> --- a/arch/arm/mach-mmp/pxa910.c
>>>> +++ b/arch/arm/mach-mmp/pxa910.c
>>>> @@ -22,8 +22,8 @@
>>>> ?#include <mach/irqs.h>
>>>> ?#include <mach/gpio.h>
>>>> ?#include <mach/dma.h>
>>>> -#include <mach/mfp.h>
>>>> ?#include <mach/devices.h>
>>>> +#include <plat/mfp.h>
>>>>
>>>> ?#include "common.h"
>>>> ?#include "clock.h"
>>>> diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-
>>>pxa/include/plat/mfp.h
>>>> index 75f6564..b7dde0c 100644
>>>> --- a/arch/arm/plat-pxa/include/plat/mfp.h
>>>> +++ b/arch/arm/plat-pxa/include/plat/mfp.h
>>>> @@ -378,6 +378,10 @@ typedef unsigned long mfp_cfg_t;
>>>> ?#define MFP_DS13X ? ? ? ? ? ? ?(0x7 << 13)
>>>> ?#define MFP_DS_MASK ? ? ? ? ? ?(0x7 << 13)
>>>> ?#define MFP_DS(x) ? ? ? ? ? ? ?(((x) >> 13) & 0x7)
>>>> +#define MFP_VERY_SLOW ? ? ? ? ?MFP_DS01X
>>>> +#define MFP_SLOW ? ? ? ? ? ? ? MFP_DS02X
>>>> +#define MFP_MEDIUM ? ? ? ? ? ? MFP_DS03X
>>>> +#define MFP_FAST ? ? ? ? ? ? ? MFP_DS04X
>>>>
>>>> ?#define MFP_LPM_DEFAULT ? ? ? ? ? ? ? ?(0x0 << 16)
>>>> ?#define MFP_LPM_DRIVE_LOW ? ? ?(0x1 << 16)
>>>> diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c
>>>> index a9aa5ad..d335551 100644
>>>> --- a/arch/arm/plat-pxa/mfp.c
>>>> +++ b/arch/arm/plat-pxa/mfp.c
>>>> @@ -19,6 +19,10 @@
>>>> ?#include <linux/io.h>
>>>> ?#include <linux/sysdev.h>
>>>>
>>>> +#ifdef CONFIG_ARCH_MMP
>>>> +#include <mach/cputype.h>
>>>> +#endif
>>>> +
>>>> ?#include <plat/mfp.h>
>>>>
>>>> ?#define MFPR_SIZE ? ? ?(PAGE_SIZE)
>>>> @@ -165,8 +169,14 @@ static inline void __mfp_config_lpm(struct
>>>mfp_pin *p)
>>>> ?void mfp_config(unsigned long *mfp_cfgs, int num)
>>>> ?{
>>>> ? ? ? ?unsigned long flags;
>>>> - ? ? ? int i;
>>>> -
>>>> + ? ? ? int i, drv_b11 = 0, no_lpm = 0;
>>>> +
>>>> +#ifdef CONFIG_ARCH_MMP
>>>> + ? ? ? if (cpu_is_pxa910() || cpu_is_mmp2())
>>>> + ? ? ? ? ? ? ? drv_b11 = 1;
>>>> + ? ? ? if (cpu_is_pxa168() || cpu_is_pxa910())
>>>> + ? ? ? ? ? ? ? no_lpm = 1;
>>>> +#endif
>>>> ? ? ? ?spin_lock_irqsave(&mfp_spin_lock, flags);
>>>>
>>>> ? ? ? ?for (i = 0; i < num; i++, mfp_cfgs++) {
>>>> @@ -183,6 +193,10 @@ void mfp_config(unsigned long *mfp_cfgs, int
>num)
>>>> ? ? ? ? ? ? ? ?lpm = MFP_LPM_STATE(c);
>>>> ? ? ? ? ? ? ? ?edge = MFP_LPM_EDGE(c);
>>>> ? ? ? ? ? ? ? ?pull = MFP_PULL(c);
>>>> + ? ? ? ? ? ? ? if (drv_b11)
>>>> + ? ? ? ? ? ? ? ? ? ? ? drv = drv << 1;
>>>> + ? ? ? ? ? ? ? if (no_lpm)
>>>> + ? ? ? ? ? ? ? ? ? ? ? lpm = 0;
>>>>
>>>> ? ? ? ? ? ? ? ?/* run-mode pull settings will conflict with MFPR
>bits
>>>of
>>>> ? ? ? ? ? ? ? ? * low power mode state, ?calculate mfpr_run and
>>>mfpr_lpm
>>>> @@ -272,6 +286,10 @@ void mfp_config_lpm(void)
>>>> ? ? ? ?struct mfp_pin *p = &mfp_table[0];
>>>> ? ? ? ?int pin;
>>>>
>>>> +#ifdef CONFIG_ARCH_MMP
>>>> + ? ? ? if (cpu_is_pxa168() || cpu_is_pxa910())
>>>> + ? ? ? ? ? ? ? return;
>>>> +#endif
>>>> ? ? ? ?for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
>>>> ? ? ? ? ? ? ? ?__mfp_config_lpm(p);
>>>> ?}
>>>> --
>>>> 1.5.6.5
>>>>
>>>>
>>

[PATCH 3/9] ARM: mmp: remove redundant macro definition in mfp

[Eric Miao]

On Fri, Apr 1, 2011 at 1:45 PM, Haojian Zhuang <hzhuang1@marvell.com> wrote:
>
>
>>-----Original Message-----
>>From: Eric Miao [mailto:eric.y.miao at gmail.com]
>>Sent: 2011?4?1? 1:31 PM
>>To: Haojian Zhuang
>>Cc: linux at arm.linux.org.uk; linux-arm-kernel at lists.infradead.org
>>Subject: Re: [PATCH 3/9] ARM: mmp: remove redundant macro definition in
>>mfp
>>
>>On Fri, Apr 1, 2011 at 1:09 PM, Haojian Zhuang <hzhuang1@marvell.com>
>>wrote:
>>>
>>>
>>>>-----Original Message-----
>>>>From: Eric Miao [mailto:eric.y.miao at gmail.com]
>>>>Sent: 2011?4?1? 12:51 PM
>>>>To: Haojian Zhuang
>>>>Cc: linux at arm.linux.org.uk; linux-arm-kernel at lists.infradead.org
>>>>Subject: Re: [PATCH 3/9] ARM: mmp: remove redundant macro definition
>>in
>>>>mfp
>>>>
>>>>On Fri, Apr 1, 2011 at 10:39 AM, Haojian Zhuang
>>>><haojian.zhuang@marvell.com> wrote:
>>>>> There're two layers in MFP implementation. One is MFP layer that is
>>>>logical
>>>>> pin setting. And the other is MFPR layer that is physical register
>>>>setting.
>>>>>
>>>>> MFP drive setting is different between PXA168 and PXA910. But the
>>>>difference
>>>>> was stored in logical layer, not physical layer. And some
>>unnecessary
>>>>macro
>>>>> definition were added for ARCH_MMP.
>>>>
>>>>The implementation is indeed a bit complicated, yet I don't see the
>>>>change here is necessary so far.
>>>>
>>>>The MFPR bit definitions for pxa168/910 and mmp2 are basically
>>>>following the pxa3xx's.
>>>>
>>>>And definitions like DRIVE_SLOW, DRIVE_VERY_SLOW are really
>>>>pxa168/910, mmp2 specific. And it's no equivalent to DS01X, DS02X
>>>>..., which is more pxa3xx specific.
>>>>
>>>>BTW, does the existing code cause any bug/limitation?
>>>>
>>> Yes, there's some limitation in existing code since it's for pxa3xx.
>>For example, driver strength is bit[12..10] in PXA3xx. In
>>PXA955/910/MMP2, it's bit[12..11]. In PXA168, it's bit[11..10].
>>
>>This can be covered by definitions of DRIVE_SLOW, DRIVE_FAST, and
>>it's transparent to the API usage.
>>
> But driver strength are different in logical layer for different SoCs. Actually it's hard reading and caused some error before.
> As my understanding, difference can only exists in physical layer. Logical layer should keep consistent.
>

The problem is, the drive strength is already defined differently across
SoCs. Like we defined:

_DRIVE_{VERY_SLOW, SLOW, MEDIUM, FAST} for MMP series
_DS{01X,02X,03X,...08X, 10X, 13X} for pxa3xx

And there is no such thing for pxa2xx.

>>> And there's no sleep mode in PXA168.
>>
>>Thus there will be no MFP_LPM_* usage in pxa168 board file.
>>
> It was touched in mfpr_lpm. Since LPM_INPUT is used by default. Those bits should not be touched if no requirement. I can use MFPR_FLOAT by default, so no_lpm can be avoided.

Yes please.

>
>>> Sleep mode bit is different in PXA910.
>>
>>Example, like?
>>
> Bit 7 should be always on in PXA910.

Can we solve this in mfp-pxa910.h by defining a pxa910 specific MFP_CFG()
macro?

>>>
>>>>>
>>>>> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
>>>>> ---
>>>>> ?arch/arm/mach-mmp/include/mach/mfp-mmp2.h ? | ? ?7 +----
>>>>> ?arch/arm/mach-mmp/include/mach/mfp-pxa168.h | ? ?7 +----
>>>>> ?arch/arm/mach-mmp/include/mach/mfp-pxa910.h | ? ?7 +----
>>>>> ?arch/arm/mach-mmp/include/mach/mfp.h ? ? ? ?| ? 34 ----------------
>>--
>>>>---------
>>>>> ?arch/arm/mach-mmp/mmp2.c ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
>>>>> ?arch/arm/mach-mmp/pxa168.c ? ? ? ? ? ? ? ? ?| ? ?2 +-
>>>>> ?arch/arm/mach-mmp/pxa910.c ? ? ? ? ? ? ? ? ?| ? ?2 +-
>>>>> ?arch/arm/plat-pxa/include/plat/mfp.h ? ? ? ?| ? ?4 +++
>>>>> ?arch/arm/plat-pxa/mfp.c ? ? ? ? ? ? ? ? ? ? | ? 22 +++++++++++++++-
>>>>> ?9 files changed, 30 insertions(+), 57 deletions(-)
>>>>> ?delete mode 100644 arch/arm/mach-mmp/include/mach/mfp.h
>>>>>
>>>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>>>b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>>>> index 4ad3862..c66eaea 100644
>>>>> --- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>>>> +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
>>>>> @@ -1,12 +1,7 @@
>>>>> ?#ifndef __ASM_MACH_MFP_MMP2_H
>>>>> ?#define __ASM_MACH_MFP_MMP2_H
>>>>>
>>>>> -#include <mach/mfp.h>
>>>>> -
>>>>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>>>>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x2 << 13)
>>>>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x4 << 13)
>>>>> -#define MFP_DRIVE_FAST ? ? ? ? (0x6 << 13)
>>>>> +#include <plat/mfp.h>
>>>>>
>>>>> ?/* GPIO */
>>>>> ?#define GPIO0_GPIO ? ? MFP_CFG(GPIO0, AF0)
>>>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>>>b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>>>> index 4621067..4aadbea 100644
>>>>> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>>>> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
>>>>> @@ -1,12 +1,7 @@
>>>>> ?#ifndef __ASM_MACH_MFP_PXA168_H
>>>>> ?#define __ASM_MACH_MFP_PXA168_H
>>>>>
>>>>> -#include <mach/mfp.h>
>>>>> -
>>>>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>>>>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x1 << 13)
>>>>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x2 << 13)
>>>>> -#define MFP_DRIVE_FAST ? ? ? ? (0x3 << 13)
>>>>> +#include <plat/mfp.h>
>>>>>
>>>>> ?/* GPIO */
>>>>> ?#define GPIO0_GPIO ? ? ? ? ? ? MFP_CFG(GPIO0, AF5)
>>>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>>>b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>>>> index fbd7ee8..f5d33be 100644
>>>>> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>>>> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
>>>>> @@ -1,12 +1,7 @@
>>>>> ?#ifndef __ASM_MACH_MFP_PXA910_H
>>>>> ?#define __ASM_MACH_MFP_PXA910_H
>>>>>
>>>>> -#include <mach/mfp.h>
>>>>> -
>>>>> -#define MFP_DRIVE_VERY_SLOW ? ?(0x0 << 13)
>>>>> -#define MFP_DRIVE_SLOW ? ? ? ? (0x2 << 13)
>>>>> -#define MFP_DRIVE_MEDIUM ? ? ? (0x4 << 13)
>>>>> -#define MFP_DRIVE_FAST ? ? ? ? (0x6 << 13)
>>>>> +#include <plat/mfp.h>
>>>>>
>>>>> ?/* UART2 */
>>>>> ?#define GPIO47_UART2_RXD ? ? ? MFP_CFG(GPIO47, AF6)
>>>>> diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-
>>>>mmp/include/mach/mfp.h
>>>>> deleted file mode 100644
>>>>> index 62e510e..0000000
>>>>> --- a/arch/arm/mach-mmp/include/mach/mfp.h
>>>>> +++ /dev/null
>>>>> @@ -1,34 +0,0 @@
>>>>> -#ifndef __ASM_MACH_MFP_H
>>>>> -#define __ASM_MACH_MFP_H
>>>>> -
>>>>> -#include <plat/mfp.h>
>>>>> -
>>>>> -/*
>>>>> - * NOTE: the MFPR register bit definitions on PXA168 processor
>>lines
>>>>are a
>>>>> - * bit different from those on PXA3xx. ?Bit [7:10] are now reserved,
>>>>which
>>>>> - * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
>>>>> - *
>>>>> - * To cope with this difference and re-use the pxa3xx mfp code as
>>>>much as
>>>>> - * possible, we make the following compromise:
>>>>> - *
>>>>> - * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
>>>>> - * 2. DRIVE strength definitions redefined to include the reserved
>>>>bit
>>>>> - * ? ?- the reserved bit differs between pxa168 and pxa910, and the
>>>>> - * ? ? ?MFP_DRIVE_* macros are individually defined in mfp-
>>>>pxa{168,910}.h
>>>>> - * 3. Override MFP_CFG() and MFP_CFG_DRV()
>>>>> - * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
>>>>> - */
>>>>> -
>>>>> -#undef MFP_CFG
>>>>> -#undef MFP_CFG_DRV
>>>>> -#undef MFP_CFG_LPM
>>>>> -#undef MFP_CFG_X
>>>>> -#undef MFP_CFG_DEFAULT
>>>>> -
>>>>> -#define MFP_CFG(pin, af) ? ? ? ? ? ? ? \
>>>>> - ? ? ? (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af |
>>>>MFP_DRIVE_MEDIUM)
>>>>> -
>>>>> -#define MFP_CFG_DRV(pin, af, drv) ? ? ?\
>>>>> - ? ? ? (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af |
>>>>MFP_DRIVE_##drv)
>>>>> -
>>>>> -#endif /* __ASM_MACH_MFP_H */
>>>>> diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
>>>>> index 8e6c3ac..14e6a23 100644
>>>>> --- a/arch/arm/mach-mmp/mmp2.c
>>>>> +++ b/arch/arm/mach-mmp/mmp2.c
>>>>> @@ -24,10 +24,10 @@
>>>>> ?#include <mach/cputype.h>
>>>>> ?#include <mach/irqs.h>
>>>>> ?#include <mach/dma.h>
>>>>> -#include <mach/mfp.h>
>>>>> ?#include <mach/gpio.h>
>>>>> ?#include <mach/devices.h>
>>>>> ?#include <mach/mmp2.h>
>>>>> +#include <plat/mfp.h>
>>>>>
>>>>> ?#include "common.h"
>>>>> ?#include "clock.h"
>>>>> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
>>>>> index 72b4e76..34df2b1 100644
>>>>> --- a/arch/arm/mach-mmp/pxa168.c
>>>>> +++ b/arch/arm/mach-mmp/pxa168.c
>>>>> @@ -24,7 +24,7 @@
>>>>> ?#include <mach/gpio.h>
>>>>> ?#include <mach/dma.h>
>>>>> ?#include <mach/devices.h>
>>>>> -#include <mach/mfp.h>
>>>>> +#include <plat/mfp.h>
>>>>>
>>>>> ?#include "common.h"
>>>>> ?#include "clock.h"
>>>>> diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
>>>>> index 8f92ccd..93b3b25 100644
>>>>> --- a/arch/arm/mach-mmp/pxa910.c
>>>>> +++ b/arch/arm/mach-mmp/pxa910.c
>>>>> @@ -22,8 +22,8 @@
>>>>> ?#include <mach/irqs.h>
>>>>> ?#include <mach/gpio.h>
>>>>> ?#include <mach/dma.h>
>>>>> -#include <mach/mfp.h>
>>>>> ?#include <mach/devices.h>
>>>>> +#include <plat/mfp.h>
>>>>>
>>>>> ?#include "common.h"
>>>>> ?#include "clock.h"
>>>>> diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-
>>>>pxa/include/plat/mfp.h
>>>>> index 75f6564..b7dde0c 100644
>>>>> --- a/arch/arm/plat-pxa/include/plat/mfp.h
>>>>> +++ b/arch/arm/plat-pxa/include/plat/mfp.h
>>>>> @@ -378,6 +378,10 @@ typedef unsigned long mfp_cfg_t;
>>>>> ?#define MFP_DS13X ? ? ? ? ? ? ?(0x7 << 13)
>>>>> ?#define MFP_DS_MASK ? ? ? ? ? ?(0x7 << 13)
>>>>> ?#define MFP_DS(x) ? ? ? ? ? ? ?(((x) >> 13) & 0x7)
>>>>> +#define MFP_VERY_SLOW ? ? ? ? ?MFP_DS01X
>>>>> +#define MFP_SLOW ? ? ? ? ? ? ? MFP_DS02X
>>>>> +#define MFP_MEDIUM ? ? ? ? ? ? MFP_DS03X
>>>>> +#define MFP_FAST ? ? ? ? ? ? ? MFP_DS04X
>>>>>
>>>>> ?#define MFP_LPM_DEFAULT ? ? ? ? ? ? ? ?(0x0 << 16)
>>>>> ?#define MFP_LPM_DRIVE_LOW ? ? ?(0x1 << 16)
>>>>> diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c
>>>>> index a9aa5ad..d335551 100644
>>>>> --- a/arch/arm/plat-pxa/mfp.c
>>>>> +++ b/arch/arm/plat-pxa/mfp.c
>>>>> @@ -19,6 +19,10 @@
>>>>> ?#include <linux/io.h>
>>>>> ?#include <linux/sysdev.h>
>>>>>
>>>>> +#ifdef CONFIG_ARCH_MMP
>>>>> +#include <mach/cputype.h>
>>>>> +#endif
>>>>> +
>>>>> ?#include <plat/mfp.h>
>>>>>
>>>>> ?#define MFPR_SIZE ? ? ?(PAGE_SIZE)
>>>>> @@ -165,8 +169,14 @@ static inline void __mfp_config_lpm(struct
>>>>mfp_pin *p)
>>>>> ?void mfp_config(unsigned long *mfp_cfgs, int num)
>>>>> ?{
>>>>> ? ? ? ?unsigned long flags;
>>>>> - ? ? ? int i;
>>>>> -
>>>>> + ? ? ? int i, drv_b11 = 0, no_lpm = 0;
>>>>> +
>>>>> +#ifdef CONFIG_ARCH_MMP
>>>>> + ? ? ? if (cpu_is_pxa910() || cpu_is_mmp2())
>>>>> + ? ? ? ? ? ? ? drv_b11 = 1;
>>>>> + ? ? ? if (cpu_is_pxa168() || cpu_is_pxa910())
>>>>> + ? ? ? ? ? ? ? no_lpm = 1;
>>>>> +#endif
>>>>> ? ? ? ?spin_lock_irqsave(&mfp_spin_lock, flags);
>>>>>
>>>>> ? ? ? ?for (i = 0; i < num; i++, mfp_cfgs++) {
>>>>> @@ -183,6 +193,10 @@ void mfp_config(unsigned long *mfp_cfgs, int
>>num)
>>>>> ? ? ? ? ? ? ? ?lpm = MFP_LPM_STATE(c);
>>>>> ? ? ? ? ? ? ? ?edge = MFP_LPM_EDGE(c);
>>>>> ? ? ? ? ? ? ? ?pull = MFP_PULL(c);
>>>>> + ? ? ? ? ? ? ? if (drv_b11)
>>>>> + ? ? ? ? ? ? ? ? ? ? ? drv = drv << 1;
>>>>> + ? ? ? ? ? ? ? if (no_lpm)
>>>>> + ? ? ? ? ? ? ? ? ? ? ? lpm = 0;
>>>>>
>>>>> ? ? ? ? ? ? ? ?/* run-mode pull settings will conflict with MFPR
>>bits
>>>>of
>>>>> ? ? ? ? ? ? ? ? * low power mode state, ?calculate mfpr_run and
>>>>mfpr_lpm
>>>>> @@ -272,6 +286,10 @@ void mfp_config_lpm(void)
>>>>> ? ? ? ?struct mfp_pin *p = &mfp_table[0];
>>>>> ? ? ? ?int pin;
>>>>>
>>>>> +#ifdef CONFIG_ARCH_MMP
>>>>> + ? ? ? if (cpu_is_pxa168() || cpu_is_pxa910())
>>>>> + ? ? ? ? ? ? ? return;
>>>>> +#endif
>>>>> ? ? ? ?for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
>>>>> ? ? ? ? ? ? ? ?__mfp_config_lpm(p);
>>>>> ?}
>>>>> --
>>>>> 1.5.6.5
>>>>>
>>>>>
>>>
>

[PATCH 2/9] ARM: pxa: enable sparsemem in saarb

[Eric Miao]

On Fri, Apr 1, 2011 at 10:39 AM, Haojian Zhuang
<haojian.zhuang@marvell.com> wrote:
> Make sparsemem to support 512MB low memory with two banks in SAARB.
>
> Change-Id: I1688dde366b5f3b13b48b7167bf6b88afc4f9a92
> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>

The concern is that this will exclude SAARB from being built into a single
binary with other boards. Did you ever try HIGHMEM?

> ---
> ?arch/arm/mach-pxa/Kconfig ? ? ? ? ? ? ? | ? ?1 +
> ?arch/arm/mach-pxa/include/mach/memory.h | ? 36 ++++++++++++++++++++++++++++++-
> ?2 files changed, 36 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
> index 2fc9f94..e8615ee 100644
> --- a/arch/arm/mach-pxa/Kconfig
> +++ b/arch/arm/mach-pxa/Kconfig
> @@ -53,6 +53,7 @@ config MACH_SAAR
> ?config MACH_SAARB
> ? ? ? ?bool "PXA955 Handheld Platform (aka SAARB)"
> ? ? ? ?select CPU_PXA955
> + ? ? ? select ARCH_SPARSEMEM_ENABLE
>
> ?comment "Third Party Dev Platforms (sorted by vendor name)"
>
> diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
> index 92361a6..9a3f265 100644
> --- a/arch/arm/mach-pxa/include/mach/memory.h
> +++ b/arch/arm/mach-pxa/include/mach/memory.h
> @@ -3,6 +3,7 @@
> ?*
> ?* Author: ? ? Nicolas Pitre
> ?* Copyright: ?(C) 2001 MontaVista Software Inc.
> + * Copyright: ?(C) 2010 Marvell Semiconductor Inc.
> ?*
> ?* This program is free software; you can redistribute it and/or modify
> ?* it under the terms of the GNU General Public License version 2 as
> @@ -27,4 +28,37 @@ void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes);
> ?#define MAX_DMA_ADDRESS ? ? ? ? ? ? ? ?(PAGE_OFFSET + SZ_64M)
> ?#endif
>
> -#endif
> +
> +#ifdef CONFIG_SPARSEMEM
> +
> +#if defined(CONFIG_MACH_SAARB) || defined(CONFIG_MACH_SAARB_MG1)
> +/*
> + * There're two DRAM banks in PXA955 Saarb board.
> + *
> + * The macros below define sections with 256MB size and a non-linear virtual to
> + * physical mapping:
> + *
> + * node 0: 0x80000000-0x8fffffff -> 0xc0000000-0xcfffffff
> + * node 1: 0xc0000000-0xcfffffff -> 0xd0000000-0xdfffffff
> + *
> + * Since DRAM can be wrapped, 0xa0000000 equals to 0x80000000.
> + */
> +#define MAX_PHYSMEM_BITS ? ? ? 32
> +#define SECTION_SIZE_BITS ? ? ?28
> +
> +/* bank page offsets */
> +#define BANK_PAGE_OFFSET ? ? ? (PAGE_OFFSET + 0x10000000)
> +
> +#define __phys_to_virt(phys) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ((phys) >= 0xc0000000 ? (phys) - 0xc0000000 + BANK_PAGE_OFFSET :\
> + ? ? ? ?(phys) >= 0xa0000000 ? (phys) - 0xa0000000 + PAGE_OFFSET : ? ? \
> + ? ? ? ?(phys) - 0x80000000 + PAGE_OFFSET) ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> +
> +#define __virt_to_phys(virt) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ((virt) >= BANK_PAGE_OFFSET ? (virt) - BANK_PAGE_OFFSET + 0xc0000000 :\
> + ? ? ? ?(virt) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
> +#endif /* CONFIG_MACH_SAARB || CONFIG_MACH_SAARB_MG1 */
> +
> +#endif /* CONFIG_SPARSEMEM */
> +
> +#endif /* __ASM_ARCH_MEMORY_H */
> --
> 1.5.6.5
>
>

[PATCH 2/9] ARM: pxa: enable sparsemem in saarb

[Haojian Zhuang]

>-----Original Message-----
>From: Eric Miao [mailto:eric.y.miao at gmail.com]
>Sent: 2011?4?1? 11:46 AM
>To: Haojian Zhuang
>Cc: linux at arm.linux.org.uk; linux-arm-kernel at lists.infradead.org
>Subject: Re: [PATCH 2/9] ARM: pxa: enable sparsemem in saarb
>
>On Fri, Apr 1, 2011 at 10:39 AM, Haojian Zhuang
><haojian.zhuang@marvell.com> wrote:
>> Make sparsemem to support 512MB low memory with two banks in SAARB.
>>
>> Change-Id: I1688dde366b5f3b13b48b7167bf6b88afc4f9a92
>> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
>
>The concern is that this will exclude SAARB from being built into a
>single
>binary with other boards. Did you ever try HIGHMEM?
>
If I use HIGHMEM now, our some drivers and apps should be changed also. We don't want to change them.

>> ---
>> ?arch/arm/mach-pxa/Kconfig ? ? ? ? ? ? ? | ? ?1 +
>> ?arch/arm/mach-pxa/include/mach/memory.h | ? 36
>++++++++++++++++++++++++++++++-
>> ?2 files changed, 36 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
>> index 2fc9f94..e8615ee 100644
>> --- a/arch/arm/mach-pxa/Kconfig
>> +++ b/arch/arm/mach-pxa/Kconfig
>> @@ -53,6 +53,7 @@ config MACH_SAAR
>> ?config MACH_SAARB
>> ? ? ? ?bool "PXA955 Handheld Platform (aka SAARB)"
>> ? ? ? ?select CPU_PXA955
>> + ? ? ? select ARCH_SPARSEMEM_ENABLE
>>
>> ?comment "Third Party Dev Platforms (sorted by vendor name)"
>>
>> diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-
>pxa/include/mach/memory.h
>> index 92361a6..9a3f265 100644
>> --- a/arch/arm/mach-pxa/include/mach/memory.h
>> +++ b/arch/arm/mach-pxa/include/mach/memory.h
>> @@ -3,6 +3,7 @@
>> ?*
>> ?* Author: ? ? Nicolas Pitre
>> ?* Copyright: ?(C) 2001 MontaVista Software Inc.
>> + * Copyright: ?(C) 2010 Marvell Semiconductor Inc.
>> ?*
>> ?* This program is free software; you can redistribute it and/or
>modify
>> ?* it under the terms of the GNU General Public License version 2 as
>> @@ -27,4 +28,37 @@ void cmx2xx_pci_adjust_zones(unsigned long *size,
>unsigned long *holes);
>> ?#define MAX_DMA_ADDRESS ? ? ? ? ? ? ? ?(PAGE_OFFSET + SZ_64M)
>> ?#endif
>>
>> -#endif
>> +
>> +#ifdef CONFIG_SPARSEMEM
>> +
>> +#if defined(CONFIG_MACH_SAARB) || defined(CONFIG_MACH_SAARB_MG1)
>> +/*
>> + * There're two DRAM banks in PXA955 Saarb board.
>> + *
>> + * The macros below define sections with 256MB size and a non-linear
>virtual to
>> + * physical mapping:
>> + *
>> + * node 0: 0x80000000-0x8fffffff -> 0xc0000000-0xcfffffff
>> + * node 1: 0xc0000000-0xcfffffff -> 0xd0000000-0xdfffffff
>> + *
>> + * Since DRAM can be wrapped, 0xa0000000 equals to 0x80000000.
>> + */
>> +#define MAX_PHYSMEM_BITS ? ? ? 32
>> +#define SECTION_SIZE_BITS ? ? ?28
>> +
>> +/* bank page offsets */
>> +#define BANK_PAGE_OFFSET ? ? ? (PAGE_OFFSET + 0x10000000)
>> +
>> +#define
>__phys_to_virt(phys) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ((phys) >= 0xc0000000 ? (phys) - 0xc0000000 +
>BANK_PAGE_OFFSET :\
>> + ? ? ? ?(phys) >= 0xa0000000 ? (phys) - 0xa0000000 +
>PAGE_OFFSET : ? ? \
>> + ? ? ? ?(phys) - 0x80000000 +
>PAGE_OFFSET) ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> +
>> +#define
>__virt_to_phys(virt) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ((virt) >= BANK_PAGE_OFFSET ? (virt) - BANK_PAGE_OFFSET +
>0xc0000000 :\
>> + ? ? ? ?(virt) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
>> +#endif /* CONFIG_MACH_SAARB || CONFIG_MACH_SAARB_MG1 */
>> +
>> +#endif /* CONFIG_SPARSEMEM */
>> +
>> +#endif /* __ASM_ARCH_MEMORY_H */
>> --
>> 1.5.6.5
>>
>>

[PATCH 2/9] ARM: pxa: enable sparsemem in saarb

[Eric Miao]

On Fri, Apr 1, 2011 at 12:35 PM, Haojian Zhuang <hzhuang1@marvell.com> wrote:
>
>
>>-----Original Message-----
>>From: Eric Miao [mailto:eric.y.miao at gmail.com]
>>Sent: 2011?4?1? 11:46 AM
>>To: Haojian Zhuang
>>Cc: linux at arm.linux.org.uk; linux-arm-kernel at lists.infradead.org
>>Subject: Re: [PATCH 2/9] ARM: pxa: enable sparsemem in saarb
>>
>>On Fri, Apr 1, 2011 at 10:39 AM, Haojian Zhuang
>><haojian.zhuang@marvell.com> wrote:
>>> Make sparsemem to support 512MB low memory with two banks in SAARB.
>>>
>>> Change-Id: I1688dde366b5f3b13b48b7167bf6b88afc4f9a92
>>> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
>>
>>The concern is that this will exclude SAARB from being built into a
>>single
>>binary with other boards. Did you ever try HIGHMEM?
>>
> If I use HIGHMEM now, our some drivers and apps should be changed also. We don't want to change them.

I don't understand this will cause side effects to other drivers and apps?

>
>>> ---
>>> ?arch/arm/mach-pxa/Kconfig ? ? ? ? ? ? ? | ? ?1 +
>>> ?arch/arm/mach-pxa/include/mach/memory.h | ? 36
>>++++++++++++++++++++++++++++++-
>>> ?2 files changed, 36 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
>>> index 2fc9f94..e8615ee 100644
>>> --- a/arch/arm/mach-pxa/Kconfig
>>> +++ b/arch/arm/mach-pxa/Kconfig
>>> @@ -53,6 +53,7 @@ config MACH_SAAR
>>> ?config MACH_SAARB
>>> ? ? ? ?bool "PXA955 Handheld Platform (aka SAARB)"
>>> ? ? ? ?select CPU_PXA955
>>> + ? ? ? select ARCH_SPARSEMEM_ENABLE
>>>
>>> ?comment "Third Party Dev Platforms (sorted by vendor name)"
>>>
>>> diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-
>>pxa/include/mach/memory.h
>>> index 92361a6..9a3f265 100644
>>> --- a/arch/arm/mach-pxa/include/mach/memory.h
>>> +++ b/arch/arm/mach-pxa/include/mach/memory.h
>>> @@ -3,6 +3,7 @@
>>> ?*
>>> ?* Author: ? ? Nicolas Pitre
>>> ?* Copyright: ?(C) 2001 MontaVista Software Inc.
>>> + * Copyright: ?(C) 2010 Marvell Semiconductor Inc.
>>> ?*
>>> ?* This program is free software; you can redistribute it and/or
>>modify
>>> ?* it under the terms of the GNU General Public License version 2 as
>>> @@ -27,4 +28,37 @@ void cmx2xx_pci_adjust_zones(unsigned long *size,
>>unsigned long *holes);
>>> ?#define MAX_DMA_ADDRESS ? ? ? ? ? ? ? ?(PAGE_OFFSET + SZ_64M)
>>> ?#endif
>>>
>>> -#endif
>>> +
>>> +#ifdef CONFIG_SPARSEMEM
>>> +
>>> +#if defined(CONFIG_MACH_SAARB) || defined(CONFIG_MACH_SAARB_MG1)
>>> +/*
>>> + * There're two DRAM banks in PXA955 Saarb board.
>>> + *
>>> + * The macros below define sections with 256MB size and a non-linear
>>virtual to
>>> + * physical mapping:
>>> + *
>>> + * node 0: 0x80000000-0x8fffffff -> 0xc0000000-0xcfffffff
>>> + * node 1: 0xc0000000-0xcfffffff -> 0xd0000000-0xdfffffff
>>> + *
>>> + * Since DRAM can be wrapped, 0xa0000000 equals to 0x80000000.
>>> + */
>>> +#define MAX_PHYSMEM_BITS ? ? ? 32
>>> +#define SECTION_SIZE_BITS ? ? ?28
>>> +
>>> +/* bank page offsets */
>>> +#define BANK_PAGE_OFFSET ? ? ? (PAGE_OFFSET + 0x10000000)
>>> +
>>> +#define
>>__phys_to_virt(phys) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>>> + ? ? ? ((phys) >= 0xc0000000 ? (phys) - 0xc0000000 +
>>BANK_PAGE_OFFSET :\
>>> + ? ? ? ?(phys) >= 0xa0000000 ? (phys) - 0xa0000000 +
>>PAGE_OFFSET : ? ? \
>>> + ? ? ? ?(phys) - 0x80000000 +
>>PAGE_OFFSET) ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>>> +
>>> +#define
>>__virt_to_phys(virt) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>>> + ? ? ? ((virt) >= BANK_PAGE_OFFSET ? (virt) - BANK_PAGE_OFFSET +
>>0xc0000000 :\
>>> + ? ? ? ?(virt) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
>>> +#endif /* CONFIG_MACH_SAARB || CONFIG_MACH_SAARB_MG1 */
>>> +
>>> +#endif /* CONFIG_SPARSEMEM */
>>> +
>>> +#endif /* __ASM_ARCH_MEMORY_H */
>>> --
>>> 1.5.6.5
>>>
>>>
>

[PATCH 2/9] ARM: pxa: enable sparsemem in saarb

[Russell King - ARM Linux]

On Fri, Apr 01, 2011 at 01:10:52PM +0800, Eric Miao wrote:
> On Fri, Apr 1, 2011 at 12:35 PM, Haojian Zhuang <hzhuang1@marvell.com> wrote:
> > If I use HIGHMEM now, our some drivers and apps should be changed also. We don't want to change them.
> 
> I don't understand this will cause side effects to other drivers and apps?

If they're not using kmap_atomic() but are dealing directly with
page addresses, they'll fail if the pages are coming from highmem.

Given Linus' complaints in the OMAP pull request thread, I think we
should refuse, and have the drivers fixed to work with highmem.

[PATCH 2/9] ARM: pxa: enable sparsemem in saarb

[Eric Miao]

On Sat, Apr 2, 2011 at 2:33 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Fri, Apr 01, 2011 at 01:10:52PM +0800, Eric Miao wrote:
>> On Fri, Apr 1, 2011 at 12:35 PM, Haojian Zhuang <hzhuang1@marvell.com> wrote:
>> > If I use HIGHMEM now, our some drivers and apps should be changed also. We don't want to change them.
>>
>> I don't understand this will cause side effects to other drivers and apps?
>
> If they're not using kmap_atomic() but are dealing directly with
> page addresses, they'll fail if the pages are coming from highmem.
>
> Given Linus' complaints in the OMAP pull request thread, I think we
> should refuse, and have the drivers fixed to work with highmem.
>

That's what I thought as well.

Haojian,

Please work on enabling highmem, anything that's going to prevent
us from having a single kernel binary, will just make the situation
worse. Thanks

[PATCH 2/9] ARM: pxa: enable sparsemem in saarb

[Russell King - ARM Linux]

On Fri, Apr 01, 2011 at 10:39:21AM +0800, Haojian Zhuang wrote:
> Make sparsemem to support 512MB low memory with two banks in SAARB.
> 
> Change-Id: I1688dde366b5f3b13b48b7167bf6b88afc4f9a92
> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
> ---
>  arch/arm/mach-pxa/Kconfig               |    1 +
>  arch/arm/mach-pxa/include/mach/memory.h |   36 ++++++++++++++++++++++++++++++-
>  2 files changed, 36 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
> index 2fc9f94..e8615ee 100644
> --- a/arch/arm/mach-pxa/Kconfig
> +++ b/arch/arm/mach-pxa/Kconfig
> @@ -53,6 +53,7 @@ config MACH_SAAR
>  config MACH_SAARB
>  	bool "PXA955 Handheld Platform (aka SAARB)"
>  	select CPU_PXA955
> +	select ARCH_SPARSEMEM_ENABLE
>  
>  comment "Third Party Dev Platforms (sorted by vendor name)"
>  
> diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
> index 92361a6..9a3f265 100644
> --- a/arch/arm/mach-pxa/include/mach/memory.h
> +++ b/arch/arm/mach-pxa/include/mach/memory.h
> @@ -3,6 +3,7 @@
>   *
>   * Author:	Nicolas Pitre
>   * Copyright:	(C) 2001 MontaVista Software Inc.
> + * Copyright:	(C) 2010 Marvell Semiconductor Inc.
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
> @@ -27,4 +28,37 @@ void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes);
>  #define MAX_DMA_ADDRESS		(PAGE_OFFSET + SZ_64M)
>  #endif
>  
> -#endif
> +
> +#ifdef CONFIG_SPARSEMEM
> +
> +#if defined(CONFIG_MACH_SAARB) || defined(CONFIG_MACH_SAARB_MG1)
> +/*
> + * There're two DRAM banks in PXA955 Saarb board.
> + *
> + * The macros below define sections with 256MB size and a non-linear virtual to
> + * physical mapping:
> + *
> + * node 0: 0x80000000-0x8fffffff -> 0xc0000000-0xcfffffff
> + * node 1: 0xc0000000-0xcfffffff -> 0xd0000000-0xdfffffff
> + *
> + * Since DRAM can be wrapped, 0xa0000000 equals to 0x80000000.
> + */
> +#define MAX_PHYSMEM_BITS	32
> +#define SECTION_SIZE_BITS	28
> +
> +/* bank page offsets */
> +#define BANK_PAGE_OFFSET	(PAGE_OFFSET + 0x10000000)
> +
> +#define __phys_to_virt(phys)						\
> +	((phys) >= 0xc0000000 ? (phys) - 0xc0000000 + BANK_PAGE_OFFSET :\
> +	 (phys) >= 0xa0000000 ? (phys) - 0xa0000000 + PAGE_OFFSET :	\
> +	 (phys) - 0x80000000 + PAGE_OFFSET)				\
> +
> +#define __virt_to_phys(virt)						\
> +	((virt) >= BANK_PAGE_OFFSET ? (virt) - BANK_PAGE_OFFSET + 0xc0000000 :\
> +	 (virt) - PAGE_OFFSET + PLAT_PHYS_OFFSET)

This immediately means that you can't use the dynamic P2V stuff on PXA,
and so PXA can't be integrated with any other platform.  Is there a reason
why you can't use highmem rather than squashing both 256MB banks into one
512MB region?

[PATCH 1/9] ARM: pxa: add clk_set_rate()

[Eric Miao]

On Fri, Apr 1, 2011 at 10:39 AM, Haojian Zhuang
<haojian.zhuang@marvell.com> wrote:
> Since there're mulitple clock rates in some device controllers, enable
> clk_set_rate() for this usage.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>

OK, looks good.

> ---
> ?arch/arm/mach-mmp/clock.c | ? 15 +++++++++++++++
> ?arch/arm/mach-mmp/clock.h | ? ?1 +
> ?arch/arm/mach-pxa/clock.c | ? 15 +++++++++++++++
> ?arch/arm/mach-pxa/clock.h | ? ?1 +
> ?4 files changed, 32 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
> index 886e056..7c6f95f 100644
> --- a/arch/arm/mach-mmp/clock.c
> +++ b/arch/arm/mach-mmp/clock.c
> @@ -88,3 +88,18 @@ unsigned long clk_get_rate(struct clk *clk)
> ? ? ? ?return rate;
> ?}
> ?EXPORT_SYMBOL(clk_get_rate);
> +
> +int clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> + ? ? ? unsigned long flags;
> + ? ? ? int ret = -EINVAL;
> +
> + ? ? ? if (clk->ops->setrate) {
> + ? ? ? ? ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? ? ? ? ? ret = clk->ops->setrate(clk, rate);
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> + ? ? ? }
> +
> + ? ? ? return ret;
> +}
> +EXPORT_SYMBOL(clk_set_rate);
> diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
> index 9b027d7..3143e99 100644
> --- a/arch/arm/mach-mmp/clock.h
> +++ b/arch/arm/mach-mmp/clock.h
> @@ -12,6 +12,7 @@ struct clkops {
> ? ? ? ?void ? ? ? ? ? ? ? ? ? ?(*enable)(struct clk *);
> ? ? ? ?void ? ? ? ? ? ? ? ? ? ?(*disable)(struct clk *);
> ? ? ? ?unsigned long ? ? ? ? ? (*getrate)(struct clk *);
> + ? ? ? int ? ? ? ? ? ? ? ? ? ? (*setrate)(struct clk *, unsigned long);
> ?};
>
> ?struct clk {
> diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
> index d515222..4d46610 100644
> --- a/arch/arm/mach-pxa/clock.c
> +++ b/arch/arm/mach-pxa/clock.c
> @@ -53,6 +53,21 @@ unsigned long clk_get_rate(struct clk *clk)
> ?}
> ?EXPORT_SYMBOL(clk_get_rate);
>
> +int clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> + ? ? ? unsigned long flags;
> + ? ? ? int ret = -EINVAL;
> +
> + ? ? ? if (clk->ops->setrate) {
> + ? ? ? ? ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? ? ? ? ? ret = clk->ops->setrate(clk, rate);
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> + ? ? ? }
> +
> + ? ? ? return ret;
> +}
> +EXPORT_SYMBOL(clk_set_rate);
> +
> ?void clk_dummy_enable(struct clk *clk)
> ?{
> ?}
> diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
> index f9f349a..7373853 100644
> --- a/arch/arm/mach-pxa/clock.h
> +++ b/arch/arm/mach-pxa/clock.h
> @@ -5,6 +5,7 @@ struct clkops {
> ? ? ? ?void ? ? ? ? ? ? ? ? ? ?(*enable)(struct clk *);
> ? ? ? ?void ? ? ? ? ? ? ? ? ? ?(*disable)(struct clk *);
> ? ? ? ?unsigned long ? ? ? ? ? (*getrate)(struct clk *);
> + ? ? ? int ? ? ? ? ? ? ? ? ? ? (*setrate)(struct clk *, unsigned long);
> ?};
>
> ?struct clk {
> --
> 1.5.6.5
>
>