[PATCH 1/7] ARM: pxa: add clk_set_rate()

[PATCH 1/7] ARM: pxa: add clk_set_rate()

[Haojian Zhuang]

Since there're mulitple clock rates in some device controllers, enable
clk_set_rate() for this usage.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: Eric Miao <eric.y.miao@gmail.com>
---
 arch/arm/mach-mmp/clock.c |   15 +++++++++++++++
 arch/arm/mach-mmp/clock.h |    1 +
 arch/arm/mach-pxa/clock.c |   15 +++++++++++++++
 arch/arm/mach-pxa/clock.h |    1 +
 4 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
index 886e056..7c6f95f 100644
--- a/arch/arm/mach-mmp/clock.c
+++ b/arch/arm/mach-mmp/clock.c
@@ -88,3 +88,18 @@ unsigned long clk_get_rate(struct clk *clk)
 	return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long flags;
+	int ret = -EINVAL;
+
+	if (clk->ops->setrate) {
+		spin_lock_irqsave(&clocks_lock, flags);
+		ret = clk->ops->setrate(clk, rate);
+		spin_unlock_irqrestore(&clocks_lock, flags);
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
index 9b027d7..3143e99 100644
--- a/arch/arm/mach-mmp/clock.h
+++ b/arch/arm/mach-mmp/clock.h
@@ -12,6 +12,7 @@ struct clkops {
 	void			(*enable)(struct clk *);
 	void			(*disable)(struct clk *);
 	unsigned long		(*getrate)(struct clk *);
+	int			(*setrate)(struct clk *, unsigned long);
 };
 
 struct clk {
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index d515222..4d46610 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -53,6 +53,21 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long flags;
+	int ret = -EINVAL;
+
+	if (clk->ops->setrate) {
+		spin_lock_irqsave(&clocks_lock, flags);
+		ret = clk->ops->setrate(clk, rate);
+		spin_unlock_irqrestore(&clocks_lock, flags);
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
 void clk_dummy_enable(struct clk *clk)
 {
 }
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index f9f349a..7373853 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -5,6 +5,7 @@ struct clkops {
 	void			(*enable)(struct clk *);
 	void			(*disable)(struct clk *);
 	unsigned long		(*getrate)(struct clk *);
+	int			(*setrate)(struct clk *, unsigned long);
 };
 
 struct clk {
-- 
1.5.6.5

[PATCH 2/7] ARM: pxa: always clear LPM bits for PXA168 MFPR

[Haojian Zhuang]

Bit[9:7] should always be zero in PXA168.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/include/mach/mfp-pxa168.h |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index 4621067..713be15 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -8,6 +8,15 @@
 #define MFP_DRIVE_MEDIUM	(0x2 << 13)
 #define MFP_DRIVE_FAST		(0x3 << 13)
 
+#undef MFP_CFG
+#undef MFP_CFG_DRV
+
+#define MFP_CFG(pin, af)		\
+	(MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
+
+#define MFP_CFG_DRV(pin, af, drv)	\
+	(MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
+
 /* GPIO */
 #define GPIO0_GPIO		MFP_CFG(GPIO0, AF5)
 #define GPIO1_GPIO		MFP_CFG(GPIO1, AF5)
-- 
1.5.6.5

[PATCH 3/7] ARM: mmp: set correct uart according to board

[Haojian Zhuang]

UART3 is the default console in jasper, brownstone and avengers lite.

Change-Id: Iacfe665cc0e20a47d50e0b2ad8724097f28e7d2c
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/include/mach/debug-macro.S |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index 7e2ebd3..b353785 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -14,8 +14,14 @@
 		.macro	addruart, rp, rv
 		ldr	\rp, =APB_PHYS_BASE		@ physical
 		ldr	\rv, =APB_VIRT_BASE		@ virtual
+#if defined(CONFIG_MACH_BROWNSTONE) || defined(CONFIG_MACH_MARVELL_JASPER) \
+	|| defined(CONFIG_MACH_AVENGERS_LITE)
+		orr	\rp, \rp, #0x00018000
+		orr	\rv, \rv, #0x00018000
+#else
 		orr	\rp, \rp, #0x00017000
 		orr	\rv, \rv, #0x00017000
+#endif
 		.endm
 
 #define UART_SHIFT	2
-- 
1.5.6.5

[PATCH 4/7] ARM: mmp: update the reset implementation

[Haojian Zhuang]

Both PXA910 and MMP2 need watchdog reset, so add these features.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/Makefile                   |    2 +-
 arch/arm/mach-mmp/include/mach/regs-mpmu.h   |   52 +++++++++++++
 arch/arm/mach-mmp/include/mach/regs-timers.h |    2 +
 arch/arm/mach-mmp/include/mach/system.h      |    8 +--
 arch/arm/mach-mmp/reset.c                    |  100 ++++++++++++++++++++++++++
 5 files changed, 156 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/mach-mmp/include/mach/regs-mpmu.h
 create mode 100644 arch/arm/mach-mmp/reset.c

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 5c68382..6043f31 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,7 +2,7 @@
 # Makefile for Marvell's PXA168 processors line
 #
 
-obj-y				+= common.o clock.o devices.o time.o
+obj-y				+= common.o clock.o devices.o time.o reset.o
 
 # SoC support
 obj-$(CONFIG_CPU_PXA168)	+= pxa168.o irq-pxa168.o
diff --git a/arch/arm/mach-mmp/include/mach/regs-mpmu.h b/arch/arm/mach-mmp/include/mach/regs-mpmu.h
new file mode 100644
index 0000000..e2fdc4e
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-mpmu.h
@@ -0,0 +1,52 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/regs-mpmu.h
+ *
+ *   Main Power Management Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_MPMU_H
+#define __ASM_MACH_REGS_MPMU_H
+
+#include <mach/addr-map.h>
+
+#define MPMU_VIRT_BASE		(APB_VIRT_BASE + 0x50000)
+#define MPMU_REG(off)		(MPMU_VIRT_BASE + (off))
+
+#define MPMU_CPCR		MPMU_REG(0x0000)
+#define MPMU_FCCR		MPMU_REG(0x0008)
+#define MPMU_POCR		MPMU_REG(0x000c)
+#define MPMU_POSR		MPMU_REG(0x0010)
+#define MPMU_SUCCR		MPMU_REG(0x0014)
+#define MPMU_VRCR		MPMU_REG(0x0018)
+#define MPMU_OHCR		MPMU_REG(0x001c)
+#define MPMU_CPRR		MPMU_REG(0x0020)
+#define MPMU_CCGR		MPMU_REG(0x0024)
+#define MPMU_GPCR		MPMU_REG(0x0030)
+#define MPMU_PLL2CR		MPMU_REG(0x0034)
+#define MPMU_SCCR		MPMU_REG(0x0038)
+#define MPMU_ISCCRX0		MPMU_REG(0x0040)
+#define MPMU_ISCCRX1		MPMU_REG(0x0044)
+#define MPMU_CWUCRM		MPMU_REG(0x004c)
+#define MPMU_PLL1_REG1		MPMU_REG(0x0050)
+#define MPMU_PLL1_REG2		MPMU_REG(0x0054)
+#define MPMU_PLL1_SSC		MPMU_REG(0x0058)
+#define MPMU_PLL2_REG1		MPMU_REG(0x0060)
+#define MPMU_PLL2_REG2		MPMU_REG(0x0064)
+#define MPMU_PLL2_SSC		MPMU_REG(0x0068)
+#define MPMU_SD_ROT_WAKE_CLR	MPMU_REG(0x007c)
+#define MPMU_PLL2_CTRL1		MPMU_REG(0x0414)
+#define MPMU_TS			MPMU_REG(0x0080)
+#define MPMU_WDTPCR		MPMU_REG(0x0200)
+#define MPMU_APCR		MPMU_REG(0x1000)
+#define MPMU_APSR		MPMU_REG(0x1004)
+#define MPMU_APRR		MPMU_REG(0x1020)
+#define MPMU_ACGR		MPMU_REG(0x1024)
+#define MPMU_ARSR		MPMU_REG(0x1028)
+#define MPMU_AWUCRS		MPMU_REG(0x1048)
+#define MPMU_AWUCRM		MPMU_REG(0x104c)
+
+#endif /* __ASM_MACH_REGS_MPMU_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-timers.h b/arch/arm/mach-mmp/include/mach/regs-timers.h
index 45589fe..17f56fe 100644
--- a/arch/arm/mach-mmp/include/mach/regs-timers.h
+++ b/arch/arm/mach-mmp/include/mach/regs-timers.h
@@ -15,6 +15,8 @@
 
 #define TIMERS1_VIRT_BASE	(APB_VIRT_BASE + 0x14000)
 #define TIMERS2_VIRT_BASE	(APB_VIRT_BASE + 0x16000)
+#define CP_TIMERS2_VIRT_BASE	(APB_VIRT_BASE + 0x80000)
+#define MMP2_TIMERS2_VIRT_BASE	(APB_VIRT_BASE + 0x80000)
 
 #define TMR_CCR		(0x0000)
 #define TMR_TN_MM(n, m)	(0x0004 + ((n) << 3) + (((n) + (m)) << 2))
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
index 1a8a25e..31e15cf 100644
--- a/arch/arm/mach-mmp/include/mach/system.h
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -16,11 +16,5 @@ static inline void arch_idle(void)
 	cpu_do_idle();
 }
 
-static inline void arch_reset(char mode, const char *cmd)
-{
-	if (cpu_is_pxa168())
-		cpu_reset(0xffff0000);
-	else
-		cpu_reset(0);
-}
+extern void arch_reset(char mode, const char *cmd);
 #endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/reset.c b/arch/arm/mach-mmp/reset.c
new file mode 100644
index 0000000..57fa65e
--- /dev/null
+++ b/arch/arm/mach-mmp/reset.c
@@ -0,0 +1,100 @@
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <mach/regs-mpmu.h>
+#include <mach/regs-timers.h>
+#include <mach/cputype.h>
+#include <linux/delay.h>
+
+#define REG_RTC_BR0     	(APB_VIRT_BASE + 0x010014)
+
+#define MPMU_APRR_CPR   	(1 << 0)
+#define MPMU_APRR_WDTR  	(1 << 4)
+#define MPMU_CPRR_DSPR  	(1 << 2)
+#define MPMU_CPRR_BBR   	(1 << 3)
+
+static void do_wdt_reset(const char *cmd)
+{
+	unsigned int reg, backup;
+	unsigned int watchdog_virt_base;
+	int i;
+	int match = 0, count = 0;
+
+	if (cpu_is_pxa910())
+		watchdog_virt_base = CP_TIMERS2_VIRT_BASE;
+	else if (cpu_is_pxa168())
+		watchdog_virt_base = TIMERS1_VIRT_BASE;
+	else if (cpu_is_mmp2())
+		watchdog_virt_base = MMP2_TIMERS2_VIRT_BASE;
+	else
+		return;
+
+	/* reset/enable WDT clock */
+	writel(0x7, MPMU_WDTPCR);
+	readl(MPMU_WDTPCR);
+	writel(0x3, MPMU_WDTPCR);
+	readl(MPMU_WDTPCR);
+
+	if (cpu_is_pxa910()) {
+		/* stores recovery flag into RTC register */
+		if (cmd && !strcmp(cmd, "recovery")) {
+			for (i = 0, backup = 0; i < 4; i++) {
+				backup <<= 8;
+				backup |= *(cmd + i);
+			}
+			do {
+				writel(backup, REG_RTC_BR0);
+			} while (readl(REG_RTC_BR0) != backup);
+		}
+	}
+
+	/* enable WDT reset */
+	writel(0xbaba, watchdog_virt_base + TMR_WFAR);
+	writel(0xeb10, watchdog_virt_base + TMR_WSAR);
+	writel(0x3, watchdog_virt_base + TMR_WMER);
+
+	if (cpu_is_pxa910()) {
+		/*hold CP first */
+		reg = readl(MPMU_APRR) | MPMU_APRR_CPR;
+		writel(reg, MPMU_APRR);
+		udelay(10);
+		/*CP reset MSA */
+		reg = readl(MPMU_CPRR) | MPMU_CPRR_DSPR | MPMU_CPRR_BBR;
+		writel(reg, MPMU_CPRR);
+		udelay(10);
+	}
+	/* negate hardware reset to the WDT after system reset */
+	reg = readl(MPMU_APRR) | MPMU_APRR_WDTR;
+	writel(reg, MPMU_APRR);
+
+	/* clear previous WDT status */
+	writel(0xbaba, watchdog_virt_base + TMR_WFAR);
+	writel(0xeb10, watchdog_virt_base + TMR_WSAR);
+	writel(0, watchdog_virt_base + TMR_WSR);
+
+	match = readl(watchdog_virt_base + TMR_WMR);
+	count = readl(watchdog_virt_base + TMR_WVR);
+
+	if (match - count > 0x20) {
+		/* set match counter */
+		writel(0xbaba, watchdog_virt_base + TMR_WFAR);
+		writel(0xeb10, watchdog_virt_base + TMR_WSAR);
+		writel(0x20 + count, watchdog_virt_base + TMR_WMR);
+	}
+}
+
+void arch_reset(char mode, const char *cmd)
+{
+	switch (mode) {
+	case 's':
+		/* Jump into ROM */
+		if (cpu_is_pxa168()) {
+			cpu_reset(0xffff0000);
+			break;
+		}
+	case 'w':
+	default:
+		do_wdt_reset(cmd);
+		break;
+	}
+}
-- 
1.5.6.5

[PATCH 5/7] ARM: pxa: align NR_BUILTIN_GPIO with GPIO interrupt number

[Haojian Zhuang]

Avoid to mismatch between NR_BUILTIN_GPIO and GPIO interrupt number

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-pxa/include/mach/gpio.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
index b024a8b..48ef925 100644
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -99,7 +99,7 @@
 #define GAFR(x)		GPIO_REG(0x54 + (((x) & 0x70) >> 2))
 
 
-#define NR_BUILTIN_GPIO 128
+#define NR_BUILTIN_GPIO		PXA_GPIO_IRQ_NUM
 
 #define gpio_to_bank(gpio)	((gpio) >> 5)
 #define gpio_to_irq(gpio)	IRQ_GPIO(gpio)
-- 
1.5.6.5

[PATCH 6/7] ARM: mmp: align NR_BUILTIN_GPIO with gpio interrupt number

[Haojian Zhuang]

Avoid to mismatch between NR_BUILTIN_GPIO and gpio interrupt number.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/include/mach/gpio.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
index ee8b02e..7bfb827 100644
--- a/arch/arm/mach-mmp/include/mach/gpio.h
+++ b/arch/arm/mach-mmp/include/mach/gpio.h
@@ -10,7 +10,7 @@
 #define BANK_OFF(n)	(((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 #define GPIO_REG(x)	(*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
 
-#define NR_BUILTIN_GPIO	(192)
+#define NR_BUILTIN_GPIO		IRQ_GPIO_NUM
 
 #define gpio_to_bank(gpio)	((gpio) >> 5)
 #define gpio_to_irq(gpio)	(IRQ_GPIO_START + (gpio))
-- 
1.5.6.5

[PATCH 7/7] ARM: mmp: enable max7312 gpio expander in dkb

[Haojian Zhuang]

Support max7312 gpio expander in TTC DKB.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
---
 arch/arm/mach-mmp/ttc_dkb.c |   31 ++++++++++++++++++++++++++++++-
 1 files changed, 30 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index e411039..8ca4a11 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -15,6 +15,8 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/onenand.h>
 #include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/i2c/pca953x.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -25,7 +27,17 @@
 
 #include "common.h"
 
-#define TTCDKB_NR_IRQS		(IRQ_BOARD_START + 24)
+#define TTCDKB_GPIO_EXT0(x)	(NR_BUILTIN_GPIO + ((x < 0) ? 0 :	\
+				((x < 16) ? x : 15)))
+#define TTCDKB_GPIO_EXT1(x)	(NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 :	\
+				((x < 16) ? x : 15)))
+
+/*
+ * 16 board interrupts -- MAX7312 GPIO expander
+ * 16 board interrupts -- PCA9575 GPIO expander
+ * 24 board interrupts -- 88PM860x PMIC
+ */
+#define TTCDKB_NR_IRQS		(IRQ_BOARD_START + 16 + 16 + 24)
 
 static unsigned long ttc_dkb_pin_config[] __initdata = {
 	/* UART2 */
@@ -113,6 +125,22 @@ static struct platform_device *ttc_dkb_devices[] = {
 	&ttc_dkb_device_onenand,
 };
 
+static struct pca953x_platform_data max7312_data[] = {
+	{
+		.gpio_base	= TTCDKB_GPIO_EXT0(0),
+		.irq_base	= IRQ_BOARD_START,
+	},
+};
+
+static struct i2c_board_info ttc_dkb_i2c_info[] = {
+	{
+		.type		= "max7312",
+		.addr		= 0x23,
+		.irq		= IRQ_GPIO(80),
+		.platform_data	= &max7312_data,
+	},
+};
+
 static void __init ttc_dkb_init(void)
 {
 	mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
@@ -121,6 +149,7 @@ static void __init ttc_dkb_init(void)
 	pxa910_add_uart(1);
 
 	/* off-chip devices */
+	pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
 	platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
 }
 
-- 
1.5.6.5

[PATCH 2/7] ARM: pxa: always clear LPM bits for PXA168 MFPR

[Eric Miao]

On Fri, Apr 8, 2011 at 8:15 PM, Haojian Zhuang
<haojian.zhuang@marvell.com> wrote:
> Bit[9:7] should always be zero in PXA168.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>

Applied to 'fix'.

> ---
> ?arch/arm/mach-mmp/include/mach/mfp-pxa168.h | ? ?9 +++++++++
> ?1 files changed, 9 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
> index 4621067..713be15 100644
> --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
> +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
> @@ -8,6 +8,15 @@
> ?#define MFP_DRIVE_MEDIUM ? ? ? (0x2 << 13)
> ?#define MFP_DRIVE_FAST ? ? ? ? (0x3 << 13)
>
> +#undef MFP_CFG
> +#undef MFP_CFG_DRV
> +
> +#define MFP_CFG(pin, af) ? ? ? ? ? ? ? \
> + ? ? ? (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
> +
> +#define MFP_CFG_DRV(pin, af, drv) ? ? ?\
> + ? ? ? (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
> +
> ?/* GPIO */
> ?#define GPIO0_GPIO ? ? ? ? ? ? MFP_CFG(GPIO0, AF5)
> ?#define GPIO1_GPIO ? ? ? ? ? ? MFP_CFG(GPIO1, AF5)
> --
> 1.5.6.5
>
>

[PATCH 5/7] ARM: pxa: align NR_BUILTIN_GPIO with GPIO interrupt number

[Eric Miao]

On Fri, Apr 8, 2011 at 8:15 PM, Haojian Zhuang
<haojian.zhuang@marvell.com> wrote:
> Avoid to mismatch between NR_BUILTIN_GPIO and GPIO interrupt number
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>

Applied to 'fix'.

> ---
> ?arch/arm/mach-pxa/include/mach/gpio.h | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
> index b024a8b..48ef925 100644
> --- a/arch/arm/mach-pxa/include/mach/gpio.h
> +++ b/arch/arm/mach-pxa/include/mach/gpio.h
> @@ -99,7 +99,7 @@
> ?#define GAFR(x) ? ? ? ? ? ? ? ?GPIO_REG(0x54 + (((x) & 0x70) >> 2))
>
>
> -#define NR_BUILTIN_GPIO 128
> +#define NR_BUILTIN_GPIO ? ? ? ? ? ? ? ?PXA_GPIO_IRQ_NUM
>
> ?#define gpio_to_bank(gpio) ? ? ((gpio) >> 5)
> ?#define gpio_to_irq(gpio) ? ? ?IRQ_GPIO(gpio)
> --
> 1.5.6.5
>
>

[PATCH 3/7] ARM: mmp: set correct uart according to board

[Russell King - ARM Linux]

On Fri, Apr 08, 2011 at 08:15:40PM +0800, Haojian Zhuang wrote:
> UART3 is the default console in jasper, brownstone and avengers lite.
> 
> Change-Id: Iacfe665cc0e20a47d50e0b2ad8724097f28e7d2c

Please don't include Change-Ids in patch submissions.

> diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
> index 7e2ebd3..b353785 100644
> --- a/arch/arm/mach-mmp/include/mach/debug-macro.S
> +++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
> @@ -14,8 +14,14 @@
>  		.macro	addruart, rp, rv
>  		ldr	\rp, =APB_PHYS_BASE		@ physical
>  		ldr	\rv, =APB_VIRT_BASE		@ virtual
> +#if defined(CONFIG_MACH_BROWNSTONE) || defined(CONFIG_MACH_MARVELL_JASPER) \
> +	|| defined(CONFIG_MACH_AVENGERS_LITE)
> +		orr	\rp, \rp, #0x00018000
> +		orr	\rv, \rv, #0x00018000
> +#else
>  		orr	\rp, \rp, #0x00017000
>  		orr	\rv, \rv, #0x00017000
> +#endif

It probably makes more sense to have this in the configuration scripts:

choice
	prompt "PXA debug uart"
	default DEBUG_PXA_UART0

config DEBUG_PXA_UART0
	bool "UART 0"

config DEBUG_PXA_UART1
	bool "UART 1"
	default y if MACH_BROWNSTONE || MACH_MARVELL_JASPER || MACH_AVENGERS_LITE

endchoice

and select the debug uart address using these symbols.  That'd avoid the
need to couple lots of platform specific stuff into the compiled files.

Alternatively, you could do more in the Kconfig like this:

config DEBUG_PXA_UART
	hex
	default 0x17000 if DEBUG_PXA_UART0
	default 0x18000 if DEBUG_PXA_UART1

and use CONFIG_DEBUG_PXA_UART in the assembly code, eliminating the
need to change sourcecode for additional uarts.  Or maybe combine the
two ideas.

[PATCH 3/7] ARM: mmp: set correct uart according to board

[Eric Miao]

On Wed, Apr 13, 2011 at 5:01 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Fri, Apr 08, 2011 at 08:15:40PM +0800, Haojian Zhuang wrote:
>> UART3 is the default console in jasper, brownstone and avengers lite.
>>
>> Change-Id: Iacfe665cc0e20a47d50e0b2ad8724097f28e7d2c
>
> Please don't include Change-Ids in patch submissions.
>
>> diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
>> index 7e2ebd3..b353785 100644
>> --- a/arch/arm/mach-mmp/include/mach/debug-macro.S
>> +++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
>> @@ -14,8 +14,14 @@
>> ? ? ? ? ? ? ? .macro ?addruart, rp, rv
>> ? ? ? ? ? ? ? ldr ? ? \rp, =APB_PHYS_BASE ? ? ? ? ? ? @ physical
>> ? ? ? ? ? ? ? ldr ? ? \rv, =APB_VIRT_BASE ? ? ? ? ? ? @ virtual
>> +#if defined(CONFIG_MACH_BROWNSTONE) || defined(CONFIG_MACH_MARVELL_JASPER) \
>> + ? ? || defined(CONFIG_MACH_AVENGERS_LITE)
>> + ? ? ? ? ? ? orr ? ? \rp, \rp, #0x00018000
>> + ? ? ? ? ? ? orr ? ? \rv, \rv, #0x00018000
>> +#else
>> ? ? ? ? ? ? ? orr ? ? \rp, \rp, #0x00017000
>> ? ? ? ? ? ? ? orr ? ? \rv, \rv, #0x00017000
>> +#endif
>
> It probably makes more sense to have this in the configuration scripts:
>
> choice
> ? ? ? ?prompt "PXA debug uart"
> ? ? ? ?default DEBUG_PXA_UART0
>
> config DEBUG_PXA_UART0
> ? ? ? ?bool "UART 0"
>
> config DEBUG_PXA_UART1
> ? ? ? ?bool "UART 1"
> ? ? ? ?default y if MACH_BROWNSTONE || MACH_MARVELL_JASPER || MACH_AVENGERS_LITE
>
> endchoice
>
> and select the debug uart address using these symbols. ?That'd avoid the
> need to couple lots of platform specific stuff into the compiled files.
>
> Alternatively, you could do more in the Kconfig like this:
>
> config DEBUG_PXA_UART
> ? ? ? ?hex
> ? ? ? ?default 0x17000 if DEBUG_PXA_UART0
> ? ? ? ?default 0x18000 if DEBUG_PXA_UART1
>
> and use CONFIG_DEBUG_PXA_UART in the assembly code, eliminating the
> need to change sourcecode for additional uarts. ?Or maybe combine the
> two ideas.
>

This looks much cleaner. I was actually thinking if it's necessary to make
this run-time determined, when multiple boards are all selected.

[PATCH 1/7] ARM: pxa: add clk_set_rate()

[Eric Miao]

On Fri, Apr 8, 2011 at 8:15 PM, Haojian Zhuang
<haojian.zhuang@marvell.com> wrote:
> Since there're mulitple clock rates in some device controllers, enable
> clk_set_rate() for this usage.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
> Acked-by: Eric Miao <eric.y.miao@gmail.com>

Applied.

> ---
> ?arch/arm/mach-mmp/clock.c | ? 15 +++++++++++++++
> ?arch/arm/mach-mmp/clock.h | ? ?1 +
> ?arch/arm/mach-pxa/clock.c | ? 15 +++++++++++++++
> ?arch/arm/mach-pxa/clock.h | ? ?1 +
> ?4 files changed, 32 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
> index 886e056..7c6f95f 100644
> --- a/arch/arm/mach-mmp/clock.c
> +++ b/arch/arm/mach-mmp/clock.c
> @@ -88,3 +88,18 @@ unsigned long clk_get_rate(struct clk *clk)
> ? ? ? ?return rate;
> ?}
> ?EXPORT_SYMBOL(clk_get_rate);
> +
> +int clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> + ? ? ? unsigned long flags;
> + ? ? ? int ret = -EINVAL;
> +
> + ? ? ? if (clk->ops->setrate) {
> + ? ? ? ? ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? ? ? ? ? ret = clk->ops->setrate(clk, rate);
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> + ? ? ? }
> +
> + ? ? ? return ret;
> +}
> +EXPORT_SYMBOL(clk_set_rate);
> diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
> index 9b027d7..3143e99 100644
> --- a/arch/arm/mach-mmp/clock.h
> +++ b/arch/arm/mach-mmp/clock.h
> @@ -12,6 +12,7 @@ struct clkops {
> ? ? ? ?void ? ? ? ? ? ? ? ? ? ?(*enable)(struct clk *);
> ? ? ? ?void ? ? ? ? ? ? ? ? ? ?(*disable)(struct clk *);
> ? ? ? ?unsigned long ? ? ? ? ? (*getrate)(struct clk *);
> + ? ? ? int ? ? ? ? ? ? ? ? ? ? (*setrate)(struct clk *, unsigned long);
> ?};
>
> ?struct clk {
> diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
> index d515222..4d46610 100644
> --- a/arch/arm/mach-pxa/clock.c
> +++ b/arch/arm/mach-pxa/clock.c
> @@ -53,6 +53,21 @@ unsigned long clk_get_rate(struct clk *clk)
> ?}
> ?EXPORT_SYMBOL(clk_get_rate);
>
> +int clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> + ? ? ? unsigned long flags;
> + ? ? ? int ret = -EINVAL;
> +
> + ? ? ? if (clk->ops->setrate) {
> + ? ? ? ? ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? ? ? ? ? ret = clk->ops->setrate(clk, rate);
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> + ? ? ? }
> +
> + ? ? ? return ret;
> +}
> +EXPORT_SYMBOL(clk_set_rate);
> +
> ?void clk_dummy_enable(struct clk *clk)
> ?{
> ?}
> diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
> index f9f349a..7373853 100644
> --- a/arch/arm/mach-pxa/clock.h
> +++ b/arch/arm/mach-pxa/clock.h
> @@ -5,6 +5,7 @@ struct clkops {
> ? ? ? ?void ? ? ? ? ? ? ? ? ? ?(*enable)(struct clk *);
> ? ? ? ?void ? ? ? ? ? ? ? ? ? ?(*disable)(struct clk *);
> ? ? ? ?unsigned long ? ? ? ? ? (*getrate)(struct clk *);
> + ? ? ? int ? ? ? ? ? ? ? ? ? ? (*setrate)(struct clk *, unsigned long);
> ?};
>
> ?struct clk {
> --
> 1.5.6.5
>
>