[PATCH 0/5] OMAP: DSS2: Add suppport for new color format

[PATCH 0/5] OMAP: DSS2: Add suppport for new color format

[Amber Jain]

This patch-set adds support for NV12 color format:
- Adds support for various new color formats supported by OMAP4.
- Corrects the fir_hinc and fir_vinc to have a non-zero value 
  as per TRM.
- Adds the support for NV12 along with the extra registers that needs to be
  configured for the same.
- Adds basic scaling support for the UV-plane in case of NV12 format.
- Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by
  Lajos Molnar <molnar@ti.com>.

Applies over:
http://gitorious.org/~amber/linux-omap-dss2/amber-omap-dss2/commits/master

Can be tested using v4l2 streaming over:
http://gitorious.org/~amber/linux-omap-dss2/amber-omap-dss2/commits/dss2-color-formats
This branch contains few private patches which enables v4l2 on OMAP4.

Amber Jain (5):
  OMAP: DSS2: Add new color formats
  OMAP: DSS2: configuring non-zero values for fir_hinc/fir_vinc
  OMAP: DSS2: Use for loop where ever possible in SR(), RR(), DUMPREG()
  OMAP: DSS2: Adds new registers for NV12 support
  OMAP: DSS2: Add support for NV12 format

 drivers/video/omap2/dss/dispc.c        |  740 +++++++++++++++++++++-----------
 drivers/video/omap2/dss/dispc.h        |  147 +++++++
 drivers/video/omap2/dss/dss.h          |    3 +-
 drivers/video/omap2/dss/dss_features.c |   36 ++-
 drivers/video/omap2/dss/dss_features.h |    2 +
 drivers/video/omap2/dss/manager.c      |   12 +-
 include/video/omapdss.h                |    6 +
 7 files changed, 681 insertions(+), 265 deletions(-)

[PATCH 1/5] OMAP: DSS2: Add new color formats

[Amber Jain]

Adds new color formats supported by OMAP4.

Signed-off-by: Amber Jain <amber@ti.com>
---
 drivers/video/omap2/dss/dispc.c        |  109 ++++++++++++++++++++++---------
 drivers/video/omap2/dss/dss_features.c |   33 +++++++++-
 drivers/video/omap2/dss/manager.c      |    7 ++
 include/video/omapdss.h                |    5 ++
 4 files changed, 121 insertions(+), 33 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 1a2d835..e680528 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -796,38 +796,78 @@ static void _dispc_set_color_mode(enum omap_plane plane,
 		enum omap_color_mode color_mode)
 {
 	u32 m = 0;
-
-	switch (color_mode) {
-	case OMAP_DSS_COLOR_CLUT1:
-		m = 0x0; break;
-	case OMAP_DSS_COLOR_CLUT2:
-		m = 0x1; break;
-	case OMAP_DSS_COLOR_CLUT4:
-		m = 0x2; break;
-	case OMAP_DSS_COLOR_CLUT8:
-		m = 0x3; break;
-	case OMAP_DSS_COLOR_RGB12U:
-		m = 0x4; break;
-	case OMAP_DSS_COLOR_ARGB16:
-		m = 0x5; break;
-	case OMAP_DSS_COLOR_RGB16:
-		m = 0x6; break;
-	case OMAP_DSS_COLOR_RGB24U:
-		m = 0x8; break;
-	case OMAP_DSS_COLOR_RGB24P:
-		m = 0x9; break;
-	case OMAP_DSS_COLOR_YUV2:
-		m = 0xa; break;
-	case OMAP_DSS_COLOR_UYVY:
-		m = 0xb; break;
-	case OMAP_DSS_COLOR_ARGB32:
-		m = 0xc; break;
-	case OMAP_DSS_COLOR_RGBA32:
-		m = 0xd; break;
-	case OMAP_DSS_COLOR_RGBX32:
-		m = 0xe; break;
-	default:
-		BUG(); break;
+	if (plane != OMAP_DSS_GFX) {
+		switch (color_mode) {
+		case OMAP_DSS_COLOR_NV12:
+			m = 0x0; break;
+		case OMAP_DSS_COLOR_RGB12U:
+			m = 0x1; break;
+		case OMAP_DSS_COLOR_RGBA16:
+			m = 0x2; break;
+		case OMAP_DSS_COLOR_RGBX16:
+			m = 0x4; break;
+		case OMAP_DSS_COLOR_ARGB16:
+			m = 0x5; break;
+		case OMAP_DSS_COLOR_RGB16:
+			m = 0x6; break;
+		case OMAP_DSS_COLOR_ARGB16_1555:
+			m = 0x7; break;
+		case OMAP_DSS_COLOR_RGB24U:
+			m = 0x8; break;
+		case OMAP_DSS_COLOR_RGB24P:
+			m = 0x9; break;
+		case OMAP_DSS_COLOR_YUV2:
+			m = 0xA; break;
+		case OMAP_DSS_COLOR_UYVY:
+			m = 0xB; break;
+		case OMAP_DSS_COLOR_ARGB32:
+			m = 0xC; break;
+		case OMAP_DSS_COLOR_RGBA32:
+			m = 0xD; break;
+		case OMAP_DSS_COLOR_RGBX32:
+			m = 0xE; break;
+		case OMAP_DSS_COLOR_XRGB16_1555:
+			m = 0xF; break;
+		default:
+			BUG(); break;
+		}
+	} else {
+		switch (color_mode) {
+		case OMAP_DSS_COLOR_CLUT1:
+			m = 0x0; break;
+		case OMAP_DSS_COLOR_CLUT2:
+			m = 0x1; break;
+		case OMAP_DSS_COLOR_CLUT4:
+			m = 0x2; break;
+		case OMAP_DSS_COLOR_CLUT8:
+			m = 0x3; break;
+		case OMAP_DSS_COLOR_RGB12U:
+			m = 0x4; break;
+		case OMAP_DSS_COLOR_ARGB16:
+			m = 0x5; break;
+		case OMAP_DSS_COLOR_RGB16:
+			m = 0x6; break;
+		case OMAP_DSS_COLOR_ARGB16_1555:
+			m = 0x7; break;
+		case OMAP_DSS_COLOR_RGB24U:
+			m = 0x8; break;
+		case OMAP_DSS_COLOR_RGB24P:
+			m = 0x9; break;
+		case OMAP_DSS_COLOR_YUV2:
+			m = 0xa; break;
+		case OMAP_DSS_COLOR_UYVY:
+			m = 0xb; break;
+		case OMAP_DSS_COLOR_ARGB32:
+			m = 0xc; break;
+		case OMAP_DSS_COLOR_RGBA32:
+			m = 0xd; break;
+		case OMAP_DSS_COLOR_RGBX32:
+			m = 0xe; break;
+		case OMAP_DSS_COLOR_XRGB16_1555:
+			m = 0xF; break;
+		default:
+			BUG(); break;
+		}
 	}
 
 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
@@ -1203,12 +1243,17 @@ static int color_mode_to_bpp(enum omap_color_mode color_mode)
 	case OMAP_DSS_COLOR_CLUT4:
 		return 4;
 	case OMAP_DSS_COLOR_CLUT8:
+	case OMAP_DSS_COLOR_NV12:
 		return 8;
 	case OMAP_DSS_COLOR_RGB12U:
 	case OMAP_DSS_COLOR_RGB16:
 	case OMAP_DSS_COLOR_ARGB16:
 	case OMAP_DSS_COLOR_YUV2:
 	case OMAP_DSS_COLOR_UYVY:
+	case OMAP_DSS_COLOR_RGBA16:
+	case OMAP_DSS_COLOR_RGBX16:
+	case OMAP_DSS_COLOR_ARGB16_1555:
+	case OMAP_DSS_COLOR_XRGB16_1555:
 		return 16;
 	case OMAP_DSS_COLOR_RGB24P:
 		return 24;
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index 5be5eb0..4c9a036 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -177,6 +177,37 @@ static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
 	OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 };
 
+static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
+	/* OMAP_DSS_GFX */
+	OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
+	OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
+	OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
+	OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
+	OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
+	OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
+	OMAP_DSS_COLOR_ARGB16_1555,
+
+	/* OMAP_DSS_VIDEO1 */
+	OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
+	OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
+	OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
+	OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
+	OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
+	OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
+	OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
+	OMAP_DSS_COLOR_RGBX32,
+
+       /* OMAP_DSS_VIDEO2 */
+	OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
+	OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
+	OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
+	OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
+	OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
+	OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
+	OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
+	OMAP_DSS_COLOR_RGBX32,
+};
+
 static const char * const omap2_dss_clk_source_names[] = {
 	[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]	= "N/A",
 	[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]	= "N/A",
@@ -299,7 +330,7 @@ static const struct omap_dss_features omap4_dss_features = {
 	.num_mgrs = 3,
 	.num_ovls = 3,
 	.supported_displays = omap4_dss_supported_displays,
-	.supported_color_modes = omap3_dss_supported_color_modes,
+	.supported_color_modes = omap4_dss_supported_color_modes,
 	.clksrc_names = omap4_dss_clk_source_names,
 	.dss_params = omap4_dss_param_range,
 };
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index ee38ca2..b40fe3d 100644
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -775,10 +775,17 @@ static int configure_overlay(enum omap_plane plane)
 		}
 
 		switch (c->color_mode) {
+		case OMAP_DSS_COLOR_NV12:
+			bpp = 8;
+			break;
 		case OMAP_DSS_COLOR_RGB16:
 		case OMAP_DSS_COLOR_ARGB16:
 		case OMAP_DSS_COLOR_YUV2:
 		case OMAP_DSS_COLOR_UYVY:
+		case OMAP_DSS_COLOR_RGBA16:
+		case OMAP_DSS_COLOR_RGBX16:
+		case OMAP_DSS_COLOR_ARGB16_1555:
+		case OMAP_DSS_COLOR_XRGB16_1555:
 			bpp = 16;
 			break;
 
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index b1b5ba5..7680c20 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -86,6 +86,11 @@ enum omap_color_mode {
 	OMAP_DSS_COLOR_ARGB32	= 1 << 11, /* ARGB32 */
 	OMAP_DSS_COLOR_RGBA32	= 1 << 12, /* RGBA32 */
 	OMAP_DSS_COLOR_RGBX32	= 1 << 13, /* RGBx32 */
+	OMAP_DSS_COLOR_NV12		= 1 << 14, /* NV12 format: YUV 4:2:0 */
+	OMAP_DSS_COLOR_RGBA16		= 1 << 15, /* RGBA16 - 4444 */
+	OMAP_DSS_COLOR_RGBX16		= 1 << 16, /* RGBx16 - 4444 */
+	OMAP_DSS_COLOR_ARGB16_1555	= 1 << 17, /* ARGB16 - 1555 */
+	OMAP_DSS_COLOR_XRGB16_1555	= 1 << 18, /* xRGB16 - 1555 */
 };
 
 enum omap_lcd_display_type {
-- 
1.7.1

[PATCH 2/5] OMAP: DSS2: configuring non-zero values for fir_hinc/fir_vinc

[Amber Jain]

fir_hinc and fir_vinc can only have a non-zero value as per TRM.
Hence removed the if...else condition and also made the necesary changes
caused as the result of the condition removal.

Signed-off-by: Amber Jain <amber@ti.com>
---
 drivers/video/omap2/dss/dispc.c |   15 ++++-----------
 1 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index e680528..92169bb 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -1128,15 +1128,8 @@ static void _dispc_set_scaling(enum omap_plane plane,
 
 	_dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
 
-	if (!orig_width || orig_width == out_width)
-		fir_hinc = 0;
-	else
-		fir_hinc = 1024 * orig_width / out_width;
-
-	if (!orig_height || orig_height == out_height)
-		fir_vinc = 0;
-	else
-		fir_vinc = 1024 * orig_height / out_height;
+	fir_hinc = 1024 * orig_width / out_width;
+	fir_vinc = 1024 * orig_height / out_height;
 
 	_dispc_set_fir(plane, fir_hinc, fir_vinc);
 
@@ -1144,8 +1137,8 @@ static void _dispc_set_scaling(enum omap_plane plane,
 
 	/* RESIZEENABLE and VERTICALTAPS */
 	l &= ~((0x3 << 5) | (0x1 << 21));
-	l |= fir_hinc ? (1 << 5) : 0;
-	l |= fir_vinc ? (1 << 6) : 0;
+	l |= (orig_width != out_width) ? (1 << 5) : 0;
+	l |= (orig_height != out_height) ? (1 << 6) : 0;
 	l |= five_taps ? (1 << 21) : 0;
 
 	/* VRESIZECONF and HRESIZECONF */
-- 
1.7.1

[PATCH 3/5] OMAP: DSS2: Use for loop where ever possible in SR(), RR(), DUMPREG()

[Amber Jain]

Use for loop instead of individual entries for OVL_FIR_COEF_H, OVL_FIR_COEF_HV,
OVL_FIR_COEF_V and OVL_CONV_COEF in SR(), RR() and DUMPREG() functions.

Signed-off-by: Amber Jain <amber@ti.com>
---
 drivers/video/omap2/dss/dispc.c |  257 +++++++++++----------------------------
 1 files changed, 70 insertions(+), 187 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 92169bb..19b0b50 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -129,6 +129,7 @@ static inline u32 dispc_read_reg(const u16 idx)
 
 void dispc_save_context(void)
 {
+	int i;
 	if (cpu_is_omap24xx())
 		return;
 
@@ -204,38 +205,17 @@ void dispc_save_context(void)
 	SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
 	SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
 
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
-
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
-
-	SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
-	SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
-	SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
-	SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
-	SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
-
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
+	for (i = 0; i < 8; i++)
+		SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
+
+	for (i = 0; i < 8; i++)
+		SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
+
+	for (i = 0; i < 5; i++)
+		SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
+
+	for (i = 0; i < 8; i++)
+		SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
 
 	SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
 
@@ -253,38 +233,17 @@ void dispc_save_context(void)
 	SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
 	SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
 
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
-	SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
-
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
-	SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
-
-	SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
-	SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
-	SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
-	SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
-	SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
-
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
-	SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
+	for (i = 0; i < 8; i++)
+		SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
+
+	for (i = 0; i < 8; i++)
+		SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
+
+	for (i = 0; i < 5; i++)
+		SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
+
+	for (i = 0; i < 8; i++)
+		SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
 
 	SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
 
@@ -294,6 +253,7 @@ void dispc_save_context(void)
 
 void dispc_restore_context(void)
 {
+	int i;
 	RR(SYSCONFIG);
 	/*RR(IRQENABLE);*/
 	/*RR(CONTROL);*/
@@ -366,38 +326,17 @@ void dispc_restore_context(void)
 	RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
 	RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
 
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
-
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
-
-	RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
-	RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
-	RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
-	RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
-	RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
-
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
+	for (i = 0; i < 8; i++)
+		RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
+
+	for (i = 0; i < 8; i++)
+		RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
+
+	for (i = 0; i < 5; i++)
+		RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
+
+	for (i = 0; i < 8; i++)
+		RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
 
 	RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
 
@@ -415,38 +354,17 @@ void dispc_restore_context(void)
 	RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
 	RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
 
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
-	RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
-
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
-	RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
-
-	RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
-	RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
-	RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
-	RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
-	RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
-
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
-	RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
+	for (i = 0; i < 8; i++)
+		RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
+
+	for (i = 0; i < 8; i++)
+		RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
+
+	for (i = 0; i < 5; i++)
+		RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
+
+	for (i = 0; i < 8; i++)
+		RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
 
 	RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
 
@@ -2454,6 +2372,7 @@ void dispc_dump_regs(struct seq_file *s)
 {
 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
 
+	int i;
 	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
 	DUMPREG(DISPC_REVISION);
@@ -2548,65 +2467,29 @@ void dispc_dump_regs(struct seq_file *s)
 	DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
 	DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
 
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
-	DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
-	DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
-	DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
-	DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
-	DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
-
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
-	DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
-	DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
-	DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
-	DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
-	DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
-	DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
-	DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
-	DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
+	for (i = 0; i < 8; i++)
+		DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
+
+	for (i = 0; i < 8; i++)
+		DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
+
+	for (i = 0; i < 5; i++)
+		DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
+
+	for (i = 0; i < 8; i++)
+		DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
+
+	for (i = 0; i < 8; i++)
+		DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
+
+	for (i = 0; i < 8; i++)
+		DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
+
+	for (i = 0; i < 5; i++)
+		DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
+
+	for (i = 0; i < 8; i++)
+		DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
 
 	DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
 	DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
-- 
1.7.1

[PATCH 4/5] OMAP: DSS2: Adds new registers for NV12 support

[Amber Jain]

Adds new register definitions and simple helper functions to configure them.
Added these new registers to save/restore and DUMPREG fumction.
Also adds two new features FEAT_HANDLE_UV_SEPARATE and FEAT_ATTR2.

Signed-off-by: Amber Jain <amber@ti.com>
---
 drivers/video/omap2/dss/dispc.c        |  160 ++++++++++++++++++++++++++++++++
 drivers/video/omap2/dss/dispc.h        |  147 +++++++++++++++++++++++++++++
 drivers/video/omap2/dss/dss_features.c |    2 +-
 drivers/video/omap2/dss/dss_features.h |    2 +
 4 files changed, 310 insertions(+), 1 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 19b0b50..48717a9 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -217,6 +217,25 @@ void dispc_save_context(void)
 	for (i = 0; i < 8; i++)
 		SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
 
+	if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+		SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
+		SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
+		SR(OVL_FIR2(OMAP_DSS_VIDEO1));
+		SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
+		SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
+
+		for (i = 0; i < 8; i++)
+			SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
+
+		for (i = 0; i < 8; i++)
+			SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
+
+		for (i = 0; i < 8; i++)
+			SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
+	}
+	if (dss_has_feature(FEAT_ATTR2))
+		SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
+
 	SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
 
 	/* VID2 */
@@ -245,6 +264,25 @@ void dispc_save_context(void)
 	for (i = 0; i < 8; i++)
 		SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
 
+	if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+		SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
+		SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
+		SR(OVL_FIR2(OMAP_DSS_VIDEO2));
+		SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
+		SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+
+		for (i = 0; i < 8; i++)
+			SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
+
+		for (i = 0; i < 8; i++)
+			SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
+
+		for (i = 0; i < 8; i++)
+			SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
+	}
+	if (dss_has_feature(FEAT_ATTR2))
+		SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
+
 	SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
 
 	if (dss_has_feature(FEAT_CORE_CLK_DIV))
@@ -338,6 +376,25 @@ void dispc_restore_context(void)
 	for (i = 0; i < 8; i++)
 		RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
 
+	if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+		RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
+		RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
+		RR(OVL_FIR2(OMAP_DSS_VIDEO1));
+		RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
+		RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
+
+		for (i = 0; i < 8; i++)
+			RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
+
+		for (i = 0; i < 8; i++)
+			RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
+
+		for (i = 0; i < 8; i++)
+			RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
+	}
+	if (dss_has_feature(FEAT_ATTR2))
+		RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
+
 	RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
 
 	/* VID2 */
@@ -366,6 +423,25 @@ void dispc_restore_context(void)
 	for (i = 0; i < 8; i++)
 		RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
 
+	if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+		RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
+		RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
+		RR(OVL_FIR2(OMAP_DSS_VIDEO2));
+		RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
+		RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+
+		for (i = 0; i < 8; i++)
+			RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
+
+		for (i = 0; i < 8; i++)
+			RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
+
+		for (i = 0; i < 8; i++)
+			RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
+	}
+	if (dss_has_feature(FEAT_ATTR2))
+		RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
+
 	RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
 
 	if (dss_has_feature(FEAT_CORE_CLK_DIV))
@@ -476,6 +552,27 @@ static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 	dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 }
 
+static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
+{
+	BUG_ON(plane == OMAP_DSS_GFX);
+
+	dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
+}
+
+static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
+{
+	BUG_ON(plane == OMAP_DSS_GFX);
+
+	dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
+}
+
+static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
+{
+	BUG_ON(plane == OMAP_DSS_GFX);
+
+	dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
+}
+
 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 		int vscaleup, int five_taps)
 {
@@ -645,6 +742,16 @@ static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 	dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 }
 
+static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
+{
+	dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
+}
+
+static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
+{
+	dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
+}
+
 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 {
 	u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
@@ -1025,6 +1132,21 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
 	dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
 }
 
+static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
+{
+	u32 val;
+
+	val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
+	dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
+}
+
+static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
+{
+	u32 val;
+
+	val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
+	dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
+}
 
 static void _dispc_set_scaling(enum omap_plane plane,
 		u16 orig_width, u16 orig_height,
@@ -2479,6 +2601,25 @@ void dispc_dump_regs(struct seq_file *s)
 	for (i = 0; i < 8; i++)
 		DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
 
+	if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+		DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO1));
+		DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO1));
+		DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO1));
+		DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO1));
+		DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO1));
+
+		for (i = 0; i < 8; i++)
+			DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
+
+		for (i = 0; i < 8; i++)
+			DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
+
+		for (i = 0; i < 8; i++)
+			DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
+	}
+	if (dss_has_feature(FEAT_ATTR2))
+		DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
+
 	for (i = 0; i < 8; i++)
 		DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
 
@@ -2491,6 +2632,25 @@ void dispc_dump_regs(struct seq_file *s)
 	for (i = 0; i < 8; i++)
 		DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
 
+	if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+		DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO2));
+		DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO2));
+		DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO2));
+		DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO2));
+		DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+
+		for (i = 0; i < 8; i++)
+			DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
+
+		for (i = 0; i < 8; i++)
+			DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
+
+		for (i = 0; i < 8; i++)
+			DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
+	}
+	if (dss_has_feature(FEAT_ATTR2))
+		DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
+
 	DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
 	DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
 
diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h
index d45f010..6c9ee0a 100644
--- a/drivers/video/omap2/dss/dispc.h
+++ b/drivers/video/omap2/dss/dispc.h
@@ -42,12 +42,18 @@
 					DISPC_BA0_OFFSET(n))
 #define DISPC_OVL_BA1(n)		(DISPC_OVL_BASE(n) + \
 					DISPC_BA1_OFFSET(n))
+#define DISPC_OVL_BA0_UV(n)		(DISPC_OVL_BASE(n) + \
+					DISPC_BA0_UV_OFFSET(n))
+#define DISPC_OVL_BA1_UV(n)		(DISPC_OVL_BASE(n) + \
+					DISPC_BA1_UV_OFFSET(n))
 #define DISPC_OVL_POSITION(n)		(DISPC_OVL_BASE(n) + \
 					DISPC_POS_OFFSET(n))
 #define DISPC_OVL_SIZE(n)		(DISPC_OVL_BASE(n) + \
 					DISPC_SIZE_OFFSET(n))
 #define DISPC_OVL_ATTRIBUTES(n)		(DISPC_OVL_BASE(n) + \
 					DISPC_ATTR_OFFSET(n))
+#define DISPC_OVL_ATTRIBUTES2(n)	(DISPC_OVL_BASE(n) + \
+					DISPC_ATTR2_OFFSET(n))
 #define DISPC_OVL_FIFO_THRESHOLD(n)	(DISPC_OVL_BASE(n) + \
 					DISPC_FIFO_THRESH_OFFSET(n))
 #define DISPC_OVL_FIFO_SIZE_STATUS(n)	(DISPC_OVL_BASE(n) + \
@@ -62,20 +68,32 @@
 					DISPC_TABLE_BA_OFFSET(n))
 #define DISPC_OVL_FIR(n)		(DISPC_OVL_BASE(n) + \
 					DISPC_FIR_OFFSET(n))
+#define DISPC_OVL_FIR2(n)		(DISPC_OVL_BASE(n) + \
+					DISPC_FIR2_OFFSET(n))
 #define DISPC_OVL_PICTURE_SIZE(n)	(DISPC_OVL_BASE(n) + \
 					DISPC_PIC_SIZE_OFFSET(n))
 #define DISPC_OVL_ACCU0(n)		(DISPC_OVL_BASE(n) + \
 					DISPC_ACCU0_OFFSET(n))
 #define DISPC_OVL_ACCU1(n)		(DISPC_OVL_BASE(n) + \
 					DISPC_ACCU1_OFFSET(n))
+#define DISPC_OVL_ACCU2_0(n)		(DISPC_OVL_BASE(n) + \
+					DISPC_ACCU2_0_OFFSET(n))
+#define DISPC_OVL_ACCU2_1(n)		(DISPC_OVL_BASE(n) + \
+					DISPC_ACCU2_1_OFFSET(n))
 #define DISPC_OVL_FIR_COEF_H(n, i)	(DISPC_OVL_BASE(n) + \
 					DISPC_FIR_COEF_H_OFFSET(n, i))
 #define DISPC_OVL_FIR_COEF_HV(n, i)	(DISPC_OVL_BASE(n) + \
 					DISPC_FIR_COEF_HV_OFFSET(n, i))
+#define DISPC_OVL_FIR_COEF_H2(n, i)	(DISPC_OVL_BASE(n) + \
+					DISPC_FIR_COEF_H2_OFFSET(n, i))
+#define DISPC_OVL_FIR_COEF_HV2(n, i)	(DISPC_OVL_BASE(n) + \
+					DISPC_FIR_COEF_HV2_OFFSET(n, i))
 #define DISPC_OVL_CONV_COEF(n, i)	(DISPC_OVL_BASE(n) + \
 					DISPC_CONV_COEF_OFFSET(n, i))
 #define DISPC_OVL_FIR_COEF_V(n, i)	(DISPC_OVL_BASE(n) + \
 					DISPC_FIR_COEF_V_OFFSET(n, i))
+#define DISPC_OVL_FIR_COEF_V2(n, i)	(DISPC_OVL_BASE(n) + \
+					DISPC_FIR_COEF_V2_OFFSET(n, i))
 #define DISPC_OVL_PRELOAD(n)		(DISPC_OVL_BASE(n) + \
 					DISPC_PRELOAD_OFFSET(n))
 
@@ -303,6 +321,34 @@ static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
 	}
 }
 
+static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
+{
+	switch (plane) {
+	case OMAP_DSS_GFX:
+		BUG();
+	case OMAP_DSS_VIDEO1:
+		return 0x0544;
+	case OMAP_DSS_VIDEO2:
+		return 0x04BC;
+	default:
+		BUG();
+	}
+}
+
+static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
+{
+	switch (plane) {
+	case OMAP_DSS_GFX:
+		BUG();
+	case OMAP_DSS_VIDEO1:
+		return 0x0548;
+	case OMAP_DSS_VIDEO2:
+		return 0x04C0;
+	default:
+		BUG();
+	}
+}
+
 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
 {
 	switch (plane) {
@@ -340,6 +386,20 @@ static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
 	}
 }
 
+static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
+{
+	switch (plane) {
+	case OMAP_DSS_GFX:
+		BUG();
+	case OMAP_DSS_VIDEO1:
+		return 0x0568;
+	case OMAP_DSS_VIDEO2:
+		return 0x04DC;
+	default:
+		BUG();
+	}
+}
+
 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
 {
 	switch (plane) {
@@ -431,6 +491,20 @@ static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
 	}
 }
 
+static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
+{
+	switch (plane) {
+	case OMAP_DSS_GFX:
+		BUG();
+	case OMAP_DSS_VIDEO1:
+		return 0x0580;
+	case OMAP_DSS_VIDEO2:
+		return 0x055C;
+	default:
+		BUG();
+	}
+}
+
 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
 {
 	switch (plane) {
@@ -458,6 +532,20 @@ static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
 	}
 }
 
+static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
+{
+	switch (plane) {
+	case OMAP_DSS_GFX:
+		BUG();
+	case OMAP_DSS_VIDEO1:
+		return 0x0584;
+	case OMAP_DSS_VIDEO2:
+		return 0x0560;
+	default:
+		BUG();
+	}
+}
+
 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 {
 	switch (plane) {
@@ -471,6 +559,20 @@ static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 	}
 }
 
+static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
+{
+	switch (plane) {
+	case OMAP_DSS_GFX:
+		BUG();
+	case OMAP_DSS_VIDEO1:
+		return 0x0588;
+	case OMAP_DSS_VIDEO2:
+		return 0x0564;
+	default:
+		BUG();
+	}
+}
+
 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 {
@@ -486,6 +588,21 @@ static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 }
 
 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
+{
+	switch (plane) {
+	case OMAP_DSS_GFX:
+		BUG();
+	case OMAP_DSS_VIDEO1:
+		return 0x058C + i * 0x8;
+	case OMAP_DSS_VIDEO2:
+		return 0x0568 + i * 0x8;
+	default:
+		BUG();
+	}
+}
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 {
 	switch (plane) {
@@ -499,6 +616,21 @@ static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 	}
 }
 
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
+{
+	switch (plane) {
+	case OMAP_DSS_GFX:
+		BUG();
+	case OMAP_DSS_VIDEO1:
+		return 0x0590 + i * 8;
+	case OMAP_DSS_VIDEO2:
+		return 0x056C + i * 0x8;
+	default:
+		BUG();
+	}
+}
+
 /* coef index i = {0, 1, 2, 3, 4,} */
 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
 {
@@ -528,6 +660,21 @@ static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
 	}
 }
 
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
+{
+	switch (plane) {
+	case OMAP_DSS_GFX:
+		BUG();
+	case OMAP_DSS_VIDEO1:
+		return 0x05CC + i * 0x4;
+	case OMAP_DSS_VIDEO2:
+		return 0x05A8 + i * 0x4;
+	default:
+		BUG();
+	}
+}
+
 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
 {
 	switch (plane) {
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index 915f700..8e37d6a 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -326,7 +326,7 @@ static const struct omap_dss_features omap4_dss_features = {
 		FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
 		FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
 		FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
-		FEAT_DSI_GNQ,
+		FEAT_DSI_GNQ | FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2,
 
 	.num_mgrs = 3,
 	.num_ovls = 3,
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index ff2cf33..895b390 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -48,6 +48,8 @@ enum dss_feat_id {
 	FEAT_DSI_VC_OCP_WIDTH		= 1 << 16,
 	FEAT_DSI_REVERSE_TXCLKESC	= 1 << 17,
 	FEAT_DSI_GNQ			= 1 << 18,
+	FEAT_HANDLE_UV_SEPARATE		= 1 << 18,
+	FEAT_ATTR2			= 1 << 19,
 };
 
 /* DSS register field id */
-- 
1.7.1

[PATCH 5/5] OMAP: DSS2: Add support for NV12 format

[Amber Jain]

Adds the support for NV12 color format.
Added basic scaling support for the UV-plane in case of NV12 format.

Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by
Lajos Molnar <molnar@ti.com>

Signed-off-by: Amber Jain <amber@ti.com>
---
 drivers/video/omap2/dss/dispc.c   |  201 +++++++++++++++++++++++++++++++------
 drivers/video/omap2/dss/dss.h     |    3 +-
 drivers/video/omap2/dss/manager.c |    5 +-
 include/video/omapdss.h           |    1 +
 4 files changed, 176 insertions(+), 34 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 48717a9..1928e3e 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -110,6 +110,18 @@ static struct {
 #endif
 } dispc;
 
+enum omap_color_component {
+	/* used for all color formats for OMAP3 and earlier
+	 * and for RGB and Y color component on OMAP4
+	 */
+	DISPC_COLOR_COMPONENT_RGB_Y		= 1 << 0,
+	/* used for UV component for
+	 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
+	 * color formats on OMAP4
+	 */
+	DISPC_COLOR_COMPONENT_UV		= 1 << 1,
+};
+
 static void _omap_dispc_set_irqs(void);
 
 static inline void dispc_write_reg(const u16 idx, u32 val)
@@ -574,7 +586,8 @@ static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 }
 
 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
-		int vscaleup, int five_taps)
+				  int vscaleup, int five_taps,
+				  enum omap_color_component color_comp)
 {
 	/* Coefficients for horizontal up-sampling */
 	static const struct dispc_h_coef coef_hup[8] = {
@@ -672,8 +685,14 @@ static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 			| FLD_VAL(v_coef[i].vc1, 23, 16)
 			| FLD_VAL(v_coef[i].vc2, 31, 24);
 
-		_dispc_write_firh_reg(plane, i, h);
-		_dispc_write_firhv_reg(plane, i, hv);
+		if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
+			_dispc_write_firh_reg(plane, i, h);
+			_dispc_write_firhv_reg(plane, i, hv);
+		} else {
+			_dispc_write_firh2_reg(plane, i, h);
+			_dispc_write_firhv2_reg(plane, i, hv);
+		}
+
 	}
 
 	if (five_taps) {
@@ -681,7 +700,10 @@ static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 			u32 v;
 			v = FLD_VAL(v_coef[i].vc00, 7, 0)
 				| FLD_VAL(v_coef[i].vc22, 15, 8);
-			_dispc_write_firv_reg(plane, i, v);
+			if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
+				_dispc_write_firv_reg(plane, i, v);
+			else
+				_dispc_write_firv2_reg(plane, i, v);
 		}
 	}
 }
@@ -1090,18 +1112,27 @@ void dispc_enable_fifomerge(bool enable)
 	enable_clocks(0);
 }
 
-static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
+static void _dispc_set_fir(enum omap_plane plane,
+				int hinc, int vinc,
+				enum omap_color_component color_comp)
 {
 	u32 val;
-	u8 hinc_start, hinc_end, vinc_start, vinc_end;
 
-	dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
-	dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
+	if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
+		u8 hinc_start, hinc_end, vinc_start, vinc_end;
 
-	val = FLD_VAL(vinc, vinc_start, vinc_end) |
-			FLD_VAL(hinc, hinc_start, hinc_end);
+		dss_feat_get_reg_field(FEAT_REG_FIRHINC,
+					&hinc_start, &hinc_end);
+		dss_feat_get_reg_field(FEAT_REG_FIRVINC,
+					&vinc_start, &vinc_end);
+		val = FLD_VAL(vinc, vinc_start, vinc_end) |
+				FLD_VAL(hinc, hinc_start, hinc_end);
 
-	dispc_write_reg(DISPC_OVL_FIR(plane), val);
+		dispc_write_reg(DISPC_OVL_FIR(plane), val);
+	} else {
+		val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
+		dispc_write_reg(DISPC_OVL_FIR2(plane), val);
+	}
 }
 
 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
@@ -1148,31 +1179,40 @@ static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
 	dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
 }
 
-static void _dispc_set_scaling(enum omap_plane plane,
+static void _dispc_set_scale_param(enum omap_plane plane,
 		u16 orig_width, u16 orig_height,
 		u16 out_width, u16 out_height,
-		bool ilace, bool five_taps,
-		bool fieldmode)
+		bool five_taps, u8 rotation,
+		enum omap_color_component color_comp)
 {
-	int fir_hinc;
-	int fir_vinc;
+	int fir_hinc, fir_vinc;
 	int hscaleup, vscaleup;
-	int accu0 = 0;
-	int accu1 = 0;
-	u32 l;
-
-	BUG_ON(plane == OMAP_DSS_GFX);
 
 	hscaleup = orig_width <= out_width;
 	vscaleup = orig_height <= out_height;
 
-	_dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
+	_dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps, color_comp);
 
 	fir_hinc = 1024 * orig_width / out_width;
 	fir_vinc = 1024 * orig_height / out_height;
 
-	_dispc_set_fir(plane, fir_hinc, fir_vinc);
+	_dispc_set_fir(plane, fir_hinc, fir_vinc, color_comp);
+}
+
+static void _dispc_set_scaling_common(enum omap_plane plane,
+		u16 orig_width, u16 orig_height,
+		u16 out_width, u16 out_height,
+		bool ilace, bool five_taps,
+		bool fieldmode, enum omap_color_mode color_mode,
+		u8 rotation)
+{
+	int accu0 = 0;
+	int accu1 = 0;
+	u32 l;
 
+	_dispc_set_scale_param(plane, orig_width, orig_height,
+				out_width, out_height, five_taps,
+				rotation, DISPC_COLOR_COMPONENT_RGB_Y);
 	l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 
 	/* RESIZEENABLE and VERTICALTAPS */
@@ -1184,8 +1224,8 @@ static void _dispc_set_scaling(enum omap_plane plane,
 	/* VRESIZECONF and HRESIZECONF */
 	if (dss_has_feature(FEAT_RESIZECONF)) {
 		l &= ~(0x3 << 7);
-		l |= hscaleup ? 0 : (1 << 7);
-		l |= vscaleup ? 0 : (1 << 8);
+		l |= (orig_width <= out_width) ? 0 : (1 << 7);
+		l |= (orig_height <= out_height) ? 0 : (1 << 8);
 	}
 
 	/* LINEBUFFERSPLIT */
@@ -1202,7 +1242,7 @@ static void _dispc_set_scaling(enum omap_plane plane,
 	 */
 	if (ilace && !fieldmode) {
 		accu1 = 0;
-		accu0 = (fir_vinc / 2) & 0x3ff;
+		accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
 		if (accu0 >= 1024/2) {
 			accu1 = 1024/2;
 			accu0 -= accu1;
@@ -1213,6 +1253,93 @@ static void _dispc_set_scaling(enum omap_plane plane,
 	_dispc_set_vid_accu1(plane, 0, accu1);
 }
 
+static void _dispc_set_scaling_uv(enum omap_plane plane,
+		u16 orig_width, u16 orig_height,
+		u16 out_width, u16 out_height,
+		bool ilace, bool five_taps,
+		bool fieldmode, enum omap_color_mode color_mode,
+		u8 rotation)
+{
+	int scale_x = out_width != orig_width;
+	int scale_y = out_height != orig_height;
+
+	if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
+		return;
+	if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
+			color_mode != OMAP_DSS_COLOR_UYVY &&
+			color_mode != OMAP_DSS_COLOR_NV12)) {
+		/* reset chroma resampling for RGB formats  */
+		REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
+		return;
+	}
+	switch (color_mode) {
+	case OMAP_DSS_COLOR_NV12:
+		/* UV is subsampled by 2 vertically*/
+		orig_height >>= 1;
+		/* UV is subsampled by 2 horz.*/
+		orig_width >>= 1;
+		break;
+	case OMAP_DSS_COLOR_YUV2:
+	case OMAP_DSS_COLOR_UYVY:
+		/*For YUV422 with 90/270 rotation,
+		 *we don't upsample chroma
+		 */
+		if (rotation == OMAP_DSS_ROT_0 ||
+			rotation == OMAP_DSS_ROT_180)
+			/* UV is subsampled by 2 hrz*/
+			orig_width >>= 1;
+		/* must use FIR for YUV422 if rotated */
+		if (rotation != OMAP_DSS_ROT_0)
+			scale_x = scale_y = true;
+		break;
+	default:
+		BUG();
+	}
+
+	if (out_width != orig_width)
+		scale_x = true;
+	if (out_height != orig_height)
+		scale_y = true;
+
+	_dispc_set_scale_param(plane, orig_width, orig_height,
+			out_width, out_height, five_taps,
+				rotation, DISPC_COLOR_COMPONENT_UV);
+
+	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
+		(scale_x || scale_y) ? 1 : 0, 8, 8);
+	/* set H scaling */
+	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
+	/* set V scaling */
+	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
+
+	_dispc_set_vid_accu2_0(plane, 0x80, 0);
+	_dispc_set_vid_accu2_1(plane, 0x80, 0);
+}
+
+static void _dispc_set_scaling(enum omap_plane plane,
+		u16 orig_width, u16 orig_height,
+		u16 out_width, u16 out_height,
+		bool ilace, bool five_taps,
+		bool fieldmode, enum omap_color_mode color_mode,
+		u8 rotation)
+{
+	BUG_ON(plane == OMAP_DSS_GFX);
+
+	_dispc_set_scaling_common(plane,
+			orig_width, orig_height,
+			out_width, out_height,
+			ilace, five_taps,
+			fieldmode, color_mode,
+			rotation);
+
+	_dispc_set_scaling_uv(plane,
+		orig_width, orig_height,
+		out_width, out_height,
+		ilace, five_taps,
+		fieldmode, color_mode,
+		rotation);
+}
+
 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
 		bool mirroring, enum omap_color_mode color_mode)
 {
@@ -1619,7 +1746,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
 		enum omap_dss_rotation_type rotation_type,
 		u8 rotation, int mirror,
 		u8 global_alpha, u8 pre_mult_alpha,
-		enum omap_channel channel)
+		enum omap_channel channel, u32 puv_addr)
 {
 	const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
 	bool five_taps = 0;
@@ -1668,7 +1795,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
 			return -EINVAL;
 
 		if (color_mode == OMAP_DSS_COLOR_YUV2 ||
-			color_mode == OMAP_DSS_COLOR_UYVY)
+			color_mode == OMAP_DSS_COLOR_UYVY ||
+			color_mode == OMAP_DSS_COLOR_NV12)
 			cconv = 1;
 
 		/* Must use 5-tap filter? */
@@ -1742,6 +1870,12 @@ static int _dispc_setup_plane(enum omap_plane plane,
 	_dispc_set_plane_ba0(plane, paddr + offset0);
 	_dispc_set_plane_ba1(plane, paddr + offset1);
 
+	if (OMAP_DSS_COLOR_NV12 == color_mode) {
+		_dispc_set_plane_ba0_uv(plane, puv_addr + offset0);
+		_dispc_set_plane_ba1_uv(plane, puv_addr + offset1);
+	}
+
+
 	_dispc_set_row_inc(plane, row_inc);
 	_dispc_set_pix_inc(plane, pix_inc);
 
@@ -1755,7 +1889,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
 	if (plane != OMAP_DSS_GFX) {
 		_dispc_set_scaling(plane, width, height,
 				   out_width, out_height,
-				   ilace, five_taps, fieldmode);
+				   ilace, five_taps, fieldmode,
+				   color_mode, rotation);
 		_dispc_set_vid_size(plane, out_width, out_height);
 		_dispc_set_vid_color_conv(plane, cconv);
 	}
@@ -3367,11 +3502,12 @@ int dispc_setup_plane(enum omap_plane plane,
 		       bool ilace,
 		       enum omap_dss_rotation_type rotation_type,
 		       u8 rotation, bool mirror, u8 global_alpha,
-		       u8 pre_mult_alpha, enum omap_channel channel)
+		       u8 pre_mult_alpha, enum omap_channel channel,
+		       u32 puv_addr)
 {
 	int r = 0;
 
-	DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
+	DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d, %d, %dx%d -> "
 	       "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
 	       plane, paddr, screen_width, pos_x, pos_y,
 	       width, height,
@@ -3390,7 +3526,8 @@ int dispc_setup_plane(enum omap_plane plane,
 			   rotation_type,
 			   rotation, mirror,
 			   global_alpha,
-			   pre_mult_alpha, channel);
+			   pre_mult_alpha,
+			   channel, puv_addr);
 
 	enable_clocks(0);
 
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 6386f6b..8ab6d43 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -421,7 +421,8 @@ int dispc_setup_plane(enum omap_plane plane,
 		      enum omap_dss_rotation_type rotation_type,
 		      u8 rotation, bool mirror,
 		      u8 global_alpha, u8 pre_mult_alpha,
-		      enum omap_channel channel);
+		      enum omap_channel channel,
+		      u32 puv_addr);
 
 bool dispc_go_busy(enum omap_channel channel);
 void dispc_go(enum omap_channel channel);
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index b40fe3d..9aeea50 100644
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -393,6 +393,7 @@ struct overlay_cache_data {
 
 	u32 paddr;
 	void __iomem *vaddr;
+	u32 p_uv_addr; /* relevant for NV12 format only */
 	u16 screen_width;
 	u16 width;
 	u16 height;
@@ -861,7 +862,8 @@ static int configure_overlay(enum omap_plane plane)
 			c->mirror,
 			c->global_alpha,
 			c->pre_mult_alpha,
-			c->channel);
+			c->channel,
+			c->p_uv_addr);
 
 	if (r) {
 		/* this shouldn't happen */
@@ -1276,6 +1278,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
 
 		oc->paddr = ovl->info.paddr;
 		oc->vaddr = ovl->info.vaddr;
+		oc->p_uv_addr = ovl->info.p_uv_addr;
 		oc->screen_width = ovl->info.screen_width;
 		oc->width = ovl->info.width;
 		oc->height = ovl->info.height;
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 7680c20..2670e55 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -305,6 +305,7 @@ struct omap_overlay_info {
 
 	u32 paddr;
 	void __iomem *vaddr;
+	u32 p_uv_addr;  /* for NV12 format */
 	u16 screen_width;
 	u16 width;
 	u16 height;
-- 
1.7.1

Re: [PATCH 1/5] OMAP: DSS2: Add new color formats

[Tomi Valkeinen]

On Thu, 2011-05-19 at 11:01 +0530, Amber Jain wrote:
> Adds new color formats supported by OMAP4.

It wouldn't hurt to be a bit more descriptive. What new color formats?
Do all of them work after this patch (NV12 doesn't, I presume)? Anything
else worth mentioning? Also the subject should mention OMAP4.

> Signed-off-by: Amber Jain <amber@ti.com>
> ---
>  drivers/video/omap2/dss/dispc.c        |  109 ++++++++++++++++++++++---------
>  drivers/video/omap2/dss/dss_features.c |   33 +++++++++-
>  drivers/video/omap2/dss/manager.c      |    7 ++
>  include/video/omapdss.h                |    5 ++
>  4 files changed, 121 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
> index 1a2d835..e680528 100644
> --- a/drivers/video/omap2/dss/dispc.c
> +++ b/drivers/video/omap2/dss/dispc.c
> @@ -796,38 +796,78 @@ static void _dispc_set_color_mode(enum omap_plane plane,
>  		enum omap_color_mode color_mode)
>  {
>  	u32 m = 0;
> -
> -	switch (color_mode) {
> -	case OMAP_DSS_COLOR_CLUT1:
> -		m = 0x0; break;
> -	case OMAP_DSS_COLOR_CLUT2:
> -		m = 0x1; break;
> -	case OMAP_DSS_COLOR_CLUT4:
> -		m = 0x2; break;
> -	case OMAP_DSS_COLOR_CLUT8:
> -		m = 0x3; break;
> -	case OMAP_DSS_COLOR_RGB12U:
> -		m = 0x4; break;
> -	case OMAP_DSS_COLOR_ARGB16:
> -		m = 0x5; break;
> -	case OMAP_DSS_COLOR_RGB16:
> -		m = 0x6; break;
> -	case OMAP_DSS_COLOR_RGB24U:
> -		m = 0x8; break;
> -	case OMAP_DSS_COLOR_RGB24P:
> -		m = 0x9; break;
> -	case OMAP_DSS_COLOR_YUV2:
> -		m = 0xa; break;
> -	case OMAP_DSS_COLOR_UYVY:
> -		m = 0xb; break;
> -	case OMAP_DSS_COLOR_ARGB32:
> -		m = 0xc; break;
> -	case OMAP_DSS_COLOR_RGBA32:
> -		m = 0xd; break;
> -	case OMAP_DSS_COLOR_RGBX32:
> -		m = 0xe; break;
> -	default:
> -		BUG(); break;
> +	if (plane != OMAP_DSS_GFX) {
> +		switch (color_mode) {
> +		case OMAP_DSS_COLOR_NV12:
> +			m = 0x0; break;
> +		case OMAP_DSS_COLOR_RGB12U:
> +			m = 0x1; break;
> +		case OMAP_DSS_COLOR_RGBA16:
> +			m = 0x2; break;
> +		case OMAP_DSS_COLOR_RGBX16:
> +			m = 0x4; break;
> +		case OMAP_DSS_COLOR_ARGB16:
> +			m = 0x5; break;
> +		case OMAP_DSS_COLOR_RGB16:
> +			m = 0x6; break;
> +		case OMAP_DSS_COLOR_ARGB16_1555:
> +			m = 0x7; break;
> +		case OMAP_DSS_COLOR_RGB24U:
> +			m = 0x8; break;
> +		case OMAP_DSS_COLOR_RGB24P:
> +			m = 0x9; break;
> +		case OMAP_DSS_COLOR_YUV2:
> +			m = 0xA; break;
> +		case OMAP_DSS_COLOR_UYVY:
> +			m = 0xB; break;
> +		case OMAP_DSS_COLOR_ARGB32:
> +			m = 0xC; break;
> +		case OMAP_DSS_COLOR_RGBA32:
> +			m = 0xD; break;
> +		case OMAP_DSS_COLOR_RGBX32:
> +			m = 0xE; break;
> +		case OMAP_DSS_COLOR_XRGB16_1555:
> +			m = 0xF; break;
> +		default:
> +			BUG(); break;
> +		}
> +	} else {
> +		switch (color_mode) {
> +		case OMAP_DSS_COLOR_CLUT1:
> +			m = 0x0; break;
> +		case OMAP_DSS_COLOR_CLUT2:
> +			m = 0x1; break;
> +		case OMAP_DSS_COLOR_CLUT4:
> +			m = 0x2; break;
> +		case OMAP_DSS_COLOR_CLUT8:
> +			m = 0x3; break;
> +		case OMAP_DSS_COLOR_RGB12U:
> +			m = 0x4; break;
> +		case OMAP_DSS_COLOR_ARGB16:
> +			m = 0x5; break;
> +		case OMAP_DSS_COLOR_RGB16:
> +			m = 0x6; break;
> +		case OMAP_DSS_COLOR_ARGB16_1555:
> +			m = 0x7; break;
> +		case OMAP_DSS_COLOR_RGB24U:
> +			m = 0x8; break;
> +		case OMAP_DSS_COLOR_RGB24P:
> +			m = 0x9; break;
> +		case OMAP_DSS_COLOR_YUV2:
> +			m = 0xa; break;
> +		case OMAP_DSS_COLOR_UYVY:
> +			m = 0xb; break;
> +		case OMAP_DSS_COLOR_ARGB32:
> +			m = 0xc; break;
> +		case OMAP_DSS_COLOR_RGBA32:
> +			m = 0xd; break;
> +		case OMAP_DSS_COLOR_RGBX32:
> +			m = 0xe; break;
> +		case OMAP_DSS_COLOR_XRGB16_1555:
> +			m = 0xF; break;
> +		default:
> +			BUG(); break;
> +		}

You are using sometimes capital and sometimes non-capital letters with
hex numbers. Pick either one (pick non-capital =), and use it all
around.

>  	}
>  
>  	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
> @@ -1203,12 +1243,17 @@ static int color_mode_to_bpp(enum omap_color_mode color_mode)
>  	case OMAP_DSS_COLOR_CLUT4:
>  		return 4;
>  	case OMAP_DSS_COLOR_CLUT8:
> +	case OMAP_DSS_COLOR_NV12:
>  		return 8;
>  	case OMAP_DSS_COLOR_RGB12U:
>  	case OMAP_DSS_COLOR_RGB16:
>  	case OMAP_DSS_COLOR_ARGB16:
>  	case OMAP_DSS_COLOR_YUV2:
>  	case OMAP_DSS_COLOR_UYVY:
> +	case OMAP_DSS_COLOR_RGBA16:
> +	case OMAP_DSS_COLOR_RGBX16:
> +	case OMAP_DSS_COLOR_ARGB16_1555:
> +	case OMAP_DSS_COLOR_XRGB16_1555:
>  		return 16;
>  	case OMAP_DSS_COLOR_RGB24P:
>  		return 24;
> diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
> index 5be5eb0..4c9a036 100644
> --- a/drivers/video/omap2/dss/dss_features.c
> +++ b/drivers/video/omap2/dss/dss_features.c
> @@ -177,6 +177,37 @@ static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
>  	OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
>  };
>  
> +static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
> +	/* OMAP_DSS_GFX */
> +	OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
> +	OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
> +	OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
> +	OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
> +	OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
> +	OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
> +	OMAP_DSS_COLOR_ARGB16_1555,
> +
> +	/* OMAP_DSS_VIDEO1 */
> +	OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
> +	OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
> +	OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
> +	OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
> +	OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
> +	OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
> +	OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
> +	OMAP_DSS_COLOR_RGBX32,
> +
> +       /* OMAP_DSS_VIDEO2 */
> +	OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
> +	OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
> +	OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
> +	OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
> +	OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
> +	OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
> +	OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
> +	OMAP_DSS_COLOR_RGBX32,
> +};
> +
>  static const char * const omap2_dss_clk_source_names[] = {
>  	[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]	= "N/A",
>  	[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]	= "N/A",
> @@ -299,7 +330,7 @@ static const struct omap_dss_features omap4_dss_features = {
>  	.num_mgrs = 3,
>  	.num_ovls = 3,
>  	.supported_displays = omap4_dss_supported_displays,
> -	.supported_color_modes = omap3_dss_supported_color_modes,
> +	.supported_color_modes = omap4_dss_supported_color_modes,

I just applied Ricardo's patches which splits omap4 features to es1 and
non-es1. So when you make changes, please rebase and check that out.

 Tomi

Re: [PATCH 2/5] OMAP: DSS2: configuring non-zero values for fir_hinc/fir_vinc

[Tomi Valkeinen]

On Thu, 2011-05-19 at 11:01 +0530, Amber Jain wrote:
> fir_hinc and fir_vinc can only have a non-zero value as per TRM.
> Hence removed the if...else condition and also made the necesary changes

Typo with necessary.

> caused as the result of the condition removal.

Here also a bit more description would help to understand the patch.

If the patch is not totally trivial, I think it's normally good to
provide at least two distinct parts in the description, which are
something like:
- The current state, and what's wrong with it
- What this patch does and why it fixes the thing

So here you should tell something like:
- FIR values can not have zero values as per TRM, and the current code
writes zero there when no scaling is used. However, when zero values are
written to FIR registers scaling is disabled, so it shouldn't cause any
problems, but it's still safer to fix it.
- The patch changes to code to write a calculated FIR value even when no
scaling is used (meaning FIR value of 1024), but the scaling enable bits
are still kept off if scaling is not needed.

Also, if it's not obvious, it's nice to mention if the patch should
change some functionality or not. In this case nothing should change.

And generally try not to refer to the code in a way that requires the
reviewer to read the patch before understanding the description, like
"Hence removed the if...else condition and also made the necesary
changes caused as the result of the condition removal". The sentence
doesn't make sense if you don't read the patch first, which is totally
not the point of the description.

Either say something like "removed the if..else condition used to do
this and that, which cause this and that, requiring changing that and
this", which may get a bit confusing. Usually it's better to speak in
higher level terms about what the patch does (not always, though),
something similar to what I wrote in the paragraph someway up there.

 Tomi

Re: [PATCH 4/5] OMAP: DSS2: Adds new registers for NV12 support

[Tomi Valkeinen]

On Thu, 2011-05-19 at 11:01 +0530, Amber Jain wrote:
> Adds new register definitions and simple helper functions to configure them.

Remember that the subject and the description are separate things. Even
if you mention NV12 in the subject, the description also should be
"whole" and mention NV12, as the line above doesn't really say anything
what kind of registers are being added. And this is not only about NV12,
it's also about the new scaling config thingie for the old YUV modes.

And it wouldn't hurt to tell a bit more about the registers, as their
use is not very clear. The reader should of course look at the TRM to
get full understanding of the subject, but it would be good to briefly
explain the UV plane registers and how it affects things.

> Added these new registers to save/restore and DUMPREG fumction.
> Also adds two new features FEAT_HANDLE_UV_SEPARATE and FEAT_ATTR2.

What do the features do and on what platforms are they enabled?

 Tomi

Re: [PATCH 5/5] OMAP: DSS2: Add support for NV12 format

[Tomi Valkeinen]

On Thu, 2011-05-19 at 11:01 +0530, Amber Jain wrote:
> Adds the support for NV12 color format.
> Added basic scaling support for the UV-plane in case of NV12 format.

This is the most complex part of the patch set, do you feel the lines
above explain what the patch is about? What about this patch affecting
the old YUV modes? The scaler being enabled always for YUV modes on
OMAP4? Any other areas the patch could affect? Things like that should
be mentioned here.

 Tomi