* [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms
@ 2011-05-19 21:18 Thomas Abraham
2011-05-19 21:18 ` [PATCH 1/7] ARM: SAMSUNG: Add clkdev infrastructure Thomas Abraham
` (7 more replies)
0 siblings, 8 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-19 21:18 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim
Thomas Abraham (7):
ARM: SAMSUNG: Add clkdev infrastructure
ARM: S3C24XX: Add clkdev support
ARM: S3C64XX: Add clkdev support
ARM: S5P64X0: Add clkdev support
ARM: S5PC100: Add clkdev support
ARM: S5PV210: Add clkdev support
ARM: Exynos4: Add clkdev support
arch/arm/Kconfig | 6 ++
arch/arm/mach-exynos4/clock.c | 63 +++++++++++++++++++-
arch/arm/mach-exynos4/include/mach/clkdev.h | 7 ++
arch/arm/mach-exynos4/time.c | 2 +
arch/arm/mach-s3c2412/clock.c | 3 +
arch/arm/mach-s3c2416/clock.c | 5 ++
arch/arm/mach-s3c2443/clock.c | 4 +
arch/arm/mach-s3c64xx/clock.c | 25 ++++++++
arch/arm/mach-s3c64xx/include/mach/clkdev.h | 7 ++
arch/arm/mach-s5p64x0/clock-s5p6440.c | 20 +++++++
arch/arm/mach-s5p64x0/clock-s5p6450.c | 19 ++++++
arch/arm/mach-s5p64x0/include/mach/clkdev.h | 7 ++
arch/arm/mach-s5pc100/clock.c | 42 +++++++++++++-
arch/arm/mach-s5pc100/include/mach/clkdev.h | 7 ++
arch/arm/mach-s5pv210/clock.c | 42 +++++++++++++-
arch/arm/mach-s5pv210/include/mach/clkdev.h | 7 ++
arch/arm/plat-s3c24xx/include/mach/clkdev.h | 7 ++
arch/arm/plat-s3c24xx/s3c2410-clock.c | 3 +
arch/arm/plat-s3c24xx/s3c2443-clock.c | 4 +
arch/arm/plat-s5p/s5p-time.c | 9 +++
arch/arm/plat-samsung/clock.c | 83 ++-------------------------
arch/arm/plat-samsung/include/plat/clock.h | 3 +
arch/arm/plat-samsung/pwm-clock.c | 10 +++
arch/arm/plat-samsung/time.c | 2 +
24 files changed, 303 insertions(+), 84 deletions(-)
create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
create mode 100644 arch/arm/mach-s3c64xx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-s5p64x0/include/mach/clkdev.h
create mode 100644 arch/arm/mach-s5pc100/include/mach/clkdev.h
create mode 100644 arch/arm/mach-s5pv210/include/mach/clkdev.h
create mode 100644 arch/arm/plat-s3c24xx/include/mach/clkdev.h
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/7] ARM: SAMSUNG: Add clkdev infrastructure
2011-05-19 21:18 [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Thomas Abraham
@ 2011-05-19 21:18 ` Thomas Abraham
2011-05-19 21:18 ` [PATCH 2/7] ARM: S3C24XX: Add clkdev support Thomas Abraham
` (6 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-19 21:18 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim
The struct clk definition for Samsung platforms is extended to include
a instance of struct clk_lookup and a device name. When clocks are
registered using s3c24xx_register_clock function, the dev_id, con_id
and clk members are initialized with information from the struct clk
instance and struct clk_lookup member is registered.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/plat-samsung/clock.c | 83 ++--------------------------
arch/arm/plat-samsung/include/plat/clock.h | 3 +
2 files changed, 8 insertions(+), 78 deletions(-)
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 7728928..6956fed 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -71,74 +71,6 @@ static int clk_null_enable(struct clk *clk, int enable)
return 0;
}
-static int dev_is_s3c_uart(struct device *dev)
-{
- struct platform_device **pdev = s3c24xx_uart_devs;
- int i;
- for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
- if (*pdev && dev == &(*pdev)->dev)
- return 1;
- return 0;
-}
-
-/*
- * Serial drivers call get_clock() very early, before platform bus
- * has been set up, this requires a special check to let them get
- * a proper clock
- */
-
-static int dev_is_platform_device(struct device *dev)
-{
- return dev->bus == &platform_bus_type ||
- (dev->bus == NULL && dev_is_s3c_uart(dev));
-}
-
-/* Clock API calls */
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
- struct clk *p;
- struct clk *clk = ERR_PTR(-ENOENT);
- int idno;
-
- if (dev == NULL || !dev_is_platform_device(dev))
- idno = -1;
- else
- idno = to_platform_device(dev)->id;
-
- spin_lock(&clocks_lock);
-
- list_for_each_entry(p, &clocks, list) {
- if (p->id == idno &&
- strcmp(id, p->name) == 0 &&
- try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
-
- /* check for the case where a device was supplied, but the
- * clock that was being searched for is not device specific */
-
- if (IS_ERR(clk)) {
- list_for_each_entry(p, &clocks, list) {
- if (p->id == -1 && strcmp(id, p->name) == 0 &&
- try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
- }
-
- spin_unlock(&clocks_lock);
- return clk;
-}
-
-void clk_put(struct clk *clk)
-{
- module_put(clk->owner);
-}
-
int clk_enable(struct clk *clk)
{
if (IS_ERR(clk) || clk == NULL)
@@ -241,8 +173,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
return ret;
}
-EXPORT_SYMBOL(clk_get);
-EXPORT_SYMBOL(clk_put);
EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
@@ -346,14 +276,11 @@ int s3c24xx_register_clock(struct clk *clk)
if (clk->enable == NULL)
clk->enable = clk_null_enable;
- /* add to the list of available clocks */
-
- /* Quick check to see if this clock has already been registered. */
- BUG_ON(clk->list.prev != clk->list.next);
-
- spin_lock(&clocks_lock);
- list_add(&clk->list, &clocks);
- spin_unlock(&clocks_lock);
+ /* fill up the clk_lookup structure and register it*/
+ clk->lookup.dev_id = clk->devname;
+ clk->lookup.con_id = clk->name;
+ clk->lookup.clk = clk;
+ clkdev_add(&clk->lookup);
return 0;
}
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 983c578..87d5b38 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -10,6 +10,7 @@
*/
#include <linux/spinlock.h>
+#include <linux/clkdev.h>
struct clk;
@@ -40,6 +41,7 @@ struct clk {
struct module *owner;
struct clk *parent;
const char *name;
+ const char *devname;
int id;
int usage;
unsigned long rate;
@@ -47,6 +49,7 @@ struct clk {
struct clk_ops *ops;
int (*enable)(struct clk *, int enable);
+ struct clk_lookup lookup;
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
struct dentry *dent; /* For visible tree hierarchy */
#endif
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/7] ARM: S3C24XX: Add clkdev support
2011-05-19 21:18 [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Thomas Abraham
2011-05-19 21:18 ` [PATCH 1/7] ARM: SAMSUNG: Add clkdev infrastructure Thomas Abraham
@ 2011-05-19 21:18 ` Thomas Abraham
2011-05-19 21:18 ` [PATCH 3/7] ARM: S3C64XX: " Thomas Abraham
` (5 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-19 21:18 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim
Add clkdev support for Samsung's s3c24xx platforms.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s3c2412/clock.c | 3 +++
arch/arm/mach-s3c2416/clock.c | 5 +++++
arch/arm/mach-s3c2443/clock.c | 4 ++++
arch/arm/plat-s3c24xx/include/mach/clkdev.h | 7 +++++++
arch/arm/plat-s3c24xx/s3c2410-clock.c | 3 +++
arch/arm/plat-s3c24xx/s3c2443-clock.c | 4 ++++
arch/arm/plat-samsung/pwm-clock.c | 10 ++++++++++
arch/arm/plat-samsung/time.c | 2 ++
9 files changed, 39 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-s3c24xx/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 377a7a5..225f63a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -686,6 +686,7 @@ config ARCH_S3C2410
select GENERIC_GPIO
select ARCH_HAS_CPUFREQ
select HAVE_CLK
+ select CLKDEV_LOOKUP
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C if I2C
help
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 0c0505b..aff4ee9 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -557,18 +557,21 @@ static struct clk init_clocks[] = {
.ctrlbit = S3C2412_CLKCON_PWMT,
}, {
.name = "uart",
+ .devname = "s3c2412-uart.0",
.id = 0,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART0,
}, {
.name = "uart",
+ .devname = "s3c2412-uart.1",
.id = 1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART1,
}, {
.name = "uart",
+ .devname = "s3c2412-uart.2",
.id = 2,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 3b02d85..60b98a9 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -42,6 +42,7 @@ static struct clksrc_clk hsmmc_div[] = {
[0] = {
.clk = {
.name = "hsmmc-div",
+ .devname = "s3c-sdhci.0",
.id = 0,
.parent = &clk_esysclk.clk,
},
@@ -50,6 +51,7 @@ static struct clksrc_clk hsmmc_div[] = {
[1] = {
.clk = {
.name = "hsmmc-div",
+ .devname = "s3c-sdhci.1",
.id = 1,
.parent = &clk_esysclk.clk,
},
@@ -62,6 +64,7 @@ static struct clksrc_clk hsmmc_mux[] = {
.clk = {
.id = 0,
.name = "hsmmc-if",
+ .devname = "s3c-sdhci.0",
.ctrlbit = (1 << 6),
.enable = s3c2443_clkcon_enable_s,
},
@@ -78,6 +81,7 @@ static struct clksrc_clk hsmmc_mux[] = {
.clk = {
.id = 1,
.name = "hsmmc-if",
+ .devname = "s3c-sdhci.1",
.ctrlbit = (1 << 12),
.enable = s3c2443_clkcon_enable_s,
},
@@ -94,6 +98,7 @@ static struct clksrc_clk hsmmc_mux[] = {
static struct clk hsmmc0_clk = {
.name = "hsmmc",
+ .devname = "s3c-sdhci.0",
.id = 0,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index f4ec6d5..3486955 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -196,6 +196,7 @@ static struct clksrc_clk clk_hsspi = {
static struct clksrc_clk clk_hsmmc_div = {
.clk = {
.name = "hsmmc-div",
+ .devname = "s3c-sdhci.1",
.id = 1,
.parent = &clk_esysclk.clk,
},
@@ -231,6 +232,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
static struct clk clk_hsmmc = {
.name = "hsmmc-if",
+ .devname = "s3c-sdhci.1",
.id = 1,
.parent = &clk_hsmmc_div.clk,
.enable = s3c2443_enable_hsmmc,
@@ -300,12 +302,14 @@ static struct clk init_clocks_off[] = {
.ctrlbit = S3C2443_PCLKCON_IIS,
}, {
.name = "spi",
+ .devname = "s3c2410-spi.0",
.id = 0,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI0,
}, {
.name = "spi",
+ .devname = "s3c2410-spi.1",
.id = 1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
new file mode 100644
index 0000000..1247f5e
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_EXYNOS4_CLKDEV_H__
+#define __MACH_EXYNOS4_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index 9ecc5d9..b84dea0 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -160,18 +160,21 @@ static struct clk init_clocks[] = {
.ctrlbit = S3C2410_CLKCON_PWMT,
}, {
.name = "uart",
+ .devname = "s3c2410-uart.0",
.id = 0,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART0,
}, {
.name = "uart",
+ .devname = "s3c2410-uart.1",
.id = 1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART1,
}, {
.name = "uart",
+ .devname = "s3c2410-uart.2",
.id = 2,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 82f2d4a..818781e 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -320,24 +320,28 @@ static struct clk init_clocks[] = {
.ctrlbit = S3C2443_HCLKCON_SSMC,
}, {
.name = "uart",
+ .devname = "s3c2440-uart.0",
.id = 0,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART0,
}, {
.name = "uart",
+ .devname = "s3c2440-uart.1",
.id = 1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART1,
}, {
.name = "uart",
+ .devname = "s3c2440-uart.2",
.id = 2,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART2,
}, {
.name = "uart",
+ .devname = "s3c2440-uart.3",
.id = 3,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
index 46c9381..f1bba88 100644
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[0] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.0",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[0],
},
@@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[1] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.1",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[0],
}
@@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[2] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.2",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[3] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.3",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[4] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.4",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = {
static struct clk clk_tin[] = {
[0] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.0",
.id = 0,
.ops = &clk_tin_ops,
},
[1] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.1",
.id = 1,
.ops = &clk_tin_ops,
},
[2] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.2",
.id = 2,
.ops = &clk_tin_ops,
},
[3] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.3",
.id = 3,
.ops = &clk_tin_ops,
},
[4] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.4",
.id = 4,
.ops = &clk_tin_ops,
},
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 2231d80..e3bb806 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void)
clk_enable(timerclk);
if (!use_tclk1_12()) {
+ tmpdev.id = 4;
+ tmpdev.dev.init_name = "s3c24xx-pwm.4";
tin = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin))
panic("failed to get pwm-tin clock for system timer");
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/7] ARM: S3C64XX: Add clkdev support
2011-05-19 21:18 [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Thomas Abraham
2011-05-19 21:18 ` [PATCH 1/7] ARM: SAMSUNG: Add clkdev infrastructure Thomas Abraham
2011-05-19 21:18 ` [PATCH 2/7] ARM: S3C24XX: Add clkdev support Thomas Abraham
@ 2011-05-19 21:18 ` Thomas Abraham
2011-05-19 21:18 ` [PATCH 4/7] ARM: S5P64X0: " Thomas Abraham
` (4 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-19 21:18 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim
Add clkdev support for Samsung's s3c64xx platforms.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s3c64xx/clock.c | 25 +++++++++++++++++++++++++
arch/arm/mach-s3c64xx/include/mach/clkdev.h | 7 +++++++
3 files changed, 33 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-s3c64xx/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 225f63a..e0a62fe 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -704,6 +704,7 @@ config ARCH_S3C64XX
select CPU_V6
select ARM_VIC
select HAVE_CLK
+ select CLKDEV_LOOKUP
select NO_IOPORT
select ARCH_USES_GETTIMEOFFSET
select ARCH_HAS_CPUFREQ
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index fdfc4d5..3b6fb54 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -152,18 +152,21 @@ static struct clk init_clocks_off[] = {
.ctrlbit = S3C_CLKCON_PCLK_IIC,
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.1",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
}, {
.name = "iis",
+ .devname = "samsung-i2s.0",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0,
}, {
.name = "iis",
+ .devname = "samsung-i2s.1",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
@@ -184,42 +187,49 @@ static struct clk init_clocks_off[] = {
.ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
.name = "spi_48m",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
}, {
.name = "spi_48m",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
}, {
.name = "48m",
+ .devname = "s3c-sdhci.0",
.id = 0,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
}, {
.name = "48m",
+ .devname = "s3c-sdhci.1",
.id = 1,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
}, {
.name = "48m",
+ .devname = "s3c-sdhci.2",
.id = 2,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
@@ -260,18 +270,21 @@ static struct clk init_clocks[] = {
.ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.0",
.id = 0,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.1",
.id = 1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.2",
.id = 2,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
@@ -290,24 +303,28 @@ static struct clk init_clocks[] = {
.ctrlbit = S3C_CLKCON_PCLK_PWM,
}, {
.name = "uart",
+ .devname = "s3c6400-uart.0",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART0,
}, {
.name = "uart",
+ .devname = "s3c6400-uart.1",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART1,
}, {
.name = "uart",
+ .devname = "s3c6400-uart.2",
.id = 2,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART2,
}, {
.name = "uart",
+ .devname = "s3c6400-uart.3",
.id = 3,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
@@ -610,6 +627,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "mmc_bus",
+ .devname = "s3c-sdhci.0",
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl,
@@ -620,6 +638,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "mmc_bus",
+ .devname = "s3c-sdhci.1",
.id = 1,
.ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl,
@@ -630,6 +649,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "mmc_bus",
+ .devname = "s3c-sdhci.2",
.id = 2,
.ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl,
@@ -661,6 +681,7 @@ static struct clksrc_clk clksrcs[] = {
/* Where does UCLK0 come from? */
.clk = {
.name = "spi-bus",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
@@ -671,6 +692,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "spi-bus",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl,
@@ -681,6 +703,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
+ .devname = "samsung-i2s.0",
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
@@ -691,6 +714,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
+ .devname = "samsung-i2s.1",
.id = 1,
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
@@ -701,6 +725,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
+ .devname = "samsung-i2s.2",
.id = 2,
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl,
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
new file mode 100644
index 0000000..1247f5e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_EXYNOS4_CLKDEV_H__
+#define __MACH_EXYNOS4_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/7] ARM: S5P64X0: Add clkdev support
2011-05-19 21:18 [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Thomas Abraham
` (2 preceding siblings ...)
2011-05-19 21:18 ` [PATCH 3/7] ARM: S3C64XX: " Thomas Abraham
@ 2011-05-19 21:18 ` Thomas Abraham
2011-05-25 21:45 ` Kukjin Kim
2011-05-19 21:18 ` [PATCH 5/7] ARM: S5PC100: " Thomas Abraham
` (3 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Thomas Abraham @ 2011-05-19 21:18 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim
Add clkdev support for Samsung's s5p64x0 platforms.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s5p64x0/clock-s5p6440.c | 20 ++++++++++++++++++++
arch/arm/mach-s5p64x0/clock-s5p6450.c | 19 +++++++++++++++++++
arch/arm/mach-s5p64x0/include/mach/clkdev.h | 7 +++++++
arch/arm/plat-s5p/s5p-time.c | 9 +++++++++
5 files changed, 56 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-s5p64x0/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e0a62fe..33ad464 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -729,6 +729,7 @@ config ARCH_S5P64X0
select CPU_V6
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 9f12c2e..8e77738 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -160,18 +160,21 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
+ .devname = "sdhci-s3c.0",
.id = 0,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
+ .devname = "sdhci-s3c.1",
.id = 1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
+ .devname = "sdhci-s3c.2",
.id = 2,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
@@ -244,12 +247,14 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 17),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
@@ -262,6 +267,7 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 25),
}, {
.name = "iis",
+ .devname = "samsung-i2s.0",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
@@ -292,30 +298,35 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 31),
}, {
.name = "sclk_spi_48",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "sclk_spi_48",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 23),
}, {
.name = "mmc_48m",
+ .devname = "sdhci-s3c.0",
.id = 0,
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "mmc_48m",
+ .devname = "sdhci-s3c.1",
.id = 1,
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "mmc_48m",
+ .devname = "sdhci-s3c.2",
.id = 2,
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
@@ -341,24 +352,28 @@ static struct clk init_clocks[] = {
.ctrlbit = (1 << 21),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.0",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.1",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.2",
.id = 2,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.3",
.id = 3,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
@@ -420,6 +435,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.0",
.id = 0,
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
@@ -430,6 +446,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.1",
.id = 1,
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
@@ -440,6 +457,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.2",
.id = 2,
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
@@ -460,6 +478,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
@@ -470,6 +489,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 4eec457..bd8adb7 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -196,18 +196,21 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
+ .devname = "sdhci-s3c.0",
.id = 0,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
+ .devname = "sdhci-s3c.1",
.id = 1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
+ .devname = "sdhci-s3c.2",
.id = 2,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
@@ -244,42 +247,49 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.0",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "iis",
+ .devname = "samsung-i2s.0",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "iis",
+ .devname = "samsung-i2s.1",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "iis",
+ .devname = "samsung-i2s.2",
.id = 2,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.1",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
@@ -311,24 +321,28 @@ static struct clk init_clocks[] = {
.ctrlbit = (1 << 21),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.0",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.1",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.2",
.id = 2,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.3",
.id = 3,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
@@ -435,6 +449,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.0",
.id = 0,
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
@@ -445,6 +460,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.1",
.id = 1,
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
@@ -455,6 +471,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.2",
.id = 2,
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
@@ -475,6 +492,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
@@ -485,6 +503,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
new file mode 100644
index 0000000..1247f5e
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_EXYNOS4_CLKDEV_H__
+#define __MACH_EXYNOS4_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index 8090403..d9efd29 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -408,6 +408,7 @@ static void __init s5p_timer_resources(void)
unsigned long event_id = timer_source.event_id;
unsigned long source_id = timer_source.source_id;
+ char devname[15];
timerclk = clk_get(NULL, "timers");
if (IS_ERR(timerclk))
@@ -415,6 +416,10 @@ static void __init s5p_timer_resources(void)
clk_enable(timerclk);
+ sprintf(devname, "s3c24xx-pwm.%lu", event_id);
+ s3c_device_timer[event_id].id = event_id;
+ s3c_device_timer[event_id].dev.init_name = devname;
+
tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
if (IS_ERR(tin_event))
panic("failed to get pwm-tin clock for event timer");
@@ -425,6 +430,10 @@ static void __init s5p_timer_resources(void)
clk_enable(tin_event);
+ sprintf(devname, "s3c24xx-pwm.%lu", source_id);
+ s3c_device_timer[source_id].id = source_id;
+ s3c_device_timer[source_id].dev.init_name = devname;
+
tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
if (IS_ERR(tin_source))
panic("failed to get pwm-tin clock for source timer");
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 5/7] ARM: S5PC100: Add clkdev support
2011-05-19 21:18 [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Thomas Abraham
` (3 preceding siblings ...)
2011-05-19 21:18 ` [PATCH 4/7] ARM: S5P64X0: " Thomas Abraham
@ 2011-05-19 21:18 ` Thomas Abraham
2011-05-25 21:42 ` Kukjin Kim
2011-05-19 21:18 ` [PATCH 6/7] ARM: S5PV210: " Thomas Abraham
` (2 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Thomas Abraham @ 2011-05-19 21:18 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim
Add clkdev support for Samsung's s5pc100 platforms.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s5pc100/clock.c | 42 ++++++++++++++++++++++++++-
arch/arm/mach-s5pc100/include/mach/clkdev.h | 7 ++++
3 files changed, 49 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-s5pc100/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 33ad464..b329ee4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -753,6 +753,7 @@ config ARCH_S5PC100
bool "Samsung S5PC100"
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select ARCH_USES_GETTIMEOFFSET
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 0305e9b..2cad06c 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -453,18 +453,21 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 1),
}, {
.name = "hsmmc",
+ .devname = "sdhci-s3c.2",
.id = 2,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
+ .devname = "sdhci-s3c.1",
.id = 1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
+ .devname = "sdhci-s3c.0",
.id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
@@ -489,12 +492,14 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 2),
}, {
.name = "pdma",
+ .devname = "s3c-pl330.1",
.id = 1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "pdma",
+ .devname = "s3c-pl330.0",
.id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
@@ -513,18 +518,21 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
+ .devname = "s5p-fimc.0",
.id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
+ .devname = "s5p-fimc.1",
.id = 1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimc",
+ .devname = "s5p-fimc.2",
.id = 2,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
@@ -549,7 +557,7 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 7),
}, {
.name = "g3d",
- .id = 0,
+ .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 8),
@@ -615,30 +623,35 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.0",
.id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.1",
.id = 1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.2",
.id = 2,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
@@ -675,18 +688,21 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 13),
}, {
.name = "iis",
+ .devname = "samsung-i2s.0",
.id = 0,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "iis",
+ .devname = "samsung-i2s.1",
.id = 1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "iis",
+ .devname = "samsung-i2s.2",
.id = 2,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
@@ -699,12 +715,14 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 3),
}, {
.name = "pcm",
+ .devname = "samsung-pcm.0",
.id = 0,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "pcm",
+ .devname = "samsung-pcm.1",
.id = 1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
@@ -729,36 +747,42 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 8),
}, {
.name = "spi_48m",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi_48m",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "spi_48m",
+ .devname = "s3c64xx-spi.2",
.id = 2,
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "mmc_48m",
+ .devname = "sdhci-s3c.0",
.id = 0,
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "mmc_48m",
+ .devname = "sdhci-s3c.1",
.id = 1,
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "mmc_48m",
+ .devname = "sdhci-s3c.2",
.id = 2,
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
@@ -836,6 +860,7 @@ struct clksrc_sources clk_src_group3 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "sclk_audio",
+ .devname = "samsung-pcm.0",
.id = 0,
.ctrlbit = (1 << 8),
.enable = s5pc100_sclk1_ctrl,
@@ -862,6 +887,7 @@ struct clksrc_sources clk_src_group4 = {
static struct clksrc_clk clk_sclk_audio1 = {
.clk = {
.name = "sclk_audio",
+ .devname = "samsung-pcm.1",
.id = 1,
.ctrlbit = (1 << 9),
.enable = s5pc100_sclk1_ctrl,
@@ -887,6 +913,7 @@ struct clksrc_sources clk_src_group5 = {
static struct clksrc_clk clk_sclk_audio2 = {
.clk = {
.name = "sclk_audio",
+ .devname = "samsung-pcm.2",
.id = 2,
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk1_ctrl,
@@ -1027,6 +1054,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.ctrlbit = (1 << 4),
.enable = s5pc100_sclk0_ctrl,
@@ -1038,6 +1066,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.ctrlbit = (1 << 5),
.enable = s5pc100_sclk0_ctrl,
@@ -1049,6 +1078,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.2",
.id = 2,
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
@@ -1092,6 +1122,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "s5p-fimc.0",
.id = 0,
.ctrlbit = (1 << 1),
.enable = s5pc100_sclk1_ctrl,
@@ -1103,6 +1134,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "s5p-fimc.1",
.id = 1,
.ctrlbit = (1 << 2),
.enable = s5pc100_sclk1_ctrl,
@@ -1114,6 +1146,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "s5p-fimc.2",
.id = 2,
.ctrlbit = (1 << 3),
.enable = s5pc100_sclk1_ctrl,
@@ -1125,6 +1158,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.0",
.id = 0,
.ctrlbit = (1 << 12),
.enable = s5pc100_sclk1_ctrl,
@@ -1136,6 +1170,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.1",
.id = 1,
.ctrlbit = (1 << 13),
.enable = s5pc100_sclk1_ctrl,
@@ -1147,6 +1182,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.2",
.id = 2,
.ctrlbit = (1 << 14),
.enable = s5pc100_sclk1_ctrl,
@@ -1339,24 +1375,28 @@ static struct clk init_clocks[] = {
.ctrlbit = (1 << 1),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.0",
.id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.1",
.id = 1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.2",
.id = 2,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
+ .devname = "s3c6400-uart.3",
.id = 3,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
diff --git a/arch/arm/mach-s5pc100/include/mach/clkdev.h b/arch/arm/mach-s5pc100/include/mach/clkdev.h
new file mode 100644
index 0000000..1247f5e
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_EXYNOS4_CLKDEV_H__
+#define __MACH_EXYNOS4_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 6/7] ARM: S5PV210: Add clkdev support
2011-05-19 21:18 [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Thomas Abraham
` (4 preceding siblings ...)
2011-05-19 21:18 ` [PATCH 5/7] ARM: S5PC100: " Thomas Abraham
@ 2011-05-19 21:18 ` Thomas Abraham
2011-05-25 21:39 ` Kukjin Kim
2011-05-19 21:18 ` [PATCH 7/7] ARM: Exynos4: " Thomas Abraham
2011-05-25 21:52 ` [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Kukjin Kim
7 siblings, 1 reply; 16+ messages in thread
From: Thomas Abraham @ 2011-05-19 21:18 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim
Add clkdev support for Samsung's s5pv210 platform.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s5pv210/clock.c | 42 ++++++++++++++++++++++++++-
arch/arm/mach-s5pv210/include/mach/clkdev.h | 7 ++++
3 files changed, 49 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-s5pv210/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b329ee4..8d010f2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -769,6 +769,7 @@ config ARCH_S5PV210
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 2d59949..747d176 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -312,12 +312,14 @@ static struct clk_ops clk_fout_apll_ops = {
static struct clk init_clocks_off[] = {
{
.name = "pdma",
+ .devname = "s3c-pl330.0",
.id = 0,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pdma",
+ .devname = "s3c-pl330.1",
.id = 1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
@@ -330,18 +332,21 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1<<29),
}, {
.name = "fimc",
+ .devname = "s5pv210-fimc.0",
.id = 0,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = "fimc",
+ .devname = "s5pv210-fimc.1",
.id = 1,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "fimc",
+ .devname = "s5pv210-fimc.2",
.id = 2,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
@@ -366,30 +371,34 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1<<0),
}, {
.name = "cfcon",
- .id = 0,
+ .id = -1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<25),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.0",
.id = 0,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.1",
.id = 1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.2",
.id = 2,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<18),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.3",
.id = 3,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
@@ -414,36 +423,42 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1<<15),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.0",
.id = 0,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<7),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.1",
.id = 1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.2",
.id = 2,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<9),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<12),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<13),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.2",
.id = 2,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
@@ -468,18 +483,21 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1<<21),
}, {
.name = "iis",
+ .devname = "samsung-i2s.0",
.id = 0,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<4),
}, {
.name = "iis",
+ .devname = "samsung-i2s.1",
.id = 1,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "iis",
+ .devname = "samsung-i2s.2",
.id = 2,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
@@ -503,24 +521,28 @@ static struct clk init_clocks[] = {
.ops = &clk_hclk_imem_ops,
}, {
.name = "uart",
+ .devname = "s5pv210-uart.0",
.id = 0,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.1",
.id = 1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.2",
.id = 2,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.3",
.id = 3,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
@@ -647,6 +669,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "sclk_audio",
+ .devname = "soc-audio.0",
.id = 0,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 24),
@@ -676,6 +699,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
static struct clksrc_clk clk_sclk_audio1 = {
.clk = {
.name = "sclk_audio",
+ .devname = "soc-audio.1",
.id = 1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 25),
@@ -705,6 +729,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
static struct clksrc_clk clk_sclk_audio2 = {
.clk = {
.name = "sclk_audio",
+ .devname = "soc-audio.2",
.id = 2,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 26),
@@ -809,6 +834,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.0",
.id = 0,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 12),
@@ -819,6 +845,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.1",
.id = 1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 13),
@@ -829,6 +856,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.2",
.id = 2,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 14),
@@ -839,6 +867,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.3",
.id = 3,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 15),
@@ -858,6 +887,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "s5pv210-fimc.0",
.id = 0,
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 2),
@@ -868,6 +898,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "s5pv210-fimc.1",
.id = 1,
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 3),
@@ -878,6 +909,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "s5pv210-fimc.2",
.id = 2,
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 4),
@@ -888,6 +920,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
+ .devname = "s5pv210-fimc.0",
.id = 0,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 3),
@@ -898,6 +931,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
+ .devname = "s5pv210-fimc.1",
.id = 1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 4),
@@ -918,6 +952,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.0",
.id = 0,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 8),
@@ -928,6 +963,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.1",
.id = 1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 9),
@@ -938,6 +974,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.2",
.id = 2,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 10),
@@ -948,6 +985,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "sdhci-s3c.3",
.id = 3,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 11),
@@ -998,6 +1036,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 16),
@@ -1008,6 +1047,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 17),
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h
new file mode 100644
index 0000000..1247f5e
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_EXYNOS4_CLKDEV_H__
+#define __MACH_EXYNOS4_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 7/7] ARM: Exynos4: Add clkdev support
2011-05-19 21:18 [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Thomas Abraham
` (5 preceding siblings ...)
2011-05-19 21:18 ` [PATCH 6/7] ARM: S5PV210: " Thomas Abraham
@ 2011-05-19 21:18 ` Thomas Abraham
2011-05-25 21:34 ` Kukjin Kim
2011-05-25 21:52 ` [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Kukjin Kim
7 siblings, 1 reply; 16+ messages in thread
From: Thomas Abraham @ 2011-05-19 21:18 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim
Add clkdev support for Samsung's Exynos4 platform.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-exynos4/clock.c | 63 +++++++++++++++++++++++++--
arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +++
arch/arm/mach-exynos4/time.c | 2 +
4 files changed, 69 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8d010f2..452e1c1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -786,6 +786,7 @@ config ARCH_EXYNOS4
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 871f9d5..901fa51 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -404,41 +404,49 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1<<24),
}, {
.name = "csis",
+ .devname = "s5p-mipi-csis.0",
.id = 0,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "csis",
+ .devname = "s5p-mipi-csis.1",
.id = 1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "fimc",
+ .devname = "exynos4-fimc.0",
.id = 0,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimc",
+ .devname = "exynos4-fimc.1",
.id = 1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
+ .devname = "exynos4-fimc.2",
.id = 2,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
+ .devname = "exynos4-fimc.3",
.id = 3,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimd",
+ .devname = "s5pv310-fb.0",
.id = 0,
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimd",
+ .devname = "s5pv310-fb.1",
.id = 1,
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
@@ -450,31 +458,35 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 3),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.0",
.id = 0,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.1",
.id = 1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.2",
.id = 2,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.3",
.id = 3,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
}, {
- .name = "hsmmc",
- .id = 4,
+ .name = "dwmmc",
+ .id = -1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
@@ -486,11 +498,13 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 10),
}, {
.name = "pdma",
+ .devname = "s3c-pl330.0",
.id = 0,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "pdma",
+ .devname = "s3c-pl330.1",
.id = 1,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
@@ -527,31 +541,37 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 13),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.2",
.id = 2,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "iis",
+ .devname = "samsung-i2s.0",
.id = 0,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "iis",
+ .devname = "samsung-i2s.1",
.id = 1,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "iis",
+ .devname = "samsung-i2s.2",
.id = 2,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 21),
@@ -567,48 +587,56 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 0),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.0",
.id = 0,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.1",
.id = 1,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.2",
.id = 2,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.3",
.id = 3,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.4",
.id = 4,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.5",
.id = 5,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.6",
.id = 6,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.7",
.id = 7,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
@@ -689,31 +717,37 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "uart",
+ .devname = "s5pv210-uart.0",
.id = 0,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.1",
.id = 1,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.2",
.id = 2,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.3",
.id = 3,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.4",
.id = 4,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.5",
.id = 5,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5),
@@ -839,6 +873,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.0",
.id = 0,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
@@ -849,6 +884,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.1",
.id = 1,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
@@ -859,6 +895,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.2",
.id = 2,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
@@ -869,6 +906,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.3",
.id = 3,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
@@ -889,6 +927,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
+ .devname = "s5p-mipi-csis.0",
.id = 0,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 24),
@@ -899,6 +938,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
+ .devname = "s5p-mipi-csis.1",
.id = 1,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 28),
@@ -909,6 +949,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
+ .devname = "exynos4-fimc.0",
.id = 0,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 16),
@@ -919,6 +960,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
+ .devname = "exynos4-fimc.1",
.id = 1,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 20),
@@ -929,6 +971,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "exynos4-fimc.0",
.id = 0,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 0),
@@ -939,6 +982,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "exynos4-fimc.1",
.id = 1,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 4),
@@ -949,6 +993,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "exynos4-fimc.2",
.id = 2,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 8),
@@ -959,6 +1004,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "exynos4-fimc.3",
.id = 3,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 12),
@@ -969,6 +1015,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
+ .devname = "s5pv310-fb.0",
.id = 0,
.enable = exynos4_clksrc_mask_lcd0_ctrl,
.ctrlbit = (1 << 0),
@@ -979,6 +1026,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
+ .devname = "s5pv310-fb.1",
.id = 1,
.enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0),
@@ -999,6 +1047,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
@@ -1009,6 +1058,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
@@ -1019,6 +1069,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.2",
.id = 2,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
@@ -1037,6 +1088,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "s3c-sdhci.0",
.id = 0,
.parent = &clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1046,6 +1098,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "s3c-sdhci.1",
.id = 1,
.parent = &clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1055,6 +1108,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "s3c-sdhci.2",
.id = 2,
.parent = &clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1064,6 +1118,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "s3c-sdhci.3",
.id = 3,
.parent = &clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1072,8 +1127,8 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
}, {
.clk = {
- .name = "sclk_mmc",
- .id = 4,
+ .name = "sclk_dwmmc",
+ .id = -1,
.parent = &clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 16),
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
new file mode 100644
index 0000000..1247f5e
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_EXYNOS4_CLKDEV_H__
+#define __MACH_EXYNOS4_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
index 86b9fa0..cb63f97 100644
--- a/arch/arm/mach-exynos4/time.c
+++ b/arch/arm/mach-exynos4/time.c
@@ -262,6 +262,7 @@ static void __init exynos4_timer_resources(void)
clk_enable(timerclk);
tmpdev.id = 2;
+ tmpdev.dev.init_name = "s3c24xx-pwm.2";
tin2 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin2))
panic("failed to get pwm-tin2 clock for system timer");
@@ -272,6 +273,7 @@ static void __init exynos4_timer_resources(void)
clk_enable(tin2);
tmpdev.id = 4;
+ tmpdev.dev.init_name = "s3c24xx-pwm.4";
tin4 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin4))
panic("failed to get pwm-tin4 clock for system timer");
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 7/7] ARM: Exynos4: Add clkdev support
2011-05-19 21:18 ` [PATCH 7/7] ARM: Exynos4: " Thomas Abraham
@ 2011-05-25 21:34 ` Kukjin Kim
2011-05-26 2:51 ` Thomas Abraham
0 siblings, 1 reply; 16+ messages in thread
From: Kukjin Kim @ 2011-05-25 21:34 UTC (permalink / raw)
To: Thomas Abraham; +Cc: linux-samsung-soc, kgene.kim
On 05/19/11 14:18, Thomas Abraham wrote:
> Add clkdev support for Samsung's Exynos4 platform.
>
> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/mach-exynos4/clock.c | 63 +++++++++++++++++++++++++--
> arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +++
> arch/arm/mach-exynos4/time.c | 2 +
> 4 files changed, 69 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
>
(snip)
> - .name = "hsmmc",
> - .id = 4,
> + .name = "dwmmc",
> + .id = -1,
This change should be split :)
(snip)
> @@ -1072,8 +1127,8 @@ static struct clksrc_clk clksrcs[] = {
> .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
> }, {
> .clk = {
> - .name = "sclk_mmc",
> - .id = 4,
> + .name = "sclk_dwmmc",
> + .id = -1,
Same as above.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 6/7] ARM: S5PV210: Add clkdev support
2011-05-19 21:18 ` [PATCH 6/7] ARM: S5PV210: " Thomas Abraham
@ 2011-05-25 21:39 ` Kukjin Kim
0 siblings, 0 replies; 16+ messages in thread
From: Kukjin Kim @ 2011-05-25 21:39 UTC (permalink / raw)
To: Thomas Abraham; +Cc: linux-samsung-soc, kgene.kim
On 05/19/11 14:18, Thomas Abraham wrote:
> Add clkdev support for Samsung's s5pv210 platform.
>
> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/mach-s5pv210/clock.c | 42 ++++++++++++++++++++++++++-
> arch/arm/mach-s5pv210/include/mach/clkdev.h | 7 ++++
> 3 files changed, 49 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-s5pv210/include/mach/clkdev.h
>
(snip)
> @@ -366,30 +371,34 @@ static struct clk init_clocks_off[] = {
> .ctrlbit = (1<<0),
> }, {
> .name = "cfcon",
> - .id = 0,
> + .id = -1,
Should be split.
--
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 5/7] ARM: S5PC100: Add clkdev support
2011-05-19 21:18 ` [PATCH 5/7] ARM: S5PC100: " Thomas Abraham
@ 2011-05-25 21:42 ` Kukjin Kim
0 siblings, 0 replies; 16+ messages in thread
From: Kukjin Kim @ 2011-05-25 21:42 UTC (permalink / raw)
To: Thomas Abraham; +Cc: linux-samsung-soc, kgene.kim
On 05/19/11 14:18, Thomas Abraham wrote:
> Add clkdev support for Samsung's s5pc100 platforms.
>
> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/mach-s5pc100/clock.c | 42 ++++++++++++++++++++++++++-
> arch/arm/mach-s5pc100/include/mach/clkdev.h | 7 ++++
> 3 files changed, 49 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-s5pc100/include/mach/clkdev.h
>
(snip)
> @@ -549,7 +557,7 @@ static struct clk init_clocks_off[] = {
> .ctrlbit = (1 << 7),
> }, {
> .name = "g3d",
> - .id = 0,
> + .id = -1,
should be split
(snip)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/7] ARM: S5P64X0: Add clkdev support
2011-05-19 21:18 ` [PATCH 4/7] ARM: S5P64X0: " Thomas Abraham
@ 2011-05-25 21:45 ` Kukjin Kim
2011-05-26 3:10 ` Thomas Abraham
0 siblings, 1 reply; 16+ messages in thread
From: Kukjin Kim @ 2011-05-25 21:45 UTC (permalink / raw)
To: Thomas Abraham; +Cc: linux-samsung-soc, kgene.kim
On 05/19/11 14:18, Thomas Abraham wrote:
> Add clkdev support for Samsung's s5p64x0 platforms.
>
> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 20 ++++++++++++++++++++
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 19 +++++++++++++++++++
> arch/arm/mach-s5p64x0/include/mach/clkdev.h | 7 +++++++
> arch/arm/plat-s5p/s5p-time.c | 9 +++++++++
> 5 files changed, 56 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-s5p64x0/include/mach/clkdev.h
(snip)
I wonder why following is included in this, "S5P64X0: Add clkdev support".
> diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
> index 8090403..d9efd29 100644
> --- a/arch/arm/plat-s5p/s5p-time.c
> +++ b/arch/arm/plat-s5p/s5p-time.c
> @@ -408,6 +408,7 @@ static void __init s5p_timer_resources(void)
>
> unsigned long event_id = timer_source.event_id;
> unsigned long source_id = timer_source.source_id;
> + char devname[15];
>
> timerclk = clk_get(NULL, "timers");
> if (IS_ERR(timerclk))
> @@ -415,6 +416,10 @@ static void __init s5p_timer_resources(void)
>
> clk_enable(timerclk);
>
> + sprintf(devname, "s3c24xx-pwm.%lu", event_id);
> + s3c_device_timer[event_id].id = event_id;
> + s3c_device_timer[event_id].dev.init_name = devname;
> +
> tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
> if (IS_ERR(tin_event))
> panic("failed to get pwm-tin clock for event timer");
> @@ -425,6 +430,10 @@ static void __init s5p_timer_resources(void)
>
> clk_enable(tin_event);
>
> + sprintf(devname, "s3c24xx-pwm.%lu", source_id);
> + s3c_device_timer[source_id].id = source_id;
> + s3c_device_timer[source_id].dev.init_name = devname;
> +
> tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
> if (IS_ERR(tin_source))
> panic("failed to get pwm-tin clock for source timer");
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms
2011-05-19 21:18 [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Thomas Abraham
` (6 preceding siblings ...)
2011-05-19 21:18 ` [PATCH 7/7] ARM: Exynos4: " Thomas Abraham
@ 2011-05-25 21:52 ` Kukjin Kim
2011-05-26 3:11 ` Thomas Abraham
7 siblings, 1 reply; 16+ messages in thread
From: Kukjin Kim @ 2011-05-25 21:52 UTC (permalink / raw)
To: Thomas Abraham; +Cc: linux-samsung-soc, kgene.kim
On 05/19/11 14:18, Thomas Abraham wrote:
> Thomas Abraham (7):
> ARM: SAMSUNG: Add clkdev infrastructure
> ARM: S3C24XX: Add clkdev support
> ARM: S3C64XX: Add clkdev support
> ARM: S5P64X0: Add clkdev support
> ARM: S5PC100: Add clkdev support
> ARM: S5PV210: Add clkdev support
> ARM: Exynos4: Add clkdev support
>
> arch/arm/Kconfig | 6 ++
> arch/arm/mach-exynos4/clock.c | 63 +++++++++++++++++++-
> arch/arm/mach-exynos4/include/mach/clkdev.h | 7 ++
> arch/arm/mach-exynos4/time.c | 2 +
> arch/arm/mach-s3c2412/clock.c | 3 +
> arch/arm/mach-s3c2416/clock.c | 5 ++
> arch/arm/mach-s3c2443/clock.c | 4 +
> arch/arm/mach-s3c64xx/clock.c | 25 ++++++++
> arch/arm/mach-s3c64xx/include/mach/clkdev.h | 7 ++
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 20 +++++++
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 19 ++++++
> arch/arm/mach-s5p64x0/include/mach/clkdev.h | 7 ++
> arch/arm/mach-s5pc100/clock.c | 42 +++++++++++++-
> arch/arm/mach-s5pc100/include/mach/clkdev.h | 7 ++
> arch/arm/mach-s5pv210/clock.c | 42 +++++++++++++-
> arch/arm/mach-s5pv210/include/mach/clkdev.h | 7 ++
> arch/arm/plat-s3c24xx/include/mach/clkdev.h | 7 ++
> arch/arm/plat-s3c24xx/s3c2410-clock.c | 3 +
> arch/arm/plat-s3c24xx/s3c2443-clock.c | 4 +
> arch/arm/plat-s5p/s5p-time.c | 9 +++
> arch/arm/plat-samsung/clock.c | 83 ++-------------------------
> arch/arm/plat-samsung/include/plat/clock.h | 3 +
> arch/arm/plat-samsung/pwm-clock.c | 10 +++
> arch/arm/plat-samsung/time.c | 2 +
> 24 files changed, 303 insertions(+), 84 deletions(-)
> create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-s3c64xx/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-s5p64x0/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-s5pc100/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-s5pv210/include/mach/clkdev.h
> create mode 100644 arch/arm/plat-s3c24xx/include/mach/clkdev.h
>
Hi Thomas,
Thanks for this patches :)
There are some comments in each patches and I need to check again about
the devname like following.
s5p-fimc vs. s5pv210-fimc
sdhci-s3c vs. s3c-sdhci
and so on...
Since I'm out of office now, don't have all regarding materials. I will
back this soon.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 7/7] ARM: Exynos4: Add clkdev support
2011-05-25 21:34 ` Kukjin Kim
@ 2011-05-26 2:51 ` Thomas Abraham
0 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-26 2:51 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-samsung-soc
Hi Mr. Kukjin Kim,
On Thu, May 26, 2011 at 3:04 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 05/19/11 14:18, Thomas Abraham wrote:
>>
>> Add clkdev support for Samsung's Exynos4 platform.
>>
>> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
>> ---
>> arch/arm/Kconfig | 1 +
>> arch/arm/mach-exynos4/clock.c | 63
>> +++++++++++++++++++++++++--
>> arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +++
>> arch/arm/mach-exynos4/time.c | 2 +
>> 4 files changed, 69 insertions(+), 4 deletions(-)
>> create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
>>
>
> (snip)
>
>> - .name = "hsmmc",
>> - .id = 4,
>> + .name = "dwmmc",
>> + .id = -1,
>
> This change should be split :)
Ok. I will move these changes to another patch.
Thanks,
Thomas.
>
> (snip)
>
>> @@ -1072,8 +1127,8 @@ static struct clksrc_clk clksrcs[] = {
>> .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size =
>> 8 },
>> }, {
>> .clk = {
>> - .name = "sclk_mmc",
>> - .id = 4,
>> + .name = "sclk_dwmmc",
>> + .id = -1,
>
> Same as above.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/7] ARM: S5P64X0: Add clkdev support
2011-05-25 21:45 ` Kukjin Kim
@ 2011-05-26 3:10 ` Thomas Abraham
0 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-26 3:10 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-samsung-soc
Hi Mr. Kukjin Kim,
On Thu, May 26, 2011 at 3:15 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 05/19/11 14:18, Thomas Abraham wrote:
>>
>> Add clkdev support for Samsung's s5p64x0 platforms.
>>
>> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
>> ---
>> arch/arm/Kconfig | 1 +
>> arch/arm/mach-s5p64x0/clock-s5p6440.c | 20 ++++++++++++++++++++
>> arch/arm/mach-s5p64x0/clock-s5p6450.c | 19 +++++++++++++++++++
>> arch/arm/mach-s5p64x0/include/mach/clkdev.h | 7 +++++++
>> arch/arm/plat-s5p/s5p-time.c | 9 +++++++++
>> 5 files changed, 56 insertions(+), 0 deletions(-)
>> create mode 100644 arch/arm/mach-s5p64x0/include/mach/clkdev.h
>
> (snip)
>
> I wonder why following is included in this, "S5P64X0: Add clkdev support".
For clock lookups (using clk_get) based on clkdev, the platform
devices should be registered before calling the clk_get function. In
this case, the clk_get is called when platform devices
(s3c_device_timer[]) is not registered. So these platform devices can
be assigned a init_name which is then used by clk_dev to lookup the
clocks. So, that is the reason for modifying the clock lookup in
s5p-time.c file.
Thanks,
Thomas.
>
>> diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
>> index 8090403..d9efd29 100644
>> --- a/arch/arm/plat-s5p/s5p-time.c
>> +++ b/arch/arm/plat-s5p/s5p-time.c
>> @@ -408,6 +408,7 @@ static void __init s5p_timer_resources(void)
>>
>> unsigned long event_id = timer_source.event_id;
>> unsigned long source_id = timer_source.source_id;
>> + char devname[15];
>>
>> timerclk = clk_get(NULL, "timers");
>> if (IS_ERR(timerclk))
>> @@ -415,6 +416,10 @@ static void __init s5p_timer_resources(void)
>>
>> clk_enable(timerclk);
>>
>> + sprintf(devname, "s3c24xx-pwm.%lu", event_id);
>> + s3c_device_timer[event_id].id = event_id;
>> + s3c_device_timer[event_id].dev.init_name = devname;
>> +
>> tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
>> if (IS_ERR(tin_event))
>> panic("failed to get pwm-tin clock for event timer");
>> @@ -425,6 +430,10 @@ static void __init s5p_timer_resources(void)
>>
>> clk_enable(tin_event);
>>
>> + sprintf(devname, "s3c24xx-pwm.%lu", source_id);
>> + s3c_device_timer[source_id].id = source_id;
>> + s3c_device_timer[source_id].dev.init_name = devname;
>> +
>> tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
>> if (IS_ERR(tin_source))
>> panic("failed to get pwm-tin clock for source timer");
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms
2011-05-25 21:52 ` [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Kukjin Kim
@ 2011-05-26 3:11 ` Thomas Abraham
0 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-26 3:11 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-samsung-soc
Hi Mr. Kukjin Kim,
On Thu, May 26, 2011 at 3:22 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 05/19/11 14:18, Thomas Abraham wrote:
>>
>> Thomas Abraham (7):
>> ARM: SAMSUNG: Add clkdev infrastructure
>> ARM: S3C24XX: Add clkdev support
>> ARM: S3C64XX: Add clkdev support
>> ARM: S5P64X0: Add clkdev support
>> ARM: S5PC100: Add clkdev support
>> ARM: S5PV210: Add clkdev support
>> ARM: Exynos4: Add clkdev support
>>
>> arch/arm/Kconfig | 6 ++
>> arch/arm/mach-exynos4/clock.c | 63 +++++++++++++++++++-
>> arch/arm/mach-exynos4/include/mach/clkdev.h | 7 ++
>> arch/arm/mach-exynos4/time.c | 2 +
>> arch/arm/mach-s3c2412/clock.c | 3 +
>> arch/arm/mach-s3c2416/clock.c | 5 ++
>> arch/arm/mach-s3c2443/clock.c | 4 +
>> arch/arm/mach-s3c64xx/clock.c | 25 ++++++++
>> arch/arm/mach-s3c64xx/include/mach/clkdev.h | 7 ++
>> arch/arm/mach-s5p64x0/clock-s5p6440.c | 20 +++++++
>> arch/arm/mach-s5p64x0/clock-s5p6450.c | 19 ++++++
>> arch/arm/mach-s5p64x0/include/mach/clkdev.h | 7 ++
>> arch/arm/mach-s5pc100/clock.c | 42 +++++++++++++-
>> arch/arm/mach-s5pc100/include/mach/clkdev.h | 7 ++
>> arch/arm/mach-s5pv210/clock.c | 42 +++++++++++++-
>> arch/arm/mach-s5pv210/include/mach/clkdev.h | 7 ++
>> arch/arm/plat-s3c24xx/include/mach/clkdev.h | 7 ++
>> arch/arm/plat-s3c24xx/s3c2410-clock.c | 3 +
>> arch/arm/plat-s3c24xx/s3c2443-clock.c | 4 +
>> arch/arm/plat-s5p/s5p-time.c | 9 +++
>> arch/arm/plat-samsung/clock.c | 83
>> ++-------------------------
>> arch/arm/plat-samsung/include/plat/clock.h | 3 +
>> arch/arm/plat-samsung/pwm-clock.c | 10 +++
>> arch/arm/plat-samsung/time.c | 2 +
>> 24 files changed, 303 insertions(+), 84 deletions(-)
>> create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
>> create mode 100644 arch/arm/mach-s3c64xx/include/mach/clkdev.h
>> create mode 100644 arch/arm/mach-s5p64x0/include/mach/clkdev.h
>> create mode 100644 arch/arm/mach-s5pc100/include/mach/clkdev.h
>> create mode 100644 arch/arm/mach-s5pv210/include/mach/clkdev.h
>> create mode 100644 arch/arm/plat-s3c24xx/include/mach/clkdev.h
>>
> Hi Thomas,
>
> Thanks for this patches :)
>
> There are some comments in each patches and I need to check again about the
> devname like following.
>
> s5p-fimc vs. s5pv210-fimc
> sdhci-s3c vs. s3c-sdhci
> and so on...
>
> Since I'm out of office now, don't have all regarding materials. I will back
> this soon.
Thanks for reviewing the patches. I will rework the patches as per
your comments and submit again.
Thanks,
Thomas.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2011-05-26 3:11 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-05-19 21:18 [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Thomas Abraham
2011-05-19 21:18 ` [PATCH 1/7] ARM: SAMSUNG: Add clkdev infrastructure Thomas Abraham
2011-05-19 21:18 ` [PATCH 2/7] ARM: S3C24XX: Add clkdev support Thomas Abraham
2011-05-19 21:18 ` [PATCH 3/7] ARM: S3C64XX: " Thomas Abraham
2011-05-19 21:18 ` [PATCH 4/7] ARM: S5P64X0: " Thomas Abraham
2011-05-25 21:45 ` Kukjin Kim
2011-05-26 3:10 ` Thomas Abraham
2011-05-19 21:18 ` [PATCH 5/7] ARM: S5PC100: " Thomas Abraham
2011-05-25 21:42 ` Kukjin Kim
2011-05-19 21:18 ` [PATCH 6/7] ARM: S5PV210: " Thomas Abraham
2011-05-25 21:39 ` Kukjin Kim
2011-05-19 21:18 ` [PATCH 7/7] ARM: Exynos4: " Thomas Abraham
2011-05-25 21:34 ` Kukjin Kim
2011-05-26 2:51 ` Thomas Abraham
2011-05-25 21:52 ` [RFC][PATCH 0/7] ARM: Add clkdev support for Samsung's platforms Kukjin Kim
2011-05-26 3:11 ` Thomas Abraham
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