[U-Boot] [U-BOOT] [PATCH 0/1] arm: smdk2410: coding style cleanup

[U-Boot] [U-BOOT] [PATCH 0/1] arm: smdk2410: coding style cleanup

[Peter Kong]

smdk2410: coding style cleanup

Peter Kong (1):
  smdk2410:coding style cleanup

 board/samsung/smdk2410/smdk2410.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

-- 
1.7.2.5

[U-Boot] [U-BOOT] [PATCH 1/1] smdk2410:coding style cleanup

[Peter Kong]

Signed-off-by: Peter Kong <peterkoug@gmail.com>
---
 board/samsung/smdk2410/smdk2410.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c
index 76a24bb..479ca8c 100644
--- a/board/samsung/smdk2410/smdk2410.c
+++ b/board/samsung/smdk2410/smdk2410.c
@@ -33,11 +33,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define FCLK_SPEED 1
 
-#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
+#if FCLK_SPEED == 0		/* Fout = 203MHz, Fin = 12MHz for Audio */
 #define M_MDIV	0xC3
 #define M_PDIV	0x4
 #define M_SDIV	0x1
-#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
+#elif FCLK_SPEED == 1		/* Fout = 202.8MHz */
 #define M_MDIV	0xA1
 #define M_PDIV	0x3
 #define M_SDIV	0x1
@@ -45,17 +45,17 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define USB_CLOCK 1
 
-#if USB_CLOCK==0
+#if USB_CLOCK == 0
 #define U_M_MDIV	0xA1
 #define U_M_PDIV	0x3
 #define U_M_SDIV	0x1
-#elif USB_CLOCK==1
+#elif USB_CLOCK == 1
 #define U_M_MDIV	0x48
 #define U_M_PDIV	0x3
 #define U_M_SDIV	0x2
 #endif
 
-static inline void delay (unsigned long loops)
+static inline void delay(unsigned long loops)
 {
 	__asm__ volatile ("1:\n"
 	  "subs %0, %1, #1\n"
@@ -66,7 +66,7 @@ static inline void delay (unsigned long loops)
  * Miscellaneous platform dependent initialisations
  */
 
-int board_init (void)
+int board_init(void)
 {
 	struct s3c24x0_clock_power * const clk_power =
 					s3c24x0_get_base_clock_power();
@@ -79,13 +79,13 @@ int board_init (void)
 	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
 
 	/* some delay between MPLL and UPLL */
-	delay (4000);
+	delay(4000);
 
 	/* configure UPLL */
 	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
 
 	/* some delay between MPLL and UPLL */
-	delay (8000);
+	delay(8000);
 
 	/* set up the I/O ports */
 	gpio->gpacon = 0x007FFFFF;
@@ -116,7 +116,7 @@ int board_init (void)
 	return 0;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-- 
1.7.2.5