* [PATCH V2 0/8] ARM: EXYNOS4: Update PM
@ 2011-07-01 1:57 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux
This patch updates EXYNOS4 PM based on Russell's suspend consolidation patches.
NOTE: Depends on external GIC patches which are from Changhwan Youn.
Changes since V1:
- address comments from Russell King
[PATCH V2 1/8] ARM: EXYNOS4: Support system level power down configuration
[PATCH V2 2/8] ARM: EXYNOS4: Remove PMU configuration for S2RAM
[PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
[PATCH V2 4/8] ARM: SAMSUNG: Add support for failure of sleep mode
[PATCH V2 5/8] ARM: EXYNOS4: Support early wakeup entering sleep mode
[PATCH V2 6/8] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION setting for PM
[PATCH V2 7/8] ARM: EXYNOS4: Add save/restore for other ARM registers
[PATCH V2 8/8] ARM: EXYNOS4: Add save/restore function for PLL
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 0/8] ARM: EXYNOS4: Update PM
@ 2011-07-01 1:57 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates EXYNOS4 PM based on Russell's suspend consolidation patches.
NOTE: Depends on external GIC patches which are from Changhwan Youn.
Changes since V1:
- address comments from Russell King
[PATCH V2 1/8] ARM: EXYNOS4: Support system level power down configuration
[PATCH V2 2/8] ARM: EXYNOS4: Remove PMU configuration for S2RAM
[PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
[PATCH V2 4/8] ARM: SAMSUNG: Add support for failure of sleep mode
[PATCH V2 5/8] ARM: EXYNOS4: Support early wakeup entering sleep mode
[PATCH V2 6/8] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION setting for PM
[PATCH V2 7/8] ARM: EXYNOS4: Add save/restore for other ARM registers
[PATCH V2 8/8] ARM: EXYNOS4: Add save/restore function for PLL
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 1/8] ARM: EXYNOS4: Support system level power down configuration
2011-07-01 1:57 ` Kukjin Kim
@ 2011-07-01 1:57 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jaecheol Lee, Kukjin Kim
From: Jaecheol Lee <jc.lee@samsung.com>
EXYNOS4 supports 3 different system level power down mode by PMU (Power
Management Unit). Each power down mode need to configure many PMU registers
with different value. This patch supports function to configure PMU registers
with pre-defined values in PMU code. This function may be used by PM code and
AFTR/LPA support driver.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/Makefile | 2 +-
arch/arm/mach-exynos4/include/mach/pmu.h | 25 +++++
arch/arm/mach-exynos4/pmu.c | 175 ++++++++++++++++++++++++++++++
3 files changed, 201 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-exynos4/include/mach/pmu.h
create mode 100644 arch/arm/mach-exynos4/pmu.c
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ec..880f902 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -13,7 +13,7 @@ obj- :=
# Core support for EXYNOS4 system
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o
+obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
new file mode 100644
index 0000000..a952904
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4210 - PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PMU_H
+#define __ASM_ARCH_PMU_H __FILE__
+
+enum sys_powerdown {
+ SYS_AFTR,
+ SYS_LPA,
+ SYS_SLEEP,
+ NUM_SYS_POWERDOWN,
+};
+
+extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+
+#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
new file mode 100644
index 0000000..7ea9eb2
--- /dev/null
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -0,0 +1,175 @@
+/* linux/arch/arm/mach-exynos4/pmu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4210 - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <mach/regs-clock.h>
+#include <mach/pmu.h>
+
+static void __iomem *sys_powerdown_reg[] = {
+ S5P_ARM_CORE0_LOWPWR,
+ S5P_DIS_IRQ_CORE0,
+ S5P_DIS_IRQ_CENTRAL0,
+ S5P_ARM_CORE1_LOWPWR,
+ S5P_DIS_IRQ_CORE1,
+ S5P_DIS_IRQ_CENTRAL1,
+ S5P_ARM_COMMON_LOWPWR,
+ S5P_L2_0_LOWPWR,
+ S5P_L2_1_LOWPWR,
+ S5P_CMU_ACLKSTOP_LOWPWR,
+ S5P_CMU_SCLKSTOP_LOWPWR,
+ S5P_CMU_RESET_LOWPWR,
+ S5P_APLL_SYSCLK_LOWPWR,
+ S5P_MPLL_SYSCLK_LOWPWR,
+ S5P_VPLL_SYSCLK_LOWPWR,
+ S5P_EPLL_SYSCLK_LOWPWR,
+ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
+ S5P_CMU_RESET_GPSALIVE_LOWPWR,
+ S5P_CMU_CLKSTOP_CAM_LOWPWR,
+ S5P_CMU_CLKSTOP_TV_LOWPWR,
+ S5P_CMU_CLKSTOP_MFC_LOWPWR,
+ S5P_CMU_CLKSTOP_G3D_LOWPWR,
+ S5P_CMU_CLKSTOP_LCD0_LOWPWR,
+ S5P_CMU_CLKSTOP_LCD1_LOWPWR,
+ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
+ S5P_CMU_CLKSTOP_GPS_LOWPWR,
+ S5P_CMU_RESET_CAM_LOWPWR,
+ S5P_CMU_RESET_TV_LOWPWR,
+ S5P_CMU_RESET_MFC_LOWPWR,
+ S5P_CMU_RESET_G3D_LOWPWR,
+ S5P_CMU_RESET_LCD0_LOWPWR,
+ S5P_CMU_RESET_LCD1_LOWPWR,
+ S5P_CMU_RESET_MAUDIO_LOWPWR,
+ S5P_CMU_RESET_GPS_LOWPWR,
+ S5P_TOP_BUS_LOWPWR,
+ S5P_TOP_RETENTION_LOWPWR,
+ S5P_TOP_PWR_LOWPWR,
+ S5P_LOGIC_RESET_LOWPWR,
+ S5P_ONENAND_MEM_LOWPWR,
+ S5P_MODIMIF_MEM_LOWPWR,
+ S5P_G2D_ACP_MEM_LOWPWR,
+ S5P_USBOTG_MEM_LOWPWR,
+ S5P_HSMMC_MEM_LOWPWR,
+ S5P_CSSYS_MEM_LOWPWR,
+ S5P_SECSS_MEM_LOWPWR,
+ S5P_PCIE_MEM_LOWPWR,
+ S5P_SATA_MEM_LOWPWR,
+ S5P_PAD_RETENTION_DRAM_LOWPWR,
+ S5P_PAD_RETENTION_MAUDIO_LOWPWR,
+ S5P_PAD_RETENTION_GPIO_LOWPWR,
+ S5P_PAD_RETENTION_UART_LOWPWR,
+ S5P_PAD_RETENTION_MMCA_LOWPWR,
+ S5P_PAD_RETENTION_MMCB_LOWPWR,
+ S5P_PAD_RETENTION_EBIA_LOWPWR,
+ S5P_PAD_RETENTION_EBIB_LOWPWR,
+ S5P_PAD_RETENTION_ISOLATION_LOWPWR,
+ S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
+ S5P_XUSBXTI_LOWPWR,
+ S5P_XXTI_LOWPWR,
+ S5P_EXT_REGULATOR_LOWPWR,
+ S5P_GPIO_MODE_LOWPWR,
+ S5P_GPIO_MODE_MAUDIO_LOWPWR,
+ S5P_CAM_LOWPWR,
+ S5P_TV_LOWPWR,
+ S5P_MFC_LOWPWR,
+ S5P_G3D_LOWPWR,
+ S5P_LCD0_LOWPWR,
+ S5P_LCD1_LOWPWR,
+ S5P_MAUDIO_LOWPWR,
+ S5P_GPS_LOWPWR,
+ S5P_GPS_ALIVE_LOWPWR,
+};
+
+static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
+ /* { AFTR, LPA, SLEEP }*/
+ { 0, 0, 2 }, /* ARM_CORE0 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
+ { 0, 0, 2 }, /* ARM_CORE1 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
+ { 0, 0, 2 }, /* ARM_COMMON */
+ { 2, 2, 3 }, /* ARM_CPU_L2_0 */
+ { 2, 2, 3 }, /* ARM_CPU_L2_1 */
+ { 1, 0, 0 }, /* CMU_ACLKSTOP */
+ { 1, 0, 0 }, /* CMU_SCLKSTOP */
+ { 1, 1, 0 }, /* CMU_RESET */
+ { 1, 0, 0 }, /* APLL_SYSCLK */
+ { 1, 0, 0 }, /* MPLL_SYSCLK */
+ { 1, 0, 0 }, /* VPLL_SYSCLK */
+ { 1, 1, 0 }, /* EPLL_SYSCLK */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
+ { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_TV */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
+ { 1, 1, 0 }, /* CMU_RESET_CAM */
+ { 1, 1, 0 }, /* CMU_RESET_TV */
+ { 1, 1, 0 }, /* CMU_RESET_MFC */
+ { 1, 1, 0 }, /* CMU_RESET_G3D */
+ { 1, 1, 0 }, /* CMU_RESET_LCD0 */
+ { 1, 1, 0 }, /* CMU_RESET_LCD1 */
+ { 1, 1, 0 }, /* CMU_RESET_MAUDIO */
+ { 1, 1, 0 }, /* CMU_RESET_GPS */
+ { 3, 0, 0 }, /* TOP_BUS */
+ { 1, 0, 1 }, /* TOP_RETENTION */
+ { 3, 0, 3 }, /* TOP_PWR */
+ { 1, 1, 0 }, /* LOGIC_RESET */
+ { 3, 0, 0 }, /* ONENAND_MEM */
+ { 3, 0, 0 }, /* MODIMIF_MEM */
+ { 3, 0, 0 }, /* G2D_ACP_MEM */
+ { 3, 0, 0 }, /* USBOTG_MEM */
+ { 3, 0, 0 }, /* HSMMC_MEM */
+ { 3, 0, 0 }, /* CSSYS_MEM */
+ { 3, 0, 0 }, /* SECSS_MEM */
+ { 3, 0, 0 }, /* PCIE_MEM */
+ { 3, 0, 0 }, /* SATA_MEM */
+ { 1, 0, 0 }, /* PAD_RETENTION_DRAM */
+ { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
+ { 1, 0, 0 }, /* PAD_RETENTION_GPIO */
+ { 1, 0, 0 }, /* PAD_RETENTION_UART */
+ { 1, 0, 0 }, /* PAD_RETENTION_MMCA */
+ { 1, 0, 0 }, /* PAD_RETENTION_MMCB */
+ { 1, 0, 0 }, /* PAD_RETENTION_EBIA */
+ { 1, 0, 0 }, /* PAD_RETENTION_EBIB */
+ { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
+ { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
+ { 1, 1, 0 }, /* XUSBXTI */
+ { 1, 1, 0 }, /* XXTI */
+ { 1, 1, 0 }, /* EXT_REGULATOR */
+ { 1, 0, 0 }, /* GPIO_MODE */
+ { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
+ { 7, 0, 0 }, /* CAM */
+ { 7, 0, 0 }, /* TV */
+ { 7, 0, 0 }, /* MFC */
+ { 7, 0, 0 }, /* G3D */
+ { 7, 0, 0 }, /* LCD0 */
+ { 7, 0, 0 }, /* LCD1 */
+ { 7, 7, 0 }, /* MAUDIO */
+ { 7, 0, 0 }, /* GPS */
+ { 7, 0, 0 }, /* GPS_ALIVE */
+};
+
+void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
+{
+ unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
+
+ for (; count > 0; count--)
+ __raw_writel(sys_powerdown_val[count - 1][mode],
+ sys_powerdown_reg[count - 1]);
+}
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 1/8] ARM: EXYNOS4: Support system level power down configuration
@ 2011-07-01 1:57 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Jaecheol Lee <jc.lee@samsung.com>
EXYNOS4 supports 3 different system level power down mode by PMU (Power
Management Unit). Each power down mode need to configure many PMU registers
with different value. This patch supports function to configure PMU registers
with pre-defined values in PMU code. This function may be used by PM code and
AFTR/LPA support driver.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/Makefile | 2 +-
arch/arm/mach-exynos4/include/mach/pmu.h | 25 +++++
arch/arm/mach-exynos4/pmu.c | 175 ++++++++++++++++++++++++++++++
3 files changed, 201 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-exynos4/include/mach/pmu.h
create mode 100644 arch/arm/mach-exynos4/pmu.c
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ec..880f902 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -13,7 +13,7 @@ obj- :=
# Core support for EXYNOS4 system
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o
+obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
new file mode 100644
index 0000000..a952904
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4210 - PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PMU_H
+#define __ASM_ARCH_PMU_H __FILE__
+
+enum sys_powerdown {
+ SYS_AFTR,
+ SYS_LPA,
+ SYS_SLEEP,
+ NUM_SYS_POWERDOWN,
+};
+
+extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+
+#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
new file mode 100644
index 0000000..7ea9eb2
--- /dev/null
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -0,0 +1,175 @@
+/* linux/arch/arm/mach-exynos4/pmu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4210 - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <mach/regs-clock.h>
+#include <mach/pmu.h>
+
+static void __iomem *sys_powerdown_reg[] = {
+ S5P_ARM_CORE0_LOWPWR,
+ S5P_DIS_IRQ_CORE0,
+ S5P_DIS_IRQ_CENTRAL0,
+ S5P_ARM_CORE1_LOWPWR,
+ S5P_DIS_IRQ_CORE1,
+ S5P_DIS_IRQ_CENTRAL1,
+ S5P_ARM_COMMON_LOWPWR,
+ S5P_L2_0_LOWPWR,
+ S5P_L2_1_LOWPWR,
+ S5P_CMU_ACLKSTOP_LOWPWR,
+ S5P_CMU_SCLKSTOP_LOWPWR,
+ S5P_CMU_RESET_LOWPWR,
+ S5P_APLL_SYSCLK_LOWPWR,
+ S5P_MPLL_SYSCLK_LOWPWR,
+ S5P_VPLL_SYSCLK_LOWPWR,
+ S5P_EPLL_SYSCLK_LOWPWR,
+ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
+ S5P_CMU_RESET_GPSALIVE_LOWPWR,
+ S5P_CMU_CLKSTOP_CAM_LOWPWR,
+ S5P_CMU_CLKSTOP_TV_LOWPWR,
+ S5P_CMU_CLKSTOP_MFC_LOWPWR,
+ S5P_CMU_CLKSTOP_G3D_LOWPWR,
+ S5P_CMU_CLKSTOP_LCD0_LOWPWR,
+ S5P_CMU_CLKSTOP_LCD1_LOWPWR,
+ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
+ S5P_CMU_CLKSTOP_GPS_LOWPWR,
+ S5P_CMU_RESET_CAM_LOWPWR,
+ S5P_CMU_RESET_TV_LOWPWR,
+ S5P_CMU_RESET_MFC_LOWPWR,
+ S5P_CMU_RESET_G3D_LOWPWR,
+ S5P_CMU_RESET_LCD0_LOWPWR,
+ S5P_CMU_RESET_LCD1_LOWPWR,
+ S5P_CMU_RESET_MAUDIO_LOWPWR,
+ S5P_CMU_RESET_GPS_LOWPWR,
+ S5P_TOP_BUS_LOWPWR,
+ S5P_TOP_RETENTION_LOWPWR,
+ S5P_TOP_PWR_LOWPWR,
+ S5P_LOGIC_RESET_LOWPWR,
+ S5P_ONENAND_MEM_LOWPWR,
+ S5P_MODIMIF_MEM_LOWPWR,
+ S5P_G2D_ACP_MEM_LOWPWR,
+ S5P_USBOTG_MEM_LOWPWR,
+ S5P_HSMMC_MEM_LOWPWR,
+ S5P_CSSYS_MEM_LOWPWR,
+ S5P_SECSS_MEM_LOWPWR,
+ S5P_PCIE_MEM_LOWPWR,
+ S5P_SATA_MEM_LOWPWR,
+ S5P_PAD_RETENTION_DRAM_LOWPWR,
+ S5P_PAD_RETENTION_MAUDIO_LOWPWR,
+ S5P_PAD_RETENTION_GPIO_LOWPWR,
+ S5P_PAD_RETENTION_UART_LOWPWR,
+ S5P_PAD_RETENTION_MMCA_LOWPWR,
+ S5P_PAD_RETENTION_MMCB_LOWPWR,
+ S5P_PAD_RETENTION_EBIA_LOWPWR,
+ S5P_PAD_RETENTION_EBIB_LOWPWR,
+ S5P_PAD_RETENTION_ISOLATION_LOWPWR,
+ S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
+ S5P_XUSBXTI_LOWPWR,
+ S5P_XXTI_LOWPWR,
+ S5P_EXT_REGULATOR_LOWPWR,
+ S5P_GPIO_MODE_LOWPWR,
+ S5P_GPIO_MODE_MAUDIO_LOWPWR,
+ S5P_CAM_LOWPWR,
+ S5P_TV_LOWPWR,
+ S5P_MFC_LOWPWR,
+ S5P_G3D_LOWPWR,
+ S5P_LCD0_LOWPWR,
+ S5P_LCD1_LOWPWR,
+ S5P_MAUDIO_LOWPWR,
+ S5P_GPS_LOWPWR,
+ S5P_GPS_ALIVE_LOWPWR,
+};
+
+static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
+ /* { AFTR, LPA, SLEEP }*/
+ { 0, 0, 2 }, /* ARM_CORE0 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
+ { 0, 0, 2 }, /* ARM_CORE1 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
+ { 0, 0, 2 }, /* ARM_COMMON */
+ { 2, 2, 3 }, /* ARM_CPU_L2_0 */
+ { 2, 2, 3 }, /* ARM_CPU_L2_1 */
+ { 1, 0, 0 }, /* CMU_ACLKSTOP */
+ { 1, 0, 0 }, /* CMU_SCLKSTOP */
+ { 1, 1, 0 }, /* CMU_RESET */
+ { 1, 0, 0 }, /* APLL_SYSCLK */
+ { 1, 0, 0 }, /* MPLL_SYSCLK */
+ { 1, 0, 0 }, /* VPLL_SYSCLK */
+ { 1, 1, 0 }, /* EPLL_SYSCLK */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
+ { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_TV */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
+ { 1, 1, 0 }, /* CMU_RESET_CAM */
+ { 1, 1, 0 }, /* CMU_RESET_TV */
+ { 1, 1, 0 }, /* CMU_RESET_MFC */
+ { 1, 1, 0 }, /* CMU_RESET_G3D */
+ { 1, 1, 0 }, /* CMU_RESET_LCD0 */
+ { 1, 1, 0 }, /* CMU_RESET_LCD1 */
+ { 1, 1, 0 }, /* CMU_RESET_MAUDIO */
+ { 1, 1, 0 }, /* CMU_RESET_GPS */
+ { 3, 0, 0 }, /* TOP_BUS */
+ { 1, 0, 1 }, /* TOP_RETENTION */
+ { 3, 0, 3 }, /* TOP_PWR */
+ { 1, 1, 0 }, /* LOGIC_RESET */
+ { 3, 0, 0 }, /* ONENAND_MEM */
+ { 3, 0, 0 }, /* MODIMIF_MEM */
+ { 3, 0, 0 }, /* G2D_ACP_MEM */
+ { 3, 0, 0 }, /* USBOTG_MEM */
+ { 3, 0, 0 }, /* HSMMC_MEM */
+ { 3, 0, 0 }, /* CSSYS_MEM */
+ { 3, 0, 0 }, /* SECSS_MEM */
+ { 3, 0, 0 }, /* PCIE_MEM */
+ { 3, 0, 0 }, /* SATA_MEM */
+ { 1, 0, 0 }, /* PAD_RETENTION_DRAM */
+ { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
+ { 1, 0, 0 }, /* PAD_RETENTION_GPIO */
+ { 1, 0, 0 }, /* PAD_RETENTION_UART */
+ { 1, 0, 0 }, /* PAD_RETENTION_MMCA */
+ { 1, 0, 0 }, /* PAD_RETENTION_MMCB */
+ { 1, 0, 0 }, /* PAD_RETENTION_EBIA */
+ { 1, 0, 0 }, /* PAD_RETENTION_EBIB */
+ { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
+ { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
+ { 1, 1, 0 }, /* XUSBXTI */
+ { 1, 1, 0 }, /* XXTI */
+ { 1, 1, 0 }, /* EXT_REGULATOR */
+ { 1, 0, 0 }, /* GPIO_MODE */
+ { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
+ { 7, 0, 0 }, /* CAM */
+ { 7, 0, 0 }, /* TV */
+ { 7, 0, 0 }, /* MFC */
+ { 7, 0, 0 }, /* G3D */
+ { 7, 0, 0 }, /* LCD0 */
+ { 7, 0, 0 }, /* LCD1 */
+ { 7, 7, 0 }, /* MAUDIO */
+ { 7, 0, 0 }, /* GPS */
+ { 7, 0, 0 }, /* GPS_ALIVE */
+};
+
+void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
+{
+ unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
+
+ for (; count > 0; count--)
+ __raw_writel(sys_powerdown_val[count - 1][mode],
+ sys_powerdown_reg[count - 1]);
+}
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 2/8] ARM: EXYNOS4: Remove PMU configuration for S2RAM
2011-07-01 1:57 ` Kukjin Kim
@ 2011-07-01 1:57 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jaecheol Lee, Kukjin Kim
From: Jaecheol Lee <jc.lee@samsung.com>
PMU(Power Management Unit) configuraion for S2RAM(SLEEP) is removed
and using function which provided by PMU support code to configure
PMU register.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/pm.c | 77 +------------------------------------------
1 files changed, 2 insertions(+), 75 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 5c01c60..4d9ee97 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -30,80 +30,7 @@
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
#include <mach/pm-core.h>
-
-static struct sleep_save exynos4_sleep[] = {
- { .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
- { .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
- { .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
- { .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
- { .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
- { .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
- { .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
- { .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
- { .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
- { .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
- { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
- { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
- { .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
- { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
- { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
- { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
- { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
- { .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
- { .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_CAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_TV_LOWPWR , .val = 0x0, },
- { .reg = S5P_MFC_LOWPWR , .val = 0x0, },
- { .reg = S5P_G3D_LOWPWR , .val = 0x0, },
- { .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
- { .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
- { .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPS_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
-};
+#include <mach/pmu.h>
static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
@@ -331,7 +258,7 @@ static void exynos4_pm_prepare(void)
/* Set value of power down register for sleep mode */
- s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
+ exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 2/8] ARM: EXYNOS4: Remove PMU configuration for S2RAM
@ 2011-07-01 1:57 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Jaecheol Lee <jc.lee@samsung.com>
PMU(Power Management Unit) configuraion for S2RAM(SLEEP) is removed
and using function which provided by PMU support code to configure
PMU register.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/pm.c | 77 +------------------------------------------
1 files changed, 2 insertions(+), 75 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 5c01c60..4d9ee97 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -30,80 +30,7 @@
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
#include <mach/pm-core.h>
-
-static struct sleep_save exynos4_sleep[] = {
- { .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
- { .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
- { .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
- { .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
- { .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
- { .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
- { .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
- { .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
- { .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
- { .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
- { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
- { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
- { .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
- { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
- { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
- { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
- { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
- { .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
- { .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_CAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_TV_LOWPWR , .val = 0x0, },
- { .reg = S5P_MFC_LOWPWR , .val = 0x0, },
- { .reg = S5P_G3D_LOWPWR , .val = 0x0, },
- { .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
- { .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
- { .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPS_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
-};
+#include <mach/pmu.h>
static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
@@ -331,7 +258,7 @@ static void exynos4_pm_prepare(void)
/* Set value of power down register for sleep mode */
- s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
+ exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
2011-07-01 1:57 ` Kukjin Kim
@ 2011-07-01 1:57 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jaecheol Lee, Kukjin Kim
From: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/pm.c | 43 +++++++++++++++++++++++++++++++++++++------
1 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 4d9ee97..9b5f3a5 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -154,6 +154,22 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x460),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x464),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x468),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x46C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x470),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x474),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x478),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x47C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x480),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x484),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x488),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x48C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x490),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x494),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x498),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x49C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
@@ -179,6 +195,22 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x860),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x864),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x868),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x86C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x870),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x874),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x878),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x87C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x880),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x884),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x888),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x88C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x890),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x894),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x898),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x89C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
@@ -186,17 +218,16 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0xC18),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0xC1C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0xC20),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0xC24),
+
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
};
static struct sleep_save exynos4_l2cc_save[] = {
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
@ 2011-07-01 1:57 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/pm.c | 43 +++++++++++++++++++++++++++++++++++++------
1 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 4d9ee97..9b5f3a5 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -154,6 +154,22 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x460),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x464),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x468),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x46C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x470),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x474),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x478),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x47C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x480),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x484),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x488),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x48C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x490),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x494),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x498),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x49C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
@@ -179,6 +195,22 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x860),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x864),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x868),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x86C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x870),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x874),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x878),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x87C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x880),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x884),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x888),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x88C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x890),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x894),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x898),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0x89C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
@@ -186,17 +218,16 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0xC18),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0xC1C),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0xC20),
+ SAVE_ITEM(S5P_VA_GIC_DIST + 0xC24),
+
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
- SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
};
static struct sleep_save exynos4_l2cc_save[] = {
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 4/8] ARM: SAMSUNG: Add support for failure of sleep mode
2011-07-01 1:57 ` Kukjin Kim
@ 2011-07-01 1:57 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jaecheol Lee, Kukjin Kim
From: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/plat-samsung/pm.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 69d6b04..df12645 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -299,7 +299,10 @@ static int s3c_pm_enter(suspend_state_t state)
* we resume as it saves its own register state and restores it
* during the resume. */
- cpu_suspend(0, pm_cpu_sleep);
+ /* If entering sleep mode is failed, non-zero value is returned */
+
+ if (cpu_suspend(0, pm_cpu_sleep));
+ goto exit;
/* restore the system state */
@@ -323,6 +326,8 @@ static int s3c_pm_enter(suspend_state_t state)
/* ok, let's return from sleep */
S3C_PMDBG("S3C PM Resume (post-restore)\n");
+
+exit:
return 0;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 4/8] ARM: SAMSUNG: Add support for failure of sleep mode
@ 2011-07-01 1:57 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/plat-samsung/pm.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 69d6b04..df12645 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -299,7 +299,10 @@ static int s3c_pm_enter(suspend_state_t state)
* we resume as it saves its own register state and restores it
* during the resume. */
- cpu_suspend(0, pm_cpu_sleep);
+ /* If entering sleep mode is failed, non-zero value is returned */
+
+ if (cpu_suspend(0, pm_cpu_sleep));
+ goto exit;
/* restore the system state */
@@ -323,6 +326,8 @@ static int s3c_pm_enter(suspend_state_t state)
/* ok, let's return from sleep */
S3C_PMDBG("S3C PM Resume (post-restore)\n");
+
+exit:
return 0;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 5/8] ARM: EXYNOS4: Support early wakeup entering sleep mode
2011-07-01 1:57 ` Kukjin Kim
@ 2011-07-01 1:57 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jaecheol Lee, Kukjin Kim
From: Jaecheol Lee <jc.lee@samsung.com>
Since early wakeup can be handled in pm so we don't need masking
interrupts of external GIC. When the early wakeup interrupt happens,
PMU(Power Management Unit) ignores WFI instruction. This means that
PC(Program Counter) passed without any changes. This patch can handle
that case by early wakeup interrupt.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/pm.c | 43 +++++++++++++++++++------------------------
1 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 9b5f3a5..17d43c2 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -241,7 +241,6 @@ static struct sleep_save exynos4_l2cc_save[] = {
void exynos4_cpu_suspend(unsigned long arg)
{
unsigned long tmp;
- unsigned long mask = 0xFFFFFFFF;
/* Setting Central Sequence Register for power down mode */
@@ -249,33 +248,10 @@ void exynos4_cpu_suspend(unsigned long arg)
tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
- /* Setting Central Sequence option Register */
-
- tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
- tmp &= ~(S5P_USE_MASK);
- tmp |= S5P_USE_STANDBY_WFI0;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-
- /* Clear all interrupt pending to avoid early wakeup */
-
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
-
- /* Disable all interrupt */
-
- __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
- __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
-
outer_flush_all();
/* issue the standby signal into the pm unit. */
cpu_do_idle();
-
- /* we should never get past here */
- panic("sleep resumed to originator?");
}
static void exynos4_pm_prepare(void)
@@ -353,6 +329,22 @@ arch_initcall(exynos4_pm_drvinit);
static void exynos4_pm_resume(void)
{
+ unsigned long tmp;
+
+ /*
+ * If PMU failed while entering sleep mode, WFI will be
+ * ignored by PMU and then exiting cpu_do_idle().
+ * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+ * in this situation.
+ */
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+ tmp |= S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ /* No need to perform below restore code */
+ goto early_wakeup;
+ }
+
/* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -373,6 +365,9 @@ static void exynos4_pm_resume(void)
/* enable L2X0*/
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
#endif
+
+early_wakeup:
+ return;
}
static struct syscore_ops exynos4_pm_syscore_ops = {
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 5/8] ARM: EXYNOS4: Support early wakeup entering sleep mode
@ 2011-07-01 1:57 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Jaecheol Lee <jc.lee@samsung.com>
Since early wakeup can be handled in pm so we don't need masking
interrupts of external GIC. When the early wakeup interrupt happens,
PMU(Power Management Unit) ignores WFI instruction. This means that
PC(Program Counter) passed without any changes. This patch can handle
that case by early wakeup interrupt.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/pm.c | 43 +++++++++++++++++++------------------------
1 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 9b5f3a5..17d43c2 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -241,7 +241,6 @@ static struct sleep_save exynos4_l2cc_save[] = {
void exynos4_cpu_suspend(unsigned long arg)
{
unsigned long tmp;
- unsigned long mask = 0xFFFFFFFF;
/* Setting Central Sequence Register for power down mode */
@@ -249,33 +248,10 @@ void exynos4_cpu_suspend(unsigned long arg)
tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
- /* Setting Central Sequence option Register */
-
- tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
- tmp &= ~(S5P_USE_MASK);
- tmp |= S5P_USE_STANDBY_WFI0;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-
- /* Clear all interrupt pending to avoid early wakeup */
-
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
-
- /* Disable all interrupt */
-
- __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
- __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
-
outer_flush_all();
/* issue the standby signal into the pm unit. */
cpu_do_idle();
-
- /* we should never get past here */
- panic("sleep resumed to originator?");
}
static void exynos4_pm_prepare(void)
@@ -353,6 +329,22 @@ arch_initcall(exynos4_pm_drvinit);
static void exynos4_pm_resume(void)
{
+ unsigned long tmp;
+
+ /*
+ * If PMU failed while entering sleep mode, WFI will be
+ * ignored by PMU and then exiting cpu_do_idle().
+ * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+ * in this situation.
+ */
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+ tmp |= S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ /* No need to perform below restore code */
+ goto early_wakeup;
+ }
+
/* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -373,6 +365,9 @@ static void exynos4_pm_resume(void)
/* enable L2X0*/
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
#endif
+
+early_wakeup:
+ return;
}
static struct syscore_ops exynos4_pm_syscore_ops = {
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 6/8] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION setting for PM
2011-07-01 1:57 ` Kukjin Kim
@ 2011-07-01 1:57 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jaecheol Lee, Kukjin Kim
From: Jaecheol Lee <jc.lee@samsung.com>
We need to balance between set and check S5P_CENTRAL_SEQ_CONFIGURATION
register in syscore_ops suspend/resume function when failure in enter
suspend mode. Moved this register setting for PM for the purpose of balancing.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/pm.c | 22 ++++++++++++++--------
1 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 17d43c2..a658318 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -240,14 +240,6 @@ static struct sleep_save exynos4_l2cc_save[] = {
void exynos4_cpu_suspend(unsigned long arg)
{
- unsigned long tmp;
-
- /* Setting Central Sequence Register for power down mode */
-
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
- tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
outer_flush_all();
/* issue the standby signal into the pm unit. */
@@ -327,6 +319,19 @@ static __init int exynos4_pm_drvinit(void)
}
arch_initcall(exynos4_pm_drvinit);
+static int exynos4_pm_suspend(void)
+{
+ unsigned long tmp;
+
+ /* Setting Central Sequence Register for power down mode */
+
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+ return 0;
+}
+
static void exynos4_pm_resume(void)
{
unsigned long tmp;
@@ -371,6 +376,7 @@ early_wakeup:
}
static struct syscore_ops exynos4_pm_syscore_ops = {
+ .suspend = exynos4_pm_suspend,
.resume = exynos4_pm_resume,
};
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 6/8] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION setting for PM
@ 2011-07-01 1:57 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Jaecheol Lee <jc.lee@samsung.com>
We need to balance between set and check S5P_CENTRAL_SEQ_CONFIGURATION
register in syscore_ops suspend/resume function when failure in enter
suspend mode. Moved this register setting for PM for the purpose of balancing.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/pm.c | 22 ++++++++++++++--------
1 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 17d43c2..a658318 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -240,14 +240,6 @@ static struct sleep_save exynos4_l2cc_save[] = {
void exynos4_cpu_suspend(unsigned long arg)
{
- unsigned long tmp;
-
- /* Setting Central Sequence Register for power down mode */
-
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
- tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
outer_flush_all();
/* issue the standby signal into the pm unit. */
@@ -327,6 +319,19 @@ static __init int exynos4_pm_drvinit(void)
}
arch_initcall(exynos4_pm_drvinit);
+static int exynos4_pm_suspend(void)
+{
+ unsigned long tmp;
+
+ /* Setting Central Sequence Register for power down mode */
+
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+ return 0;
+}
+
static void exynos4_pm_resume(void)
{
unsigned long tmp;
@@ -371,6 +376,7 @@ early_wakeup:
}
static struct syscore_ops exynos4_pm_syscore_ops = {
+ .suspend = exynos4_pm_suspend,
.resume = exynos4_pm_resume,
};
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 7/8] ARM: EXYNOS4: Add save/restore for other ARM registers
2011-07-01 1:57 ` Kukjin Kim
@ 2011-07-01 1:57 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jaecheol Lee, Kukjin Kim
From: Jaecheol Lee <jc.lee@samsung.com>
This patch adds save/restore values for Power Control Register and
Diagnostic Register for PM.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/pm.c | 24 ++++++++++++++++++++++++
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index a658318..4130e5a 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -238,6 +238,9 @@ static struct sleep_save exynos4_l2cc_save[] = {
SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
};
+/* For Cortex-A9 Diagnostic and Power control register */
+static unsigned int save_arm_register[2];
+
void exynos4_cpu_suspend(unsigned long arg)
{
outer_flush_all();
@@ -329,6 +332,16 @@ static int exynos4_pm_suspend(void)
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ /* Save Power control register */
+ asm ("mrc p15, 0, %0, c15, c0, 0"
+ : "=r" (tmp) : : "cc");
+ save_arm_register[0] = tmp;
+
+ /* Save Diagnostic register */
+ asm ("mrc p15, 0, %0, c15, c0, 1"
+ : "=r" (tmp) : : "cc");
+ save_arm_register[1] = tmp;
+
return 0;
}
@@ -349,6 +362,17 @@ static void exynos4_pm_resume(void)
/* No need to perform below restore code */
goto early_wakeup;
}
+ /* Restore Power control register */
+ tmp = save_arm_register[0];
+ asm volatile ("mcr p15, 0, %0, c15, c0, 0"
+ : : "r" (tmp)
+ : "cc");
+
+ /* Restore Diagnostic register */
+ tmp = save_arm_register[1];
+ asm volatile ("mcr p15, 0, %0, c15, c0, 1"
+ : : "r" (tmp)
+ : "cc");
/* For release retention */
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 7/8] ARM: EXYNOS4: Add save/restore for other ARM registers
@ 2011-07-01 1:57 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Jaecheol Lee <jc.lee@samsung.com>
This patch adds save/restore values for Power Control Register and
Diagnostic Register for PM.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/pm.c | 24 ++++++++++++++++++++++++
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index a658318..4130e5a 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -238,6 +238,9 @@ static struct sleep_save exynos4_l2cc_save[] = {
SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
};
+/* For Cortex-A9 Diagnostic and Power control register */
+static unsigned int save_arm_register[2];
+
void exynos4_cpu_suspend(unsigned long arg)
{
outer_flush_all();
@@ -329,6 +332,16 @@ static int exynos4_pm_suspend(void)
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ /* Save Power control register */
+ asm ("mrc p15, 0, %0, c15, c0, 0"
+ : "=r" (tmp) : : "cc");
+ save_arm_register[0] = tmp;
+
+ /* Save Diagnostic register */
+ asm ("mrc p15, 0, %0, c15, c0, 1"
+ : "=r" (tmp) : : "cc");
+ save_arm_register[1] = tmp;
+
return 0;
}
@@ -349,6 +362,17 @@ static void exynos4_pm_resume(void)
/* No need to perform below restore code */
goto early_wakeup;
}
+ /* Restore Power control register */
+ tmp = save_arm_register[0];
+ asm volatile ("mcr p15, 0, %0, c15, c0, 0"
+ : : "r" (tmp)
+ : "cc");
+
+ /* Restore Diagnostic register */
+ tmp = save_arm_register[1];
+ asm volatile ("mcr p15, 0, %0, c15, c0, 1"
+ : : "r" (tmp)
+ : "cc");
/* For release retention */
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 8/8] ARM: EXYNOS4: Add save/restore function for PLL
2011-07-01 1:57 ` Kukjin Kim
@ 2011-07-01 1:57 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jaecheol Lee, Kukjin Kim
From: Jaecheol Lee <jc.lee@samsung.com>
The PLL restore routine supports waiting pll locking. If PLL is
enabled in restoring sequence, it should wait until PLL is locked.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/include/mach/regs-clock.h | 9 ++
arch/arm/mach-exynos4/pm.c | 96 ++++++++++++++++++++++-
2 files changed, 101 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1..64bdd24 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
+#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
+#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
+
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
@@ -120,6 +123,12 @@
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
+#define S5P_EPLLCON0_ENABLE_SHIFT (31)
+#define S5P_EPLLCON0_LOCKED_SHIFT (29)
+
+#define S5P_VPLLCON0_ENABLE_SHIFT (31)
+#define S5P_VPLLCON0_LOCKED_SHIFT (29)
+
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 4130e5a..e3d4147 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -18,12 +18,15 @@
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <plat/cpu.h>
#include <plat/pm.h>
+#include <plat/pll.h>
#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>
@@ -45,16 +48,22 @@ static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
};
+static struct sleep_save exynos4_epll_save[] = {
+ SAVE_ITEM(S5P_EPLL_CON0),
+ SAVE_ITEM(S5P_EPLL_CON1),
+};
+
+static struct sleep_save exynos4_vpll_save[] = {
+ SAVE_ITEM(S5P_VPLL_CON0),
+ SAVE_ITEM(S5P_VPLL_CON1),
+};
+
static struct sleep_save exynos4_core_save[] = {
/* CMU side */
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
- SAVE_ITEM(S5P_EPLL_CON0),
- SAVE_ITEM(S5P_EPLL_CON1),
- SAVE_ITEM(S5P_VPLL_CON0),
- SAVE_ITEM(S5P_VPLL_CON1),
SAVE_ITEM(S5P_CLKSRC_TOP0),
SAVE_ITEM(S5P_CLKSRC_TOP1),
SAVE_ITEM(S5P_CLKSRC_CAM),
@@ -255,6 +264,8 @@ static void exynos4_pm_prepare(void)
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+ s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
+ s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
tmp = __raw_readl(S5P_INFORM1);
@@ -302,12 +313,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
flush_cache_all();
}
+static unsigned long pll_base_rate;
+
+static void exynos4_restore_pll(void)
+{
+ unsigned long pll_con, locktime, lockcnt;
+ unsigned long pll_in_rate;
+ unsigned int p_div, epll_wait = 0, vpll_wait = 0;
+
+ if (pll_base_rate == 0)
+ return;
+
+ pll_in_rate = pll_base_rate;
+
+ /* EPLL */
+ pll_con = exynos4_epll_save[0].val;
+
+ if (pll_con & (1 << 31)) {
+ pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
+ p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
+
+ pll_in_rate /= 1000000;
+
+ locktime = (3000 / pll_in_rate) * p_div;
+ lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+ __raw_writel(lockcnt, S5P_EPLL_LOCK);
+
+ s3c_pm_do_restore_core(exynos4_epll_save,
+ ARRAY_SIZE(exynos4_epll_save));
+ epll_wait = 1;
+ }
+
+ pll_in_rate = pll_base_rate;
+
+ /* VPLL */
+ pll_con = exynos4_vpll_save[0].val;
+
+ if (pll_con & (1 << 31)) {
+ pll_in_rate /= 1000000;
+ /* 750us */
+ locktime = 750;
+ lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+ __raw_writel(lockcnt, S5P_VPLL_LOCK);
+
+ s3c_pm_do_restore_core(exynos4_vpll_save,
+ ARRAY_SIZE(exynos4_vpll_save));
+ vpll_wait = 1;
+ }
+
+ /* Wait PLL locking */
+
+ do {
+ if (epll_wait) {
+ pll_con = __raw_readl(S5P_EPLL_CON0);
+ if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+ epll_wait = 0;
+ }
+
+ if (vpll_wait) {
+ pll_con = __raw_readl(S5P_VPLL_CON0);
+ if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+ vpll_wait = 0;
+ }
+ } while (epll_wait || vpll_wait);
+}
+
static struct sysdev_driver exynos4_pm_driver = {
.add = exynos4_pm_add,
};
static __init int exynos4_pm_drvinit(void)
{
+ struct clk *pll_base;
unsigned int tmp;
s3c_pm_init();
@@ -318,6 +397,13 @@ static __init int exynos4_pm_drvinit(void)
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
+ pll_base = clk_get(NULL, "xtal");
+
+ if (!IS_ERR(pll_base)) {
+ pll_base_rate = clk_get_rate(pll_base);
+ clk_put(pll_base);
+ }
+
return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
}
arch_initcall(exynos4_pm_drvinit);
@@ -386,6 +472,8 @@ static void exynos4_pm_resume(void)
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+ exynos4_restore_pll();
+
exynos4_scu_enable(S5P_VA_SCU);
#ifdef CONFIG_CACHE_L2X0
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 8/8] ARM: EXYNOS4: Add save/restore function for PLL
@ 2011-07-01 1:57 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-01 1:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Jaecheol Lee <jc.lee@samsung.com>
The PLL restore routine supports waiting pll locking. If PLL is
enabled in restoring sequence, it should wait until PLL is locked.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/include/mach/regs-clock.h | 9 ++
arch/arm/mach-exynos4/pm.c | 96 ++++++++++++++++++++++-
2 files changed, 101 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1..64bdd24 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
+#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
+#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
+
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
@@ -120,6 +123,12 @@
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
+#define S5P_EPLLCON0_ENABLE_SHIFT (31)
+#define S5P_EPLLCON0_LOCKED_SHIFT (29)
+
+#define S5P_VPLLCON0_ENABLE_SHIFT (31)
+#define S5P_VPLLCON0_LOCKED_SHIFT (29)
+
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 4130e5a..e3d4147 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -18,12 +18,15 @@
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <plat/cpu.h>
#include <plat/pm.h>
+#include <plat/pll.h>
#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>
@@ -45,16 +48,22 @@ static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
};
+static struct sleep_save exynos4_epll_save[] = {
+ SAVE_ITEM(S5P_EPLL_CON0),
+ SAVE_ITEM(S5P_EPLL_CON1),
+};
+
+static struct sleep_save exynos4_vpll_save[] = {
+ SAVE_ITEM(S5P_VPLL_CON0),
+ SAVE_ITEM(S5P_VPLL_CON1),
+};
+
static struct sleep_save exynos4_core_save[] = {
/* CMU side */
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
- SAVE_ITEM(S5P_EPLL_CON0),
- SAVE_ITEM(S5P_EPLL_CON1),
- SAVE_ITEM(S5P_VPLL_CON0),
- SAVE_ITEM(S5P_VPLL_CON1),
SAVE_ITEM(S5P_CLKSRC_TOP0),
SAVE_ITEM(S5P_CLKSRC_TOP1),
SAVE_ITEM(S5P_CLKSRC_CAM),
@@ -255,6 +264,8 @@ static void exynos4_pm_prepare(void)
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+ s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
+ s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
tmp = __raw_readl(S5P_INFORM1);
@@ -302,12 +313,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
flush_cache_all();
}
+static unsigned long pll_base_rate;
+
+static void exynos4_restore_pll(void)
+{
+ unsigned long pll_con, locktime, lockcnt;
+ unsigned long pll_in_rate;
+ unsigned int p_div, epll_wait = 0, vpll_wait = 0;
+
+ if (pll_base_rate == 0)
+ return;
+
+ pll_in_rate = pll_base_rate;
+
+ /* EPLL */
+ pll_con = exynos4_epll_save[0].val;
+
+ if (pll_con & (1 << 31)) {
+ pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
+ p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
+
+ pll_in_rate /= 1000000;
+
+ locktime = (3000 / pll_in_rate) * p_div;
+ lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+ __raw_writel(lockcnt, S5P_EPLL_LOCK);
+
+ s3c_pm_do_restore_core(exynos4_epll_save,
+ ARRAY_SIZE(exynos4_epll_save));
+ epll_wait = 1;
+ }
+
+ pll_in_rate = pll_base_rate;
+
+ /* VPLL */
+ pll_con = exynos4_vpll_save[0].val;
+
+ if (pll_con & (1 << 31)) {
+ pll_in_rate /= 1000000;
+ /* 750us */
+ locktime = 750;
+ lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+ __raw_writel(lockcnt, S5P_VPLL_LOCK);
+
+ s3c_pm_do_restore_core(exynos4_vpll_save,
+ ARRAY_SIZE(exynos4_vpll_save));
+ vpll_wait = 1;
+ }
+
+ /* Wait PLL locking */
+
+ do {
+ if (epll_wait) {
+ pll_con = __raw_readl(S5P_EPLL_CON0);
+ if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+ epll_wait = 0;
+ }
+
+ if (vpll_wait) {
+ pll_con = __raw_readl(S5P_VPLL_CON0);
+ if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+ vpll_wait = 0;
+ }
+ } while (epll_wait || vpll_wait);
+}
+
static struct sysdev_driver exynos4_pm_driver = {
.add = exynos4_pm_add,
};
static __init int exynos4_pm_drvinit(void)
{
+ struct clk *pll_base;
unsigned int tmp;
s3c_pm_init();
@@ -318,6 +397,13 @@ static __init int exynos4_pm_drvinit(void)
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
+ pll_base = clk_get(NULL, "xtal");
+
+ if (!IS_ERR(pll_base)) {
+ pll_base_rate = clk_get_rate(pll_base);
+ clk_put(pll_base);
+ }
+
return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
}
arch_initcall(exynos4_pm_drvinit);
@@ -386,6 +472,8 @@ static void exynos4_pm_resume(void)
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+ exynos4_restore_pll();
+
exynos4_scu_enable(S5P_VA_SCU);
#ifdef CONFIG_CACHE_L2X0
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
2011-07-01 1:57 ` Kukjin Kim
@ 2011-07-01 21:21 ` Russell King - ARM Linux
-1 siblings, 0 replies; 28+ messages in thread
From: Russell King - ARM Linux @ 2011-07-01 21:21 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-arm-kernel, linux-samsung-soc, Jaecheol Lee, ben-linux
On Fri, Jul 01, 2011 at 10:57:32AM +0900, Kukjin Kim wrote:
> From: Jaecheol Lee <jc.lee@samsung.com>
>
> Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Why not fix arch/arm/common/gic.c to save and restore the GIC state
itself?
You really need to start thinking bigger than just Samsung with this
stuff - we can't have SoC people addressing these obviously common
issues within their own code and duplicating it across all SoCs. We
_need_ you folk to start thinking about implementing common support
where its needed.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
@ 2011-07-01 21:21 ` Russell King - ARM Linux
0 siblings, 0 replies; 28+ messages in thread
From: Russell King - ARM Linux @ 2011-07-01 21:21 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 01, 2011 at 10:57:32AM +0900, Kukjin Kim wrote:
> From: Jaecheol Lee <jc.lee@samsung.com>
>
> Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Why not fix arch/arm/common/gic.c to save and restore the GIC state
itself?
You really need to start thinking bigger than just Samsung with this
stuff - we can't have SoC people addressing these obviously common
issues within their own code and duplicating it across all SoCs. We
_need_ you folk to start thinking about implementing common support
where its needed.
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
2011-07-01 21:21 ` Russell King - ARM Linux
@ 2011-07-04 9:35 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-04 9:35 UTC (permalink / raw)
To: 'Russell King - ARM Linux'
Cc: linux-arm-kernel, linux-samsung-soc, 'Jaecheol Lee',
ben-linux, 'Colin Cross'
Russell King - ARM Linux wrote:
>
> Why not fix arch/arm/common/gic.c to save and restore the GIC state
> itself?
>
Sorry I missed that. I saw "ARM: gic: Use cpu pm notifiers to save gic
state" by Colin Cross just now so will follow that up for supporting Samsung
SoCs which use GIC.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
@ 2011-07-04 9:35 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-04 9:35 UTC (permalink / raw)
To: linux-arm-kernel
Russell King - ARM Linux wrote:
>
> Why not fix arch/arm/common/gic.c to save and restore the GIC state
> itself?
>
Sorry I missed that. I saw "ARM: gic: Use cpu pm notifiers to save gic
state" by Colin Cross just now so will follow that up for supporting Samsung
SoCs which use GIC.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
2011-07-01 21:21 ` Russell King - ARM Linux
@ 2011-07-08 7:21 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-08 7:21 UTC (permalink / raw)
To: 'Kukjin Kim', 'Russell King - ARM Linux'
Cc: linux-arm-kernel, linux-samsung-soc, 'Jaecheol Lee',
ben-linux, 'Colin Cross'
Kukjin Kim wrote:
>
> Russell King - ARM Linux wrote:
> >
> > Why not fix arch/arm/common/gic.c to save and restore the GIC state
> > itself?
> >
> Sorry I missed that. I saw "ARM: gic: Use cpu pm notifiers to save gic
state" by
> Colin Cross just now so will follow that up for supporting Samsung SoCs
which
> use GIC.
>
Hi Russell,
We tested this with Colin's "ARM: gic: Use cpu pm notifiers to save gic
state" and it works fine.
So right now we don't need to add some stuff of GIC in common but I'm not
sure how it was going on...
Anyway how do you think that firstly I apply these into -next? If this
commit is not required will rebase(to remove existing save/restore GIC)
before pull request.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
@ 2011-07-08 7:21 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-08 7:21 UTC (permalink / raw)
To: linux-arm-kernel
Kukjin Kim wrote:
>
> Russell King - ARM Linux wrote:
> >
> > Why not fix arch/arm/common/gic.c to save and restore the GIC state
> > itself?
> >
> Sorry I missed that. I saw "ARM: gic: Use cpu pm notifiers to save gic
state" by
> Colin Cross just now so will follow that up for supporting Samsung SoCs
which
> use GIC.
>
Hi Russell,
We tested this with Colin's "ARM: gic: Use cpu pm notifiers to save gic
state" and it works fine.
So right now we don't need to add some stuff of GIC in common but I'm not
sure how it was going on...
Anyway how do you think that firstly I apply these into -next? If this
commit is not required will rebase(to remove existing save/restore GIC)
before pull request.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH V2 0/8] ARM: EXYNOS4: Update PM
2011-07-01 1:57 ` Kukjin Kim
@ 2011-07-18 8:00 ` Kukjin Kim
-1 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-18 8:00 UTC (permalink / raw)
To: 'Kukjin Kim', linux-arm-kernel, linux-samsung-soc
Cc: ben-linux, 'Russell King - ARM Linux'
Kukjin Kim wrote:
>
> This patch updates EXYNOS4 PM based on Russell's suspend consolidation
> patches.
>
> NOTE: Depends on external GIC patches which are from Changhwan Youn.
>
> Changes since V1:
> - address comments from Russell King
>
> [PATCH V2 1/8] ARM: EXYNOS4: Support system level power down configuration
> [PATCH V2 2/8] ARM: EXYNOS4: Remove PMU configuration for S2RAM
> [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
> [PATCH V2 4/8] ARM: SAMSUNG: Add support for failure of sleep mode
> [PATCH V2 5/8] ARM: EXYNOS4: Support early wakeup entering sleep mode
> [PATCH V2 6/8] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION
> setting for PM
> [PATCH V2 7/8] ARM: EXYNOS4: Add save/restore for other ARM registers
> [PATCH V2 8/8] ARM: EXYNOS4: Add save/restore function for PLL
Hi Russell and all,
I'm going to merge this whole series in my for-next except 3rd and 4th
patches late today.
The 3rd patch can be replaced with Colin's regarding suspend-to-ram GIC and
the 4th patch is not needed now because it's ok with Russell's suspend
patch.
If any problems, please let me know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 0/8] ARM: EXYNOS4: Update PM
@ 2011-07-18 8:00 ` Kukjin Kim
0 siblings, 0 replies; 28+ messages in thread
From: Kukjin Kim @ 2011-07-18 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Kukjin Kim wrote:
>
> This patch updates EXYNOS4 PM based on Russell's suspend consolidation
> patches.
>
> NOTE: Depends on external GIC patches which are from Changhwan Youn.
>
> Changes since V1:
> - address comments from Russell King
>
> [PATCH V2 1/8] ARM: EXYNOS4: Support system level power down configuration
> [PATCH V2 2/8] ARM: EXYNOS4: Remove PMU configuration for S2RAM
> [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
> [PATCH V2 4/8] ARM: SAMSUNG: Add support for failure of sleep mode
> [PATCH V2 5/8] ARM: EXYNOS4: Support early wakeup entering sleep mode
> [PATCH V2 6/8] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION
> setting for PM
> [PATCH V2 7/8] ARM: EXYNOS4: Add save/restore for other ARM registers
> [PATCH V2 8/8] ARM: EXYNOS4: Add save/restore function for PLL
Hi Russell and all,
I'm going to merge this whole series in my for-next except 3rd and 4th
patches late today.
The 3rd patch can be replaced with Colin's regarding suspend-to-ram GIC and
the 4th patch is not needed now because it's ok with Russell's suspend
patch.
If any problems, please let me know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH V2 0/8] ARM: EXYNOS4: Update PM
2011-07-18 8:00 ` Kukjin Kim
@ 2011-07-18 10:16 ` Russell King - ARM Linux
-1 siblings, 0 replies; 28+ messages in thread
From: Russell King - ARM Linux @ 2011-07-18 10:16 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-arm-kernel, linux-samsung-soc, ben-linux
On Mon, Jul 18, 2011 at 05:00:56PM +0900, Kukjin Kim wrote:
> I'm going to merge this whole series in my for-next except 3rd and 4th
> patches late today.
> The 3rd patch can be replaced with Colin's regarding suspend-to-ram GIC and
> the 4th patch is not needed now because it's ok with Russell's suspend
> patch.
Ok.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 0/8] ARM: EXYNOS4: Update PM
@ 2011-07-18 10:16 ` Russell King - ARM Linux
0 siblings, 0 replies; 28+ messages in thread
From: Russell King - ARM Linux @ 2011-07-18 10:16 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 18, 2011 at 05:00:56PM +0900, Kukjin Kim wrote:
> I'm going to merge this whole series in my for-next except 3rd and 4th
> patches late today.
> The 3rd patch can be replaced with Colin's regarding suspend-to-ram GIC and
> the 4th patch is not needed now because it's ok with Russell's suspend
> patch.
Ok.
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2011-07-18 10:16 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-07-01 1:57 [PATCH V2 0/8] ARM: EXYNOS4: Update PM Kukjin Kim
2011-07-01 1:57 ` Kukjin Kim
2011-07-01 1:57 ` [PATCH V2 1/8] ARM: EXYNOS4: Support system level power down configuration Kukjin Kim
2011-07-01 1:57 ` Kukjin Kim
2011-07-01 1:57 ` [PATCH V2 2/8] ARM: EXYNOS4: Remove PMU configuration for S2RAM Kukjin Kim
2011-07-01 1:57 ` Kukjin Kim
2011-07-01 1:57 ` [PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC Kukjin Kim
2011-07-01 1:57 ` Kukjin Kim
2011-07-01 21:21 ` Russell King - ARM Linux
2011-07-01 21:21 ` Russell King - ARM Linux
2011-07-04 9:35 ` Kukjin Kim
2011-07-04 9:35 ` Kukjin Kim
2011-07-08 7:21 ` Kukjin Kim
2011-07-08 7:21 ` Kukjin Kim
2011-07-01 1:57 ` [PATCH V2 4/8] ARM: SAMSUNG: Add support for failure of sleep mode Kukjin Kim
2011-07-01 1:57 ` Kukjin Kim
2011-07-01 1:57 ` [PATCH V2 5/8] ARM: EXYNOS4: Support early wakeup entering " Kukjin Kim
2011-07-01 1:57 ` Kukjin Kim
2011-07-01 1:57 ` [PATCH V2 6/8] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION setting for PM Kukjin Kim
2011-07-01 1:57 ` Kukjin Kim
2011-07-01 1:57 ` [PATCH V2 7/8] ARM: EXYNOS4: Add save/restore for other ARM registers Kukjin Kim
2011-07-01 1:57 ` Kukjin Kim
2011-07-01 1:57 ` [PATCH V2 8/8] ARM: EXYNOS4: Add save/restore function for PLL Kukjin Kim
2011-07-01 1:57 ` Kukjin Kim
2011-07-18 8:00 ` [PATCH V2 0/8] ARM: EXYNOS4: Update PM Kukjin Kim
2011-07-18 8:00 ` Kukjin Kim
2011-07-18 10:16 ` Russell King - ARM Linux
2011-07-18 10:16 ` Russell King - ARM Linux
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