[U-Boot] [PATCH 00/18] Blackfin updates for v2011.09

[U-Boot] [PATCH 00/18] Blackfin updates for v2011.09

[Mike Frysinger]

Many of these have been posted already, but some have not.  We've pulled
some updates from the Linux port, added support for multiple serial devs
at the same time, and random tweaks/improvements all over.

Harald Krapfenbauer (2):
  Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings
  Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support

Mike Frysinger (16):
  Blackfin: uart: move debug buffers into local bss
  Blackfin: uart: add multiple serial support
  Blackfin: adi boards: enable multi serial support by default
  Blackfin: dont reset SWRST on newer bf526 parts
  Blackfin: add init.elf helper code
  Blackfin: uart: fix printf warning
  Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDR
  Blackfin: gpio: optimize free path a little
  Blackfin: sync MMR read/write helpers with Linux
  Blackfin: portmux: allow header to be included in assembly files
  Blackfin: drop unused dma.h header from start code
  Blackfin: adi boards: enable pretty flash progress output
  Blackfin: split out async setup
  Blackfin: serial: convert to bfin_{read,write} helpers
  Blackfin: update anomaly lists to latest public info
  Blackfin: adi boards: also set stderr to nc with helper

 Makefile                                       |    3 +-
 arch/blackfin/cpu/.gitignore                   |    3 +
 arch/blackfin/cpu/Makefile                     |    7 +-
 arch/blackfin/cpu/cpu.c                        |   16 +-
 arch/blackfin/cpu/gpio.c                       |    2 +
 arch/blackfin/cpu/init.S                       |    9 +
 arch/blackfin/cpu/init.lds.S                   |   25 +++
 arch/blackfin/cpu/initcode.c                   |   61 ++-----
 arch/blackfin/cpu/initcode.h                   |   71 +++++++
 arch/blackfin/cpu/reset.c                      |    4 +-
 arch/blackfin/cpu/serial.c                     |  234 ++++++++++++++++++------
 arch/blackfin/cpu/serial.h                     |   60 ++++--
 arch/blackfin/cpu/start.S                      |    1 -
 arch/blackfin/include/asm/blackfin_local.h     |   88 +++++-----
 arch/blackfin/include/asm/config.h             |    3 +
 arch/blackfin/include/asm/gpio.h               |    3 +-
 arch/blackfin/include/asm/mach-bf506/anomaly.h |   25 ++-
 arch/blackfin/include/asm/mach-bf518/anomaly.h |   28 ++-
 arch/blackfin/include/asm/mach-bf527/anomaly.h |   38 +++--
 arch/blackfin/include/asm/mach-bf533/anomaly.h |   23 ++-
 arch/blackfin/include/asm/mach-bf537/anomaly.h |   37 +++--
 arch/blackfin/include/asm/mach-bf538/anomaly.h |   42 +++--
 arch/blackfin/include/asm/mach-bf548/anomaly.h |  227 +++++++++++++----------
 arch/blackfin/include/asm/mach-bf561/anomaly.h |  136 ++++++++------
 arch/blackfin/include/asm/portmux.h            |    4 +
 arch/blackfin/lib/board.c                      |    4 +
 board/cm-bf537e/cm-bf537e.c                    |   34 +++--
 board/cm-bf537u/cm-bf537u.c                    |   39 ++--
 board/tcm-bf537/tcm-bf537.c                    |   34 +++--
 common/serial.c                                |    3 +
 include/configs/bf537-stamp.h                  |    1 -
 include/configs/bfin_adi_common.h              |   12 +-
 include/configs/cm-bf537e.h                    |   20 ++-
 include/configs/cm-bf537u.h                    |   24 ++-
 include/configs/tcm-bf537.h                    |   20 ++-
 include/serial.h                               |    9 +
 36 files changed, 896 insertions(+), 454 deletions(-)
 create mode 100644 arch/blackfin/cpu/init.S
 create mode 100644 arch/blackfin/cpu/init.lds.S
 create mode 100644 arch/blackfin/cpu/initcode.h

-- 
1.7.5.3

[U-Boot] [PATCH 01/18] Blackfin: uart: move debug buffers into local bss

[Mike Frysinger]

There's no need for these saved buffers to be global symbols, or in
the data section.  So mark them static to move them into the bss.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/serial.c |   11 +++--------
 1 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c
index 650202e..b15c945 100644
--- a/arch/blackfin/cpu/serial.c
+++ b/arch/blackfin/cpu/serial.c
@@ -49,9 +49,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #include "serial.h"
 
 #ifdef CONFIG_DEBUG_SERIAL
-uint16_t cached_lsr[256];
-uint16_t cached_rbr[256];
-size_t cache_count;
+static uint16_t cached_lsr[256];
+static uint16_t cached_rbr[256];
+static size_t cache_count;
 
 /* The LSR is read-to-clear on some parts, so we have to make sure status
  * bits aren't inadvertently lost when doing various tests.  This also
@@ -112,11 +112,6 @@ int serial_init(void)
 	serial_initialize();
 	serial_setbrg();
 	uart_lsr_clear();
-#ifdef CONFIG_DEBUG_SERIAL
-	cache_count = 0;
-	memset(cached_lsr, 0x00, sizeof(cached_lsr));
-	memset(cached_rbr, 0x00, sizeof(cached_rbr));
-#endif
 	return 0;
 }
 
-- 
1.7.5.3

[U-Boot] [PATCH 02/18] Blackfin: uart: add multiple serial support

[Mike Frysinger]

This brings CONFIG_SERIAL_MULTI support to the Blackfin on-chip UARTs.
Ends up adding only ~512bytes per additional UART.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/initcode.c |   12 ++-
 arch/blackfin/cpu/serial.c   |  205 +++++++++++++++++++++++++++++++++---------
 arch/blackfin/cpu/serial.h   |   44 +++++++---
 arch/blackfin/lib/board.c    |    4 +
 common/serial.c              |    3 +
 include/serial.h             |    9 ++
 6 files changed, 222 insertions(+), 55 deletions(-)

diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
index 750add0..61dc5ab 100644
--- a/arch/blackfin/cpu/initcode.c
+++ b/arch/blackfin/cpu/initcode.c
@@ -24,6 +24,8 @@
 __attribute__((always_inline))
 static inline void serial_init(void)
 {
+	uint32_t uart_base = UART_DLL;
+
 #ifdef __ADSPBF54x__
 # ifdef BFIN_BOOT_UART_USE_RTS
 #  define BFIN_UART_USE_RTS 1
@@ -65,13 +67,13 @@ static inline void serial_init(void)
 
 	if (BFIN_DEBUG_EARLY_SERIAL) {
 		int ucen = bfin_read16(&pUART->gctl) & UCEN;
-		serial_early_init();
+		serial_early_init(uart_base);
 
 		/* If the UART is off, that means we need to program
 		 * the baud rate ourselves initially.
 		 */
 		if (ucen != UCEN)
-			serial_early_set_baud(CONFIG_BAUDRATE);
+			serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
 	}
 }
 
@@ -79,6 +81,8 @@ __attribute__((always_inline))
 static inline void serial_deinit(void)
 {
 #ifdef __ADSPBF54x__
+	uint32_t uart_base = UART_DLL;
+
 	if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 		/* clear forced RTS rather than relying on auto RTS */
 		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
@@ -89,6 +93,8 @@ static inline void serial_deinit(void)
 __attribute__((always_inline))
 static inline void serial_putc(char c)
 {
+	uint32_t uart_base = UART_DLL;
+
 	if (!BFIN_DEBUG_EARLY_SERIAL)
 		return;
 
@@ -519,7 +525,7 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 		unsigned int quotient;
 		for (quotient = 0; dividend > 0; ++quotient)
 			dividend -= divisor;
-		serial_early_put_div(quotient - ANOMALY_05000230);
+		serial_early_put_div(UART_DLL, quotient - ANOMALY_05000230);
 		serial_putc('c');
 	}
 
diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c
index b15c945..0252220 100644
--- a/arch/blackfin/cpu/serial.c
+++ b/arch/blackfin/cpu/serial.c
@@ -39,6 +39,8 @@
 
 #include <common.h>
 #include <watchdog.h>
+#include <serial.h>
+#include <linux/compiler.h>
 #include <asm/blackfin.h>
 #include <asm/mach-common/bits/uart.h>
 
@@ -59,14 +61,14 @@ static size_t cache_count;
  * tally of all the status bits.
  */
 static uint16_t uart_lsr_save;
-static uint16_t uart_lsr_read(void)
+static uint16_t uart_lsr_read(uint32_t uart_base)
 {
 	uint16_t lsr = bfin_read16(&pUART->lsr);
 	uart_lsr_save |= (lsr & (OE|PE|FE|BI));
 	return lsr | uart_lsr_save;
 }
 /* Just do the clear for everyone since it can't hurt. */
-static void uart_lsr_clear(void)
+static void uart_lsr_clear(uint32_t uart_base)
 {
 	uart_lsr_save = 0;
 	bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
@@ -76,46 +78,17 @@ static void uart_lsr_clear(void)
  * bits get set/cleared, we don't really care since we don't read them
  * anyways (and thus anomaly 05000099 is irrelevant).
  */
-static uint16_t uart_lsr_read(void)
+static inline uint16_t uart_lsr_read(uint32_t uart_base)
 {
 	return bfin_read16(&pUART->lsr);
 }
-static void uart_lsr_clear(void)
+static void uart_lsr_clear(uint32_t uart_base)
 {
 	bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
 }
 #endif
 
-/* Symbol for our assembly to call. */
-void serial_set_baud(uint32_t baud)
-{
-	serial_early_set_baud(baud);
-}
-
-/* Symbol for common u-boot code to call.
- * Setup the baudrate (brg: baudrate generator).
- */
-void serial_setbrg(void)
-{
-	serial_set_baud(gd->baudrate);
-}
-
-/* Symbol for our assembly to call. */
-void serial_initialize(void)
-{
-	serial_early_init();
-}
-
-/* Symbol for common u-boot code to call. */
-int serial_init(void)
-{
-	serial_initialize();
-	serial_setbrg();
-	uart_lsr_clear();
-	return 0;
-}
-
-void serial_putc(const char c)
+static void uart_putc(uint32_t uart_base, const char c)
 {
 	/* send a \r for compatibility */
 	if (c == '\n')
@@ -124,7 +97,7 @@ void serial_putc(const char c)
 	WATCHDOG_RESET();
 
 	/* wait for the hardware fifo to clear up */
-	while (!(uart_lsr_read() & THRE))
+	while (!(uart_lsr_read(uart_base) & THRE))
 		continue;
 
 	/* queue the character for transmission */
@@ -134,18 +107,18 @@ void serial_putc(const char c)
 	WATCHDOG_RESET();
 }
 
-int serial_tstc(void)
+static int uart_tstc(uint32_t uart_base)
 {
 	WATCHDOG_RESET();
-	return (uart_lsr_read() & DR) ? 1 : 0;
+	return (uart_lsr_read(uart_base) & DR) ? 1 : 0;
 }
 
-int serial_getc(void)
+static int uart_getc(uint32_t uart_base)
 {
 	uint16_t uart_rbr_val;
 
 	/* wait for data ! */
-	while (!serial_tstc())
+	while (!uart_tstc(uart_base))
 		continue;
 
 	/* grab the new byte */
@@ -153,7 +126,7 @@ int serial_getc(void)
 
 #ifdef CONFIG_DEBUG_SERIAL
 	/* grab & clear the LSR */
-	uint16_t uart_lsr_val = uart_lsr_read();
+	uint16_t uart_lsr_val = uart_lsr_read(uart_base);
 
 	cached_lsr[cache_count] = uart_lsr_val;
 	cached_rbr[cache_count] = uart_rbr_val;
@@ -175,11 +148,159 @@ int serial_getc(void)
 		return -1;
 	}
 #endif
-	uart_lsr_clear();
+	uart_lsr_clear(uart_base);
 
 	return uart_rbr_val;
 }
 
+#ifdef CONFIG_SYS_BFIN_UART
+
+static void uart_puts(uint32_t uart_base, const char *s)
+{
+	while (*s)
+		uart_putc(uart_base, *s++);
+}
+
+#define DECL_BFIN_UART(n) \
+static int uart##n##_init(void) \
+{ \
+	const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \
+	peripheral_request_list(pins, "bfin-uart"); \
+	uart_init(MMR_UART(n)); \
+	serial_early_set_baud(MMR_UART(n), gd->baudrate); \
+	uart_lsr_clear(MMR_UART(n)); \
+	return 0; \
+} \
+\
+static int uart##n##_uninit(void) \
+{ \
+	return serial_early_uninit(MMR_UART(n)); \
+} \
+\
+static void uart##n##_setbrg(void) \
+{ \
+	serial_early_set_baud(MMR_UART(n), gd->baudrate); \
+} \
+\
+static int uart##n##_getc(void) \
+{ \
+	return uart_getc(MMR_UART(n)); \
+} \
+\
+static int uart##n##_tstc(void) \
+{ \
+	return uart_tstc(MMR_UART(n)); \
+} \
+\
+static void uart##n##_putc(const char c) \
+{ \
+	uart_putc(MMR_UART(n), c); \
+} \
+\
+static void uart##n##_puts(const char *s) \
+{ \
+	uart_puts(MMR_UART(n), s); \
+} \
+\
+struct serial_device bfin_serial##n##_device = { \
+	.name   = "bfin_uart"#n, \
+	.init   = uart##n##_init, \
+	.uninit = uart##n##_uninit, \
+	.setbrg = uart##n##_setbrg, \
+	.getc   = uart##n##_getc, \
+	.tstc   = uart##n##_tstc, \
+	.putc   = uart##n##_putc, \
+	.puts   = uart##n##_puts, \
+};
+
+#ifdef UART0_DLL
+DECL_BFIN_UART(0)
+#endif
+#ifdef UART1_DLL
+DECL_BFIN_UART(1)
+#endif
+#ifdef UART2_DLL
+DECL_BFIN_UART(2)
+#endif
+#ifdef UART3_DLL
+DECL_BFIN_UART(3)
+#endif
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if CONFIG_UART_CONSOLE == 0
+	return &bfin_serial0_device;
+#elif CONFIG_UART_CONSOLE == 1
+	return &bfin_serial1_device;
+#elif CONFIG_UART_CONSOLE == 2
+	return &bfin_serial2_device;
+#elif CONFIG_UART_CONSOLE == 3
+	return &bfin_serial3_device;
+#endif
+}
+
+void serial_register_bfin_uart(void)
+{
+#ifdef UART0_DLL
+	serial_register(&bfin_serial0_device);
+#endif
+#ifdef UART1_DLL
+	serial_register(&bfin_serial1_device);
+#endif
+#ifdef UART2_DLL
+	serial_register(&bfin_serial2_device);
+#endif
+#ifdef UART3_DLL
+	serial_register(&bfin_serial3_device);
+#endif
+}
+
+#else
+
+/* Symbol for our assembly to call. */
+void serial_set_baud(uint32_t baud)
+{
+	serial_early_set_baud(UART_DLL, baud);
+}
+
+/* Symbol for common u-boot code to call.
+ * Setup the baudrate (brg: baudrate generator).
+ */
+void serial_setbrg(void)
+{
+	serial_set_baud(gd->baudrate);
+}
+
+/* Symbol for our assembly to call. */
+void serial_initialize(void)
+{
+	serial_early_init(UART_DLL);
+}
+
+/* Symbol for common u-boot code to call. */
+int serial_init(void)
+{
+	serial_initialize();
+	serial_setbrg();
+	uart_lsr_clear(UART_DLL);
+	return 0;
+}
+
+int serial_tstc(void)
+{
+	return uart_tstc(UART_DLL);
+}
+
+int serial_getc(void)
+{
+	return uart_getc(UART_DLL);
+}
+
+void serial_putc(const char c)
+{
+	uart_putc(UART_DLL, c);
+}
+
 void serial_puts(const char *s)
 {
 	while (*s)
@@ -187,3 +308,5 @@ void serial_puts(const char *s)
 }
 
 #endif
+
+#endif
diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h
index 7999a19..aa5c217 100644
--- a/arch/blackfin/cpu/serial.h
+++ b/arch/blackfin/cpu/serial.h
@@ -82,17 +82,19 @@ struct bfin_mmr_serial {
 
 #define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
 #define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
-#define MMR_UART(mmr) _PASTE_UART(CONFIG_UART_CONSOLE, UART, DLL)
-#define P_UART(pin) _PASTE_UART(CONFIG_UART_CONSOLE, P_UART, pin)
+#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
+#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin)
+#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin)
 
 #ifndef UART_DLL
-# define UART_DLL MMR_UART(DLL)
+# define UART_DLL MMR_UART(CONFIG_UART_CONSOLE)
 #else
+# define UART0_DLL UART_DLL
 # if CONFIG_UART_CONSOLE != 0
 #  error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
 # endif
 #endif
-#define pUART ((volatile struct bfin_mmr_serial *)UART_DLL)
+#define pUART ((volatile struct bfin_mmr_serial *)uart_base)
 
 #if BFIN_UART_HW_VER == 2
 # define ACCESS_LATCH()
@@ -168,11 +170,8 @@ static inline void serial_do_portmux(void)
 }
 
 __attribute__((always_inline))
-static inline void serial_early_init(void)
+static inline int uart_init(uint32_t uart_base)
 {
-	/* handle portmux crap on different Blackfins */
-	serial_do_portmux();
-
 	/* always enable UART -- avoids anomalies 05000309 and 05000350 */
 	bfin_write16(&pUART->gctl, UCEN);
 
@@ -180,10 +179,30 @@ static inline void serial_early_init(void)
 	bfin_write16(&pUART->lcr, WLS_8);
 
 	SSYNC();
+
+	return 0;
 }
 
 __attribute__((always_inline))
-static inline void serial_early_put_div(uint16_t divisor)
+static inline int serial_early_init(uint32_t uart_base)
+{
+	/* handle portmux crap on different Blackfins */
+	serial_do_portmux();
+
+	return uart_init(uart_base);
+}
+
+__attribute__((always_inline))
+static inline int serial_early_uninit(uint32_t uart_base)
+{
+	/* disable the UART by clearing UCEN */
+	bfin_write16(&pUART->gctl, 0);
+
+	return 0;
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint32_t uart_base, uint16_t divisor)
 {
 	/* Set DLAB in LCR to Access DLL and DLH */
 	ACCESS_LATCH();
@@ -202,6 +221,8 @@ static inline void serial_early_put_div(uint16_t divisor)
 __attribute__((always_inline))
 static inline uint16_t serial_early_get_div(void)
 {
+	uint32_t uart_base = UART_DLL;
+
 	/* Set DLAB in LCR to Access DLL and DLH */
 	ACCESS_LATCH();
 	SSYNC();
@@ -223,13 +244,14 @@ static inline uint16_t serial_early_get_div(void)
 #endif
 
 __attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t baud)
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
 {
 	/* Translate from baud into divisor in terms of SCLK.  The
 	 * weird multiplication is to make sure we over sample just
 	 * a little rather than under sample the incoming signals.
 	 */
-	serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
+	serial_early_put_div(uart_base,
+		(get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
 }
 
 #ifndef BFIN_IN_INITCODE
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index 362b8c4..e00050c 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -12,6 +12,7 @@
 #include <common.h>
 #include <command.h>
 #include <stdio_dev.h>
+#include <serial.h>
 #include <environment.h>
 #include <malloc.h>
 #include <mmc.h>
@@ -265,6 +266,9 @@ void board_init_f(ulong bootflag)
 	init_baudrate();
 	serial_early_puts("Serial init\n");
 	serial_init();
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
 	serial_early_puts("Console init flash\n");
 	console_init_f();
 	serial_early_puts("End of early debugging\n");
diff --git a/common/serial.c b/common/serial.c
index 8ebf9a5..7a69fc1 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -173,6 +173,9 @@ void serial_initialize (void)
 	serial_register(&serial6_device);
 #endif
 #endif
+#if defined(CONFIG_SYS_BFIN_UART)
+	serial_register_bfin_uart();
+#endif
 	serial_assign (default_serial_console ()->name);
 }
 
diff --git a/include/serial.h b/include/serial.h
index f21d961..4aa1cdc 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -71,6 +71,15 @@ extern struct serial_device serial_ffuart_device;
 extern struct serial_device serial_btuart_device;
 extern struct serial_device serial_stuart_device;
 
+#if defined(CONFIG_SYS_BFIN_UART)
+extern void serial_register_bfin_uart(void);
+extern struct serial_device bfin_serial0_device;
+extern struct serial_device bfin_serial1_device;
+extern struct serial_device bfin_serial2_device;
+extern struct serial_device bfin_serial3_device;
+#endif
+
+extern void serial_register(struct serial_device *);
 extern void serial_initialize(void);
 extern void serial_stdio_init(void);
 extern int serial_assign(char * name);
-- 
1.7.5.3

[U-Boot] [PATCH 03/18] Blackfin: adi boards: enable multi serial support by default

[Mike Frysinger]

Since this only adds less than 3KiB, enable for all ADI boards.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bfin_adi_common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 3312681..5d78403 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -112,6 +112,10 @@
 #ifndef CONFIG_BAUDRATE
 # define CONFIG_BAUDRATE	57600
 #endif
+#ifndef CONFIG_DEBUG_EARLY_SERIAL
+# define CONFIG_SERIAL_MULTI
+# define CONFIG_SYS_BFIN_UART
+#endif
 
 /*
  * Debug Settings
-- 
1.7.5.3

[U-Boot] [PATCH 04/18] Blackfin: dont reset SWRST on newer bf526 parts

[Mike Frysinger]

The bug in the BF526 rom when doing a software reset exists only in older
silicon versions, so don't clear SWRST on newer parts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/reset.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c
index e23dcc7..5567cd0 100644
--- a/arch/blackfin/cpu/reset.c
+++ b/arch/blackfin/cpu/reset.c
@@ -51,7 +51,9 @@ static void bfin_reset(void)
 
 	/* The BF526 ROM will crash during reset */
 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-	bfin_read_SWRST();
+	/* Seems to be fixed with newer parts though ... */
+	if (__SILICON_REVISION__ < 2 && bfin_revid() < 2)
+		bfin_read_SWRST();
 #endif
 
 	/* Wait for the SWRST write to complete.  Cannot rely on SSYNC
-- 
1.7.5.3

[U-Boot] [PATCH 05/18] Blackfin: add init.elf helper code

[Mike Frysinger]

This creates a standalone ELF that executes just the Blackfin initcode.
This is useful for people who want to program the low level aspects of
the CPU (memory/clocks/etc...) and can easily be used with JTAG for
quick booting while developing.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 Makefile                     |    3 ++-
 arch/blackfin/cpu/.gitignore |    3 +++
 arch/blackfin/cpu/Makefile   |    7 ++++++-
 arch/blackfin/cpu/init.S     |    9 +++++++++
 arch/blackfin/cpu/init.lds.S |   25 +++++++++++++++++++++++++
 5 files changed, 45 insertions(+), 2 deletions(-)
 create mode 100644 arch/blackfin/cpu/init.S
 create mode 100644 arch/blackfin/cpu/init.lds.S

diff --git a/Makefile b/Makefile
index 3454db6..8dfb174 100644
--- a/Makefile
+++ b/Makefile
@@ -1089,7 +1089,8 @@ clean:
 	       $(obj)board/voiceblue/eeprom 				  \
 	       $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds  \
 	       $(obj)u-boot.lds						  \
-	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]
+	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]	  \
+	       $(obj)arch/blackfin/cpu/init.{lds,elf}
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)lib/asm-offsets.s
 	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
diff --git a/arch/blackfin/cpu/.gitignore b/arch/blackfin/cpu/.gitignore
index 0ec9d56..ba986d8 100644
--- a/arch/blackfin/cpu/.gitignore
+++ b/arch/blackfin/cpu/.gitignore
@@ -1 +1,4 @@
 bootrom-asm-offsets.[chs]
+
+init.lds
+init.elf
diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile
index df10f1b..5deaa9e 100644
--- a/arch/blackfin/cpu/Makefile
+++ b/arch/blackfin/cpu/Makefile
@@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).o
 
-EXTRA    :=
+EXTRA    := init.elf
 CEXTRA   := initcode.o
 SEXTRA   := start.o
 SOBJS    := interrupt.o cache.o
@@ -61,6 +61,11 @@ ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
 	fi
 endif
 
+$(obj)init.lds: init.lds.S
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@
+$(obj)init.elf: $(obj)init.lds $(obj)init.o $(obj)initcode.o
+	$(LD) $(LDFLAGS) -T $^ -o $@
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/arch/blackfin/cpu/init.S b/arch/blackfin/cpu/init.S
new file mode 100644
index 0000000..f48c113
--- /dev/null
+++ b/arch/blackfin/cpu/init.S
@@ -0,0 +1,9 @@
+#include <asm/blackfin.h>
+ENTRY(_start)
+	sp.l = LO(L1_SRAM_SCRATCH_END - 20);
+	sp.h = HI(L1_SRAM_SCRATCH_END - 20);
+	call _initcode;
+1:
+	emuexcpt;
+	jump 1b;
+END(_start)
diff --git a/arch/blackfin/cpu/init.lds.S b/arch/blackfin/cpu/init.lds.S
new file mode 100644
index 0000000..602e7c8
--- /dev/null
+++ b/arch/blackfin/cpu/init.lds.S
@@ -0,0 +1,25 @@
+/*
+ * linker script for simple init.elf
+ *
+ * Copyright (c) 2005-2011 Analog Device Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+	l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+	.text.l1 : { *(.text .text.*) } >l1_code
+}
-- 
1.7.5.3

[U-Boot] [PATCH 06/18] Blackfin: uart: fix printf warning

[Mike Frysinger]

The code uses %i to printf a size_t when it should use %zu, otherwise
we get a warning from gcc about it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/serial.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c
index 0252220..1124ffd 100644
--- a/arch/blackfin/cpu/serial.c
+++ b/arch/blackfin/cpu/serial.c
@@ -142,7 +142,7 @@ static int uart_getc(uint32_t uart_base)
 		printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
 		do {
 			--cache_count;
-			printf("\t%3i: RBR=0x%02x LSR=0x%02x\n", cache_count,
+			printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
 				cached_rbr[cache_count], cached_lsr[cache_count]);
 		} while (cache_count > 0);
 		return -1;
-- 
1.7.5.3

[U-Boot] [PATCH 07/18] Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDR

[Mike Frysinger]

Set the default post word location to an L1 data location for all
Blackfin parts so things "just work" for most people.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/include/asm/config.h |    3 +++
 include/configs/bf537-stamp.h      |    1 -
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index 89814cd..bc3c252 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -121,6 +121,9 @@
 #ifndef CONFIG_SYS_MEMTEST_END
 # define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4)
 #endif
+#ifndef CONFIG_SYS_POST_WORD_ADDR
+# define CONFIG_SYS_POST_WORD_ADDR (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE - 4)
+#endif
 
 /* Check to make sure everything fits in external RAM */
 #if CONFIG_SYS_MAX_RAM_SIZE && \
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index c31e914..da14a4f 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -260,7 +260,6 @@
 #define FLASH_START_POST_BLOCK	11	/* Should > = 11 */
 #define FLASH_END_POST_BLOCK	71	/* Should < = 71 */
 #endif
-#define CONFIG_SYS_POST_WORD_ADDR	0xFF903FFC
 
 /* These are for board tests */
 #if 0
-- 
1.7.5.3

[U-Boot] [PATCH 08/18] Blackfin: gpio: optimize free path a little

[Mike Frysinger]

When we aren't doing resource tracking, the gpio_free() function is a
stub that simply returns, so pull this logic up a level and make it an
inline stub in the header.  Now we don't have to waste time at any of
the call sites.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/gpio.c         |    2 ++
 arch/blackfin/include/asm/gpio.h |    3 ++-
 2 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c
index cb96721..5674d42 100644
--- a/arch/blackfin/cpu/gpio.c
+++ b/arch/blackfin/cpu/gpio.c
@@ -665,6 +665,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
 	return 0;
 }
 
+#ifdef CONFIG_BFIN_GPIO_TRACK
 void bfin_gpio_free(unsigned gpio)
 {
 	if (check_gpio(gpio) < 0)
@@ -679,6 +680,7 @@ void bfin_gpio_free(unsigned gpio)
 
 	set_label(gpio, "free");
 }
+#endif
 
 #ifdef BFIN_SPECIAL_GPIO_BANKS
 DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 9c0e5d1..224688f 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -142,8 +142,10 @@ struct gpio_port_t {
 
 #ifdef CONFIG_BFIN_GPIO_TRACK
 void bfin_gpio_labels(void);
+void bfin_gpio_free(unsigned gpio);
 #else
 #define bfin_gpio_labels()
+#define bfin_gpio_free(gpio)
 #define bfin_gpio_request(gpio, label) bfin_gpio_request(gpio)
 #define bfin_special_gpio_request(gpio, label) bfin_special_gpio_request(gpio)
 #endif
@@ -154,7 +156,6 @@ int bfin_special_gpio_request(unsigned gpio, const char *label);
 #endif
 
 int bfin_gpio_request(unsigned gpio, const char *label);
-void bfin_gpio_free(unsigned gpio);
 int bfin_gpio_direction_input(unsigned gpio);
 int bfin_gpio_direction_output(unsigned gpio, int value);
 int bfin_gpio_get_value(unsigned gpio);
-- 
1.7.5.3

[U-Boot] [PATCH 09/18] Blackfin: sync MMR read/write helpers with Linux

[Mike Frysinger]

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/include/asm/blackfin_local.h |   88 +++++++++++++--------------
 1 files changed, 42 insertions(+), 46 deletions(-)

diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
index 48f793a..27034d3 100644
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -93,65 +93,61 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
 # define NOP_PAD_ANOMALY_05000198
 #endif
 
-#define bfin_read8(addr) ({ \
-	uint8_t __v; \
+#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
+	u32 __v; \
 	__asm__ __volatile__( \
 		NOP_PAD_ANOMALY_05000198 \
-		"%0 = b[%1] (z);" \
+		"%0 = " #asm_size "[%1]" #asm_ext ";" \
 		: "=d" (__v) \
 		: "a" (addr) \
 	); \
 	__v; })
-
-#define bfin_read16(addr) ({ \
-	uint16_t __v; \
-	__asm__ __volatile__( \
-		NOP_PAD_ANOMALY_05000198 \
-		"%0 = w[%1] (z);" \
-		: "=d" (__v) \
-		: "a" (addr) \
-	); \
-	__v; })
-
-#define bfin_read32(addr) ({ \
-	uint32_t __v; \
+#define _bfin_writeX(addr, val, size, asm_size) \
 	__asm__ __volatile__( \
 		NOP_PAD_ANOMALY_05000198 \
-		"%0 = [%1];" \
-		: "=d" (__v) \
-		: "a" (addr) \
-	); \
-	__v; })
-
-#define bfin_readPTR(addr) bfin_read32(addr)
-
-#define bfin_write8(addr, val) \
-	__asm__ __volatile__( \
-		NOP_PAD_ANOMALY_05000198 \
-		"b[%0] = %1;" \
-		: \
-		: "a" (addr), "d" (val) \
-		: "memory" \
-	)
-
-#define bfin_write16(addr, val) \
-	__asm__ __volatile__( \
-		NOP_PAD_ANOMALY_05000198 \
-		"w[%0] = %1;" \
+		#asm_size "[%0] = %1;" \
 		: \
-		: "a" (addr), "d" (val) \
+		: "a" (addr), "d" ((u##size)(val)) \
 		: "memory" \
 	)
 
-#define bfin_write32(addr, val) \
-	__asm__ __volatile__( \
-		NOP_PAD_ANOMALY_05000198 \
-		"[%0] = %1;" \
-		: \
-		: "a" (addr), "d" (val) \
-		: "memory" \
-	)
+#define bfin_read8(addr)  _bfin_readX(addr,  8, b, (z))
+#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
+#define bfin_read32(addr) _bfin_readX(addr, 32,  ,    )
+#define bfin_write8(addr, val)  _bfin_writeX(addr, val,  8, b)
+#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
+#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32,  )
+
+#define bfin_read(addr) \
+({ \
+	sizeof(*(addr)) == 1 ? bfin_read8(addr)  : \
+	sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
+	sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
+	({ BUG(); 0; }); \
+})
+#define bfin_write(addr, val) \
+do { \
+	switch (sizeof(*(addr))) { \
+	case 1: bfin_write8(addr, val);  break; \
+	case 2: bfin_write16(addr, val); break; \
+	case 4: bfin_write32(addr, val); break; \
+	default: BUG(); \
+	} \
+} while (0)
+
+#define bfin_write_or(addr, bits) \
+do { \
+	typeof(addr) __addr = (addr); \
+	bfin_write(__addr, bfin_read(__addr) | (bits)); \
+} while (0)
+
+#define bfin_write_and(addr, bits) \
+do { \
+	typeof(addr) __addr = (addr); \
+	bfin_write(__addr, bfin_read(__addr) & (bits)); \
+} while (0)
 
+#define bfin_readPTR(addr) bfin_read32(addr)
 #define bfin_writePTR(addr, val) bfin_write32(addr, val)
 
 /* SSYNC implementation for C file */
-- 
1.7.5.3

[U-Boot] [PATCH 10/18] Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings

[Mike Frysinger]

From: Harald Krapfenbauer <harald.krapfenbauer@bluetechnix.com>

These boards can have an addon card plugged onto them, so enable
support for it.

Signed-off-by: Harald Krapfenbauer <harald.krapfenbauer@bluetechnix.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 board/cm-bf537e/cm-bf537e.c |   34 ++++++++++++++++++++++------------
 board/cm-bf537u/cm-bf537u.c |   39 +++++++++++++++++++++------------------
 board/tcm-bf537/tcm-bf537.c |   34 ++++++++++++++++++++++------------
 include/configs/cm-bf537e.h |    3 +++
 include/configs/cm-bf537u.h |    8 ++++----
 include/configs/tcm-bf537.h |    4 +++-
 6 files changed, 75 insertions(+), 47 deletions(-)

diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c
index 1e350dc..38dbc6e 100644
--- a/board/cm-bf537e/cm-bf537e.c
+++ b/board/cm-bf537e/cm-bf537e.c
@@ -24,27 +24,37 @@ int checkboard(void)
 	return 0;
 }
 
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
+static void board_init_enetaddr(char *var)
 {
-	puts("Warning: Generating 'random' MAC address\n");
-	bfin_gen_rand_mac(mac_addr);
-	eth_setenv_enetaddr("ethaddr", mac_addr);
+#ifdef CONFIG_NET_MULTI
+	uchar enetaddr[6];
+
+	if (eth_getenv_enetaddr(var, enetaddr))
+		return;
+
+	printf("Warning: %s: generating 'random' MAC address\n", var);
+	bfin_gen_rand_mac(enetaddr);
+	eth_setenv_enetaddr(var, enetaddr);
+#endif
 }
 
+#ifndef CONFIG_BFIN_MAC
+# define bfin_EMAC_initialize(x) 1
+#endif
+#ifndef CONFIG_SMC911X
+# define smc911x_initialize(n, x) 1
+#endif
 int board_eth_init(bd_t *bis)
 {
-	return bfin_EMAC_initialize(bis);
+	/* return ok if at least 1 eth device works */
+	return bfin_EMAC_initialize(bis) &
+	       smc911x_initialize(0, CONFIG_SMC911X_BASE);
 }
-#endif
 
 int misc_init_r(void)
 {
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
+	board_init_enetaddr("ethaddr");
+	board_init_enetaddr("eth1addr");
 
 	gpio_cfi_flash_init();
 
diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c
index 4b7e864..a62ddd6 100644
--- a/board/cm-bf537u/cm-bf537u.c
+++ b/board/cm-bf537u/cm-bf537u.c
@@ -24,34 +24,37 @@ int checkboard(void)
 	return 0;
 }
 
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
+static void board_init_enetaddr(char *var)
 {
-	puts("Warning: Generating 'random' MAC address\n");
-	bfin_gen_rand_mac(mac_addr);
-	eth_setenv_enetaddr("ethaddr", mac_addr);
-}
+#ifdef CONFIG_NET_MULTI
+	uchar enetaddr[6];
 
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
+	if (eth_getenv_enetaddr(var, enetaddr))
+		return;
+
+	printf("Warning: %s: generating 'random' MAC address\n", var);
+	bfin_gen_rand_mac(enetaddr);
+	eth_setenv_enetaddr(var, enetaddr);
 #endif
+}
 
-#ifdef CONFIG_SMC911X
+#ifndef CONFIG_BFIN_MAC
+# define bfin_EMAC_initialize(x) 1
+#endif
+#ifndef CONFIG_SMC911X
+# define smc911x_initialize(n, x) 1
+#endif
 int board_eth_init(bd_t *bis)
 {
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+	/* return ok if at least 1 eth device works */
+	return bfin_EMAC_initialize(bis) &
+	       smc911x_initialize(0, CONFIG_SMC911X_BASE);
 }
-#endif
 
 int misc_init_r(void)
 {
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
+	board_init_enetaddr("ethaddr");
+	board_init_enetaddr("eth1addr");
 
 	gpio_cfi_flash_init();
 
diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c
index 04d6bdb..004e0d9 100644
--- a/board/tcm-bf537/tcm-bf537.c
+++ b/board/tcm-bf537/tcm-bf537.c
@@ -24,27 +24,37 @@ int checkboard(void)
 	return 0;
 }
 
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
+static void board_init_enetaddr(char *var)
 {
-	puts("Warning: Generating 'random' MAC address\n");
-	bfin_gen_rand_mac(mac_addr);
-	eth_setenv_enetaddr("ethaddr", mac_addr);
+#ifdef CONFIG_NET_MULTI
+	uchar enetaddr[6];
+
+	if (eth_getenv_enetaddr(var, enetaddr))
+		return;
+
+	printf("Warning: %s: generating 'random' MAC address\n", var);
+	bfin_gen_rand_mac(enetaddr);
+	eth_setenv_enetaddr(var, enetaddr);
+#endif
 }
 
+#ifndef CONFIG_BFIN_MAC
+# define bfin_EMAC_initialize(x) 1
+#endif
+#ifndef CONFIG_SMC911X
+# define smc911x_initialize(n, x) 1
+#endif
 int board_eth_init(bd_t *bis)
 {
-	return bfin_EMAC_initialize(bis);
+	/* return ok if at least 1 eth device works */
+	return bfin_EMAC_initialize(bis) &
+	       smc911x_initialize(0, CONFIG_SMC911X_BASE);
 }
-#endif
 
 int misc_init_r(void)
 {
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
+	board_init_enetaddr("ethaddr");
+	board_init_enetaddr("eth1addr");
 
 	gpio_cfi_flash_init();
 
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 04bca6c..3ee7738 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -65,6 +65,9 @@
 #ifndef __ADSPBF534__
 #define ADI_CMDS_NETWORK	1
 #define CONFIG_BFIN_MAC
+#define CONFIG_SMC911X		1
+#define CONFIG_SMC911X_BASE	0x20308000
+#define CONFIG_SMC911X_16_BIT
 #define CONFIG_NETCONSOLE	1
 #define CONFIG_NET_MULTI	1
 #endif
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index af2fe89..c791926 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -63,11 +63,11 @@
  */
 #ifndef __ADSPBF534__
 #define ADI_CMDS_NETWORK	1
-#define CONFIG_NET_MULTI
-/* The next 3 lines are for use with SMSC on EXT-BF5xx-USB-ETH2 */
-#define CONFIG_SMC911X	1
-#define CONFIG_SMC911X_BASE	0x24000000
+#define CONFIG_SMC911X		1
+#define CONFIG_SMC911X_BASE	0x20308000
 #define CONFIG_SMC911X_16_BIT
+#define CONFIG_NETCONSOLE	1
+#define CONFIG_NET_MULTI	1
 #endif
 #define CONFIG_HOSTNAME		cm-bf537u
 /* Uncomment next line to use fixed MAC address */
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 9a6100e..f2c5b98 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -62,10 +62,12 @@
 /*
  * Network Settings
  */
-/* TCM-BF537E has no PHY on it, but EXT-BF5xx-USB/Ethernet board has */
 #ifndef __ADSPBF534__
 #define ADI_CMDS_NETWORK	1
 #define CONFIG_BFIN_MAC
+#define CONFIG_SMC911X		1
+#define CONFIG_SMC911X_BASE	0x20308000
+#define CONFIG_SMC911X_16_BIT
 #define CONFIG_NETCONSOLE	1
 #define CONFIG_NET_MULTI	1
 #endif
-- 
1.7.5.3

[U-Boot] [PATCH 11/18] Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support

[Mike Frysinger]

From: Harald Krapfenbauer <harald.krapfenbauer@bluetechnix.com>

These boards have an mmc/sd slot on them connected over SPI, so
enable the driver.

Signed-off-by: Harald Krapfenbauer <harald.krapfenbauer@bluetechnix.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/cm-bf537e.h |   17 ++++++++++++++++-
 include/configs/cm-bf537u.h |   16 +++++++++++++++-
 include/configs/tcm-bf537.h |   16 +++++++++++++++-
 3 files changed, 46 insertions(+), 3 deletions(-)

diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 3ee7738..9649e18 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -55,7 +55,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
 #define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
 
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
 
@@ -89,6 +89,13 @@
 
 
 /*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+
+
+/*
  * Env Storage Settings
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -121,6 +128,14 @@
 
 
 /*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+
+
+/*
  * Misc Settings
  */
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index c791926..84846ef 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -54,7 +54,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
 #define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
 
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
 
@@ -87,6 +87,13 @@
 
 
 /*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+
+
+/*
  * Env Storage Settings
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -119,6 +126,13 @@
 
 
 /*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+
+/*
  * Misc Settings
  */
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index f2c5b98..2375fc5 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -55,7 +55,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
 #define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
 
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
 
@@ -89,6 +89,13 @@
 
 
 /*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+
+
+/*
  * Env Storage Settings
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -121,6 +128,13 @@
 
 
 /*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+
+/*
  * Misc Settings
  */
 #define CONFIG_BAUDRATE		115200
-- 
1.7.5.3

[U-Boot] [PATCH 12/18] Blackfin: portmux: allow header to be included in assembly files

[Mike Frysinger]

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/include/asm/portmux.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
index b17207f..300ef44 100644
--- a/arch/blackfin/include/asm/portmux.h
+++ b/arch/blackfin/include/asm/portmux.h
@@ -22,11 +22,15 @@
 #define peripheral_request_list(per, label) peripheral_request_list(per)
 #endif
 
+#ifndef __ASSEMBLY__
+
 int peripheral_request(unsigned short per, const char *label);
 void peripheral_free(unsigned short per);
 int peripheral_request_list(const unsigned short per[], const char *label);
 void peripheral_free_list(const unsigned short per[]);
 
+#endif
+
 #include <asm/blackfin.h>
 
 #ifndef P_SPORT2_TFS
-- 
1.7.5.3

[U-Boot] [PATCH 13/18] Blackfin: drop unused dma.h header from start code

[Mike Frysinger]

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/start.S |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S
index 15ecb1e..90b4d1a 100644
--- a/arch/blackfin/cpu/start.S
+++ b/arch/blackfin/cpu/start.S
@@ -33,7 +33,6 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/dma.h>
 #include <asm/mach-common/bits/pll.h>
 
 #include "serial.h"
-- 
1.7.5.3

[U-Boot] [PATCH 14/18] Blackfin: adi boards: enable pretty flash progress output

[Mike Frysinger]

For only ~150 bytes increase in size, we can get a nice flash progress
indicator rather than just the boring dots (which don't tell too much
about overall progress).  So enable it for all ADI boards.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bfin_adi_common.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 5d78403..80f8a14 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -277,6 +277,11 @@
 #endif
 
 /*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+
+/*
  * SPI Settings
  */
 #ifdef CONFIG_SPI_FLASH_ALL
-- 
1.7.5.3

[U-Boot] [PATCH 15/18] Blackfin: split out async setup

[Mike Frysinger]

We really only need to tweak the async banks in the initcode if the
processor is booting out of it, otherwise we can wait until later
on in the CPU booting setup.

This also makes testing in the sim and early bring up over JTAG work
much smoother when the initcode gets bypassed.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/cpu.c      |   16 ++++++---
 arch/blackfin/cpu/initcode.c |   47 ++--------------------------
 arch/blackfin/cpu/initcode.h |   71 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 84 insertions(+), 50 deletions(-)
 create mode 100644 arch/blackfin/cpu/initcode.h

diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
index 18dbdf7..6a0bcca 100644
--- a/arch/blackfin/cpu/cpu.c
+++ b/arch/blackfin/cpu/cpu.c
@@ -19,6 +19,7 @@
 
 #include "cpu.h"
 #include "serial.h"
+#include "initcode.h"
 
 ulong bfin_poweron_retx;
 
@@ -44,13 +45,16 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 		extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
 		memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
 	}
-#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
-	/* The BF537 bootrom will reset the EBIU_AMGCTL register on us
-	 * after it has finished loading the LDR.  So configure it again.
+
+	/*
+	 * Make sure our async settings are committed.  Some bootroms
+	 * (like the BF537) will reset some registers on us after it
+	 * has finished loading the LDR.  Or if we're booting over
+	 * JTAG, the initcode never got a chance to run.  Or if we
+	 * aren't booting from parallel flash, the initcode skipped
+	 * this step completely.
 	 */
-	else
-		bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
-#endif
+	program_async_controller(NULL);
 
 	/* Save RETX so we can pass it while booting Linux */
 	bfin_poweron_retx = bootflag;
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
index 61dc5ab..917b7f9 100644
--- a/arch/blackfin/cpu/initcode.c
+++ b/arch/blackfin/cpu/initcode.c
@@ -4,7 +4,7 @@
  * cannot make any function calls as it may be executed all by itself by
  * the Blackfin's bootrom in LDR format.
  *
- * Copyright (c) 2004-2008 Analog Devices Inc.
+ * Copyright (c) 2004-2011 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -107,6 +107,8 @@ static inline void serial_putc(char c)
 		continue;
 }
 
+#include "initcode.h"
+
 __attribute__((always_inline)) static inline void
 program_nmi_handler(void)
 {
@@ -172,21 +174,6 @@ program_nmi_handler(void)
 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
 #endif
 
-#ifndef CONFIG_EBIU_RSTCTL_VAL
-# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
-#endif
-#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
-# error invalid EBIU_RSTCTL value: must not set reserved bits
-#endif
-
-#ifndef CONFIG_EBIU_MBSCTL_VAL
-# define CONFIG_EBIU_MBSCTL_VAL 0
-#endif
-
-#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
-# error invalid EBIU_DDRQUE value: must not set reserved bits
-#endif
-
 /* Make sure our voltage value is sane so we don't blow up! */
 #ifndef CONFIG_VR_CTL_VAL
 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
@@ -642,34 +629,6 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
 	serial_putc('e');
 }
 
-__attribute__((always_inline)) static inline void
-program_async_controller(ADI_BOOT_DATA *bs)
-{
-	serial_putc('a');
-
-	/* Program the async banks controller. */
-	bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
-	bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
-	bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
-
-	serial_putc('b');
-
-	/* Not all parts have these additional MMRs. */
-#ifdef EBIU_MBSCTL
-	bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
-#endif
-#ifdef EBIU_MODE
-# ifdef CONFIG_EBIU_MODE_VAL
-	bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
-# endif
-# ifdef CONFIG_EBIU_FCTL_VAL
-	bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
-# endif
-#endif
-
-	serial_putc('c');
-}
-
 BOOTROM_CALLED_FUNC_ATTR
 void initcode(ADI_BOOT_DATA *bs)
 {
diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h
new file mode 100644
index 0000000..e0aad6d
--- /dev/null
+++ b/arch/blackfin/cpu/initcode.h
@@ -0,0 +1,71 @@
+/*
+ * Code for early processor initialization
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_INITCODE_H__
+#define __BFIN_INITCODE_H__
+
+#include <asm/mach-common/bits/bootrom.h>
+
+#ifndef BFIN_IN_INITCODE
+# define serial_putc(c)
+#endif
+
+#ifndef CONFIG_EBIU_RSTCTL_VAL
+# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
+#endif
+#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
+# error invalid EBIU_RSTCTL value: must not set reserved bits
+#endif
+
+#ifndef CONFIG_EBIU_MBSCTL_VAL
+# define CONFIG_EBIU_MBSCTL_VAL 0
+#endif
+
+#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
+# error invalid EBIU_DDRQUE value: must not set reserved bits
+#endif
+
+__attribute__((always_inline)) static inline void
+program_async_controller(ADI_BOOT_DATA *bs)
+{
+#ifdef BFIN_IN_INITCODE
+	/*
+	 * We really only need to setup the async banks early if we're
+	 * booting out of it.  Otherwise, do it later on in cpu_init.
+	 */
+	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS &&
+	    CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_PARA)
+		return;
+#endif
+
+	serial_putc('a');
+
+	/* Program the async banks controller. */
+	bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
+	bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
+	bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+
+	serial_putc('b');
+
+	/* Not all parts have these additional MMRs. */
+#ifdef EBIU_MBSCTL
+	bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
+#endif
+#ifdef EBIU_MODE
+# ifdef CONFIG_EBIU_MODE_VAL
+	bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
+# endif
+# ifdef CONFIG_EBIU_FCTL_VAL
+	bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
+# endif
+#endif
+
+	serial_putc('c');
+}
+
+#endif
-- 
1.7.5.3

[U-Boot] [PATCH 16/18] Blackfin: serial: convert to bfin_{read, write} helpers

[Mike Frysinger]

Since the serial struct declares the sizes for us, no need to hardcode
them in the accessor functions.  Let the bfin_{read,write} helpers do
it for us.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/initcode.c |    2 ++
 arch/blackfin/cpu/serial.c   |   16 ++++++++--------
 arch/blackfin/cpu/serial.h   |   18 +++++++++---------
 3 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
index 917b7f9..fb3a101 100644
--- a/arch/blackfin/cpu/initcode.c
+++ b/arch/blackfin/cpu/initcode.c
@@ -19,6 +19,8 @@
 #include <asm/mach-common/bits/pll.h>
 #include <asm/mach-common/bits/uart.h>
 
+#define BUG() while (1) { asm volatile("emuexcpt;"); }
+
 #include "serial.h"
 
 __attribute__((always_inline))
diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c
index 1124ffd..030160f 100644
--- a/arch/blackfin/cpu/serial.c
+++ b/arch/blackfin/cpu/serial.c
@@ -63,7 +63,7 @@ static size_t cache_count;
 static uint16_t uart_lsr_save;
 static uint16_t uart_lsr_read(uint32_t uart_base)
 {
-	uint16_t lsr = bfin_read16(&pUART->lsr);
+	uint16_t lsr = bfin_read(&pUART->lsr);
 	uart_lsr_save |= (lsr & (OE|PE|FE|BI));
 	return lsr | uart_lsr_save;
 }
@@ -71,7 +71,7 @@ static uint16_t uart_lsr_read(uint32_t uart_base)
 static void uart_lsr_clear(uint32_t uart_base)
 {
 	uart_lsr_save = 0;
-	bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
+	bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1);
 }
 #else
 /* When debugging is disabled, we only care about the DR bit, so if other
@@ -80,11 +80,11 @@ static void uart_lsr_clear(uint32_t uart_base)
  */
 static inline uint16_t uart_lsr_read(uint32_t uart_base)
 {
-	return bfin_read16(&pUART->lsr);
+	return bfin_read(&pUART->lsr);
 }
 static void uart_lsr_clear(uint32_t uart_base)
 {
-	bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
+	bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1);
 }
 #endif
 
@@ -101,7 +101,7 @@ static void uart_putc(uint32_t uart_base, const char c)
 		continue;
 
 	/* queue the character for transmission */
-	bfin_write16(&pUART->thr, c);
+	bfin_write(&pUART->thr, c);
 	SSYNC();
 
 	WATCHDOG_RESET();
@@ -122,7 +122,7 @@ static int uart_getc(uint32_t uart_base)
 		continue;
 
 	/* grab the new byte */
-	uart_rbr_val = bfin_read16(&pUART->rbr);
+	uart_rbr_val = bfin_read(&pUART->rbr);
 
 #ifdef CONFIG_DEBUG_SERIAL
 	/* grab & clear the LSR */
@@ -136,8 +136,8 @@ static int uart_getc(uint32_t uart_base)
 		uint16_t dll, dlh;
 		printf("\n[SERIAL ERROR]\n");
 		ACCESS_LATCH();
-		dll = bfin_read16(&pUART->dll);
-		dlh = bfin_read16(&pUART->dlh);
+		dll = bfin_read(&pUART->dll);
+		dlh = bfin_read(&pUART->dlh);
 		ACCESS_PORT_IER();
 		printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
 		do {
diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h
index aa5c217..f649e40 100644
--- a/arch/blackfin/cpu/serial.h
+++ b/arch/blackfin/cpu/serial.h
@@ -101,9 +101,9 @@ struct bfin_mmr_serial {
 # define ACCESS_PORT_IER()
 #else
 # define ACCESS_LATCH() \
-	bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) | DLAB)
+	bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) | DLAB)
 # define ACCESS_PORT_IER() \
-	bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) & ~DLAB)
+	bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) & ~DLAB)
 #endif
 
 __attribute__((always_inline))
@@ -173,10 +173,10 @@ __attribute__((always_inline))
 static inline int uart_init(uint32_t uart_base)
 {
 	/* always enable UART -- avoids anomalies 05000309 and 05000350 */
-	bfin_write16(&pUART->gctl, UCEN);
+	bfin_write(&pUART->gctl, UCEN);
 
 	/* Set LCR to Word Lengh 8-bit word select */
-	bfin_write16(&pUART->lcr, WLS_8);
+	bfin_write(&pUART->lcr, WLS_8);
 
 	SSYNC();
 
@@ -196,7 +196,7 @@ __attribute__((always_inline))
 static inline int serial_early_uninit(uint32_t uart_base)
 {
 	/* disable the UART by clearing UCEN */
-	bfin_write16(&pUART->gctl, 0);
+	bfin_write(&pUART->gctl, 0);
 
 	return 0;
 }
@@ -209,8 +209,8 @@ static inline void serial_early_put_div(uint32_t uart_base, uint16_t divisor)
 	SSYNC();
 
 	/* Program the divisor to get the baud rate we want */
-	bfin_write16(&pUART->dll, LOB(divisor));
-	bfin_write16(&pUART->dlh, HIB(divisor));
+	bfin_write(&pUART->dll, LOB(divisor));
+	bfin_write(&pUART->dlh, HIB(divisor));
 	SSYNC();
 
 	/* Clear DLAB in LCR to Access THR RBR IER */
@@ -227,8 +227,8 @@ static inline uint16_t serial_early_get_div(void)
 	ACCESS_LATCH();
 	SSYNC();
 
-	uint8_t dll = bfin_read16(&pUART->dll);
-	uint8_t dlh = bfin_read16(&pUART->dlh);
+	uint8_t dll = bfin_read(&pUART->dll);
+	uint8_t dlh = bfin_read(&pUART->dlh);
 	uint16_t divisor = (dlh << 8) | dll;
 
 	/* Clear DLAB in LCR to Access THR RBR IER */
-- 
1.7.5.3

[U-Boot] [PATCH 17/18] Blackfin: update anomaly lists to latest public info

[Mike Frysinger]

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/include/asm/mach-bf506/anomaly.h |   25 +++-
 arch/blackfin/include/asm/mach-bf518/anomaly.h |   28 ++-
 arch/blackfin/include/asm/mach-bf527/anomaly.h |   38 +++--
 arch/blackfin/include/asm/mach-bf533/anomaly.h |   23 ++-
 arch/blackfin/include/asm/mach-bf537/anomaly.h |   37 +++--
 arch/blackfin/include/asm/mach-bf538/anomaly.h |   42 +++--
 arch/blackfin/include/asm/mach-bf548/anomaly.h |  227 +++++++++++++-----------
 arch/blackfin/include/asm/mach-bf561/anomaly.h |  136 ++++++++-------
 8 files changed, 335 insertions(+), 221 deletions(-)

diff --git a/arch/blackfin/include/asm/mach-bf506/anomaly.h b/arch/blackfin/include/asm/mach-bf506/anomaly.h
index e767233..5b3227a 100644
--- a/arch/blackfin/include/asm/mach-bf506/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf506/anomaly.h
@@ -5,12 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
+ *  - Revision A, 02/18/2011; ADSP-BF504/BF504F/BF506F Blackfin Processor Anomaly List
  */
 
 #if __SILICON_REVISION__ < 0
@@ -36,8 +37,6 @@
 #define ANOMALY_05000310 (1)
 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
 #define ANOMALY_05000366 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
 #define ANOMALY_05000426 (1)
 /* IFLUSH Instruction@End of Hardware Loop Causes Infinite Stall */
@@ -52,12 +51,28 @@
 #define ANOMALY_05000472 (1)
 /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
+/* SPORT0 Data Transmit Error in Multi-Channel Mode with Internal Clock */
+#define ANOMALY_05000476 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
+/* Disabling ACM During an Ongoing Transfer Can Lead to Undefined ACM Behavior */
+#define ANOMALY_05000478 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* TWI Vbus Minimum Specification Can Be Violated under Certain Conditions */
+#define ANOMALY_05000486 (1)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* Maximum Idd-deepsleep Specifications Can Be Exceeded under Certain Conditions */
+#define ANOMALY_05000495 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
@@ -109,6 +124,7 @@
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000371 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (0)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000400 (0)
@@ -123,6 +139,7 @@
 #define ANOMALY_05000467 (0)
 #define ANOMALY_05000474 (0)
 #define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
 #define ANOMALY_05000485 (0)
 
 #endif
diff --git a/arch/blackfin/include/asm/mach-bf518/anomaly.h b/arch/blackfin/include/asm/mach-bf518/anomaly.h
index 24918c5..56383f7 100644
--- a/arch/blackfin/include/asm/mach-bf518/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf518/anomaly.h
@@ -5,16 +5,15 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
+ *  - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
  */
 
-/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
 #if __SILICON_REVISION__ < 0
 # error will not work on BF518 silicon version
 #endif
@@ -77,19 +76,29 @@
 /* False Hardware Error when RETI Points to Invalid Memory */
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem@Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
+#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
 /* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (1)
+#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
 /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL Latches Incorrect Settings During Reset */
+#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
+/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
+#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
@@ -141,6 +150,7 @@
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000371 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (0)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000400 (0)
@@ -155,6 +165,6 @@
 #define ANOMALY_05000467 (0)
 #define ANOMALY_05000474 (0)
 #define ANOMALY_05000475 (0)
-#define ANOMALY_05000485 (0)
+#define ANOMALY_05000480 (0)
 
 #endif
diff --git a/arch/blackfin/include/asm/mach-bf527/anomaly.h b/arch/blackfin/include/asm/mach-bf527/anomaly.h
index 72a6369..6884706 100644
--- a/arch/blackfin/include/asm/mach-bf527/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf527/anomaly.h
@@ -5,14 +5,14 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
- *  - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
+ *  - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
+ *  - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -57,7 +57,7 @@
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
 #define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
 /* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
 #define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
@@ -135,7 +135,7 @@
 /* Incorrect Default Internal Voltage Regulator Setting */
 #define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
 /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2))
+#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
 /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
 #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* DEB2_URGENT Bit Not Functional */
@@ -181,11 +181,11 @@
 /* IFLUSH Instruction@End of Hardware Loop Causes Infinite Stall */
 #define ANOMALY_05000443 (1)
 /* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (1)
-/* USB DMA Mode 1 Short Packet Data Corruption */
+#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
+/* USB DMA Short Packet Data Corruption */
 #define ANOMALY_05000450 (1)
 /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (1)
+#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
 /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
 #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
@@ -198,19 +198,19 @@
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
 #define ANOMALY_05000462 (1)
-/* USB Rx DMA hang */
+/* USB Rx DMA Hang */
 #define ANOMALY_05000465 (1)
 /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
 #define ANOMALY_05000466 (1)
-/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
+/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
 #define ANOMALY_05000467 (1)
 /* PLL Latches Incorrect Settings During Reset */
 #define ANOMALY_05000469 (1)
 /* Incorrect Default MSEL Value in PLL_CTL */
 #define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
@@ -219,11 +219,19 @@
 /* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
 #define ANOMALY_05000483 (1)
 /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
 /* The CODEC Zero-Cross Detect Feature is not Functional */
 #define ANOMALY_05000487 (1)
-/* IFLUSH sucks at life */
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
@@ -270,11 +278,13 @@
 #define ANOMALY_05000323 (0)
 #define ANOMALY_05000362 (1)
 #define ANOMALY_05000363 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000400 (0)
 #define ANOMALY_05000402 (0)
 #define ANOMALY_05000412 (0)
 #define ANOMALY_05000447 (0)
 #define ANOMALY_05000448 (0)
 #define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
 
 #endif
diff --git a/arch/blackfin/include/asm/mach-bf533/anomaly.h b/arch/blackfin/include/asm/mach-bf533/anomaly.h
index 30e0eba..03f2b40 100644
--- a/arch/blackfin/include/asm/mach-bf533/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf533/anomaly.h
@@ -5,13 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ *  - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -152,7 +152,7 @@
 #define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
 #define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 #define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
 #define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
@@ -210,18 +210,25 @@
 #define ANOMALY_05000462 (1)
 /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
 #define ANOMALY_05000471 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
 
-/* These anomalies have been "phased" out of analog.com anomaly sheets and are
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
  * here to show running on older silicon just isn't feasible.
  */
 
@@ -355,6 +362,7 @@
 #define ANOMALY_05000362 (1)
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (1)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000412 (0)
@@ -369,6 +377,7 @@
 #define ANOMALY_05000465 (0)
 #define ANOMALY_05000467 (0)
 #define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
 #define ANOMALY_05000485 (0)
 
 #endif
diff --git a/arch/blackfin/include/asm/mach-bf537/anomaly.h b/arch/blackfin/include/asm/mach-bf537/anomaly.h
index d3a2966..543cd3f 100644
--- a/arch/blackfin/include/asm/mach-bf537/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf537/anomaly.h
@@ -5,13 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -44,18 +44,12 @@
 #define ANOMALY_05000119 (1)
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
 /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
 #define ANOMALY_05000180 (1)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
 #define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
-/* Buffered CLKIN Output Is Disabled by Default */
-#define ANOMALY_05000247 (1)
 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
 #define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
 /* EMAC TX DMA Error After an Early Frame Abort */
@@ -98,7 +92,7 @@
 #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
 /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
 #define ANOMALY_05000280 (1)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 #define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
 #define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
@@ -162,9 +156,9 @@
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem@Startup May Cause SPORT Transmit Channels to Misalign */
 #define ANOMALY_05000462 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
@@ -172,8 +166,26 @@
 #define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
+/* Instruction Cache Is Not Functional */
+#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
+/* Buffered CLKIN Output Is Disabled by Default */
+#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
@@ -208,6 +220,7 @@
 #define ANOMALY_05000363 (0)
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (1)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000400 (0)
diff --git a/arch/blackfin/include/asm/mach-bf538/anomaly.h b/arch/blackfin/include/asm/mach-bf538/anomaly.h
index 4bc1f4a..b6ca997 100644
--- a/arch/blackfin/include/asm/mach-bf538/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf538/anomaly.h
@@ -5,14 +5,14 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- *  - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
+ *  - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
+ *  - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -56,25 +56,21 @@
 #define ANOMALY_05000229 (1)
 /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
 #define ANOMALY_05000233 (1)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
 /* Maximum External Clock Speed for Timers */
 #define ANOMALY_05000253 (1)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
 #define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
+#define ANOMALY_05000272 (ANOMALY_BF538)
 /* Writes to Synchronous SDRAM Memory May Be Lost */
 #define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
 #define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
 #define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 #define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
 #define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
@@ -102,8 +98,10 @@
 #define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
 /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
 #define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
+/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
+#define ANOMALY_05000317 (__SILICON_REVISION__ < 4)	/* XXX: Same as 05000318 */
 /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
-#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
+#define ANOMALY_05000318 (__SILICON_REVISION__ < 4)	/* XXX: Same as 05000317 */
 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
 #define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
@@ -134,16 +132,32 @@
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem@Startup May Cause SPORT Transmit Channels to Misalign */
 #define ANOMALY_05000462 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
@@ -179,6 +193,7 @@
 #define ANOMALY_05000363 (0)
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (1)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000400 (0)
@@ -194,6 +209,7 @@
 #define ANOMALY_05000465 (0)
 #define ANOMALY_05000467 (0)
 #define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
 #define ANOMALY_05000485 (0)
 
 #endif
diff --git a/arch/blackfin/include/asm/mach-bf548/anomaly.h b/arch/blackfin/include/asm/mach-bf548/anomaly.h
index b9f4ecc..021fb19 100644
--- a/arch/blackfin/include/asm/mach-bf548/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf548/anomaly.h
@@ -5,13 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ *  - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -31,111 +31,37 @@
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (1)
+#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
 #define ANOMALY_05000265 (1)
 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
 #define ANOMALY_05000272 (1)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
 #define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
 /* FIFO Boot Mode Not Functional */
 #define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0x5411
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
 /* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
-/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
-#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
+/*
+ * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
+ *       shows that the fix itself does not cover all cases.
+ */
+#define ANOMALY_05000353 (1)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
 #define ANOMALY_05000357 (1)
 /* External Memory Read Access Hangs Core With PLL Bypass */
 #define ANOMALY_05000360 (1)
 /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
 #define ANOMALY_05000365 (1)
-/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
-#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
 /* Addressing Conflict between Boot ROM and Asynchronous Memory */
 #define ANOMALY_05000369 (1)
-/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
-#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 #define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
-/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
-#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
 /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
 #define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
 /* 16-Bit NAND FLASH Boot Mode Is Not Functional */
 #define ANOMALY_05000379 (1)
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
-/* Changed Meaning of BCODE Field in SYSCR Register */
-#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
-/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
-#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
 /* Lockbox SESR Disallows Certain User Interrupts */
 #define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
 /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
@@ -157,7 +83,7 @@
 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
 #define ANOMALY_05000416 (1)
 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
+#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
 #define ANOMALY_05000426 (1)
 /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
@@ -170,8 +96,6 @@
 #define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
 /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
 #define ANOMALY_05000434 (1)
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
 #define ANOMALY_05000443 (1)
 /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
@@ -182,34 +106,32 @@
 #define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
 /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
 #define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
-/* USB DMA Mode 1 Short Packet Data Corruption */
+/* USB DMA Short Packet Data Corruption */
 #define ANOMALY_05000450 (1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
 #define ANOMALY_05000456 (1)
 /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
 #define ANOMALY_05000457 (1)
 /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
+#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
 /* False Hardware Error when RETI Points to Invalid Memory */
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem@Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
+#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
 /* USB DMA RX Data Corruption */
-#define ANOMALY_05000463 (1)
+#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
 /* USB TX DMA Hang */
-#define ANOMALY_05000464 (1)
-/* USB Rx DMA hang */
+#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
+/* USB Rx DMA Hang */
 #define ANOMALY_05000465 (1)
 /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
-#define ANOMALY_05000467 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
+/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
+#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
-#define ANOMALY_05000474 (1)
+/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
+#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
@@ -219,9 +141,111 @@
 /* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
 #define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
 /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
-/* IFLUSH sucks at life */
+#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
+#define ANOMALY_05000500 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
+#define ANOMALY_05000502 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* False Hardware Error when ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
+/* TWI Slave Boot Mode Is Not Functional */
+#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
+/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
+#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
+/* Incorrect Access of OTP_STATUS During otp_write() Function */
+#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
+/* Synchronous Burst Flash Boot Mode Is Not Functional */
+#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
+/* Host DMA Boot Modes Are Not Functional */
+#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
+/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
+#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
+/* Inadequate Rotary Debounce Logic Duration */
+#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
+/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
+#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
+/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
+#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
+/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
+#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
+/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
+#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
+/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
+#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value Is Not Initialized */
+#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0x5411
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
+#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
+/* Data Lost when Core Reads SDH Data FIFO */
+#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
+/* PLL Status Register Is Inaccurate */
+#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
+/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
+#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
+/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
+#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
+/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
+#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
+/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
+#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
+/* Changed Meaning of BCODE Field in SYSCR Register */
+#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
+/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
+#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
+/* OTP Write Accesses Not Supported */
+#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
+/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
+#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
@@ -274,5 +298,6 @@
 #define ANOMALY_05000435 (0)
 #define ANOMALY_05000440 (0)
 #define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
 
 #endif
diff --git a/arch/blackfin/include/asm/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h
index 9313c27..b27173c 100644
--- a/arch/blackfin/include/asm/mach-bf561/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf561/anomaly.h
@@ -5,13 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
+ *  - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -26,62 +26,16 @@
 #define ANOMALY_05000074 (1)
 /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
 #define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
 /* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
 #define ANOMALY_05000120 (1)
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
 /* SIGNBITS Instruction Not Functional under Certain Conditions */
 #define ANOMALY_05000127 (1)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
 /* IMDMA S1/D1 Channel May Stall */
 #define ANOMALY_05000149 (1)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
 /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
 #define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up@CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
 /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
 #define ANOMALY_05000166 (1)
 /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
@@ -92,10 +46,6 @@
 #define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
 /* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
 #define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
 /* Cache Fill Buffer Data lost */
 #define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
 /* Overlapping Sequencer and Memory Stalls */
@@ -124,8 +74,6 @@
 #define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
 /* PPI Not Functional@Core Voltage < 1Volt */
 #define ANOMALY_05000190 (1)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
 /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
 #define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
 /* Restarting SPORT in Specific Modes May Cause Data Corruption */
@@ -213,10 +161,10 @@
 /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
 #define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
 #define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 /* Temporarily walk around for bug 5423 till this issue is confirmed by
  * official anomaly document. It looks 05000281 still exists on bf561
  * v0.5.
@@ -270,8 +218,6 @@
 #define ANOMALY_05000366 (1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 #define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 #define ANOMALY_05000403 (1)
 /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
@@ -294,16 +240,82 @@
 #define ANOMALY_05000462 (1)
 /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
 #define ANOMALY_05000471 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
+#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
+/* Erroneous Exception when Enabling Cache */
+#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
+/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
+#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
+/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
+#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
+/* Stall in multi-unit DMA operations */
+#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
+/* Allowing the SPORT RX FIFO to fill will cause an overflow */
+#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
+/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
+#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
+/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
+#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
+/* DMA and TESTSET conflict when both are accessing external memory */
+#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
+/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
+#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
+/* MDMA may lose the first few words of a descriptor chain */
+#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
+/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
+#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
+/* DMA engine may lose data due to incorrect handshaking */
+#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
+/* DMA stalls when all three controllers read data from the same source */
+#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
+/* Execution stall when executing in L2 and doing external accesses */
+#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
+/* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
+/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
+#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
+/* DMA Lock-up@CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
+#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
+/* A read from external memory may return a wrong value with data cache enabled */
+#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
+/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
+#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
+/* DMEM_CONTROL<12> is not set on Reset */
+#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
+/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
+#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
+/* DSPID register values incorrect */
+#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
+/* DMA vs Core accesses to external memory */
+#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
+/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
+#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000119 (0)
@@ -316,6 +328,7 @@
 #define ANOMALY_05000353 (1)
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (1)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000400 (0)
@@ -330,6 +343,7 @@
 #define ANOMALY_05000465 (0)
 #define ANOMALY_05000467 (0)
 #define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
 #define ANOMALY_05000485 (0)
 
 #endif
-- 
1.7.5.3

[U-Boot] [PATCH 18/18] Blackfin: adi boards: also set stderr to nc with helper

[Mike Frysinger]

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bfin_adi_common.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 80f8a14..57d9b97 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -204,7 +204,8 @@
 	"nc=" \
 		"set ncip ${serverip};" \
 		"set stdin nc;" \
-		"set stdout nc" \
+		"set stdout nc;" \
+		"set stderr nc" \
 		"\0"
 # else
 #  define NETCONSOLE_ENV
-- 
1.7.5.3

[U-Boot] Pull request u-boot-blackfin.git

[Mike Frysinger]

The following changes since commit b1af6f532e0d348b153d5c148369229d24af361a:

  Prepare v2011.06 (2011-06-27 22:22:42 +0200)

are available in the git repository at:
  git://www.denx.de/git/u-boot-blackfin.git master

Harald Krapfenbauer (2):
      Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings
      Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support

Mike Frysinger (16):
      Blackfin: uart: move debug buffers into local bss
      Blackfin: uart: add multiple serial support
      Blackfin: adi boards: enable multi serial support by default
      Blackfin: dont reset SWRST on newer bf526 parts
      Blackfin: add init.elf helper code
      Blackfin: uart: fix printf warning
      Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDR
      Blackfin: gpio: optimize free path a little
      Blackfin: sync MMR read/write helpers with Linux
      Blackfin: portmux: allow header to be included in assembly files
      Blackfin: drop unused dma.h header from start code
      Blackfin: adi boards: enable pretty flash progress output
      Blackfin: split out async setup
      Blackfin: serial: convert to bfin_{read,write} helpers
      Blackfin: update anomaly lists to latest public info
      Blackfin: adi boards: also set stderr to nc with helper

 Makefile                                       |    3 +-
 arch/blackfin/cpu/.gitignore                   |    3 +
 arch/blackfin/cpu/Makefile                     |    7 +-
 arch/blackfin/cpu/cpu.c                        |   16 +-
 arch/blackfin/cpu/gpio.c                       |    2 +
 arch/blackfin/cpu/init.S                       |    9 +
 arch/blackfin/cpu/init.lds.S                   |   25 +++
 arch/blackfin/cpu/initcode.c                   |   61 ++-----
 arch/blackfin/cpu/initcode.h                   |   71 +++++++
 arch/blackfin/cpu/reset.c                      |    4 +-
 arch/blackfin/cpu/serial.c                     |  234 ++++++++++++++++++------
 arch/blackfin/cpu/serial.h                     |   60 ++++--
 arch/blackfin/cpu/start.S                      |    1 -
 arch/blackfin/include/asm/blackfin_local.h     |   88 +++++-----
 arch/blackfin/include/asm/config.h             |    3 +
 arch/blackfin/include/asm/gpio.h               |    3 +-
 arch/blackfin/include/asm/mach-bf506/anomaly.h |   25 ++-
 arch/blackfin/include/asm/mach-bf518/anomaly.h |   28 ++-
 arch/blackfin/include/asm/mach-bf527/anomaly.h |   38 +++--
 arch/blackfin/include/asm/mach-bf533/anomaly.h |   23 ++-
 arch/blackfin/include/asm/mach-bf537/anomaly.h |   37 +++--
 arch/blackfin/include/asm/mach-bf538/anomaly.h |   42 +++--
 arch/blackfin/include/asm/mach-bf548/anomaly.h |  227 +++++++++++++----------
 arch/blackfin/include/asm/mach-bf561/anomaly.h |  136 ++++++++------
 arch/blackfin/include/asm/portmux.h            |    4 +
 arch/blackfin/lib/board.c                      |    4 +
 board/cm-bf537e/cm-bf537e.c                    |   34 +++--
 board/cm-bf537u/cm-bf537u.c                    |   39 ++--
 board/tcm-bf537/tcm-bf537.c                    |   34 +++--
 common/serial.c                                |    3 +
 include/configs/bf537-stamp.h                  |    1 -
 include/configs/bfin_adi_common.h              |   12 +-
 include/configs/cm-bf537e.h                    |   20 ++-
 include/configs/cm-bf537u.h                    |   24 ++-
 include/configs/tcm-bf537.h                    |   20 ++-
 include/serial.h                               |    9 +
 36 files changed, 896 insertions(+), 454 deletions(-)
 create mode 100644 arch/blackfin/cpu/init.S
 create mode 100644 arch/blackfin/cpu/init.lds.S
 create mode 100644 arch/blackfin/cpu/initcode.h

[U-Boot] [PATCH 00/18] Blackfin updates for v2011.09

[Wolfgang Denk]

Dear Mike Frysinger,

In message <1309289787-7846-1-git-send-email-vapier@gentoo.org> you wrote:
> Many of these have been posted already, but some have not.  We've pulled
> some updates from the Linux port, added support for multiple serial devs
> at the same time, and random tweaks/improvements all over.
> 
> Harald Krapfenbauer (2):
>   Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings
>   Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support
> 
> Mike Frysinger (16):
>   Blackfin: uart: move debug buffers into local bss
>   Blackfin: uart: add multiple serial support
>   Blackfin: adi boards: enable multi serial support by default
>   Blackfin: dont reset SWRST on newer bf526 parts
>   Blackfin: add init.elf helper code
>   Blackfin: uart: fix printf warning
>   Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDR
>   Blackfin: gpio: optimize free path a little
>   Blackfin: sync MMR read/write helpers with Linux
>   Blackfin: portmux: allow header to be included in assembly files
>   Blackfin: drop unused dma.h header from start code
>   Blackfin: adi boards: enable pretty flash progress output
>   Blackfin: split out async setup
>   Blackfin: serial: convert to bfin_{read,write} helpers
>   Blackfin: update anomaly lists to latest public info
>   Blackfin: adi boards: also set stderr to nc with helper

All NAK for disobeying the well known rules.

See previous messages.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Life is a garment we continuously alter, but which  never  seems  to
fit."                                                  - David McCord

[U-Boot] Pull request u-boot-blackfin.git

[Wolfgang Denk]

Dear Mike Frysinger,

In message <1309315854-10359-1-git-send-email-vapier@gentoo.org> you wrote:
> The following changes since commit b1af6f532e0d348b153d5c148369229d24af361a:
> 
>   Prepare v2011.06 (2011-06-27 22:22:42 +0200)
> 
> are available in the git repository at:
>   git://www.denx.de/git/u-boot-blackfin.git master

NAK, as before.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"The more data I punch in this card,  the lighter it becomes, and the
lower the mailing cost."
                     - Stan Kelly-Bootle, "The Devil's DP Dictionary"

[U-Boot] Pull request u-boot-blackfin.git

[Mike Frysinger]

On Wed, Jun 29, 2011 at 17:23, Wolfgang Denk wrote:
> Mike Frysinger wrote:
>> The following changes since commit b1af6f532e0d348b153d5c148369229d24af361a:
>>
>> ? Prepare v2011.06 (2011-06-27 22:22:42 +0200)
>>
>> are available in the git repository at:
>> ? git://www.denx.de/git/u-boot-blackfin.git master
>
> NAK, as before.

i sent out the pull request immediately for this tree because your
latency tends to be high (and if there was any problems with the
patches, i'd get them fixed and updated the request), and this is how
i'm used to doing things with linux.  the trees are ready before the
merge window opens, not during.  seems u-boot is more of a "do the
development/review during the merge window, and then merge
during/after".  i did not realize that.
-mike

[U-Boot] Pull request u-boot-blackfin.git

[Wolfgang Denk]

Dear Mike Frysinger,

In message <BANLkTimLUUBsrYg3jTgStP55UFQN-O4DyQ@mail.gmail.com> you wrote:
>
> i sent out the pull request immediately for this tree because your
> latency tends to be high (and if there was any problems with the
> patches, i'd get them fixed and updated the request), and this is how
> i'm used to doing things with linux.  the trees are ready before the
> merge window opens, not during.  seems u-boot is more of a "do the
> development/review during the merge window, and then merge
> during/after".  i did not realize that.

Review is supposed to happen between the time the patches get posted
on the mailing list, and the time they get accepted and applied by a
custodian.   Posting a ptach and a pull request for a branch which
includes it at the same time leaves no time for review.

Don't repeat that you posted unchanged stuff.  We cannot know this -
there was no indication in the patches what was changed to their
earlier versions, there was not even an indication like proper
In-reply-to: or References: headers pointing to the earlier posts.

This reposting of unchanged stuff is stupid and counter-productive.
Don't do it.  I will NAK any such reposts, and any pull requests
that include them.


Thanks.

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Veni, Vidi, VISA:
        I came, I saw, I did a little shopping.

[U-Boot] [PATCH 00/18] Blackfin updates for v2011.09

[Mike Frysinger]

On Tue, Jun 28, 2011 at 15:36, Mike Frysinger wrote:
> Many of these have been posted already, but some have not. ?We've pulled
> some updates from the Linux port, added support for multiple serial devs
> at the same time, and random tweaks/improvements all over.
>
> Harald Krapfenbauer (2):
> ?Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings
> ?Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support

i think in this patch series, these are the only two that were sent
out previously.  and they should be unchanged from the previous
posting.
-mike

[U-Boot] [PATCH v2] Blackfin: dont reset SWRST on newer bf526 parts

[Mike Frysinger]

The bug in the BF526 rom when doing a software reset exists only in older
silicon versions, so don't clear SWRST on newer parts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
v2
	- skip 0.1 silicon as well since it seems to work

 arch/blackfin/cpu/reset.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c
index e23dcc7..ff39035 100644
--- a/arch/blackfin/cpu/reset.c
+++ b/arch/blackfin/cpu/reset.c
@@ -51,7 +51,9 @@ static void bfin_reset(void)
 
 	/* The BF526 ROM will crash during reset */
 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-	bfin_read_SWRST();
+	/* Seems to be fixed with newer parts though ... */
+	if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
+		bfin_read_SWRST();
 #endif
 
 	/* Wait for the SWRST write to complete.  Cannot rely on SSYNC
-- 
1.7.6

[U-Boot] [PATCH 19/21] Blackfin: serial: move early debug strings into .rodata section

[Mike Frysinger]

Rewrite the assembly serial_early_puts() helper to place the strings
in the .rodata section rather than embedding them directly in the
.text section.  Using .text is a little simpler, but it doesn't let
people execute out of internal L1 sram (since core reads don't work
on those regions).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/serial.h |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h
index f649e40..8a076dd 100644
--- a/arch/blackfin/cpu/serial.h
+++ b/arch/blackfin/cpu/serial.h
@@ -288,16 +288,16 @@ static inline void serial_early_puts(const char *s)
  */
 #ifdef CONFIG_DEBUG_EARLY_SERIAL
 # define serial_early_puts(str) \
-	call _get_pc; \
-	jump 1f; \
+	.section .rodata; \
+	7: \
 	.ascii "Early:"; \
 	.ascii __FILE__; \
 	.ascii ": "; \
 	.ascii str; \
 	.asciz "\n"; \
-	.align 4; \
-1: \
-	R0 += 2; \
+	.previous; \
+	R0.L = 7b; \
+	R0.H = 7b; \
 	call _serial_puts;
 #else
 # define serial_early_puts(str)
-- 
1.7.6

[U-Boot] [PATCH 20/21] Blackfin: switch to common display_options()

[Mike Frysinger]

Use common code to output the version string rather than doing it
ourselves.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/lib/board.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index e00050c..14ad3e8 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -53,7 +53,7 @@ static inline void serial_early_puts(const char *s)
 
 static int display_banner(void)
 {
-	printf("\n\n%s\n\n", version_string);
+	display_options();
 	printf("CPU:   ADSP %s "
 		"(Detected Rev: 0.%d) "
 		"(%s boot)\n",
-- 
1.7.6

[U-Boot] [PATCH 21/21] Blackfin: jtag-console: fix timer usage

[Mike Frysinger]

Reported-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/jtag-console.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c
index e0f2975..a77358a 100644
--- a/arch/blackfin/cpu/jtag-console.c
+++ b/arch/blackfin/cpu/jtag-console.c
@@ -48,11 +48,11 @@ static inline uint32_t bfin_read_emudat(void)
 static bool jtag_write_emudat(uint32_t emudat)
 {
 	static bool overflowed = false;
-	ulong timeout = get_timer(0) + CONFIG_JTAG_CONSOLE_TIMEOUT;
+	ulong timeout = get_timer(0);
 	while (bfin_read_DBGSTAT() & 0x1) {
 		if (overflowed)
 			return overflowed;
-		if (timeout < get_timer(0))
+		if (get_timer(timeout) > CONFIG_JTAG_CONSOLE_TIMEOUT)
 			overflowed = true;
 	}
 	overflowed = false;
-- 
1.7.6

[U-Boot] [PATCH 00/18] Blackfin updates for v2011.09

[Mike Frysinger]

On Tuesday, June 28, 2011 15:36:09 Mike Frysinger wrote:
> Many of these have been posted already, but some have not.  We've pulled
> some updates from the Linux port, added support for multiple serial devs
> at the same time, and random tweaks/improvements all over.
> 
> Harald Krapfenbauer (2):
>   Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings
>   Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support

these are the only ones that have been previously posted.  they were part of a 
diff patchset for merging that was ultimately split up and the other 
changesets were merged.  these two are unmodified from their previous 
appearance on the list.
-mike
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[U-Boot] Pull request u-boot-blackfin.git

[Mike Frysinger]

The following changes since commit 68d4230c3ccce96a72c5b99e48399bf1796fe3c6:

  powerpc/85xx: Add default usb mode and phy type to hwconfig (2011-07-11 13:24:21 -0500)

are available in the git repository at:
  git://www.denx.de/git/u-boot-blackfin.git master

Harald Krapfenbauer (2):
      Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings
      Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support

Mike Frysinger (19):
      Blackfin: uart: move debug buffers into local bss
      Blackfin: uart: add multiple serial support
      Blackfin: adi boards: enable multi serial support by default
      Blackfin: dont reset SWRST on newer bf526 parts
      Blackfin: add init.elf helper code
      Blackfin: uart: fix printf warning
      Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDR
      Blackfin: gpio: optimize free path a little
      Blackfin: sync MMR read/write helpers with Linux
      Blackfin: portmux: allow header to be included in assembly files
      Blackfin: drop unused dma.h header from start code
      Blackfin: adi boards: enable pretty flash progress output
      Blackfin: split out async setup
      Blackfin: serial: convert to bfin_{read,write} helpers
      Blackfin: update anomaly lists to latest public info
      Blackfin: adi boards: also set stderr to nc with helper
      Blackfin: serial: move early debug strings into .rodata section
      Blackfin: switch to common display_options()
      Blackfin: jtag-console: fix timer usage

 Makefile                                       |    3 +-
 arch/blackfin/cpu/.gitignore                   |    3 +
 arch/blackfin/cpu/Makefile                     |    7 +-
 arch/blackfin/cpu/cpu.c                        |   16 +-
 arch/blackfin/cpu/gpio.c                       |    2 +
 arch/blackfin/cpu/init.S                       |    9 +
 arch/blackfin/cpu/init.lds.S                   |   25 +++
 arch/blackfin/cpu/initcode.c                   |   61 ++-----
 arch/blackfin/cpu/initcode.h                   |   71 +++++++
 arch/blackfin/cpu/jtag-console.c               |    4 +-
 arch/blackfin/cpu/reset.c                      |    4 +-
 arch/blackfin/cpu/serial.c                     |  234 ++++++++++++++++++------
 arch/blackfin/cpu/serial.h                     |   70 +++++---
 arch/blackfin/cpu/start.S                      |    1 -
 arch/blackfin/include/asm/blackfin_local.h     |   88 +++++-----
 arch/blackfin/include/asm/config.h             |    3 +
 arch/blackfin/include/asm/gpio.h               |    3 +-
 arch/blackfin/include/asm/mach-bf506/anomaly.h |   25 ++-
 arch/blackfin/include/asm/mach-bf518/anomaly.h |   28 ++-
 arch/blackfin/include/asm/mach-bf527/anomaly.h |   38 +++--
 arch/blackfin/include/asm/mach-bf533/anomaly.h |   23 ++-
 arch/blackfin/include/asm/mach-bf537/anomaly.h |   37 +++--
 arch/blackfin/include/asm/mach-bf538/anomaly.h |   42 +++--
 arch/blackfin/include/asm/mach-bf548/anomaly.h |  227 +++++++++++++----------
 arch/blackfin/include/asm/mach-bf561/anomaly.h |  136 ++++++++------
 arch/blackfin/include/asm/portmux.h            |    4 +
 arch/blackfin/lib/board.c                      |    6 +-
 board/cm-bf537e/cm-bf537e.c                    |   34 +++--
 board/cm-bf537u/cm-bf537u.c                    |   39 ++--
 board/tcm-bf537/tcm-bf537.c                    |   34 +++--
 common/serial.c                                |    3 +
 include/configs/bf537-stamp.h                  |    1 -
 include/configs/bfin_adi_common.h              |   12 +-
 include/configs/cm-bf537e.h                    |   20 ++-
 include/configs/cm-bf537u.h                    |   24 ++-
 include/configs/tcm-bf537.h                    |   20 ++-
 include/serial.h                               |    9 +
 37 files changed, 904 insertions(+), 462 deletions(-)
 create mode 100644 arch/blackfin/cpu/init.S
 create mode 100644 arch/blackfin/cpu/init.lds.S
 create mode 100644 arch/blackfin/cpu/initcode.h

[U-Boot] Pull request u-boot-blackfin.git

[Wolfgang Denk]

Dear Mike Frysinger,

In message <1310451782-19008-1-git-send-email-vapier@gentoo.org> you wrote:
> The following changes since commit 68d4230c3ccce96a72c5b99e48399bf1796fe3c6:
> 
>   powerpc/85xx: Add default usb mode and phy type to hwconfig (2011-07-11 13:24:21 -0500)
> 
> are available in the git repository at:
>   git://www.denx.de/git/u-boot-blackfin.git master
> 
> Harald Krapfenbauer (2):
>       Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings
>       Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support
> 
> Mike Frysinger (19):
>       Blackfin: uart: move debug buffers into local bss
>       Blackfin: uart: add multiple serial support
>       Blackfin: adi boards: enable multi serial support by default
>       Blackfin: dont reset SWRST on newer bf526 parts
>       Blackfin: add init.elf helper code
>       Blackfin: uart: fix printf warning
>       Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDR
>       Blackfin: gpio: optimize free path a little
>       Blackfin: sync MMR read/write helpers with Linux
>       Blackfin: portmux: allow header to be included in assembly files
>       Blackfin: drop unused dma.h header from start code
>       Blackfin: adi boards: enable pretty flash progress output
>       Blackfin: split out async setup
>       Blackfin: serial: convert to bfin_{read,write} helpers
>       Blackfin: update anomaly lists to latest public info
>       Blackfin: adi boards: also set stderr to nc with helper
>       Blackfin: serial: move early debug strings into .rodata section
>       Blackfin: switch to common display_options()
>       Blackfin: jtag-console: fix timer usage
> 
>  Makefile                                       |    3 +-
>  arch/blackfin/cpu/.gitignore                   |    3 +
>  arch/blackfin/cpu/Makefile                     |    7 +-
>  arch/blackfin/cpu/cpu.c                        |   16 +-
>  arch/blackfin/cpu/gpio.c                       |    2 +
>  arch/blackfin/cpu/init.S                       |    9 +
>  arch/blackfin/cpu/init.lds.S                   |   25 +++
>  arch/blackfin/cpu/initcode.c                   |   61 ++-----
>  arch/blackfin/cpu/initcode.h                   |   71 +++++++
>  arch/blackfin/cpu/jtag-console.c               |    4 +-
>  arch/blackfin/cpu/reset.c                      |    4 +-
>  arch/blackfin/cpu/serial.c                     |  234 ++++++++++++++++++------
>  arch/blackfin/cpu/serial.h                     |   70 +++++---
>  arch/blackfin/cpu/start.S                      |    1 -
>  arch/blackfin/include/asm/blackfin_local.h     |   88 +++++-----
>  arch/blackfin/include/asm/config.h             |    3 +
>  arch/blackfin/include/asm/gpio.h               |    3 +-
>  arch/blackfin/include/asm/mach-bf506/anomaly.h |   25 ++-
>  arch/blackfin/include/asm/mach-bf518/anomaly.h |   28 ++-
>  arch/blackfin/include/asm/mach-bf527/anomaly.h |   38 +++--
>  arch/blackfin/include/asm/mach-bf533/anomaly.h |   23 ++-
>  arch/blackfin/include/asm/mach-bf537/anomaly.h |   37 +++--
>  arch/blackfin/include/asm/mach-bf538/anomaly.h |   42 +++--
>  arch/blackfin/include/asm/mach-bf548/anomaly.h |  227 +++++++++++++----------
>  arch/blackfin/include/asm/mach-bf561/anomaly.h |  136 ++++++++------
>  arch/blackfin/include/asm/portmux.h            |    4 +
>  arch/blackfin/lib/board.c                      |    6 +-
>  board/cm-bf537e/cm-bf537e.c                    |   34 +++--
>  board/cm-bf537u/cm-bf537u.c                    |   39 ++--
>  board/tcm-bf537/tcm-bf537.c                    |   34 +++--
>  common/serial.c                                |    3 +
>  include/configs/bf537-stamp.h                  |    1 -
>  include/configs/bfin_adi_common.h              |   12 +-
>  include/configs/cm-bf537e.h                    |   20 ++-
>  include/configs/cm-bf537u.h                    |   24 ++-
>  include/configs/tcm-bf537.h                    |   20 ++-
>  include/serial.h                               |    9 +
>  37 files changed, 904 insertions(+), 462 deletions(-)
>  create mode 100644 arch/blackfin/cpu/init.S
>  create mode 100644 arch/blackfin/cpu/init.lds.S
>  create mode 100644 arch/blackfin/cpu/initcode.h

Applied, thanks.

Best regards,

Wolfgang Denk

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