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* [PATCH] drm/radeon/kms: fix typo in read_disabled vbios code
@ 2011-07-11 19:45 Alex Deucher
  2011-07-11 20:05 ` Alex Deucher
  0 siblings, 1 reply; 3+ messages in thread
From: Alex Deucher @ 2011-07-11 19:45 UTC (permalink / raw)
  To: airlied, dri-devel

Rom bit changed between pre-PCIE and PCIE asics.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
---
 drivers/gpu/drm/radeon/radeon_bios.c |    7 +++++--
 drivers/gpu/drm/radeon/radeon_reg.h  |    3 ++-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 3fc5fa1..c2dcca5 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -350,7 +350,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 
 	/* enable the rom */
-	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
+	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 
 	/* Disable VGA mode */
 	WREG32(AVIVO_D1VGA_CONTROL,
@@ -412,7 +412,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 
 	/* enable the rom */
-	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
+	if (rdev->flags & RADEON_IS_PCIE)
+		WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
+	else
+		WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 
 	/* Turn off mem requests and CRTC for both controllers */
 	WREG32(RADEON_CRTC_GEN_CNTL,
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index ec93a75..115fa67 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -289,8 +289,9 @@
 #define RADEON_BRUSH_SCALE                  0x1470
 #define RADEON_BRUSH_Y_X                    0x1474
 #define RADEON_BUS_CNTL                     0x0030
+#       define RV370_BUS_BIOS_DIS_ROM        (1 << 2) /* pcie chips */
 #       define RADEON_BUS_MASTER_DIS         (1 << 6)
-#       define RADEON_BUS_BIOS_DIS_ROM       (1 << 12)
+#       define RADEON_BUS_BIOS_DIS_ROM       (1 << 12) /* non-pcie chips, r1xx, r2xx, r300, r350, rv350, r420 */
 #	define RS600_BUS_MASTER_DIS	     (1 << 14)
 #	define RS600_MSI_REARM		     (1 << 20) /* rs600/rs690/rs740 */
 #       define RADEON_BUS_RD_DISCARD_EN      (1 << 24)
-- 
1.7.1.1

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] drm/radeon/kms: fix typo in read_disabled vbios code
  2011-07-11 19:45 [PATCH] drm/radeon/kms: fix typo in read_disabled vbios code Alex Deucher
@ 2011-07-11 20:05 ` Alex Deucher
  2011-07-11 20:22   ` Alex Deucher
  0 siblings, 1 reply; 3+ messages in thread
From: Alex Deucher @ 2011-07-11 20:05 UTC (permalink / raw)
  To: airlied, dri-devel

Ignore this.  new version on the way.

On Mon, Jul 11, 2011 at 3:45 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> Rom bit changed between pre-PCIE and PCIE asics.
>
> Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
> ---
>  drivers/gpu/drm/radeon/radeon_bios.c |    7 +++++--
>  drivers/gpu/drm/radeon/radeon_reg.h  |    3 ++-
>  2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
> index 3fc5fa1..c2dcca5 100644
> --- a/drivers/gpu/drm/radeon/radeon_bios.c
> +++ b/drivers/gpu/drm/radeon/radeon_bios.c
> @@ -350,7 +350,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
>        WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
>
>        /* enable the rom */
> -       WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
> +       WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
>
>        /* Disable VGA mode */
>        WREG32(AVIVO_D1VGA_CONTROL,
> @@ -412,7 +412,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
>        WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
>
>        /* enable the rom */
> -       WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
> +       if (rdev->flags & RADEON_IS_PCIE)
> +               WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
> +       else
> +               WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
>
>        /* Turn off mem requests and CRTC for both controllers */
>        WREG32(RADEON_CRTC_GEN_CNTL,
> diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
> index ec93a75..115fa67 100644
> --- a/drivers/gpu/drm/radeon/radeon_reg.h
> +++ b/drivers/gpu/drm/radeon/radeon_reg.h
> @@ -289,8 +289,9 @@
>  #define RADEON_BRUSH_SCALE                  0x1470
>  #define RADEON_BRUSH_Y_X                    0x1474
>  #define RADEON_BUS_CNTL                     0x0030
> +#       define RV370_BUS_BIOS_DIS_ROM        (1 << 2) /* pcie chips */
>  #       define RADEON_BUS_MASTER_DIS         (1 << 6)
> -#       define RADEON_BUS_BIOS_DIS_ROM       (1 << 12)
> +#       define RADEON_BUS_BIOS_DIS_ROM       (1 << 12) /* non-pcie chips, r1xx, r2xx, r300, r350, rv350, r420 */
>  #      define RS600_BUS_MASTER_DIS          (1 << 14)
>  #      define RS600_MSI_REARM               (1 << 20) /* rs600/rs690/rs740 */
>  #       define RADEON_BUS_RD_DISCARD_EN      (1 << 24)
> --
> 1.7.1.1
>
>

^ permalink raw reply	[flat|nested] 3+ messages in thread
* [PATCH] drm/radeon/kms: fix typo in read_disabled vbios code
  2011-07-11 20:05 ` Alex Deucher
@ 2011-07-11 20:22   ` Alex Deucher
  0 siblings, 0 replies; 3+ messages in thread
From: Alex Deucher @ 2011-07-11 20:22 UTC (permalink / raw)
  To: airlied, dri-devel

BUS_CNTL reg and bits moved between pre-PCIE and PCIE asics.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
---
 drivers/gpu/drm/radeon/radeon_bios.c |   21 +++++++++++++++------
 drivers/gpu/drm/radeon/radeon_reg.h  |    2 ++
 2 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 3fc5fa1..229a20f 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -331,7 +331,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 
 	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 	viph_control = RREG32(RADEON_VIPH_CONTROL);
-	bus_cntl = RREG32(RADEON_BUS_CNTL);
+	bus_cntl = RREG32(RV370_BUS_CNTL);
 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -350,7 +350,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 
 	/* enable the rom */
-	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
+	WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 
 	/* Disable VGA mode */
 	WREG32(AVIVO_D1VGA_CONTROL,
@@ -367,7 +367,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 	/* restore regs */
 	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 	WREG32(RADEON_VIPH_CONTROL, viph_control);
-	WREG32(RADEON_BUS_CNTL, bus_cntl);
+	WREG32(RV370_BUS_CNTL, bus_cntl);
 	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
@@ -390,7 +390,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 
 	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 	viph_control = RREG32(RADEON_VIPH_CONTROL);
-	bus_cntl = RREG32(RADEON_BUS_CNTL);
+	if (rdev->flags & RADEON_IS_PCIE)
+		bus_cntl = RREG32(RV370_BUS_CNTL);
+	else
+		bus_cntl = RREG32(RADEON_BUS_CNTL);
 	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 	crtc2_gen_cntl = 0;
 	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
@@ -412,7 +415,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 
 	/* enable the rom */
-	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
+	if (rdev->flags & RADEON_IS_PCIE)
+		WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
+	else
+		WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 
 	/* Turn off mem requests and CRTC for both controllers */
 	WREG32(RADEON_CRTC_GEN_CNTL,
@@ -439,7 +445,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 	/* restore regs */
 	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 	WREG32(RADEON_VIPH_CONTROL, viph_control);
-	WREG32(RADEON_BUS_CNTL, bus_cntl);
+	if (rdev->flags & RADEON_IS_PCIE)
+		WREG32(RV370_BUS_CNTL, bus_cntl);
+	else
+		WREG32(RADEON_BUS_CNTL, bus_cntl);
 	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index ec93a75..bc44a3d 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -300,6 +300,8 @@
 #       define RADEON_BUS_READ_BURST         (1 << 30)
 #define RADEON_BUS_CNTL1                    0x0034
 #       define RADEON_BUS_WAIT_ON_LOCK_EN    (1 << 4)
+#define RV370_BUS_CNTL                      0x004c
+#       define RV370_BUS_BIOS_DIS_ROM        (1 << 2)
 /* rv370/rv380, rv410, r423/r430/r480, r5xx */
 #define RADEON_MSI_REARM_EN		    0x0160
 #	define RV370_MSI_REARM_EN	     (1 << 0)
-- 
1.7.1.1

^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2011-07-11 20:22 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-07-11 19:45 [PATCH] drm/radeon/kms: fix typo in read_disabled vbios code Alex Deucher
2011-07-11 20:05 ` Alex Deucher
2011-07-11 20:22   ` Alex Deucher

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