* [PATCH 00/24] Memory API batch 4: more conversions
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
This patchset converts a few more devices (and boards) to the memory API.
Nothing is really interesting except for the last patch, which brings
proper PAM support (and better SMRAM emulation). It should also fix the
regressions that were reported in some non-default pc configurations.
The patchset does not depend on or conflict with batch 3 (which was sent
without a batch identifier; the subject was "Memory API updates").
Avi Kivity (24):
apb_pci: convert to memory API
apic: convert to memory API
arm_gic: convert to memory API
arm_sysctl: convert to memory API
arm_timer: convert to memory API
armv7m: convert to memory API
gt64xxx.c: convert to memory API
tusb6010: move declarations to new file tusb6010.h
omap_gpmc/nseries/tusb6010: convert to memory API
onenand: convert to memory API
pcie_host: convert to memory API
ppc405_uc: convert to memory API
ppc4xx_sdram: convert to memory API
stellaris_enet: convert to memory API
sysbus: add a variant of sysbus_init_mmio_cb with an unmap callback
sh_pci: convert to memory API
arm11mpcore: use sysbus_init_mmio_cb2
versatile_pci: convert to memory API
ppce500_pci: convert to sysbus_init_mmio_cb2()
sysbus: remove sysbus_init_mmio_cb()
isa: add isa_address_space()
pci: add pci_address_space()
vga: drop get_system_memory() from vga devices and derivatives
440fx: fix PAM, PCI holes
hw/apb_pci.c | 84 +++++++++++++++-------------------
hw/apic.c | 25 ++++------
hw/arm11mpcore.c | 7 ++-
hw/arm_gic.c | 22 +++------
hw/arm_sysctl.c | 27 ++++-------
hw/arm_timer.c | 55 ++++++++--------------
hw/armv7m.c | 24 ++++------
hw/armv7m_nvic.c | 3 +-
hw/cirrus_vga.c | 12 ++--
hw/devices.h | 7 ---
hw/gt64xxx.c | 36 ++++++--------
hw/isa-bus.c | 6 ++
hw/isa.h | 1 +
hw/mips_jazz.c | 3 +-
hw/mpcore.c | 37 +++++++--------
hw/nseries.c | 1 +
hw/omap.h | 3 +-
hw/omap_gpmc.c | 53 ++++++++++++----------
hw/onenand.c | 69 +++++++++++++++-------------
hw/pc.c | 14 ++++--
hw/pc.h | 18 +++++--
hw/pc_piix.c | 23 +++++++--
hw/pci.c | 5 ++
hw/pci.h | 1 +
hw/pcie_host.c | 98 ++++++++++-----------------------------
hw/pcie_host.h | 12 ++--
hw/piix_pci.c | 114 ++++++++++++++++++++++++++++++++-------------
hw/ppc405.h | 9 ++-
hw/ppc405_boards.c | 18 +++++--
hw/ppc405_uc.c | 128 +++++++++++++++++++++++---------------------------
hw/ppc440.c | 7 ++-
hw/ppc4xx.h | 2 +
hw/ppc4xx_devs.c | 50 ++++++++++++++------
hw/ppce500_pci.c | 12 ++++-
hw/qxl.c | 2 +-
hw/realview_gic.c | 38 +++++++--------
hw/sh_pci.c | 63 +++++++++++++++++--------
hw/stellaris_enet.c | 29 +++++-------
hw/sysbus.c | 9 ++-
hw/sysbus.h | 5 +-
hw/tusb6010.c | 32 ++++++-------
hw/tusb6010.h | 13 +++++
hw/versatile_pci.c | 94 +++++++++++++++++--------------------
hw/vga-isa-mm.c | 15 +++---
hw/vga-isa.c | 5 +-
hw/vga-pci.c | 4 +-
hw/vga.c | 9 ++--
hw/vga_int.h | 4 +-
hw/vmware_vga.c | 9 ++--
49 files changed, 682 insertions(+), 635 deletions(-)
create mode 100644 hw/tusb6010.h
--
1.7.5.3
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 00/24] Memory API batch 4: more conversions
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
This patchset converts a few more devices (and boards) to the memory API.
Nothing is really interesting except for the last patch, which brings
proper PAM support (and better SMRAM emulation). It should also fix the
regressions that were reported in some non-default pc configurations.
The patchset does not depend on or conflict with batch 3 (which was sent
without a batch identifier; the subject was "Memory API updates").
Avi Kivity (24):
apb_pci: convert to memory API
apic: convert to memory API
arm_gic: convert to memory API
arm_sysctl: convert to memory API
arm_timer: convert to memory API
armv7m: convert to memory API
gt64xxx.c: convert to memory API
tusb6010: move declarations to new file tusb6010.h
omap_gpmc/nseries/tusb6010: convert to memory API
onenand: convert to memory API
pcie_host: convert to memory API
ppc405_uc: convert to memory API
ppc4xx_sdram: convert to memory API
stellaris_enet: convert to memory API
sysbus: add a variant of sysbus_init_mmio_cb with an unmap callback
sh_pci: convert to memory API
arm11mpcore: use sysbus_init_mmio_cb2
versatile_pci: convert to memory API
ppce500_pci: convert to sysbus_init_mmio_cb2()
sysbus: remove sysbus_init_mmio_cb()
isa: add isa_address_space()
pci: add pci_address_space()
vga: drop get_system_memory() from vga devices and derivatives
440fx: fix PAM, PCI holes
hw/apb_pci.c | 84 +++++++++++++++-------------------
hw/apic.c | 25 ++++------
hw/arm11mpcore.c | 7 ++-
hw/arm_gic.c | 22 +++------
hw/arm_sysctl.c | 27 ++++-------
hw/arm_timer.c | 55 ++++++++--------------
hw/armv7m.c | 24 ++++------
hw/armv7m_nvic.c | 3 +-
hw/cirrus_vga.c | 12 ++--
hw/devices.h | 7 ---
hw/gt64xxx.c | 36 ++++++--------
hw/isa-bus.c | 6 ++
hw/isa.h | 1 +
hw/mips_jazz.c | 3 +-
hw/mpcore.c | 37 +++++++--------
hw/nseries.c | 1 +
hw/omap.h | 3 +-
hw/omap_gpmc.c | 53 ++++++++++++----------
hw/onenand.c | 69 +++++++++++++++-------------
hw/pc.c | 14 ++++--
hw/pc.h | 18 +++++--
hw/pc_piix.c | 23 +++++++--
hw/pci.c | 5 ++
hw/pci.h | 1 +
hw/pcie_host.c | 98 ++++++++++-----------------------------
hw/pcie_host.h | 12 ++--
hw/piix_pci.c | 114 ++++++++++++++++++++++++++++++++-------------
hw/ppc405.h | 9 ++-
hw/ppc405_boards.c | 18 +++++--
hw/ppc405_uc.c | 128 +++++++++++++++++++++++---------------------------
hw/ppc440.c | 7 ++-
hw/ppc4xx.h | 2 +
hw/ppc4xx_devs.c | 50 ++++++++++++++------
hw/ppce500_pci.c | 12 ++++-
hw/qxl.c | 2 +-
hw/realview_gic.c | 38 +++++++--------
hw/sh_pci.c | 63 +++++++++++++++++--------
hw/stellaris_enet.c | 29 +++++-------
hw/sysbus.c | 9 ++-
hw/sysbus.h | 5 +-
hw/tusb6010.c | 32 ++++++-------
hw/tusb6010.h | 13 +++++
hw/versatile_pci.c | 94 +++++++++++++++++--------------------
hw/vga-isa-mm.c | 15 +++---
hw/vga-isa.c | 5 +-
hw/vga-pci.c | 4 +-
hw/vga.c | 9 ++--
hw/vga_int.h | 4 +-
hw/vmware_vga.c | 9 ++--
49 files changed, 682 insertions(+), 635 deletions(-)
create mode 100644 hw/tusb6010.h
--
1.7.5.3
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH 01/24] apb_pci: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/apb_pci.c | 84 +++++++++++++++++++++++++--------------------------------
1 files changed, 37 insertions(+), 47 deletions(-)
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 1638226..6ee2068 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -31,7 +31,6 @@
#include "pci_host.h"
#include "pci_bridge.h"
#include "pci_internals.h"
-#include "rwhandler.h"
#include "apb_pci.h"
#include "sysemu.h"
#include "exec-memory.h"
@@ -70,7 +69,9 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
typedef struct APBState {
SysBusDevice busdev;
PCIBus *bus;
- ReadWriteHandler pci_config_handler;
+ MemoryRegion apb_config;
+ MemoryRegion pci_config;
+ MemoryRegion pci_ioport;
uint32_t iommu[4];
uint32_t pci_control[16];
uint32_t pci_irq_map[8];
@@ -81,7 +82,7 @@ typedef struct APBState {
} APBState;
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
APBState *s = opaque;
@@ -128,8 +129,8 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
}
}
-static uint32_t apb_config_readl (void *opaque,
- target_phys_addr_t addr)
+static uint64_t apb_config_readl (void *opaque,
+ target_phys_addr_t addr, unsigned size)
{
APBState *s = opaque;
uint32_t val;
@@ -176,33 +177,27 @@ static uint32_t apb_config_readl (void *opaque,
return val;
}
-static CPUWriteMemoryFunc * const apb_config_write[] = {
- &apb_config_writel,
- &apb_config_writel,
- &apb_config_writel,
+static const MemoryRegionOps apb_config_ops = {
+ .read = apb_config_readl,
+ .write = apb_config_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUReadMemoryFunc * const apb_config_read[] = {
- &apb_config_readl,
- &apb_config_readl,
- &apb_config_readl,
-};
-
-static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
- uint32_t val, int size)
+static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
- APBState *s = container_of(h, APBState, pci_config_handler);
+ APBState *s = opaque;
val = qemu_bswap_len(val, size);
APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
pci_data_write(s->bus, addr, val, size);
}
-static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
- int size)
+static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t ret;
- APBState *s = container_of(h, APBState, pci_config_handler);
+ APBState *s = opaque;
ret = pci_data_read(s->bus, addr, size);
ret = qemu_bswap_len(ret, size);
@@ -252,16 +247,12 @@ static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
return val;
}
-static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
- &pci_apb_iowriteb,
- &pci_apb_iowritew,
- &pci_apb_iowritel,
-};
-
-static CPUReadMemoryFunc * const pci_apb_ioread[] = {
- &pci_apb_ioreadb,
- &pci_apb_ioreadw,
- &pci_apb_ioreadl,
+static const MemoryRegionOps pci_ioport_ops = {
+ .old_mmio = {
+ .read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl },
+ .write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* The APB host has an IRQ line for each IRQ line of each slot. */
@@ -393,10 +384,15 @@ static void pci_pbm_reset(DeviceState *d)
}
}
+static const MemoryRegionOps pci_config_ops = {
+ .read = apb_pci_config_read,
+ .write = apb_pci_config_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
static int pci_pbm_init_device(SysBusDevice *dev)
{
APBState *s;
- int pci_config, apb_config, pci_ioport;
unsigned int i;
s = FROM_SYSBUS(APBState, dev);
@@ -408,27 +404,21 @@ static int pci_pbm_init_device(SysBusDevice *dev)
}
/* apb_config */
- apb_config = cpu_register_io_memory(apb_config_read,
- apb_config_write, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
+ 0x10000);
/* at region 0 */
- sysbus_init_mmio(dev, 0x10000ULL, apb_config);
+ sysbus_init_mmio_region(dev, &s->apb_config);
- /* PCI configuration space */
- s->pci_config_handler.read = apb_pci_config_read;
- s->pci_config_handler.write = apb_pci_config_write;
- pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
- DEVICE_NATIVE_ENDIAN);
- assert(pci_config >= 0);
+ memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
+ 0x1000000);
/* at region 1 */
- sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
+ sysbus_init_mmio_region(dev, &s->pci_config);
/* pci_ioport */
- pci_ioport = cpu_register_io_memory(pci_apb_ioread,
- pci_apb_iowrite, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
+ "apb-pci-ioport", 0x10000);
/* at region 2 */
- sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
+ sysbus_init_mmio_region(dev, &s->pci_ioport);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 01/24] apb_pci: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/apb_pci.c | 84 +++++++++++++++++++++++++--------------------------------
1 files changed, 37 insertions(+), 47 deletions(-)
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 1638226..6ee2068 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -31,7 +31,6 @@
#include "pci_host.h"
#include "pci_bridge.h"
#include "pci_internals.h"
-#include "rwhandler.h"
#include "apb_pci.h"
#include "sysemu.h"
#include "exec-memory.h"
@@ -70,7 +69,9 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
typedef struct APBState {
SysBusDevice busdev;
PCIBus *bus;
- ReadWriteHandler pci_config_handler;
+ MemoryRegion apb_config;
+ MemoryRegion pci_config;
+ MemoryRegion pci_ioport;
uint32_t iommu[4];
uint32_t pci_control[16];
uint32_t pci_irq_map[8];
@@ -81,7 +82,7 @@ typedef struct APBState {
} APBState;
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
APBState *s = opaque;
@@ -128,8 +129,8 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
}
}
-static uint32_t apb_config_readl (void *opaque,
- target_phys_addr_t addr)
+static uint64_t apb_config_readl (void *opaque,
+ target_phys_addr_t addr, unsigned size)
{
APBState *s = opaque;
uint32_t val;
@@ -176,33 +177,27 @@ static uint32_t apb_config_readl (void *opaque,
return val;
}
-static CPUWriteMemoryFunc * const apb_config_write[] = {
- &apb_config_writel,
- &apb_config_writel,
- &apb_config_writel,
+static const MemoryRegionOps apb_config_ops = {
+ .read = apb_config_readl,
+ .write = apb_config_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUReadMemoryFunc * const apb_config_read[] = {
- &apb_config_readl,
- &apb_config_readl,
- &apb_config_readl,
-};
-
-static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
- uint32_t val, int size)
+static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
- APBState *s = container_of(h, APBState, pci_config_handler);
+ APBState *s = opaque;
val = qemu_bswap_len(val, size);
APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
pci_data_write(s->bus, addr, val, size);
}
-static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
- int size)
+static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t ret;
- APBState *s = container_of(h, APBState, pci_config_handler);
+ APBState *s = opaque;
ret = pci_data_read(s->bus, addr, size);
ret = qemu_bswap_len(ret, size);
@@ -252,16 +247,12 @@ static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
return val;
}
-static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
- &pci_apb_iowriteb,
- &pci_apb_iowritew,
- &pci_apb_iowritel,
-};
-
-static CPUReadMemoryFunc * const pci_apb_ioread[] = {
- &pci_apb_ioreadb,
- &pci_apb_ioreadw,
- &pci_apb_ioreadl,
+static const MemoryRegionOps pci_ioport_ops = {
+ .old_mmio = {
+ .read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl },
+ .write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* The APB host has an IRQ line for each IRQ line of each slot. */
@@ -393,10 +384,15 @@ static void pci_pbm_reset(DeviceState *d)
}
}
+static const MemoryRegionOps pci_config_ops = {
+ .read = apb_pci_config_read,
+ .write = apb_pci_config_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
static int pci_pbm_init_device(SysBusDevice *dev)
{
APBState *s;
- int pci_config, apb_config, pci_ioport;
unsigned int i;
s = FROM_SYSBUS(APBState, dev);
@@ -408,27 +404,21 @@ static int pci_pbm_init_device(SysBusDevice *dev)
}
/* apb_config */
- apb_config = cpu_register_io_memory(apb_config_read,
- apb_config_write, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
+ 0x10000);
/* at region 0 */
- sysbus_init_mmio(dev, 0x10000ULL, apb_config);
+ sysbus_init_mmio_region(dev, &s->apb_config);
- /* PCI configuration space */
- s->pci_config_handler.read = apb_pci_config_read;
- s->pci_config_handler.write = apb_pci_config_write;
- pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
- DEVICE_NATIVE_ENDIAN);
- assert(pci_config >= 0);
+ memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
+ 0x1000000);
/* at region 1 */
- sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
+ sysbus_init_mmio_region(dev, &s->pci_config);
/* pci_ioport */
- pci_ioport = cpu_register_io_memory(pci_apb_ioread,
- pci_apb_iowrite, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
+ "apb-pci-ioport", 0x10000);
/* at region 2 */
- sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
+ sysbus_init_mmio_region(dev, &s->pci_ioport);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 02/24] apic: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/apic.c | 25 ++++++++++---------------
1 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/hw/apic.c b/hw/apic.c
index 9febf40..7d0b0f6 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -80,6 +80,7 @@ typedef struct APICState APICState;
struct APICState {
SysBusDevice busdev;
+ MemoryRegion io_memory;
void *cpu_env;
uint32_t apicbase;
uint8_t id;
@@ -979,31 +980,25 @@ static void apic_reset(DeviceState *d)
}
}
-static CPUReadMemoryFunc * const apic_mem_read[3] = {
- apic_mem_readb,
- apic_mem_readw,
- apic_mem_readl,
-};
-
-static CPUWriteMemoryFunc * const apic_mem_write[3] = {
- apic_mem_writeb,
- apic_mem_writew,
- apic_mem_writel,
+static const MemoryRegionOps apic_io_ops = {
+ .old_mmio = {
+ .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
+ .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int apic_init1(SysBusDevice *dev)
{
APICState *s = FROM_SYSBUS(APICState, dev);
- int apic_io_memory;
static int last_apic_idx;
if (last_apic_idx >= MAX_APICS) {
return -1;
}
- apic_io_memory = cpu_register_io_memory(apic_mem_read,
- apic_mem_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
+ memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic",
+ MSI_ADDR_SIZE);
+ sysbus_init_mmio_region(dev, &s->io_memory);
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
s->idx = last_apic_idx++;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 02/24] apic: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/apic.c | 25 ++++++++++---------------
1 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/hw/apic.c b/hw/apic.c
index 9febf40..7d0b0f6 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -80,6 +80,7 @@ typedef struct APICState APICState;
struct APICState {
SysBusDevice busdev;
+ MemoryRegion io_memory;
void *cpu_env;
uint32_t apicbase;
uint8_t id;
@@ -979,31 +980,25 @@ static void apic_reset(DeviceState *d)
}
}
-static CPUReadMemoryFunc * const apic_mem_read[3] = {
- apic_mem_readb,
- apic_mem_readw,
- apic_mem_readl,
-};
-
-static CPUWriteMemoryFunc * const apic_mem_write[3] = {
- apic_mem_writeb,
- apic_mem_writew,
- apic_mem_writel,
+static const MemoryRegionOps apic_io_ops = {
+ .old_mmio = {
+ .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
+ .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int apic_init1(SysBusDevice *dev)
{
APICState *s = FROM_SYSBUS(APICState, dev);
- int apic_io_memory;
static int last_apic_idx;
if (last_apic_idx >= MAX_APICS) {
return -1;
}
- apic_io_memory = cpu_register_io_memory(apic_mem_read,
- apic_mem_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
+ memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic",
+ MSI_ADDR_SIZE);
+ sysbus_init_mmio_region(dev, &s->io_memory);
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
s->idx = last_apic_idx++;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 03/24] arm_gic: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/arm_gic.c | 22 ++++++++--------------
hw/armv7m_nvic.c | 3 ++-
hw/mpcore.c | 37 +++++++++++++++++--------------------
hw/realview_gic.c | 38 +++++++++++++++++---------------------
4 files changed, 44 insertions(+), 56 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index fb07314..83213dd 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -104,7 +104,7 @@ typedef struct gic_state
int num_cpu;
#endif
- int iomemtype;
+ MemoryRegion iomem;
} gic_state;
/* TODO: Many places that call this routine could be optimized. */
@@ -567,16 +567,12 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
gic_dist_writew(opaque, offset + 2, value >> 16);
}
-static CPUReadMemoryFunc * const gic_dist_readfn[] = {
- gic_dist_readb,
- gic_dist_readw,
- gic_dist_readl
-};
-
-static CPUWriteMemoryFunc * const gic_dist_writefn[] = {
- gic_dist_writeb,
- gic_dist_writew,
- gic_dist_writel
+static const MemoryRegionOps gic_dist_ops = {
+ .old_mmio = {
+ .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
+ .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
#ifndef NVIC
@@ -741,9 +737,7 @@ static void gic_init(gic_state *s)
for (i = 0; i < NUM_CPU(s); i++) {
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
}
- s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
- gic_dist_writefn, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
gic_reset(s);
register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s);
}
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index 1df8d4d..bf8c3c5 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -13,6 +13,7 @@
#include "sysbus.h"
#include "qemu-timer.h"
#include "arm-misc.h"
+#include "exec-memory.h"
/* 32 internal lines (16 used for system exceptions) plus 64 external
interrupt lines. */
@@ -384,7 +385,7 @@ static int armv7m_nvic_init(SysBusDevice *dev)
nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev);
gic_init(&s->gic);
- cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype);
+ memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->gic.iomem);
s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
vmstate_register(&dev->qdev, -1, &vmstate_nvic, s);
return 0;
diff --git a/hw/mpcore.c b/hw/mpcore.c
index d778507..d6175cf 100644
--- a/hw/mpcore.c
+++ b/hw/mpcore.c
@@ -40,6 +40,8 @@ typedef struct mpcore_priv_state {
int iomemtype;
mpcore_timer_state timer[8];
uint32_t num_cpu;
+ MemoryRegion iomem;
+ MemoryRegion container;
} mpcore_priv_state;
/* Per-CPU Timers. */
@@ -151,7 +153,8 @@ static void mpcore_timer_init(mpcore_priv_state *mpcore,
/* Per-CPU private memory mapped IO. */
-static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id;
@@ -203,7 +206,7 @@ bad_reg:
}
static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id;
@@ -250,23 +253,19 @@ bad_reg:
hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
}
-static CPUReadMemoryFunc * const mpcore_priv_readfn[] = {
- mpcore_priv_read,
- mpcore_priv_read,
- mpcore_priv_read
+static const MemoryRegionOps mpcore_priv_ops = {
+ .read = mpcore_priv_read,
+ .write = mpcore_priv_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const mpcore_priv_writefn[] = {
- mpcore_priv_write,
- mpcore_priv_write,
- mpcore_priv_write
-};
-
-static void mpcore_priv_map(SysBusDevice *dev, target_phys_addr_t base)
+static void mpcore_priv_map_setup(mpcore_priv_state *s)
{
- mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
- cpu_register_physical_memory(base, 0x1000, s->iomemtype);
- cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype);
+ memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
+ memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv",
+ 0x1000);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+ memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
}
static int mpcore_priv_init(SysBusDevice *dev)
@@ -275,10 +274,8 @@ static int mpcore_priv_init(SysBusDevice *dev)
int i;
gic_init(&s->gic, s->num_cpu);
- s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn,
- mpcore_priv_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map);
+ mpcore_priv_map_setup(s);
+ sysbus_init_mmio_region(dev, &s->container);
for (i = 0; i < s->num_cpu * 2; i++) {
mpcore_timer_init(s, &s->timer[i], i);
}
diff --git a/hw/realview_gic.c b/hw/realview_gic.c
index 43a2a0d..cd6a44d 100644
--- a/hw/realview_gic.c
+++ b/hw/realview_gic.c
@@ -23,39 +23,37 @@ gic_get_current_cpu(void)
typedef struct {
gic_state gic;
- int iomemtype;
+ MemoryRegion iomem;
+ MemoryRegion container;
} RealViewGICState;
-static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset)
+static uint64_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
gic_state *s = (gic_state *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(), offset);
}
static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
gic_state *s = (gic_state *)opaque;
gic_cpu_write(s, gic_get_current_cpu(), offset, value);
}
-static CPUReadMemoryFunc * const realview_gic_cpu_readfn[] = {
- realview_gic_cpu_read,
- realview_gic_cpu_read,
- realview_gic_cpu_read
+static const MemoryRegionOps realview_gic_cpu_ops = {
+ .read = realview_gic_cpu_read,
+ .write = realview_gic_cpu_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = {
- realview_gic_cpu_write,
- realview_gic_cpu_write,
- realview_gic_cpu_write
-};
-
-static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base)
+static void realview_gic_map_setup(RealViewGICState *s)
{
- RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
- cpu_register_physical_memory(base, 0x1000, s->iomemtype);
- cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype);
+ memory_region_init(&s->container, "realview-gic-container", 0x2000);
+ memory_region_init_io(&s->iomem, &realview_gic_cpu_ops, &s->gic,
+ "realview-gic", 0x1000);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+ memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
}
static int realview_gic_init(SysBusDevice *dev)
@@ -63,10 +61,8 @@ static int realview_gic_init(SysBusDevice *dev)
RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
gic_init(&s->gic);
- s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn,
- realview_gic_cpu_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map);
+ realview_gic_map_setup(s);
+ sysbus_init_mmio_region(dev, &s->container);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 03/24] arm_gic: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/arm_gic.c | 22 ++++++++--------------
hw/armv7m_nvic.c | 3 ++-
hw/mpcore.c | 37 +++++++++++++++++--------------------
hw/realview_gic.c | 38 +++++++++++++++++---------------------
4 files changed, 44 insertions(+), 56 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index fb07314..83213dd 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -104,7 +104,7 @@ typedef struct gic_state
int num_cpu;
#endif
- int iomemtype;
+ MemoryRegion iomem;
} gic_state;
/* TODO: Many places that call this routine could be optimized. */
@@ -567,16 +567,12 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
gic_dist_writew(opaque, offset + 2, value >> 16);
}
-static CPUReadMemoryFunc * const gic_dist_readfn[] = {
- gic_dist_readb,
- gic_dist_readw,
- gic_dist_readl
-};
-
-static CPUWriteMemoryFunc * const gic_dist_writefn[] = {
- gic_dist_writeb,
- gic_dist_writew,
- gic_dist_writel
+static const MemoryRegionOps gic_dist_ops = {
+ .old_mmio = {
+ .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
+ .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
#ifndef NVIC
@@ -741,9 +737,7 @@ static void gic_init(gic_state *s)
for (i = 0; i < NUM_CPU(s); i++) {
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
}
- s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
- gic_dist_writefn, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
gic_reset(s);
register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s);
}
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index 1df8d4d..bf8c3c5 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -13,6 +13,7 @@
#include "sysbus.h"
#include "qemu-timer.h"
#include "arm-misc.h"
+#include "exec-memory.h"
/* 32 internal lines (16 used for system exceptions) plus 64 external
interrupt lines. */
@@ -384,7 +385,7 @@ static int armv7m_nvic_init(SysBusDevice *dev)
nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev);
gic_init(&s->gic);
- cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype);
+ memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->gic.iomem);
s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
vmstate_register(&dev->qdev, -1, &vmstate_nvic, s);
return 0;
diff --git a/hw/mpcore.c b/hw/mpcore.c
index d778507..d6175cf 100644
--- a/hw/mpcore.c
+++ b/hw/mpcore.c
@@ -40,6 +40,8 @@ typedef struct mpcore_priv_state {
int iomemtype;
mpcore_timer_state timer[8];
uint32_t num_cpu;
+ MemoryRegion iomem;
+ MemoryRegion container;
} mpcore_priv_state;
/* Per-CPU Timers. */
@@ -151,7 +153,8 @@ static void mpcore_timer_init(mpcore_priv_state *mpcore,
/* Per-CPU private memory mapped IO. */
-static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id;
@@ -203,7 +206,7 @@ bad_reg:
}
static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id;
@@ -250,23 +253,19 @@ bad_reg:
hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
}
-static CPUReadMemoryFunc * const mpcore_priv_readfn[] = {
- mpcore_priv_read,
- mpcore_priv_read,
- mpcore_priv_read
+static const MemoryRegionOps mpcore_priv_ops = {
+ .read = mpcore_priv_read,
+ .write = mpcore_priv_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const mpcore_priv_writefn[] = {
- mpcore_priv_write,
- mpcore_priv_write,
- mpcore_priv_write
-};
-
-static void mpcore_priv_map(SysBusDevice *dev, target_phys_addr_t base)
+static void mpcore_priv_map_setup(mpcore_priv_state *s)
{
- mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
- cpu_register_physical_memory(base, 0x1000, s->iomemtype);
- cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype);
+ memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
+ memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv",
+ 0x1000);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+ memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
}
static int mpcore_priv_init(SysBusDevice *dev)
@@ -275,10 +274,8 @@ static int mpcore_priv_init(SysBusDevice *dev)
int i;
gic_init(&s->gic, s->num_cpu);
- s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn,
- mpcore_priv_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map);
+ mpcore_priv_map_setup(s);
+ sysbus_init_mmio_region(dev, &s->container);
for (i = 0; i < s->num_cpu * 2; i++) {
mpcore_timer_init(s, &s->timer[i], i);
}
diff --git a/hw/realview_gic.c b/hw/realview_gic.c
index 43a2a0d..cd6a44d 100644
--- a/hw/realview_gic.c
+++ b/hw/realview_gic.c
@@ -23,39 +23,37 @@ gic_get_current_cpu(void)
typedef struct {
gic_state gic;
- int iomemtype;
+ MemoryRegion iomem;
+ MemoryRegion container;
} RealViewGICState;
-static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset)
+static uint64_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
gic_state *s = (gic_state *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(), offset);
}
static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
gic_state *s = (gic_state *)opaque;
gic_cpu_write(s, gic_get_current_cpu(), offset, value);
}
-static CPUReadMemoryFunc * const realview_gic_cpu_readfn[] = {
- realview_gic_cpu_read,
- realview_gic_cpu_read,
- realview_gic_cpu_read
+static const MemoryRegionOps realview_gic_cpu_ops = {
+ .read = realview_gic_cpu_read,
+ .write = realview_gic_cpu_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = {
- realview_gic_cpu_write,
- realview_gic_cpu_write,
- realview_gic_cpu_write
-};
-
-static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base)
+static void realview_gic_map_setup(RealViewGICState *s)
{
- RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
- cpu_register_physical_memory(base, 0x1000, s->iomemtype);
- cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype);
+ memory_region_init(&s->container, "realview-gic-container", 0x2000);
+ memory_region_init_io(&s->iomem, &realview_gic_cpu_ops, &s->gic,
+ "realview-gic", 0x1000);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+ memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
}
static int realview_gic_init(SysBusDevice *dev)
@@ -63,10 +61,8 @@ static int realview_gic_init(SysBusDevice *dev)
RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
gic_init(&s->gic);
- s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn,
- realview_gic_cpu_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map);
+ realview_gic_map_setup(s);
+ sysbus_init_mmio_region(dev, &s->container);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 04/24] arm_sysctl: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/arm_sysctl.c | 27 ++++++++++-----------------
1 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index fd0c8bc..1838401 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -17,6 +17,7 @@
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t sys_id;
uint32_t leds;
uint16_t lockval;
@@ -80,7 +81,8 @@ static void arm_sysctl_reset(DeviceState *d)
s->resetlevel = 0;
}
-static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
+static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@@ -177,7 +179,7 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
}
static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
- uint32_t val)
+ uint64_t val, unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@@ -284,16 +286,10 @@ static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
- arm_sysctl_read,
- arm_sysctl_read,
- arm_sysctl_read
-};
-
-static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
- arm_sysctl_write,
- arm_sysctl_write,
- arm_sysctl_write
+static const MemoryRegionOps arm_sysctl_ops = {
+ .read = arm_sysctl_read,
+ .write = arm_sysctl_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void arm_sysctl_gpio_set(void *opaque, int line, int level)
@@ -327,12 +323,9 @@ static void arm_sysctl_gpio_set(void *opaque, int line, int level)
static int arm_sysctl_init1(SysBusDevice *dev)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
- int iomemtype;
- iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
- arm_sysctl_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
+ sysbus_init_mmio_region(dev, &s->iomem);
qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
/* ??? Save/restore. */
return 0;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 04/24] arm_sysctl: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/arm_sysctl.c | 27 ++++++++++-----------------
1 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index fd0c8bc..1838401 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -17,6 +17,7 @@
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t sys_id;
uint32_t leds;
uint16_t lockval;
@@ -80,7 +81,8 @@ static void arm_sysctl_reset(DeviceState *d)
s->resetlevel = 0;
}
-static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
+static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@@ -177,7 +179,7 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
}
static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
- uint32_t val)
+ uint64_t val, unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@@ -284,16 +286,10 @@ static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
- arm_sysctl_read,
- arm_sysctl_read,
- arm_sysctl_read
-};
-
-static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
- arm_sysctl_write,
- arm_sysctl_write,
- arm_sysctl_write
+static const MemoryRegionOps arm_sysctl_ops = {
+ .read = arm_sysctl_read,
+ .write = arm_sysctl_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void arm_sysctl_gpio_set(void *opaque, int line, int level)
@@ -327,12 +323,9 @@ static void arm_sysctl_gpio_set(void *opaque, int line, int level)
static int arm_sysctl_init1(SysBusDevice *dev)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
- int iomemtype;
- iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
- arm_sysctl_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
+ sysbus_init_mmio_region(dev, &s->iomem);
qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
/* ??? Save/restore. */
return 0;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 05/24] arm_timer: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/arm_timer.c | 55 ++++++++++++++++++++-----------------------------------
1 files changed, 20 insertions(+), 35 deletions(-)
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index fd9448f..457736b 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -176,6 +176,7 @@ static arm_timer_state *arm_timer_init(uint32_t freq)
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
arm_timer_state *timer[2];
int level[2];
qemu_irq irq;
@@ -190,7 +191,8 @@ static void sp804_set_irq(void *opaque, int irq, int level)
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
-static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
+static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
@@ -203,7 +205,7 @@ static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
}
static void sp804_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
@@ -214,19 +216,12 @@ static void sp804_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const sp804_readfn[] = {
- sp804_read,
- sp804_read,
- sp804_read
+static const MemoryRegionOps sp804_ops = {
+ .read = sp804_read,
+ .write = sp804_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const sp804_writefn[] = {
- sp804_write,
- sp804_write,
- sp804_write
-};
-
-
static const VMStateDescription vmstate_sp804 = {
.name = "sp804",
.version_id = 1,
@@ -240,7 +235,6 @@ static const VMStateDescription vmstate_sp804 = {
static int sp804_init(SysBusDevice *dev)
{
- int iomemtype;
sp804_state *s = FROM_SYSBUS(sp804_state, dev);
qemu_irq *qi;
@@ -252,9 +246,8 @@ static int sp804_init(SysBusDevice *dev)
s->timer[1] = arm_timer_init(1000000);
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
- iomemtype = cpu_register_io_memory(sp804_readfn,
- sp804_writefn, s, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
+ sysbus_init_mmio_region(dev, &s->iomem);
vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
return 0;
}
@@ -264,10 +257,12 @@ static int sp804_init(SysBusDevice *dev)
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
arm_timer_state *timer[3];
} icp_pit_state;
-static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
+static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
@@ -282,7 +277,7 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
}
static void icp_pit_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
@@ -295,22 +290,14 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset,
arm_timer_write(s->timer[n], offset & 0xff, value);
}
-
-static CPUReadMemoryFunc * const icp_pit_readfn[] = {
- icp_pit_read,
- icp_pit_read,
- icp_pit_read
-};
-
-static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
- icp_pit_write,
- icp_pit_write,
- icp_pit_write
+static const MemoryRegionOps icp_pit_ops = {
+ .read = icp_pit_read,
+ .write = icp_pit_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int icp_pit_init(SysBusDevice *dev)
{
- int iomemtype;
icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
/* Timer 0 runs at the system clock speed (40MHz). */
@@ -323,10 +310,8 @@ static int icp_pit_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->timer[1]->irq);
sysbus_init_irq(dev, &s->timer[2]->irq);
- iomemtype = cpu_register_io_memory(icp_pit_readfn,
- icp_pit_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
+ sysbus_init_mmio_region(dev, &s->iomem);
/* This device has no state to save/restore. The component timers will
save themselves. */
return 0;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 05/24] arm_timer: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/arm_timer.c | 55 ++++++++++++++++++++-----------------------------------
1 files changed, 20 insertions(+), 35 deletions(-)
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index fd9448f..457736b 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -176,6 +176,7 @@ static arm_timer_state *arm_timer_init(uint32_t freq)
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
arm_timer_state *timer[2];
int level[2];
qemu_irq irq;
@@ -190,7 +191,8 @@ static void sp804_set_irq(void *opaque, int irq, int level)
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
-static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
+static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
@@ -203,7 +205,7 @@ static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
}
static void sp804_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
@@ -214,19 +216,12 @@ static void sp804_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const sp804_readfn[] = {
- sp804_read,
- sp804_read,
- sp804_read
+static const MemoryRegionOps sp804_ops = {
+ .read = sp804_read,
+ .write = sp804_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const sp804_writefn[] = {
- sp804_write,
- sp804_write,
- sp804_write
-};
-
-
static const VMStateDescription vmstate_sp804 = {
.name = "sp804",
.version_id = 1,
@@ -240,7 +235,6 @@ static const VMStateDescription vmstate_sp804 = {
static int sp804_init(SysBusDevice *dev)
{
- int iomemtype;
sp804_state *s = FROM_SYSBUS(sp804_state, dev);
qemu_irq *qi;
@@ -252,9 +246,8 @@ static int sp804_init(SysBusDevice *dev)
s->timer[1] = arm_timer_init(1000000);
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
- iomemtype = cpu_register_io_memory(sp804_readfn,
- sp804_writefn, s, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
+ sysbus_init_mmio_region(dev, &s->iomem);
vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
return 0;
}
@@ -264,10 +257,12 @@ static int sp804_init(SysBusDevice *dev)
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
arm_timer_state *timer[3];
} icp_pit_state;
-static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
+static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
@@ -282,7 +277,7 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
}
static void icp_pit_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
@@ -295,22 +290,14 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset,
arm_timer_write(s->timer[n], offset & 0xff, value);
}
-
-static CPUReadMemoryFunc * const icp_pit_readfn[] = {
- icp_pit_read,
- icp_pit_read,
- icp_pit_read
-};
-
-static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
- icp_pit_write,
- icp_pit_write,
- icp_pit_write
+static const MemoryRegionOps icp_pit_ops = {
+ .read = icp_pit_read,
+ .write = icp_pit_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int icp_pit_init(SysBusDevice *dev)
{
- int iomemtype;
icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
/* Timer 0 runs at the system clock speed (40MHz). */
@@ -323,10 +310,8 @@ static int icp_pit_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->timer[1]->irq);
sysbus_init_irq(dev, &s->timer[2]->irq);
- iomemtype = cpu_register_io_memory(icp_pit_readfn,
- icp_pit_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
+ sysbus_init_mmio_region(dev, &s->iomem);
/* This device has no state to save/restore. The component timers will
save themselves. */
return 0;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 06/24] armv7m: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/armv7m.c | 24 ++++++++++--------------
1 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 83f3393..a932f16 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -106,31 +106,27 @@ static void bitband_writel(void *opaque, target_phys_addr_t offset,
cpu_physical_memory_write(addr, (uint8_t *)&v, 4);
}
-static CPUReadMemoryFunc * const bitband_readfn[] = {
- bitband_readb,
- bitband_readw,
- bitband_readl
-};
-
-static CPUWriteMemoryFunc * const bitband_writefn[] = {
- bitband_writeb,
- bitband_writew,
- bitband_writel
+static const MemoryRegionOps bitband_ops = {
+ .old_mmio = {
+ .read = { bitband_readb, bitband_readw, bitband_readl, },
+ .write = { bitband_writeb, bitband_writew, bitband_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t base;
} BitBandState;
static int bitband_init(SysBusDevice *dev)
{
BitBandState *s = FROM_SYSBUS(BitBandState, dev);
- int iomemtype;
- iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,
- &s->base, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x02000000, iomemtype);
+ memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband",
+ 0x02000000);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 06/24] armv7m: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/armv7m.c | 24 ++++++++++--------------
1 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 83f3393..a932f16 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -106,31 +106,27 @@ static void bitband_writel(void *opaque, target_phys_addr_t offset,
cpu_physical_memory_write(addr, (uint8_t *)&v, 4);
}
-static CPUReadMemoryFunc * const bitband_readfn[] = {
- bitband_readb,
- bitband_readw,
- bitband_readl
-};
-
-static CPUWriteMemoryFunc * const bitband_writefn[] = {
- bitband_writeb,
- bitband_writew,
- bitband_writel
+static const MemoryRegionOps bitband_ops = {
+ .old_mmio = {
+ .read = { bitband_readb, bitband_readw, bitband_readl, },
+ .write = { bitband_writeb, bitband_writew, bitband_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t base;
} BitBandState;
static int bitband_init(SysBusDevice *dev)
{
BitBandState *s = FROM_SYSBUS(BitBandState, dev);
- int iomemtype;
- iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,
- &s->base, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x02000000, iomemtype);
+ memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband",
+ 0x02000000);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 07/24] gt64xxx.c: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/gt64xxx.c | 36 +++++++++++++++---------------------
1 files changed, 15 insertions(+), 21 deletions(-)
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index d541558..6af9782 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -227,7 +227,7 @@
#define PCI_MAPPING_ENTRY(regname) \
target_phys_addr_t regname ##_start; \
target_phys_addr_t regname ##_length; \
- int regname ##_handle
+ MemoryRegion regname ##_mem
typedef struct GT64120State {
SysBusDevice busdev;
@@ -269,9 +269,9 @@ static void gt64120_isd_mapping(GT64120State *s)
target_phys_addr_t start = s->regs[GT_ISD] << 21;
target_phys_addr_t length = 0x1000;
- if (s->ISD_length)
- cpu_register_physical_memory(s->ISD_start, s->ISD_length,
- IO_MEM_UNASSIGNED);
+ if (s->ISD_length) {
+ memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
+ }
check_reserved_space(&start, &length);
length = 0x1000;
/* Map new address */
@@ -279,7 +279,7 @@ static void gt64120_isd_mapping(GT64120State *s)
length, start, s->ISD_handle);
s->ISD_start = start;
s->ISD_length = length;
- cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
+ memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
}
static void gt64120_pci_mapping(GT64120State *s)
@@ -290,7 +290,8 @@ static void gt64120_pci_mapping(GT64120State *s)
/* Unmap old IO address */
if (s->PCI0IO_length)
{
- cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
+ memory_region_destroy(&s->PCI0IO_mem);
}
/* Map new IO address */
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
@@ -301,7 +302,7 @@ static void gt64120_pci_mapping(GT64120State *s)
}
static void gt64120_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
GT64120State *s = opaque;
uint32_t saddr;
@@ -579,8 +580,8 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
}
}
-static uint32_t gt64120_readl (void *opaque,
- target_phys_addr_t addr)
+static uint64_t gt64120_readl (void *opaque,
+ target_phys_addr_t addr, unsigned size)
{
GT64120State *s = opaque;
uint32_t val;
@@ -851,16 +852,10 @@ static uint32_t gt64120_readl (void *opaque,
return val;
}
-static CPUWriteMemoryFunc * const gt64120_write[] = {
- >64120_writel,
- >64120_writel,
- >64120_writel,
-};
-
-static CPUReadMemoryFunc * const gt64120_read[] = {
- >64120_readl,
- >64120_readl,
- >64120_readl,
+static const MemoryRegionOps isd_mem_ops = {
+ .read = gt64120_readl,
+ .write = gt64120_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
@@ -1097,8 +1092,7 @@ PCIBus *gt64120_register(qemu_irq *pic)
get_system_memory(),
get_system_io(),
PCI_DEVFN(18, 0), 4);
- d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000);
pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci");
return d->pci.bus;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 07/24] gt64xxx.c: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/gt64xxx.c | 36 +++++++++++++++---------------------
1 files changed, 15 insertions(+), 21 deletions(-)
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index d541558..6af9782 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -227,7 +227,7 @@
#define PCI_MAPPING_ENTRY(regname) \
target_phys_addr_t regname ##_start; \
target_phys_addr_t regname ##_length; \
- int regname ##_handle
+ MemoryRegion regname ##_mem
typedef struct GT64120State {
SysBusDevice busdev;
@@ -269,9 +269,9 @@ static void gt64120_isd_mapping(GT64120State *s)
target_phys_addr_t start = s->regs[GT_ISD] << 21;
target_phys_addr_t length = 0x1000;
- if (s->ISD_length)
- cpu_register_physical_memory(s->ISD_start, s->ISD_length,
- IO_MEM_UNASSIGNED);
+ if (s->ISD_length) {
+ memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
+ }
check_reserved_space(&start, &length);
length = 0x1000;
/* Map new address */
@@ -279,7 +279,7 @@ static void gt64120_isd_mapping(GT64120State *s)
length, start, s->ISD_handle);
s->ISD_start = start;
s->ISD_length = length;
- cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
+ memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
}
static void gt64120_pci_mapping(GT64120State *s)
@@ -290,7 +290,8 @@ static void gt64120_pci_mapping(GT64120State *s)
/* Unmap old IO address */
if (s->PCI0IO_length)
{
- cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
+ memory_region_destroy(&s->PCI0IO_mem);
}
/* Map new IO address */
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
@@ -301,7 +302,7 @@ static void gt64120_pci_mapping(GT64120State *s)
}
static void gt64120_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
GT64120State *s = opaque;
uint32_t saddr;
@@ -579,8 +580,8 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
}
}
-static uint32_t gt64120_readl (void *opaque,
- target_phys_addr_t addr)
+static uint64_t gt64120_readl (void *opaque,
+ target_phys_addr_t addr, unsigned size)
{
GT64120State *s = opaque;
uint32_t val;
@@ -851,16 +852,10 @@ static uint32_t gt64120_readl (void *opaque,
return val;
}
-static CPUWriteMemoryFunc * const gt64120_write[] = {
- >64120_writel,
- >64120_writel,
- >64120_writel,
-};
-
-static CPUReadMemoryFunc * const gt64120_read[] = {
- >64120_readl,
- >64120_readl,
- >64120_readl,
+static const MemoryRegionOps isd_mem_ops = {
+ .read = gt64120_readl,
+ .write = gt64120_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
@@ -1097,8 +1092,7 @@ PCIBus *gt64120_register(qemu_irq *pic)
get_system_memory(),
get_system_io(),
PCI_DEVFN(18, 0), 4);
- d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000);
pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci");
return d->pci.bus;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 08/24] tusb6010: move declarations to new file tusb6010.h
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Avoid #include hell.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/devices.h | 7 -------
hw/nseries.c | 1 +
hw/tusb6010.c | 2 +-
hw/tusb6010.h | 10 ++++++++++
4 files changed, 12 insertions(+), 8 deletions(-)
create mode 100644 hw/tusb6010.h
diff --git a/hw/devices.h b/hw/devices.h
index c788373..07fda83 100644
--- a/hw/devices.h
+++ b/hw/devices.h
@@ -47,13 +47,6 @@ void *tahvo_init(qemu_irq irq, int betty);
void retu_key_event(void *retu, int state);
-/* tusb6010.c */
-typedef struct TUSBState TUSBState;
-TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
-void tusb6010_power(TUSBState *s, int on);
-
/* tc6393xb.c */
typedef struct TC6393xbState TC6393xbState;
#define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */
diff --git a/hw/nseries.c b/hw/nseries.c
index 6a5575e..5521f28 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -32,6 +32,7 @@
#include "bt.h"
#include "loader.h"
#include "blockdev.h"
+#include "tusb6010.h"
/* Nokia N8x0 support */
struct n800_s {
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index ccd01ad..add748c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -23,7 +23,7 @@
#include "usb.h"
#include "omap.h"
#include "irq.h"
-#include "devices.h"
+#include "tusb6010.h"
struct TUSBState {
int iomemtype[2];
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
new file mode 100644
index 0000000..6faa94d
--- /dev/null
+++ b/hw/tusb6010.h
@@ -0,0 +1,10 @@
+#ifndef TUSB6010_H
+#define TUSB6010_H
+
+typedef struct TUSBState TUSBState;
+TUSBState *tusb6010_init(qemu_irq intr);
+int tusb6010_sync_io(TUSBState *s);
+int tusb6010_async_io(TUSBState *s);
+void tusb6010_power(TUSBState *s, int on);
+
+#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 08/24] tusb6010: move declarations to new file tusb6010.h
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Avoid #include hell.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/devices.h | 7 -------
hw/nseries.c | 1 +
hw/tusb6010.c | 2 +-
hw/tusb6010.h | 10 ++++++++++
4 files changed, 12 insertions(+), 8 deletions(-)
create mode 100644 hw/tusb6010.h
diff --git a/hw/devices.h b/hw/devices.h
index c788373..07fda83 100644
--- a/hw/devices.h
+++ b/hw/devices.h
@@ -47,13 +47,6 @@ void *tahvo_init(qemu_irq irq, int betty);
void retu_key_event(void *retu, int state);
-/* tusb6010.c */
-typedef struct TUSBState TUSBState;
-TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
-void tusb6010_power(TUSBState *s, int on);
-
/* tc6393xb.c */
typedef struct TC6393xbState TC6393xbState;
#define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */
diff --git a/hw/nseries.c b/hw/nseries.c
index 6a5575e..5521f28 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -32,6 +32,7 @@
#include "bt.h"
#include "loader.h"
#include "blockdev.h"
+#include "tusb6010.h"
/* Nokia N8x0 support */
struct n800_s {
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index ccd01ad..add748c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -23,7 +23,7 @@
#include "usb.h"
#include "omap.h"
#include "irq.h"
-#include "devices.h"
+#include "tusb6010.h"
struct TUSBState {
int iomemtype[2];
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
new file mode 100644
index 0000000..6faa94d
--- /dev/null
+++ b/hw/tusb6010.h
@@ -0,0 +1,10 @@
+#ifndef TUSB6010_H
+#define TUSB6010_H
+
+typedef struct TUSBState TUSBState;
+TUSBState *tusb6010_init(qemu_irq intr);
+int tusb6010_sync_io(TUSBState *s);
+int tusb6010_async_io(TUSBState *s);
+void tusb6010_power(TUSBState *s, int on);
+
+#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Somewhat clumsy since it needs a variable sized region.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/omap.h | 3 ++-
hw/omap_gpmc.c | 53 +++++++++++++++++++++++++++++------------------------
hw/tusb6010.c | 30 +++++++++++++-----------------
hw/tusb6010.h | 7 +++++--
4 files changed, 49 insertions(+), 44 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index a064353..c2fe54c 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -17,6 +17,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef hw_omap_h
+#include "memory.h"
# define hw_omap_h "omap.h"
# define OMAP_EMIFS_BASE 0x00000000
@@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
void omap_gpmc_reset(struct omap_gpmc_s *s);
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque);
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
index 8bf3343..4901aba 100644
--- a/hw/omap_gpmc.c
+++ b/hw/omap_gpmc.c
@@ -21,10 +21,13 @@
#include "hw.h"
#include "flash.h"
#include "omap.h"
+#include "memory.h"
+#include "exec-memory.h"
/* General-Purpose Memory Controller */
struct omap_gpmc_s {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t sysconfig;
uint16_t irqst;
@@ -39,7 +42,8 @@ struct omap_gpmc_s {
uint32_t config[7];
target_phys_addr_t base;
size_t size;
- int iomemtype;
+ MemoryRegion *iomem;
+ MemoryRegion container;
void (*base_update)(void *opaque, target_phys_addr_t new);
void (*unmap)(void *opaque);
void *opaque;
@@ -75,8 +79,12 @@ static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
* constant), the mask should cause wrapping of the address space, so
* that the same memory becomes accessible at every <i>size</i> bytes
* starting from <i>base</i>. */
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, f->iomemtype);
+ if (f->iomem) {
+ memory_region_init(&f->container, "omap-gpmc-file", f->size);
+ memory_region_add_subregion(&f->container, 0, f->iomem);
+ memory_region_add_subregion(get_system_memory(), f->base,
+ &f->container);
+ }
if (f->base_update)
f->base_update(f->opaque, f->base);
@@ -87,8 +95,11 @@ static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
if (f->size) {
if (f->unmap)
f->unmap(f->opaque);
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
+ if (f->iomem) {
+ memory_region_del_subregion(get_system_memory(), &f->container);
+ memory_region_del_subregion(&f->container, f->iomem);
+ memory_region_destroy(&f->container);
+ }
f->base = 0;
f->size = 0;
}
@@ -132,7 +143,8 @@ void omap_gpmc_reset(struct omap_gpmc_s *s)
ecc_reset(&s->ecc[i]);
}
-static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
@@ -230,7 +242,7 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
@@ -249,7 +261,7 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
case 0x010: /* GPMC_SYSCONFIG */
if ((value >> 3) == 0x3)
- fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
+ fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
__FUNCTION__, value >> 3);
if (value & 2)
omap_gpmc_reset(s);
@@ -369,34 +381,27 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
- omap_badwidth_read32, /* TODO */
- omap_badwidth_read32, /* TODO */
- omap_gpmc_read,
-};
-
-static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
- omap_badwidth_write32, /* TODO */
- omap_badwidth_write32, /* TODO */
- omap_gpmc_write,
+static const MemoryRegionOps omap_gpmc_ops = {
+ /* TODO: specialize <4 byte writes? */
+ .read = omap_gpmc_read,
+ .write = omap_gpmc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
{
- int iomemtype;
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
qemu_mallocz(sizeof(struct omap_gpmc_s));
omap_gpmc_reset(s);
- iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
- omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
+ memory_region_add_subregion(get_system_memory(), base, &s->iomem);
return s;
}
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque)
{
@@ -408,7 +413,7 @@ void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
}
f = &s->cs_file[cs];
- f->iomemtype = iomemtype;
+ f->iomem = iomem;
f->base_update = base_upd;
f->unmap = unmap;
f->opaque = opaque;
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index add748c..28ff52c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -26,7 +26,7 @@
#include "tusb6010.h"
struct TUSBState {
- int iomemtype[2];
+ MemoryRegion iomem[2];
qemu_irq irq;
MUSBState *musb;
QEMUTimer *otg_timer;
@@ -234,14 +234,14 @@ struct TUSBState {
#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
#define TUSB_PROD_TEST_RESET_VAL 0xa596
-int tusb6010_sync_io(TUSBState *s)
+MemoryRegion *tusb6010_sync_io(TUSBState *s)
{
- return s->iomemtype[0];
+ return &s->iomem[0];
}
-int tusb6010_async_io(TUSBState *s)
+MemoryRegion *tusb6010_async_io(TUSBState *s)
{
- return s->iomemtype[1];
+ return &s->iomem[1];
}
static void tusb_intr_update(TUSBState *s)
@@ -647,16 +647,12 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const tusb_async_readfn[] = {
- tusb_async_readb,
- tusb_async_readh,
- tusb_async_readw,
-};
-
-static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
- tusb_async_writeb,
- tusb_async_writeh,
- tusb_async_writew,
+static const MemoryRegionOps tusb_async_ops = {
+ .old_mmio = {
+ .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
+ .write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void tusb_otg_tick(void *opaque)
@@ -739,8 +735,8 @@ TUSBState *tusb6010_init(qemu_irq intr)
s->mask = 0xffffffff;
s->intr = 0x00000000;
s->otg_timer_val = 0;
- s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
- tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async",
+ UINT32_MAX);
s->irq = intr;
s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
index 6faa94d..9d53b26 100644
--- a/hw/tusb6010.h
+++ b/hw/tusb6010.h
@@ -1,10 +1,13 @@
#ifndef TUSB6010_H
#define TUSB6010_H
+#include "targphys.h"
+#include "memory.h"
+
typedef struct TUSBState TUSBState;
TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
+MemoryRegion *tusb6010_sync_io(TUSBState *s);
+MemoryRegion *tusb6010_async_io(TUSBState *s);
void tusb6010_power(TUSBState *s, int on);
#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Somewhat clumsy since it needs a variable sized region.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/omap.h | 3 ++-
hw/omap_gpmc.c | 53 +++++++++++++++++++++++++++++------------------------
hw/tusb6010.c | 30 +++++++++++++-----------------
hw/tusb6010.h | 7 +++++--
4 files changed, 49 insertions(+), 44 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index a064353..c2fe54c 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -17,6 +17,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef hw_omap_h
+#include "memory.h"
# define hw_omap_h "omap.h"
# define OMAP_EMIFS_BASE 0x00000000
@@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
void omap_gpmc_reset(struct omap_gpmc_s *s);
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque);
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
index 8bf3343..4901aba 100644
--- a/hw/omap_gpmc.c
+++ b/hw/omap_gpmc.c
@@ -21,10 +21,13 @@
#include "hw.h"
#include "flash.h"
#include "omap.h"
+#include "memory.h"
+#include "exec-memory.h"
/* General-Purpose Memory Controller */
struct omap_gpmc_s {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t sysconfig;
uint16_t irqst;
@@ -39,7 +42,8 @@ struct omap_gpmc_s {
uint32_t config[7];
target_phys_addr_t base;
size_t size;
- int iomemtype;
+ MemoryRegion *iomem;
+ MemoryRegion container;
void (*base_update)(void *opaque, target_phys_addr_t new);
void (*unmap)(void *opaque);
void *opaque;
@@ -75,8 +79,12 @@ static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
* constant), the mask should cause wrapping of the address space, so
* that the same memory becomes accessible at every <i>size</i> bytes
* starting from <i>base</i>. */
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, f->iomemtype);
+ if (f->iomem) {
+ memory_region_init(&f->container, "omap-gpmc-file", f->size);
+ memory_region_add_subregion(&f->container, 0, f->iomem);
+ memory_region_add_subregion(get_system_memory(), f->base,
+ &f->container);
+ }
if (f->base_update)
f->base_update(f->opaque, f->base);
@@ -87,8 +95,11 @@ static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
if (f->size) {
if (f->unmap)
f->unmap(f->opaque);
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
+ if (f->iomem) {
+ memory_region_del_subregion(get_system_memory(), &f->container);
+ memory_region_del_subregion(&f->container, f->iomem);
+ memory_region_destroy(&f->container);
+ }
f->base = 0;
f->size = 0;
}
@@ -132,7 +143,8 @@ void omap_gpmc_reset(struct omap_gpmc_s *s)
ecc_reset(&s->ecc[i]);
}
-static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
@@ -230,7 +242,7 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
@@ -249,7 +261,7 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
case 0x010: /* GPMC_SYSCONFIG */
if ((value >> 3) == 0x3)
- fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
+ fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
__FUNCTION__, value >> 3);
if (value & 2)
omap_gpmc_reset(s);
@@ -369,34 +381,27 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
- omap_badwidth_read32, /* TODO */
- omap_badwidth_read32, /* TODO */
- omap_gpmc_read,
-};
-
-static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
- omap_badwidth_write32, /* TODO */
- omap_badwidth_write32, /* TODO */
- omap_gpmc_write,
+static const MemoryRegionOps omap_gpmc_ops = {
+ /* TODO: specialize <4 byte writes? */
+ .read = omap_gpmc_read,
+ .write = omap_gpmc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
{
- int iomemtype;
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
qemu_mallocz(sizeof(struct omap_gpmc_s));
omap_gpmc_reset(s);
- iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
- omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
+ memory_region_add_subregion(get_system_memory(), base, &s->iomem);
return s;
}
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque)
{
@@ -408,7 +413,7 @@ void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
}
f = &s->cs_file[cs];
- f->iomemtype = iomemtype;
+ f->iomem = iomem;
f->base_update = base_upd;
f->unmap = unmap;
f->opaque = opaque;
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index add748c..28ff52c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -26,7 +26,7 @@
#include "tusb6010.h"
struct TUSBState {
- int iomemtype[2];
+ MemoryRegion iomem[2];
qemu_irq irq;
MUSBState *musb;
QEMUTimer *otg_timer;
@@ -234,14 +234,14 @@ struct TUSBState {
#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
#define TUSB_PROD_TEST_RESET_VAL 0xa596
-int tusb6010_sync_io(TUSBState *s)
+MemoryRegion *tusb6010_sync_io(TUSBState *s)
{
- return s->iomemtype[0];
+ return &s->iomem[0];
}
-int tusb6010_async_io(TUSBState *s)
+MemoryRegion *tusb6010_async_io(TUSBState *s)
{
- return s->iomemtype[1];
+ return &s->iomem[1];
}
static void tusb_intr_update(TUSBState *s)
@@ -647,16 +647,12 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const tusb_async_readfn[] = {
- tusb_async_readb,
- tusb_async_readh,
- tusb_async_readw,
-};
-
-static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
- tusb_async_writeb,
- tusb_async_writeh,
- tusb_async_writew,
+static const MemoryRegionOps tusb_async_ops = {
+ .old_mmio = {
+ .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
+ .write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void tusb_otg_tick(void *opaque)
@@ -739,8 +735,8 @@ TUSBState *tusb6010_init(qemu_irq intr)
s->mask = 0xffffffff;
s->intr = 0x00000000;
s->otg_timer_val = 0;
- s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
- tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async",
+ UINT32_MAX);
s->irq = intr;
s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
index 6faa94d..9d53b26 100644
--- a/hw/tusb6010.h
+++ b/hw/tusb6010.h
@@ -1,10 +1,13 @@
#ifndef TUSB6010_H
#define TUSB6010_H
+#include "targphys.h"
+#include "memory.h"
+
typedef struct TUSBState TUSBState;
TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
+MemoryRegion *tusb6010_sync_io(TUSBState *s);
+MemoryRegion *tusb6010_async_io(TUSBState *s);
void tusb6010_power(TUSBState *s, int on);
#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 10/24] onenand: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/onenand.c | 69 +++++++++++++++++++++++++++++++--------------------------
1 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/hw/onenand.c b/hw/onenand.c
index b0cbebc..5b2f01e 100644
--- a/hw/onenand.c
+++ b/hw/onenand.c
@@ -23,6 +23,8 @@
#include "flash.h"
#include "irq.h"
#include "blockdev.h"
+#include "memory.h"
+#include "exec-memory.h"
/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
#define PAGE_SHIFT 11
@@ -45,10 +47,12 @@ typedef struct {
uint8_t *image;
uint8_t *otp;
uint8_t *current;
- ram_addr_t ram;
+ MemoryRegion ram;
+ MemoryRegion mapped_ram;
uint8_t *boot[2];
uint8_t *data[2][2];
- int iomemtype;
+ MemoryRegion iomem;
+ MemoryRegion container;
int cycle;
int otpmode;
@@ -100,31 +104,36 @@ enum {
ONEN_LOCK_UNLOCKED = 1 << 2,
};
+static void onenand_mem_setup(OneNANDState *s)
+{
+ /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
+ * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
+ * write boot commands. Also take note of the BWPS bit. */
+ memory_region_init(&s->container, "onenand", 0x10000 << s->shift);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+ memory_region_init_alias(&s->mapped_ram, "onenand-mapped-ram",
+ &s->ram, 0x0200 << s->shift,
+ 0xbe00 << s->shift);
+ memory_region_add_subregion_overlap(&s->container,
+ 0x0200 << s->shift,
+ &s->mapped_ram,
+ 1);
+}
+
void onenand_base_update(void *opaque, target_phys_addr_t new)
{
OneNANDState *s = (OneNANDState *) opaque;
s->base = new;
- /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
- * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
- * write boot commands. Also take note of the BWPS bit. */
- cpu_register_physical_memory(s->base + (0x0000 << s->shift),
- 0x0200 << s->shift, s->iomemtype);
- cpu_register_physical_memory(s->base + (0x0200 << s->shift),
- 0xbe00 << s->shift,
- (s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
- if (s->iomemtype)
- cpu_register_physical_memory_offset(s->base + (0xc000 << s->shift),
- 0x4000 << s->shift, s->iomemtype, (0xc000 << s->shift));
+ memory_region_add_subregion(get_system_memory(), s->base, &s->container);
}
void onenand_base_unmap(void *opaque)
{
OneNANDState *s = (OneNANDState *) opaque;
- cpu_register_physical_memory(s->base,
- 0x10000 << s->shift, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &s->container);
}
static void onenand_intr_update(OneNANDState *s)
@@ -524,7 +533,8 @@ static void onenand_command(OneNANDState *s, int cmd)
onenand_intr_update(s);
}
-static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
+static uint64_t onenand_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
@@ -589,7 +599,7 @@ static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
}
static void onenand_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
@@ -628,7 +638,7 @@ static void onenand_write(void *opaque, target_phys_addr_t addr,
break;
default:
- fprintf(stderr, "%s: unknown OneNAND boot command %x\n",
+ fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
__FUNCTION__, value);
}
break;
@@ -684,16 +694,10 @@ static void onenand_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const onenand_readfn[] = {
- onenand_read, /* TODO */
- onenand_read,
- onenand_read,
-};
-
-static CPUWriteMemoryFunc * const onenand_writefn[] = {
- onenand_write, /* TODO */
- onenand_write,
- onenand_write,
+static const MemoryRegionOps onenand_ops = {
+ .read = onenand_read,
+ .write = onenand_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
void *onenand_init(BlockDriverState *bdrv,
@@ -714,8 +718,8 @@ void *onenand_init(BlockDriverState *bdrv,
s->secs = size >> 9;
s->blockwp = qemu_malloc(s->blocks);
s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0;
- s->iomemtype = cpu_register_io_memory(onenand_readfn,
- onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &onenand_ops, s, "onenand",
+ 0x10000 << s->shift);
s->bdrv = bdrv;
if (!s->bdrv) {
s->image = memset(qemu_malloc(size + (size >> 5)),
@@ -723,14 +727,15 @@ void *onenand_init(BlockDriverState *bdrv,
}
s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
- s->ram = qemu_ram_alloc(NULL, "onenand.ram", 0xc000 << s->shift);
- ram = qemu_get_ram_ptr(s->ram);
+ memory_region_init_ram(&s->ram, NULL, "onenand.ram", 0xc000 << s->shift);
+ ram = memory_region_get_ram_ptr(&s->ram);
s->boot[0] = ram + (0x0000 << s->shift);
s->boot[1] = ram + (0x8000 << s->shift);
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift);
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift);
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift);
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift);
+ onenand_mem_setup(s);
onenand_reset(s, 1);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 10/24] onenand: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/onenand.c | 69 +++++++++++++++++++++++++++++++--------------------------
1 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/hw/onenand.c b/hw/onenand.c
index b0cbebc..5b2f01e 100644
--- a/hw/onenand.c
+++ b/hw/onenand.c
@@ -23,6 +23,8 @@
#include "flash.h"
#include "irq.h"
#include "blockdev.h"
+#include "memory.h"
+#include "exec-memory.h"
/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
#define PAGE_SHIFT 11
@@ -45,10 +47,12 @@ typedef struct {
uint8_t *image;
uint8_t *otp;
uint8_t *current;
- ram_addr_t ram;
+ MemoryRegion ram;
+ MemoryRegion mapped_ram;
uint8_t *boot[2];
uint8_t *data[2][2];
- int iomemtype;
+ MemoryRegion iomem;
+ MemoryRegion container;
int cycle;
int otpmode;
@@ -100,31 +104,36 @@ enum {
ONEN_LOCK_UNLOCKED = 1 << 2,
};
+static void onenand_mem_setup(OneNANDState *s)
+{
+ /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
+ * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
+ * write boot commands. Also take note of the BWPS bit. */
+ memory_region_init(&s->container, "onenand", 0x10000 << s->shift);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+ memory_region_init_alias(&s->mapped_ram, "onenand-mapped-ram",
+ &s->ram, 0x0200 << s->shift,
+ 0xbe00 << s->shift);
+ memory_region_add_subregion_overlap(&s->container,
+ 0x0200 << s->shift,
+ &s->mapped_ram,
+ 1);
+}
+
void onenand_base_update(void *opaque, target_phys_addr_t new)
{
OneNANDState *s = (OneNANDState *) opaque;
s->base = new;
- /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
- * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
- * write boot commands. Also take note of the BWPS bit. */
- cpu_register_physical_memory(s->base + (0x0000 << s->shift),
- 0x0200 << s->shift, s->iomemtype);
- cpu_register_physical_memory(s->base + (0x0200 << s->shift),
- 0xbe00 << s->shift,
- (s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
- if (s->iomemtype)
- cpu_register_physical_memory_offset(s->base + (0xc000 << s->shift),
- 0x4000 << s->shift, s->iomemtype, (0xc000 << s->shift));
+ memory_region_add_subregion(get_system_memory(), s->base, &s->container);
}
void onenand_base_unmap(void *opaque)
{
OneNANDState *s = (OneNANDState *) opaque;
- cpu_register_physical_memory(s->base,
- 0x10000 << s->shift, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &s->container);
}
static void onenand_intr_update(OneNANDState *s)
@@ -524,7 +533,8 @@ static void onenand_command(OneNANDState *s, int cmd)
onenand_intr_update(s);
}
-static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
+static uint64_t onenand_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
@@ -589,7 +599,7 @@ static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
}
static void onenand_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
@@ -628,7 +638,7 @@ static void onenand_write(void *opaque, target_phys_addr_t addr,
break;
default:
- fprintf(stderr, "%s: unknown OneNAND boot command %x\n",
+ fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
__FUNCTION__, value);
}
break;
@@ -684,16 +694,10 @@ static void onenand_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const onenand_readfn[] = {
- onenand_read, /* TODO */
- onenand_read,
- onenand_read,
-};
-
-static CPUWriteMemoryFunc * const onenand_writefn[] = {
- onenand_write, /* TODO */
- onenand_write,
- onenand_write,
+static const MemoryRegionOps onenand_ops = {
+ .read = onenand_read,
+ .write = onenand_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
void *onenand_init(BlockDriverState *bdrv,
@@ -714,8 +718,8 @@ void *onenand_init(BlockDriverState *bdrv,
s->secs = size >> 9;
s->blockwp = qemu_malloc(s->blocks);
s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0;
- s->iomemtype = cpu_register_io_memory(onenand_readfn,
- onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &onenand_ops, s, "onenand",
+ 0x10000 << s->shift);
s->bdrv = bdrv;
if (!s->bdrv) {
s->image = memset(qemu_malloc(size + (size >> 5)),
@@ -723,14 +727,15 @@ void *onenand_init(BlockDriverState *bdrv,
}
s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
- s->ram = qemu_ram_alloc(NULL, "onenand.ram", 0xc000 << s->shift);
- ram = qemu_get_ram_ptr(s->ram);
+ memory_region_init_ram(&s->ram, NULL, "onenand.ram", 0xc000 << s->shift);
+ ram = memory_region_get_ram_ptr(&s->ram);
s->boot[0] = ram + (0x0000 << s->shift);
s->boot[1] = ram + (0x8000 << s->shift);
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift);
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift);
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift);
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift);
+ onenand_mem_setup(s);
onenand_reset(s, 1);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 11/24] pcie_host: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Assuming that mmcfg size cannot change at runtime.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/pcie_host.c | 98 ++++++++++++++-----------------------------------------
hw/pcie_host.h | 12 +++---
2 files changed, 31 insertions(+), 79 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index f9fea3d..28bbe72 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_host.c
@@ -22,6 +22,7 @@
#include "hw.h"
#include "pci.h"
#include "pcie_host.h"
+#include "exec-memory.h"
/*
* PCI express mmcfig address
@@ -52,9 +53,11 @@ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
PCIE_MMCFG_DEVFN(mmcfg_addr));
}
-static void pcie_mmcfg_data_write(PCIBus *s,
- uint32_t mmcfg_addr, uint32_t val, int len)
+static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr,
+ uint64_t val, unsigned len)
{
+ PCIExpressHost *e = opaque;
+ PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
uint32_t limit;
@@ -72,8 +75,12 @@ static void pcie_mmcfg_data_write(PCIBus *s,
pci_host_config_write_common(pci_dev, addr, limit, val, len);
}
-static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
+static uint64_t pcie_mmcfg_data_read(void *opaque,
+ target_phys_addr_t mmcfg_addr,
+ unsigned len)
{
+ PCIExpressHost *e = opaque;
+ PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
uint32_t limit;
@@ -91,72 +98,23 @@ static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
return pci_host_config_read_common(pci_dev, addr, limit, len);
}
-static void pcie_mmcfg_data_writeb(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1);
-}
-
-static void pcie_mmcfg_data_writew(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2);
-}
-
-static void pcie_mmcfg_data_writel(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4);
-}
-
-static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1);
-}
-
-static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2);
-}
-
-static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4);
-}
-
-
-static CPUWriteMemoryFunc * const pcie_mmcfg_write[] =
-{
- pcie_mmcfg_data_writeb,
- pcie_mmcfg_data_writew,
- pcie_mmcfg_data_writel,
-};
-
-static CPUReadMemoryFunc * const pcie_mmcfg_read[] =
-{
- pcie_mmcfg_data_readb,
- pcie_mmcfg_data_readw,
- pcie_mmcfg_data_readl,
+static const MemoryRegionOps pcie_mmcfg_ops = {
+ .read = pcie_mmcfg_data_read,
+ .write = pcie_mmcfg_data_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
-int pcie_host_init(PCIExpressHost *e)
+int pcie_host_init(PCIExpressHost *e, uint32_t size)
{
+ assert(!(size & (size - 1))); /* power of 2 */
+ assert(size >= PCIE_MMCFG_SIZE_MIN);
+ assert(size <= PCIE_MMCFG_SIZE_MAX);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
- e->mmio_index =
- cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e,
- DEVICE_NATIVE_ENDIAN);
- if (e->mmio_index < 0) {
- return -1;
- }
+ e->size = size;
+ memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
return 0;
}
@@ -164,29 +122,23 @@ int pcie_host_init(PCIExpressHost *e)
void pcie_host_mmcfg_unmap(PCIExpressHost *e)
{
if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
- cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &e->mmio);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
}
}
-void pcie_host_mmcfg_map(PCIExpressHost *e,
- target_phys_addr_t addr, uint32_t size)
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
{
- assert(!(size & (size - 1))); /* power of 2 */
- assert(size >= PCIE_MMCFG_SIZE_MIN);
- assert(size <= PCIE_MMCFG_SIZE_MAX);
-
e->base_addr = addr;
- e->size = size;
- cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index);
+ memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
}
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr, uint32_t size)
+ target_phys_addr_t addr)
{
pcie_host_mmcfg_unmap(e);
if (enable) {
- pcie_host_mmcfg_map(e, addr, size);
+ pcie_host_mmcfg_map(e, addr);
}
}
diff --git a/hw/pcie_host.h b/hw/pcie_host.h
index a202661..0074508 100644
--- a/hw/pcie_host.h
+++ b/hw/pcie_host.h
@@ -22,6 +22,7 @@
#define PCIE_HOST_H
#include "pci_host.h"
+#include "memory.h"
struct PCIExpressHost {
PCIHostState pci;
@@ -34,16 +35,15 @@ struct PCIExpressHost {
/* the size of MMCONFIG area. It's host bridge dependent */
target_phys_addr_t size;
- /* result of cpu_register_io_memory() to map MMCONFIG area */
- int mmio_index;
+ /* MMCONFIG mmio area */
+ MemoryRegion mmio;
};
-int pcie_host_init(PCIExpressHost *e);
+int pcie_host_init(PCIExpressHost *e, uint32_t size);
void pcie_host_mmcfg_unmap(PCIExpressHost *e);
-void pcie_host_mmcfg_map(PCIExpressHost *e,
- target_phys_addr_t addr, uint32_t size);
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr, uint32_t size);
+ target_phys_addr_t addr);
#endif /* PCIE_HOST_H */
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 11/24] pcie_host: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Assuming that mmcfg size cannot change at runtime.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/pcie_host.c | 98 ++++++++++++++-----------------------------------------
hw/pcie_host.h | 12 +++---
2 files changed, 31 insertions(+), 79 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index f9fea3d..28bbe72 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_host.c
@@ -22,6 +22,7 @@
#include "hw.h"
#include "pci.h"
#include "pcie_host.h"
+#include "exec-memory.h"
/*
* PCI express mmcfig address
@@ -52,9 +53,11 @@ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
PCIE_MMCFG_DEVFN(mmcfg_addr));
}
-static void pcie_mmcfg_data_write(PCIBus *s,
- uint32_t mmcfg_addr, uint32_t val, int len)
+static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr,
+ uint64_t val, unsigned len)
{
+ PCIExpressHost *e = opaque;
+ PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
uint32_t limit;
@@ -72,8 +75,12 @@ static void pcie_mmcfg_data_write(PCIBus *s,
pci_host_config_write_common(pci_dev, addr, limit, val, len);
}
-static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
+static uint64_t pcie_mmcfg_data_read(void *opaque,
+ target_phys_addr_t mmcfg_addr,
+ unsigned len)
{
+ PCIExpressHost *e = opaque;
+ PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
uint32_t limit;
@@ -91,72 +98,23 @@ static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
return pci_host_config_read_common(pci_dev, addr, limit, len);
}
-static void pcie_mmcfg_data_writeb(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1);
-}
-
-static void pcie_mmcfg_data_writew(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2);
-}
-
-static void pcie_mmcfg_data_writel(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4);
-}
-
-static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1);
-}
-
-static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2);
-}
-
-static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4);
-}
-
-
-static CPUWriteMemoryFunc * const pcie_mmcfg_write[] =
-{
- pcie_mmcfg_data_writeb,
- pcie_mmcfg_data_writew,
- pcie_mmcfg_data_writel,
-};
-
-static CPUReadMemoryFunc * const pcie_mmcfg_read[] =
-{
- pcie_mmcfg_data_readb,
- pcie_mmcfg_data_readw,
- pcie_mmcfg_data_readl,
+static const MemoryRegionOps pcie_mmcfg_ops = {
+ .read = pcie_mmcfg_data_read,
+ .write = pcie_mmcfg_data_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
-int pcie_host_init(PCIExpressHost *e)
+int pcie_host_init(PCIExpressHost *e, uint32_t size)
{
+ assert(!(size & (size - 1))); /* power of 2 */
+ assert(size >= PCIE_MMCFG_SIZE_MIN);
+ assert(size <= PCIE_MMCFG_SIZE_MAX);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
- e->mmio_index =
- cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e,
- DEVICE_NATIVE_ENDIAN);
- if (e->mmio_index < 0) {
- return -1;
- }
+ e->size = size;
+ memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
return 0;
}
@@ -164,29 +122,23 @@ int pcie_host_init(PCIExpressHost *e)
void pcie_host_mmcfg_unmap(PCIExpressHost *e)
{
if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
- cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &e->mmio);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
}
}
-void pcie_host_mmcfg_map(PCIExpressHost *e,
- target_phys_addr_t addr, uint32_t size)
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
{
- assert(!(size & (size - 1))); /* power of 2 */
- assert(size >= PCIE_MMCFG_SIZE_MIN);
- assert(size <= PCIE_MMCFG_SIZE_MAX);
-
e->base_addr = addr;
- e->size = size;
- cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index);
+ memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
}
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr, uint32_t size)
+ target_phys_addr_t addr)
{
pcie_host_mmcfg_unmap(e);
if (enable) {
- pcie_host_mmcfg_map(e, addr, size);
+ pcie_host_mmcfg_map(e, addr);
}
}
diff --git a/hw/pcie_host.h b/hw/pcie_host.h
index a202661..0074508 100644
--- a/hw/pcie_host.h
+++ b/hw/pcie_host.h
@@ -22,6 +22,7 @@
#define PCIE_HOST_H
#include "pci_host.h"
+#include "memory.h"
struct PCIExpressHost {
PCIHostState pci;
@@ -34,16 +35,15 @@ struct PCIExpressHost {
/* the size of MMCONFIG area. It's host bridge dependent */
target_phys_addr_t size;
- /* result of cpu_register_io_memory() to map MMCONFIG area */
- int mmio_index;
+ /* MMCONFIG mmio area */
+ MemoryRegion mmio;
};
-int pcie_host_init(PCIExpressHost *e);
+int pcie_host_init(PCIExpressHost *e, uint32_t size);
void pcie_host_mmcfg_unmap(PCIExpressHost *e);
-void pcie_host_mmcfg_map(PCIExpressHost *e,
- target_phys_addr_t addr, uint32_t size);
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr, uint32_t size);
+ target_phys_addr_t addr);
#endif /* PCIE_HOST_H */
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 12/24] ppc405_uc: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/ppc405_uc.c | 116 ++++++++++++++++++++++++-------------------------------
1 files changed, 51 insertions(+), 65 deletions(-)
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 06a053b..9caece0 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -28,6 +28,7 @@
#include "qemu-timer.h"
#include "sysemu.h"
#include "qemu-log.h"
+#include "exec-memory.h"
#define DEBUG_OPBA
#define DEBUG_SDRAM
@@ -259,6 +260,7 @@ static void ppc4xx_pob_init(CPUState *env)
/* OPB arbitrer */
typedef struct ppc4xx_opba_t ppc4xx_opba_t;
struct ppc4xx_opba_t {
+ MemoryRegion io;
uint8_t cr;
uint8_t pr;
};
@@ -357,16 +359,12 @@ static void opba_writel (void *opaque,
opba_writeb(opaque, addr + 1, value >> 16);
}
-static CPUReadMemoryFunc * const opba_read[] = {
- &opba_readb,
- &opba_readw,
- &opba_readl,
-};
-
-static CPUWriteMemoryFunc * const opba_write[] = {
- &opba_writeb,
- &opba_writew,
- &opba_writel,
+static const MemoryRegionOps opba_ops = {
+ .old_mmio = {
+ .read = { opba_readb, opba_readw, opba_readl, },
+ .write = { opba_writeb, opba_writew, opba_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_opba_reset (void *opaque)
@@ -381,15 +379,13 @@ static void ppc4xx_opba_reset (void *opaque)
static void ppc4xx_opba_init(target_phys_addr_t base)
{
ppc4xx_opba_t *opba;
- int io;
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
#ifdef DEBUG_OPBA
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(opba_read, opba_write, opba,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x002, io);
+ memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);
+ memory_region_add_subregion(get_system_memory(), base, &opba->io);
qemu_register_reset(ppc4xx_opba_reset, opba);
}
@@ -722,6 +718,7 @@ static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
/* GPIO */
typedef struct ppc405_gpio_t ppc405_gpio_t;
struct ppc405_gpio_t {
+ MemoryRegion io;
uint32_t or;
uint32_t tcr;
uint32_t osrh;
@@ -789,16 +786,12 @@ static void ppc405_gpio_writel (void *opaque,
#endif
}
-static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
- &ppc405_gpio_readb,
- &ppc405_gpio_readw,
- &ppc405_gpio_readl,
-};
-
-static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
- &ppc405_gpio_writeb,
- &ppc405_gpio_writew,
- &ppc405_gpio_writel,
+static const MemoryRegionOps ppc405_gpio_ops = {
+ .old_mmio = {
+ .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
+ .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc405_gpio_reset (void *opaque)
@@ -808,15 +801,13 @@ static void ppc405_gpio_reset (void *opaque)
static void ppc405_gpio_init(target_phys_addr_t base)
{
ppc405_gpio_t *gpio;
- int io;
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
#ifdef DEBUG_GPIO
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x038, io);
+ memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);
+ memory_region_add_subregion(get_system_memory(), base, &gpio->io);
qemu_register_reset(&ppc405_gpio_reset, gpio);
}
@@ -831,7 +822,9 @@ enum {
typedef struct ppc405_ocm_t ppc405_ocm_t;
struct ppc405_ocm_t {
- target_ulong offset;
+ MemoryRegion ram;
+ MemoryRegion isarc_ram;
+ MemoryRegion dsarc_ram;
uint32_t isarc;
uint32_t isacntl;
uint32_t dsarc;
@@ -854,16 +847,15 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
if (ocm->isacntl & 0x80000000) {
/* Unmap previously assigned memory region */
printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
- cpu_register_physical_memory(ocm->isarc, 0x04000000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
}
if (isacntl & 0x80000000) {
/* Map new instruction memory region */
#ifdef DEBUG_OCM
printf("OCM map ISA %08" PRIx32 "\n", isarc);
#endif
- cpu_register_physical_memory(isarc, 0x04000000,
- ocm->offset | IO_MEM_RAM);
+ memory_region_add_subregion(get_system_memory(), isarc,
+ &ocm->isarc_ram);
}
}
if (ocm->dsarc != dsarc ||
@@ -875,8 +867,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
#ifdef DEBUG_OCM
printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
#endif
- cpu_register_physical_memory(ocm->dsarc, 0x04000000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &ocm->dsarc_ram);
}
}
if (dsacntl & 0x80000000) {
@@ -886,8 +878,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
#ifdef DEBUG_OCM
printf("OCM map DSA %08" PRIx32 "\n", dsarc);
#endif
- cpu_register_physical_memory(dsarc, 0x04000000,
- ocm->offset | IO_MEM_RAM);
+ memory_region_add_subregion(get_system_memory(), dsarc,
+ &ocm->dsarc_ram);
}
}
}
@@ -973,7 +965,10 @@ static void ppc405_ocm_init(CPUState *env)
ppc405_ocm_t *ocm;
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
- ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096);
+ /* XXX: Size is 4096 or 0x04000000 */
+ memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096);
+ memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
+ 0, 4096);
qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
@@ -990,6 +985,7 @@ static void ppc405_ocm_init(CPUState *env)
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
struct ppc4xx_i2c_t {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t mdata;
uint8_t lmadr;
uint8_t hmadr;
@@ -1186,16 +1182,12 @@ static void ppc4xx_i2c_writel (void *opaque,
ppc4xx_i2c_writeb(opaque, addr + 3, value);
}
-static CPUReadMemoryFunc * const i2c_read[] = {
- &ppc4xx_i2c_readb,
- &ppc4xx_i2c_readw,
- &ppc4xx_i2c_readl,
-};
-
-static CPUWriteMemoryFunc * const i2c_write[] = {
- &ppc4xx_i2c_writeb,
- &ppc4xx_i2c_writew,
- &ppc4xx_i2c_writel,
+static const MemoryRegionOps i2c_ops = {
+ .old_mmio = {
+ .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
+ .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_i2c_reset (void *opaque)
@@ -1217,16 +1209,14 @@ static void ppc4xx_i2c_reset (void *opaque)
static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
{
ppc4xx_i2c_t *i2c;
- int io;
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
i2c->irq = irq;
#ifdef DEBUG_I2C
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x011, io);
+ memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011);
+ memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
@@ -1234,6 +1224,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
/* General purpose timers */
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
struct ppc4xx_gpt_t {
+ MemoryRegion iomem;
int64_t tb_offset;
uint32_t tb_freq;
struct QEMUTimer *timer;
@@ -1454,16 +1445,12 @@ static void ppc4xx_gpt_writel (void *opaque,
}
}
-static CPUReadMemoryFunc * const gpt_read[] = {
- &ppc4xx_gpt_readb,
- &ppc4xx_gpt_readw,
- &ppc4xx_gpt_readl,
-};
-
-static CPUWriteMemoryFunc * const gpt_write[] = {
- &ppc4xx_gpt_writeb,
- &ppc4xx_gpt_writew,
- &ppc4xx_gpt_writel,
+static const MemoryRegionOps gpt_ops = {
+ .old_mmio = {
+ .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
+ .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_gpt_cb (void *opaque)
@@ -1498,7 +1485,6 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
{
ppc4xx_gpt_t *gpt;
int i;
- int io;
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
for (i = 0; i < 5; i++) {
@@ -1508,8 +1494,8 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
#ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x0d4, io);
+ memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4);
+ memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 12/24] ppc405_uc: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/ppc405_uc.c | 116 ++++++++++++++++++++++++-------------------------------
1 files changed, 51 insertions(+), 65 deletions(-)
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 06a053b..9caece0 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -28,6 +28,7 @@
#include "qemu-timer.h"
#include "sysemu.h"
#include "qemu-log.h"
+#include "exec-memory.h"
#define DEBUG_OPBA
#define DEBUG_SDRAM
@@ -259,6 +260,7 @@ static void ppc4xx_pob_init(CPUState *env)
/* OPB arbitrer */
typedef struct ppc4xx_opba_t ppc4xx_opba_t;
struct ppc4xx_opba_t {
+ MemoryRegion io;
uint8_t cr;
uint8_t pr;
};
@@ -357,16 +359,12 @@ static void opba_writel (void *opaque,
opba_writeb(opaque, addr + 1, value >> 16);
}
-static CPUReadMemoryFunc * const opba_read[] = {
- &opba_readb,
- &opba_readw,
- &opba_readl,
-};
-
-static CPUWriteMemoryFunc * const opba_write[] = {
- &opba_writeb,
- &opba_writew,
- &opba_writel,
+static const MemoryRegionOps opba_ops = {
+ .old_mmio = {
+ .read = { opba_readb, opba_readw, opba_readl, },
+ .write = { opba_writeb, opba_writew, opba_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_opba_reset (void *opaque)
@@ -381,15 +379,13 @@ static void ppc4xx_opba_reset (void *opaque)
static void ppc4xx_opba_init(target_phys_addr_t base)
{
ppc4xx_opba_t *opba;
- int io;
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
#ifdef DEBUG_OPBA
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(opba_read, opba_write, opba,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x002, io);
+ memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);
+ memory_region_add_subregion(get_system_memory(), base, &opba->io);
qemu_register_reset(ppc4xx_opba_reset, opba);
}
@@ -722,6 +718,7 @@ static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
/* GPIO */
typedef struct ppc405_gpio_t ppc405_gpio_t;
struct ppc405_gpio_t {
+ MemoryRegion io;
uint32_t or;
uint32_t tcr;
uint32_t osrh;
@@ -789,16 +786,12 @@ static void ppc405_gpio_writel (void *opaque,
#endif
}
-static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
- &ppc405_gpio_readb,
- &ppc405_gpio_readw,
- &ppc405_gpio_readl,
-};
-
-static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
- &ppc405_gpio_writeb,
- &ppc405_gpio_writew,
- &ppc405_gpio_writel,
+static const MemoryRegionOps ppc405_gpio_ops = {
+ .old_mmio = {
+ .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
+ .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc405_gpio_reset (void *opaque)
@@ -808,15 +801,13 @@ static void ppc405_gpio_reset (void *opaque)
static void ppc405_gpio_init(target_phys_addr_t base)
{
ppc405_gpio_t *gpio;
- int io;
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
#ifdef DEBUG_GPIO
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x038, io);
+ memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);
+ memory_region_add_subregion(get_system_memory(), base, &gpio->io);
qemu_register_reset(&ppc405_gpio_reset, gpio);
}
@@ -831,7 +822,9 @@ enum {
typedef struct ppc405_ocm_t ppc405_ocm_t;
struct ppc405_ocm_t {
- target_ulong offset;
+ MemoryRegion ram;
+ MemoryRegion isarc_ram;
+ MemoryRegion dsarc_ram;
uint32_t isarc;
uint32_t isacntl;
uint32_t dsarc;
@@ -854,16 +847,15 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
if (ocm->isacntl & 0x80000000) {
/* Unmap previously assigned memory region */
printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
- cpu_register_physical_memory(ocm->isarc, 0x04000000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
}
if (isacntl & 0x80000000) {
/* Map new instruction memory region */
#ifdef DEBUG_OCM
printf("OCM map ISA %08" PRIx32 "\n", isarc);
#endif
- cpu_register_physical_memory(isarc, 0x04000000,
- ocm->offset | IO_MEM_RAM);
+ memory_region_add_subregion(get_system_memory(), isarc,
+ &ocm->isarc_ram);
}
}
if (ocm->dsarc != dsarc ||
@@ -875,8 +867,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
#ifdef DEBUG_OCM
printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
#endif
- cpu_register_physical_memory(ocm->dsarc, 0x04000000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &ocm->dsarc_ram);
}
}
if (dsacntl & 0x80000000) {
@@ -886,8 +878,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
#ifdef DEBUG_OCM
printf("OCM map DSA %08" PRIx32 "\n", dsarc);
#endif
- cpu_register_physical_memory(dsarc, 0x04000000,
- ocm->offset | IO_MEM_RAM);
+ memory_region_add_subregion(get_system_memory(), dsarc,
+ &ocm->dsarc_ram);
}
}
}
@@ -973,7 +965,10 @@ static void ppc405_ocm_init(CPUState *env)
ppc405_ocm_t *ocm;
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
- ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096);
+ /* XXX: Size is 4096 or 0x04000000 */
+ memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096);
+ memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
+ 0, 4096);
qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
@@ -990,6 +985,7 @@ static void ppc405_ocm_init(CPUState *env)
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
struct ppc4xx_i2c_t {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t mdata;
uint8_t lmadr;
uint8_t hmadr;
@@ -1186,16 +1182,12 @@ static void ppc4xx_i2c_writel (void *opaque,
ppc4xx_i2c_writeb(opaque, addr + 3, value);
}
-static CPUReadMemoryFunc * const i2c_read[] = {
- &ppc4xx_i2c_readb,
- &ppc4xx_i2c_readw,
- &ppc4xx_i2c_readl,
-};
-
-static CPUWriteMemoryFunc * const i2c_write[] = {
- &ppc4xx_i2c_writeb,
- &ppc4xx_i2c_writew,
- &ppc4xx_i2c_writel,
+static const MemoryRegionOps i2c_ops = {
+ .old_mmio = {
+ .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
+ .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_i2c_reset (void *opaque)
@@ -1217,16 +1209,14 @@ static void ppc4xx_i2c_reset (void *opaque)
static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
{
ppc4xx_i2c_t *i2c;
- int io;
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
i2c->irq = irq;
#ifdef DEBUG_I2C
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x011, io);
+ memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011);
+ memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
@@ -1234,6 +1224,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
/* General purpose timers */
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
struct ppc4xx_gpt_t {
+ MemoryRegion iomem;
int64_t tb_offset;
uint32_t tb_freq;
struct QEMUTimer *timer;
@@ -1454,16 +1445,12 @@ static void ppc4xx_gpt_writel (void *opaque,
}
}
-static CPUReadMemoryFunc * const gpt_read[] = {
- &ppc4xx_gpt_readb,
- &ppc4xx_gpt_readw,
- &ppc4xx_gpt_readl,
-};
-
-static CPUWriteMemoryFunc * const gpt_write[] = {
- &ppc4xx_gpt_writeb,
- &ppc4xx_gpt_writew,
- &ppc4xx_gpt_writel,
+static const MemoryRegionOps gpt_ops = {
+ .old_mmio = {
+ .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
+ .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_gpt_cb (void *opaque)
@@ -1498,7 +1485,6 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
{
ppc4xx_gpt_t *gpt;
int i;
- int io;
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
for (i = 0; i < 5; i++) {
@@ -1508,8 +1494,8 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
#ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x0d4, io);
+ memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4);
+ memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 13/24] ppc4xx_sdram: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Clumsy due to the lack of clipping support, needed for
changing exposed ram size.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/ppc405.h | 9 ++++++---
hw/ppc405_boards.c | 18 +++++++++++++-----
hw/ppc405_uc.c | 12 ++++++++----
hw/ppc440.c | 7 +++++--
hw/ppc4xx.h | 2 ++
hw/ppc4xx_devs.c | 50 +++++++++++++++++++++++++++++++++++---------------
6 files changed, 69 insertions(+), 29 deletions(-)
diff --git a/hw/ppc405.h b/hw/ppc405.h
index e042a05..f0e81a6 100644
--- a/hw/ppc405.h
+++ b/hw/ppc405.h
@@ -59,16 +59,19 @@ struct ppc4xx_bd_info_t {
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
-CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
+CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
+ target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init);
-CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
+CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
+ target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init);
/* IBM STBxxx microcontrollers */
-CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
+CPUState *ppc_stb025_init (MemoryRegion ram_memories[2],
+ target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
ram_addr_t *offsetp);
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index ad27181..c9fe9a2 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -182,6 +182,7 @@ static void ref405ep_init (ram_addr_t ram_size,
CPUPPCState *env;
qemu_irq *pic;
ram_addr_t sram_offset, bios_offset, bdloc;
+ MemoryRegion *ram_memories = qemu_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
target_ulong sram_size;
long bios_size;
@@ -194,15 +195,17 @@ static void ref405ep_init (ram_addr_t ram_size,
DriveInfo *dinfo;
/* XXX: fix this */
- ram_bases[0] = qemu_ram_alloc(NULL, "ef405ep.ram", 0x08000000);
+ memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000);
+ ram_bases[0] = 0;
ram_sizes[0] = 0x08000000;
+ memory_region_init(&ram_memories[1], "ef405ep.ram1", 0);
ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000;
ram_size = 128 * 1024 * 1024;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
+ env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */
sram_size = 512 * 1024;
@@ -505,6 +508,7 @@ static void taihu_405ep_init(ram_addr_t ram_size,
char *filename;
qemu_irq *pic;
ram_addr_t bios_offset;
+ MemoryRegion *ram_memories = qemu_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
long bios_size;
target_ulong kernel_base, initrd_base;
@@ -514,15 +518,19 @@ static void taihu_405ep_init(ram_addr_t ram_size,
DriveInfo *dinfo;
/* RAM is soldered to the board so the size cannot be changed */
- ram_bases[0] = qemu_ram_alloc(NULL, "taihu_405ep.ram-0", 0x04000000);
+ memory_region_init_ram(&ram_memories[0], NULL,
+ "taihu_405ep.ram-0", 0x04000000);
+ ram_bases[0] = 0;
ram_sizes[0] = 0x04000000;
- ram_bases[1] = qemu_ram_alloc(NULL, "taihu_405ep.ram-1", 0x04000000);
+ memory_region_init_ram(&ram_memories[1], NULL,
+ "taihu_405ep.ram-1", 0x04000000);
+ ram_bases[1] = 0x04000000;
ram_sizes[1] = 0x04000000;
ram_size = 0x08000000;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
+ ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
#ifdef DEBUG_BOARD_INIT
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 9caece0..efdf37d 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -2107,7 +2107,8 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
qemu_register_reset(ppc405cr_cpc_reset, cpc);
}
-CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
+CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
+ target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init)
@@ -2136,7 +2137,8 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
*picp = pic;
/* SDRAM controller */
- ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* External bus controller */
ppc405_ebc_init(env);
/* DMA controller */
@@ -2451,7 +2453,8 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
#endif
}
-CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
+CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
+ target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init)
@@ -2485,7 +2488,8 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
*picp = pic;
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* External bus controller */
ppc405_ebc_init(env);
/* DMA controller */
diff --git a/hw/ppc440.c b/hw/ppc440.c
index 90abc91..f34d68d 100644
--- a/hw/ppc440.c
+++ b/hw/ppc440.c
@@ -38,6 +38,8 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
const unsigned int pci_irq_nrs[4], int do_init,
const char *cpu_model)
{
+ MemoryRegion *ram_memories
+ = qemu_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
CPUState *env;
@@ -66,11 +68,12 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
memset(ram_bases, 0, sizeof(ram_bases));
memset(ram_sizes, 0, sizeof(ram_sizes));
*ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS,
+ ram_memories,
ram_bases, ram_sizes,
ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_bases,
- ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* PCI */
pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);
diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h
index bc4ee01..f969e44 100644
--- a/hw/ppc4xx.h
+++ b/hw/ppc4xx.h
@@ -42,11 +42,13 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr);
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ MemoryRegion ram_memories[],
target_phys_addr_t ram_bases[],
target_phys_addr_t ram_sizes[],
const unsigned int sdram_bank_sizes[]);
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
+ MemoryRegion ram_memories[],
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
int do_init);
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 68bdfaa..2947b3f 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -25,6 +25,7 @@
#include "ppc.h"
#include "ppc4xx.h"
#include "qemu-log.h"
+#include "exec-memory.h"
//#define DEBUG_MMIO
//#define DEBUG_UNASSIGNED
@@ -313,6 +314,8 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
uint32_t addr;
int nbanks;
+ MemoryRegion containers[4]; /* used for clipping */
+ MemoryRegion *ram_memories;
target_phys_addr_t ram_bases[4];
target_phys_addr_t ram_sizes[4];
uint32_t besr0;
@@ -395,16 +398,22 @@ static target_ulong sdram_size (uint32_t bcr)
return size;
}
-static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
+static void sdram_set_bcr(ppc4xx_sdram_t *sdram,
+ uint32_t *bcrp, uint32_t bcr, int enabled)
{
+ unsigned n = bcrp - sdram->bcr;
+
if (*bcrp & 0x00000001) {
/* Unmap RAM */
#ifdef DEBUG_SDRAM
printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(*bcrp), sdram_size(*bcrp));
#endif
- cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->containers[n]);
+ memory_region_del_subregion(&sdram->containers[n],
+ &sdram->ram_memories[n]);
+ memory_region_destroy(&sdram->containers[n]);
}
*bcrp = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
@@ -412,8 +421,13 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(bcr), sdram_size(bcr));
#endif
- cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
- sdram_base(bcr) | IO_MEM_RAM);
+ memory_region_init(&sdram->containers[n], "sdram-containers",
+ sdram_size(bcr));
+ memory_region_add_subregion(&sdram->containers[n], 0,
+ &sdram->ram_memories[n]);
+ memory_region_add_subregion(get_system_memory(),
+ sdram_base(bcr),
+ &sdram->containers[n]);
}
}
@@ -423,11 +437,12 @@ static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->ram_sizes[i] != 0) {
- sdram_set_bcr(&sdram->bcr[i],
+ sdram_set_bcr(sdram,
+ &sdram->bcr[i],
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
1);
} else {
- sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
+ sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0);
}
}
}
@@ -441,9 +456,8 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
#endif
- cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
- sdram_size(sdram->bcr[i]),
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->ram_memories[i]);
}
}
@@ -568,16 +582,16 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
sdram->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
- sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
- sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
- sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
sdram->tr = val & 0x018FC01F;
@@ -621,6 +635,7 @@ static void sdram_reset (void *opaque)
}
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
+ MemoryRegion *ram_memories,
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
int do_init)
@@ -630,6 +645,7 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
sdram->irq = irq;
sdram->nbanks = nbanks;
+ sdram->ram_memories = ram_memories;
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_bases, ram_bases,
nbanks * sizeof(target_phys_addr_t));
@@ -653,11 +669,13 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
* must be one of a small set of sizes. The number of banks and the supported
* sizes varies by SoC. */
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ MemoryRegion ram_memories[],
target_phys_addr_t ram_bases[],
target_phys_addr_t ram_sizes[],
const unsigned int sdram_bank_sizes[])
{
ram_addr_t size_left = ram_size;
+ ram_addr_t base = 0;
int i;
int j;
@@ -668,8 +686,10 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
if (bank_size <= size_left) {
char name[32];
snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
- ram_bases[i] = qemu_ram_alloc(NULL, name, bank_size);
+ memory_region_init_ram(&ram_memories[i], NULL, name, bank_size);
+ ram_bases[i] = base;
ram_sizes[i] = bank_size;
+ base += ram_size;
size_left -= bank_size;
break;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 13/24] ppc4xx_sdram: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Clumsy due to the lack of clipping support, needed for
changing exposed ram size.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/ppc405.h | 9 ++++++---
hw/ppc405_boards.c | 18 +++++++++++++-----
hw/ppc405_uc.c | 12 ++++++++----
hw/ppc440.c | 7 +++++--
hw/ppc4xx.h | 2 ++
hw/ppc4xx_devs.c | 50 +++++++++++++++++++++++++++++++++++---------------
6 files changed, 69 insertions(+), 29 deletions(-)
diff --git a/hw/ppc405.h b/hw/ppc405.h
index e042a05..f0e81a6 100644
--- a/hw/ppc405.h
+++ b/hw/ppc405.h
@@ -59,16 +59,19 @@ struct ppc4xx_bd_info_t {
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
-CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
+CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
+ target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init);
-CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
+CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
+ target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init);
/* IBM STBxxx microcontrollers */
-CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
+CPUState *ppc_stb025_init (MemoryRegion ram_memories[2],
+ target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
ram_addr_t *offsetp);
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index ad27181..c9fe9a2 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -182,6 +182,7 @@ static void ref405ep_init (ram_addr_t ram_size,
CPUPPCState *env;
qemu_irq *pic;
ram_addr_t sram_offset, bios_offset, bdloc;
+ MemoryRegion *ram_memories = qemu_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
target_ulong sram_size;
long bios_size;
@@ -194,15 +195,17 @@ static void ref405ep_init (ram_addr_t ram_size,
DriveInfo *dinfo;
/* XXX: fix this */
- ram_bases[0] = qemu_ram_alloc(NULL, "ef405ep.ram", 0x08000000);
+ memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000);
+ ram_bases[0] = 0;
ram_sizes[0] = 0x08000000;
+ memory_region_init(&ram_memories[1], "ef405ep.ram1", 0);
ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000;
ram_size = 128 * 1024 * 1024;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
+ env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */
sram_size = 512 * 1024;
@@ -505,6 +508,7 @@ static void taihu_405ep_init(ram_addr_t ram_size,
char *filename;
qemu_irq *pic;
ram_addr_t bios_offset;
+ MemoryRegion *ram_memories = qemu_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
long bios_size;
target_ulong kernel_base, initrd_base;
@@ -514,15 +518,19 @@ static void taihu_405ep_init(ram_addr_t ram_size,
DriveInfo *dinfo;
/* RAM is soldered to the board so the size cannot be changed */
- ram_bases[0] = qemu_ram_alloc(NULL, "taihu_405ep.ram-0", 0x04000000);
+ memory_region_init_ram(&ram_memories[0], NULL,
+ "taihu_405ep.ram-0", 0x04000000);
+ ram_bases[0] = 0;
ram_sizes[0] = 0x04000000;
- ram_bases[1] = qemu_ram_alloc(NULL, "taihu_405ep.ram-1", 0x04000000);
+ memory_region_init_ram(&ram_memories[1], NULL,
+ "taihu_405ep.ram-1", 0x04000000);
+ ram_bases[1] = 0x04000000;
ram_sizes[1] = 0x04000000;
ram_size = 0x08000000;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
+ ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
#ifdef DEBUG_BOARD_INIT
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 9caece0..efdf37d 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -2107,7 +2107,8 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
qemu_register_reset(ppc405cr_cpc_reset, cpc);
}
-CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
+CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
+ target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init)
@@ -2136,7 +2137,8 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
*picp = pic;
/* SDRAM controller */
- ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* External bus controller */
ppc405_ebc_init(env);
/* DMA controller */
@@ -2451,7 +2453,8 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
#endif
}
-CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
+CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
+ target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init)
@@ -2485,7 +2488,8 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
*picp = pic;
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* External bus controller */
ppc405_ebc_init(env);
/* DMA controller */
diff --git a/hw/ppc440.c b/hw/ppc440.c
index 90abc91..f34d68d 100644
--- a/hw/ppc440.c
+++ b/hw/ppc440.c
@@ -38,6 +38,8 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
const unsigned int pci_irq_nrs[4], int do_init,
const char *cpu_model)
{
+ MemoryRegion *ram_memories
+ = qemu_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
CPUState *env;
@@ -66,11 +68,12 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
memset(ram_bases, 0, sizeof(ram_bases));
memset(ram_sizes, 0, sizeof(ram_sizes));
*ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS,
+ ram_memories,
ram_bases, ram_sizes,
ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_bases,
- ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* PCI */
pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);
diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h
index bc4ee01..f969e44 100644
--- a/hw/ppc4xx.h
+++ b/hw/ppc4xx.h
@@ -42,11 +42,13 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr);
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ MemoryRegion ram_memories[],
target_phys_addr_t ram_bases[],
target_phys_addr_t ram_sizes[],
const unsigned int sdram_bank_sizes[]);
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
+ MemoryRegion ram_memories[],
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
int do_init);
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 68bdfaa..2947b3f 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -25,6 +25,7 @@
#include "ppc.h"
#include "ppc4xx.h"
#include "qemu-log.h"
+#include "exec-memory.h"
//#define DEBUG_MMIO
//#define DEBUG_UNASSIGNED
@@ -313,6 +314,8 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
uint32_t addr;
int nbanks;
+ MemoryRegion containers[4]; /* used for clipping */
+ MemoryRegion *ram_memories;
target_phys_addr_t ram_bases[4];
target_phys_addr_t ram_sizes[4];
uint32_t besr0;
@@ -395,16 +398,22 @@ static target_ulong sdram_size (uint32_t bcr)
return size;
}
-static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
+static void sdram_set_bcr(ppc4xx_sdram_t *sdram,
+ uint32_t *bcrp, uint32_t bcr, int enabled)
{
+ unsigned n = bcrp - sdram->bcr;
+
if (*bcrp & 0x00000001) {
/* Unmap RAM */
#ifdef DEBUG_SDRAM
printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(*bcrp), sdram_size(*bcrp));
#endif
- cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->containers[n]);
+ memory_region_del_subregion(&sdram->containers[n],
+ &sdram->ram_memories[n]);
+ memory_region_destroy(&sdram->containers[n]);
}
*bcrp = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
@@ -412,8 +421,13 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(bcr), sdram_size(bcr));
#endif
- cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
- sdram_base(bcr) | IO_MEM_RAM);
+ memory_region_init(&sdram->containers[n], "sdram-containers",
+ sdram_size(bcr));
+ memory_region_add_subregion(&sdram->containers[n], 0,
+ &sdram->ram_memories[n]);
+ memory_region_add_subregion(get_system_memory(),
+ sdram_base(bcr),
+ &sdram->containers[n]);
}
}
@@ -423,11 +437,12 @@ static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->ram_sizes[i] != 0) {
- sdram_set_bcr(&sdram->bcr[i],
+ sdram_set_bcr(sdram,
+ &sdram->bcr[i],
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
1);
} else {
- sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
+ sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0);
}
}
}
@@ -441,9 +456,8 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
#endif
- cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
- sdram_size(sdram->bcr[i]),
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->ram_memories[i]);
}
}
@@ -568,16 +582,16 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
sdram->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
- sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
- sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
- sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
sdram->tr = val & 0x018FC01F;
@@ -621,6 +635,7 @@ static void sdram_reset (void *opaque)
}
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
+ MemoryRegion *ram_memories,
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
int do_init)
@@ -630,6 +645,7 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
sdram->irq = irq;
sdram->nbanks = nbanks;
+ sdram->ram_memories = ram_memories;
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_bases, ram_bases,
nbanks * sizeof(target_phys_addr_t));
@@ -653,11 +669,13 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
* must be one of a small set of sizes. The number of banks and the supported
* sizes varies by SoC. */
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ MemoryRegion ram_memories[],
target_phys_addr_t ram_bases[],
target_phys_addr_t ram_sizes[],
const unsigned int sdram_bank_sizes[])
{
ram_addr_t size_left = ram_size;
+ ram_addr_t base = 0;
int i;
int j;
@@ -668,8 +686,10 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
if (bank_size <= size_left) {
char name[32];
snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
- ram_bases[i] = qemu_ram_alloc(NULL, name, bank_size);
+ memory_region_init_ram(&ram_memories[i], NULL, name, bank_size);
+ ram_bases[i] = base;
ram_sizes[i] = bank_size;
+ base += ram_size;
size_left -= bank_size;
break;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 14/24] stellaris_enet: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:06 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/stellaris_enet.c | 29 ++++++++++++-----------------
1 files changed, 12 insertions(+), 17 deletions(-)
diff --git a/hw/stellaris_enet.c b/hw/stellaris_enet.c
index 1291931..9f1f37a 100644
--- a/hw/stellaris_enet.c
+++ b/hw/stellaris_enet.c
@@ -69,7 +69,7 @@ typedef struct {
NICState *nic;
NICConf conf;
qemu_irq irq;
- int mmio_index;
+ MemoryRegion mmio;
} stellaris_enet_state;
static void stellaris_enet_update(stellaris_enet_state *s)
@@ -130,7 +130,8 @@ static int stellaris_enet_can_receive(VLANClientState *nc)
return (s->np < 31);
}
-static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
+static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
uint32_t val;
@@ -198,7 +199,7 @@ static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
}
static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
@@ -303,17 +304,12 @@ static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const stellaris_enet_readfn[] = {
- stellaris_enet_read,
- stellaris_enet_read,
- stellaris_enet_read
+static const MemoryRegionOps stellaris_enet_ops = {
+ .read = stellaris_enet_read,
+ .write = stellaris_enet_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const stellaris_enet_writefn[] = {
- stellaris_enet_write,
- stellaris_enet_write,
- stellaris_enet_write
-};
static void stellaris_enet_reset(stellaris_enet_state *s)
{
s->mdv = 0x80;
@@ -391,7 +387,7 @@ static void stellaris_enet_cleanup(VLANClientState *nc)
unregister_savevm(&s->busdev.qdev, "stellaris_enet", s);
- cpu_unregister_io_memory(s->mmio_index);
+ memory_region_destroy(&s->mmio);
qemu_free(s);
}
@@ -408,10 +404,9 @@ static int stellaris_enet_init(SysBusDevice *dev)
{
stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
- s->mmio_index = cpu_register_io_memory(stellaris_enet_readfn,
- stellaris_enet_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, s->mmio_index);
+ memory_region_init_io(&s->mmio, &stellaris_enet_ops, s, "stellaris_enet",
+ 0x1000);
+ sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 14/24] stellaris_enet: convert to memory API
@ 2011-08-08 17:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:06 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/stellaris_enet.c | 29 ++++++++++++-----------------
1 files changed, 12 insertions(+), 17 deletions(-)
diff --git a/hw/stellaris_enet.c b/hw/stellaris_enet.c
index 1291931..9f1f37a 100644
--- a/hw/stellaris_enet.c
+++ b/hw/stellaris_enet.c
@@ -69,7 +69,7 @@ typedef struct {
NICState *nic;
NICConf conf;
qemu_irq irq;
- int mmio_index;
+ MemoryRegion mmio;
} stellaris_enet_state;
static void stellaris_enet_update(stellaris_enet_state *s)
@@ -130,7 +130,8 @@ static int stellaris_enet_can_receive(VLANClientState *nc)
return (s->np < 31);
}
-static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
+static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
uint32_t val;
@@ -198,7 +199,7 @@ static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
}
static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
@@ -303,17 +304,12 @@ static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const stellaris_enet_readfn[] = {
- stellaris_enet_read,
- stellaris_enet_read,
- stellaris_enet_read
+static const MemoryRegionOps stellaris_enet_ops = {
+ .read = stellaris_enet_read,
+ .write = stellaris_enet_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const stellaris_enet_writefn[] = {
- stellaris_enet_write,
- stellaris_enet_write,
- stellaris_enet_write
-};
static void stellaris_enet_reset(stellaris_enet_state *s)
{
s->mdv = 0x80;
@@ -391,7 +387,7 @@ static void stellaris_enet_cleanup(VLANClientState *nc)
unregister_savevm(&s->busdev.qdev, "stellaris_enet", s);
- cpu_unregister_io_memory(s->mmio_index);
+ memory_region_destroy(&s->mmio);
qemu_free(s);
}
@@ -408,10 +404,9 @@ static int stellaris_enet_init(SysBusDevice *dev)
{
stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
- s->mmio_index = cpu_register_io_memory(stellaris_enet_readfn,
- stellaris_enet_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, s->mmio_index);
+ memory_region_init_io(&s->mmio, &stellaris_enet_ops, s, "stellaris_enet",
+ 0x1000);
+ sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 15/24] sysbus: add a variant of sysbus_init_mmio_cb with an unmap callback
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:07 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
sysbus_init_mmio_cb() uses the destructive IO_MEM_UNASSIGNED to remove a
region. Provide an alternative that calls an unmap callback, so the removal
may be done non-destructively.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/sysbus.c | 15 +++++++++++++++
hw/sysbus.h | 3 +++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/sysbus.c b/hw/sysbus.c
index ea442ac..64749e0 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -53,6 +53,8 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr)
if (dev->mmio[n].memory) {
memory_region_del_subregion(get_system_memory(),
dev->mmio[n].memory);
+ } else if (dev->mmio[n].unmap) {
+ dev->mmio[n].unmap(dev, dev->mmio[n].addr);
} else {
cpu_register_physical_memory(dev->mmio[n].addr, dev->mmio[n].size,
IO_MEM_UNASSIGNED);
@@ -117,6 +119,19 @@ void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
dev->mmio[n].cb = cb;
}
+void sysbus_init_mmio_cb2(SysBusDevice *dev,
+ mmio_mapfunc cb, mmio_mapfunc unmap)
+{
+ int n;
+
+ assert(dev->num_mmio < QDEV_MAX_MMIO);
+ n = dev->num_mmio++;
+ dev->mmio[n].addr = -1;
+ dev->mmio[n].size = 0;
+ dev->mmio[n].cb = cb;
+ dev->mmio[n].unmap = unmap;
+}
+
void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory)
{
int n;
diff --git a/hw/sysbus.h b/hw/sysbus.h
index 5f62e2d..16fd969 100644
--- a/hw/sysbus.h
+++ b/hw/sysbus.h
@@ -23,6 +23,7 @@ struct SysBusDevice {
target_phys_addr_t addr;
target_phys_addr_t size;
mmio_mapfunc cb;
+ mmio_mapfunc unmap;
ram_addr_t iofunc;
MemoryRegion *memory;
} mmio[QDEV_MAX_MMIO];
@@ -48,6 +49,8 @@ void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size,
ram_addr_t iofunc);
void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
mmio_mapfunc cb);
+void sysbus_init_mmio_cb2(SysBusDevice *dev,
+ mmio_mapfunc cb, mmio_mapfunc unmap);
void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory);
void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p);
void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 15/24] sysbus: add a variant of sysbus_init_mmio_cb with an unmap callback
@ 2011-08-08 17:07 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
sysbus_init_mmio_cb() uses the destructive IO_MEM_UNASSIGNED to remove a
region. Provide an alternative that calls an unmap callback, so the removal
may be done non-destructively.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/sysbus.c | 15 +++++++++++++++
hw/sysbus.h | 3 +++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/sysbus.c b/hw/sysbus.c
index ea442ac..64749e0 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -53,6 +53,8 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr)
if (dev->mmio[n].memory) {
memory_region_del_subregion(get_system_memory(),
dev->mmio[n].memory);
+ } else if (dev->mmio[n].unmap) {
+ dev->mmio[n].unmap(dev, dev->mmio[n].addr);
} else {
cpu_register_physical_memory(dev->mmio[n].addr, dev->mmio[n].size,
IO_MEM_UNASSIGNED);
@@ -117,6 +119,19 @@ void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
dev->mmio[n].cb = cb;
}
+void sysbus_init_mmio_cb2(SysBusDevice *dev,
+ mmio_mapfunc cb, mmio_mapfunc unmap)
+{
+ int n;
+
+ assert(dev->num_mmio < QDEV_MAX_MMIO);
+ n = dev->num_mmio++;
+ dev->mmio[n].addr = -1;
+ dev->mmio[n].size = 0;
+ dev->mmio[n].cb = cb;
+ dev->mmio[n].unmap = unmap;
+}
+
void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory)
{
int n;
diff --git a/hw/sysbus.h b/hw/sysbus.h
index 5f62e2d..16fd969 100644
--- a/hw/sysbus.h
+++ b/hw/sysbus.h
@@ -23,6 +23,7 @@ struct SysBusDevice {
target_phys_addr_t addr;
target_phys_addr_t size;
mmio_mapfunc cb;
+ mmio_mapfunc unmap;
ram_addr_t iofunc;
MemoryRegion *memory;
} mmio[QDEV_MAX_MMIO];
@@ -48,6 +49,8 @@ void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size,
ram_addr_t iofunc);
void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
mmio_mapfunc cb);
+void sysbus_init_mmio_cb2(SysBusDevice *dev,
+ mmio_mapfunc cb, mmio_mapfunc unmap);
void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory);
void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p);
void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 16/24] sh_pci: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:07 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/sh_pci.c | 63 +++++++++++++++++++++++++++++++++++++++-------------------
1 files changed, 42 insertions(+), 21 deletions(-)
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index cd86501..76061bb 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -33,13 +33,16 @@ typedef struct SHPCIState {
PCIBus *bus;
PCIDevice *dev;
qemu_irq irq[4];
- int memconfig;
+ MemoryRegion memconfig_p4;
+ MemoryRegion memconfig_a7;
+ MemoryRegion isa;
uint32_t par;
uint32_t mbr;
uint32_t iobr;
} SHPCIState;
-static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
+static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val,
+ unsigned size)
{
SHPCIState *pcic = p;
switch(addr) {
@@ -54,10 +57,10 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
break;
case 0x1c8:
if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
- cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &pcic->isa);
pcic->iobr = val & 0xfffc0001;
- isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000);
+ memory_region_add_subregion(get_system_memory(),
+ pcic->iobr & 0xfffc0000, &pcic->isa);
}
break;
case 0x220:
@@ -66,7 +69,8 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
}
}
-static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
+static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr,
+ unsigned size)
{
SHPCIState *pcic = p;
switch(addr) {
@@ -84,14 +88,14 @@ static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
return 0;
}
-typedef struct {
- CPUReadMemoryFunc * const r[3];
- CPUWriteMemoryFunc * const w[3];
-} MemOp;
-
-static MemOp sh_pci_reg = {
- { NULL, NULL, sh_pci_reg_read },
- { NULL, NULL, sh_pci_reg_write },
+static const MemoryRegionOps sh_pci_reg_ops = {
+ .read = sh_pci_reg_read,
+ .write = sh_pci_reg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static int sh_pci_map_irq(PCIDevice *d, int irq_num)
@@ -110,11 +114,23 @@ static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base)
{
SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
- cpu_register_physical_memory(P4ADDR(base), 0x224, s->memconfig);
- cpu_register_physical_memory(A7ADDR(base), 0x224, s->memconfig);
-
+ memory_region_add_subregion(get_system_memory(),
+ P4ADDR(base),
+ &s->memconfig_p4);
+ memory_region_add_subregion(get_system_memory(),
+ A7ADDR(base),
+ &s->memconfig_a7);
s->iobr = 0xfe240000;
- isa_mmio_init(s->iobr, 0x40000);
+ memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa);
+}
+
+static void sh_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
+
+ memory_region_del_subregion(get_system_memory(), &s->memconfig_p4);
+ memory_region_del_subregion(get_system_memory(), &s->memconfig_a7);
+ memory_region_del_subregion(get_system_memory(), &s->isa);
}
static int sh_pci_init_device(SysBusDevice *dev)
@@ -132,9 +148,14 @@ static int sh_pci_init_device(SysBusDevice *dev)
get_system_memory(),
get_system_io(),
PCI_DEVFN(0, 0), 4);
- s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w,
- s, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x224, sh_pci_map);
+ memory_region_init_io(&s->memconfig_p4, &sh_pci_reg_ops, s,
+ "sh_pci", 0x224);
+ memory_region_init_alias(&s->memconfig_a7, "sh_pci.2", &s->memconfig_a7,
+ 0, 0x224);
+ isa_mmio_setup(&s->isa, 0x40000);
+ sysbus_init_mmio_cb2(dev, sh_pci_map, sh_pci_unmap);
+ sysbus_init_mmio_region(dev, &s->memconfig_a7);
+ sysbus_init_mmio_region(dev, &s->isa);
s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host");
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 16/24] sh_pci: convert to memory API
@ 2011-08-08 17:07 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/sh_pci.c | 63 +++++++++++++++++++++++++++++++++++++++-------------------
1 files changed, 42 insertions(+), 21 deletions(-)
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index cd86501..76061bb 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -33,13 +33,16 @@ typedef struct SHPCIState {
PCIBus *bus;
PCIDevice *dev;
qemu_irq irq[4];
- int memconfig;
+ MemoryRegion memconfig_p4;
+ MemoryRegion memconfig_a7;
+ MemoryRegion isa;
uint32_t par;
uint32_t mbr;
uint32_t iobr;
} SHPCIState;
-static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
+static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val,
+ unsigned size)
{
SHPCIState *pcic = p;
switch(addr) {
@@ -54,10 +57,10 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
break;
case 0x1c8:
if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
- cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &pcic->isa);
pcic->iobr = val & 0xfffc0001;
- isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000);
+ memory_region_add_subregion(get_system_memory(),
+ pcic->iobr & 0xfffc0000, &pcic->isa);
}
break;
case 0x220:
@@ -66,7 +69,8 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
}
}
-static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
+static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr,
+ unsigned size)
{
SHPCIState *pcic = p;
switch(addr) {
@@ -84,14 +88,14 @@ static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
return 0;
}
-typedef struct {
- CPUReadMemoryFunc * const r[3];
- CPUWriteMemoryFunc * const w[3];
-} MemOp;
-
-static MemOp sh_pci_reg = {
- { NULL, NULL, sh_pci_reg_read },
- { NULL, NULL, sh_pci_reg_write },
+static const MemoryRegionOps sh_pci_reg_ops = {
+ .read = sh_pci_reg_read,
+ .write = sh_pci_reg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static int sh_pci_map_irq(PCIDevice *d, int irq_num)
@@ -110,11 +114,23 @@ static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base)
{
SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
- cpu_register_physical_memory(P4ADDR(base), 0x224, s->memconfig);
- cpu_register_physical_memory(A7ADDR(base), 0x224, s->memconfig);
-
+ memory_region_add_subregion(get_system_memory(),
+ P4ADDR(base),
+ &s->memconfig_p4);
+ memory_region_add_subregion(get_system_memory(),
+ A7ADDR(base),
+ &s->memconfig_a7);
s->iobr = 0xfe240000;
- isa_mmio_init(s->iobr, 0x40000);
+ memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa);
+}
+
+static void sh_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
+
+ memory_region_del_subregion(get_system_memory(), &s->memconfig_p4);
+ memory_region_del_subregion(get_system_memory(), &s->memconfig_a7);
+ memory_region_del_subregion(get_system_memory(), &s->isa);
}
static int sh_pci_init_device(SysBusDevice *dev)
@@ -132,9 +148,14 @@ static int sh_pci_init_device(SysBusDevice *dev)
get_system_memory(),
get_system_io(),
PCI_DEVFN(0, 0), 4);
- s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w,
- s, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x224, sh_pci_map);
+ memory_region_init_io(&s->memconfig_p4, &sh_pci_reg_ops, s,
+ "sh_pci", 0x224);
+ memory_region_init_alias(&s->memconfig_a7, "sh_pci.2", &s->memconfig_a7,
+ 0, 0x224);
+ isa_mmio_setup(&s->isa, 0x40000);
+ sysbus_init_mmio_cb2(dev, sh_pci_map, sh_pci_unmap);
+ sysbus_init_mmio_region(dev, &s->memconfig_a7);
+ sysbus_init_mmio_region(dev, &s->isa);
s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host");
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 17/24] arm11mpcore: use sysbus_init_mmio_cb2
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:07 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
This tells the sysbus code it need not use IO_MEM_UNASSIGNED.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/arm11mpcore.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
index b47707f..7d60ef6 100644
--- a/hw/arm11mpcore.c
+++ b/hw/arm11mpcore.c
@@ -54,6 +54,11 @@ static void mpcore_rirq_map(SysBusDevice *dev, target_phys_addr_t base)
sysbus_mmio_map(s->priv, 0, base);
}
+static void mpcore_rirq_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ /* nothing to do */
+}
+
static int realview_mpcore_init(SysBusDevice *dev)
{
mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
@@ -79,7 +84,7 @@ static int realview_mpcore_init(SysBusDevice *dev)
}
}
qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
- sysbus_init_mmio_cb(dev, 0x2000, mpcore_rirq_map);
+ sysbus_init_mmio_cb2(dev, mpcore_rirq_map, mpcore_rirq_unmap);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 17/24] arm11mpcore: use sysbus_init_mmio_cb2
@ 2011-08-08 17:07 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
This tells the sysbus code it need not use IO_MEM_UNASSIGNED.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/arm11mpcore.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
index b47707f..7d60ef6 100644
--- a/hw/arm11mpcore.c
+++ b/hw/arm11mpcore.c
@@ -54,6 +54,11 @@ static void mpcore_rirq_map(SysBusDevice *dev, target_phys_addr_t base)
sysbus_mmio_map(s->priv, 0, base);
}
+static void mpcore_rirq_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ /* nothing to do */
+}
+
static int realview_mpcore_init(SysBusDevice *dev)
{
mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
@@ -79,7 +84,7 @@ static int realview_mpcore_init(SysBusDevice *dev)
}
}
qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
- sysbus_init_mmio_cb(dev, 0x2000, mpcore_rirq_map);
+ sysbus_init_mmio_cb2(dev, mpcore_rirq_map, mpcore_rirq_unmap);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 18/24] versatile_pci: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:07 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/versatile_pci.c | 94 ++++++++++++++++++++++++---------------------------
1 files changed, 44 insertions(+), 50 deletions(-)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index e1d5c0b..43edf77 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -16,7 +16,9 @@ typedef struct {
SysBusDevice busdev;
qemu_irq irq[4];
int realview;
- int mem_config;
+ MemoryRegion mem_config;
+ MemoryRegion mem_config2;
+ MemoryRegion isa;
} PCIVPBState;
static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
@@ -24,55 +26,24 @@ static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
return addr & 0xffffff;
}
-static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
+ pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
}
-static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
-}
-
-static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
-}
-
-static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
+static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
- return val;
+ val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
+ return size;
}
-static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
- return val;
-}
-
-static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
- return val;
-}
-
-static CPUWriteMemoryFunc * const pci_vpb_config_write[] = {
- &pci_vpb_config_writeb,
- &pci_vpb_config_writew,
- &pci_vpb_config_writel,
-};
-
-static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
- &pci_vpb_config_readb,
- &pci_vpb_config_readw,
- &pci_vpb_config_readl,
+static const MemoryRegionOps pci_vpb_config_ops = {
+ .read = pci_vpb_config_read,
+ .write = pci_vpb_config_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
@@ -87,17 +58,35 @@ static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
+
static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
{
PCIVPBState *s = (PCIVPBState *)dev;
/* Selfconfig area. */
- cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
+ memory_region_add_subregion(get_system_memory(), base + 0x01000000,
+ &s->mem_config);
/* Normal config area. */
- cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
+ memory_region_add_subregion(get_system_memory(), base + 0x02000000,
+ &s->mem_config2);
if (s->realview) {
/* IO memory area. */
- isa_mmio_init(base + 0x03000000, 0x00100000);
+ memory_region_add_subregion(get_system_memory(), base + 0x03000000,
+ &s->isa);
+ }
+}
+
+static void pci_vpb_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ PCIVPBState *s = (PCIVPBState *)dev;
+ /* Selfconfig area. */
+ memory_region_del_subregion(get_system_memory(), &s->mem_config);
+ /* Normal config area. */
+ memory_region_del_subregion(get_system_memory(), &s->mem_config2);
+
+ if (s->realview) {
+ /* IO memory area. */
+ memory_region_del_subregion(get_system_memory(), &s->isa);
}
}
@@ -117,10 +106,15 @@ static int pci_vpb_init(SysBusDevice *dev)
/* ??? Register memory space. */
- s->mem_config = cpu_register_io_memory(pci_vpb_config_read,
- pci_vpb_config_write, bus,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
+ memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
+ "pci-vpb-selfconfig", 0x1000000);
+ memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
+ "pci-vpb-config", 0x1000000);
+ if (s->realview) {
+ isa_mmio_setup(&s->isa, 0x0100000);
+ }
+
+ sysbus_init_mmio_cb2(dev, pci_vpb_map, pci_vpb_unmap);
pci_create_simple(bus, -1, "versatile_pci_host");
return 0;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 18/24] versatile_pci: convert to memory API
@ 2011-08-08 17:07 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/versatile_pci.c | 94 ++++++++++++++++++++++++---------------------------
1 files changed, 44 insertions(+), 50 deletions(-)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index e1d5c0b..43edf77 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -16,7 +16,9 @@ typedef struct {
SysBusDevice busdev;
qemu_irq irq[4];
int realview;
- int mem_config;
+ MemoryRegion mem_config;
+ MemoryRegion mem_config2;
+ MemoryRegion isa;
} PCIVPBState;
static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
@@ -24,55 +26,24 @@ static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
return addr & 0xffffff;
}
-static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
+ pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
}
-static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
-}
-
-static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
-}
-
-static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
+static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
- return val;
+ val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
+ return size;
}
-static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
- return val;
-}
-
-static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
- return val;
-}
-
-static CPUWriteMemoryFunc * const pci_vpb_config_write[] = {
- &pci_vpb_config_writeb,
- &pci_vpb_config_writew,
- &pci_vpb_config_writel,
-};
-
-static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
- &pci_vpb_config_readb,
- &pci_vpb_config_readw,
- &pci_vpb_config_readl,
+static const MemoryRegionOps pci_vpb_config_ops = {
+ .read = pci_vpb_config_read,
+ .write = pci_vpb_config_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
@@ -87,17 +58,35 @@ static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
+
static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
{
PCIVPBState *s = (PCIVPBState *)dev;
/* Selfconfig area. */
- cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
+ memory_region_add_subregion(get_system_memory(), base + 0x01000000,
+ &s->mem_config);
/* Normal config area. */
- cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
+ memory_region_add_subregion(get_system_memory(), base + 0x02000000,
+ &s->mem_config2);
if (s->realview) {
/* IO memory area. */
- isa_mmio_init(base + 0x03000000, 0x00100000);
+ memory_region_add_subregion(get_system_memory(), base + 0x03000000,
+ &s->isa);
+ }
+}
+
+static void pci_vpb_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ PCIVPBState *s = (PCIVPBState *)dev;
+ /* Selfconfig area. */
+ memory_region_del_subregion(get_system_memory(), &s->mem_config);
+ /* Normal config area. */
+ memory_region_del_subregion(get_system_memory(), &s->mem_config2);
+
+ if (s->realview) {
+ /* IO memory area. */
+ memory_region_del_subregion(get_system_memory(), &s->isa);
}
}
@@ -117,10 +106,15 @@ static int pci_vpb_init(SysBusDevice *dev)
/* ??? Register memory space. */
- s->mem_config = cpu_register_io_memory(pci_vpb_config_read,
- pci_vpb_config_write, bus,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
+ memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
+ "pci-vpb-selfconfig", 0x1000000);
+ memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
+ "pci-vpb-config", 0x1000000);
+ if (s->realview) {
+ isa_mmio_setup(&s->isa, 0x0100000);
+ }
+
+ sysbus_init_mmio_cb2(dev, pci_vpb_map, pci_vpb_unmap);
pci_create_simple(bus, -1, "versatile_pci_host");
return 0;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 19/24] ppce500_pci: convert to sysbus_init_mmio_cb2()
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:07 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Not a huge step forward, but at least we now have a 1:1 relationship
between registration and unregistration.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/ppce500_pci.c | 12 +++++++++++-
1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 6a9f979..4390aeb 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -274,6 +274,16 @@ static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
s->reg);
}
+static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ cpu_register_physical_memory(base + PCIE500_CFGADDR, 4,
+ IO_MEM_UNASSIGNED);
+ cpu_register_physical_memory(base + PCIE500_CFGDATA, 4,
+ IO_MEM_UNASSIGNED);
+ cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
+ IO_MEM_UNASSIGNED);
+}
+
#include "exec-memory.h"
static int e500_pcihost_initfn(SysBusDevice *dev)
@@ -304,7 +314,7 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
DEVICE_LITTLE_ENDIAN);
s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
DEVICE_BIG_ENDIAN);
- sysbus_init_mmio_cb(dev, PCIE500_ALL_SIZE, e500_pci_map);
+ sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 19/24] ppce500_pci: convert to sysbus_init_mmio_cb2()
@ 2011-08-08 17:07 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Not a huge step forward, but at least we now have a 1:1 relationship
between registration and unregistration.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/ppce500_pci.c | 12 +++++++++++-
1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 6a9f979..4390aeb 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -274,6 +274,16 @@ static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
s->reg);
}
+static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ cpu_register_physical_memory(base + PCIE500_CFGADDR, 4,
+ IO_MEM_UNASSIGNED);
+ cpu_register_physical_memory(base + PCIE500_CFGDATA, 4,
+ IO_MEM_UNASSIGNED);
+ cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
+ IO_MEM_UNASSIGNED);
+}
+
#include "exec-memory.h"
static int e500_pcihost_initfn(SysBusDevice *dev)
@@ -304,7 +314,7 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
DEVICE_LITTLE_ENDIAN);
s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
DEVICE_BIG_ENDIAN);
- sysbus_init_mmio_cb(dev, PCIE500_ALL_SIZE, e500_pci_map);
+ sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 20/24] sysbus: remove sysbus_init_mmio_cb()
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:07 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
This problem with this function is that it is not reversible - it is
impossible to know where things are registered and unregister them
exactly. As there are no more users, we can remove it.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/sysbus.c | 12 ------------
hw/sysbus.h | 2 --
2 files changed, 0 insertions(+), 14 deletions(-)
diff --git a/hw/sysbus.c b/hw/sysbus.c
index 64749e0..87221df 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -107,18 +107,6 @@ void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size,
dev->mmio[n].iofunc = iofunc;
}
-void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
- mmio_mapfunc cb)
-{
- int n;
-
- assert(dev->num_mmio < QDEV_MAX_MMIO);
- n = dev->num_mmio++;
- dev->mmio[n].addr = -1;
- dev->mmio[n].size = size;
- dev->mmio[n].cb = cb;
-}
-
void sysbus_init_mmio_cb2(SysBusDevice *dev,
mmio_mapfunc cb, mmio_mapfunc unmap)
{
diff --git a/hw/sysbus.h b/hw/sysbus.h
index 16fd969..b87c6c5 100644
--- a/hw/sysbus.h
+++ b/hw/sysbus.h
@@ -47,8 +47,6 @@ void sysbus_register_withprop(SysBusDeviceInfo *info);
void *sysbus_new(void);
void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size,
ram_addr_t iofunc);
-void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
- mmio_mapfunc cb);
void sysbus_init_mmio_cb2(SysBusDevice *dev,
mmio_mapfunc cb, mmio_mapfunc unmap);
void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 20/24] sysbus: remove sysbus_init_mmio_cb()
@ 2011-08-08 17:07 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
This problem with this function is that it is not reversible - it is
impossible to know where things are registered and unregister them
exactly. As there are no more users, we can remove it.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/sysbus.c | 12 ------------
hw/sysbus.h | 2 --
2 files changed, 0 insertions(+), 14 deletions(-)
diff --git a/hw/sysbus.c b/hw/sysbus.c
index 64749e0..87221df 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -107,18 +107,6 @@ void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size,
dev->mmio[n].iofunc = iofunc;
}
-void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
- mmio_mapfunc cb)
-{
- int n;
-
- assert(dev->num_mmio < QDEV_MAX_MMIO);
- n = dev->num_mmio++;
- dev->mmio[n].addr = -1;
- dev->mmio[n].size = size;
- dev->mmio[n].cb = cb;
-}
-
void sysbus_init_mmio_cb2(SysBusDevice *dev,
mmio_mapfunc cb, mmio_mapfunc unmap)
{
diff --git a/hw/sysbus.h b/hw/sysbus.h
index 16fd969..b87c6c5 100644
--- a/hw/sysbus.h
+++ b/hw/sysbus.h
@@ -47,8 +47,6 @@ void sysbus_register_withprop(SysBusDeviceInfo *info);
void *sysbus_new(void);
void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size,
ram_addr_t iofunc);
-void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
- mmio_mapfunc cb);
void sysbus_init_mmio_cb2(SysBusDevice *dev,
mmio_mapfunc cb, mmio_mapfunc unmap);
void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 21/24] isa: add isa_address_space()
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:07 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
A helper that returns the address space used by ISA devices. Useful
for getting rid of isa_mem_base, multiple ISA buses, or ISA buses behind
bridges.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/isa-bus.c | 6 ++++++
hw/isa.h | 1 +
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index 2765543..1cb497f 100644
--- a/hw/isa-bus.c
+++ b/hw/isa-bus.c
@@ -20,6 +20,7 @@
#include "monitor.h"
#include "sysbus.h"
#include "isa.h"
+#include "exec-memory.h"
struct ISABus {
BusState qbus;
@@ -202,4 +203,9 @@ static char *isabus_get_fw_dev_path(DeviceState *dev)
return strdup(path);
}
+MemoryRegion *isa_address_space(ISADevice *dev)
+{
+ return get_system_memory();
+}
+
device_init(isabus_register_devices)
diff --git a/hw/isa.h b/hw/isa.h
index f1f2181..f344699 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -32,6 +32,7 @@ void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
void isa_init_ioport(ISADevice *dev, uint16_t ioport);
void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length);
void isa_qdev_register(ISADeviceInfo *info);
+MemoryRegion *isa_address_space(ISADevice *dev);
ISADevice *isa_create(const char *name);
ISADevice *isa_try_create(const char *name);
ISADevice *isa_create_simple(const char *name);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 21/24] isa: add isa_address_space()
@ 2011-08-08 17:07 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
A helper that returns the address space used by ISA devices. Useful
for getting rid of isa_mem_base, multiple ISA buses, or ISA buses behind
bridges.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/isa-bus.c | 6 ++++++
hw/isa.h | 1 +
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index 2765543..1cb497f 100644
--- a/hw/isa-bus.c
+++ b/hw/isa-bus.c
@@ -20,6 +20,7 @@
#include "monitor.h"
#include "sysbus.h"
#include "isa.h"
+#include "exec-memory.h"
struct ISABus {
BusState qbus;
@@ -202,4 +203,9 @@ static char *isabus_get_fw_dev_path(DeviceState *dev)
return strdup(path);
}
+MemoryRegion *isa_address_space(ISADevice *dev)
+{
+ return get_system_memory();
+}
+
device_init(isabus_register_devices)
diff --git a/hw/isa.h b/hw/isa.h
index f1f2181..f344699 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -32,6 +32,7 @@ void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
void isa_init_ioport(ISADevice *dev, uint16_t ioport);
void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length);
void isa_qdev_register(ISADeviceInfo *info);
+MemoryRegion *isa_address_space(ISADevice *dev);
ISADevice *isa_create(const char *name);
ISADevice *isa_try_create(const char *name);
ISADevice *isa_create_simple(const char *name);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 22/24] pci: add pci_address_space()
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:07 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Returns the PCI address space. Useful for bridges that can obscure
part of the PCI address space.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/pci.c | 5 +++++
hw/pci.h | 1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index dc7271a..4e495b4 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -2165,3 +2165,8 @@ int pci_qdev_find_device(const char *id, PCIDevice **pdev)
return rc;
}
+
+MemoryRegion *pci_address_space(PCIDevice *dev)
+{
+ return dev->bus->address_space_mem;
+}
diff --git a/hw/pci.h b/hw/pci.h
index d7ad7fb..391217e 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -220,6 +220,7 @@ void pci_default_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len);
void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f);
+MemoryRegion *pci_address_space(PCIDevice *dev);
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 22/24] pci: add pci_address_space()
@ 2011-08-08 17:07 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Returns the PCI address space. Useful for bridges that can obscure
part of the PCI address space.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/pci.c | 5 +++++
hw/pci.h | 1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index dc7271a..4e495b4 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -2165,3 +2165,8 @@ int pci_qdev_find_device(const char *id, PCIDevice **pdev)
return rc;
}
+
+MemoryRegion *pci_address_space(PCIDevice *dev)
+{
+ return dev->bus->address_space_mem;
+}
diff --git a/hw/pci.h b/hw/pci.h
index d7ad7fb..391217e 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -220,6 +220,7 @@ void pci_default_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len);
void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f);
+MemoryRegion *pci_address_space(PCIDevice *dev);
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 23/24] vga: drop get_system_memory() from vga devices and derivatives
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:07 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Instead, use the bus accessors, or get the address space directly
from the board constructor.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/cirrus_vga.c | 12 ++++++------
hw/mips_jazz.c | 3 ++-
hw/pc.c | 3 ++-
hw/pc.h | 5 +++--
hw/qxl.c | 2 +-
hw/vga-isa-mm.c | 15 ++++++++-------
hw/vga-isa.c | 5 ++---
hw/vga-pci.c | 4 ++--
hw/vga.c | 9 ++++-----
hw/vga_int.h | 4 ++--
hw/vmware_vga.c | 9 +++++----
11 files changed, 37 insertions(+), 34 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index b489309..8e8b24c 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -32,7 +32,6 @@
#include "console.h"
#include "vga_int.h"
#include "loader.h"
-#include "exec-memory.h"
/*
* TODO:
@@ -2803,7 +2802,8 @@ static const MemoryRegionOps cirrus_linear_io_ops = {
},
};
-static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
+static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
+ MemoryRegion *system_memory)
{
int i;
static int inited;
@@ -2856,7 +2856,7 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
"cirrus-low-memory", 0x20000);
memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
- memory_region_add_subregion_overlap(get_system_memory(),
+ memory_region_add_subregion_overlap(system_memory,
isa_mem_base + 0x000a0000,
&s->low_mem_container,
1);
@@ -2899,14 +2899,14 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
*
***************************************/
-void isa_cirrus_vga_init(void)
+void isa_cirrus_vga_init(MemoryRegion *system_memory)
{
CirrusVGAState *s;
s = qemu_mallocz(sizeof(CirrusVGAState));
vga_common_init(&s->vga, VGA_RAM_SIZE);
- cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
+ cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0, system_memory);
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update,
&s->vga);
@@ -2930,7 +2930,7 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
/* setup VGA */
vga_common_init(&s->vga, VGA_RAM_SIZE);
- cirrus_init_common(s, device_id, 1);
+ cirrus_init_common(s, device_id, 1, pci_address_space(dev));
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update,
&s->vga);
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index f6ab6dc..499c707 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -38,6 +38,7 @@
#include "mc146818rtc.h"
#include "blockdev.h"
#include "sysbus.h"
+#include "exec-memory.h"
enum jazz_model_e
{
@@ -197,7 +198,7 @@ void mips_jazz_init (ram_addr_t ram_size,
g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
break;
case JAZZ_PICA61:
- isa_vga_mm_init(0x40000000, 0x60000000, 0);
+ isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
break;
default:
break;
diff --git a/hw/pc.c b/hw/pc.c
index 1c9d89a..f43d181 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -42,6 +42,7 @@
#include "blockdev.h"
#include "ui/qemu-spice.h"
#include "memory.h"
+#include "exec-memory.h"
/* output Bochs bios info messages */
//#define DEBUG_BIOS
@@ -1066,7 +1067,7 @@ void pc_vga_init(PCIBus *pci_bus)
if (pci_bus) {
pci_cirrus_vga_init(pci_bus);
} else {
- isa_cirrus_vga_init();
+ isa_cirrus_vga_init(get_system_memory());
}
} else if (vmsvga_enabled) {
if (pci_bus) {
diff --git a/hw/pc.h b/hw/pc.h
index ec34db7..d871fd8 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -212,11 +212,12 @@ static inline int isa_vga_init(void)
int pci_vga_init(PCIBus *bus);
int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift);
+ target_phys_addr_t ctrl_base, int it_shift,
+ MemoryRegion *address_space);
/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus);
-void isa_cirrus_vga_init(void);
+void isa_cirrus_vga_init(MemoryRegion *address_space);
/* ne2000.c */
static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd)
diff --git a/hw/qxl.c b/hw/qxl.c
index db7ae7a..9fe36cf 100644
--- a/hw/qxl.c
+++ b/hw/qxl.c
@@ -1599,7 +1599,7 @@ static int qxl_init_primary(PCIDevice *dev)
ram_size = 32 * 1024 * 1024;
}
vga_common_init(vga, ram_size);
- vga_init(vga);
+ vga_init(vga, pci_address_space(dev));
register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga);
register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga);
diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c
index 96e6e7d..3fe23dd 100644
--- a/hw/vga-isa-mm.c
+++ b/hw/vga-isa-mm.c
@@ -27,7 +27,6 @@
#include "vga_int.h"
#include "pixel_ops.h"
#include "qemu-timer.h"
-#include "exec-memory.h"
typedef struct ISAVGAMMState {
VGACommonState vga;
@@ -97,7 +96,8 @@ static const MemoryRegionOps vga_mm_ctrl_ops = {
};
static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift)
+ target_phys_addr_t ctrl_base, int it_shift,
+ MemoryRegion *address_space)
{
MemoryRegion *s_ioport_ctrl, *vga_io_memory;
@@ -113,26 +113,27 @@ static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
vmstate_register(NULL, 0, &vmstate_vga_common, s);
- memory_region_add_subregion(get_system_memory(), ctrl_base, s_ioport_ctrl);
+ memory_region_add_subregion(address_space, ctrl_base, s_ioport_ctrl);
s->vga.bank_offset = 0;
- memory_region_add_subregion(get_system_memory(),
+ memory_region_add_subregion(address_space,
vram_base + 0x000a0000, vga_io_memory);
memory_region_set_coalescing(vga_io_memory);
}
int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift)
+ target_phys_addr_t ctrl_base, int it_shift,
+ MemoryRegion *address_space)
{
ISAVGAMMState *s;
s = qemu_mallocz(sizeof(*s));
vga_common_init(&s->vga, VGA_RAM_SIZE);
- vga_mm_init(s, vram_base, ctrl_base, it_shift);
+ vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space);
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update, s);
- vga_init_vbe(&s->vga);
+ vga_init_vbe(&s->vga, address_space);
return 0;
}
diff --git a/hw/vga-isa.c b/hw/vga-isa.c
index fef7f58..0d19901 100644
--- a/hw/vga-isa.c
+++ b/hw/vga-isa.c
@@ -28,7 +28,6 @@
#include "pixel_ops.h"
#include "qemu-timer.h"
#include "loader.h"
-#include "exec-memory.h"
typedef struct ISAVGAState {
ISADevice dev;
@@ -51,7 +50,7 @@ static int vga_initfn(ISADevice *dev)
vga_common_init(s, VGA_RAM_SIZE);
vga_io_memory = vga_init_io(s);
- memory_region_add_subregion_overlap(get_system_memory(),
+ memory_region_add_subregion_overlap(isa_address_space(dev),
isa_mem_base + 0x000a0000,
vga_io_memory, 1);
memory_region_set_coalescing(vga_io_memory);
@@ -68,7 +67,7 @@ static int vga_initfn(ISADevice *dev)
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
- vga_init_vbe(s);
+ vga_init_vbe(s, isa_address_space(dev));
/* ROM BIOS */
rom_add_vga(VGABIOS_FILENAME);
return 0;
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index c67be0a..3c8bcb0 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -54,7 +54,7 @@ static int pci_vga_initfn(PCIDevice *dev)
// vga + console init
vga_common_init(s, VGA_RAM_SIZE);
- vga_init(s);
+ vga_init(s, pci_address_space(dev));
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
@@ -64,7 +64,7 @@ static int pci_vga_initfn(PCIDevice *dev)
if (!dev->rom_bar) {
/* compatibility with pc-0.13 and older */
- vga_init_vbe(s);
+ vga_init_vbe(s, pci_address_space(dev));
}
return 0;
diff --git a/hw/vga.c b/hw/vga.c
index 33dc478..8acc545 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -28,7 +28,6 @@
#include "vga_int.h"
#include "pixel_ops.h"
#include "qemu-timer.h"
-#include "exec-memory.h"
//#define DEBUG_VGA
//#define DEBUG_VGA_MEM
@@ -2241,7 +2240,7 @@ MemoryRegion *vga_init_io(VGACommonState *s)
return vga_mem;
}
-void vga_init(VGACommonState *s)
+void vga_init(VGACommonState *s, MemoryRegion *address_space)
{
MemoryRegion *vga_io_memory;
@@ -2250,18 +2249,18 @@ void vga_init(VGACommonState *s)
s->bank_offset = 0;
vga_io_memory = vga_init_io(s);
- memory_region_add_subregion_overlap(get_system_memory(),
+ memory_region_add_subregion_overlap(address_space,
isa_mem_base + 0x000a0000,
vga_io_memory,
1);
memory_region_set_coalescing(vga_io_memory);
}
-void vga_init_vbe(VGACommonState *s)
+void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
{
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
- memory_region_add_subregion(get_system_memory(),
+ memory_region_add_subregion(system_memory,
VBE_DISPI_LFB_PHYSICAL_ADDRESS,
&s->vram);
s->vbe_mapped = 1;
diff --git a/hw/vga_int.h b/hw/vga_int.h
index 100d98c..7e4ed71 100644
--- a/hw/vga_int.h
+++ b/hw/vga_int.h
@@ -187,7 +187,7 @@ static inline int c6_to_8(int v)
}
void vga_common_init(VGACommonState *s, int vga_ram_size);
-void vga_init(VGACommonState *s);
+void vga_init(VGACommonState *s, MemoryRegion *address_space);
MemoryRegion *vga_init_io(VGACommonState *s);
void vga_common_reset(VGACommonState *s);
@@ -217,7 +217,7 @@ void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
unsigned int color_xor);
int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
-void vga_init_vbe(VGACommonState *s);
+void vga_init_vbe(VGACommonState *s, MemoryRegion *address_space);
extern const uint8_t sr_mask[8];
extern const uint8_t gr_mask[16];
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index d5cfa70..dded3f6 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -1207,7 +1207,8 @@ static const VMStateDescription vmstate_vmware_vga = {
}
};
-static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
+static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size,
+ MemoryRegion *address_space)
{
s->scratch_size = SVGA_SCRATCH_SIZE;
s->scratch = qemu_malloc(s->scratch_size * 4);
@@ -1223,7 +1224,7 @@ static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
vga_common_init(&s->vga, vga_ram_size);
- vga_init(&s->vga);
+ vga_init(&s->vga, address_space);
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
vmsvga_reset(s);
@@ -1293,7 +1294,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
"vmsvga-io", 0x10);
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
- vmsvga_init(&s->chip, VGA_RAM_SIZE);
+ vmsvga_init(&s->chip, VGA_RAM_SIZE, pci_address_space(dev));
pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
@@ -1301,7 +1302,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
if (!dev->rom_bar) {
/* compatibility with pc-0.13 and older */
- vga_init_vbe(&s->chip.vga);
+ vga_init_vbe(&s->chip.vga, pci_address_space(dev));
}
return 0;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 23/24] vga: drop get_system_memory() from vga devices and derivatives
@ 2011-08-08 17:07 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
Instead, use the bus accessors, or get the address space directly
from the board constructor.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/cirrus_vga.c | 12 ++++++------
hw/mips_jazz.c | 3 ++-
hw/pc.c | 3 ++-
hw/pc.h | 5 +++--
hw/qxl.c | 2 +-
hw/vga-isa-mm.c | 15 ++++++++-------
hw/vga-isa.c | 5 ++---
hw/vga-pci.c | 4 ++--
hw/vga.c | 9 ++++-----
hw/vga_int.h | 4 ++--
hw/vmware_vga.c | 9 +++++----
11 files changed, 37 insertions(+), 34 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index b489309..8e8b24c 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -32,7 +32,6 @@
#include "console.h"
#include "vga_int.h"
#include "loader.h"
-#include "exec-memory.h"
/*
* TODO:
@@ -2803,7 +2802,8 @@ static const MemoryRegionOps cirrus_linear_io_ops = {
},
};
-static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
+static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
+ MemoryRegion *system_memory)
{
int i;
static int inited;
@@ -2856,7 +2856,7 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
"cirrus-low-memory", 0x20000);
memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
- memory_region_add_subregion_overlap(get_system_memory(),
+ memory_region_add_subregion_overlap(system_memory,
isa_mem_base + 0x000a0000,
&s->low_mem_container,
1);
@@ -2899,14 +2899,14 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
*
***************************************/
-void isa_cirrus_vga_init(void)
+void isa_cirrus_vga_init(MemoryRegion *system_memory)
{
CirrusVGAState *s;
s = qemu_mallocz(sizeof(CirrusVGAState));
vga_common_init(&s->vga, VGA_RAM_SIZE);
- cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
+ cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0, system_memory);
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update,
&s->vga);
@@ -2930,7 +2930,7 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
/* setup VGA */
vga_common_init(&s->vga, VGA_RAM_SIZE);
- cirrus_init_common(s, device_id, 1);
+ cirrus_init_common(s, device_id, 1, pci_address_space(dev));
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update,
&s->vga);
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index f6ab6dc..499c707 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -38,6 +38,7 @@
#include "mc146818rtc.h"
#include "blockdev.h"
#include "sysbus.h"
+#include "exec-memory.h"
enum jazz_model_e
{
@@ -197,7 +198,7 @@ void mips_jazz_init (ram_addr_t ram_size,
g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
break;
case JAZZ_PICA61:
- isa_vga_mm_init(0x40000000, 0x60000000, 0);
+ isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
break;
default:
break;
diff --git a/hw/pc.c b/hw/pc.c
index 1c9d89a..f43d181 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -42,6 +42,7 @@
#include "blockdev.h"
#include "ui/qemu-spice.h"
#include "memory.h"
+#include "exec-memory.h"
/* output Bochs bios info messages */
//#define DEBUG_BIOS
@@ -1066,7 +1067,7 @@ void pc_vga_init(PCIBus *pci_bus)
if (pci_bus) {
pci_cirrus_vga_init(pci_bus);
} else {
- isa_cirrus_vga_init();
+ isa_cirrus_vga_init(get_system_memory());
}
} else if (vmsvga_enabled) {
if (pci_bus) {
diff --git a/hw/pc.h b/hw/pc.h
index ec34db7..d871fd8 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -212,11 +212,12 @@ static inline int isa_vga_init(void)
int pci_vga_init(PCIBus *bus);
int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift);
+ target_phys_addr_t ctrl_base, int it_shift,
+ MemoryRegion *address_space);
/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus);
-void isa_cirrus_vga_init(void);
+void isa_cirrus_vga_init(MemoryRegion *address_space);
/* ne2000.c */
static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd)
diff --git a/hw/qxl.c b/hw/qxl.c
index db7ae7a..9fe36cf 100644
--- a/hw/qxl.c
+++ b/hw/qxl.c
@@ -1599,7 +1599,7 @@ static int qxl_init_primary(PCIDevice *dev)
ram_size = 32 * 1024 * 1024;
}
vga_common_init(vga, ram_size);
- vga_init(vga);
+ vga_init(vga, pci_address_space(dev));
register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga);
register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga);
diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c
index 96e6e7d..3fe23dd 100644
--- a/hw/vga-isa-mm.c
+++ b/hw/vga-isa-mm.c
@@ -27,7 +27,6 @@
#include "vga_int.h"
#include "pixel_ops.h"
#include "qemu-timer.h"
-#include "exec-memory.h"
typedef struct ISAVGAMMState {
VGACommonState vga;
@@ -97,7 +96,8 @@ static const MemoryRegionOps vga_mm_ctrl_ops = {
};
static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift)
+ target_phys_addr_t ctrl_base, int it_shift,
+ MemoryRegion *address_space)
{
MemoryRegion *s_ioport_ctrl, *vga_io_memory;
@@ -113,26 +113,27 @@ static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
vmstate_register(NULL, 0, &vmstate_vga_common, s);
- memory_region_add_subregion(get_system_memory(), ctrl_base, s_ioport_ctrl);
+ memory_region_add_subregion(address_space, ctrl_base, s_ioport_ctrl);
s->vga.bank_offset = 0;
- memory_region_add_subregion(get_system_memory(),
+ memory_region_add_subregion(address_space,
vram_base + 0x000a0000, vga_io_memory);
memory_region_set_coalescing(vga_io_memory);
}
int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift)
+ target_phys_addr_t ctrl_base, int it_shift,
+ MemoryRegion *address_space)
{
ISAVGAMMState *s;
s = qemu_mallocz(sizeof(*s));
vga_common_init(&s->vga, VGA_RAM_SIZE);
- vga_mm_init(s, vram_base, ctrl_base, it_shift);
+ vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space);
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update, s);
- vga_init_vbe(&s->vga);
+ vga_init_vbe(&s->vga, address_space);
return 0;
}
diff --git a/hw/vga-isa.c b/hw/vga-isa.c
index fef7f58..0d19901 100644
--- a/hw/vga-isa.c
+++ b/hw/vga-isa.c
@@ -28,7 +28,6 @@
#include "pixel_ops.h"
#include "qemu-timer.h"
#include "loader.h"
-#include "exec-memory.h"
typedef struct ISAVGAState {
ISADevice dev;
@@ -51,7 +50,7 @@ static int vga_initfn(ISADevice *dev)
vga_common_init(s, VGA_RAM_SIZE);
vga_io_memory = vga_init_io(s);
- memory_region_add_subregion_overlap(get_system_memory(),
+ memory_region_add_subregion_overlap(isa_address_space(dev),
isa_mem_base + 0x000a0000,
vga_io_memory, 1);
memory_region_set_coalescing(vga_io_memory);
@@ -68,7 +67,7 @@ static int vga_initfn(ISADevice *dev)
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
- vga_init_vbe(s);
+ vga_init_vbe(s, isa_address_space(dev));
/* ROM BIOS */
rom_add_vga(VGABIOS_FILENAME);
return 0;
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index c67be0a..3c8bcb0 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -54,7 +54,7 @@ static int pci_vga_initfn(PCIDevice *dev)
// vga + console init
vga_common_init(s, VGA_RAM_SIZE);
- vga_init(s);
+ vga_init(s, pci_address_space(dev));
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
@@ -64,7 +64,7 @@ static int pci_vga_initfn(PCIDevice *dev)
if (!dev->rom_bar) {
/* compatibility with pc-0.13 and older */
- vga_init_vbe(s);
+ vga_init_vbe(s, pci_address_space(dev));
}
return 0;
diff --git a/hw/vga.c b/hw/vga.c
index 33dc478..8acc545 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -28,7 +28,6 @@
#include "vga_int.h"
#include "pixel_ops.h"
#include "qemu-timer.h"
-#include "exec-memory.h"
//#define DEBUG_VGA
//#define DEBUG_VGA_MEM
@@ -2241,7 +2240,7 @@ MemoryRegion *vga_init_io(VGACommonState *s)
return vga_mem;
}
-void vga_init(VGACommonState *s)
+void vga_init(VGACommonState *s, MemoryRegion *address_space)
{
MemoryRegion *vga_io_memory;
@@ -2250,18 +2249,18 @@ void vga_init(VGACommonState *s)
s->bank_offset = 0;
vga_io_memory = vga_init_io(s);
- memory_region_add_subregion_overlap(get_system_memory(),
+ memory_region_add_subregion_overlap(address_space,
isa_mem_base + 0x000a0000,
vga_io_memory,
1);
memory_region_set_coalescing(vga_io_memory);
}
-void vga_init_vbe(VGACommonState *s)
+void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
{
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
- memory_region_add_subregion(get_system_memory(),
+ memory_region_add_subregion(system_memory,
VBE_DISPI_LFB_PHYSICAL_ADDRESS,
&s->vram);
s->vbe_mapped = 1;
diff --git a/hw/vga_int.h b/hw/vga_int.h
index 100d98c..7e4ed71 100644
--- a/hw/vga_int.h
+++ b/hw/vga_int.h
@@ -187,7 +187,7 @@ static inline int c6_to_8(int v)
}
void vga_common_init(VGACommonState *s, int vga_ram_size);
-void vga_init(VGACommonState *s);
+void vga_init(VGACommonState *s, MemoryRegion *address_space);
MemoryRegion *vga_init_io(VGACommonState *s);
void vga_common_reset(VGACommonState *s);
@@ -217,7 +217,7 @@ void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
unsigned int color_xor);
int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
-void vga_init_vbe(VGACommonState *s);
+void vga_init_vbe(VGACommonState *s, MemoryRegion *address_space);
extern const uint8_t sr_mask[8];
extern const uint8_t gr_mask[16];
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index d5cfa70..dded3f6 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -1207,7 +1207,8 @@ static const VMStateDescription vmstate_vmware_vga = {
}
};
-static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
+static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size,
+ MemoryRegion *address_space)
{
s->scratch_size = SVGA_SCRATCH_SIZE;
s->scratch = qemu_malloc(s->scratch_size * 4);
@@ -1223,7 +1224,7 @@ static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
vga_common_init(&s->vga, vga_ram_size);
- vga_init(&s->vga);
+ vga_init(&s->vga, address_space);
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
vmsvga_reset(s);
@@ -1293,7 +1294,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
"vmsvga-io", 0x10);
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
- vmsvga_init(&s->chip, VGA_RAM_SIZE);
+ vmsvga_init(&s->chip, VGA_RAM_SIZE, pci_address_space(dev));
pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
@@ -1301,7 +1302,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
if (!dev->rom_bar) {
/* compatibility with pc-0.13 and older */
- vga_init_vbe(&s->chip.vga);
+ vga_init_vbe(&s->chip.vga, pci_address_space(dev));
}
return 0;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH 24/24] 440fx: fix PAM, PCI holes
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-08 17:07 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
The current implementation of PAM and the PCI holes is broken in several
ways:
- PCI BARs are not restricted to the PCI hole (a BAR may hide memory)
- PCI devices do not respect PAM (if a PCI device maps a region while
PAM maps the region to RAM, the request will be honored)
This patch fixes things by introducing a pci address space, and using
memory region aliases to represent PAM regions, SMRAM, and PCI holes.
The memory hierarchy looks something like
system_memory
|
+--- low memory alias (0-0xe0000000)
| |
| +-- ram@0
|
+--- high memory alias (0x100000000-EOM)
| |
| +-- ram@0xe0000000
|
+--- pci hole alias (end of low memory-0x100000000)
| |
| +-- pci@end-of-low-memory
|
|
+--- pam[n] (0xc0000-0xc3fff etc) (when set to pci, priority 1)
| |
| +-- pci@0xc4000 etc
|
+--- smram (0xa0000-0xbffff) (when set to pci/vga, priority 1)
|
+-- pci@0xa0000 etc
ram (simple ram region)
pci
|
+--- BARn
|
+--- VGA 0xa0000-0xbffff
|
+--- ROMs
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/pc.c | 11 +++--
hw/pc.h | 13 +++++-
hw/pc_piix.c | 23 ++++++++---
hw/piix_pci.c | 114 ++++++++++++++++++++++++++++++++++++++++----------------
4 files changed, 115 insertions(+), 46 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index f43d181..d328304 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -964,7 +964,9 @@ void pc_memory_init(MemoryRegion *system_memory,
const char *kernel_cmdline,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size)
+ ram_addr_t above_4g_mem_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion **ram_memory)
{
char *filename;
int ret, linux_boot, i;
@@ -982,6 +984,7 @@ void pc_memory_init(MemoryRegion *system_memory,
ram = qemu_malloc(sizeof(*ram));
memory_region_init_ram(ram, NULL, "pc.ram",
below_4g_mem_size + above_4g_mem_size);
+ *ram_memory = ram;
ram_below_4g = qemu_malloc(sizeof(*ram_below_4g));
memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
0, below_4g_mem_size);
@@ -1026,7 +1029,7 @@ void pc_memory_init(MemoryRegion *system_memory,
isa_bios = qemu_malloc(sizeof(*isa_bios));
memory_region_init_alias(isa_bios, "isa-bios", bios,
bios_size - isa_bios_size, isa_bios_size);
- memory_region_add_subregion_overlap(system_memory,
+ memory_region_add_subregion_overlap(pci_memory,
0x100000 - isa_bios_size,
isa_bios,
1);
@@ -1034,13 +1037,13 @@ void pc_memory_init(MemoryRegion *system_memory,
option_rom_mr = qemu_malloc(sizeof(*option_rom_mr));
memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
- memory_region_add_subregion_overlap(system_memory,
+ memory_region_add_subregion_overlap(pci_memory,
PC_ROM_MIN_VGA,
option_rom_mr,
1);
/* map all the bios at the top of memory */
- memory_region_add_subregion(system_memory,
+ memory_region_add_subregion(pci_memory,
(uint32_t)(-bios_size),
bios);
diff --git a/hw/pc.h b/hw/pc.h
index d871fd8..dae736e 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -136,7 +136,9 @@ void pc_memory_init(MemoryRegion *system_memory,
const char *kernel_cmdline,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size);
+ ram_addr_t above_4g_mem_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion **ram_memory);
qemu_irq *pc_allocate_cpu_irq(void);
void pc_vga_init(PCIBus *pci_bus);
void pc_basic_device_init(qemu_irq *isa_irq,
@@ -182,8 +184,13 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
- ram_addr_t ram_size);
-void i440fx_init_memory_mappings(PCII440FXState *d);
+ ram_addr_t ram_size,
+ target_phys_addr_t pci_hole_start,
+ target_phys_addr_t pci_hole_size,
+ target_phys_addr_t pci_hole64_start,
+ target_phys_addr_t pci_hole64_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion *ram_memory);
/* piix4.c */
extern PCIDevice *piix4_dev;
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 7dd5008..ee404d9 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -22,6 +22,8 @@
* THE SOFTWARE.
*/
+#include <glib.h>
+
#include "hw.h"
#include "pc.h"
#include "apic.h"
@@ -93,6 +95,8 @@ static void pc_init1(MemoryRegion *system_memory,
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
+ MemoryRegion *ram_memory;
+ MemoryRegion *pci_memory;
pc_cpus_init(cpu_model);
@@ -108,11 +112,15 @@ static void pc_init1(MemoryRegion *system_memory,
below_4g_mem_size = ram_size;
}
+ pci_memory = g_new(MemoryRegion, 1);
+ memory_region_init(pci_memory, "pci", INT64_MAX);
+
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
pc_memory_init(system_memory,
kernel_filename, kernel_cmdline, initrd_filename,
- below_4g_mem_size, above_4g_mem_size);
+ below_4g_mem_size, above_4g_mem_size,
+ pci_memory, &ram_memory);
}
if (!xen_enabled()) {
@@ -130,7 +138,14 @@ static void pc_init1(MemoryRegion *system_memory,
if (pci_enabled) {
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq,
- system_memory, system_io, ram_size);
+ system_memory, system_io, ram_size,
+ below_4g_mem_size,
+ 0x100000000ULL - below_4g_mem_size,
+ 0x100000000ULL + above_4g_mem_size,
+ (sizeof(target_phys_addr_t) == 4
+ ? 0
+ : ((uint64_t)1 << 62)),
+ pci_memory, ram_memory);
} else {
pci_bus = NULL;
i440fx_state = NULL;
@@ -202,10 +217,6 @@ static void pc_init1(MemoryRegion *system_memory,
smbus_eeprom_init(smbus, 8, NULL, 0);
}
- if (i440fx_state) {
- i440fx_init_memory_mappings(i440fx_state);
- }
-
if (pci_enabled) {
pc_pci_device_init(pci_bus);
}
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 28a3ee2..c563c6e 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -66,10 +66,22 @@ typedef struct PIIX3State {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
} PIIX3State;
+typedef struct PAMMemoryRegion {
+ MemoryRegion mem;
+ bool initialized;
+} PAMMemoryRegion;
+
struct PCII440FXState {
PCIDevice dev;
- target_phys_addr_t isa_page_descs[384 / 4];
+ MemoryRegion *system_memory;
+ MemoryRegion *pci_address_space;
+ MemoryRegion *ram_memory;
+ MemoryRegion pci_hole;
+ MemoryRegion pci_hole_64bit;
+ PAMMemoryRegion pam_regions[13];
+ MemoryRegion smram_region;
uint8_t smm_enabled;
+ bool smram_enabled;
PIIX3State *piix3;
};
@@ -92,50 +104,62 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
return (pci_intx + slot_addend) & 3;
}
-static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
+static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
+ PAMMemoryRegion *mem)
{
- uint32_t addr;
+ if (mem->initialized) {
+ memory_region_del_subregion(d->system_memory, &mem->mem);
+ memory_region_destroy(&mem->mem);
+ }
// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
switch(r) {
case 3:
/* RAM */
- cpu_register_physical_memory(start, end - start,
- start);
+ memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
+ start, end - start);
break;
case 1:
/* ROM (XXX: not quite correct) */
- cpu_register_physical_memory(start, end - start,
- start | IO_MEM_ROM);
+ memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
+ start, end - start);
+ memory_region_set_readonly(&mem->mem, true);
break;
case 2:
case 0:
/* XXX: should distinguish read/write cases */
- for(addr = start; addr < end; addr += 4096) {
- cpu_register_physical_memory(addr, 4096,
- d->isa_page_descs[(addr - 0xa0000) >> 12]);
- }
+ memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
+ start, end - start);
break;
}
+ memory_region_add_subregion_overlap(d->system_memory,
+ start, &mem->mem, 1);
+ mem->initialized = true;
}
static void i440fx_update_memory_mappings(PCII440FXState *d)
{
int i, r;
- uint32_t smram, addr;
+ uint32_t smram;
- update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
+ update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
+ &d->pam_regions[0]);
for(i = 0; i < 12; i++) {
r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
- update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
+ update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
+ &d->pam_regions[i+1]);
}
smram = d->dev.config[I440FX_SMRAM];
if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
- cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
+ if (!d->smram_enabled) {
+ memory_region_del_subregion(d->system_memory, &d->smram_region);
+ d->smram_enabled = true;
+ }
} else {
- for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
- cpu_register_physical_memory(addr, 4096,
- d->isa_page_descs[(addr - 0xa0000) >> 12]);
+ if (d->smram_enabled) {
+ memory_region_add_subregion_overlap(d->system_memory, 0xa0000,
+ &d->smram_region, 1);
+ d->smram_enabled = false;
}
}
}
@@ -152,17 +176,6 @@ static void i440fx_set_smm(int val, void *arg)
}
-/* XXX: suppress when better memory API. We make the assumption that
- no device (in particular the VGA) changes the memory mappings in
- the 0xa0000-0x100000 range */
-void i440fx_init_memory_mappings(PCII440FXState *d)
-{
- int i;
- for(i = 0; i < 96; i++) {
- d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
- }
-}
-
static void i440fx_write_config(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
@@ -244,24 +257,48 @@ static PCIBus *i440fx_common_init(const char *device_name,
qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
- ram_addr_t ram_size)
+ ram_addr_t ram_size,
+ target_phys_addr_t pci_hole_start,
+ target_phys_addr_t pci_hole_size,
+ target_phys_addr_t pci_hole64_start,
+ target_phys_addr_t pci_hole64_size,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *ram_memory)
{
DeviceState *dev;
PCIBus *b;
PCIDevice *d;
I440FXState *s;
PIIX3State *piix3;
+ PCII440FXState *f;
dev = qdev_create(NULL, "i440FX-pcihost");
s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
s->address_space = address_space_mem;
- b = pci_bus_new(&s->busdev.qdev, NULL, s->address_space,
+ b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
address_space_io, 0);
s->bus = b;
qdev_init_nofail(dev);
d = pci_create_simple(b, 0, device_name);
*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
+ f = *pi440fx_state;
+ f->system_memory = address_space_mem;
+ f->pci_address_space = pci_address_space;
+ f->ram_memory = ram_memory;
+ memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
+ pci_hole_start, pci_hole_size);
+ memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
+ memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
+ f->pci_address_space,
+ pci_hole64_start, pci_hole64_size);
+ if (pci_hole64_size) {
+ memory_region_add_subregion(f->system_memory, pci_hole64_start,
+ &f->pci_hole_64bit);
+ }
+ memory_region_init_alias(&f->smram_region, "smram-region",
+ f->pci_address_space, 0xa0000, 0x20000);
+ f->smram_enabled = true;
/* Xen supports additional interrupt routes from the PCI devices to
* the IOAPIC: the four pins of each PCI device on the bus are also
@@ -289,6 +326,8 @@ static PCIBus *i440fx_common_init(const char *device_name,
ram_size = 255;
(*pi440fx_state)->dev.config[0x57]=ram_size;
+ i440fx_update_memory_mappings(f);
+
return b;
}
@@ -296,12 +335,21 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
- ram_addr_t ram_size)
+ ram_addr_t ram_size,
+ target_phys_addr_t pci_hole_start,
+ target_phys_addr_t pci_hole_size,
+ target_phys_addr_t pci_hole64_start,
+ target_phys_addr_t pci_hole64_size,
+ MemoryRegion *pci_memory, MemoryRegion *ram_memory)
+
{
PCIBus *b;
b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
- address_space_mem, address_space_io, ram_size);
+ address_space_mem, address_space_io, ram_size,
+ pci_hole_start, pci_hole_size,
+ pci_hole64_size, pci_hole64_size,
+ pci_memory, ram_memory);
return b;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH 24/24] 440fx: fix PAM, PCI holes
@ 2011-08-08 17:07 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-08 17:07 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm
The current implementation of PAM and the PCI holes is broken in several
ways:
- PCI BARs are not restricted to the PCI hole (a BAR may hide memory)
- PCI devices do not respect PAM (if a PCI device maps a region while
PAM maps the region to RAM, the request will be honored)
This patch fixes things by introducing a pci address space, and using
memory region aliases to represent PAM regions, SMRAM, and PCI holes.
The memory hierarchy looks something like
system_memory
|
+--- low memory alias (0-0xe0000000)
| |
| +-- ram@0
|
+--- high memory alias (0x100000000-EOM)
| |
| +-- ram@0xe0000000
|
+--- pci hole alias (end of low memory-0x100000000)
| |
| +-- pci@end-of-low-memory
|
|
+--- pam[n] (0xc0000-0xc3fff etc) (when set to pci, priority 1)
| |
| +-- pci@0xc4000 etc
|
+--- smram (0xa0000-0xbffff) (when set to pci/vga, priority 1)
|
+-- pci@0xa0000 etc
ram (simple ram region)
pci
|
+--- BARn
|
+--- VGA 0xa0000-0xbffff
|
+--- ROMs
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/pc.c | 11 +++--
hw/pc.h | 13 +++++-
hw/pc_piix.c | 23 ++++++++---
hw/piix_pci.c | 114 ++++++++++++++++++++++++++++++++++++++++----------------
4 files changed, 115 insertions(+), 46 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index f43d181..d328304 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -964,7 +964,9 @@ void pc_memory_init(MemoryRegion *system_memory,
const char *kernel_cmdline,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size)
+ ram_addr_t above_4g_mem_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion **ram_memory)
{
char *filename;
int ret, linux_boot, i;
@@ -982,6 +984,7 @@ void pc_memory_init(MemoryRegion *system_memory,
ram = qemu_malloc(sizeof(*ram));
memory_region_init_ram(ram, NULL, "pc.ram",
below_4g_mem_size + above_4g_mem_size);
+ *ram_memory = ram;
ram_below_4g = qemu_malloc(sizeof(*ram_below_4g));
memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
0, below_4g_mem_size);
@@ -1026,7 +1029,7 @@ void pc_memory_init(MemoryRegion *system_memory,
isa_bios = qemu_malloc(sizeof(*isa_bios));
memory_region_init_alias(isa_bios, "isa-bios", bios,
bios_size - isa_bios_size, isa_bios_size);
- memory_region_add_subregion_overlap(system_memory,
+ memory_region_add_subregion_overlap(pci_memory,
0x100000 - isa_bios_size,
isa_bios,
1);
@@ -1034,13 +1037,13 @@ void pc_memory_init(MemoryRegion *system_memory,
option_rom_mr = qemu_malloc(sizeof(*option_rom_mr));
memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
- memory_region_add_subregion_overlap(system_memory,
+ memory_region_add_subregion_overlap(pci_memory,
PC_ROM_MIN_VGA,
option_rom_mr,
1);
/* map all the bios at the top of memory */
- memory_region_add_subregion(system_memory,
+ memory_region_add_subregion(pci_memory,
(uint32_t)(-bios_size),
bios);
diff --git a/hw/pc.h b/hw/pc.h
index d871fd8..dae736e 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -136,7 +136,9 @@ void pc_memory_init(MemoryRegion *system_memory,
const char *kernel_cmdline,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size);
+ ram_addr_t above_4g_mem_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion **ram_memory);
qemu_irq *pc_allocate_cpu_irq(void);
void pc_vga_init(PCIBus *pci_bus);
void pc_basic_device_init(qemu_irq *isa_irq,
@@ -182,8 +184,13 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
- ram_addr_t ram_size);
-void i440fx_init_memory_mappings(PCII440FXState *d);
+ ram_addr_t ram_size,
+ target_phys_addr_t pci_hole_start,
+ target_phys_addr_t pci_hole_size,
+ target_phys_addr_t pci_hole64_start,
+ target_phys_addr_t pci_hole64_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion *ram_memory);
/* piix4.c */
extern PCIDevice *piix4_dev;
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 7dd5008..ee404d9 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -22,6 +22,8 @@
* THE SOFTWARE.
*/
+#include <glib.h>
+
#include "hw.h"
#include "pc.h"
#include "apic.h"
@@ -93,6 +95,8 @@ static void pc_init1(MemoryRegion *system_memory,
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
+ MemoryRegion *ram_memory;
+ MemoryRegion *pci_memory;
pc_cpus_init(cpu_model);
@@ -108,11 +112,15 @@ static void pc_init1(MemoryRegion *system_memory,
below_4g_mem_size = ram_size;
}
+ pci_memory = g_new(MemoryRegion, 1);
+ memory_region_init(pci_memory, "pci", INT64_MAX);
+
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
pc_memory_init(system_memory,
kernel_filename, kernel_cmdline, initrd_filename,
- below_4g_mem_size, above_4g_mem_size);
+ below_4g_mem_size, above_4g_mem_size,
+ pci_memory, &ram_memory);
}
if (!xen_enabled()) {
@@ -130,7 +138,14 @@ static void pc_init1(MemoryRegion *system_memory,
if (pci_enabled) {
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq,
- system_memory, system_io, ram_size);
+ system_memory, system_io, ram_size,
+ below_4g_mem_size,
+ 0x100000000ULL - below_4g_mem_size,
+ 0x100000000ULL + above_4g_mem_size,
+ (sizeof(target_phys_addr_t) == 4
+ ? 0
+ : ((uint64_t)1 << 62)),
+ pci_memory, ram_memory);
} else {
pci_bus = NULL;
i440fx_state = NULL;
@@ -202,10 +217,6 @@ static void pc_init1(MemoryRegion *system_memory,
smbus_eeprom_init(smbus, 8, NULL, 0);
}
- if (i440fx_state) {
- i440fx_init_memory_mappings(i440fx_state);
- }
-
if (pci_enabled) {
pc_pci_device_init(pci_bus);
}
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 28a3ee2..c563c6e 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -66,10 +66,22 @@ typedef struct PIIX3State {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
} PIIX3State;
+typedef struct PAMMemoryRegion {
+ MemoryRegion mem;
+ bool initialized;
+} PAMMemoryRegion;
+
struct PCII440FXState {
PCIDevice dev;
- target_phys_addr_t isa_page_descs[384 / 4];
+ MemoryRegion *system_memory;
+ MemoryRegion *pci_address_space;
+ MemoryRegion *ram_memory;
+ MemoryRegion pci_hole;
+ MemoryRegion pci_hole_64bit;
+ PAMMemoryRegion pam_regions[13];
+ MemoryRegion smram_region;
uint8_t smm_enabled;
+ bool smram_enabled;
PIIX3State *piix3;
};
@@ -92,50 +104,62 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
return (pci_intx + slot_addend) & 3;
}
-static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
+static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
+ PAMMemoryRegion *mem)
{
- uint32_t addr;
+ if (mem->initialized) {
+ memory_region_del_subregion(d->system_memory, &mem->mem);
+ memory_region_destroy(&mem->mem);
+ }
// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
switch(r) {
case 3:
/* RAM */
- cpu_register_physical_memory(start, end - start,
- start);
+ memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
+ start, end - start);
break;
case 1:
/* ROM (XXX: not quite correct) */
- cpu_register_physical_memory(start, end - start,
- start | IO_MEM_ROM);
+ memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
+ start, end - start);
+ memory_region_set_readonly(&mem->mem, true);
break;
case 2:
case 0:
/* XXX: should distinguish read/write cases */
- for(addr = start; addr < end; addr += 4096) {
- cpu_register_physical_memory(addr, 4096,
- d->isa_page_descs[(addr - 0xa0000) >> 12]);
- }
+ memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
+ start, end - start);
break;
}
+ memory_region_add_subregion_overlap(d->system_memory,
+ start, &mem->mem, 1);
+ mem->initialized = true;
}
static void i440fx_update_memory_mappings(PCII440FXState *d)
{
int i, r;
- uint32_t smram, addr;
+ uint32_t smram;
- update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
+ update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
+ &d->pam_regions[0]);
for(i = 0; i < 12; i++) {
r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
- update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
+ update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
+ &d->pam_regions[i+1]);
}
smram = d->dev.config[I440FX_SMRAM];
if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
- cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
+ if (!d->smram_enabled) {
+ memory_region_del_subregion(d->system_memory, &d->smram_region);
+ d->smram_enabled = true;
+ }
} else {
- for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
- cpu_register_physical_memory(addr, 4096,
- d->isa_page_descs[(addr - 0xa0000) >> 12]);
+ if (d->smram_enabled) {
+ memory_region_add_subregion_overlap(d->system_memory, 0xa0000,
+ &d->smram_region, 1);
+ d->smram_enabled = false;
}
}
}
@@ -152,17 +176,6 @@ static void i440fx_set_smm(int val, void *arg)
}
-/* XXX: suppress when better memory API. We make the assumption that
- no device (in particular the VGA) changes the memory mappings in
- the 0xa0000-0x100000 range */
-void i440fx_init_memory_mappings(PCII440FXState *d)
-{
- int i;
- for(i = 0; i < 96; i++) {
- d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
- }
-}
-
static void i440fx_write_config(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
@@ -244,24 +257,48 @@ static PCIBus *i440fx_common_init(const char *device_name,
qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
- ram_addr_t ram_size)
+ ram_addr_t ram_size,
+ target_phys_addr_t pci_hole_start,
+ target_phys_addr_t pci_hole_size,
+ target_phys_addr_t pci_hole64_start,
+ target_phys_addr_t pci_hole64_size,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *ram_memory)
{
DeviceState *dev;
PCIBus *b;
PCIDevice *d;
I440FXState *s;
PIIX3State *piix3;
+ PCII440FXState *f;
dev = qdev_create(NULL, "i440FX-pcihost");
s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
s->address_space = address_space_mem;
- b = pci_bus_new(&s->busdev.qdev, NULL, s->address_space,
+ b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
address_space_io, 0);
s->bus = b;
qdev_init_nofail(dev);
d = pci_create_simple(b, 0, device_name);
*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
+ f = *pi440fx_state;
+ f->system_memory = address_space_mem;
+ f->pci_address_space = pci_address_space;
+ f->ram_memory = ram_memory;
+ memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
+ pci_hole_start, pci_hole_size);
+ memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
+ memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
+ f->pci_address_space,
+ pci_hole64_start, pci_hole64_size);
+ if (pci_hole64_size) {
+ memory_region_add_subregion(f->system_memory, pci_hole64_start,
+ &f->pci_hole_64bit);
+ }
+ memory_region_init_alias(&f->smram_region, "smram-region",
+ f->pci_address_space, 0xa0000, 0x20000);
+ f->smram_enabled = true;
/* Xen supports additional interrupt routes from the PCI devices to
* the IOAPIC: the four pins of each PCI device on the bus are also
@@ -289,6 +326,8 @@ static PCIBus *i440fx_common_init(const char *device_name,
ram_size = 255;
(*pi440fx_state)->dev.config[0x57]=ram_size;
+ i440fx_update_memory_mappings(f);
+
return b;
}
@@ -296,12 +335,21 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
- ram_addr_t ram_size)
+ ram_addr_t ram_size,
+ target_phys_addr_t pci_hole_start,
+ target_phys_addr_t pci_hole_size,
+ target_phys_addr_t pci_hole64_start,
+ target_phys_addr_t pci_hole64_size,
+ MemoryRegion *pci_memory, MemoryRegion *ram_memory)
+
{
PCIBus *b;
b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
- address_space_mem, address_space_io, ram_size);
+ address_space_mem, address_space_io, ram_size,
+ pci_hole_start, pci_hole_size,
+ pci_hole64_size, pci_hole64_size,
+ pci_memory, ram_memory);
return b;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
(?)
@ 2011-08-08 17:43 ` Peter Maydell
2011-08-09 6:34 ` Avi Kivity
-1 siblings, 1 reply; 90+ messages in thread
From: Peter Maydell @ 2011-08-08 17:43 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 8 August 2011 18:06, Avi Kivity <avi@redhat.com> wrote:
> Somewhat clumsy since it needs a variable sized region.
> @@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
> struct omap_gpmc_s;
> struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
> void omap_gpmc_reset(struct omap_gpmc_s *s);
> -void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
> +void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
> void (*base_upd)(void *opaque, target_phys_addr_t new),
> void (*unmap)(void *opaque), void *opaque);
I have a pile of omap_gpmc patches almost ready to submit which
are mostly waiting on my figuring out how to get them to work
with the new memory API.
In particular I think this is wrong -- omap_gpmc_attach should
just take a MemoryRegion*, and there should be standard APIs
for "resize this memory region" and "unmap this memory region",
[we have the latter but not the former currently], at which point
there's no need to pass in base_upd or unmap function pointers.
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-08 17:43 ` Peter Maydell
@ 2011-08-09 6:34 ` Avi Kivity
2011-08-09 7:37 ` Peter Maydell
0 siblings, 1 reply; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 6:34 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/08/2011 08:43 PM, Peter Maydell wrote:
> On 8 August 2011 18:06, Avi Kivity<avi@redhat.com> wrote:
> > Somewhat clumsy since it needs a variable sized region.
>
> > @@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
> > struct omap_gpmc_s;
> > struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
> > void omap_gpmc_reset(struct omap_gpmc_s *s);
> > -void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
> > +void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
> > void (*base_upd)(void *opaque, target_phys_addr_t new),
> > void (*unmap)(void *opaque), void *opaque);
>
> I have a pile of omap_gpmc patches almost ready to submit which
> are mostly waiting on my figuring out how to get them to work
> with the new memory API.
>
> In particular I think this is wrong -- omap_gpmc_attach should
> just take a MemoryRegion*, and there should be standard APIs
> for "resize this memory region" and "unmap this memory region",
> [we have the latter but not the former currently], at which point
> there's no need to pass in base_upd or unmap function pointers.
>
I agree we need better support for this in the core. But I'm limiting
core updates so I can continue to convert users, without which the
entire effort is useless, and so I can collect additional requirements.
Also, my patchset focuses on mechanical transformations. It is already
risky enough in terms of regressions, I'm not going to rewrite/improve
all of qemu; if you want those callbacks removed, you will have to
remove them yourself.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 6:34 ` Avi Kivity
@ 2011-08-09 7:37 ` Peter Maydell
2011-08-09 7:41 ` Avi Kivity
0 siblings, 1 reply; 90+ messages in thread
From: Peter Maydell @ 2011-08-09 7:37 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 9 August 2011 07:34, Avi Kivity <avi@redhat.com> wrote:
> Also, my patchset focuses on mechanical transformations. It is already
> risky enough in terms of regressions, I'm not going to rewrite/improve all
> of qemu; if you want those callbacks removed, you will have to remove them
> yourself.
Sure. Can I ask you to drop this one and the onenand patch, and I'll
have a go over the next week or three at incorporating a conversion into
the patchset I have for those?
Thanks
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 7:37 ` Peter Maydell
@ 2011-08-09 7:41 ` Avi Kivity
2011-08-09 8:07 ` Peter Maydell
0 siblings, 1 reply; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 7:41 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/09/2011 10:37 AM, Peter Maydell wrote:
> On 9 August 2011 07:34, Avi Kivity<avi@redhat.com> wrote:
> > Also, my patchset focuses on mechanical transformations. It is already
> > risky enough in terms of regressions, I'm not going to rewrite/improve all
> > of qemu; if you want those callbacks removed, you will have to remove them
> > yourself.
>
> Sure. Can I ask you to drop this one and the onenand patch, and I'll
> have a go over the next week or three at incorporating a conversion into
> the patchset I have for those?
>
Umm... next week or three? I'd like to move fast on this.
Can't you base your patches on this instead? After all, this is just a
mechanical transformation, there should be no functional change.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH 08/24] tusb6010: move declarations to new file tusb6010.h
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
@ 2011-08-09 7:51 ` Peter Maydell
-1 siblings, 0 replies; 90+ messages in thread
From: Peter Maydell @ 2011-08-09 7:51 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 8 August 2011 18:06, Avi Kivity <avi@redhat.com> wrote:
> diff --git a/hw/tusb6010.h b/hw/tusb6010.h
> new file mode 100644
> index 0000000..6faa94d
> --- /dev/null
> +++ b/hw/tusb6010.h
> @@ -0,0 +1,10 @@
> +#ifndef TUSB6010_H
> +#define TUSB6010_H
> +
> +typedef struct TUSBState TUSBState;
> +TUSBState *tusb6010_init(qemu_irq intr);
> +int tusb6010_sync_io(TUSBState *s);
> +int tusb6010_async_io(TUSBState *s);
> +void tusb6010_power(TUSBState *s, int on);
> +
> +#endif
New files should have a copyright/license boilerplate comment.
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 08/24] tusb6010: move declarations to new file tusb6010.h
@ 2011-08-09 7:51 ` Peter Maydell
0 siblings, 0 replies; 90+ messages in thread
From: Peter Maydell @ 2011-08-09 7:51 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 8 August 2011 18:06, Avi Kivity <avi@redhat.com> wrote:
> diff --git a/hw/tusb6010.h b/hw/tusb6010.h
> new file mode 100644
> index 0000000..6faa94d
> --- /dev/null
> +++ b/hw/tusb6010.h
> @@ -0,0 +1,10 @@
> +#ifndef TUSB6010_H
> +#define TUSB6010_H
> +
> +typedef struct TUSBState TUSBState;
> +TUSBState *tusb6010_init(qemu_irq intr);
> +int tusb6010_sync_io(TUSBState *s);
> +int tusb6010_async_io(TUSBState *s);
> +void tusb6010_power(TUSBState *s, int on);
> +
> +#endif
New files should have a copyright/license boilerplate comment.
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 7:41 ` Avi Kivity
@ 2011-08-09 8:07 ` Peter Maydell
2011-08-09 8:44 ` Avi Kivity
0 siblings, 1 reply; 90+ messages in thread
From: Peter Maydell @ 2011-08-09 8:07 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 9 August 2011 08:41, Avi Kivity <avi@redhat.com> wrote:
> On 08/09/2011 10:37 AM, Peter Maydell wrote:
>>
>> On 9 August 2011 07:34, Avi Kivity<avi@redhat.com> wrote:
>> > Also, my patchset focuses on mechanical transformations. It is already
>> > risky enough in terms of regressions, I'm not going to rewrite/improve
>> > all
>> > of qemu; if you want those callbacks removed, you will have to remove
>> > them
>> > yourself.
>>
>> Sure. Can I ask you to drop this one and the onenand patch, and I'll
>> have a go over the next week or three at incorporating a conversion into
>> the patchset I have for those?
> Umm... next week or three? I'd like to move fast on this.
I'm busy at least half of this week, and next week is the KVM
Forum, so I didn't want to promise anything faster.
> Can't you base your patches on this instead? After all, this is just a
> mechanical transformation, there should be no functional change.
Well, maybe, but it seems a bit silly to commit something which is
going to be half-reverted and rewritten.
Also I just noticed this change:
-static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
- omap_badwidth_read32, /* TODO */
- omap_badwidth_read32, /* TODO */
- omap_gpmc_read,
-};
-
-static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
- omap_badwidth_write32, /* TODO */
- omap_badwidth_write32, /* TODO */
- omap_gpmc_write,
+static const MemoryRegionOps omap_gpmc_ops = {
+ /* TODO: specialize <4 byte writes? */
+ .read = omap_gpmc_read,
+ .write = omap_gpmc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
...isn't this just throwing away the warnings on bad-width accesses?
(it's not clear to me from the docs what the behaviour of the new
API on bad-width accesses is going to be.)
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 8:07 ` Peter Maydell
@ 2011-08-09 8:44 ` Avi Kivity
2011-08-09 8:56 ` [Qemu-devel] " Avi Kivity
0 siblings, 1 reply; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 8:44 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/09/2011 11:07 AM, Peter Maydell wrote:
> On 9 August 2011 08:41, Avi Kivity<avi@redhat.com> wrote:
> > On 08/09/2011 10:37 AM, Peter Maydell wrote:
> >>
> >> On 9 August 2011 07:34, Avi Kivity<avi@redhat.com> wrote:
> >> > Also, my patchset focuses on mechanical transformations. It is already
> >> > risky enough in terms of regressions, I'm not going to rewrite/improve
> >> > all
> >> > of qemu; if you want those callbacks removed, you will have to remove
> >> > them
> >> > yourself.
> >>
> >> Sure. Can I ask you to drop this one and the onenand patch, and I'll
> >> have a go over the next week or three at incorporating a conversion into
> >> the patchset I have for those?
>
> > Umm... next week or three? I'd like to move fast on this.
>
> I'm busy at least half of this week, and next week is the KVM
> Forum, so I didn't want to promise anything faster.
>
> > Can't you base your patches on this instead? After all, this is just a
> > mechanical transformation, there should be no functional change.
>
> Well, maybe, but it seems a bit silly to commit something which is
> going to be half-reverted and rewritten.
It certainly won't be reverted, since the ram_addr_t based API will be
removed. So it will just be modified to suit however you want it to
be. If you want it otherwise, post a patch, either on top of this or
instead of it, and I will incorporate it into this patchset.
Again, this is not about improving individual devices (that is left for
device maintainers); it's just about converting to the new API with
minimal changes.
> Also I just noticed this change:
>
> -static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
> - omap_badwidth_read32, /* TODO */
> - omap_badwidth_read32, /* TODO */
> - omap_gpmc_read,
> -};
> -
> -static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
> - omap_badwidth_write32, /* TODO */
> - omap_badwidth_write32, /* TODO */
> - omap_gpmc_write,
> +static const MemoryRegionOps omap_gpmc_ops = {
> + /* TODO: specialize<4 byte writes? */
> + .read = omap_gpmc_read,
> + .write = omap_gpmc_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> ...isn't this just throwing away the warnings on bad-width accesses?
It is; will fix.
> (it's not clear to me from the docs what the behaviour of the new
> API on bad-width accesses is going to be.)
It's one of the things I'm collecting requirements on. So far I think
we'll have an inheritable, configurable policy that allows you to ignore
writes/read ones, raise a machine check exception, or warn (in developer
mode only).
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 8:44 ` Avi Kivity
@ 2011-08-09 8:56 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 8:56 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/09/2011 11:44 AM, Avi Kivity wrote:
>> ...isn't this just throwing away the warnings on bad-width accesses?
>
>
> It is; will fix.
Reading the original code, it seems broken:
uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
OMAP_32B_REG(addr);
cpu_physical_memory_read(addr, (void *) &ret, 4);
return ret;
}
The code issues a read from addr, but that is not the original address
used by the guest, since addresses are relative to the start of the
region (in both the old and new APIs), not to physical address start.
So I'll just set access size validity in the new code.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
@ 2011-08-09 8:56 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 8:56 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/09/2011 11:44 AM, Avi Kivity wrote:
>> ...isn't this just throwing away the warnings on bad-width accesses?
>
>
> It is; will fix.
Reading the original code, it seems broken:
uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
OMAP_32B_REG(addr);
cpu_physical_memory_read(addr, (void *) &ret, 4);
return ret;
}
The code issues a read from addr, but that is not the original address
used by the guest, since addresses are relative to the start of the
region (in both the old and new APIs), not to physical address start.
So I'll just set access size validity in the new code.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v1.1 08/24] tusb6010: move declarations to new file tusb6010.h
2011-08-09 7:51 ` [Qemu-devel] " Peter Maydell
@ 2011-08-09 9:02 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 9:02 UTC (permalink / raw)
To: qemu-devel, Peter Maydell; +Cc: kvm
Avoid #include hell.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
v1.1: add copyright/license blurb
hw/devices.h | 7 -------
hw/nseries.c | 1 +
hw/tusb6010.c | 2 +-
hw/tusb6010.h | 25 +++++++++++++++++++++++++
4 files changed, 27 insertions(+), 8 deletions(-)
create mode 100644 hw/tusb6010.h
diff --git a/hw/devices.h b/hw/devices.h
index c788373..07fda83 100644
--- a/hw/devices.h
+++ b/hw/devices.h
@@ -47,13 +47,6 @@ void *tahvo_init(qemu_irq irq, int betty);
void retu_key_event(void *retu, int state);
-/* tusb6010.c */
-typedef struct TUSBState TUSBState;
-TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
-void tusb6010_power(TUSBState *s, int on);
-
/* tc6393xb.c */
typedef struct TC6393xbState TC6393xbState;
#define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */
diff --git a/hw/nseries.c b/hw/nseries.c
index 6a5575e..5521f28 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -32,6 +32,7 @@
#include "bt.h"
#include "loader.h"
#include "blockdev.h"
+#include "tusb6010.h"
/* Nokia N8x0 support */
struct n800_s {
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index ccd01ad..add748c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -23,7 +23,7 @@
#include "usb.h"
#include "omap.h"
#include "irq.h"
-#include "devices.h"
+#include "tusb6010.h"
struct TUSBState {
int iomemtype[2];
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
new file mode 100644
index 0000000..ebb3584
--- /dev/null
+++ b/hw/tusb6010.h
@@ -0,0 +1,25 @@
+/*
+ * tusb6010 interfaces
+ *
+ * Copyright 2011 Red Hat, Inc. and/or its affiliates
+ *
+ * Authors:
+ * Avi Kivity <avi@redhat.com>
+ *
+ * Derived from hw/devices.h.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef TUSB6010_H
+#define TUSB6010_H
+
+typedef struct TUSBState TUSBState;
+TUSBState *tusb6010_init(qemu_irq intr);
+int tusb6010_sync_io(TUSBState *s);
+int tusb6010_async_io(TUSBState *s);
+void tusb6010_power(TUSBState *s, int on);
+
+#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v1.1 08/24] tusb6010: move declarations to new file tusb6010.h
@ 2011-08-09 9:02 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 9:02 UTC (permalink / raw)
To: qemu-devel, Peter Maydell; +Cc: kvm
Avoid #include hell.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
v1.1: add copyright/license blurb
hw/devices.h | 7 -------
hw/nseries.c | 1 +
hw/tusb6010.c | 2 +-
hw/tusb6010.h | 25 +++++++++++++++++++++++++
4 files changed, 27 insertions(+), 8 deletions(-)
create mode 100644 hw/tusb6010.h
diff --git a/hw/devices.h b/hw/devices.h
index c788373..07fda83 100644
--- a/hw/devices.h
+++ b/hw/devices.h
@@ -47,13 +47,6 @@ void *tahvo_init(qemu_irq irq, int betty);
void retu_key_event(void *retu, int state);
-/* tusb6010.c */
-typedef struct TUSBState TUSBState;
-TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
-void tusb6010_power(TUSBState *s, int on);
-
/* tc6393xb.c */
typedef struct TC6393xbState TC6393xbState;
#define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */
diff --git a/hw/nseries.c b/hw/nseries.c
index 6a5575e..5521f28 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -32,6 +32,7 @@
#include "bt.h"
#include "loader.h"
#include "blockdev.h"
+#include "tusb6010.h"
/* Nokia N8x0 support */
struct n800_s {
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index ccd01ad..add748c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -23,7 +23,7 @@
#include "usb.h"
#include "omap.h"
#include "irq.h"
-#include "devices.h"
+#include "tusb6010.h"
struct TUSBState {
int iomemtype[2];
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
new file mode 100644
index 0000000..ebb3584
--- /dev/null
+++ b/hw/tusb6010.h
@@ -0,0 +1,25 @@
+/*
+ * tusb6010 interfaces
+ *
+ * Copyright 2011 Red Hat, Inc. and/or its affiliates
+ *
+ * Authors:
+ * Avi Kivity <avi@redhat.com>
+ *
+ * Derived from hw/devices.h.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef TUSB6010_H
+#define TUSB6010_H
+
+typedef struct TUSBState TUSBState;
+TUSBState *tusb6010_init(qemu_irq intr);
+int tusb6010_sync_io(TUSBState *s);
+int tusb6010_async_io(TUSBState *s);
+void tusb6010_power(TUSBState *s, int on);
+
+#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH v1.1 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 8:56 ` [Qemu-devel] " Avi Kivity
@ 2011-08-09 9:02 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 9:02 UTC (permalink / raw)
To: qemu-devel, Peter Maydell; +Cc: kvm
Somewhat clumsy since it needs a variable sized region.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
v1.1: set access size validity for omap gpmc region to allow only 32-bit
accesses
hw/omap.h | 3 ++-
hw/omap_gpmc.c | 56 ++++++++++++++++++++++++++++++++------------------------
hw/tusb6010.c | 30 +++++++++++++-----------------
hw/tusb6010.h | 7 +++++--
4 files changed, 52 insertions(+), 44 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index a064353..c2fe54c 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -17,6 +17,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef hw_omap_h
+#include "memory.h"
# define hw_omap_h "omap.h"
# define OMAP_EMIFS_BASE 0x00000000
@@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
void omap_gpmc_reset(struct omap_gpmc_s *s);
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque);
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
index 8bf3343..19e0865 100644
--- a/hw/omap_gpmc.c
+++ b/hw/omap_gpmc.c
@@ -21,10 +21,13 @@
#include "hw.h"
#include "flash.h"
#include "omap.h"
+#include "memory.h"
+#include "exec-memory.h"
/* General-Purpose Memory Controller */
struct omap_gpmc_s {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t sysconfig;
uint16_t irqst;
@@ -39,7 +42,8 @@ struct omap_gpmc_s {
uint32_t config[7];
target_phys_addr_t base;
size_t size;
- int iomemtype;
+ MemoryRegion *iomem;
+ MemoryRegion container;
void (*base_update)(void *opaque, target_phys_addr_t new);
void (*unmap)(void *opaque);
void *opaque;
@@ -75,8 +79,12 @@ static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
* constant), the mask should cause wrapping of the address space, so
* that the same memory becomes accessible at every <i>size</i> bytes
* starting from <i>base</i>. */
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, f->iomemtype);
+ if (f->iomem) {
+ memory_region_init(&f->container, "omap-gpmc-file", f->size);
+ memory_region_add_subregion(&f->container, 0, f->iomem);
+ memory_region_add_subregion(get_system_memory(), f->base,
+ &f->container);
+ }
if (f->base_update)
f->base_update(f->opaque, f->base);
@@ -87,8 +95,11 @@ static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
if (f->size) {
if (f->unmap)
f->unmap(f->opaque);
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
+ if (f->iomem) {
+ memory_region_del_subregion(get_system_memory(), &f->container);
+ memory_region_del_subregion(&f->container, f->iomem);
+ memory_region_destroy(&f->container);
+ }
f->base = 0;
f->size = 0;
}
@@ -132,7 +143,8 @@ void omap_gpmc_reset(struct omap_gpmc_s *s)
ecc_reset(&s->ecc[i]);
}
-static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
@@ -230,7 +242,7 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
@@ -249,7 +261,7 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
case 0x010: /* GPMC_SYSCONFIG */
if ((value >> 3) == 0x3)
- fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
+ fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
__FUNCTION__, value >> 3);
if (value & 2)
omap_gpmc_reset(s);
@@ -369,34 +381,30 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
- omap_badwidth_read32, /* TODO */
- omap_badwidth_read32, /* TODO */
- omap_gpmc_read,
-};
-
-static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
- omap_badwidth_write32, /* TODO */
- omap_badwidth_write32, /* TODO */
- omap_gpmc_write,
+static const MemoryRegionOps omap_gpmc_ops = {
+ .read = omap_gpmc_read,
+ .write = omap_gpmc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
{
- int iomemtype;
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
qemu_mallocz(sizeof(struct omap_gpmc_s));
omap_gpmc_reset(s);
- iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
- omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
+ memory_region_add_subregion(get_system_memory(), base, &s->iomem);
return s;
}
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque)
{
@@ -408,7 +416,7 @@ void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
}
f = &s->cs_file[cs];
- f->iomemtype = iomemtype;
+ f->iomem = iomem;
f->base_update = base_upd;
f->unmap = unmap;
f->opaque = opaque;
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index add748c..28ff52c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -26,7 +26,7 @@
#include "tusb6010.h"
struct TUSBState {
- int iomemtype[2];
+ MemoryRegion iomem[2];
qemu_irq irq;
MUSBState *musb;
QEMUTimer *otg_timer;
@@ -234,14 +234,14 @@ struct TUSBState {
#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
#define TUSB_PROD_TEST_RESET_VAL 0xa596
-int tusb6010_sync_io(TUSBState *s)
+MemoryRegion *tusb6010_sync_io(TUSBState *s)
{
- return s->iomemtype[0];
+ return &s->iomem[0];
}
-int tusb6010_async_io(TUSBState *s)
+MemoryRegion *tusb6010_async_io(TUSBState *s)
{
- return s->iomemtype[1];
+ return &s->iomem[1];
}
static void tusb_intr_update(TUSBState *s)
@@ -647,16 +647,12 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const tusb_async_readfn[] = {
- tusb_async_readb,
- tusb_async_readh,
- tusb_async_readw,
-};
-
-static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
- tusb_async_writeb,
- tusb_async_writeh,
- tusb_async_writew,
+static const MemoryRegionOps tusb_async_ops = {
+ .old_mmio = {
+ .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
+ .write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void tusb_otg_tick(void *opaque)
@@ -739,8 +735,8 @@ TUSBState *tusb6010_init(qemu_irq intr)
s->mask = 0xffffffff;
s->intr = 0x00000000;
s->otg_timer_val = 0;
- s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
- tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async",
+ UINT32_MAX);
s->irq = intr;
s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
index ebb3584..b85ee86 100644
--- a/hw/tusb6010.h
+++ b/hw/tusb6010.h
@@ -16,10 +16,13 @@
#ifndef TUSB6010_H
#define TUSB6010_H
+#include "targphys.h"
+#include "memory.h"
+
typedef struct TUSBState TUSBState;
TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
+MemoryRegion *tusb6010_sync_io(TUSBState *s);
+MemoryRegion *tusb6010_async_io(TUSBState *s);
void tusb6010_power(TUSBState *s, int on);
#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v1.1 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
@ 2011-08-09 9:02 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 9:02 UTC (permalink / raw)
To: qemu-devel, Peter Maydell; +Cc: kvm
Somewhat clumsy since it needs a variable sized region.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
v1.1: set access size validity for omap gpmc region to allow only 32-bit
accesses
hw/omap.h | 3 ++-
hw/omap_gpmc.c | 56 ++++++++++++++++++++++++++++++++------------------------
hw/tusb6010.c | 30 +++++++++++++-----------------
hw/tusb6010.h | 7 +++++--
4 files changed, 52 insertions(+), 44 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index a064353..c2fe54c 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -17,6 +17,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef hw_omap_h
+#include "memory.h"
# define hw_omap_h "omap.h"
# define OMAP_EMIFS_BASE 0x00000000
@@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
void omap_gpmc_reset(struct omap_gpmc_s *s);
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque);
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
index 8bf3343..19e0865 100644
--- a/hw/omap_gpmc.c
+++ b/hw/omap_gpmc.c
@@ -21,10 +21,13 @@
#include "hw.h"
#include "flash.h"
#include "omap.h"
+#include "memory.h"
+#include "exec-memory.h"
/* General-Purpose Memory Controller */
struct omap_gpmc_s {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t sysconfig;
uint16_t irqst;
@@ -39,7 +42,8 @@ struct omap_gpmc_s {
uint32_t config[7];
target_phys_addr_t base;
size_t size;
- int iomemtype;
+ MemoryRegion *iomem;
+ MemoryRegion container;
void (*base_update)(void *opaque, target_phys_addr_t new);
void (*unmap)(void *opaque);
void *opaque;
@@ -75,8 +79,12 @@ static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
* constant), the mask should cause wrapping of the address space, so
* that the same memory becomes accessible at every <i>size</i> bytes
* starting from <i>base</i>. */
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, f->iomemtype);
+ if (f->iomem) {
+ memory_region_init(&f->container, "omap-gpmc-file", f->size);
+ memory_region_add_subregion(&f->container, 0, f->iomem);
+ memory_region_add_subregion(get_system_memory(), f->base,
+ &f->container);
+ }
if (f->base_update)
f->base_update(f->opaque, f->base);
@@ -87,8 +95,11 @@ static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
if (f->size) {
if (f->unmap)
f->unmap(f->opaque);
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
+ if (f->iomem) {
+ memory_region_del_subregion(get_system_memory(), &f->container);
+ memory_region_del_subregion(&f->container, f->iomem);
+ memory_region_destroy(&f->container);
+ }
f->base = 0;
f->size = 0;
}
@@ -132,7 +143,8 @@ void omap_gpmc_reset(struct omap_gpmc_s *s)
ecc_reset(&s->ecc[i]);
}
-static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
@@ -230,7 +242,7 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
@@ -249,7 +261,7 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
case 0x010: /* GPMC_SYSCONFIG */
if ((value >> 3) == 0x3)
- fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
+ fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
__FUNCTION__, value >> 3);
if (value & 2)
omap_gpmc_reset(s);
@@ -369,34 +381,30 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
- omap_badwidth_read32, /* TODO */
- omap_badwidth_read32, /* TODO */
- omap_gpmc_read,
-};
-
-static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
- omap_badwidth_write32, /* TODO */
- omap_badwidth_write32, /* TODO */
- omap_gpmc_write,
+static const MemoryRegionOps omap_gpmc_ops = {
+ .read = omap_gpmc_read,
+ .write = omap_gpmc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
{
- int iomemtype;
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
qemu_mallocz(sizeof(struct omap_gpmc_s));
omap_gpmc_reset(s);
- iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
- omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
+ memory_region_add_subregion(get_system_memory(), base, &s->iomem);
return s;
}
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque)
{
@@ -408,7 +416,7 @@ void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
}
f = &s->cs_file[cs];
- f->iomemtype = iomemtype;
+ f->iomem = iomem;
f->base_update = base_upd;
f->unmap = unmap;
f->opaque = opaque;
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index add748c..28ff52c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -26,7 +26,7 @@
#include "tusb6010.h"
struct TUSBState {
- int iomemtype[2];
+ MemoryRegion iomem[2];
qemu_irq irq;
MUSBState *musb;
QEMUTimer *otg_timer;
@@ -234,14 +234,14 @@ struct TUSBState {
#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
#define TUSB_PROD_TEST_RESET_VAL 0xa596
-int tusb6010_sync_io(TUSBState *s)
+MemoryRegion *tusb6010_sync_io(TUSBState *s)
{
- return s->iomemtype[0];
+ return &s->iomem[0];
}
-int tusb6010_async_io(TUSBState *s)
+MemoryRegion *tusb6010_async_io(TUSBState *s)
{
- return s->iomemtype[1];
+ return &s->iomem[1];
}
static void tusb_intr_update(TUSBState *s)
@@ -647,16 +647,12 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const tusb_async_readfn[] = {
- tusb_async_readb,
- tusb_async_readh,
- tusb_async_readw,
-};
-
-static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
- tusb_async_writeb,
- tusb_async_writeh,
- tusb_async_writew,
+static const MemoryRegionOps tusb_async_ops = {
+ .old_mmio = {
+ .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
+ .write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void tusb_otg_tick(void *opaque)
@@ -739,8 +735,8 @@ TUSBState *tusb6010_init(qemu_irq intr)
s->mask = 0xffffffff;
s->intr = 0x00000000;
s->otg_timer_val = 0;
- s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
- tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async",
+ UINT32_MAX);
s->irq = intr;
s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
index ebb3584..b85ee86 100644
--- a/hw/tusb6010.h
+++ b/hw/tusb6010.h
@@ -16,10 +16,13 @@
#ifndef TUSB6010_H
#define TUSB6010_H
+#include "targphys.h"
+#include "memory.h"
+
typedef struct TUSBState TUSBState;
TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
+MemoryRegion *tusb6010_sync_io(TUSBState *s);
+MemoryRegion *tusb6010_async_io(TUSBState *s);
void tusb6010_power(TUSBState *s, int on);
#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* Re: [PATCH v1.1 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 9:02 ` [Qemu-devel] " Avi Kivity
@ 2011-08-09 9:23 ` Peter Maydell
-1 siblings, 0 replies; 90+ messages in thread
From: Peter Maydell @ 2011-08-09 9:23 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 9 August 2011 10:02, Avi Kivity <avi@redhat.com> wrote:
> +static const MemoryRegionOps omap_gpmc_ops = {
> + .read = omap_gpmc_read,
> + .write = omap_gpmc_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> };
Does this give debug trace output for missized accesses?
That's the main point of the badread/badwrite functions...
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
@ 2011-08-09 9:23 ` Peter Maydell
0 siblings, 0 replies; 90+ messages in thread
From: Peter Maydell @ 2011-08-09 9:23 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 9 August 2011 10:02, Avi Kivity <avi@redhat.com> wrote:
> +static const MemoryRegionOps omap_gpmc_ops = {
> + .read = omap_gpmc_read,
> + .write = omap_gpmc_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> };
Does this give debug trace output for missized accesses?
That's the main point of the badread/badwrite functions...
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH v1.1 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 9:23 ` [Qemu-devel] " Peter Maydell
@ 2011-08-09 9:26 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 9:26 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/09/2011 12:23 PM, Peter Maydell wrote:
> On 9 August 2011 10:02, Avi Kivity<avi@redhat.com> wrote:
> > +static const MemoryRegionOps omap_gpmc_ops = {
> > + .read = omap_gpmc_read,
> > + .write = omap_gpmc_write,
> > + .endianness = DEVICE_NATIVE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 4,
> > + .max_access_size = 4,
> > + },
> > };
>
> Does this give debug trace output for missized accesses?
Only after we implement and configure a debug policy in memory.c
> That's the main point of the badread/badwrite functions...
These are broken now, aren't they?
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
@ 2011-08-09 9:26 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 9:26 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/09/2011 12:23 PM, Peter Maydell wrote:
> On 9 August 2011 10:02, Avi Kivity<avi@redhat.com> wrote:
> > +static const MemoryRegionOps omap_gpmc_ops = {
> > + .read = omap_gpmc_read,
> > + .write = omap_gpmc_write,
> > + .endianness = DEVICE_NATIVE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 4,
> > + .max_access_size = 4,
> > + },
> > };
>
> Does this give debug trace output for missized accesses?
Only after we implement and configure a debug policy in memory.c
> That's the main point of the badread/badwrite functions...
These are broken now, aren't they?
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 9:26 ` [Qemu-devel] " Avi Kivity
(?)
@ 2011-08-09 9:41 ` Peter Maydell
2011-08-09 12:56 ` Avi Kivity
2011-08-09 13:06 ` [Qemu-devel] " Avi Kivity
-1 siblings, 2 replies; 90+ messages in thread
From: Peter Maydell @ 2011-08-09 9:41 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 9 August 2011 10:26, Avi Kivity <avi@redhat.com> wrote:
> On 08/09/2011 12:23 PM, Peter Maydell wrote:
>>
>> On 9 August 2011 10:02, Avi Kivity<avi@redhat.com> wrote:
>> > +static const MemoryRegionOps omap_gpmc_ops = {
>> > + .read = omap_gpmc_read,
>> > + .write = omap_gpmc_write,
>> > + .endianness = DEVICE_NATIVE_ENDIAN,
>> > + .valid = {
>> > + .min_access_size = 4,
>> > + .max_access_size = 4,
>> > + },
>> > };
>>
>> Does this give debug trace output for missized accesses?
>
> Only after we implement and configure a debug policy in memory.c
>
>> That's the main point of the badread/badwrite functions...
>
> These are broken now, aren't they?
They successfully print a message, which as I say is the
main point. The OMAP TRM typically says the behaviour isn't
defined for wrong-size accesses, so guest code doing it is
broken anyhow and so the error in the current implementation
is IMHO not so serious.
I think if (as here) it turns out that we need more functionality
in memory.c then we should be implementing it, not silently
dropping things in the conversion process.
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 9:41 ` Peter Maydell
@ 2011-08-09 12:56 ` Avi Kivity
2011-08-09 13:06 ` [Qemu-devel] " Avi Kivity
1 sibling, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 12:56 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/09/2011 12:41 PM, Peter Maydell wrote:
> On 9 August 2011 10:26, Avi Kivity<avi@redhat.com> wrote:
> > On 08/09/2011 12:23 PM, Peter Maydell wrote:
> >>
> >> On 9 August 2011 10:02, Avi Kivity<avi@redhat.com> wrote:
> >> > +static const MemoryRegionOps omap_gpmc_ops = {
> >> > + .read = omap_gpmc_read,
> >> > + .write = omap_gpmc_write,
> >> > + .endianness = DEVICE_NATIVE_ENDIAN,
> >> > + .valid = {
> >> > + .min_access_size = 4,
> >> > + .max_access_size = 4,
> >> > + },
> >> > };
> >>
> >> Does this give debug trace output for missized accesses?
> >
> > Only after we implement and configure a debug policy in memory.c
> >
> >> That's the main point of the badread/badwrite functions...
> >
> > These are broken now, aren't they?
>
> They successfully print a message, which as I say is the
> main point. The OMAP TRM typically says the behaviour isn't
> defined for wrong-size accesses, so guest code doing it is
> broken anyhow and so the error in the current implementation
> is IMHO not so serious.
>
> I think if (as here) it turns out that we need more functionality
> in memory.c then we should be implementing it, not silently
> dropping things in the conversion process.
>
Okay. I'll update the patch to forward to the badread/badwrite
functions on bad size.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v1.2 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
2011-08-09 9:41 ` Peter Maydell
@ 2011-08-09 13:06 ` Avi Kivity
2011-08-09 13:06 ` [Qemu-devel] " Avi Kivity
1 sibling, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 13:06 UTC (permalink / raw)
To: qemu-devel, Peter Maydell; +Cc: kvm
Somewhat clumsy since it needs a variable sized region.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
v1.2: drop v1.1 changes, instead forward invalid size accesses to original
omap_badwidth_*() functions
v1.1: set access size validity for omap gpmc region to allow only 32-bit
accesses
hw/omap.h | 3 +-
hw/omap_gpmc.c | 60 +++++++++++++++++++++++++++++++++----------------------
hw/tusb6010.c | 30 ++++++++++++---------------
hw/tusb6010.h | 7 ++++-
4 files changed, 56 insertions(+), 44 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index a064353..c2fe54c 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -17,6 +17,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef hw_omap_h
+#include "memory.h"
# define hw_omap_h "omap.h"
# define OMAP_EMIFS_BASE 0x00000000
@@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
void omap_gpmc_reset(struct omap_gpmc_s *s);
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque);
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
index 8bf3343..e137e4a 100644
--- a/hw/omap_gpmc.c
+++ b/hw/omap_gpmc.c
@@ -21,10 +21,13 @@
#include "hw.h"
#include "flash.h"
#include "omap.h"
+#include "memory.h"
+#include "exec-memory.h"
/* General-Purpose Memory Controller */
struct omap_gpmc_s {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t sysconfig;
uint16_t irqst;
@@ -39,7 +42,8 @@ struct omap_gpmc_s {
uint32_t config[7];
target_phys_addr_t base;
size_t size;
- int iomemtype;
+ MemoryRegion *iomem;
+ MemoryRegion container;
void (*base_update)(void *opaque, target_phys_addr_t new);
void (*unmap)(void *opaque);
void *opaque;
@@ -75,8 +79,12 @@ static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
* constant), the mask should cause wrapping of the address space, so
* that the same memory becomes accessible at every <i>size</i> bytes
* starting from <i>base</i>. */
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, f->iomemtype);
+ if (f->iomem) {
+ memory_region_init(&f->container, "omap-gpmc-file", f->size);
+ memory_region_add_subregion(&f->container, 0, f->iomem);
+ memory_region_add_subregion(get_system_memory(), f->base,
+ &f->container);
+ }
if (f->base_update)
f->base_update(f->opaque, f->base);
@@ -87,8 +95,11 @@ static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
if (f->size) {
if (f->unmap)
f->unmap(f->opaque);
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
+ if (f->iomem) {
+ memory_region_del_subregion(get_system_memory(), &f->container);
+ memory_region_del_subregion(&f->container, f->iomem);
+ memory_region_destroy(&f->container);
+ }
f->base = 0;
f->size = 0;
}
@@ -132,12 +143,17 @@ void omap_gpmc_reset(struct omap_gpmc_s *s)
ecc_reset(&s->ecc[i]);
}
-static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
struct omap_gpmc_cs_file_s *f;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x000: /* GPMC_REVISION */
return 0x20;
@@ -230,12 +246,16 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
struct omap_gpmc_cs_file_s *f;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x000: /* GPMC_REVISION */
case 0x014: /* GPMC_SYSSTATUS */
@@ -249,7 +269,7 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
case 0x010: /* GPMC_SYSCONFIG */
if ((value >> 3) == 0x3)
- fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
+ fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
__FUNCTION__, value >> 3);
if (value & 2)
omap_gpmc_reset(s);
@@ -369,34 +389,26 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
- omap_badwidth_read32, /* TODO */
- omap_badwidth_read32, /* TODO */
- omap_gpmc_read,
-};
-
-static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
- omap_badwidth_write32, /* TODO */
- omap_badwidth_write32, /* TODO */
- omap_gpmc_write,
+static const MemoryRegionOps omap_gpmc_ops = {
+ .read = omap_gpmc_read,
+ .write = omap_gpmc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
{
- int iomemtype;
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
qemu_mallocz(sizeof(struct omap_gpmc_s));
omap_gpmc_reset(s);
- iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
- omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
+ memory_region_add_subregion(get_system_memory(), base, &s->iomem);
return s;
}
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque)
{
@@ -408,7 +420,7 @@ void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
}
f = &s->cs_file[cs];
- f->iomemtype = iomemtype;
+ f->iomem = iomem;
f->base_update = base_upd;
f->unmap = unmap;
f->opaque = opaque;
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index add748c..28ff52c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -26,7 +26,7 @@
#include "tusb6010.h"
struct TUSBState {
- int iomemtype[2];
+ MemoryRegion iomem[2];
qemu_irq irq;
MUSBState *musb;
QEMUTimer *otg_timer;
@@ -234,14 +234,14 @@ struct TUSBState {
#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
#define TUSB_PROD_TEST_RESET_VAL 0xa596
-int tusb6010_sync_io(TUSBState *s)
+MemoryRegion *tusb6010_sync_io(TUSBState *s)
{
- return s->iomemtype[0];
+ return &s->iomem[0];
}
-int tusb6010_async_io(TUSBState *s)
+MemoryRegion *tusb6010_async_io(TUSBState *s)
{
- return s->iomemtype[1];
+ return &s->iomem[1];
}
static void tusb_intr_update(TUSBState *s)
@@ -647,16 +647,12 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const tusb_async_readfn[] = {
- tusb_async_readb,
- tusb_async_readh,
- tusb_async_readw,
-};
-
-static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
- tusb_async_writeb,
- tusb_async_writeh,
- tusb_async_writew,
+static const MemoryRegionOps tusb_async_ops = {
+ .old_mmio = {
+ .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
+ .write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void tusb_otg_tick(void *opaque)
@@ -739,8 +735,8 @@ TUSBState *tusb6010_init(qemu_irq intr)
s->mask = 0xffffffff;
s->intr = 0x00000000;
s->otg_timer_val = 0;
- s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
- tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async",
+ UINT32_MAX);
s->irq = intr;
s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
index ebb3584..b85ee86 100644
--- a/hw/tusb6010.h
+++ b/hw/tusb6010.h
@@ -16,10 +16,13 @@
#ifndef TUSB6010_H
#define TUSB6010_H
+#include "targphys.h"
+#include "memory.h"
+
typedef struct TUSBState TUSBState;
TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
+MemoryRegion *tusb6010_sync_io(TUSBState *s);
+MemoryRegion *tusb6010_async_io(TUSBState *s);
void tusb6010_power(TUSBState *s, int on);
#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v1.2 09/24] omap_gpmc/nseries/tusb6010: convert to memory API
@ 2011-08-09 13:06 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-09 13:06 UTC (permalink / raw)
To: qemu-devel, Peter Maydell; +Cc: kvm
Somewhat clumsy since it needs a variable sized region.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
v1.2: drop v1.1 changes, instead forward invalid size accesses to original
omap_badwidth_*() functions
v1.1: set access size validity for omap gpmc region to allow only 32-bit
accesses
hw/omap.h | 3 +-
hw/omap_gpmc.c | 60 +++++++++++++++++++++++++++++++++----------------------
hw/tusb6010.c | 30 ++++++++++++---------------
hw/tusb6010.h | 7 ++++-
4 files changed, 56 insertions(+), 44 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index a064353..c2fe54c 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -17,6 +17,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef hw_omap_h
+#include "memory.h"
# define hw_omap_h "omap.h"
# define OMAP_EMIFS_BASE 0x00000000
@@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
void omap_gpmc_reset(struct omap_gpmc_s *s);
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque);
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
index 8bf3343..e137e4a 100644
--- a/hw/omap_gpmc.c
+++ b/hw/omap_gpmc.c
@@ -21,10 +21,13 @@
#include "hw.h"
#include "flash.h"
#include "omap.h"
+#include "memory.h"
+#include "exec-memory.h"
/* General-Purpose Memory Controller */
struct omap_gpmc_s {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t sysconfig;
uint16_t irqst;
@@ -39,7 +42,8 @@ struct omap_gpmc_s {
uint32_t config[7];
target_phys_addr_t base;
size_t size;
- int iomemtype;
+ MemoryRegion *iomem;
+ MemoryRegion container;
void (*base_update)(void *opaque, target_phys_addr_t new);
void (*unmap)(void *opaque);
void *opaque;
@@ -75,8 +79,12 @@ static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
* constant), the mask should cause wrapping of the address space, so
* that the same memory becomes accessible at every <i>size</i> bytes
* starting from <i>base</i>. */
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, f->iomemtype);
+ if (f->iomem) {
+ memory_region_init(&f->container, "omap-gpmc-file", f->size);
+ memory_region_add_subregion(&f->container, 0, f->iomem);
+ memory_region_add_subregion(get_system_memory(), f->base,
+ &f->container);
+ }
if (f->base_update)
f->base_update(f->opaque, f->base);
@@ -87,8 +95,11 @@ static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
if (f->size) {
if (f->unmap)
f->unmap(f->opaque);
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
+ if (f->iomem) {
+ memory_region_del_subregion(get_system_memory(), &f->container);
+ memory_region_del_subregion(&f->container, f->iomem);
+ memory_region_destroy(&f->container);
+ }
f->base = 0;
f->size = 0;
}
@@ -132,12 +143,17 @@ void omap_gpmc_reset(struct omap_gpmc_s *s)
ecc_reset(&s->ecc[i]);
}
-static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
struct omap_gpmc_cs_file_s *f;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x000: /* GPMC_REVISION */
return 0x20;
@@ -230,12 +246,16 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
struct omap_gpmc_cs_file_s *f;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x000: /* GPMC_REVISION */
case 0x014: /* GPMC_SYSSTATUS */
@@ -249,7 +269,7 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
case 0x010: /* GPMC_SYSCONFIG */
if ((value >> 3) == 0x3)
- fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
+ fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
__FUNCTION__, value >> 3);
if (value & 2)
omap_gpmc_reset(s);
@@ -369,34 +389,26 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
- omap_badwidth_read32, /* TODO */
- omap_badwidth_read32, /* TODO */
- omap_gpmc_read,
-};
-
-static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
- omap_badwidth_write32, /* TODO */
- omap_badwidth_write32, /* TODO */
- omap_gpmc_write,
+static const MemoryRegionOps omap_gpmc_ops = {
+ .read = omap_gpmc_read,
+ .write = omap_gpmc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
{
- int iomemtype;
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
qemu_mallocz(sizeof(struct omap_gpmc_s));
omap_gpmc_reset(s);
- iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
- omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
+ memory_region_add_subregion(get_system_memory(), base, &s->iomem);
return s;
}
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque)
{
@@ -408,7 +420,7 @@ void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
}
f = &s->cs_file[cs];
- f->iomemtype = iomemtype;
+ f->iomem = iomem;
f->base_update = base_upd;
f->unmap = unmap;
f->opaque = opaque;
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index add748c..28ff52c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -26,7 +26,7 @@
#include "tusb6010.h"
struct TUSBState {
- int iomemtype[2];
+ MemoryRegion iomem[2];
qemu_irq irq;
MUSBState *musb;
QEMUTimer *otg_timer;
@@ -234,14 +234,14 @@ struct TUSBState {
#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
#define TUSB_PROD_TEST_RESET_VAL 0xa596
-int tusb6010_sync_io(TUSBState *s)
+MemoryRegion *tusb6010_sync_io(TUSBState *s)
{
- return s->iomemtype[0];
+ return &s->iomem[0];
}
-int tusb6010_async_io(TUSBState *s)
+MemoryRegion *tusb6010_async_io(TUSBState *s)
{
- return s->iomemtype[1];
+ return &s->iomem[1];
}
static void tusb_intr_update(TUSBState *s)
@@ -647,16 +647,12 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const tusb_async_readfn[] = {
- tusb_async_readb,
- tusb_async_readh,
- tusb_async_readw,
-};
-
-static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
- tusb_async_writeb,
- tusb_async_writeh,
- tusb_async_writew,
+static const MemoryRegionOps tusb_async_ops = {
+ .old_mmio = {
+ .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
+ .write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void tusb_otg_tick(void *opaque)
@@ -739,8 +735,8 @@ TUSBState *tusb6010_init(qemu_irq intr)
s->mask = 0xffffffff;
s->intr = 0x00000000;
s->otg_timer_val = 0;
- s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
- tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async",
+ UINT32_MAX);
s->irq = intr;
s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
index ebb3584..b85ee86 100644
--- a/hw/tusb6010.h
+++ b/hw/tusb6010.h
@@ -16,10 +16,13 @@
#ifndef TUSB6010_H
#define TUSB6010_H
+#include "targphys.h"
+#include "memory.h"
+
typedef struct TUSBState TUSBState;
TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
+MemoryRegion *tusb6010_sync_io(TUSBState *s);
+MemoryRegion *tusb6010_async_io(TUSBState *s);
void tusb6010_power(TUSBState *s, int on);
#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 21/24] isa: add isa_address_space()
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
(?)
@ 2011-08-10 16:24 ` Richard Henderson
2011-08-10 16:26 ` Richard Henderson
2011-08-10 16:32 ` Avi Kivity
-1 siblings, 2 replies; 90+ messages in thread
From: Richard Henderson @ 2011-08-10 16:24 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 08/08/2011 10:07 AM, Avi Kivity wrote:
> A helper that returns the address space used by ISA devices. Useful
> for getting rid of isa_mem_base, multiple ISA buses, or ISA buses behind
> bridges.
>
> Signed-off-by: Avi Kivity <avi@redhat.com>
> ---
> hw/isa-bus.c | 6 ++++++
> hw/isa.h | 1 +
> 2 files changed, 7 insertions(+), 0 deletions(-)
>
> diff --git a/hw/isa-bus.c b/hw/isa-bus.c
> index 2765543..1cb497f 100644
> --- a/hw/isa-bus.c
> +++ b/hw/isa-bus.c
> @@ -20,6 +20,7 @@
> #include "monitor.h"
> #include "sysbus.h"
> #include "isa.h"
> +#include "exec-memory.h"
>
> struct ISABus {
> BusState qbus;
> @@ -202,4 +203,9 @@ static char *isabus_get_fw_dev_path(DeviceState *dev)
> return strdup(path);
> }
>
> +MemoryRegion *isa_address_space(ISADevice *dev)
> +{
> + return get_system_memory();
> +}
> +
This does not help get rid of isa_mem_base, as far as I can see.
All this is going to do is the equivalent of isa_mem_base == 0.
Did you have a plan beyond this?
The simplest replacement, as far as I can see, is to replace one
global variable with another:
MemoryRegion *isa_address_space;
Define that this variable *must* be set by any platform that
wants to use ISA. It can be set to the address_space_mem
parameter (i.e. the copy of get_system_memory() that the
platforms receive as a parameter).
For Alpha, I can set this to the sub-region that I pass off to
the PCI subsystem.
For those other non-x86 platforms that currently set isa_mem_base
to a non-zero value, they either re-use an otherwise existing
memory region or create a new sub-region properly placed.
Of course, as far as I can see, this variable is only used by
the VGA devices. Surely we can arrange to pass down some address
space during setup of the VGA?
r~
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 21/24] isa: add isa_address_space()
2011-08-10 16:24 ` Richard Henderson
@ 2011-08-10 16:26 ` Richard Henderson
2011-08-10 16:35 ` Avi Kivity
2011-08-10 18:44 ` Avi Kivity
2011-08-10 16:32 ` Avi Kivity
1 sibling, 2 replies; 90+ messages in thread
From: Richard Henderson @ 2011-08-10 16:26 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 08/10/2011 09:24 AM, Richard Henderson wrote:
> Of course, as far as I can see, this variable is only used by
> the VGA devices. Surely we can arrange to pass down some address
> space during setup of the VGA?
... Which seems to be what you've done in patch 23.
So what's the point of this patch?
r~
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 21/24] isa: add isa_address_space()
2011-08-10 16:24 ` Richard Henderson
2011-08-10 16:26 ` Richard Henderson
@ 2011-08-10 16:32 ` Avi Kivity
1 sibling, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-10 16:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, kvm
On 08/10/2011 07:24 PM, Richard Henderson wrote:
> > @@ -202,4 +203,9 @@ static char *isabus_get_fw_dev_path(DeviceState *dev)
> > return strdup(path);
> > }
> >
> > +MemoryRegion *isa_address_space(ISADevice *dev)
> > +{
> > + return get_system_memory();
> > +}
> > +
>
> This does not help get rid of isa_mem_base, as far as I can see.
> All this is going to do is the equivalent of isa_mem_base == 0.
It abstracts away the problem. We can now have multiple ISA buses, and
each can have its own base, we just need to change the implementation.
> Did you have a plan beyond this?
I'll probably add two MemoryRegion *s to isabus_bridge_init(). The plan
is to eliminate all get_system_memory() calls.
>
> The simplest replacement, as far as I can see, is to replace one
> global variable with another:
>
> MemoryRegion *isa_address_space;
>
> Define that this variable *must* be set by any platform that
> wants to use ISA. It can be set to the address_space_mem
> parameter (i.e. the copy of get_system_memory() that the
> platforms receive as a parameter).
>
> For Alpha, I can set this to the sub-region that I pass off to
> the PCI subsystem.
>
> For those other non-x86 platforms that currently set isa_mem_base
> to a non-zero value, they either re-use an otherwise existing
> memory region or create a new sub-region properly placed.
>
> Of course, as far as I can see, this variable is only used by
> the VGA devices. Surely we can arrange to pass down some address
> space during setup of the VGA?
>
You mean pass VGA's memory regions to ISA, instead of vice versa? Yes,
that's the right thing to do, and is how PCI and sysbus do it.
Because of the huge amount of devices that need to be converted, I'm
giving myself some leeway in the conversion process and introducing some
shortcuts. I don't see a away to do a perfect conversion in a
reasonable time frame, and in any case I'm learning a lot during the
conversion (except that I call it "collecting requirements").
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 21/24] isa: add isa_address_space()
2011-08-10 16:26 ` Richard Henderson
@ 2011-08-10 16:35 ` Avi Kivity
2011-08-10 16:38 ` Avi Kivity
2011-08-10 18:44 ` Avi Kivity
1 sibling, 1 reply; 90+ messages in thread
From: Avi Kivity @ 2011-08-10 16:35 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, kvm
On 08/10/2011 07:26 PM, Richard Henderson wrote:
> On 08/10/2011 09:24 AM, Richard Henderson wrote:
> > Of course, as far as I can see, this variable is only used by
> > the VGA devices. Surely we can arrange to pass down some address
> > space during setup of the VGA?
>
> ... Which seems to be what you've done in patch 23.
>
> So what's the point of this patch?
>
>
Okay, so I'm learning a lot and also applying that learning... a good
thing except that I've forgotten all about it. Had a similar case with
omap_gpmc.
Again, there's so much work here that the quality is bound to be less
than perfect. The plan is to have a pretty good end result though
(fully hierarchical - no globals).
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 21/24] isa: add isa_address_space()
2011-08-10 16:35 ` Avi Kivity
@ 2011-08-10 16:38 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-10 16:38 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, kvm
On 08/10/2011 07:35 PM, Avi Kivity wrote:
> On 08/10/2011 07:26 PM, Richard Henderson wrote:
>> On 08/10/2011 09:24 AM, Richard Henderson wrote:
>> > Of course, as far as I can see, this variable is only used by
>> > the VGA devices. Surely we can arrange to pass down some address
>> > space during setup of the VGA?
>>
>> ... Which seems to be what you've done in patch 23.
>>
>> So what's the point of this patch?
>>
>>
>
> Okay, so I'm learning a lot and also applying that learning... a good
> thing except that I've forgotten all about it. Had a similar case
> with omap_gpmc.
>
Well, actually reading patch 23, this one doesn't make much sense.
I'd like to let it in though. If I spend time polishing patchsets I'll
never get rid of ram_addr_t.
The plan is:
- convert devices
- clean up bus APIs
If I do all of the at once, it will end up in tears.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 21/24] isa: add isa_address_space()
2011-08-10 16:26 ` Richard Henderson
2011-08-10 16:35 ` Avi Kivity
@ 2011-08-10 18:44 ` Avi Kivity
1 sibling, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-10 18:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, kvm
On 08/10/2011 07:26 PM, Richard Henderson wrote:
> On 08/10/2011 09:24 AM, Richard Henderson wrote:
> > Of course, as far as I can see, this variable is only used by
> > the VGA devices. Surely we can arrange to pass down some address
> > space during setup of the VGA?
>
> ... Which seems to be what you've done in patch 23.
>
> So what's the point of this patch?
>
>
Some more about this:
We have a few dual (or even tripe) interface devices, of which vga is an
example. This requires a common interface when we add a memory region
to a device's bus. Let's enumerate the options:
1. just ignore the parent bus
this is cpu_register_physical_memory()
2. pass the right MemoryRegion to the device
this series
3. Integrate qdev and the memory API
introduce qdev_add_memory(), have vga.c call that.
4. Have the specialized device constructor (isa-vga.c's vga_initfn()
pass down a callback to the generaized device (vga_init_vbe()) that
wraps the bus-specific memory registration function:
static void isa_vga_add_region(void *opaque, ...)
{
ISAVGAState *d = opaque;
isa_add_region(&d->dev, ...);
}
vga_initfn()
{
...
vga_init_vbe(s, isa_vga_add_region, d);
...
}
1 and 2 are layering violations in that they don't allow bookkeeping by
the specific bus. 3 allows it to some extent but I still feel it is
wrong. 4 is correct in this sense but takes some work.
It may be that no bookkeeping is actually required and we can do 3, but
that will have to wait until qdev/memory integration. If not we'll
switch to 4.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH 18/24] versatile_pci: convert to memory API
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
@ 2011-08-11 16:20 ` Peter Maydell
-1 siblings, 0 replies; 90+ messages in thread
From: Peter Maydell @ 2011-08-11 16:20 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 8 August 2011 18:07, Avi Kivity <avi@redhat.com> wrote:
> -static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
> +static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
> + unsigned size)
> {
> uint32_t val;
> - val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
> - return val;
> + val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
> + return size;
> }
This should be 'return val', not 'return size', I think...
(otherwise PCI is broken on versatilepb; tested with your memory-region
branch rather than with this particular patch.)
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 18/24] versatile_pci: convert to memory API
@ 2011-08-11 16:20 ` Peter Maydell
0 siblings, 0 replies; 90+ messages in thread
From: Peter Maydell @ 2011-08-11 16:20 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 8 August 2011 18:07, Avi Kivity <avi@redhat.com> wrote:
> -static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
> +static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
> + unsigned size)
> {
> uint32_t val;
> - val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
> - return val;
> + val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
> + return size;
> }
This should be 'return val', not 'return size', I think...
(otherwise PCI is broken on versatilepb; tested with your memory-region
branch rather than with this particular patch.)
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 18/24] versatile_pci: convert to memory API
2011-08-11 16:20 ` [Qemu-devel] " Peter Maydell
(?)
@ 2011-08-11 16:26 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-11 16:26 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/11/2011 07:20 PM, Peter Maydell wrote:
> On 8 August 2011 18:07, Avi Kivity<avi@redhat.com> wrote:
> > -static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
> > +static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
> > + unsigned size)
> > {
> > uint32_t val;
> > - val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
> > - return val;
> > + val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
> > + return size;
> > }
>
> This should be 'return val', not 'return size', I think...
Wow, how did that happen?
> (otherwise PCI is broken on versatilepb; tested with your memory-region
> branch rather than with this particular patch.)
>
Updated patch to follow, thanks for the report.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v1.1 18/24] versatile_pci: convert to memory API
2011-08-11 16:20 ` [Qemu-devel] " Peter Maydell
@ 2011-08-11 16:29 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-11 16:29 UTC (permalink / raw)
To: qemu-devel, Peter Maydell; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
v1.1: fix bogus 'return size', thanks to Peter Maydell
hw/versatile_pci.c | 92 ++++++++++++++++++++++++---------------------------
1 files changed, 43 insertions(+), 49 deletions(-)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index e1d5c0b..98e56f1 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -16,7 +16,9 @@ typedef struct {
SysBusDevice busdev;
qemu_irq irq[4];
int realview;
- int mem_config;
+ MemoryRegion mem_config;
+ MemoryRegion mem_config2;
+ MemoryRegion isa;
} PCIVPBState;
static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
@@ -24,55 +26,24 @@ static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
return addr & 0xffffff;
}
-static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
+ pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
}
-static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
-}
-
-static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
-}
-
-static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
- return val;
-}
-
-static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
- return val;
-}
-
-static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
+ val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
return val;
}
-static CPUWriteMemoryFunc * const pci_vpb_config_write[] = {
- &pci_vpb_config_writeb,
- &pci_vpb_config_writew,
- &pci_vpb_config_writel,
-};
-
-static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
- &pci_vpb_config_readb,
- &pci_vpb_config_readw,
- &pci_vpb_config_readl,
+static const MemoryRegionOps pci_vpb_config_ops = {
+ .read = pci_vpb_config_read,
+ .write = pci_vpb_config_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
@@ -87,17 +58,35 @@ static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
+
static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
{
PCIVPBState *s = (PCIVPBState *)dev;
/* Selfconfig area. */
- cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
+ memory_region_add_subregion(get_system_memory(), base + 0x01000000,
+ &s->mem_config);
+ /* Normal config area. */
+ memory_region_add_subregion(get_system_memory(), base + 0x02000000,
+ &s->mem_config2);
+
+ if (s->realview) {
+ /* IO memory area. */
+ memory_region_add_subregion(get_system_memory(), base + 0x03000000,
+ &s->isa);
+ }
+}
+
+static void pci_vpb_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ PCIVPBState *s = (PCIVPBState *)dev;
+ /* Selfconfig area. */
+ memory_region_del_subregion(get_system_memory(), &s->mem_config);
/* Normal config area. */
- cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
+ memory_region_del_subregion(get_system_memory(), &s->mem_config2);
if (s->realview) {
/* IO memory area. */
- isa_mmio_init(base + 0x03000000, 0x00100000);
+ memory_region_del_subregion(get_system_memory(), &s->isa);
}
}
@@ -117,10 +106,15 @@ static int pci_vpb_init(SysBusDevice *dev)
/* ??? Register memory space. */
- s->mem_config = cpu_register_io_memory(pci_vpb_config_read,
- pci_vpb_config_write, bus,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
+ memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
+ "pci-vpb-selfconfig", 0x1000000);
+ memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
+ "pci-vpb-config", 0x1000000);
+ if (s->realview) {
+ isa_mmio_setup(&s->isa, 0x0100000);
+ }
+
+ sysbus_init_mmio_cb2(dev, pci_vpb_map, pci_vpb_unmap);
pci_create_simple(bus, -1, "versatile_pci_host");
return 0;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v1.1 18/24] versatile_pci: convert to memory API
@ 2011-08-11 16:29 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-11 16:29 UTC (permalink / raw)
To: qemu-devel, Peter Maydell; +Cc: kvm
Signed-off-by: Avi Kivity <avi@redhat.com>
---
v1.1: fix bogus 'return size', thanks to Peter Maydell
hw/versatile_pci.c | 92 ++++++++++++++++++++++++---------------------------
1 files changed, 43 insertions(+), 49 deletions(-)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index e1d5c0b..98e56f1 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -16,7 +16,9 @@ typedef struct {
SysBusDevice busdev;
qemu_irq irq[4];
int realview;
- int mem_config;
+ MemoryRegion mem_config;
+ MemoryRegion mem_config2;
+ MemoryRegion isa;
} PCIVPBState;
static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
@@ -24,55 +26,24 @@ static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
return addr & 0xffffff;
}
-static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
+ pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
}
-static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
-}
-
-static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
-}
-
-static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
- return val;
-}
-
-static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
- return val;
-}
-
-static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
+ val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
return val;
}
-static CPUWriteMemoryFunc * const pci_vpb_config_write[] = {
- &pci_vpb_config_writeb,
- &pci_vpb_config_writew,
- &pci_vpb_config_writel,
-};
-
-static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
- &pci_vpb_config_readb,
- &pci_vpb_config_readw,
- &pci_vpb_config_readl,
+static const MemoryRegionOps pci_vpb_config_ops = {
+ .read = pci_vpb_config_read,
+ .write = pci_vpb_config_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
@@ -87,17 +58,35 @@ static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
+
static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
{
PCIVPBState *s = (PCIVPBState *)dev;
/* Selfconfig area. */
- cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
+ memory_region_add_subregion(get_system_memory(), base + 0x01000000,
+ &s->mem_config);
+ /* Normal config area. */
+ memory_region_add_subregion(get_system_memory(), base + 0x02000000,
+ &s->mem_config2);
+
+ if (s->realview) {
+ /* IO memory area. */
+ memory_region_add_subregion(get_system_memory(), base + 0x03000000,
+ &s->isa);
+ }
+}
+
+static void pci_vpb_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ PCIVPBState *s = (PCIVPBState *)dev;
+ /* Selfconfig area. */
+ memory_region_del_subregion(get_system_memory(), &s->mem_config);
/* Normal config area. */
- cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
+ memory_region_del_subregion(get_system_memory(), &s->mem_config2);
if (s->realview) {
/* IO memory area. */
- isa_mmio_init(base + 0x03000000, 0x00100000);
+ memory_region_del_subregion(get_system_memory(), &s->isa);
}
}
@@ -117,10 +106,15 @@ static int pci_vpb_init(SysBusDevice *dev)
/* ??? Register memory space. */
- s->mem_config = cpu_register_io_memory(pci_vpb_config_read,
- pci_vpb_config_write, bus,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
+ memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
+ "pci-vpb-selfconfig", 0x1000000);
+ memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
+ "pci-vpb-config", 0x1000000);
+ if (s->realview) {
+ isa_mmio_setup(&s->isa, 0x0100000);
+ }
+
+ sysbus_init_mmio_cb2(dev, pci_vpb_map, pci_vpb_unmap);
pci_create_simple(bus, -1, "versatile_pci_host");
return 0;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 90+ messages in thread
* Re: [PATCH v1.1 18/24] versatile_pci: convert to memory API
2011-08-11 16:29 ` [Qemu-devel] " Avi Kivity
@ 2011-08-11 21:53 ` Peter Maydell
-1 siblings, 0 replies; 90+ messages in thread
From: Peter Maydell @ 2011-08-11 21:53 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 11 August 2011 17:29, Avi Kivity <avi@redhat.com> wrote:
> -static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
> +static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
> + unsigned size)
> {
> uint32_t val;
> - val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
> + val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
> return val;
> }
...actually this looks a bit odd now, because the return type has
become uint64_t but val is still uint32_t (though pci_data_read()
still returns a uint32_t, so I suppose it's defensible).
I'm not sure why the local is there anyway, so I'd be tempted to
just return pci_data_read(...).
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 18/24] versatile_pci: convert to memory API
@ 2011-08-11 21:53 ` Peter Maydell
0 siblings, 0 replies; 90+ messages in thread
From: Peter Maydell @ 2011-08-11 21:53 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 11 August 2011 17:29, Avi Kivity <avi@redhat.com> wrote:
> -static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
> +static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
> + unsigned size)
> {
> uint32_t val;
> - val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
> + val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
> return val;
> }
...actually this looks a bit odd now, because the return type has
become uint64_t but val is still uint32_t (though pci_data_read()
still returns a uint32_t, so I suppose it's defensible).
I'm not sure why the local is there anyway, so I'd be tempted to
just return pci_data_read(...).
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 17/24] arm11mpcore: use sysbus_init_mmio_cb2
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
(?)
@ 2011-08-12 13:23 ` Peter Maydell
2011-08-14 18:45 ` [Qemu-devel] " Avi Kivity
-1 siblings, 1 reply; 90+ messages in thread
From: Peter Maydell @ 2011-08-12 13:23 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel, kvm
On 8 August 2011 18:07, Avi Kivity <avi@redhat.com> wrote:
> This tells the sysbus code it need not use IO_MEM_UNASSIGNED.
>
> Signed-off-by: Avi Kivity <avi@redhat.com>
> ---
> hw/arm11mpcore.c | 7 ++++++-
> 1 files changed, 6 insertions(+), 1 deletions(-)
>
> diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
> index b47707f..7d60ef6 100644
> --- a/hw/arm11mpcore.c
> +++ b/hw/arm11mpcore.c
> @@ -54,6 +54,11 @@ static void mpcore_rirq_map(SysBusDevice *dev, target_phys_addr_t base)
> sysbus_mmio_map(s->priv, 0, base);
> }
>
> +static void mpcore_rirq_unmap(SysBusDevice *dev, target_phys_addr_t base)
> +{
> + /* nothing to do */
> +}
> +
> static int realview_mpcore_init(SysBusDevice *dev)
> {
> mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
> @@ -79,7 +84,7 @@ static int realview_mpcore_init(SysBusDevice *dev)
> }
> }
> qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
> - sysbus_init_mmio_cb(dev, 0x2000, mpcore_rirq_map);
> + sysbus_init_mmio_cb2(dev, mpcore_rirq_map, mpcore_rirq_unmap);
> return 0;
> }
Since the mpcore code here is only using sysbus mmio callbacks as
a way to pass things through to a sysbus mmio provided by another
device, I think it would be cleaner to just have a way to say "my
mmio is actually provided by this other device".
For instance you could have
MemoryRegion* sysbus_mmio_get_region(SysBusDevice *dev, int n))
{
return dev->mmio[n].memory;
}
and then realview_mpcore_init() can just
sysbus_init_mmio_region(dev, sysbus_mmio_get_region(s->priv, 0));
Or you could have a sysbus_pass_mmio() which worked like
sysbus_pass_irq() and just said "my mmios are all this other
device's mmios"; that's less flexible though.
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH v1.1 18/24] versatile_pci: convert to memory API
2011-08-11 21:53 ` [Qemu-devel] " Peter Maydell
@ 2011-08-14 18:31 ` Avi Kivity
-1 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-14 18:31 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/11/2011 02:53 PM, Peter Maydell wrote:
> On 11 August 2011 17:29, Avi Kivity<avi@redhat.com> wrote:
> > -static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
> > +static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
> > + unsigned size)
> > {
> > uint32_t val;
> > - val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
> > + val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
> > return val;
> > }
>
> ...actually this looks a bit odd now, because the return type has
> become uint64_t but val is still uint32_t (though pci_data_read()
> still returns a uint32_t, so I suppose it's defensible).
I probably should have left 64-bit data width until later. Note the
core will never ask a device for 64-bit data unless the device declares
it supports it.
> I'm not sure why the local is there anyway, so I'd be tempted to
> just return pci_data_read(...).
>
I'm making minimal, reviewable changes, not trying to improve things.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 18/24] versatile_pci: convert to memory API
@ 2011-08-14 18:31 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-14 18:31 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/11/2011 02:53 PM, Peter Maydell wrote:
> On 11 August 2011 17:29, Avi Kivity<avi@redhat.com> wrote:
> > -static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
> > +static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
> > + unsigned size)
> > {
> > uint32_t val;
> > - val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
> > + val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
> > return val;
> > }
>
> ...actually this looks a bit odd now, because the return type has
> become uint64_t but val is still uint32_t (though pci_data_read()
> still returns a uint32_t, so I suppose it's defensible).
I probably should have left 64-bit data width until later. Note the
core will never ask a device for 64-bit data unless the device declares
it supports it.
> I'm not sure why the local is there anyway, so I'd be tempted to
> just return pci_data_read(...).
>
I'm making minimal, reviewable changes, not trying to improve things.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH 17/24] arm11mpcore: use sysbus_init_mmio_cb2
2011-08-12 13:23 ` Peter Maydell
@ 2011-08-14 18:45 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-14 18:45 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/12/2011 06:23 AM, Peter Maydell wrote:
> > static int realview_mpcore_init(SysBusDevice *dev)
> > {
> > mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
> > @@ -79,7 +84,7 @@ static int realview_mpcore_init(SysBusDevice *dev)
> > }
> > }
> > qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
> > - sysbus_init_mmio_cb(dev, 0x2000, mpcore_rirq_map);
> > + sysbus_init_mmio_cb2(dev, mpcore_rirq_map, mpcore_rirq_unmap);
> > return 0;
> > }
>
> Since the mpcore code here is only using sysbus mmio callbacks as
> a way to pass things through to a sysbus mmio provided by another
> device, I think it would be cleaner to just have a way to say "my
> mmio is actually provided by this other device".
>
> For instance you could have
> MemoryRegion* sysbus_mmio_get_region(SysBusDevice *dev, int n))
> {
> return dev->mmio[n].memory;
> }
>
> and then realview_mpcore_init() can just
> sysbus_init_mmio_region(dev, sysbus_mmio_get_region(s->priv, 0));
>
> Or you could have a sysbus_pass_mmio() which worked like
> sysbus_pass_irq() and just said "my mmios are all this other
> device's mmios"; that's less flexible though.
>
>
Yes. Yet another option is to create a container MemoryRegion and pass
it upwards, then allow the device that actually implements that mmio to
register its regions with the container.
I'll leave this to the device maintainer though.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH 17/24] arm11mpcore: use sysbus_init_mmio_cb2
@ 2011-08-14 18:45 ` Avi Kivity
0 siblings, 0 replies; 90+ messages in thread
From: Avi Kivity @ 2011-08-14 18:45 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, kvm
On 08/12/2011 06:23 AM, Peter Maydell wrote:
> > static int realview_mpcore_init(SysBusDevice *dev)
> > {
> > mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
> > @@ -79,7 +84,7 @@ static int realview_mpcore_init(SysBusDevice *dev)
> > }
> > }
> > qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
> > - sysbus_init_mmio_cb(dev, 0x2000, mpcore_rirq_map);
> > + sysbus_init_mmio_cb2(dev, mpcore_rirq_map, mpcore_rirq_unmap);
> > return 0;
> > }
>
> Since the mpcore code here is only using sysbus mmio callbacks as
> a way to pass things through to a sysbus mmio provided by another
> device, I think it would be cleaner to just have a way to say "my
> mmio is actually provided by this other device".
>
> For instance you could have
> MemoryRegion* sysbus_mmio_get_region(SysBusDevice *dev, int n))
> {
> return dev->mmio[n].memory;
> }
>
> and then realview_mpcore_init() can just
> sysbus_init_mmio_region(dev, sysbus_mmio_get_region(s->priv, 0));
>
> Or you could have a sysbus_pass_mmio() which worked like
> sysbus_pass_irq() and just said "my mmios are all this other
> device's mmios"; that's less flexible though.
>
>
Yes. Yet another option is to create a container MemoryRegion and pass
it upwards, then allow the device that actually implements that mmio to
register its regions with the container.
I'll leave this to the device maintainer though.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
^ permalink raw reply [flat|nested] 90+ messages in thread
end of thread, other threads:[~2011-08-14 18:45 UTC | newest]
Thread overview: 90+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-08-08 17:06 [PATCH 00/24] Memory API batch 4: more conversions Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 01/24] apb_pci: convert to memory API Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 02/24] apic: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 03/24] arm_gic: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 04/24] arm_sysctl: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 05/24] arm_timer: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 06/24] armv7m: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 07/24] gt64xxx.c: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 08/24] tusb6010: move declarations to new file tusb6010.h Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-09 7:51 ` Peter Maydell
2011-08-09 7:51 ` [Qemu-devel] " Peter Maydell
2011-08-09 9:02 ` [PATCH v1.1 " Avi Kivity
2011-08-09 9:02 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 09/24] omap_gpmc/nseries/tusb6010: convert to memory API Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:43 ` Peter Maydell
2011-08-09 6:34 ` Avi Kivity
2011-08-09 7:37 ` Peter Maydell
2011-08-09 7:41 ` Avi Kivity
2011-08-09 8:07 ` Peter Maydell
2011-08-09 8:44 ` Avi Kivity
2011-08-09 8:56 ` Avi Kivity
2011-08-09 8:56 ` [Qemu-devel] " Avi Kivity
2011-08-09 9:02 ` [PATCH v1.1 " Avi Kivity
2011-08-09 9:02 ` [Qemu-devel] " Avi Kivity
2011-08-09 9:23 ` Peter Maydell
2011-08-09 9:23 ` [Qemu-devel] " Peter Maydell
2011-08-09 9:26 ` Avi Kivity
2011-08-09 9:26 ` [Qemu-devel] " Avi Kivity
2011-08-09 9:41 ` Peter Maydell
2011-08-09 12:56 ` Avi Kivity
2011-08-09 13:06 ` [PATCH v1.2 " Avi Kivity
2011-08-09 13:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 10/24] onenand: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 11/24] pcie_host: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 12/24] ppc405_uc: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 13/24] ppc4xx_sdram: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:06 ` [PATCH 14/24] stellaris_enet: " Avi Kivity
2011-08-08 17:06 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:07 ` [PATCH 15/24] sysbus: add a variant of sysbus_init_mmio_cb with an unmap callback Avi Kivity
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:07 ` [PATCH 16/24] sh_pci: convert to memory API Avi Kivity
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:07 ` [PATCH 17/24] arm11mpcore: use sysbus_init_mmio_cb2 Avi Kivity
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
2011-08-12 13:23 ` Peter Maydell
2011-08-14 18:45 ` Avi Kivity
2011-08-14 18:45 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:07 ` [PATCH 18/24] versatile_pci: convert to memory API Avi Kivity
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
2011-08-11 16:20 ` Peter Maydell
2011-08-11 16:20 ` [Qemu-devel] " Peter Maydell
2011-08-11 16:26 ` Avi Kivity
2011-08-11 16:29 ` [PATCH v1.1 " Avi Kivity
2011-08-11 16:29 ` [Qemu-devel] " Avi Kivity
2011-08-11 21:53 ` Peter Maydell
2011-08-11 21:53 ` [Qemu-devel] " Peter Maydell
2011-08-14 18:31 ` Avi Kivity
2011-08-14 18:31 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:07 ` [PATCH 19/24] ppce500_pci: convert to sysbus_init_mmio_cb2() Avi Kivity
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:07 ` [PATCH 20/24] sysbus: remove sysbus_init_mmio_cb() Avi Kivity
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:07 ` [PATCH 21/24] isa: add isa_address_space() Avi Kivity
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
2011-08-10 16:24 ` Richard Henderson
2011-08-10 16:26 ` Richard Henderson
2011-08-10 16:35 ` Avi Kivity
2011-08-10 16:38 ` Avi Kivity
2011-08-10 18:44 ` Avi Kivity
2011-08-10 16:32 ` Avi Kivity
2011-08-08 17:07 ` [PATCH 22/24] pci: add pci_address_space() Avi Kivity
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:07 ` [PATCH 23/24] vga: drop get_system_memory() from vga devices and derivatives Avi Kivity
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
2011-08-08 17:07 ` [PATCH 24/24] 440fx: fix PAM, PCI holes Avi Kivity
2011-08-08 17:07 ` [Qemu-devel] " Avi Kivity
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