[U-Boot] [PATCH] powerpc/mpc83xx: Rename CONFIG_SYS_DDR_CONFIG to CONFIG_SYS_DDR_CS_CONFIG

[U-Boot] [PATCH] powerpc/mpc83xx: Rename CONFIG_SYS_DDR_CONFIG to CONFIG_SYS_DDR_CS_CONFIG

[Joe Hershberger]

The register this is written to is named ddr.cs_config, so name the #define similarly to reduce confusion

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
---
 board/freescale/mpc8313erdb/sdram.c       |    2 +-
 board/freescale/mpc8349emds/mpc8349emds.c |    2 +-
 board/freescale/mpc8349itx/mpc8349itx.c   |    2 +-
 board/freescale/mpc8360emds/mpc8360emds.c |    4 ++--
 board/sbc8349/sbc8349.c                   |    2 +-
 board/ve8313/ve8313.c                     |    2 +-
 include/configs/MPC8313ERDB.h             |    2 +-
 include/configs/MPC8349EMDS.h             |    2 +-
 include/configs/MPC8349ITX.h              |    2 +-
 include/configs/MPC8360EMDS.h             |    2 +-
 include/configs/sbc8349.h                 |    2 +-
 include/configs/ve8313.h                  |    2 +-
 12 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 7aede13..35e3055 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -75,7 +75,7 @@ static long fixed_sdram(void)
 	__udelay(50000);
 
 	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS_CONFIG;
 
 	/* Currently we use only one CS, so disable the other bank. */
 	im->ddr.cs_config[1] = 0;
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 365ac37..14f6e9f 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -130,7 +130,7 @@ int fixed_sdram(void)
 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 #else
 	im->ddr.csbnds[2].csbnds = 0x0000000f;
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS_CONFIG;
 
 	/* currently we use only one CS, so disable the other banks */
 	im->ddr.cs_config[0] = 0;
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 5647579..1d69f17 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -59,7 +59,7 @@ int fixed_sdram(void)
 
 	/* Only one CS0 for DDR */
 	im->ddr.csbnds[0].csbnds = 0x0000000f;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS_CONFIG;
 
 	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
 	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 51d8035..91f4194 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -249,8 +249,8 @@ int fixed_sdram(void)
 	im->ddr.csbnds[0].csbnds = 0x00000007;
 	im->ddr.csbnds[1].csbnds = 0x0008000f;
 
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
-	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS_CONFIG;
+	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS_CONFIG;
 
 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 50fae7c..a67fee1 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -108,7 +108,7 @@ int fixed_sdram(void)
 #warning Currently any ddr size other than 256 is not supported
 #endif
 	im->ddr.csbnds[2].csbnds = 0x0000000f;
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS_CONFIG;
 
 	/* currently we use only one CS, so disable the other banks */
 	im->ddr.cs_config[0] = 0;
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 166e459..bf6699d 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -66,7 +66,7 @@ static long fixed_sdram(void)
 	__udelay(50000);
 
 	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
-	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS_CONFIG);
 
 	/* Currently we use only one CS, so disable the other bank. */
 	out_be32(&im->ddr.cs_config[1], 0);
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 92c54d0..78ad565 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -130,7 +130,7 @@
  * seem to have the SPD connected to I2C.
  */
 #define CONFIG_SYS_DDR_SIZE		128		/* MB */
-#define CONFIG_SYS_DDR_CONFIG		( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS_CONFIG	( CSCONFIG_EN \
 				| 0x00010000 /* TODO */ \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
 				/* 0x80010102 */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 45b6b5f..a723210 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -126,7 +126,7 @@
 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #else
-#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_CS_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 #define CONFIG_SYS_DDR_TIMING_1	0x36332321
 #define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
 #define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index de233ff..720b61b 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -202,7 +202,7 @@
 
 #ifndef CONFIG_SPD_EEPROM	/* No SPD? Then manually set up DDR parameters */
     #define CONFIG_SYS_DDR_SIZE	256		/* Mb */
-    #define CONFIG_SYS_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+    #define CONFIG_SYS_DDR_CS_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 
     #define CONFIG_SYS_DDR_TIMING_1	0x26242321
     #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 49d64a5..63a2a0c 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -144,7 +144,7 @@
 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #else
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
 #define CONFIG_SYS_DDR_TIMING_1	0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 #define CONFIG_SYS_DDR_TIMING_2	0x00000800 /* may need tuning */
 #define CONFIG_SYS_DDR_CONTROL		0x42008000 /* Self refresh,2T timing */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index b418cf2..3067abd 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -114,7 +114,7 @@
  * NB: manual DDR setup untested on sbc834x
  */
 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_CS_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 #define CONFIG_SYS_DDR_TIMING_1	0x36332321
 #define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
 #define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index abb57fe..8f5696a 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -79,7 +79,7 @@
  * have the SPD connected to I2C.
  */
 #define CONFIG_SYS_DDR_SIZE		128		/* MB */
-#define CONFIG_SYS_DDR_CONFIG		( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS_CONFIG	( CSCONFIG_EN \
 				| CSCONFIG_AP \
 				| 0x00040000 /* TODO */ \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
-- 
1.6.0.2

[U-Boot] [PATCH v2] powerpc/mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code

[Joe Hershberger]

Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring
Cleanup the setting of the csnbds to respect the setting of CONFIG_SYS_DDR_SDRAM_BASE
Use __ilog2 instead of writing the code to compute it
Disable unused CS configs
Ensure ddrlaw.bar is configured

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
---
Changes for v2:
 - Changed from CONFIG_SYS_DDR_CS_CONFIG to CONFIG_SYS_DDR_CS[x]_CONFIG where [x] is the actual CS used
 - Cleaup code that uses the csbnds associated with the DDR_CS_CONFIG

 board/freescale/mpc8313erdb/sdram.c       |    9 +++++-
 board/freescale/mpc8349emds/mpc8349emds.c |   26 +++++++++----------
 board/freescale/mpc8349itx/mpc8349itx.c   |   26 ++++++++++---------
 board/freescale/mpc8360emds/mpc8360emds.c |   39 +++++++++++++++++------------
 board/sbc8349/sbc8349.c                   |   26 +++++++++----------
 board/ve8313/ve8313.c                     |    9 +++++-
 include/configs/MPC8313ERDB.h             |    2 +-
 include/configs/MPC8349EMDS.h             |    2 +-
 include/configs/MPC8349ITX.h              |    2 +-
 include/configs/MPC8360EMDS.h             |    3 +-
 include/configs/sbc8349.h                 |    2 +-
 include/configs/ve8313.h                  |    2 +-
 12 files changed, 82 insertions(+), 66 deletions(-)

diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 7aede13..ab3fb3c 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -74,8 +74,13 @@ static long fixed_sdram(void)
 	 */
 	__udelay(50000);
 
-	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0 )
+#warning Chip select bounds is only configurable in 16MB increments (modify CONFIG_SYS_DDR_SDRAM_BASE)
+#endif
+	im->ddr.csbnds[0].csbnds =
+		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA);
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 
 	/* Currently we use only one CS, so disable the other bank. */
 	im->ddr.cs_config[1] = 0;
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 365ac37..29b8a4b 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -97,18 +97,10 @@ phys_size_t initdram (int board_type)
 int fixed_sdram(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1);
-	     ddr_size = ddr_size>>1, ddr_size_log2++) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-	}
+	u32 msize = CONFIG_SYS_DDR_SIZE;
+	u32 ddr_size = msize << 20;	/* DDR size in bytes */
+	u32 ddr_size_log2 = __ilog2(ddr_size);
+
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
@@ -129,8 +121,14 @@ int fixed_sdram(void)
 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 #else
-	im->ddr.csbnds[2].csbnds = 0x0000000f;
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0 )
+#warning Chip select bounds is only configurable in 16MB increments (modify CONFIG_SYS_DDR_SDRAM_BASE)
+#endif
+	im->ddr.csbnds[2].csbnds =
+		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA);
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 
 	/* currently we use only one CS, so disable the other banks */
 	im->ddr.cs_config[0] = 0;
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 5647579..22b4234 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -43,23 +43,25 @@
 int fixed_sdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 ddr_size;		/* The size of RAM, in bytes */
-	u32 ddr_size_log2 = 0;
-
-	for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-		ddr_size_log2++;
-	}
+	u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;	/* The size of RAM, in bytes */
+	u32 ddr_size_log2 = __ilog2(ddr_size);
 
 	im->sysconf.ddrlaw[0].ar =
 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 
-	/* Only one CS0 for DDR */
-	im->ddr.csbnds[0].csbnds = 0x0000000f;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0 )
+#warning Chip select bounds is only configurable in 16MB increments (modify CONFIG_SYS_DDR_SDRAM_BASE)
+#endif
+	im->ddr.csbnds[0].csbnds =
+		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA);
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+	/* Only one CS for DDR */
+	im->ddr.cs_config[1] = 0;
+	im->ddr.cs_config[2] = 0;
+	im->ddr.cs_config[3] = 0;
 
 	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
 	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 51d8035..cde5bec 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -216,19 +216,15 @@ phys_size_t initdram(int board_type)
 int fixed_sdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-	}
+	u32 msize = CONFIG_SYS_DDR_SIZE;
+	u32 ddr_size = msize << 20;
+	u32 ddr_size_log2 = __ilog2(ddr_size);
+	u32 half_ddr_size = ddr_size >> 1;
+
+	im->sysconf.ddrlaw[0].bar =
+		CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+		LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 #if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currenly any ddr size other than 256 is not supported
 #endif
@@ -246,11 +242,22 @@ int fixed_sdram(void)
 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 #else
-	im->ddr.csbnds[0].csbnds = 0x00000007;
-	im->ddr.csbnds[1].csbnds = 0x0008000f;
 
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
-	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0 )
+#warning Chip select bounds is only configurable in 16MB increments (modify CONFIG_SYS_DDR_SDRAM_BASE)
+#endif
+	im->ddr.csbnds[0].csbnds =
+		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA);
+	im->ddr.csbnds[1].csbnds =
+		(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA);
+
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
+
+	im->ddr.cs_config[2] = 0;
+	im->ddr.cs_config[3] = 0;
 
 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 50fae7c..eb558b4 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -89,26 +89,24 @@ phys_size_t initdram (int board_type)
 int fixed_sdram(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1);
-	     ddr_size = ddr_size>>1, ddr_size_log2++) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-	}
+	u32 msize = CONFIG_SYS_DDR_SIZE;
+	u32 ddr_size = msize << 20;	/* DDR size in bytes */
+	u32 ddr_size_log2 = __ilog2(msize);
+
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
 #if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currently any ddr size other than 256 is not supported
 #endif
-	im->ddr.csbnds[2].csbnds = 0x0000000f;
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0 )
+#warning Chip select bounds is only configurable in 16MB increments (modify CONFIG_SYS_DDR_SDRAM_BASE)
+#endif
+	im->ddr.csbnds[2].csbnds =
+		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA);
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 
 	/* currently we use only one CS, so disable the other banks */
 	im->ddr.cs_config[0] = 0;
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 166e459..8ae5edf 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -65,8 +65,13 @@ static long fixed_sdram(void)
 	 */
 	__udelay(50000);
 
-	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
-	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0 )
+#warning Chip select bounds is only configurable in 16MB increments (modify CONFIG_SYS_DDR_SDRAM_BASE)
+#endif
+	out_be32(&im->ddr.csbnds[0].csbnds,
+		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA));
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 
 	/* Currently we use only one CS, so disable the other bank. */
 	out_be32(&im->ddr.cs_config[1], 0);
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 92c54d0..354278a 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -130,7 +130,7 @@
  * seem to have the SPD connected to I2C.
  */
 #define CONFIG_SYS_DDR_SIZE		128		/* MB */
-#define CONFIG_SYS_DDR_CONFIG		( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS0_CONFIG	( CSCONFIG_EN \
 				| 0x00010000 /* TODO */ \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
 				/* 0x80010102 */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 45b6b5f..7e42f6e 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -126,7 +126,7 @@
 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #else
-#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 #define CONFIG_SYS_DDR_TIMING_1	0x36332321
 #define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
 #define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index de233ff..981058f 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -202,7 +202,7 @@
 
 #ifndef CONFIG_SPD_EEPROM	/* No SPD? Then manually set up DDR parameters */
     #define CONFIG_SYS_DDR_SIZE	256		/* Mb */
-    #define CONFIG_SYS_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+    #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 
     #define CONFIG_SYS_DDR_TIMING_1	0x26242321
     #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 49d64a5..1a9e9b5 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -144,7 +144,8 @@
 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #else
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG
 #define CONFIG_SYS_DDR_TIMING_1	0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 #define CONFIG_SYS_DDR_TIMING_2	0x00000800 /* may need tuning */
 #define CONFIG_SYS_DDR_CONTROL		0x42008000 /* Self refresh,2T timing */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index b418cf2..7662c84 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -114,7 +114,7 @@
  * NB: manual DDR setup untested on sbc834x
  */
 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 #define CONFIG_SYS_DDR_TIMING_1	0x36332321
 #define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
 #define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index abb57fe..175adf5 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -79,7 +79,7 @@
  * have the SPD connected to I2C.
  */
 #define CONFIG_SYS_DDR_SIZE		128		/* MB */
-#define CONFIG_SYS_DDR_CONFIG		( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS0_CONFIG	( CSCONFIG_EN \
 				| CSCONFIG_AP \
 				| 0x00040000 /* TODO */ \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
-- 
1.6.0.2

[U-Boot] [PATCH v2] powerpc/mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code

[Kim Phillips]

On Tue, 16 Aug 2011 19:48:13 -0500
Joe Hershberger <joe.hershberger@ni.com> wrote:

> Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring
> Cleanup the setting of the csnbds to respect the setting of CONFIG_SYS_DDR_SDRAM_BASE
> Use __ilog2 instead of writing the code to compute it
> Disable unused CS configs
> Ensure ddrlaw.bar is configured
> 
> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Kim Phillips <kim.phillips@freescale.com>

applied, thanks.

Kim

[U-Boot] [PATCH v2] powerpc/mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code

[Wolfgang Denk]

Dear Joe Hershberger,

In message <1313542093-7252-1-git-send-email-joe.hershberger@ni.com> you wrote:
> Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring
> Cleanup the setting of the csnbds to respect the setting of CONFIG_SYS_DDR_SDRAM_BASE
> Use __ilog2 instead of writing the code to compute it
> Disable unused CS configs
> Ensure ddrlaw.bar is configured
> 
> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Kim Phillips <kim.phillips@freescale.com>
> ---
> Changes for v2:
>  - Changed from CONFIG_SYS_DDR_CS_CONFIG to CONFIG_SYS_DDR_CS[x]_CONFIG where [x] is the actual CS used
>  - Cleaup code that uses the csbnds associated with the DDR_CS_CONFIG
> 
>  board/freescale/mpc8313erdb/sdram.c       |    9 +++++-
>  board/freescale/mpc8349emds/mpc8349emds.c |   26 +++++++++----------
>  board/freescale/mpc8349itx/mpc8349itx.c   |   26 ++++++++++---------
>  board/freescale/mpc8360emds/mpc8360emds.c |   39 +++++++++++++++++------------
>  board/sbc8349/sbc8349.c                   |   26 +++++++++----------
>  board/ve8313/ve8313.c                     |    9 +++++-
>  include/configs/MPC8313ERDB.h             |    2 +-
>  include/configs/MPC8349EMDS.h             |    2 +-
>  include/configs/MPC8349ITX.h              |    2 +-
>  include/configs/MPC8360EMDS.h             |    3 +-
>  include/configs/sbc8349.h                 |    2 +-
>  include/configs/ve8313.h                  |    2 +-
>  12 files changed, 82 insertions(+), 66 deletions(-)

Checkpatch says:

total: 8 errors, 19 warnings, 245 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Every revolutionary idea - in science, politics, art, or  whatever  -
evokes three stages of reaction in a hearer:
  1. It is completely impossible - don't waste my time.
  2. It is possible, but it is not worth doing.
  3. I said it was a good idea all along.

[U-Boot] [PATCH v2] powerpc/mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code

[Wolfgang Denk]

Dear Kim Phillips,

In message <20110913201006.2c0d3fa1.kim.phillips@freescale.com> you wrote:
> On Tue, 16 Aug 2011 19:48:13 -0500
> Joe Hershberger <joe.hershberger@ni.com> wrote:
> 
> > Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring
> > Cleanup the setting of the csnbds to respect the setting of CONFIG_SYS_DDR_SDRAM_BASE
> > Use __ilog2 instead of writing the code to compute it
> > Disable unused CS configs
> > Ensure ddrlaw.bar is configured
> > 
> > Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
> > Cc: Joe Hershberger <joe.hershberger@gmail.com>
> > Cc: Kim Phillips <kim.phillips@freescale.com>
> 
> applied, thanks.

Please undo.

You might want to run checkpatch over the stuff before applying it.
Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Hegel was right when he said that we learn from history that man  can
never learn anything from history.              - George Bernard Shaw

[U-Boot] [PATCH] powerpc/mpc83xx: Rename CONFIG_SYS_DDR_CONFIG to CONFIG_SYS_DDR_CS_CONFIG

[Wolfgang Denk]

Dear Joe Hershberger,

In message <1313015637-5160-1-git-send-email-joe.hershberger@ni.com> you wrote:
> The register this is written to is named ddr.cs_config, so name the #define similarly to reduce confusion
> 
> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Kim Phillips <kim.phillips@freescale.com>
> ---
>  board/freescale/mpc8313erdb/sdram.c       |    2 +-
>  board/freescale/mpc8349emds/mpc8349emds.c |    2 +-
>  board/freescale/mpc8349itx/mpc8349itx.c   |    2 +-
>  board/freescale/mpc8360emds/mpc8360emds.c |    4 ++--
>  board/sbc8349/sbc8349.c                   |    2 +-
>  board/ve8313/ve8313.c                     |    2 +-
>  include/configs/MPC8313ERDB.h             |    2 +-
>  include/configs/MPC8349EMDS.h             |    2 +-
>  include/configs/MPC8349ITX.h              |    2 +-
>  include/configs/MPC8360EMDS.h             |    2 +-
>  include/configs/sbc8349.h                 |    2 +-
>  include/configs/ve8313.h                  |    2 +-
>  12 files changed, 13 insertions(+), 13 deletions(-)

Checkpatch says:

total: 2 errors, 4 warnings, 98 lines checked

Please clean up and resubmit.  Thanks.


Seems your're trying to break the record for the highest number of
rejects due to never running checkpatch :-(

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
SW engineering is a race between programmers trying  to  make  better
idiot-proof programs and the universe producing greater idiots.

[U-Boot] [PATCH v2] powerpc/mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code

[Wolfgang Denk]

Dear Kim Phillips,

In message <20110913201006.2c0d3fa1.kim.phillips@freescale.com> you wrote:
> On Tue, 16 Aug 2011 19:48:13 -0500
> Joe Hershberger <joe.hershberger@ni.com> wrote:
> 
> > Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring
> > Cleanup the setting of the csnbds to respect the setting of CONFIG_SYS_DDR_SDRAM_BASE
> > Use __ilog2 instead of writing the code to compute it
> > Disable unused CS configs
> > Ensure ddrlaw.bar is configured
> > 
> > Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
> > Cc: Joe Hershberger <joe.hershberger@gmail.com>
> > Cc: Kim Phillips <kim.phillips@freescale.com>
> 
> applied, thanks.

Please undo.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It's certainly  convenient  the  way  the  crime  (or  condition)  of
stupidity   carries   with   it  its  own  punishment,  automatically
admisistered without remorse, pity, or prejudice. :-)
         -- Tom Christiansen in <559seq$ag1$1@csnews.cs.colorado.edu>

[U-Boot] [PATCH] powerpc/mpc83xx: Rename CONFIG_SYS_DDR_CONFIG to CONFIG_SYS_DDR_CS_CONFIG

[Joe Hershberger]

On Thu, Oct 6, 2011 at 5:02 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Joe Hershberger,
>
> Seems your're trying to break the record for the highest number of
> rejects due to never running checkpatch :-(

Many appologies for neglecting this step.

I've changed all of the include/config/*.h files for mpc83xx targets
to be checkpatch compliant and rebased my patches on that.  Coming
soon...

Again, sorry for the churn that I've caused.  I'll be more diligent in
the future.

-Joe