[U-Boot] [PATCH v3 0/8] feature additions and fixes for da850

[U-Boot] [PATCH v3 0/8] feature additions and fixes for da850

[nagabhushana.netagunte at ti.com]

From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>

Fix from last version (addressed comments from Detlev)
1: fixed env size for NOR boot mode.

Manjunathappa, Prakash (1):
  da850: add support for Spectrum Digital AM18xx EVM

Nagabhushana Netagunte (6):
  da850: indicate cache usage disable in config file
  da850: add NOR boot mode support
  da850: modify the U-Boot prompt string
  da850: add support to wake up DSP during board init
  da850: fix the channel number for EMAC teardown init
  da850: modifications for Logic PD Rev.3 AM18xx EVM

Sudhakar Rajashekhara (1):
  da8xx: add support for multiple PLL controllers

 arch/arm/cpu/arm926ejs/davinci/cpu.c         |   30 ++++---
 arch/arm/include/asm/arch-davinci/hardware.h |   14 +++-
 board/davinci/da8xxevm/da850evm.c            |  123 ++++++++++++++++++++++++++
 drivers/net/davinci_emac.c                   |    4 +-
 include/configs/da850evm.h                   |   26 +++++-
 5 files changed, 181 insertions(+), 16 deletions(-)

[U-Boot] [PATCH v3 1/8] da850: indicate cache usage disable in config file

[nagabhushana.netagunte at ti.com]

From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>

there are cache coherency issues when using the DAVINCI Ethernet driver,
hence caches cant be used for da850 u-boot. As per new cache management
framework,if the caches are not used in u-boot, it needs to be explicitly
indicated through macros in config file. CACHE disable is  indicated by
the following macro definitions in config file,

1. CONFIG_SYS_ICACHE_OFF
2. CONFIG_SYS_DCACHE_OFF
3. CONFIG_SYS_L2CACHE_OFF

Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
 include/configs/da850evm.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index bbb5a9b..fdcc6e3 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -42,6 +42,9 @@
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_TEXT_BASE		0xc1080000
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_L2CACHE_OFF
 
 /*
  * Memory Info
-- 
1.6.2.4

[U-Boot] [PATCH v3 2/8] da8xx: add support for multiple PLL controllers

[nagabhushana.netagunte at ti.com]

From: Sudhakar Rajashekhara <sudhakar.raj@ti.com>

Modify clk_get() function in cpu file to work for
multiple PLL controllers.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/cpu.c         |   30 ++++++++++++++++---------
 arch/arm/include/asm/arch-davinci/hardware.h |    4 ++-
 2 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 8b57205..b705dfd 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -37,6 +37,7 @@
 #define PLLC_PLLDIV4	0x160
 #define PLLC_PLLDIV5	0x164
 #define PLLC_PLLDIV6	0x168
+#define PLLC_PLLDIV7	0x16c
 #define PLLC_PLLDIV8	0x170
 #define PLLC_PLLDIV9	0x174
 
@@ -61,11 +62,9 @@
 #endif
 
 #ifdef CONFIG_SOC_DA8XX
-const dv_reg * const sysdiv[7] = {
-	&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
-	&davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
-	&davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
-	&davinci_pllc_regs->plldiv7
+unsigned int sysdiv[9] = {
+	PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
+	PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
 };
 
 int clk_get(enum davinci_clk_ids id)
@@ -74,19 +73,27 @@ int clk_get(enum davinci_clk_ids id)
 	int pllm;
 	int post_div;
 	int pll_out;
+	unsigned int pll_base;
 
 	pll_out = CONFIG_SYS_OSCIN_FREQ;
 
 	if (id == DAVINCI_AUXCLK_CLKID)
 		goto out;
 
+	if ((id >> 16) == 1)
+		pll_base = (unsigned int)davinci_pllc1_regs;
+	else
+		pll_base = (unsigned int)davinci_pllc0_regs;
+
+	id &= 0xFFFF;
+
 	/*
 	 * Lets keep this simple. Combining operations can result in
 	 * unexpected approximations
 	 */
-	pre_div = (readl(&davinci_pllc_regs->prediv) &
-		   DAVINCI_PLLC_DIV_MASK) + 1;
-	pllm = readl(&davinci_pllc_regs->pllm) + 1;
+	pre_div = (readl(pll_base + PLLC_PREDIV) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
+	pllm = readl(pll_base + PLLC_PLLM) + 1;
 
 	pll_out /= pre_div;
 	pll_out *= pllm;
@@ -94,15 +101,16 @@ int clk_get(enum davinci_clk_ids id)
 	if (id == DAVINCI_PLLM_CLKID)
 		goto out;
 
-	post_div = (readl(&davinci_pllc_regs->postdiv) &
-		    DAVINCI_PLLC_DIV_MASK) + 1;
+	post_div = (readl(pll_base + PLLC_POSTDIV) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
 
 	pll_out /= post_div;
 
 	if (id == DAVINCI_PLLC_CLKID)
 		goto out;
 
-	pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
+	pll_out /= (readl(pll_base + sysdiv[id - 1]) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
 
 out:
 	return pll_out;
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index f537c4b..646e2ce 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -129,6 +129,7 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_TIMER1_BASE			0x01c21000
 #define DAVINCI_WDOG_BASE			0x01c21000
 #define DAVINCI_PLL_CNTRL0_BASE			0x01c11000
+#define DAVINCI_PLL_CNTRL1_BASE			0x01e1a000
 #define DAVINCI_PSC0_BASE			0x01c10000
 #define DAVINCI_PSC1_BASE			0x01e27000
 #define DAVINCI_SPI0_BASE			0x01c41000
@@ -387,7 +388,8 @@ struct davinci_pllc_regs {
 	dv_reg	emucnt1;
 };
 
-#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
 #define DAVINCI_PLLC_DIV_MASK	0x1f
 
 #define ASYNC3          get_async3_src()
-- 
1.6.2.4

[U-Boot] [PATCH v3 3/8] da850: add NOR boot mode support

[nagabhushana.netagunte at ti.com]

From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>

Add pin-mux support for NOR in board file and correspanding
macros to use NOR boot mode in configuration file.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
 board/davinci/da8xxevm/da850evm.c |   51 +++++++++++++++++++++++++++++++++++++
 include/configs/da850evm.h        |   17 ++++++++++++
 2 files changed, 68 insertions(+), 0 deletions(-)

diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 73eaa48..d3d965c 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -105,6 +105,55 @@ const struct pinmux_config nand_pins[] = {
 	{ pinmux(12), 1, 5 },
 	{ pinmux(12), 1, 6 }
 };
+#elif defined(CONFIG_USE_NOR)
+/* NOR pin muxer settings */
+const struct pinmux_config nor_pins[] = {
+	{ pinmux(5), 1, 6 },
+	{ pinmux(6), 1, 6 },
+	{ pinmux(7), 1, 0 },
+	{ pinmux(7), 1, 4 },
+	{ pinmux(7), 1, 5 },
+	{ pinmux(8), 1, 0 },
+	{ pinmux(8), 1, 1 },
+	{ pinmux(8), 1, 2 },
+	{ pinmux(8), 1, 3 },
+	{ pinmux(8), 1, 4 },
+	{ pinmux(8), 1, 5 },
+	{ pinmux(8), 1, 6 },
+	{ pinmux(8), 1, 7 },
+	{ pinmux(9), 1, 0 },
+	{ pinmux(9), 1, 1 },
+	{ pinmux(9), 1, 2 },
+	{ pinmux(9), 1, 3 },
+	{ pinmux(9), 1, 4 },
+	{ pinmux(9), 1, 5 },
+	{ pinmux(9), 1, 6 },
+	{ pinmux(9), 1, 7 },
+	{ pinmux(10), 1, 0 },
+	{ pinmux(10), 1, 1 },
+	{ pinmux(10), 1, 2 },
+	{ pinmux(10), 1, 3 },
+	{ pinmux(10), 1, 4 },
+	{ pinmux(10), 1, 5 },
+	{ pinmux(10), 1, 6 },
+	{ pinmux(10), 1, 7 },
+	{ pinmux(11), 1, 0 },
+	{ pinmux(11), 1, 1 },
+	{ pinmux(11), 1, 2 },
+	{ pinmux(11), 1, 3 },
+	{ pinmux(11), 1, 4 },
+	{ pinmux(11), 1, 5 },
+	{ pinmux(11), 1, 6 },
+	{ pinmux(11), 1, 7 },
+	{ pinmux(12), 1, 0 },
+	{ pinmux(12), 1, 1 },
+	{ pinmux(12), 1, 2 },
+	{ pinmux(12), 1, 3 },
+	{ pinmux(12), 1, 4 },
+	{ pinmux(12), 1, 5 },
+	{ pinmux(12), 1, 6 },
+	{ pinmux(12), 1, 7 }
+};
 #endif
 
 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
@@ -122,6 +171,8 @@ static const struct pinmux_resource pinmuxes[] = {
 	PINMUX_ITEM(i2c_pins),
 #ifdef CONFIG_NAND_DAVINCI
 	PINMUX_ITEM(nand_pins),
+#elif defined(CONFIG_USE_NOR)
+	PINMUX_ITEM(nor_pins),
 #endif
 };
 
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index fdcc6e3..b1bce11 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -29,6 +29,7 @@
 #define CONFIG_DRIVER_TI_EMAC
 #define CONFIG_USE_SPIFLASH
 
+
 /*
  * SoC Configuration
  */
@@ -129,6 +130,22 @@
 #define CONFIG_NET_MULTI
 #endif
 
+#ifdef CONFIG_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
+#define CONFIG_ENV_SIZE			(10 << 10) /* 10KB */
+#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
+#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
+	       + 3)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
+#endif
+
 #ifdef CONFIG_USE_SPIFLASH
 #undef CONFIG_ENV_IS_IN_FLASH
 #undef CONFIG_ENV_IS_IN_NAND
-- 
1.6.2.4

[U-Boot] [PATCH v3 4/8] da850: modify the U-Boot prompt string

[nagabhushana.netagunte at ti.com]

From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>

Modify U-Boot prompt string from "DA850-evm >" to "U-Boot >".

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
 include/configs/da850evm.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index b1bce11..cf0ceac 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -160,7 +160,7 @@
  * U-Boot general configuration
  */
 #define CONFIG_BOOTFILE		"uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT	"DA850-evm > " /* Command Prompt */
+#define CONFIG_SYS_PROMPT	"U-Boot > " /* Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16 /* max number of command args */
-- 
1.6.2.4

[U-Boot] [PATCH v3 5/8] da850: add support to wake up DSP during board init

[nagabhushana.netagunte at ti.com]

From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>

add support for DSP wake-up by default on DA850/OMAP-L138
during board initialization. Enable hwconfig environment and added
extra env setting through CONFIG_EXTRA_ENV_SETTINGS.
To prevent DSP from being woken up,set the environment variable as,
set hwconfig "dsp:wake=no"

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
 arch/arm/include/asm/arch-davinci/hardware.h |    4 ++
 board/davinci/da8xxevm/da850evm.c            |   59 ++++++++++++++++++++++++++
 include/configs/da850evm.h                   |    3 +
 3 files changed, 66 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 646e2ce..4a3af7d 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -153,7 +153,11 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_DDR_EMIF_DATA_BASE		0xc0000000
 #define DAVINCI_INTC_BASE			0xfffee000
 #define DAVINCI_BOOTCFG_BASE			0x01c14000
+#define DAVINCI_L3CBARAM_BASE			0x80000000
 #define JTAG_ID_REG                            (DAVINCI_BOOTCFG_BASE + 0x18)
+#define CHIP_REV_ID_REG				(DAVINCI_BOOTCFG_BASE + 0x24)
+#define HOST1CFG				(DAVINCI_BOOTCFG_BASE + 0x44)
+#define PSC0_MDCTL				(DAVINCI_PSC0_BASE + 0xa00)
 
 #define GPIO_BANK2_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x38)
 #define GPIO_BANK2_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x3c)
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index d3d965c..8c3d64e 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -30,6 +30,7 @@
 #include <asm/arch/emac_defs.h>
 #include <asm/io.h>
 #include <asm/arch/davinci_misc.h>
+#include <hwconfig.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -163,6 +164,64 @@ const struct pinmux_config nor_pins[] = {
 #endif
 #endif /* CONFIG_DRIVER_TI_EMAC */
 
+void dsp_lpsc_on(unsigned domain, unsigned int id)
+{
+	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
+	struct davinci_psc_regs *psc_regs;
+
+	psc_regs = davinci_psc0_regs;
+	mdstat = &psc_regs->psc0.mdstat[id];
+	mdctl = &psc_regs->psc0.mdctl[id];
+	ptstat = &psc_regs->ptstat;
+	ptcmd = &psc_regs->ptcmd;
+
+	while (*ptstat & (0x1 << domain))
+		;
+
+	if ((*mdstat & 0x1f) == 0x03)
+		return;                 /* Already on and enabled */
+
+	*mdctl |= 0x03;
+
+	*ptcmd = 0x1 << domain;
+
+	while (*ptstat & (0x1 << domain))
+		;
+	while ((*mdstat & 0x1f) != 0x03)
+		;		/* Probably an overkill... */
+}
+
+static void dspwake(void)
+{
+	unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
+	u32 val;
+
+	/* if the device is ARM only, return */
+	if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
+		return;
+
+	if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
+		return;
+
+	*resetvect++ = 0x1E000; /* DSP Idle */
+	/* clear out the next 10 words as NOP */
+	memset(resetvect, 0, sizeof(unsigned) *10);
+
+	/* setup the DSP reset vector */
+	writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
+
+	dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
+	val = readl(PSC0_MDCTL + (15 * 4));
+	val |= 0x100;
+	writel(val, (PSC0_MDCTL + (15 * 4)));
+}
+
+int misc_init_r(void)
+{
+	dspwake();
+	return 0;
+}
+
 static const struct pinmux_resource pinmuxes[] = {
 #ifdef CONFIG_SPI_FLASH
 	PINMUX_ITEM(spi1_pins),
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index cf0ceac..9c92489 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -159,6 +159,7 @@
 /*
  * U-Boot general configuration
  */
+#define CONFIG_MISC_INIT_R
 #define CONFIG_BOOTFILE		"uImage" /* Boot file name */
 #define CONFIG_SYS_PROMPT	"U-Boot > " /* Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
@@ -179,12 +180,14 @@
  * Linux Information
  */
 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_HWCONFIG		/* enable hwconfig */
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_REVISION_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS		\
 	"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
 #define CONFIG_BOOTDELAY	3
+#define CONFIG_EXTRA_ENV_SETTINGS	"hwconfig=dsp:wake=yes"
 
 /*
  * U-Boot commands
-- 
1.6.2.4

[U-Boot] [PATCH v3 6/8] da850: add support for Spectrum Digital AM18xx EVM

[nagabhushana.netagunte at ti.com]

From: Manjunathappa, Prakash <prakash.pm@ti.com>

The AM18xx EVM contains winbond SPI flash instead of ST SPI flash in
comparison with logic PD da850/omap-l138 EVM. So enable configuration
to look for winbond flash.

Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
 include/configs/da850evm.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 9c92489..f6068a2 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -79,6 +79,7 @@
 #define CONFIG_SPI
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
 #define CONFIG_DAVINCI_SPI
 #define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
 #define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
-- 
1.6.2.4

[U-Boot] [PATCH v3 7/8] da850: fix the channel number for EMAC teardown init

[nagabhushana.netagunte at ti.com]

From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>

TX and RX channel numbers programmed as '1' during EMAC
teardown initialization is wrong. This patch fixes the
same by setting channel number to '0' which is used by U-boot.

Signed-off-by: Sugumar Natarajan <sugumar@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
 drivers/net/davinci_emac.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 66c0d13..c0b8929 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -457,7 +457,7 @@ static void davinci_eth_ch_teardown(int ch)
 
 	if (ch == EMAC_CH_TX) {
 		/* Init TX channel teardown */
-		writel(1, &adap_emac->TXTEARDOWN);
+		writel(0, &adap_emac->TXTEARDOWN);
 		do {
 			/*
 			 * Wait here for Tx teardown completion interrupt to
@@ -476,7 +476,7 @@ static void davinci_eth_ch_teardown(int ch)
 		writel(0, &adap_emac->TX0HDP);
 	} else {
 		/* Init RX channel teardown */
-		writel(1, &adap_emac->RXTEARDOWN);
+		writel(0, &adap_emac->RXTEARDOWN);
 		do {
 			/*
 			 * Wait here for Rx teardown completion interrupt to
-- 
1.6.2.4

[U-Boot] [PATCH v3 8/8] da850: modifications for Logic PD Rev.3 AM18xx EVM

[nagabhushana.netagunte at ti.com]

From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>

AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will.

Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
 arch/arm/include/asm/arch-davinci/hardware.h |    4 ++++
 board/davinci/da8xxevm/da850evm.c            |   13 +++++++++++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 4a3af7d..692d507 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -159,6 +159,10 @@ typedef volatile unsigned int *	dv_reg_p;
 #define HOST1CFG				(DAVINCI_BOOTCFG_BASE + 0x44)
 #define PSC0_MDCTL				(DAVINCI_PSC0_BASE + 0xa00)
 
+#define GPIO_BANK0_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x10)
+#define GPIO_BANK0_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x14)
+#define GPIO_BANK0_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x18)
+#define GPIO_BANK0_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x1c)
 #define GPIO_BANK2_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x38)
 #define GPIO_BANK2_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x3c)
 #define GPIO_BANK2_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x40)
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 8c3d64e..2f950e7 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -109,6 +109,8 @@ const struct pinmux_config nand_pins[] = {
 #elif defined(CONFIG_USE_NOR)
 /* NOR pin muxer settings */
 const struct pinmux_config nor_pins[] = {
+	/* GP0[11] is required for NOR to work on Rev 3 EVMs */
+	{ pinmux(0), 8, 4 },	/* GP0[11] */
 	{ pinmux(5), 1, 6 },
 	{ pinmux(6), 1, 6 },
 	{ pinmux(7), 1, 0 },
@@ -278,6 +280,7 @@ u32 get_board_rev(void)
 
 int board_init(void)
 {
+	u32 val;
 #ifndef CONFIG_USE_IRQ
 	irq_init();
 #endif
@@ -325,6 +328,16 @@ int board_init(void)
 	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
 		return 1;
 
+#ifdef CONFIG_USE_NOR
+	/* Set the GPIO direction as output */
+	clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+
+	/* Set the output as low */
+	val = readl(GPIO_BANK0_REG_SET_ADDR);
+	val |= (0x01 << 11);
+	writel(val, GPIO_BANK0_REG_CLR_ADDR);
+#endif
+
 #ifdef CONFIG_DRIVER_TI_EMAC
 	if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
 		return 1;
-- 
1.6.2.4

[U-Boot] [PATCH v3 1/8] da850: indicate cache usage disable in config file

[Ben Gardiner]

Hi,

On Wed, Aug 17, 2011 at 10:14 AM,  <nagabhushana.netagunte@ti.com> wrote:
> From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
>
> there are cache coherency issues when using the DAVINCI Ethernet driver,
> hence caches cant be used for da850 u-boot. As per new cache management
> framework,if the caches are not used in u-boot, it needs to be explicitly
> indicated through macros in config file. CACHE disable is ?indicated by
> the following macro definitions in config file,
>
> 1. CONFIG_SYS_ICACHE_OFF
> 2. CONFIG_SYS_DCACHE_OFF
> 3. CONFIG_SYS_L2CACHE_OFF
>
> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
> ---
> ?include/configs/da850evm.h | ? ?3 +++
> ?1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
> index bbb5a9b..fdcc6e3 100644
> --- a/include/configs/da850evm.h
> +++ b/include/configs/da850evm.h
> @@ -42,6 +42,9 @@
> ?#define CONFIG_SYS_HZ ? ? ? ? ? ? ? ? ?1000
> ?#define CONFIG_SKIP_LOWLEVEL_INIT
> ?#define CONFIG_SYS_TEXT_BASE ? ? ? ? ? 0xc1080000
> +#define CONFIG_SYS_ICACHE_OFF
> +#define CONFIG_SYS_DCACHE_OFF
> +#define CONFIG_SYS_L2CACHE_OFF

I've done plenty of tftp transfers of rootfs and kernel images and
flashed these to the da850evm with the caches enabled and I can't say
I've ever encountered a fatal issue here.

I understand that both Laurence and Stefan (cc'd) have confirmed that
there dcache issues with the EMA; I am assuming that the 'issue'
results in a delay in tftp'ing...

Disabling the caches will slow down decompression which will slow down
boot overall when booting from flash.

Rather than masking the issue by disabling caches and slowing down
u-boot for it's users perhaps TI should be fixing the EMAC drivers'
cache bugs instead?

Best Regards,
Ben Gardiner

---
Nanometrics Inc.
http://www.nanometrics.ca

[U-Boot] [PATCH v3 1/8] da850: indicate cache usage disable in config file

[Laurence Withers]

On Thu, Aug 18, 2011 at 11:13:19AM -0400, Ben Gardiner wrote:
> I understand that both Laurence and Stefan (cc'd) have confirmed that
> there dcache issues with the EMA; I am assuming that the 'issue'
> results in a delay in tftp'ing...

No; the issue was that packets were being sent on to the wire with incorrect
IP checksums. It twigged that the problem was cache coherency when I put a
full hexdump of each outgoing packet in and suddenly the outbound packets
started being valid.

> Disabling the caches will slow down decompression which will slow down
> boot overall when booting from flash.
> 
> Rather than masking the issue by disabling caches and slowing down
> u-boot for it's users perhaps TI should be fixing the EMAC drivers'
> cache bugs instead?

Indeed, the correct solution is to properly manage the net buffers with
respect to the cache, although I have not attempted that change myself. I
have seen some patches start to flow that make changes in drivers to work
correctly with caches enabled, such as
http://lists.denx.de/pipermail/u-boot/2011-August/098484.html .

Bye for now,
-- 
Laurence Withers, <lwithers@guralp.com>                http://www.guralp.com/
Direct tel:+447753988197 or tel:+443333408643               Software Engineer
General support queries: <support@guralp.com>         CMG-DCM CMG-EAM CMG-NAM

[U-Boot] [PATCH v3 1/8] da850: indicate cache usage disable in config file

[Netagunte, Nagabhushana]

Gentlemen,

We will address cache coherency issues soon after these patches.
Earlier also, chache was disabled. Only due to new cache management
Framework which was added recently, it is explicitly needed to be 
Indicated to turn off cache. 

Since fixing the cache coherency issues with EMAC will take some time,
I want this patch to go in mainline so that issue doesn't crop up for
People who use u-boot.

Regards,
Nag
-----Original Message-----
From: Laurence Withers [mailto:lwithers at guralp.com] 
Sent: Thursday, August 18, 2011 8:50 PM
To: Ben Gardiner
Cc: Netagunte, Nagabhushana; u-boot at lists.denx.de; Rajashekhara, Sudhakar; Hadli, Manjunath; Stefan Roese
Subject: Re: [U-Boot] [PATCH v3 1/8] da850: indicate cache usage disable in config file

On Thu, Aug 18, 2011 at 11:13:19AM -0400, Ben Gardiner wrote:
> I understand that both Laurence and Stefan (cc'd) have confirmed that
> there dcache issues with the EMA; I am assuming that the 'issue'
> results in a delay in tftp'ing...

No; the issue was that packets were being sent on to the wire with incorrect
IP checksums. It twigged that the problem was cache coherency when I put a
full hexdump of each outgoing packet in and suddenly the outbound packets
started being valid.

> Disabling the caches will slow down decompression which will slow down
> boot overall when booting from flash.
> 
> Rather than masking the issue by disabling caches and slowing down
> u-boot for it's users perhaps TI should be fixing the EMAC drivers'
> cache bugs instead?

Indeed, the correct solution is to properly manage the net buffers with
respect to the cache, although I have not attempted that change myself. I
have seen some patches start to flow that make changes in drivers to work
correctly with caches enabled, such as
http://lists.denx.de/pipermail/u-boot/2011-August/098484.html .

Bye for now,
-- 
Laurence Withers, <lwithers@guralp.com>                http://www.guralp.com/
Direct tel:+447753988197 or tel:+443333408643               Software Engineer
General support queries: <support@guralp.com>         CMG-DCM CMG-EAM CMG-NAM

[U-Boot] [PATCH v3 0/8] feature additions and fixes for da850

[Netagunte, Nagabhushana]

Denk,

If you have no comments, can you please ACK patches?

Regards,
Nag
On Wed, Aug 17, 2011 at 19:44:07, Netagunte, Nagabhushana wrote:
> From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
> 
> Fix from last version (addressed comments from Detlev)
> 1: fixed env size for NOR boot mode.
> 
> Manjunathappa, Prakash (1):
>   da850: add support for Spectrum Digital AM18xx EVM
> 
> Nagabhushana Netagunte (6):
>   da850: indicate cache usage disable in config file
>   da850: add NOR boot mode support
>   da850: modify the U-Boot prompt string
>   da850: add support to wake up DSP during board init
>   da850: fix the channel number for EMAC teardown init
>   da850: modifications for Logic PD Rev.3 AM18xx EVM
> 
> Sudhakar Rajashekhara (1):
>   da8xx: add support for multiple PLL controllers
> 
>  arch/arm/cpu/arm926ejs/davinci/cpu.c         |   30 ++++---
>  arch/arm/include/asm/arch-davinci/hardware.h |   14 +++-
>  board/davinci/da8xxevm/da850evm.c            |  123 ++++++++++++++++++++++++++
>  drivers/net/davinci_emac.c                   |    4 +-
>  include/configs/da850evm.h                   |   26 +++++-
>  5 files changed, 181 insertions(+), 16 deletions(-)
> 
> 

[U-Boot] [PATCH v3 1/8] da850: indicate cache usage disable in config file

[Netagunte, Nagabhushana]

Gentlemen,

If you have no further comments, can you please ACK patches?

Regards,
Nag

On Mon, Aug 29, 2011 at 16:26:57, Netagunte, Nagabhushana wrote:
> Gentlemen,
> 
> We will address cache coherency issues soon after these patches.
> Earlier also, chache was disabled. Only due to new cache management Framework which was added recently, it is explicitly needed to be Indicated to turn off cache. 
> 
> Since fixing the cache coherency issues with EMAC will take some time, I want this patch to go in mainline so that issue doesn't crop up for People who use u-boot.
> 
> Regards,
> Nag
> -----Original Message-----
> From: Laurence Withers [mailto:lwithers at guralp.com]
> Sent: Thursday, August 18, 2011 8:50 PM
> To: Ben Gardiner
> Cc: Netagunte, Nagabhushana; u-boot at lists.denx.de; Rajashekhara, Sudhakar; Hadli, Manjunath; Stefan Roese
> Subject: Re: [U-Boot] [PATCH v3 1/8] da850: indicate cache usage disable in config file
> 
> On Thu, Aug 18, 2011 at 11:13:19AM -0400, Ben Gardiner wrote:
> > I understand that both Laurence and Stefan (cc'd) have confirmed that 
> > there dcache issues with the EMA; I am assuming that the 'issue'
> > results in a delay in tftp'ing...
> 
> No; the issue was that packets were being sent on to the wire with incorrect IP checksums. It twigged that the problem was cache coherency when I put a full hexdump of each outgoing packet in and suddenly the outbound packets started being valid.
> 
> > Disabling the caches will slow down decompression which will slow down 
> > boot overall when booting from flash.
> > 
> > Rather than masking the issue by disabling caches and slowing down 
> > u-boot for it's users perhaps TI should be fixing the EMAC drivers'
> > cache bugs instead?
> 
> Indeed, the correct solution is to properly manage the net buffers with respect to the cache, although I have not attempted that change myself. I have seen some patches start to flow that make changes in drivers to work correctly with caches enabled, such as http://lists.denx.de/pipermail/u-boot/2011-August/098484.html .
> 
> Bye for now,
> -- 
> Laurence Withers, <lwithers@guralp.com>                http://www.guralp.com/
> Direct tel:+447753988197 or tel:+443333408643               Software Engineer
> General support queries: <support@guralp.com>         CMG-DCM CMG-EAM CMG-NAM
> 

[U-Boot] [PATCH v3 1/8] da850: indicate cache usage disable in config file

[Ben Gardiner]

Nagabhushana,

On Mon, Aug 29, 2011 at 6:56 AM, Netagunte, Nagabhushana
<nagabhushana.netagunte@ti.com> wrote:
>
> Gentlemen,
>
> We will address cache coherency issues soon after these patches.

Ok -- that's great news; we greatly anticipate U-boot improvements for
da850 from TI.

> Earlier also, chache was disabled. Only due to new cache management
> Framework which was added recently, it is explicitly needed to be
> Indicated to turn off cache.

My experience with the ARM-relocation changes on da8xx (which enabled
caches as I understood it) was very positive. I'm sorry I missed the
patch that disabled cache for davinci;

git log --decorate u-boot/master -- board/davinci/
arch/arm/cpu/arm926ejs/davinci/ include/configs/davinci_*
arch/arm/include/asm/arch-davinci doesn't turn up anything related to
caches so the patch (re: 'Earlier also, chache was disabled') is still
in mailing lists?

> Since fixing the cache coherency issues with EMAC will take some time,
> I want this patch to go in mainline so that issue doesn't crop up for
> People who use u-boot.

I certainly don't want anything less than the best user experience for
da850 u-boot.

It's possible that I have not been using caches in u-boot as I thought
I was -- considering I did not experience corrupted frames from the
EMAC.

On Wed, Aug 31, 2011 at 1:39 AM, Netagunte, Nagabhushana
<nagabhushana.netagunte@ti.com> wrote:
> If you have no further comments, can you please ACK patches?

for what it's worth:

Acked-by: Ben Gardiner <bengardiner@nanometrics.ca>


Best Regards,
Ben Gardiner

---
Nanometrics Inc.
+1 (613) 592-6776 x239
http://www.nanometrics.ca