[Qemu-devel] [RFC][PATCH 0/8] NeXT black hardware support

[Qemu-devel] [RFC][PATCH 0/8] NeXT black hardware support

[Bryce Lanham]

Thes patches add NeXT hardware support to QEMU, and are intended to be applied on top of Laurent's work on
the M68k core.

[Qemu-devel] [PATCH 0/8] *** SUBJECT HERE ***

[Bryce Lanham]

*** BLURB HERE ***

Bryce Lanham (8):
  added next source files to Makefile.target
  main next driver, needs a bit of cleanup
  next framebuffer driver, very basic, only supports running under 32
    bit color at the moment
  next keyboard driver, only supports a subset of modifier keys
  partially working network driver, needs more comparison with real
    hardware before it can be made fully working
  adds SFC, DFC, MMU TC, access control register, and user stack
    pointer acces to movec_to/from
  added move16, cinva, pflush instructions, and disabled abort on
    execution of frestore/fsave
  added mmu tc, sfc, dfc, and access control registers to the cpu
    header

 Makefile.target         |    2 +
 hw/next-cube.c          |  471 +++++++++++++++++++++++++++++++++++++++++++
 hw/next-fb.c            |  102 ++++++++++
 hw/next-fb.h            |   14 ++
 hw/next-kbd.c           |  243 ++++++++++++++++++++++
 hw/next-kbd.h           |    2 +
 hw/next-net.c           |  513 +++++++++++++++++++++++++++++++++++++++++++++++
 hw/next-net.h           |    2 +
 target-m68k/cpu.h       |   12 +-
 target-m68k/helper.c    |   44 ++++-
 target-m68k/translate.c |  108 +++++++++-
 11 files changed, 1491 insertions(+), 22 deletions(-)
 create mode 100644 hw/next-cube.c
 create mode 100644 hw/next-fb.c
 create mode 100644 hw/next-fb.h
 create mode 100644 hw/next-kbd.c
 create mode 100644 hw/next-kbd.h
 create mode 100644 hw/next-net.c
 create mode 100644 hw/next-net.h

-- 
1.7.2.3

[Qemu-devel] [PATCH 1/8] added next source files to Makefile.target

[Bryce Lanham]

Signed-off-by: Bryce Lanham <blanham@gmail.com>
---
 Makefile.target |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/Makefile.target b/Makefile.target
index 43624dc..ad0bd6b 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -316,6 +316,7 @@ obj-microblaze-$(CONFIG_FDT) += device_tree.o
 # Boards
 obj-cris-y = cris_pic_cpu.o
 obj-cris-y += cris-boot.o
+obj-cris-y += etraxfs.o axis_dev88.o
 obj-cris-y += axis_dev88.o
 
 # IO blocks
@@ -374,6 +375,7 @@ obj-sh4-y += ide/mmio.o
 obj-m68k-y = an5206.o mcf5206.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
 obj-m68k-y += m68k-semi.o dummy_m68k.o
 obj-m68k-y += m68k_mac.o
+obj-m68k-y += next-cube.o next-kbd.o next-fb.o next-net.o framebuffer.o
 
 obj-s390x-y = s390-virtio-bus.o s390-virtio.o
 
-- 
1.7.2.3

[Qemu-devel] [PATCH 2/8] main next driver, needs a bit of cleanup

[Bryce Lanham]

Signed-off-by: Bryce Lanham <blanham@gmail.com>
---
 hw/next-cube.c |  471 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 471 insertions(+), 0 deletions(-)
 create mode 100644 hw/next-cube.c

diff --git a/hw/next-cube.c b/hw/next-cube.c
new file mode 100644
index 0000000..37e3c17
--- /dev/null
+++ b/hw/next-cube.c
@@ -0,0 +1,471 @@
+/*
+ * Next Cube System Driver
+ * Copyright (c) 2011 Bryce Lanham
+ *
+ * Based on dummy_m68k.c Copyright (c) 2007 CodeSourcery.
+ *
+ * Scr2 code from Previous, used under the GPL
+ *
+ * This code is licensed under the GPL
+ */
+
+
+#include "hw.h"
+#include "next-fb.h"
+#include "next-kbd.h"
+#include "next-net.h"
+
+#include "monitor.h"
+#include "sysemu.h"
+#include "boards.h"
+#include "console.h"
+#include "loader.h"//probably not needed
+#include "elf.h"
+#include "esp.h" //SCSI ESP should work out of the box
+#include "escc.h" //ZILOG 8530 Serial Emulation
+#define ENTRY 0x0100001e
+
+/* Board init.  */
+#define ROM_FILE "rom66.bin"
+/* these need to be in machine state */
+uint32_t scr1 = 0;
+uint32_t scr2 = 0;
+uint32_t int_status = 4;//from previous
+uint32_t int_mask = 0;
+uint32_t event_test = 0;
+/* Thanks to NeXT forums for this */
+uint8_t rtc_ram3[32]={
+0x94,0x0f,0x40,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xfb,0x6d,0x00,0x00,0x7B,0x00,
+0x00,0x00,0x65,0x6e,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x50,0x13
+};
+uint8_t *rtc_ram;
+uint8_t rtc_ram2[32]={
+0x94,0x0f,0x40,0x03,0x00,0x00,0x00,0x00,
+0x00,0x00,0xfb,0x6d,0x00,0x00,0x4b,0x00,
+0x41,0x00,0x20,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x84,0x7e,
+};
+
+next_state_t next_state;
+
+static uint32_t mmio_readb(void*opaque, target_phys_addr_t addr);
+static uint32_t mmio_readw(void*opaque, target_phys_addr_t addr);
+static uint32_t mmio_readl(void*opaque, target_phys_addr_t addr);
+
+static void mmio_writeb(void*opaque, target_phys_addr_t addr, uint32_t val);
+static void mmio_writew(void*opaque, target_phys_addr_t addr, uint32_t val);
+static void mmio_writel(void*opaque, target_phys_addr_t addr, uint32_t val);
+static CPUReadMemoryFunc *mmio_read[3] = {
+	mmio_readb,
+	mmio_readw,
+	mmio_readl
+};
+
+static CPUWriteMemoryFunc *mmio_write[3] = {
+	mmio_writeb,
+	mmio_writew,
+	mmio_writel
+};
+static uint32_t mmio_readb(void*opaque, target_phys_addr_t addr)
+{
+	switch(addr)
+	{
+		case 0xc002:
+		return (scr1 >> 8) & 0xFF;
+		case 0xc0008:
+		return 0xff;//hack to hide memory error
+		default:
+	        fprintf(stderr,"MMIO Read B @ %x\n",addr);
+        return 0x0;
+    }
+}
+static uint32_t mmio_readw(void*opaque, target_phys_addr_t addr)
+{
+	switch(addr)
+	{
+        default:
+	    fprintf(stderr,"MMIO Read W @ %x\n",addr);
+        return 0x0;
+    }
+}
+
+static uint32_t mmio_readl(void*opaque, target_phys_addr_t addr)
+{
+
+	switch(addr)
+	{
+        case 0x7000:
+	//	fprintf(stderr,"INTSTAT\n");
+        return int_status;
+	
+    	case 0x7800:
+		//fprintf(stderr,"INTMASK\n");
+		return int_mask;
+	
+    	case 0xc000:
+	//	fprintf(stderr, "SCR1 Read: @ %X\n",((CPUM68KState *)opaque)->pc);
+		return scr1;
+	
+    	case 0xd000:
+	//	fprintf(stderr, "SCR2 Read: @ %X %X\n",((CPUM68KState *)opaque)->pc,scr2);
+		return scr2;
+		
+		case 0xc0000:
+		return 0x01;	
+       	
+		case 0xc0034:
+		return 0x560;
+ 		
+		default:
+		fprintf(stderr,"MMIO Read L @ %x\n",addr);
+		return 0x0;
+	}
+}
+static void mmio_writeb(void*opaque, target_phys_addr_t addr, uint32_t val)
+{
+	
+	switch(addr)
+	{
+		default:
+		fprintf(stderr,"MMIO Write B @ %x with %x\n",addr,val);
+	}
+
+}
+static void mmio_writew(void*opaque, target_phys_addr_t addr, uint32_t val)
+{
+	fprintf(stderr,"MMIO Write W\n"	);
+}
+int led = 0;
+
+static void mmio_writel(void*opaque, target_phys_addr_t addr, uint32_t val)
+{
+	static int phase = 0;
+	static uint8_t old_scr2;
+	static uint8_t rtc_command = 0;
+	static uint8_t rtc_value = 0;
+	static uint8_t rtc_status = 0x90;
+	static uint8_t rtc_return = 0;
+	uint8_t scr2_2; 
+    switch(addr)
+	{
+		case 0x10:
+        break;
+        case 0x7000:
+		fprintf(stderr,"INT Status old: %x new: %x\n",int_status,val);
+        int_status = val;
+		break;
+		case 0x7800:
+		fprintf(stderr,"INT Status old: %x new: %x\n",int_mask,val);
+		int_mask  = val;
+		break;
+		case 0xc000:
+		fprintf(stderr, "SCR1 Write: %x @ %X\n",val,((CPUM68KState *)opaque)->pc);
+		break;
+		case 0xd000:
+		//old_scr2 = val;
+		scr2_2 = (val >> 8) & 0xFF;
+			if(val &0x1)
+		{	
+			printf("fault!\n");
+			led++;
+			if(led == 10)
+			{
+				fprintf(stderr,"LED flashing, possible fault, pausing emulation\n");
+				led = 0;
+				vm_stop(VMSTOP_DEBUG);
+			}
+
+		}
+		
+		if (scr2_2& 0x1) {
+		//	fprintf(stderr,"RTC %x phase %i\n",scr2_2,phase);
+			if (phase==-1) phase=0;
+				// if we are in going down clock... do something
+				#define SCR2_RTCLK 0x2
+				#define SCR2_RTDATA 0x4
+				if (((old_scr2&SCR2_RTCLK)!=(scr2_2&SCR2_RTCLK)) && ((scr2_2&SCR2_RTCLK)==0) ) {
+					if (phase<8)
+						rtc_command=(rtc_command<<1)|((scr2_2&SCR2_RTDATA)?1:0);
+					if ((phase>=8) && (phase<16)) {
+						rtc_value=(rtc_value<<1)|((scr2_2&SCR2_RTDATA)?1:0);
+			
+					// if we read RAM register, output RT_DATA bit
+					if (rtc_command<=0x1F) {
+						scr2_2=scr2_2&(~SCR2_RTDATA);
+					if (rtc_ram[rtc_command]&(0x80>>(phase-8)))
+						scr2_2 |=SCR2_RTDATA;
+				
+					rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
+				}
+					// read the status 0x30
+					if (rtc_command==0x30) {
+						scr2_2=scr2_2&(~SCR2_RTDATA);
+						// for now status = 0x98 (new rtc + FTU)
+						if (rtc_status&(0x80>>(phase-8)))
+							scr2_2|=SCR2_RTDATA;
+					
+						rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
+					}
+					// read the status 0x31
+					if (rtc_command==0x31) {
+						scr2_2=scr2_2&(~SCR2_RTDATA);
+					// for now 0x00
+					if (0x00&(0x80>>(phase-8)))
+						scr2_2|=SCR2_RTDATA;
+					rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
+				}
+			
+				if ((rtc_command>=0x20) && (rtc_command<=0x2F)) {
+					scr2_2=scr2_2&(~SCR2_RTDATA);
+					// for now 0x00
+					if (0x00&(0x80>>(phase-8)))
+						scr2_2|=SCR2_RTDATA;
+					rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
+				}
+			
+			}
+		
+			phase++;
+				if (phase==16) {
+		//	fprintf(stderr,"SCR2 RTC command complete %x %x %x at PC=$%08x\n",
+		//	rtc_command,rtc_value,rtc_return,0);
+						if ((rtc_command>=0x80) && (rtc_command<=0x9F))
+                        {
+							rtc_ram[rtc_command-0x80]=rtc_value;
+                            #ifdef READ_RTC
+							FILE *fp = fopen("rtc.ram","wb+");
+                            int ret = fwrite(rtc_ram,1,32,fp);
+							if(ret != 32)
+									abort();
+                            fclose(fp);
+							#endif
+                        }
+						// write to x30 register
+						if (rtc_command==0xB1) {
+						// clear FTU
+						if (rtc_value & 0x04) {
+							rtc_status=rtc_status&(~0x18);
+							int_status=int_status&(~0x04);
+						}
+					}		
+				}
+			}
+		} else {
+						// else end or abort
+						phase=-1;
+						rtc_command=0;
+						rtc_value=0;
+		}
+		scr2 = val & 0xFFFF00FF;
+		scr2 |= scr2_2<< 8;	
+		old_scr2 = scr2_2;
+
+		break;
+		case 0xc0034:
+	//	if(val == 0x90000560)
+	//	vm_stop(VMSTOP_DEBUG);
+		default:
+			fprintf(stderr,"MMIO Write l @ %x with %x\n",addr,val);
+
+	}
+}
+
+
+static uint32_t scr_readb(void*opaque, target_phys_addr_t addr);
+static uint32_t scr_readw(void*opaque, target_phys_addr_t addr);
+static uint32_t scr_readl(void*opaque, target_phys_addr_t addr);
+static CPUReadMemoryFunc *scr_read[3] = {
+	scr_readb,
+	scr_readw,
+	scr_readl
+
+};
+
+static void scr_writeb(void*opaque, target_phys_addr_t addr, uint32_t value);
+static void scr_writew(void*opaque, target_phys_addr_t addr, uint32_t value);
+static void scr_writel(void*opaque, target_phys_addr_t addr, uint32_t value);
+static CPUWriteMemoryFunc * const scr_write[3] = {
+	scr_writeb,
+	scr_writew,
+	scr_writel
+};
+
+static uint32_t scr_readb(void*opaque, target_phys_addr_t addr)
+{
+ //   CPUState *s = (CPUState *)opaque;
+    switch(addr)
+    {
+        
+        case 0x14000: case 0x14005:
+        fprintf(stderr,"SCSI read b\n");
+        return 0x0;
+        
+        case 0x14104://FDD
+      //  return 0x0;
+        
+        case 0x14108:
+        return 0x0;
+        
+        case 0x18001: 
+	//	fprintf(stderr, "SCC @ %X\n",((CPUM68KState *)opaque)->pc);
+        return 0;
+        case 0x1a000:
+    //    return 0;
+        case 0x1a001: 
+     //   return 0;
+        case 0x1a002: 
+       // return 0;
+        case 0x1a003: 
+     //   fprintf(stderr,"event #%x @ %x\n",addr &0x3,s->pc);
+       // event_test++;
+      // if(event_test == 200) event_test = 0;
+        return event_test; 
+        default:
+        fprintf(stderr,"BMAP Read B @ %x\n",addr);
+        return 0;
+    }
+    return 0;
+}
+static uint32_t scr_readw(void*opaque, target_phys_addr_t addr)
+{
+	fprintf(stderr,"S Read W @ %x\n",addr);
+	return 0;
+}
+static uint32_t scr_readl(void*opaque, target_phys_addr_t addr)
+{
+	fprintf(stderr,"SRead L @ %x\n",addr);
+	return 0;
+}
+static void scr_writeb(void*opaque, target_phys_addr_t addr, uint32_t value)
+{
+    switch(addr)
+    {
+        case 0x10000: break;//Screen brightness
+        case 0x18000:
+        case 0x18001:
+        case 0x18004:
+        break;
+    	default:
+        fprintf(stderr,"BMAP Write B @ %x with %x\n",addr,value);
+    }
+}
+static void scr_writew(void*opaque, target_phys_addr_t addr, uint32_t value)
+{
+	fprintf(stderr,"SWrite w @ %x with %x\n",addr,value);
+}
+static void scr_writel(void*opaque, target_phys_addr_t addr, uint32_t value)
+{
+
+	fprintf(stderr,"SWrite l @ %x with %x\n",addr,value);
+}
+
+/* need to make more defines, put them into a header */
+#define RAM_SIZE 0x4000000
+
+void serial_irq(void *opaque, int n, int level);
+static void next_cube_init(ram_addr_t ram_size,
+                     const char *boot_device,
+                     const char *kernel_filename, const char *kernel_cmdline,
+                     const char *initrd_filename, const char *cpu_model)
+{
+    /* Initialize the cpu core */ 
+    CPUState *env = cpu_init("m68040");
+    if (env == NULL) {
+        fprintf(stderr, "Unable to find m68k CPU definition\n");
+        exit(1);
+    }
+    
+    /* Initialize CPU registers.  */
+    env->vbr = 0;
+    env->pc  = 0x100001e; //technically should read vector
+    env->sr  = 0x2700;
+    
+    /* Set internal registers to initial values */
+	scr1 = 0x01000220;
+    scr2 = 0x00ff8880;
+    
+    int_mask = 0x88027640; 
+    int_status= 0x200;
+    
+    /* Load RTC ram,  needs to be in a function probably */
+    { 
+	   	rtc_ram = malloc(32);
+       	#ifdef LOAD_RTC
+        FILE *fp = fopen("rtc.ram","rb");
+        if(fread(rtc_ram,1,32,fp) != 32)
+            abort();
+        fclose(fp);
+		#endif
+        memcpy(rtc_ram,rtc_ram2,32);
+    }
+
+
+    /* 64MB RAM starting at 0x4000000  */
+    cpu_register_physical_memory(0x4000000, RAM_SIZE,
+        qemu_ram_alloc(NULL, "next-cube.ram", RAM_SIZE) | IO_MEM_RAM);
+  
+	/* Framebuffer */
+    nextfb_init(&next_state);
+ 
+    /* MMIO */
+	cpu_register_physical_memory((uint32_t)0x2000000,0xD0000,
+        cpu_register_io_memory(mmio_read,mmio_write, (void *)env,DEVICE_NATIVE_ENDIAN));    
+    
+    /* BMAP */ //acts as a catch-all for now
+    cpu_register_physical_memory((uint32_t)0x2100000,0x3A7FF,
+        cpu_register_io_memory(scr_read,scr_write, (void *)env,DEVICE_NATIVE_ENDIAN));
+    
+    /* KBD */
+    nextkbd_init((void *)env);
+
+    /* Serial */
+   	//CharDriverState *console = text_console_init(NULL);
+  	//qemu_irq *serial = qemu_allocate_irqs(serial_irq, env, 2);
+  	//escc_init(0x2118000, serial[0], serial[1],
+    //        console, NULL,   (9600*384),0);
+
+  	
+    /* Load ROM here */	 
+    if(get_image_size(ROM_FILE) != 0x20000)
+    {
+        fprintf(stderr,"Failed to load rom file!\n");
+        exit(1);
+    }
+    
+    rom_add_file_fixed(ROM_FILE,0x1000000,0);
+    rom_add_file_fixed(ROM_FILE,0x000000,1);
+	cpu_register_physical_memory((uint32_t)0x1000000, 0x20000,
+        qemu_ram_alloc(NULL, "next.rom", 0x20000) | IO_MEM_ROM);
+		cpu_register_physical_memory((uint32_t)0x000000, 0x20000,
+        qemu_ram_alloc(NULL, "nex.rom", 0x20000) | IO_MEM_ROM);
+
+	/* Ethernet */
+    nextnet_init((void *)env);
+
+    
+}
+
+void serial_irq(void *opaque, int n, int level)
+{
+  //  fprintf(stderr,"IRQQQQQ\n");
+ //   int_status |= 0xFFFFFF00;
+//	int_status |= 1<<17;
+//CPUM68KState *env = (CPUM68KState *)opaque;
+//env->exception_index = 10;
+//m68k_set_irq_level((CPUM68KState *)opaque, 5,29);//25);
+
+}
+static QEMUMachine next_machine = {
+    .name = "next-cube",
+    .desc = "NeXT Cube",
+    .init = next_cube_init,
+};
+
+static void next_machine_init(void)
+{
+    qemu_register_machine(&next_machine);
+}
+
+machine_init(next_machine_init);
-- 
1.7.2.3

[Qemu-devel] [PATCH 3/8] next framebuffer driver, very basic, only supports running under 32 bit color at the moment

[Bryce Lanham]

Signed-off-by: Bryce Lanham <blanham@gmail.com>
---
 hw/next-fb.c |  102 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/next-fb.h |   14 ++++++++
 2 files changed, 116 insertions(+), 0 deletions(-)
 create mode 100644 hw/next-fb.c
 create mode 100644 hw/next-fb.h

diff --git a/hw/next-fb.c b/hw/next-fb.c
new file mode 100644
index 0000000..0cccae3
--- /dev/null
+++ b/hw/next-fb.c
@@ -0,0 +1,102 @@
+/*
+ * NeXT Cube/Staion Framebuffer Emulation
+ *
+ * Copyright (c) 2011 Bryce Lanham
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "loader.h"
+#include "console.h"
+#include "framebuffer.h"
+#define BITS 8
+#include "pixel_ops.h"
+#include "next-fb.h"
+/*
+typedef struct NextVGAState {
+    VGACommonState vga;
+    target_phys_addr_t vram_base;
+	};*/
+//need a function to register the mm i/o for fb and to register vram
+
+void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s, int width, int pitch)
+{
+    uint32_t pal[4] = {0xFFFFFFFF, 0xFFAAAAAA, 0xFF555555,0xFF000000};
+    uint32_t*buf = qemu_malloc(1120*4);
+    int i = 0;
+    for(;i<280; i++)
+    {
+        int j=i*4;
+        uint8_t src = s[i];
+        buf[j+3]= pal[src & 0x3];
+        src >>=2;
+        buf[j+2]= pal[src & 0x3];
+        src >>=2;
+        buf[j+1]= pal[src & 0x3];
+        src >>=2;
+        buf[j+0]= pal[src & 0x3];
+    }
+	
+    memcpy(d,buf,1120*4);
+	free(buf);
+}
+
+
+static void nextfb_update(void * opaque)
+{
+	next_state_t *s = (next_state_t *)opaque;
+	DisplaySurface *info = s->ds->surface;
+
+	
+	
+	int dest_width = 4;
+	int src_width;
+	int first = 0;
+	int last  = 0;
+	src_width = s->cols = 1120;
+	src_width = 288;
+	dest_width = 1120;
+  	dest_width = info->linesize;
+	framebuffer_update_display(s->ds,
+							0xB000000,1120,832,
+							src_width,dest_width, 0,
+							1,
+							nextfb_draw_line,
+							NULL,
+							&first, &last);
+
+	dpy_update(s->ds,0,0,1120,832);	
+}
+
+static void nextfb_invalidate(void *opaque)
+{
+}
+
+void nextfb_init(next_state_t *s)
+{
+    s->ds = graphic_console_init(nextfb_update,nextfb_invalidate, NULL, NULL, s);
+	qemu_console_resize(s->ds,1120,832);	
+	s->cols = 1120;
+	s->rows = 832;
+	s->invalidate = 1;
+
+    cpu_register_physical_memory(0xB000000, 0x1CB100, 
+        qemu_ram_alloc(NULL,"next-vram.ram",0x1CB100) | IO_MEM_RAM);
+
+}
diff --git a/hw/next-fb.h b/hw/next-fb.h
new file mode 100644
index 0000000..9d2b547
--- /dev/null
+++ b/hw/next-fb.h
@@ -0,0 +1,14 @@
+typedef struct {
+	DisplayState *ds;
+	uint32_t base;
+	uint32_t pitch;
+	uint32_t cols;
+	uint32_t rows;
+	int invalidate;
+
+
+} next_state_t;
+
+void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s, int width, int pitch);
+
+void nextfb_init(next_state_t *s);
-- 
1.7.2.3

[Qemu-devel] [PATCH 4/8] next keyboard driver, only supports a subset of modifier keys

[Bryce Lanham]

Signed-off-by: Bryce Lanham <blanham@gmail.com>
---
 hw/next-kbd.c |  243 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/next-kbd.h |    2 +
 2 files changed, 245 insertions(+), 0 deletions(-)
 create mode 100644 hw/next-kbd.c
 create mode 100644 hw/next-kbd.h

diff --git a/hw/next-kbd.c b/hw/next-kbd.c
new file mode 100644
index 0000000..31bda7d
--- /dev/null
+++ b/hw/next-kbd.c
@@ -0,0 +1,243 @@
+/*
+ * QEMU NeXT Keyboard/Mouse emulation
+ *
+ * Copyright (c) 2011 Bryce Lanham
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* This is admittedly hackish, but works well enough for basic input
+   Mouse support will be added once we can boot something that needs
+	the mouse. */ 
+
+#include "hw.h"
+#include "console.h"
+#include "next-kbd.h"
+
+/* debug NeXT keyboard */
+//#define DEBUG_KBD
+
+#ifdef DEBUG_KBD
+#define DPRINTF(fmt, ...)                                       \
+    do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0);
+#else
+#define DPRINTF(fmt, ...)
+#endif
+/* follwoing defintions from next68k netbsd */
+#define CSR_INT 0x00800000
+#define CSR_DATA 0x00400000
+
+#define KD_KEYMASK              0x007f
+#define KD_DIRECTION            0x0080 /* pressed or released */
+#define KD_CNTL                 0x0100
+#define KD_LSHIFT               0x0200
+#define KD_RSHIFT               0x0400
+#define KD_LCOMM                0x0800
+#define KD_RCOMM                0x1000
+#define KD_LALT                 0x2000
+#define KD_RALT                 0x4000
+#define KD_VALID                0x8000 /* only set for scancode keys ? */
+#define KD_MODS                 0x4f00
+
+#define KBD_QUEUE_SIZE 256
+
+typedef struct {
+    uint8_t data[KBD_QUEUE_SIZE];
+    int rptr, wptr, count;
+} KBDQueue;
+
+
+typedef struct KBDState {
+    KBDQueue queue;
+    uint8_t blank;
+    int shift;//make this an unsigned short, and set it to the modifier value
+
+} KBDState;
+KBDState *kbd_env;
+static void nextkbd_event(void *opaque, int ch);
+
+static void queue_code(void *opaque, int code);
+static uint32_t kbd_read_byte(void *opaque, target_phys_addr_t addr);
+static uint32_t kbd_read_word(void *opaque, target_phys_addr_t addr);
+static uint32_t kbd_read_long(void *opaque, target_phys_addr_t addr);
+
+static void kbd_write_byte(void *opaque, target_phys_addr_t addr, uint32_t val);
+static void kbd_write_word(void *opaque, target_phys_addr_t addr, uint32_t val);
+static void kbd_write_long(void *opaque, target_phys_addr_t addr, uint32_t val);
+
+static CPUWriteMemoryFunc *kbd_write[3] = {
+    kbd_write_byte,
+    kbd_write_word,
+    kbd_write_long
+};
+static CPUReadMemoryFunc *kbd_read[3] = {
+    kbd_read_byte,
+    kbd_read_word,
+    kbd_read_long
+};
+
+
+
+
+void nextkbd_init(void *opaque)
+{
+	KBDState *s = qemu_mallocz(sizeof(KBDState));
+    
+	s->shift = 0;
+	
+	int kbd_addr = cpu_register_io_memory(kbd_read,kbd_write, (void *)s,DEVICE_NATIVE_ENDIAN);
+	
+	cpu_register_physical_memory((uint32_t)0x200e000,0x1000,kbd_addr);//from netbsd's cpu.h
+
+    qemu_add_kbd_event_handler(nextkbd_event, s);
+}
+
+static uint32_t kbd_read_byte(void *opaque, target_phys_addr_t addr)
+{
+    addr = addr & 0xe003;
+    switch(addr)
+    {
+    	
+        case 0xe000:
+		return 0x80|0x20;
+		
+        case 0xe001:
+		return 0x80|0x40|0x20|0x10;
+		
+        case 0xe002:
+		return 0x40|0x10|0x2|0x1;
+
+        default:
+        DPRINTF("RB ADDR %x\n",addr);
+        return 0;
+    }
+    return 0;
+}
+static uint32_t kbd_read_word(void *opaque, target_phys_addr_t addr)
+{
+    DPRINTF("RW ADDR %x\n",addr);
+    return 0;
+}
+static uint32_t kbd_read_long(void *opaque, target_phys_addr_t addr)
+{
+    int key = 0;
+    KBDState *s = (KBDState *)opaque;
+    KBDQueue *q = &s->queue;
+    switch(addr & 0xe00f)
+	{
+    	case 0xe000:
+	//	fprintf(stderr,"KB L Read: @ %X\n",((CPUM68KState *)opaque)->pc);
+		return 0xA0F09300;
+        
+        case 0xe008:
+        /* get keycode from buffer */
+        if(q->count > 0)
+        {
+            
+        key = q->data[q->rptr];
+        if (++q->rptr == KBD_QUEUE_SIZE)
+            q->rptr = 0;
+
+            q->count--;
+            
+          
+            if(s->shift)
+            key |= KD_LSHIFT;
+            if(key & 0x80)
+            return 0;
+            else
+            return 0x10000000 | KD_VALID | key;
+        }
+        else
+            return 0;
+    //    return 0x10009026;		
+        
+        default:
+        DPRINTF("RL ADDR %x\n",addr);
+        return 0;
+    }
+}
+
+static void kbd_write_byte(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+    //DPRINTF("WB ADDR %x\n",addr);
+}
+static void kbd_write_word(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+    DPRINTF("WW ADDR %x\n",addr);
+}
+static void kbd_write_long(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+   // DPRINTF("WL ADDR %x\n",addr);
+}
+
+
+static void nextkbd_event(void *opaque, int ch)
+{
+    /*will want to set vars for caps/num lock*/
+    /*if (ch & 0x80) -> key release */
+   /* there's also e0 escaped scancodes that might need to be handled */ 
+     DPRINTF("EVENT %X\n",ch);
+ 
+    queue_code(opaque, ch);
+   
+}
+
+static const unsigned char next_keycodes[128] = {
+  0,    0x49, 0x4A,  0x4B,  0x4C,  0x4D,  0x50,  0x4F,  0x4E,  0x1E,  0x1F,  0x20,  0x1D,  0x1C, 0x1B,  0,
+  0x42, 0x43, 0x44,  0x45,  0x48,  0x47,  0x46,  0x06,  0x07,  0x08,  0x0,  0,  0x2A,  0, 0x39,  0x3A,
+  0x3B,  0x3C,  0x3D,  0x40,  0x3F,  0x3E,  0x2D,  0x2C,  0x2B,  0x26,  0,  0,  0x31,  0x32, 0x33,  0x34,
+  0x35,  0x37,  0x36,  0x2e,  0x2f,  0x30,  0,  0,  0,  0x38,  0,  0,  0,  0, 0,  0,
+  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, 0,  0,
+  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, 0,  0,
+  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, 0,  0,
+  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, 0,  0
+};
+
+static void queue_code(void *opaque, int code)
+{
+
+    KBDState *s = (KBDState *)opaque;
+    KBDQueue *q = &s->queue;
+    int key = code & 0x7F;
+    int release = code & 0x80;
+      if(code == 0x2A)
+            {
+                s->shift = 1;
+                return;
+            }
+            else if(code == (0x2A | 0x80))
+            {
+                s->shift = 0;
+                return;
+            }
+
+
+
+
+    if (q->count >= KBD_QUEUE_SIZE)
+        return;
+    
+    q->data[q->wptr] = next_keycodes[key] | release;
+    if (++q->wptr == KBD_QUEUE_SIZE)
+        q->wptr = 0;
+    q->count++;
+    //s->update_irq(s->update_arg, 1);
+    s->blank += 1;
+}
diff --git a/hw/next-kbd.h b/hw/next-kbd.h
new file mode 100644
index 0000000..efee144
--- /dev/null
+++ b/hw/next-kbd.h
@@ -0,0 +1,2 @@
+
+void nextkbd_init(void *opaque);
-- 
1.7.2.3

[Qemu-devel] [PATCH 5/8] partially working network driver, needs more comparison with real hardware before it can be made fully working

[Bryce Lanham]

Signed-off-by: Bryce Lanham <blanham@gmail.com>
---
 hw/next-net.c |  513 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/next-net.h |    2 +
 2 files changed, 515 insertions(+), 0 deletions(-)
 create mode 100644 hw/next-net.c
 create mode 100644 hw/next-net.h

diff --git a/hw/next-net.c b/hw/next-net.c
new file mode 100644
index 0000000..94739a1
--- /dev/null
+++ b/hw/next-net.c
@@ -0,0 +1,513 @@
+/*
+ * QEMU NeXT Network (MB8795) emulation
+ *
+ * Copyright (c) 2011 Bryce Lanham
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "sysemu.h"//only needed for vm_stop
+#include "hw.h"
+#include "net.h"
+#include "next-net.h"
+#include "sysbus.h"
+/* debug NeXT ethernet */
+#define DEBUG_NET
+
+#ifdef DEBUG_NET
+#define DPRINTF(fmt, ...)                                       \
+    do { printf("NET: " fmt , ## __VA_ARGS__); } while (0);
+#else
+#define DPRINTF(fmt, ...)
+#endif
+    
+/* IRQs should be moved to header later */
+#define TX_I_DMA 0
+#define RX_I_DMA 1
+#define TX_I 	 2
+#define RX_I     3
+/* names could be better */
+typedef struct NextDMA {
+	uint32_t csr;
+	uint32_t savedbase;
+	uint32_t savedlimit;
+	
+    uint32_t baser;
+    uint32_t base;
+    uint32_t limit;
+    uint32_t chainbase;
+    uint32_t chainlimit;
+	uint32_t basew;
+
+	
+} NextDMA;
+
+typedef struct NextNetState {
+    uint8_t mac[6];
+    
+    qemu_irq *irq;
+    
+    NICState *nic;
+    NICConf c;
+	
+    NextDMA tx_dma;
+	uint8_t tx_stat;
+	uint8_t tx_mask;
+    uint8_t tx_mode;
+	
+    NextDMA rx_dma;
+    uint8_t rx_stat;
+    uint8_t rx_mask;
+    uint8_t rx_mode;
+
+    uint8_t rst_mode;
+
+} NextNetState;
+
+NextNetState nextnet_state;
+
+void *env_g;
+
+void nextnet_irq(void *opaque, int n, int level);
+static int nextnet_can_rx(VLANClientState *nc);
+static ssize_t nextnet_rx(VLANClientState *nc, const uint8_t *buf, size_t size);
+static void nextnet_cleanup(VLANClientState *nc);
+
+static NetClientInfo nextnet_info = {
+    .type = NET_CLIENT_TYPE_NIC,
+    .size = sizeof(NICState),
+    .can_receive = nextnet_can_rx,
+    .receive = nextnet_rx,
+    .cleanup = nextnet_cleanup,
+};
+/* these need to be somewhere else */
+extern uint32_t int_status;//should be set in a global irq handler
+extern uint32_t int_mask;
+extern uint32_t event_test;
+
+void nextnet_reset(NextNetState *s);
+void nextnet_reset(NextNetState *s)
+{
+
+
+}
+
+static uint32_t net_readb(void*opaque, target_phys_addr_t addr);
+static uint32_t net_readw(void*opaque, target_phys_addr_t addr);
+static uint32_t net_readl(void*opaque, target_phys_addr_t addr);
+static CPUReadMemoryFunc *net_read[3] = {
+	net_readb,
+	net_readw,
+	net_readl
+};
+
+static void net_writeb(void*opaque, target_phys_addr_t addr, uint32_t value);
+static void net_writew(void*opaque, target_phys_addr_t addr, uint32_t value);
+static void net_writel(void*opaque, target_phys_addr_t addr, uint32_t value);
+static CPUWriteMemoryFunc * const net_write[3] = {
+	net_writeb,
+	net_writew,
+	net_writel
+};
+
+
+void nextnet_init(void *opaque)
+{
+    NextNetState *s = &nextnet_state;
+	CPUState *env = (CPUState *)opaque; 
+    env_g = opaque;//used this as a global during testing, should be removed
+    
+	/*register device register space */
+    cpu_register_physical_memory((uint32_t)0x2106000,0x1000,
+        cpu_register_io_memory(net_read,net_write, (void *)&nextnet_state,DEVICE_NATIVE_ENDIAN));
+  cpu_register_physical_memory((uint32_t)0x2006000,0x1000,
+        cpu_register_io_memory(net_read,net_write, (void *)&nextnet_state,DEVICE_NATIVE_ENDIAN));
+
+
+    /* and ethernet control/status registers *///including DMA for now, will seperate out later
+    cpu_register_physical_memory((uint32_t)0x2000110,0x4400,
+        cpu_register_io_memory(net_read,net_write, (void *)&nextnet_state,DEVICE_NATIVE_ENDIAN));
+
+    /* connect to virtual lan */
+    s->c.vlan = qemu_find_vlan(0,1); 
+    
+    /* register nic */
+    s->nic = qemu_new_nic(&nextnet_info,&s->c, "NeXT MB8795\0", NULL, s);
+
+    /* this needs to be read, will have to load rom file i guess */
+    uint8_t mac[6] = {0,0,0xf,0,0xf3,0x2};
+    memcpy(&s->mac,mac,6); 	
+    
+	/* allocate TX/RX and DMA irqs - will be global later */
+    s->irq = qemu_allocate_irqs(nextnet_irq, env, 4);
+    
+    /* this sets the nic's info */
+    qemu_format_nic_info_str(&s->nic->nc, mac);
+
+
+}
+/* It is likely that all register reads are bytes, while all CSR r/w are longs */
+static uint32_t net_readb(void*opaque, target_phys_addr_t addr)
+{
+    NextNetState *s = (NextNetState *)opaque;
+    
+//	CPUState *env = (CPUState *)env_g; 
+    switch(addr)
+    {
+        case 0x6000://TXSTAT
+            // DPRINTF("TXSTAT \tRead\n");
+            return s->tx_stat;
+        
+        case 0x6001:
+            DPRINTF("TXMASK \tRead\n");
+            return s->tx_mask;
+
+        case 0x6002:
+          //  DPRINTF("RXSTAT \tRead  %x @ %x\n",s->rx_stat,env->pc);
+            return s->rx_stat;
+
+        case 0x6003:
+          //  DPRINTF("RXMASK \tRead\n");
+            return s->rx_mask;
+
+        case 0x6004:
+            DPRINTF("TXMODE \tRead\n");
+            return s->tx_mode;
+        
+        case 0x6005:
+          //  DPRINTF("RXMODE \tRead\n");
+            return s->rx_mode;
+        
+        case 0x6006:
+            DPRINTF("RSTMODE \tRead\n");
+            return s->rst_mode;
+        
+        default:
+            fprintf(stderr,"NET Read B @ %x\n",addr);
+            return 0;
+    }
+}
+static uint32_t net_readw(void*opaque, target_phys_addr_t addr)
+{
+	fprintf(stderr,"S Read W @ %x\n",addr);
+	return 0;
+}
+static uint32_t net_readl(void*opaque, target_phys_addr_t addr)
+{
+    NextNetState *s = (NextNetState *)opaque;
+	CPUState *env = (CPUState *)env_g; 
+	switch(addr)
+    {
+        case 0x110:
+
+            //DPRINTF("TXCSR Read\n");
+            return s->tx_dma.csr;
+        case 0x4100: 
+            fprintf(stderr,"SAVEDBASE Read\n");
+            return s->tx_dma.savedbase;
+		case 0x4104: 
+            fprintf(stderr,"SAVELIMIT Read\n");
+			return s->tx_dma.savedlimit;
+		case 0x4114: 
+            fprintf(stderr,"TXLIMIT Read\n");
+			return s->tx_dma.limit;
+		case 0x4310:
+            fprintf(stderr,"TXBASE Read\n");
+			/* FUTURE :return nextdma_read(device, addr); */	
+			return s->tx_dma.basew;
+
+		case 0x150:
+           // fprintf(stderr,"RXCSR Read %x\n",s->rx_dma.csr);
+            return s->rx_dma.csr;
+        
+		case 0x4140:
+			return s->rx_dma.savedbase;
+        case 0x4144:
+            DPRINTF("SAVELIMIT %x @ %x\n",s->rx_dma.savedlimit,env->pc);
+            return s->rx_dma.savedlimit;
+		
+        default:
+        fprintf(stderr,"NET Read l @ %x\n",addr);
+        return 0;
+    }
+}
+#define NET_TXSTAT_CLEAR 0xFF
+#define NET_RXSTAT_CLEAR 0xFF
+static void net_writeb(void*opaque, target_phys_addr_t addr, uint32_t value)
+{
+//	CPUState *env = (CPUState *)env_g; 
+    NextNetState *s = (NextNetState *)opaque;
+    switch(addr)
+    {
+    	case 0x6000:
+            DPRINTF("TXSTAT \tWrite: %x\n",value);
+            if(value == NET_TXSTAT_CLEAR)
+               s->tx_stat = 0x80;
+            else
+                s->tx_stat = value;
+            break;
+        case 0x6001:
+            DPRINTF("TXMASK \tWrite: %x\n",value);
+            s->tx_mask = value;
+            break;
+        case 0x6002:
+         //   DPRINTF("RXSTAT \tWrite: %x @ %x\n",value,env->pc);
+            if(value == NET_RXSTAT_CLEAR)
+                s->rx_stat = 0;
+            else
+                s->rx_stat = value;
+            break;
+        case 0x6003:
+        //    DPRINTF("RXMASK \tWrite: %x\n",value);
+            s->rx_mask = value;
+            break;
+        case 0x6004:
+            DPRINTF("TXMODE \tWrite: %x\n",value);
+            s->tx_mode = value;
+            break;
+        case 0x6005:
+          //  DPRINTF("RXMODE \tWrite: %x\n",value);
+            s->rx_mode = value;
+            break;
+        case 0x6006:
+            DPRINTF("RSTMODE \tWrite: %x\n",value);
+            s->rst_mode = value;
+            break;
+        case 0x600d:
+        s->mac[(addr&0xF)-8] = value;         
+        DPRINTF("Set MAC ADDR %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+            s->mac[0],s->mac[1],s->mac[2],s->mac[3],s->mac[4],s->mac[5]);
+        qemu_macaddr_default_if_unset((MACAddr *)&s->mac);
+        break;
+        case 0x6008:case 0x6009:case 0x600a: case 0x600b: case 0x600c:
+        s->mac[(addr&0xF)-8] = value;         
+        break; 
+        case 0x6010:case 0x6011: case 0x6012: case 0x6013: case 0x6014:
+     //   break;
+        default:
+        fprintf(stderr,"NET Write B @ %x with %x\n",addr,value);
+    }
+}
+static void net_writew(void*opaque, target_phys_addr_t addr, uint32_t value)
+{
+	fprintf(stderr,"NET W w @ %x with %x\n",addr,value);
+}
+#define DMA_ENABLE		0x01000000
+#define DMA_SUPDATE		0x02000000
+#define DMA_COMPLETE	0x08000000
+
+#define DMA_M2DEV       0x0
+#define DMA_SETENABLE   0x00010000
+#define DMA_SETSUPDATE  0x00020000
+#define DMA_DEV2M		0x00040000
+#define DMA_CLRCOMPLETE 0x00080000
+#define DMA_RESET		0x00100000
+static void net_writel(void*opaque, target_phys_addr_t addr, uint32_t value)
+{
+	static int tx_count = 0;
+    NextNetState *s = (NextNetState *)opaque;
+	switch(addr)
+    {
+        case 0x110:
+        {
+				
+								
+				if(value & DMA_SETENABLE)
+				{
+                tx_count++;
+			//	if(tx_count % 4) return;
+				size_t len = (0xFFFFFFF & s->tx_dma.limit) - s->tx_dma.base;
+              DPRINTF("TXDMA ENABLE: %x len: %zu\n",s->tx_dma.base, len);
+				DPRINTF("TX Enable\n");
+                uint8_t buf[1600];//needs to be in dma struct?
+                cpu_physical_memory_read(s->tx_dma.base, buf, len); 
+                
+				qemu_send_packet(&s->nic->nc, buf,len);   
+               	s->tx_dma.csr |= DMA_COMPLETE | DMA_SUPDATE;
+			    s->tx_stat =  0x80;
+			//	if(tx_count > 1510) vm_stop(VMSTOP_DEBUG);
+				
+    			qemu_set_irq(s->irq[TX_I_DMA],3);
+
+				}
+				if(value & DMA_SETSUPDATE)
+					s->tx_dma.csr |= DMA_SUPDATE;	
+		
+				if(value & DMA_CLRCOMPLETE)
+					s->tx_dma.csr &= ~DMA_COMPLETE;
+
+				if(value & DMA_RESET)
+					s->tx_dma.csr &= ~(DMA_COMPLETE | DMA_SUPDATE | DMA_ENABLE);	        
+		}
+        break;
+        
+        case 0x4100: 
+        DPRINTF("Write l @ %x with %x\n",addr,value);
+			s->tx_dma.savedbase = value;
+		    break;
+		
+		case 0x4104: 
+        DPRINTF("Write l @ %x with %x\n",addr,value);
+			s->tx_dma.savedlimit = value;
+		    break;
+		case 0x4110:
+        DPRINTF("Write l @ %x with %x\n",addr,value);
+			s->tx_dma.base = value;
+			break;	
+        case 0x4114: 
+        DPRINTF("Write l @ %x with %x\n",addr,value);
+			s->tx_dma.limit = value;
+		    break;
+		
+        case 0x4310:
+        DPRINTF("Write l @ %x with %x\n",addr,value);
+			s->tx_dma.base = value;
+			/* FUTURE :nextdma_write(device, addr, value); */	
+            break;
+
+        case 0x150:
+            	if(value & DMA_DEV2M)
+                {
+                    DPRINTF("RX Dev to Memory\n");
+				}	
+				
+                if(value & DMA_SETENABLE)
+                    s->rx_dma.csr |= DMA_ENABLE;
+                
+				if(value & DMA_SETSUPDATE)
+					s->rx_dma.csr |= DMA_SUPDATE;	
+		
+				if(value & DMA_CLRCOMPLETE)
+					s->rx_dma.csr &= ~DMA_COMPLETE;
+
+				if(value & DMA_RESET)
+					s->rx_dma.csr &= ~(DMA_COMPLETE | DMA_SUPDATE | DMA_ENABLE);				
+				//
+	
+				DPRINTF("RXCSR \tWrite: %x\n",value);
+	        	break;
+        
+        case 0x4150:
+            
+       // DPRINTF("Write l @ %x with %x\n",addr,value);
+            s->rx_dma.base = value;
+		//	s->rx_dma.savedbase = value;
+            break;
+
+        case 0x4154:
+            s->rx_dma.limit = value;
+       // DPRINTF("Write l @ %x with %x\n",addr,value);
+            break;
+
+        case 0x4158:
+            s->rx_dma.chainbase = value;
+       // DPRINTF("Write l @ %x with %x\n",addr,value);
+            break;
+    
+        case 0x415c:
+            s->rx_dma.chainlimit = value;
+       // DPRINTF("Write l @ %x with %x\n",addr,value);
+            //DPRINTF("Pointer write %x w %x\n",addr,value);
+            break;
+        default:
+        DPRINTF("Write l @ %x with %x\n",addr,value);
+    }
+
+}
+
+static int nextnet_can_rx(VLANClientState *nc)
+{
+    NextNetState *s = DO_UPCAST(NICState, nc, nc)->opaque;
+    if(s->rx_mode & 0x3)
+		return 1;
+	else
+		return -1;
+}
+
+static ssize_t nextnet_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
+{
+	NextNetState *s = DO_UPCAST(NICState, nc, nc)->opaque;
+    
+	DPRINTF("received packet %zu\n",size);
+
+	/* Ethernet DMA is supposedly 32 byte aligned */	
+	if((size % 32) != 0)
+	{
+		size -= size % 32;
+		size += 32;
+	}
+	
+	/* write the packet into memory */
+	cpu_physical_memory_write(s->rx_dma.base,buf,size);
+	
+	/* saved limit is checked to calculate packet size
+		by both the rom and netbsd */ 
+	s->rx_dma.savedlimit = (s->rx_dma.base + size);
+	s->rx_dma.savedbase = (s->rx_dma.base);
+	
+	/*32 bytes under savedbase seems to be some kind of register
+	of which the purpose is unknown as of yet*/
+	//stl_phys(s->rx_dma.base-32,0xFFFFFFFF);
+	
+	if((s->rx_dma.csr & DMA_SUPDATE)){	
+		s->rx_dma.base = s->rx_dma.chainbase;
+		s->rx_dma.limit = s->rx_dma.chainlimit;
+	}
+	//we received a packet
+    s->rx_stat = 0x80;
+	
+	//Set dma registers and raise an irq
+	s->rx_dma.csr |= DMA_COMPLETE; //DON'T CHANGE THIS!!!!
+   	qemu_set_irq(s->irq[RX_I_DMA],6);
+    
+	return size;
+}
+
+static void nextnet_cleanup(VLANClientState *nc)
+{
+}
+
+/* level and vector values taken from Plan 9 source */
+void nextnet_irq(void *opaque, int n, int level)
+{
+    CPUM68KState *s = (CPUM68KState *)opaque;
+    switch(n)
+	{
+		case TX_I:
+			int_status = 1<<10;
+			m68k_set_irq_level(s,3,27);
+			break;
+		
+		case RX_I:
+			int_status = 1<<9;
+			m68k_set_irq_level(s,3,27);
+			break;
+		
+		case TX_I_DMA:
+			int_status = 1<<28;
+			m68k_set_irq_level(s,6,30);
+            break;
+		
+		case RX_I_DMA:
+			int_status = 1<<27;
+			m68k_set_irq_level(s,6,30);
+			break;
+	}
+
+	
+}		
diff --git a/hw/next-net.h b/hw/next-net.h
new file mode 100644
index 0000000..28b7358
--- /dev/null
+++ b/hw/next-net.h
@@ -0,0 +1,2 @@
+
+void nextnet_init(void *opaque);
-- 
1.7.2.3

[Qemu-devel] [PATCH 6/8] adds SFC, DFC, MMU TC, access control register, and user stack pointer acces to movec_to/from

[Bryce Lanham]

Signed-off-by: Bryce Lanham <blanham@gmail.com>
---
 target-m68k/helper.c |   44 ++++++++++++++++++++++++++++++++++++--------
 1 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 71294c0..5fa5b06 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -480,9 +480,25 @@ void HELPER(movec_to)(CPUM68KState * env, uint32_t reg, uint32_t val)
         env->cacr = val;
         m68k_switch_sp(env);
         break;
-    case 0x04: case 0x05: case 0x06: case 0x07: /* ACR[0-3] */
-        /* TODO: Implement Access Control Registers.  */
-        break;
+    case 0x03: /* MMU Translation Control */
+		env->mmu.tc = val;
+		break;
+    /*Translation/Access Control Registers*/
+	case 0x04:
+		env->itt0 = val;
+		return;
+	case 0x05:
+		env->itt1 = val;
+		break;
+	case 0x06:
+		env->dtt0 = val;
+		break;
+	case 0x07:
+		env->dtt1 = val;
+		break;
+    case 0x800: /* USP */
+		env->sp[M68K_USP] = val;
+		break;
     case 0x801: /* VBR */
         env->vbr = val;
         break;
@@ -496,14 +512,26 @@ void HELPER(movec_to)(CPUM68KState * env, uint32_t reg, uint32_t val)
 uint32_t HELPER(movec_from)(CPUM68KState * env, uint32_t reg)
 {
     switch (reg) {
+ 	case 0x00: /* SFC */
+        return env->sfc;
+    case 0x01: /* DFC */
+        return env->dfc;
     case 0x02: /* CACR */
-        return env->cacr;
-    case 0x04: case 0x05: case 0x06: case 0x07: /* ACR[0-3] */
-        /* TODO: Implement Access Control Registers.  */
-        return 0;
+        return env->cacr; 
+    case 0x03: /*MMU TC*/
+        return env->mmu.tc;
+    case 0x04:
+        return env->itt0;
+	case 0x05:
+		return env->itt1;
+	case 0x06:
+		return env->dtt0;
+    case 0x07:
+        return env->dtt1;
+    case 0x800:/*USP*/
+        return env->sp[M68K_USP];
     case 0x801: /* VBR */
         return env->vbr;
-        break;
     /* TODO: Implement control registers.  */
     default:
         cpu_abort(env, "Unimplemented control register read 0x%x\n",
-- 
1.7.2.3

[Qemu-devel] [PATCH 7/8] added move16, cinva, pflush instructions, and disabled abort on execution of frestore/fsave

[Bryce Lanham]

Signed-off-by: Bryce Lanham <blanham@gmail.com>
---
 target-m68k/translate.c |  108 ++++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 97 insertions(+), 11 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 0be011e..1975a06 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -29,6 +29,8 @@
 #include "tcg-op.h"
 #include "qemu-log.h"
 
+#include "sysemu.h"
+
 #include "helpers.h"
 #define GEN_HELPER 1
 #include "helpers.h"
@@ -179,7 +181,6 @@ static inline void gen_flush_cc_op(DisasContext *s)
         tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
 }
 
-
 /* Generate a jump to an immediate address.  */
 static void gen_jmp_im(DisasContext *s, uint32_t dest)
 {
@@ -191,7 +192,7 @@ static void gen_jmp_im(DisasContext *s, uint32_t dest)
 static void gen_exception(DisasContext *s, uint32_t where, int nr)
 {
     gen_flush_cc_op(s);
-    gen_jmp_im(s, where);
+    gen_jmp_im(s,where);
     gen_helper_raise_exception(tcg_const_i32(nr));
 }
 
@@ -1768,7 +1769,7 @@ DISAS_INSN(arith_im)
         tcg_gen_addi_i32(dest, dest, im);
         gen_update_cc_add(dest, tcg_const_i32(im));
         SET_X_FLAG(opsize, dest, tcg_const_i32(im));
-	SET_CC_OP(opsize, ADD);
+    SET_CC_OP(opsize, ADD);
         break;
     case 5: /* eori */
         tcg_gen_xori_i32(dest, src1, im);
@@ -3445,7 +3446,7 @@ DISAS_INSN(move_from_sr)
 {
     TCGv sr;
 
-    if (IS_USER(s)) {    /* FIXME: not privileged on 68000 */
+    if (IS_USER(s)) { /* FICME: not privledged on 68000 */
         gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
         return;
     }
@@ -3829,8 +3830,8 @@ DISAS_INSN(fpu)
     case 0x33: case 0x34: case 0x35:
     case 0x36: case 0x37:
         gen_helper_sincos_FP0_FP1(cpu_env);
-        gen_op_store_fpr_FP0(REG(ext, 7));	/* sin */
-        gen_op_store_fpr_FP1(REG(ext, 0));	/* cos */
+        gen_op_store_fpr_FP0(REG(ext, 7));  /* sin */
+        gen_op_store_fpr_FP1(REG(ext, 0));  /* cos */
         break;
     case 0x38: /* fcmp */
         gen_op_load_fpr_FP1(REG(ext, 7));
@@ -3996,17 +3997,27 @@ DISAS_INSN(fscc_reg)
     tcg_gen_andi_i32(reg, reg, 0xffffff00);
     gen_set_label(l1);
 }
-
+/* abort is disabled here, as pasing through these instructions merely breaks the fpu
+ *  preferable when we want to get the machine booting first
+ */
 DISAS_INSN(frestore)
 {
     /* TODO: Implement frestore.  */
-    qemu_assert(0, "FRESTORE not implemented");
+ //   qemu_assert(0, "FRESTORE not implemented");
+  // cpu_abort(cpu_single_env, "Illegal instruction: %04x @ %08x",
+    //          insn, s->pc - 2);
+
+
 }
 
 DISAS_INSN(fsave)
 {
     /* TODO: Implement fsave.  */
-    qemu_assert(0, "FSAVE not implemented");
+  //  qemu_assert(0, "FSAVE not implemented");
+  // cpu_abort(cpu_single_env, "Illegal instruction: %04x @ %08x",
+           //   insn, s->pc - 2);
+
+
 }
 
 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
@@ -4363,6 +4374,73 @@ register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
   }
 }
 
+/* my instructions start here */
+DISAS_INSN(cinva)
+{
+/* Cache invalidate (NOP)*/
+}
+/* page flush acts as a NOP at the moment, as I have not gotten far enough
+ * to test its functionality 
+ * */
+DISAS_INSN(pflush)
+{
+    int opmode = (insn>>3) & 0x3;
+    switch(opmode)
+    {
+        case 0x0:
+        case 0x1:
+        fprintf(stderr,"entry\n");
+        break;
+        case 0x2:
+        case 0x3:
+        fprintf(stderr,"all\n");
+        break;
+
+    }
+    
+
+}
+DISAS_INSN(move16)
+{
+    TCGv src;
+    TCGv s_addr;
+    TCGv d_addr;
+    uint16_t im;
+    if(insn & 0x8){
+        
+                vm_stop(VMSTOP_DEBUG);
+        //abort();
+    }else if(insn & 0x10){
+
+                vm_stop(VMSTOP_DEBUG);
+        //abort();
+
+    }else{
+      
+        d_addr = tcg_temp_new();
+        s_addr = tcg_temp_new();    
+        
+        s_addr = AREG(insn,0);
+        src = gen_load(s, OS_LONG, s_addr, 0); 
+        
+        im = read_im16(s);
+        d_addr = AREG(im,12);
+
+        gen_store(s, OS_LONG, d_addr, src);
+        
+        int i = 0;
+        for(;i <3; i++)
+        {
+            tcg_gen_addi_i32(d_addr,d_addr,4);
+            tcg_gen_addi_i32(s_addr,s_addr,4);
+
+            src = gen_load(s, OS_LONG, s_addr, 0); 
+            gen_store(s, OS_LONG, d_addr, src);
+        }
+    }
+}
+
+
 /* Register m68k opcode handlers.  Order is important.
    Later insn override earlier ones.  */
 void register_m68k_insns (CPUM68KState *env)
@@ -4565,6 +4643,7 @@ void register_m68k_insns (CPUM68KState *env)
     INSN(addx_mem,  d108, f138, M68000);
     INSN(adda,      d1c0, f1c0, CF_ISA_A);
     INSN(adda,      d0c0, f0c0, M68000);
+    /* Bit ops */
     INSN(shift_im,  e080, f0f0, CF_ISA_A);
     INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
     INSN(shift8_im, e000, f0f0, M68000);
@@ -4583,6 +4662,7 @@ void register_m68k_insns (CPUM68KState *env)
     INSN(rotate_mem, e4c0, fcc0, M68000);
     INSN(bitfield_mem,e8c0, f8c0, BITFIELD);
     INSN(bitfield_reg,e8c0, f8f8, BITFIELD);
+    /* FPU */
     INSN(undef_fpu, f000, f000, CF_ISA_A);
     INSN(undef_fpu, f000, f000, M68000);
     INSN(fpu,       f200, ffc0, CF_FPU);
@@ -4593,10 +4673,16 @@ void register_m68k_insns (CPUM68KState *env)
     INSN(fscc_mem,  f240, ffc0, FPU);
     INSN(fscc_reg,  f240, fff8, FPU);
     INSN(fbcc,      f280, ffc0, FPU);
-    INSN(frestore,  f340, ffc0, FPU);
+    INSN(frestore,  f300, ffc0, FPU);
     INSN(fsave,     f340, ffc0, FPU);
     INSN(intouch,   f340, ffc0, CF_ISA_A);
+    /* MMU */
     INSN(cpushl,    f428, ff38, CF_ISA_A);
+    INSN(cpushl,    f478, ff78, M68000);
+    INSN(cinva,     f4d8, f4d8, M68000);
+    INSN(pflush,    f500, f500, M68000);
+    
+    INSN(move16,    f600, f600, M68000);
     INSN(wddata,    fb00, ff00, CF_ISA_A);
     INSN(wdebug,    fbc0, ffc0, CF_ISA_A);
 #ifdef CONFIG_EMULOP
@@ -4684,7 +4770,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
             gen_io_start();
         dc->insn_pc = dc->pc;
-	disas_m68k_insn(env, dc);
+    disas_m68k_insn(env, dc);
         num_insns++;
     } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
              !env->singlestep_enabled &&
-- 
1.7.2.3

[Qemu-devel] [PATCH 8/8] added mmu tc, sfc, dfc, and access control registers to the cpu header

[Bryce Lanham]

Signed-off-by: Bryce Lanham <blanham@gmail.com>
---
 target-m68k/cpu.h |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 2587512..006ecdc 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -99,13 +99,17 @@ typedef struct CPUM68KState {
     /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
     int current_sp;
     uint32_t sp[2];
-
     /* Condition flags.  */
     uint32_t cc_op;
     uint32_t cc_dest;
     uint32_t cc_src;
     uint32_t cc_x;
-
+	/* Control Registers */
+	uint32_t sfc;
+	uint32_t dfc;
+	uint32_t itt0,itt1;
+	uint32_t dtt0,dtt1;
+	/* FPU Registers */
     FPReg fregs[8];
     uint32_t fpcr;
     uint32_t fpsr;
@@ -136,7 +140,8 @@ typedef struct CPUM68KState {
     /* MMU status.  */
     struct {
         uint32_t ar;
-    } mmu;
+    	uint32_t tc;
+	} mmu;
 
     /* Control registers.  */
     uint32_t vbr;
@@ -314,4 +319,5 @@ static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
     env->pc = tb->pc;
 }
 
+
 #endif
-- 
1.7.2.3

Re: [Qemu-devel] [PATCH 0/8] *** SUBJECT HERE ***

[Laurent Vivier]

[-- Attachment #1: Type: text/plain, Size: 2195 bytes --]

Bryce,
 
please, run scripts/checkpatch.pl before submitting them to check the style.

Then, IMHO, you can put all next-cube stuff in one patch (hw/next-* +
Makefile.target),
then make one patch by m68k feature/instruction added or m68k default corrected.
 
And remember, to be able to bisect, each patch must be able to be compiled and
run.
 
Good Luck,
Laurent

 


Le 18 août 2011 à 00:09, Bryce Lanham <blanham@gmail.com> a écrit :

> *** BLURB HERE ***
>
> Bryce Lanham (8):
>   added next source files to Makefile.target
>   main next driver, needs a bit of cleanup
>   next framebuffer driver, very basic, only supports running under 32
>     bit color at the moment
>   next keyboard driver, only supports a subset of modifier keys
>   partially working network driver, needs more comparison with real
>     hardware before it can be made fully working
>   adds SFC, DFC, MMU TC, access control register, and user stack
>     pointer acces to movec_to/from
>   added move16, cinva, pflush instructions, and disabled abort on
>     execution of frestore/fsave
>   added mmu tc, sfc, dfc, and access control registers to the cpu
>     header
>
>  Makefile.target         |    2 +
>  hw/next-cube.c          |  471 +++++++++++++++++++++++++++++++++++++++++++
>  hw/next-fb.c            |  102 ++++++++++
>  hw/next-fb.h            |   14 ++
>  hw/next-kbd.c           |  243 ++++++++++++++++++++++
>  hw/next-kbd.h           |    2 +
>  hw/next-net.c           |  513
>+++++++++++++++++++++++++++++++++++++++++++++++
>  hw/next-net.h           |    2 +
>  target-m68k/cpu.h       |   12 +-
>  target-m68k/helper.c    |   44 ++++-
>  target-m68k/translate.c |  108 +++++++++-
>  11 files changed, 1491 insertions(+), 22 deletions(-)
>  create mode 100644 hw/next-cube.c
>  create mode 100644 hw/next-fb.c
>  create mode 100644 hw/next-fb.h
>  create mode 100644 hw/next-kbd.c
>  create mode 100644 hw/next-kbd.h
>  create mode 100644 hw/next-net.c
>  create mode 100644 hw/next-net.h
>
> --
> 1.7.2.3
>
>

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Re: [Qemu-devel] [PATCH 1/8] added next source files to Makefile.target

[Andreas Färber]

Am 18.08.2011 um 00:09 schrieb Bryce Lanham:

>
> Signed-off-by: Bryce Lanham <blanham@gmail.com>
> ---
> Makefile.target |    2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/Makefile.target b/Makefile.target
> index 43624dc..ad0bd6b 100644
> --- a/Makefile.target
> +++ b/Makefile.target

> @@ -316,6 +316,7 @@ obj-microblaze-$(CONFIG_FDT) += device_tree.o
> # Boards
> obj-cris-y = cris_pic_cpu.o
> obj-cris-y += cris-boot.o
> +obj-cris-y += etraxfs.o axis_dev88.o
> obj-cris-y += axis_dev88.o
>
> # IO blocks

Accidental, unrelated change?

> @@ -374,6 +375,7 @@ obj-sh4-y += ide/mmio.o
> obj-m68k-y = an5206.o mcf5206.o mcf_uart.o mcf_intc.o mcf5208.o  
> mcf_fec.o
> obj-m68k-y += m68k-semi.o dummy_m68k.o
> obj-m68k-y += m68k_mac.o
> +obj-m68k-y += next-cube.o next-kbd.o next-fb.o next-net.o  
> framebuffer.o

Nack. Those files are added later in the series, so this will break  
the build. Add each file in the respective patch where you introduce  
it, so that a) the project keeps compiling and b) the source files in  
the patch get compiled for error checking.

Andreas

>
> obj-s390x-y = s390-virtio-bus.o s390-virtio.o
>
> -- 
> 1.7.2.3