* [Qemu-devel] [PATCH v2 01/22] stellaris_enet: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 02/22] sysbus: add helpers to add and delete memory regions to the system bus Avi Kivity
` (21 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/stellaris_enet.c | 29 ++++++++++++-----------------
1 files changed, 12 insertions(+), 17 deletions(-)
diff --git a/hw/stellaris_enet.c b/hw/stellaris_enet.c
index f9bd3da..d5613ff 100644
--- a/hw/stellaris_enet.c
+++ b/hw/stellaris_enet.c
@@ -69,7 +69,7 @@ typedef struct {
NICState *nic;
NICConf conf;
qemu_irq irq;
- int mmio_index;
+ MemoryRegion mmio;
} stellaris_enet_state;
static void stellaris_enet_update(stellaris_enet_state *s)
@@ -130,7 +130,8 @@ static int stellaris_enet_can_receive(VLANClientState *nc)
return (s->np < 31);
}
-static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
+static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
uint32_t val;
@@ -198,7 +199,7 @@ static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
}
static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
@@ -303,17 +304,12 @@ static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const stellaris_enet_readfn[] = {
- stellaris_enet_read,
- stellaris_enet_read,
- stellaris_enet_read
+static const MemoryRegionOps stellaris_enet_ops = {
+ .read = stellaris_enet_read,
+ .write = stellaris_enet_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const stellaris_enet_writefn[] = {
- stellaris_enet_write,
- stellaris_enet_write,
- stellaris_enet_write
-};
static void stellaris_enet_reset(stellaris_enet_state *s)
{
s->mdv = 0x80;
@@ -391,7 +387,7 @@ static void stellaris_enet_cleanup(VLANClientState *nc)
unregister_savevm(&s->busdev.qdev, "stellaris_enet", s);
- cpu_unregister_io_memory(s->mmio_index);
+ memory_region_destroy(&s->mmio);
g_free(s);
}
@@ -408,10 +404,9 @@ static int stellaris_enet_init(SysBusDevice *dev)
{
stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
- s->mmio_index = cpu_register_io_memory(stellaris_enet_readfn,
- stellaris_enet_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, s->mmio_index);
+ memory_region_init_io(&s->mmio, &stellaris_enet_ops, s, "stellaris_enet",
+ 0x1000);
+ sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 02/22] sysbus: add helpers to add and delete memory regions to the system bus
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 01/22] stellaris_enet: convert to memory API Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 03/22] pci_host: convert conf index and data ports to memory API Avi Kivity
` (20 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/sysbus.c | 22 ++++++++++++++++++++++
hw/sysbus.h | 6 ++++++
2 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/hw/sysbus.c b/hw/sysbus.c
index f39768b..f5f0ed2 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -256,3 +256,25 @@ static char *sysbus_get_fw_dev_path(DeviceState *dev)
return strdup(path);
}
+
+void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
+ MemoryRegion *mem)
+{
+ memory_region_add_subregion(get_system_memory(), addr, mem);
+}
+
+void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem)
+{
+ memory_region_del_subregion(get_system_memory(), mem);
+}
+
+void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
+ MemoryRegion *mem)
+{
+ memory_region_add_subregion(get_system_io(), addr, mem);
+}
+
+void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem)
+{
+ memory_region_del_subregion(get_system_io(), mem);
+}
diff --git a/hw/sysbus.h b/hw/sysbus.h
index b87c6c5..e4d56cf 100644
--- a/hw/sysbus.h
+++ b/hw/sysbus.h
@@ -57,6 +57,12 @@ void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t ioport, pio_addr_t size);
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr);
+void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
+ MemoryRegion *mem);
+void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem);
+void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
+ MemoryRegion *mem);
+void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem);
/* Legacy helper function for creating devices. */
DeviceState *sysbus_create_varargs(const char *name,
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 03/22] pci_host: convert conf index and data ports to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 01/22] stellaris_enet: convert to memory API Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 02/22] sysbus: add helpers to add and delete memory regions to the system bus Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 04/22] ReadWriteHandler: remove Avi Kivity
` (19 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/dec_pci.c | 13 ++++----
hw/grackle_pci.c | 13 ++++----
hw/pci_host.c | 86 ++++++++++++++++++++++++------------------------------
hw/pci_host.h | 16 ++++------
hw/piix_pci.c | 11 +++++-
hw/ppc4xx_pci.c | 10 ++++--
hw/ppce500_pci.c | 21 ++++++-------
hw/prep_pci.c | 12 +++++--
hw/unin_pci.c | 82 +++++++++++++++++++++++++-------------------------
9 files changed, 131 insertions(+), 133 deletions(-)
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index a35f382..1aec066 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -80,16 +80,15 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
static int pci_dec_21154_init_device(SysBusDevice *dev)
{
DECState *s;
- int pci_mem_config, pci_mem_data;
s = FROM_SYSBUS(DECState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
- DEVICE_LITTLE_ENDIAN);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, pci_mem_config);
- sysbus_init_mmio(dev, 0x1000, pci_mem_data);
+ memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
+ &s->host_state, "pci-conf-idx", 0x1000);
+ memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
+ &s->host_state, "pci-data-idx", 0x1000);
+ sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
+ sysbus_init_mmio_region(dev, &s->host_state.data_mem);
return 0;
}
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 9a823e1..9d3ff7d 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -92,16 +92,15 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
static int pci_grackle_init_device(SysBusDevice *dev)
{
GrackleState *s;
- int pci_mem_config, pci_mem_data;
s = FROM_SYSBUS(GrackleState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
- DEVICE_LITTLE_ENDIAN);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, pci_mem_config);
- sysbus_init_mmio(dev, 0x1000, pci_mem_data);
+ memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
+ &s->host_state, "pci-conf-idx", 0x1000);
+ memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
+ &s->host_state, "pci-data-idx", 0x1000);
+ sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
+ sysbus_init_mmio_region(dev, &s->host_state.data_mem);
qemu_register_reset(pci_grackle_reset, &s->host_state);
return 0;
diff --git a/hw/pci_host.c b/hw/pci_host.c
index 2e8a29f..44c6c20 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -94,82 +94,72 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return val;
}
-static void pci_host_config_write(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned len)
{
- PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
+ PCIHostState *s = opaque;
- PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
+ PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
__func__, addr, len, val);
s->config_reg = val;
}
-static uint32_t pci_host_config_read(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned len)
{
- PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
+ PCIHostState *s = opaque;
uint32_t val = s->config_reg;
- PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
+ PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
__func__, addr, len, val);
return val;
}
-static void pci_host_data_write(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_data_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned len)
{
- PCIHostState *s = container_of(handler, PCIHostState, data_handler);
- PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
- addr, len, val);
+ PCIHostState *s = opaque;
+ PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n",
+ addr, len, (unsigned)val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}
-static uint32_t pci_host_data_read(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint64_t pci_host_data_read(void *opaque,
+ target_phys_addr_t addr, unsigned len)
{
- PCIHostState *s = container_of(handler, PCIHostState, data_handler);
+ PCIHostState *s = opaque;
uint32_t val;
if (!(s->config_reg & (1 << 31)))
return 0xffffffff;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
- PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
+ PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
addr, len, val);
return val;
}
-static void pci_host_init(PCIHostState *s)
-{
- s->conf_handler.write = pci_host_config_write;
- s->conf_handler.read = pci_host_config_read;
- s->data_handler.write = pci_host_data_write;
- s->data_handler.read = pci_host_data_read;
-}
+const MemoryRegionOps pci_host_conf_le_ops = {
+ .read = pci_host_config_read,
+ .write = pci_host_config_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
-int pci_host_conf_register_mmio(PCIHostState *s, int endian)
-{
- pci_host_init(s);
- return cpu_register_io_memory_simple(&s->conf_handler, endian);
-}
+const MemoryRegionOps pci_host_conf_be_ops = {
+ .read = pci_host_config_read,
+ .write = pci_host_config_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
-void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s)
-{
- pci_host_init(s);
- register_ioport_simple(&s->conf_handler, ioport, 4, 4);
- sysbus_init_ioports(&s->busdev, ioport, 4);
-}
+const MemoryRegionOps pci_host_data_le_ops = {
+ .read = pci_host_data_read,
+ .write = pci_host_data_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+const MemoryRegionOps pci_host_data_be_ops = {
+ .read = pci_host_data_read,
+ .write = pci_host_data_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
-int pci_host_data_register_mmio(PCIHostState *s, int endian)
-{
- pci_host_init(s);
- return cpu_register_io_memory_simple(&s->data_handler, endian);
-}
-void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
-{
- pci_host_init(s);
- register_ioport_simple(&s->data_handler, ioport, 4, 1);
- register_ioport_simple(&s->data_handler, ioport, 4, 2);
- register_ioport_simple(&s->data_handler, ioport, 4, 4);
- sysbus_init_ioports(&s->busdev, ioport, 4);
-}
diff --git a/hw/pci_host.h b/hw/pci_host.h
index 7f55114..0211086 100644
--- a/hw/pci_host.h
+++ b/hw/pci_host.h
@@ -29,12 +29,11 @@
#define PCI_HOST_H
#include "sysbus.h"
-#include "rwhandler.h"
struct PCIHostState {
SysBusDevice busdev;
- ReadWriteHandler conf_handler;
- ReadWriteHandler data_handler;
+ MemoryRegion conf_mem;
+ MemoryRegion data_mem;
MemoryRegion *address_space;
uint32_t config_reg;
PCIBus *bus;
@@ -49,12 +48,9 @@ uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len);
uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
-/* for mmio */
-int pci_host_conf_register_mmio(PCIHostState *s, int endian);
-int pci_host_data_register_mmio(PCIHostState *s, int endian);
-
-/* for ioio */
-void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s);
-void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s);
+extern const MemoryRegionOps pci_host_conf_le_ops;
+extern const MemoryRegionOps pci_host_conf_be_ops;
+extern const MemoryRegionOps pci_host_data_le_ops;
+extern const MemoryRegionOps pci_host_data_be_ops;
#endif /* PCI_HOST_H */
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index c563c6e..f892994 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -235,9 +235,16 @@ static int i440fx_pcihost_initfn(SysBusDevice *dev)
{
I440FXState *s = FROM_SYSBUS(I440FXState, dev);
- pci_host_conf_register_ioport(0xcf8, s);
+ memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
+ "pci-conf-idx", 4);
+ sysbus_add_io(dev, 0xcf8, &s->conf_mem);
+ sysbus_init_ioports(&s->busdev, 0xcf8, 4);
+
+ memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
+ "pci-conf-data", 4);
+ sysbus_add_io(dev, 0xcfc, &s->data_mem);
+ sysbus_init_ioports(&s->busdev, 0xcfc, 4);
- pci_host_data_register_ioport(0xcfc, s);
return 0;
}
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index 52e2663..339b38e 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -368,10 +368,12 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
/* CFGDATA */
- index = pci_host_data_register_mmio(&controller->pci_state, 1);
- if (index < 0)
- goto free;
- cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
+ memory_region_init_io(&controller->pci_state.data_mem,
+ &pci_host_data_be_ops,
+ &controller->pci_state, "pci-conf-data", 4);
+ memory_region_add_subregion(get_system_memory(),
+ config_space + PCIC0_CFGDATA,
+ &controller->pci_state.data_mem);
/* Internal registers */
index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 4390aeb..2db365d 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -79,8 +79,6 @@ struct PPCE500PCIState {
uint32_t gasket_time;
qemu_irq irq[4];
/* mmio maps */
- int cfgaddr;
- int cfgdata;
int reg;
};
@@ -268,18 +266,18 @@ static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h);
- cpu_register_physical_memory(base + PCIE500_CFGADDR, 4, s->cfgaddr);
- cpu_register_physical_memory(base + PCIE500_CFGDATA, 4, s->cfgdata);
+ sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem);
+ sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem);
cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
s->reg);
}
static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
{
- cpu_register_physical_memory(base + PCIE500_CFGADDR, 4,
- IO_MEM_UNASSIGNED);
- cpu_register_physical_memory(base + PCIE500_CFGDATA, 4,
- IO_MEM_UNASSIGNED);
+ PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
+
+ sysbus_del_memory(dev, &h->conf_mem);
+ sysbus_del_memory(dev, &h->data_mem);
cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
IO_MEM_UNASSIGNED);
}
@@ -309,9 +307,10 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
pci_create_simple(b, 0, "e500-host-bridge");
- s->cfgaddr = pci_host_conf_register_mmio(&s->pci_state, DEVICE_BIG_ENDIAN);
- s->cfgdata = pci_host_data_register_mmio(&s->pci_state,
- DEVICE_LITTLE_ENDIAN);
+ memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
+ "pci-conf-idx", 4);
+ memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
+ "pci-conf-data", 4);
s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
DEVICE_BIG_ENDIAN);
sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index c36232a..55e4e25 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -125,9 +125,15 @@ PCIBus *pci_prep_init(qemu_irq *pic,
address_space_io,
0, 4);
- pci_host_conf_register_ioport(0xcf8, s);
-
- pci_host_data_register_ioport(0xcfc, s);
+ memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s,
+ "pci-conf-idx", 1);
+ memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem);
+ sysbus_init_ioports(&s->busdev, 0xcf8, 1);
+
+ memory_region_init_io(&s->conf_mem, &pci_host_data_be_ops, s,
+ "pci-conf-data", 1);
+ memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem);
+ sysbus_init_ioports(&s->busdev, 0xcfc, 1);
PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
PPC_PCIIO_write, s,
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index f896f8c..600cd1e 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -41,7 +41,6 @@ static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
typedef struct UNINState {
SysBusDevice busdev;
PCIHostState host_state;
- ReadWriteHandler data_handler;
} UNINState;
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
@@ -100,67 +99,70 @@ static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
return retval;
}
-static void unin_data_write(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void unin_data_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned len)
{
- UNINState *s = container_of(handler, UNINState, data_handler);
- UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
+ UNINState *s = opaque;
+ UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
+ addr, len, val);
pci_data_write(s->host_state.bus,
unin_get_config_reg(s->host_state.config_reg, addr),
val, len);
}
-static uint32_t unin_data_read(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
+ unsigned len)
{
- UNINState *s = container_of(handler, UNINState, data_handler);
+ UNINState *s = opaque;
uint32_t val;
val = pci_data_read(s->host_state.bus,
unin_get_config_reg(s->host_state.config_reg, addr),
len);
- UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
+ UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
+ addr, len, val);
return val;
}
+static const MemoryRegionOps unin_data_ops = {
+ .read = unin_data_read,
+ .write = unin_data_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
static int pci_unin_main_init_device(SysBusDevice *dev)
{
UNINState *s;
- int pci_mem_config, pci_mem_data;
/* Use values found on a real PowerMac */
/* Uninorth main bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
- DEVICE_LITTLE_ENDIAN);
- s->data_handler.read = unin_data_read;
- s->data_handler.write = unin_data_write;
- pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, pci_mem_config);
- sysbus_init_mmio(dev, 0x1000, pci_mem_data);
+ memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
+ &s->host_state, "pci-conf-idx", 0x1000);
+ memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
+ "pci-conf-data", 0x1000);
+ sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
+ sysbus_init_mmio_region(dev, &s->host_state.data_mem);
qemu_register_reset(pci_unin_reset, &s->host_state);
return 0;
}
+
static int pci_u3_agp_init_device(SysBusDevice *dev)
{
UNINState *s;
- int pci_mem_config, pci_mem_data;
/* Uninorth U3 AGP bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
- DEVICE_LITTLE_ENDIAN);
- s->data_handler.read = unin_data_read;
- s->data_handler.write = unin_data_write;
- pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, pci_mem_config);
- sysbus_init_mmio(dev, 0x1000, pci_mem_data);
+ memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
+ &s->host_state, "pci-conf-idx", 0x1000);
+ memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
+ "pci-conf-data", 0x1000);
+ sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
+ sysbus_init_mmio_region(dev, &s->host_state.data_mem);
qemu_register_reset(pci_unin_reset, &s->host_state);
@@ -170,34 +172,32 @@ static int pci_u3_agp_init_device(SysBusDevice *dev)
static int pci_unin_agp_init_device(SysBusDevice *dev)
{
UNINState *s;
- int pci_mem_config, pci_mem_data;
/* Uninorth AGP bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
- DEVICE_LITTLE_ENDIAN);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, pci_mem_config);
- sysbus_init_mmio(dev, 0x1000, pci_mem_data);
+ memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
+ &s->host_state, "pci-conf-idx", 0x1000);
+ memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
+ &s->host_state, "pci-conf-data", 0x1000);
+ sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
+ sysbus_init_mmio_region(dev, &s->host_state.data_mem);
return 0;
}
static int pci_unin_internal_init_device(SysBusDevice *dev)
{
UNINState *s;
- int pci_mem_config, pci_mem_data;
/* Uninorth internal bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
- DEVICE_LITTLE_ENDIAN);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, pci_mem_config);
- sysbus_init_mmio(dev, 0x1000, pci_mem_data);
+ memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
+ &s->host_state, "pci-conf-idx", 0x1000);
+ memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
+ &s->host_state, "pci-conf-data", 0x1000);
+ sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
+ sysbus_init_mmio_region(dev, &s->host_state.data_mem);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 04/22] ReadWriteHandler: remove
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (2 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 03/22] pci_host: convert conf index and data ports to memory API Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 05/22] an5206: convert to memory API Avi Kivity
` (18 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
No longer used.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
Makefile.target | 1 -
rwhandler.c | 87 -------------------------------------------------------
rwhandler.h | 27 -----------------
3 files changed, 0 insertions(+), 115 deletions(-)
delete mode 100644 rwhandler.c
delete mode 100644 rwhandler.h
diff --git a/Makefile.target b/Makefile.target
index e280bf6..c9957ae 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -195,7 +195,6 @@ obj-$(CONFIG_VIRTIO) += virtio.o virtio-blk.o virtio-balloon.o virtio-net.o virt
obj-y += vhost_net.o
obj-$(CONFIG_VHOST_NET) += vhost.o
obj-$(CONFIG_REALLY_VIRTFS) += 9pfs/virtio-9p-device.o
-obj-y += rwhandler.o
obj-$(CONFIG_KVM) += kvm.o kvm-all.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-y += memory.o
diff --git a/rwhandler.c b/rwhandler.c
deleted file mode 100644
index bb2238f..0000000
--- a/rwhandler.c
+++ /dev/null
@@ -1,87 +0,0 @@
-#include "rwhandler.h"
-#include "ioport.h"
-#include "cpu-all.h"
-
-#define RWHANDLER_WRITE(name, len, type) \
-static void name(void *opaque, type addr, uint32_t value) \
-{\
- struct ReadWriteHandler *handler = opaque;\
- handler->write(handler, addr, value, len);\
-}
-
-#define RWHANDLER_READ(name, len, type) \
-static uint32_t name(void *opaque, type addr) \
-{ \
- struct ReadWriteHandler *handler = opaque; \
- return handler->read(handler, addr, len); \
-}
-
-RWHANDLER_WRITE(cpu_io_memory_simple_writeb, 1, target_phys_addr_t);
-RWHANDLER_READ(cpu_io_memory_simple_readb, 1, target_phys_addr_t);
-RWHANDLER_WRITE(cpu_io_memory_simple_writew, 2, target_phys_addr_t);
-RWHANDLER_READ(cpu_io_memory_simple_readw, 2, target_phys_addr_t);
-RWHANDLER_WRITE(cpu_io_memory_simple_writel, 4, target_phys_addr_t);
-RWHANDLER_READ(cpu_io_memory_simple_readl, 4, target_phys_addr_t);
-
-static CPUWriteMemoryFunc * const cpu_io_memory_simple_write[] = {
- &cpu_io_memory_simple_writeb,
- &cpu_io_memory_simple_writew,
- &cpu_io_memory_simple_writel,
-};
-
-static CPUReadMemoryFunc * const cpu_io_memory_simple_read[] = {
- &cpu_io_memory_simple_readb,
- &cpu_io_memory_simple_readw,
- &cpu_io_memory_simple_readl,
-};
-
-int cpu_register_io_memory_simple(struct ReadWriteHandler *handler, int endian)
-{
- if (!handler->read || !handler->write) {
- return -1;
- }
- return cpu_register_io_memory(cpu_io_memory_simple_read,
- cpu_io_memory_simple_write,
- handler, endian);
-}
-
-RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t);
-RWHANDLER_READ(ioport_simple_readb, 1, uint32_t);
-RWHANDLER_WRITE(ioport_simple_writew, 2, uint32_t);
-RWHANDLER_READ(ioport_simple_readw, 2, uint32_t);
-RWHANDLER_WRITE(ioport_simple_writel, 4, uint32_t);
-RWHANDLER_READ(ioport_simple_readl, 4, uint32_t);
-
-int register_ioport_simple(ReadWriteHandler* handler,
- pio_addr_t start, int length, int size)
-{
- IOPortWriteFunc *write;
- IOPortReadFunc *read;
- int r;
- switch (size) {
- case 1:
- write = ioport_simple_writeb;
- read = ioport_simple_readb;
- break;
- case 2:
- write = ioport_simple_writew;
- read = ioport_simple_readw;
- break;
- default:
- write = ioport_simple_writel;
- read = ioport_simple_readl;
- }
- if (handler->write) {
- r = register_ioport_write(start, length, size, write, handler);
- if (r < 0) {
- return r;
- }
- }
- if (handler->read) {
- r = register_ioport_read(start, length, size, read, handler);
- if (r < 0) {
- return r;
- }
- }
- return 0;
-}
diff --git a/rwhandler.h b/rwhandler.h
deleted file mode 100644
index b2a5790..0000000
--- a/rwhandler.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef READ_WRITE_HANDLER_H
-#define READ_WRITE_HANDLER_H
-
-#include "qemu-common.h"
-#include "ioport.h"
-
-typedef struct ReadWriteHandler ReadWriteHandler;
-
-/* len is guaranteed to be one of 1, 2 or 4, addr is guaranteed to fit in an
- * appropriate type (io/memory/etc). They do not need to be range checked. */
-typedef void WriteHandlerFunc(ReadWriteHandler *, pcibus_t addr,
- uint32_t value, int len);
-typedef uint32_t ReadHandlerFunc(ReadWriteHandler *, pcibus_t addr, int len);
-
-struct ReadWriteHandler {
- WriteHandlerFunc *write;
- ReadHandlerFunc *read;
-};
-
-/* Helpers for when we want to use a single routine with length. */
-/* CPU memory handler: both read and write must be present. */
-int cpu_register_io_memory_simple(ReadWriteHandler *, int endian);
-/* io port handler: can supply only read or write handlers. */
-int register_ioport_simple(ReadWriteHandler *,
- pio_addr_t start, int length, int size);
-
-#endif
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 05/22] an5206: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (3 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 04/22] ReadWriteHandler: remove Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 06/22] armv7m: " Avi Kivity
` (17 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/an5206.c | 12 ++++++++----
1 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/an5206.c b/hw/an5206.c
index 04ca420..481ae60 100644
--- a/hw/an5206.c
+++ b/hw/an5206.c
@@ -12,6 +12,7 @@
#include "boards.h"
#include "loader.h"
#include "elf.h"
+#include "exec-memory.h"
#define KERNEL_LOAD_ADDR 0x10000
#define AN5206_MBAR_ADDR 0x10000000
@@ -37,6 +38,9 @@ static void an5206_init(ram_addr_t ram_size,
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model)
cpu_model = "m5206";
@@ -52,12 +56,12 @@ static void an5206_init(ram_addr_t ram_size,
env->rambar0 = AN5206_RAMBAR_ADDR | 1;
/* DRAM at address zero */
- cpu_register_physical_memory(0, ram_size,
- qemu_ram_alloc(NULL, "an5206.ram", ram_size) | IO_MEM_RAM);
+ memory_region_init_ram(ram, NULL, "an5206.ram", ram_size);
+ memory_region_add_subregion(address_space_mem, 0, ram);
/* Internal SRAM. */
- cpu_register_physical_memory(AN5206_RAMBAR_ADDR, 512,
- qemu_ram_alloc(NULL, "an5206.sram", 512) | IO_MEM_RAM);
+ memory_region_init_ram(sram, NULL, "an5206.sram", 512);
+ memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram);
mcf5206_init(AN5206_MBAR_ADDR, env);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 06/22] armv7m: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (4 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 05/22] an5206: convert to memory API Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 07/22] axis_dev88: convert to memory API (RAM only) Avi Kivity
` (16 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/arm-misc.h | 5 ++++-
hw/armv7m.c | 22 ++++++++++++----------
hw/stellaris.c | 5 ++++-
3 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index f8a7472..af403a1 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -11,13 +11,16 @@
#ifndef ARM_MISC_H
#define ARM_MISC_H 1
+#include "memory.h"
+
/* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
qemu_irq *arm_pic_init_cpu(CPUState *env);
/* armv7m.c */
-qemu_irq *armv7m_init(int flash_size, int sram_size,
+qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
+ int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model);
/* arm_boot.c */
diff --git a/hw/armv7m.c b/hw/armv7m.c
index a932f16..28d41b8 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -156,7 +156,8 @@ static void armv7m_reset(void *opaque)
flash_size and sram_size are in kb.
Returns the NVIC array. */
-qemu_irq *armv7m_init(int flash_size, int sram_size,
+qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
+ int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model)
{
CPUState *env;
@@ -169,6 +170,9 @@ qemu_irq *armv7m_init(int flash_size, int sram_size,
uint64_t lowaddr;
int i;
int big_endian;
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
+ MemoryRegion *flash = g_new(MemoryRegion, 1);
+ MemoryRegion *hack = g_new(MemoryRegion, 1);
flash_size *= 1024;
sram_size *= 1024;
@@ -194,12 +198,11 @@ qemu_irq *armv7m_init(int flash_size, int sram_size,
#endif
/* Flash programming is done via the SCU, so pretend it is ROM. */
- cpu_register_physical_memory(0, flash_size,
- qemu_ram_alloc(NULL, "armv7m.flash",
- flash_size) | IO_MEM_ROM);
- cpu_register_physical_memory(0x20000000, sram_size,
- qemu_ram_alloc(NULL, "armv7m.sram",
- sram_size) | IO_MEM_RAM);
+ memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size);
+ memory_region_set_readonly(flash, true);
+ memory_region_add_subregion(address_space_mem, 0, flash);
+ memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size);
+ memory_region_add_subregion(address_space_mem, 0x20000000, sram);
armv7m_bitband_init();
nvic = qdev_create(NULL, "armv7m_nvic");
@@ -232,9 +235,8 @@ qemu_irq *armv7m_init(int flash_size, int sram_size,
/* Hack to map an additional page of ram at the top of the address
space. This stops qemu complaining about executing code outside RAM
when returning from an exception. */
- cpu_register_physical_memory(0xfffff000, 0x1000,
- qemu_ram_alloc(NULL, "armv7m.hack",
- 0x1000) | IO_MEM_RAM);
+ memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000);
+ memory_region_add_subregion(address_space_mem, 0xfffff000, hack);
qemu_register_reset(armv7m_reset, env);
return pic;
diff --git a/hw/stellaris.c b/hw/stellaris.c
index 9b0db7f..2bf1c23 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -15,6 +15,7 @@
#include "i2c.h"
#include "net.h"
#include "boards.h"
+#include "exec-memory.h"
#define GPIO_A 0
#define GPIO_B 1
@@ -1260,6 +1261,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
0x40024000, 0x40025000, 0x40026000};
static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
+ MemoryRegion *address_space_mem = get_system_memory();
qemu_irq *pic;
DeviceState *gpio_dev[7];
qemu_irq gpio_in[7][8];
@@ -1274,7 +1276,8 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
flash_size = ((board->dc0 & 0xffff) + 1) << 1;
sram_size = (board->dc0 >> 18) + 1;
- pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model);
+ pic = armv7m_init(address_space_mem,
+ flash_size, sram_size, kernel_filename, cpu_model);
if (board->dc1 & (1 << 16)) {
dev = sysbus_create_varargs("stellaris-adc", 0x40038000,
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 07/22] axis_dev88: convert to memory API (RAM only)
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (5 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 06/22] armv7m: " Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 19:04 ` Edgar E. Iglesias
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 08/22] sysbus: add sysbus_add_memory_overlap() Avi Kivity
` (15 subsequent siblings)
22 siblings, 1 reply; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/axis_dev88.c | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c
index 06200e2..73eb39d 100644
--- a/hw/axis_dev88.c
+++ b/hw/axis_dev88.c
@@ -31,6 +31,7 @@
#include "elf.h"
#include "cris-boot.h"
#include "blockdev.h"
+#include "exec-memory.h"
#define D(x)
#define DNAND(x)
@@ -259,8 +260,9 @@ void axisdev88_init (ram_addr_t ram_size,
int i;
int nand_regs;
int gpio_regs;
- ram_addr_t phys_ram;
- ram_addr_t phys_intmem;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
+ MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
/* init CPUs */
if (cpu_model == NULL) {
@@ -269,15 +271,13 @@ void axisdev88_init (ram_addr_t ram_size,
env = cpu_init(cpu_model);
/* allocate RAM */
- phys_ram = qemu_ram_alloc(NULL, "axisdev88.ram", ram_size);
- cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
+ memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
+ memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
internal memory. */
- phys_intmem = qemu_ram_alloc(NULL, "axisdev88.chipram", INTMEM_SIZE);
- cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
- phys_intmem | IO_MEM_RAM);
-
+ memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
+ memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
/* Attach a NAND flash to CS1. */
nand = drive_get(IF_MTD, 0, 0);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 08/22] sysbus: add sysbus_add_memory_overlap()
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (6 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 07/22] axis_dev88: convert to memory API (RAM only) Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 17:00 ` Richard Henderson
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 09/22] integratorcp: convert to memory API (RAM/flash only) Avi Kivity
` (14 subsequent siblings)
22 siblings, 1 reply; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/sysbus.c | 6 ++++++
hw/sysbus.h | 2 ++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/hw/sysbus.c b/hw/sysbus.c
index f5f0ed2..4efb91a 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -263,6 +263,12 @@ void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
memory_region_add_subregion(get_system_memory(), addr, mem);
}
+void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
+ MemoryRegion *mem, unsigned priority)
+{
+ memory_region_add_subregion(get_system_memory(), addr, mem);
+}
+
void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem)
{
memory_region_del_subregion(get_system_memory(), mem);
diff --git a/hw/sysbus.h b/hw/sysbus.h
index e4d56cf..b3e1f99 100644
--- a/hw/sysbus.h
+++ b/hw/sysbus.h
@@ -59,6 +59,8 @@ void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr);
void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem);
+void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
+ MemoryRegion *mem, unsigned priority);
void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem);
void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH v2 08/22] sysbus: add sysbus_add_memory_overlap()
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 08/22] sysbus: add sysbus_add_memory_overlap() Avi Kivity
@ 2011-08-24 17:00 ` Richard Henderson
2011-08-24 17:11 ` Avi Kivity
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2011-08-24 17:00 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel
On 08/24/2011 03:40 AM, Avi Kivity wrote:
> +void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
> + MemoryRegion *mem, unsigned priority)
> +{
> + memory_region_add_subregion(get_system_memory(), addr, mem);
> +}
> +
memory_region_add_subregion_overlap, with "priority" actually used, surely?
r~
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH v2 08/22] sysbus: add sysbus_add_memory_overlap()
2011-08-24 17:00 ` Richard Henderson
@ 2011-08-24 17:11 ` Avi Kivity
0 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 17:11 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On 08/24/2011 08:00 PM, Richard Henderson wrote:
> On 08/24/2011 03:40 AM, Avi Kivity wrote:
> > +void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
> > + MemoryRegion *mem, unsigned priority)
> > +{
> > + memory_region_add_subregion(get_system_memory(), addr, mem);
> > +}
> > +
>
> memory_region_add_subregion_overlap, with "priority" actually used, surely?
>
>
Shirley can't write any code. I'll fix it up.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v2 09/22] integratorcp: convert to memory API (RAM/flash only)
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (7 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 08/22] sysbus: add sysbus_add_memory_overlap() Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 10/22] leon3: convert to memory API Avi Kivity
` (13 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/integratorcp.c | 28 ++++++++++++++++++++--------
1 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index 2814108..3c8982e 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -13,11 +13,13 @@
#include "boards.h"
#include "arm-misc.h"
#include "net.h"
+#include "exec-memory.h"
typedef struct {
SysBusDevice busdev;
uint32_t memsz;
- uint32_t flash_offset;
+ MemoryRegion flash;
+ bool flash_mapped;
uint32_t cm_osc;
uint32_t cm_ctrl;
uint32_t cm_lock;
@@ -108,9 +110,15 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
static void integratorcm_do_remap(integratorcm_state *s, int flash)
{
if (flash) {
- cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
+ if (s->flash_mapped) {
+ sysbus_del_memory(&s->busdev, &s->flash);
+ s->flash_mapped = false;
+ }
} else {
- cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
+ if (!s->flash_mapped) {
+ sysbus_add_memory_overlap(&s->busdev, 0, &s->flash, 1);
+ s->flash_mapped = true;
+ }
}
//??? tlb_flush (cpu_single_env, 1);
}
@@ -252,7 +260,8 @@ static int integratorcm_init(SysBusDevice *dev)
}
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
s->cm_init = 0x00000112;
- s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000);
+ memory_region_init_ram(&s->flash, NULL, "integrator.flash", 0x100000);
+ s->flash_mapped = false;
iomemtype = cpu_register_io_memory(integratorcm_readfn,
integratorcm_writefn, s,
@@ -456,7 +465,9 @@ static void integratorcp_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
- ram_addr_t ram_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
qemu_irq pic[32];
qemu_irq *cpu_pic;
DeviceState *dev;
@@ -469,13 +480,14 @@ static void integratorcp_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- ram_offset = qemu_ram_alloc(NULL, "integrator.ram", ram_size);
+ memory_region_init_ram(ram, NULL, "integrator.ram", ram_size);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero*/
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_add_subregion(address_space_mem, 0, ram);
/* And again at address 0x80000000 */
- cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
+ memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, "integrator_core");
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 10/22] leon3: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (8 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 09/22] integratorcp: convert to memory API (RAM/flash only) Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 11/22] cirrus: wrap memory update in a transaction Avi Kivity
` (12 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/leon3.c | 15 +++++++++------
1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/leon3.c b/hw/leon3.c
index a62a941..607ec85 100644
--- a/hw/leon3.c
+++ b/hw/leon3.c
@@ -29,6 +29,7 @@
#include "loader.h"
#include "elf.h"
#include "trace.h"
+#include "exec-memory.h"
#include "grlib.h"
@@ -100,7 +101,9 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
const char *cpu_model)
{
CPUState *env;
- ram_addr_t ram_offset, prom_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *prom = g_new(MemoryRegion, 1);
int ret;
char *filename;
qemu_irq *cpu_irqs = NULL;
@@ -139,14 +142,14 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
exit(1);
}
- ram_offset = qemu_ram_alloc(NULL, "leon3.ram", ram_size);
- cpu_register_physical_memory(0x40000000, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_init_ram(ram, NULL, "leon3.ram", ram_size);
+ memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Allocate BIOS */
prom_size = 8 * 1024 * 1024; /* 8Mb */
- prom_offset = qemu_ram_alloc(NULL, "Leon3.bios", prom_size);
- cpu_register_physical_memory(0x00000000, prom_size,
- prom_offset | IO_MEM_ROM);
+ memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size);
+ memory_region_set_readonly(prom, true);
+ memory_region_add_subregion(address_space_mem, 0x00000000, prom);
/* Load boot prom */
if (bios_name == NULL) {
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 11/22] cirrus: wrap memory update in a transaction
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (9 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 10/22] leon3: convert to memory API Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 12/22] piix_pci: " Avi Kivity
` (11 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
This prevents spurious unmapping and remapping of the vga windows,
which reduces performance.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/cirrus_vga.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 4d0ef0d..ec7ea82 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2424,6 +2424,7 @@ static void cirrus_update_memory_access(CirrusVGAState *s)
{
unsigned mode;
+ memory_region_transaction_begin();
if ((s->vga.sr[0x17] & 0x44) == 0x44) {
goto generic_io;
} else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
@@ -2443,6 +2444,7 @@ static void cirrus_update_memory_access(CirrusVGAState *s)
unmap_linear_vram(s);
}
}
+ memory_region_transaction_commit();
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 12/22] piix_pci: wrap memory update in a transaction
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (10 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 11/22] cirrus: wrap memory update in a transaction Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 13/22] Makefile.hw: allow hw/ files to include glib headers Avi Kivity
` (10 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
The code will remap all PAMs, even if just one is updated, resulting
in reduced performance. Wrap in a transaction to detect that those
other PAMs have not changed.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/piix_pci.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index f892994..8f6ea42 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -142,6 +142,7 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
int i, r;
uint32_t smram;
+ memory_region_transaction_begin();
update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
&d->pam_regions[0]);
for(i = 0; i < 12; i++) {
@@ -162,6 +163,7 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
d->smram_enabled = false;
}
}
+ memory_region_transaction_commit();
}
static void i440fx_set_smm(int val, void *arg)
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 13/22] Makefile.hw: allow hw/ files to include glib headers
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (11 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 12/22] piix_pci: " Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 14/22] pflash_cfi01/pflash_cfi02: convert to memory API Avi Kivity
` (9 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
Makefile.hw | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/Makefile.hw b/Makefile.hw
index 659e441..63eb7e4 100644
--- a/Makefile.hw
+++ b/Makefile.hw
@@ -10,6 +10,7 @@ include $(SRC_PATH)/rules.mak
$(call set-vpath, $(SRC_PATH):$(SRC_PATH)/hw)
QEMU_CFLAGS+=-I..
+QEMU_CFLAGS += $(GLIB_CFLAGS)
include $(SRC_PATH)/Makefile.objs
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 14/22] pflash_cfi01/pflash_cfi02: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (12 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 13/22] Makefile.hw: allow hw/ files to include glib headers Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-25 11:37 ` Jan Kiszka
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 15/22] dummy_m68k: " Avi Kivity
` (8 subsequent siblings)
22 siblings, 1 reply; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
cfi02 is annoying in that is ignores some address bits; we probably
want explicit support in the memory API for that.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/collie.c | 16 ++++---
hw/flash.h | 16 +++++--
hw/gumstix.c | 28 +++++++-----
hw/lm32_boards.c | 14 ++++---
hw/mainstone.c | 20 +++++----
hw/milkymist.c | 7 ++-
hw/mips_malta.c | 45 +++++++++++---------
hw/mips_r4k.c | 20 +++++----
hw/musicpal.c | 15 ++++---
hw/omap_sx1.c | 21 +++++----
hw/petalogix_ml605_mmu.c | 7 ++-
hw/petalogix_s3adsp1800_mmu.c | 8 ++-
hw/pflash_cfi01.c | 67 ++++++++++-------------------
hw/pflash_cfi02.c | 93 ++++++++++++++++++++---------------------
hw/ppc405_boards.c | 63 +++++++++++++++------------
hw/r2d.c | 7 ++-
hw/virtex_ml507.c | 7 ++-
hw/z2.c | 15 ++++---
18 files changed, 246 insertions(+), 223 deletions(-)
diff --git a/hw/collie.c b/hw/collie.c
index 156404d..0b955e0 100644
--- a/hw/collie.c
+++ b/hw/collie.c
@@ -26,7 +26,7 @@ static void collie_init(ram_addr_t ram_size,
{
StrongARMState *s;
DriveInfo *dinfo;
- ram_addr_t phys_flash;
+ MemoryRegion *phys_flash = g_new(MemoryRegion, 2);
if (!cpu_model) {
cpu_model = "sa1110";
@@ -34,17 +34,19 @@ static void collie_init(ram_addr_t ram_size,
s = sa1110_init(collie_binfo.ram_size, cpu_model);
- phys_flash = qemu_ram_alloc(NULL, "collie.fl1", 0x02000000);
+ memory_region_init_rom_device(&phys_flash[0], &pflash_cfi01_ops_le,
+ NULL, "collie.fl1", 0x02000000);
dinfo = drive_get(IF_PFLASH, 0, 0);
- pflash_cfi01_register(SA_CS0, phys_flash,
+ pflash_cfi01_register(SA_CS0, &phys_flash[0],
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
- 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
+ 512, 4, 0x00, 0x00, 0x00, 0x00);
- phys_flash = qemu_ram_alloc(NULL, "collie.fl2", 0x02000000);
+ memory_region_init_rom_device(&phys_flash[1], &pflash_cfi01_ops_le,
+ NULL, "collie.fl2", 0x02000000);
dinfo = drive_get(IF_PFLASH, 0, 1);
- pflash_cfi01_register(SA_CS1, phys_flash,
+ pflash_cfi01_register(SA_CS1, &phys_flash[1],
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
- 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
+ 512, 4, 0x00, 0x00, 0x00, 0x00);
sysbus_create_simple("scoop", 0x40800000, NULL);
diff --git a/hw/flash.h b/hw/flash.h
index 140ae39..7fb012b 100644
--- a/hw/flash.h
+++ b/hw/flash.h
@@ -1,21 +1,27 @@
+#include "memory.h"
+
/* NOR flash devices */
typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */
-pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
+extern const MemoryRegionOps pflash_cfi01_ops_be;
+extern const MemoryRegionOps pflash_cfi01_ops_le;
+extern const MemoryRegionOps pflash_cfi02_ops_be;
+extern const MemoryRegionOps pflash_cfi02_ops_le;
+
+pflash_t *pflash_cfi01_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
- uint16_t id2, uint16_t id3, int be);
+ uint16_t id2, uint16_t id3);
/* pflash_cfi02.c */
-pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
+pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3,
- uint16_t unlock_addr0, uint16_t unlock_addr1,
- int be);
+ uint16_t unlock_addr0, uint16_t unlock_addr1);
/* nand.c */
DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id);
diff --git a/hw/gumstix.c b/hw/gumstix.c
index 853f7e1..d3a4bb4 100644
--- a/hw/gumstix.c
+++ b/hw/gumstix.c
@@ -48,7 +48,8 @@ static void connex_init(ram_addr_t ram_size,
{
PXA2xxState *cpu;
DriveInfo *dinfo;
- int be;
+ const MemoryRegionOps *flash_ops;
+ MemoryRegion *flash = g_new(MemoryRegion, 1);
uint32_t connex_rom = 0x01000000;
uint32_t connex_ram = 0x04000000;
@@ -63,14 +64,15 @@ static void connex_init(ram_addr_t ram_size,
}
#ifdef TARGET_WORDS_BIGENDIAN
- be = 1;
+ flash_ops = &pflash_cfi01_ops_be;
#else
- be = 0;
+ flash_ops = &pflash_cfi01_ops_le;
#endif
- if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "connext.rom",
- connex_rom),
+ memory_region_init_rom_device(flash, flash_ops,
+ NULL, "connext.rom", connex_rom);
+ if (!pflash_cfi01_register(0x00000000, flash,
dinfo->bdrv, sector_len, connex_rom / sector_len,
- 2, 0, 0, 0, 0, be)) {
+ 2, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
@@ -87,7 +89,8 @@ static void verdex_init(ram_addr_t ram_size,
{
PXA2xxState *cpu;
DriveInfo *dinfo;
- int be;
+ MemoryRegion *flash = g_new(MemoryRegion, 1);
+ const MemoryRegionOps *flash_ops;
uint32_t verdex_rom = 0x02000000;
uint32_t verdex_ram = 0x10000000;
@@ -102,14 +105,15 @@ static void verdex_init(ram_addr_t ram_size,
}
#ifdef TARGET_WORDS_BIGENDIAN
- be = 1;
+ flash_ops = &pflash_cfi01_ops_be;
#else
- be = 0;
+ flash_ops = &pflash_cfi01_ops_le;
#endif
- if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "verdex.rom",
- verdex_rom),
+ memory_region_init_rom_device(flash, flash_ops,
+ NULL, "verdex.rom", verdex_rom);
+ if (!pflash_cfi01_register(0x00000000, flash,
dinfo->bdrv, sector_len, verdex_rom / sector_len,
- 2, 0, 0, 0, 0, be)) {
+ 2, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c
index d18aad7..f032bc0 100644
--- a/hw/lm32_boards.c
+++ b/hw/lm32_boards.c
@@ -77,7 +77,7 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
CPUState *env;
DriveInfo *dinfo;
ram_addr_t phys_ram;
- ram_addr_t phys_flash;
+ MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32];
ResetInfo *reset_info;
int i;
@@ -108,13 +108,14 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
- phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size);
+ memory_region_init_rom_device(phys_flash, &pflash_cfi02_ops_be,
+ NULL, "lm32_evr.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* Spansion S29NS128P */
pflash_cfi02_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 1, 2,
- 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
+ 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa);
/* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
@@ -165,7 +166,7 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
CPUState *env;
DriveInfo *dinfo;
ram_addr_t phys_ram;
- ram_addr_t phys_flash;
+ MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32];
HWSetup *hw;
ResetInfo *reset_info;
@@ -203,13 +204,14 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
- phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size);
+ memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
+ NULL, "lm32_uclinux.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* Spansion S29NS128P */
pflash_cfi02_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 1, 2,
- 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
+ 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa);
/* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
diff --git a/hw/mainstone.c b/hw/mainstone.c
index 4792f0e..78af41b 100644
--- a/hw/mainstone.c
+++ b/hw/mainstone.c
@@ -101,7 +101,8 @@ static void mainstone_common_init(ram_addr_t ram_size,
DeviceState *mst_irq;
DriveInfo *dinfo;
int i;
- int be;
+ MemoryRegion *flashes = g_new(MemoryRegion, 2);
+ const MemoryRegionOps *flash_ops;
if (!cpu_model)
cpu_model = "pxa270-c5";
@@ -113,9 +114,9 @@ static void mainstone_common_init(ram_addr_t ram_size,
MAINSTONE_ROM) | IO_MEM_ROM);
#ifdef TARGET_WORDS_BIGENDIAN
- be = 1;
+ flash_ops = &pflash_cfi01_ops_be;
#else
- be = 0;
+ flash_ops = &pflash_cfi01_ops_le;
#endif
/* There are two 32MiB flash devices on the board */
for (i = 0; i < 2; i ++) {
@@ -126,13 +127,14 @@ static void mainstone_common_init(ram_addr_t ram_size,
exit(1);
}
+ memory_region_init_rom_device(&flashes[i], flash_ops,
+ NULL, (i ? "mainstone.flash1"
+ : "mainstone.flash0"),
+ MAINSTONE_FLASH);
if (!pflash_cfi01_register(mainstone_flash_base[i],
- qemu_ram_alloc(NULL, i ? "mainstone.flash1" :
- "mainstone.flash0",
- MAINSTONE_FLASH),
- dinfo->bdrv, sector_len,
- MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0,
- be)) {
+ &flashes[i], dinfo->bdrv, sector_len,
+ MAINSTONE_FLASH / sector_len, 4, 0, 0, 0,
+ 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
diff --git a/hw/milkymist.c b/hw/milkymist.c
index 93288c8..092d8b0 100644
--- a/hw/milkymist.c
+++ b/hw/milkymist.c
@@ -82,7 +82,7 @@ milkymist_init(ram_addr_t ram_size_not_used,
int kernel_size;
DriveInfo *dinfo;
ram_addr_t phys_sdram;
- ram_addr_t phys_flash;
+ MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
int i;
char *bios_filename;
@@ -113,13 +113,14 @@ milkymist_init(ram_addr_t ram_size_not_used,
cpu_register_physical_memory(sdram_base, sdram_size,
phys_sdram | IO_MEM_RAM);
- phys_flash = qemu_ram_alloc(NULL, "milkymist.flash", flash_size);
+ memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
+ NULL, "milkymist.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* Numonyx JS28F256J3F105 */
pflash_cfi01_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 2,
- 0x00, 0x89, 0x00, 0x1d, 1);
+ 0x00, 0x89, 0x00, 0x1d);
/* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 86a8ba0..b5c9bcf 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -46,6 +46,7 @@
#include "elf.h"
#include "mc146818rtc.h"
#include "blockdev.h"
+#include "exec-memory.h"
//#define DEBUG_BOARD_INIT
@@ -762,7 +763,10 @@ void mips_malta_init (ram_addr_t ram_size,
{
char *filename;
ram_addr_t ram_offset;
- ram_addr_t bios_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
+ MemoryRegion *bios_1e0 = g_new(MemoryRegion, 1);
+ MemoryRegion *bios_1fc = g_new(MemoryRegion, 1);
target_long bios_size;
int64_t kernel_entry;
PCIBus *pci_bus;
@@ -777,7 +781,7 @@ void mips_malta_init (ram_addr_t ram_size,
DriveInfo *fd[MAX_FD];
int fl_idx = 0;
int fl_sectors = 0;
- int be;
+ const MemoryRegionOps *bios_ops;
/* Make sure the first 3 serial ports are associated with a device. */
for(i = 0; i < 3; i++) {
@@ -810,23 +814,24 @@ void mips_malta_init (ram_addr_t ram_size,
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
- ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size);
- bios_offset = qemu_ram_alloc(NULL, "mips_malta.bios", BIOS_SIZE);
+#ifdef TARGET_WORDS_BIGENDIAN
+ bios_ops = &pflash_cfi01_ops_be;
+#else
+ bios_ops = &pflash_cfi01_ops_le;
+#endif
+ ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size);
+ memory_region_init_rom_device(bios, bios_ops, NULL,
+ "mips_malta.bios", BIOS_SIZE);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
/* Map the bios at two physical locations, as on the real board. */
- cpu_register_physical_memory(0x1e000000LL,
- BIOS_SIZE, bios_offset | IO_MEM_ROM);
- cpu_register_physical_memory(0x1fc00000LL,
- BIOS_SIZE, bios_offset | IO_MEM_ROM);
+ memory_region_init_alias(bios_1e0, "bios-1e0", bios, 0, BIOS_SIZE);
+ memory_region_add_subregion(address_space_mem, 0x1e000000LL, bios_1e0);
+ memory_region_init_alias(bios_1fc, "bios-1fc", bios, 0, BIOS_SIZE);
+ memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios_1fc);
-#ifdef TARGET_WORDS_BIGENDIAN
- be = 1;
-#else
- be = 0;
-#endif
/* FPGA */
malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
@@ -838,7 +843,7 @@ void mips_malta_init (ram_addr_t ram_size,
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel();
- write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
+ write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
} else {
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
if (dinfo) {
@@ -847,13 +852,13 @@ void mips_malta_init (ram_addr_t ram_size,
fl_sectors = bios_size >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size " TARGET_FMT_lx " at "
- "offset %08lx addr %08llx '%s' %x\n",
- fl_idx, bios_size, bios_offset, 0x1e000000LL,
+ "addr %08llx '%s' %x\n",
+ fl_idx, bios_size, 0x1e000000LL,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
- pflash_cfi01_register(0x1e000000LL, bios_offset,
+ pflash_cfi01_register(0x1e000000LL, bios,
dinfo->bdrv, 65536, fl_sectors,
- 4, 0x0000, 0x0000, 0x0000, 0x0000, be);
+ 4, 0x0000, 0x0000, 0x0000, 0x0000);
fl_idx++;
} else {
/* Load a BIOS image. */
@@ -878,7 +883,7 @@ void mips_malta_init (ram_addr_t ram_size,
a neat trick which allows bi-endian firmware. */
#ifndef TARGET_WORDS_BIGENDIAN
{
- uint32_t *addr = qemu_get_ram_ptr(bios_offset);;
+ uint32_t *addr = memory_region_get_ram_ptr(bios);
uint32_t *end = addr + bios_size;
while (addr < end) {
bswap32s(addr);
@@ -890,7 +895,7 @@ void mips_malta_init (ram_addr_t ram_size,
/* Board ID = 0x420 (Malta Board with CoreLV)
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
map to the board ID. */
- stl_p(qemu_get_ram_ptr(bios_offset) + 0x10, 0x00000420);
+ stl_p(memory_region_get_ram_ptr(bios) + 0x10, 0x00000420);
/* Init internal devices */
cpu_mips_irq_init_cpu(env);
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 9d90568..51dc868 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -23,6 +23,7 @@
#include "elf.h"
#include "mc146818rtc.h"
#include "blockdev.h"
+#include "exec-memory.h"
#define MAX_IDE_BUS 2
@@ -163,7 +164,8 @@ void mips_r4k_init (ram_addr_t ram_size,
{
char *filename;
ram_addr_t ram_offset;
- ram_addr_t bios_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
int bios_size;
CPUState *env;
ResetData *reset_info;
@@ -227,18 +229,20 @@ void mips_r4k_init (ram_addr_t ram_size,
be = 0;
#endif
if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
- bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", BIOS_SIZE);
- cpu_register_physical_memory(0x1fc00000, BIOS_SIZE,
- bios_offset | IO_MEM_ROM);
-
+ memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE);
+ memory_region_set_readonly(bios, true);
+ memory_region_add_subregion(address_space_mem, 0x1fc00000, bios);
load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
} else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
uint32_t mips_rom = 0x00400000;
- bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", mips_rom);
- if (!pflash_cfi01_register(0x1fc00000, bios_offset,
+ memory_region_init_rom_device(bios,
+ (be ? &pflash_cfi01_ops_be
+ : &pflash_cfi01_ops_le),
+ NULL, "mips_r4k.bios", mips_rom);
+ if (!pflash_cfi01_register(0x1fc00000, bios,
dinfo->bdrv, sector_len,
mips_rom / sector_len,
- 4, 0, 0, 0, 0, be)) {
+ 4, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
}
}
diff --git a/hw/musicpal.c b/hw/musicpal.c
index 63dd391..5e74ee7 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -1502,6 +1502,7 @@ static void musicpal_init(ram_addr_t ram_size,
unsigned long flash_size;
DriveInfo *dinfo;
ram_addr_t sram_off;
+ MemoryRegion *flash = g_new(MemoryRegion, 1);
if (!cpu_model) {
cpu_model = "arm926";
@@ -1565,21 +1566,23 @@ static void musicpal_init(ram_addr_t ram_size,
* image is smaller than 32 MB.
*/
#ifdef TARGET_WORDS_BIGENDIAN
- pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
- "musicpal.flash", flash_size),
+ memory_region_init_rom_device(flash, &pflash_cfi02_ops_be,
+ NULL, "musicpal.flash", flash_size);
+ pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, flash,
dinfo->bdrv, 0x10000,
(flash_size + 0xffff) >> 16,
MP_FLASH_SIZE_MAX / flash_size,
2, 0x00BF, 0x236D, 0x0000, 0x0000,
- 0x5555, 0x2AAA, 1);
+ 0x5555, 0x2AAA);
#else
- pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
- "musicpal.flash", flash_size),
+ memory_region_init_rom_device(flash, &pflash_cfi02_ops_le,
+ NULL, "musicpal.flash", flash_size);
+ pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, flash,
dinfo->bdrv, 0x10000,
(flash_size + 0xffff) >> 16,
MP_FLASH_SIZE_MAX / flash_size,
2, 0x00BF, 0x236D, 0x0000, 0x0000,
- 0x5555, 0x2AAA, 0);
+ 0x5555, 0x2AAA);
#endif
}
diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c
index a7b687b..70364f4 100644
--- a/hw/omap_sx1.c
+++ b/hw/omap_sx1.c
@@ -129,7 +129,8 @@ static void sx1_init(ram_addr_t ram_size,
DriveInfo *dinfo;
int fl_idx;
uint32_t flash_size = flash0_size;
- int be;
+ const MemoryRegionOps *flash_ops;
+ MemoryRegion *flash = g_new(MemoryRegion, 2);
if (version == 2) {
flash_size = flash2_size;
@@ -155,17 +156,18 @@ static void sx1_init(ram_addr_t ram_size,
fl_idx = 0;
#ifdef TARGET_WORDS_BIGENDIAN
- be = 1;
+ flash_ops = &pflash_cfi01_ops_be;
#else
- be = 0;
+ flash_ops = &pflash_cfi01_ops_le;
#endif
if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
- if (!pflash_cfi01_register(OMAP_CS0_BASE, qemu_ram_alloc(NULL,
- "omap_sx1.flash0-1", flash_size),
+ memory_region_init_rom_device(&flash[0], flash_ops,
+ NULL, "omap_sx1.flash0-1", flash_size);
+ if (!pflash_cfi01_register(OMAP_CS0_BASE, &flash[0],
dinfo->bdrv, sector_size,
flash_size / sector_size,
- 4, 0, 0, 0, 0, be)) {
+ 4, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory %d.\n",
fl_idx);
}
@@ -182,11 +184,12 @@ static void sx1_init(ram_addr_t ram_size,
cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
OMAP_CS1_SIZE - flash1_size, io);
- if (!pflash_cfi01_register(OMAP_CS1_BASE, qemu_ram_alloc(NULL,
- "omap_sx1.flash1-1", flash1_size),
+ memory_region_init_rom_device(&flash[1], flash_ops,
+ NULL, "omap_sx1.flash1-1", flash1_size);
+ if (!pflash_cfi01_register(OMAP_CS1_BASE, &flash[1],
dinfo->bdrv, sector_size,
flash1_size / sector_size,
- 4, 0, 0, 0, 0, be)) {
+ 4, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory %d.\n",
fl_idx);
}
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index e3ca310..257fcca 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -149,7 +149,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
target_phys_addr_t ddr_base = MEMORY_BASEADDR;
ram_addr_t phys_lmb_bram;
ram_addr_t phys_ram;
- ram_addr_t phys_flash;
+ MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
@@ -169,14 +169,15 @@ petalogix_ml605_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "petalogix_ml605.ram", ram_size);
cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM);
- phys_flash = qemu_ram_alloc(NULL, "petalogix_ml605.flash", FLASH_SIZE);
+ memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_le,
+ NULL, "petalogix_ml605.flash", FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* 5th parameter 2 means bank-width
* 10th paremeter 0 means little-endian */
pflash_cfi01_register(FLASH_BASEADDR, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16,
- 2, 0x89, 0x18, 0x0000, 0x0, 0);
+ 2, 0x89, 0x18, 0x0000, 0x0);
cpu_irq = microblaze_pic_init_cpu(env);
diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c
index a43fb4c..1481745 100644
--- a/hw/petalogix_s3adsp1800_mmu.c
+++ b/hw/petalogix_s3adsp1800_mmu.c
@@ -127,7 +127,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
target_phys_addr_t ddr_base = 0x90000000;
ram_addr_t phys_lmb_bram;
ram_addr_t phys_ram;
- ram_addr_t phys_flash;
+ MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
@@ -148,12 +148,14 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.ram", ram_size);
cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM);
- phys_flash = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE);
+ memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
+ NULL, "petalogix_s3adsp1800.flash",
+ FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(0xa0000000, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16,
- 1, 0x89, 0x18, 0x0000, 0x0, 1);
+ 1, 0x89, 0x18, 0x0000, 0x0);
cpu_irq = microblaze_pic_init_cpu(env);
dev = xilinx_intc_create(0x81800000, cpu_irq[0], 2);
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index 90e1301..2144c6a 100644
--- a/hw/pflash_cfi01.c
+++ b/hw/pflash_cfi01.c
@@ -40,6 +40,7 @@
#include "flash.h"
#include "block.h"
#include "qemu-timer.h"
+#include "exec-memory.h"
#define PFLASH_BUG(fmt, ...) \
do { \
@@ -74,8 +75,7 @@ struct pflash_t {
target_phys_addr_t counter;
unsigned int writeblock_size;
QEMUTimer *timer;
- ram_addr_t off;
- int fl_mem;
+ MemoryRegion *mem;
void *storage;
};
@@ -89,8 +89,7 @@ static void pflash_timer (void *opaque)
if (pfl->bypass) {
pfl->wcycle = 2;
} else {
- cpu_register_physical_memory(pfl->base, pfl->total_len,
- pfl->off | IO_MEM_ROMD | pfl->fl_mem);
+ memory_region_rom_device_set_readable(pfl->mem, true);
pfl->wcycle = 0;
}
pfl->cmd = 0;
@@ -263,7 +262,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
if (!pfl->wcycle) {
/* Set the device in I/O access mode */
- cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
+ memory_region_rom_device_set_readable(pfl->mem, false);
}
switch (pfl->wcycle) {
@@ -422,8 +421,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
__func__, offset, pfl->wcycle, pfl->cmd, value);
reset_flash:
- cpu_register_physical_memory(pfl->base, pfl->total_len,
- pfl->off | IO_MEM_ROMD | pfl->fl_mem);
+ memory_region_rom_device_set_readable(pfl->mem, true);
pfl->bypass = 0;
pfl->wcycle = 0;
@@ -514,28 +512,20 @@ static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4, 0);
}
-static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
- &pflash_writeb_be,
- &pflash_writew_be,
- &pflash_writel_be,
+const MemoryRegionOps pflash_cfi01_ops_be = {
+ .old_mmio = {
+ .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
+ .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
- &pflash_readb_be,
- &pflash_readw_be,
- &pflash_readl_be,
-};
-
-static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
- &pflash_writeb_le,
- &pflash_writew_le,
- &pflash_writel_le,
-};
-
-static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
- &pflash_readb_le,
- &pflash_readw_le,
- &pflash_readl_le,
+const MemoryRegionOps pflash_cfi01_ops_le = {
+ .old_mmio = {
+ .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
+ .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* Count trailing zeroes of a 32 bits quantity */
@@ -574,12 +564,11 @@ static int ctz32 (uint32_t n)
return ret;
}
-pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
+pflash_t *pflash_cfi01_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int width,
uint16_t id0, uint16_t id1,
- uint16_t id2, uint16_t id3,
- int be)
+ uint16_t id2, uint16_t id3)
{
pflash_t *pfl;
target_phys_addr_t total_len;
@@ -597,26 +586,16 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
pfl = g_malloc0(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */
- pfl->storage = qemu_get_ram_ptr(off);
- if (be) {
- pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
- pflash_write_ops_be, pfl,
- DEVICE_NATIVE_ENDIAN);
- } else {
- pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
- pflash_write_ops_le, pfl,
- DEVICE_NATIVE_ENDIAN);
- }
- pfl->off = off;
- cpu_register_physical_memory(base, total_len,
- off | pfl->fl_mem | IO_MEM_ROMD);
+ pfl->storage = memory_region_get_ram_ptr(mem);
+ pfl->mem = mem;
+ memory_region_add_subregion(get_system_memory(), base, mem);
pfl->bs = bs;
if (pfl->bs) {
/* read the initial flash content */
ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
if (ret < 0) {
- cpu_unregister_io_memory(pfl->fl_mem);
+ memory_region_del_subregion(get_system_memory(), mem);
g_free(pfl);
return NULL;
}
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
index ac5115e..e7e0408 100644
--- a/hw/pflash_cfi02.c
+++ b/hw/pflash_cfi02.c
@@ -39,6 +39,7 @@
#include "flash.h"
#include "qemu-timer.h"
#include "block.h"
+#include "exec-memory.h"
//#define PFLASH_DEBUG
#ifdef PFLASH_DEBUG
@@ -69,25 +70,39 @@ struct pflash_t {
uint8_t cfi_len;
uint8_t cfi_table[0x52];
QEMUTimer *timer;
- ram_addr_t off;
- int fl_mem;
+ /* The device replicates the flash memory across its memory space. Emulate
+ * that by having a container (.mem) filled with an array of aliases
+ * (.mem_mappings) pointing to the flash memory (.orig_mem).
+ */
+ MemoryRegion mem;
+ MemoryRegion *mem_mappings; /* array; one per mapping */
+ MemoryRegion *orig_mem;
int rom_mode;
int read_counter; /* used for lazy switch-back to rom mode */
void *storage;
};
-static void pflash_register_memory(pflash_t *pfl, int rom_mode)
+/*
+ * Set up replicated mappings of the same region.
+ */
+static void pflash_setup_mappings(pflash_t *pfl, MemoryRegion *mem)
{
- unsigned long phys_offset = pfl->fl_mem;
- int i;
-
- if (rom_mode)
- phys_offset |= pfl->off | IO_MEM_ROMD;
- pfl->rom_mode = rom_mode;
+ unsigned i;
+ target_phys_addr_t size = memory_region_size(mem);
+
+ pfl->orig_mem = mem;
+ memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
+ pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
+ for (i = 0; i < pfl->mappings; ++i) {
+ memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias", mem,
+ 0, size);
+ memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
+ }
+}
- for (i = 0; i < pfl->mappings; i++)
- cpu_register_physical_memory(pfl->base + i * pfl->chip_len,
- pfl->chip_len, phys_offset);
+static void pflash_register_memory(pflash_t *pfl, int rom_mode)
+{
+ memory_region_rom_device_set_readable(pfl->orig_mem, rom_mode);
}
static void pflash_timer (void *opaque)
@@ -538,28 +553,20 @@ static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4, 0);
}
-static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
- &pflash_writeb_be,
- &pflash_writew_be,
- &pflash_writel_be,
-};
-
-static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
- &pflash_readb_be,
- &pflash_readw_be,
- &pflash_readl_be,
+const MemoryRegionOps pflash_cfi02_ops_be = {
+ .old_mmio = {
+ .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
+ .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
- &pflash_writeb_le,
- &pflash_writew_le,
- &pflash_writel_le,
-};
-
-static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
- &pflash_readb_le,
- &pflash_readw_le,
- &pflash_readl_le,
+const MemoryRegionOps pflash_cfi02_ops_le = {
+ .old_mmio = {
+ .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
+ .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* Count trailing zeroes of a 32 bits quantity */
@@ -598,13 +605,12 @@ static int ctz32 (uint32_t n)
return ret;
}
-pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
+pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3,
- uint16_t unlock_addr0, uint16_t unlock_addr1,
- int be)
+ uint16_t unlock_addr0, uint16_t unlock_addr1)
{
pflash_t *pfl;
int32_t chip_len;
@@ -619,31 +625,22 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
#endif
pfl = g_malloc0(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */
- pfl->storage = qemu_get_ram_ptr(off);
- if (be) {
- pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
- pflash_write_ops_be,
- pfl, DEVICE_NATIVE_ENDIAN);
- } else {
- pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
- pflash_write_ops_le,
- pfl, DEVICE_NATIVE_ENDIAN);
- }
- pfl->off = off;
+ pfl->storage = memory_region_get_ram_ptr(mem);
pfl->base = base;
pfl->chip_len = chip_len;
pfl->mappings = nb_mappings;
- pflash_register_memory(pfl, 1);
pfl->bs = bs;
if (pfl->bs) {
/* read the initial flash content */
ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
if (ret < 0) {
- cpu_unregister_io_memory(pfl->fl_mem);
g_free(pfl);
return NULL;
}
}
+ pflash_setup_mappings(pfl, mem);
+ pfl->rom_mode = 1;
+ memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem);
#if 0 /* XXX: there should be a bit to set up read-only,
* the same way the hardware does (with WP pin).
*/
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index dec165e..1eb807c 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -32,6 +32,7 @@
#include "qemu-log.h"
#include "loader.h"
#include "blockdev.h"
+#include "exec-memory.h"
#define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2048 * 1024)
@@ -181,7 +182,9 @@ static void ref405ep_init (ram_addr_t ram_size,
ppc4xx_bd_info_t bd;
CPUPPCState *env;
qemu_irq *pic;
- ram_addr_t sram_offset, bios_offset, bdloc;
+ ram_addr_t sram_offset, bdloc;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
target_ulong sram_size;
@@ -224,18 +227,18 @@ static void ref405ep_init (ram_addr_t ram_size,
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
if (dinfo) {
bios_size = bdrv_getlength(dinfo->bdrv);
- bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size);
+ memory_region_init_rom_device(bios, &pflash_cfi02_ops_be,
+ NULL, "ef405ep.bios", bios_size);
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx"
- " at offset %08lx addr %lx '%s' %d\n",
- fl_idx, bios_size, bios_offset, -bios_size,
+ " at addr %lx '%s' %d\n",
+ fl_idx, bios_size, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
- pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
+ pflash_cfi02_register((uint32_t)(-bios_size), bios,
dinfo->bdrv, 65536, fl_sectors, 1,
- 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
+ 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
fl_idx++;
} else
#endif
@@ -243,12 +246,12 @@ static void ref405ep_init (ram_addr_t ram_size,
#ifdef DEBUG_BOARD_INIT
printf("Load BIOS from file\n");
#endif
- bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE);
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
- bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
+ bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
g_free(filename);
} else {
bios_size = -1;
@@ -259,8 +262,9 @@ static void ref405ep_init (ram_addr_t ram_size,
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
- cpu_register_physical_memory((uint32_t)(-bios_size),
- bios_size, bios_offset | IO_MEM_ROM);
+ memory_region_set_readonly(bios, true);
+ memory_region_add_subregion(address_space_mem, (uint32_t)(-bios_size),
+ bios);
}
/* Register FPGA */
#ifdef DEBUG_BOARD_INIT
@@ -507,7 +511,9 @@ static void taihu_405ep_init(ram_addr_t ram_size,
{
char *filename;
qemu_irq *pic;
- ram_addr_t bios_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
+ MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
long bios_size;
@@ -544,17 +550,17 @@ static void taihu_405ep_init(ram_addr_t ram_size,
/* XXX: should check that size is 2MB */
// bios_size = 2 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16;
- bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size);
+ memory_region_init_rom_device(bios, &pflash_cfi02_ops_be,
+ NULL, "taihu_405ep.bios", bios_size);
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx"
- " at offset %08lx addr %lx '%s' %d\n",
- fl_idx, bios_size, bios_offset, -bios_size,
+ " at addr %lx '%s' %d\n",
+ fl_idx, bios_size, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
- pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
+ pflash_cfi02_register((uint32_t)(-bios_size), bios,
dinfo->bdrv, 65536, fl_sectors, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
+ 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
fl_idx++;
} else
#endif
@@ -564,10 +570,10 @@ static void taihu_405ep_init(ram_addr_t ram_size,
#endif
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
- bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
- bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
+ bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
g_free(filename);
} else {
bios_size = -1;
@@ -578,8 +584,9 @@ static void taihu_405ep_init(ram_addr_t ram_size,
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
- cpu_register_physical_memory((uint32_t)(-bios_size),
- bios_size, bios_offset | IO_MEM_ROM);
+ memory_region_set_readonly(bios, true);
+ memory_region_add_subregion(address_space_mem,
+ (uint32_t)(-bios_size), bios);
}
/* Register Linux flash */
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
@@ -590,15 +597,15 @@ static void taihu_405ep_init(ram_addr_t ram_size,
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx"
- " at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
- fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
+ " at addr " TARGET_FMT_lx " '%s'\n",
+ fl_idx, bios_size, (target_ulong)0xfc000000,
bdrv_get_device_name(dinfo->bdrv));
#endif
- bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size);
- pflash_cfi02_register(0xfc000000, bios_offset,
+ memory_region_init_rom_device(flash, &pflash_cfi02_ops_be,
+ NULL, "taihu_405ep.flash", bios_size);
+ pflash_cfi02_register(0xfc000000, flash,
dinfo->bdrv, 65536, fl_sectors, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
+ 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
fl_idx++;
}
/* Register CLPD & LCD display */
diff --git a/hw/r2d.c b/hw/r2d.c
index 96a7ff8..41aa2c2 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -235,6 +235,7 @@ static void r2d_init(ram_addr_t ram_size,
qemu_irq *irq;
DriveInfo *dinfo;
int i;
+ MemoryRegion *flash = g_new(MemoryRegion, 1);
if (!cpu_model)
cpu_model = "SH7751R";
@@ -267,11 +268,13 @@ static void r2d_init(ram_addr_t ram_size,
/* onboard flash memory */
dinfo = drive_get(IF_PFLASH, 0, 0);
- pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE),
+ memory_region_init_rom_device(flash, &pflash_cfi02_ops_le,
+ NULL, "r2d.flash", FLASH_SIZE);
+ pflash_cfi02_register(0x0, flash,
dinfo ? dinfo->bdrv : NULL, (16 * 1024),
FLASH_SIZE >> 16,
1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x555, 0x2aa, 0);
+ 0x555, 0x2aa);
/* NIC: rtl8139 on-board, and 2 slots. */
for (i = 0; i < nb_nics; i++)
diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c
index 333050c..aa9e512 100644
--- a/hw/virtex_ml507.c
+++ b/hw/virtex_ml507.c
@@ -196,7 +196,7 @@ static void virtex_init(ram_addr_t ram_size,
target_phys_addr_t ram_base = 0;
DriveInfo *dinfo;
ram_addr_t phys_ram;
- ram_addr_t phys_flash;
+ MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
clk_setup_t clk_setup[7];
int kernel_size;
@@ -215,12 +215,13 @@ static void virtex_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "ram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
- phys_flash = qemu_ram_alloc(NULL, "virtex.flash", FLASH_SIZE);
+ memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
+ NULL, "virtex.flash", FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(0xfc000000, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16,
- 1, 0x89, 0x18, 0x0000, 0x0, 1);
+ 1, 0x89, 0x18, 0x0000, 0x0);
cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
dev = xilinx_intc_create(0x81800000, cpu_irq[0], 0);
diff --git a/hw/z2.c b/hw/z2.c
index f93a1bf..d7b8d53 100644
--- a/hw/z2.c
+++ b/hw/z2.c
@@ -280,10 +280,11 @@ static void z2_init(ram_addr_t ram_size,
uint32_t sector_len = 0x10000;
PXA2xxState *cpu;
DriveInfo *dinfo;
- int be;
+ const MemoryRegionOps *flash_ops;
void *z2_lcd;
i2c_bus *bus;
DeviceState *wm;
+ MemoryRegion *flash = g_new(MemoryRegion, 1);
if (!cpu_model) {
cpu_model = "pxa270-c5";
@@ -293,9 +294,9 @@ static void z2_init(ram_addr_t ram_size,
cpu = pxa270_init(z2_binfo.ram_size, cpu_model);
#ifdef TARGET_WORDS_BIGENDIAN
- be = 1;
+ flash_ops = &pflash_cfi01_ops_be;
#else
- be = 0;
+ flash_ops = &pflash_cfi01_ops_le;
#endif
dinfo = drive_get(IF_PFLASH, 0, 0);
if (!dinfo) {
@@ -304,11 +305,11 @@ static void z2_init(ram_addr_t ram_size,
exit(1);
}
- if (!pflash_cfi01_register(Z2_FLASH_BASE,
- qemu_ram_alloc(NULL, "z2.flash0", Z2_FLASH_SIZE),
+ memory_region_init_rom_device(flash, flash_ops,
+ NULL, "z2.flash0", Z2_FLASH_SIZE);
+ if (!pflash_cfi01_register(Z2_FLASH_BASE, flash,
dinfo->bdrv, sector_len,
- Z2_FLASH_SIZE / sector_len, 4, 0, 0, 0, 0,
- be)) {
+ Z2_FLASH_SIZE / sector_len, 4, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH v2 14/22] pflash_cfi01/pflash_cfi02: convert to memory API
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 14/22] pflash_cfi01/pflash_cfi02: convert to memory API Avi Kivity
@ 2011-08-25 11:37 ` Jan Kiszka
2011-08-25 11:48 ` Avi Kivity
0 siblings, 1 reply; 29+ messages in thread
From: Jan Kiszka @ 2011-08-25 11:37 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel
On 2011-08-24 15:40, Avi Kivity wrote:
> cfi02 is annoying in that is ignores some address bits; we probably
> want explicit support in the memory API for that.
...
> diff --git a/hw/musicpal.c b/hw/musicpal.c
> index 63dd391..5e74ee7 100644
> --- a/hw/musicpal.c
> +++ b/hw/musicpal.c
> @@ -1502,6 +1502,7 @@ static void musicpal_init(ram_addr_t ram_size,
> unsigned long flash_size;
> DriveInfo *dinfo;
> ram_addr_t sram_off;
> + MemoryRegion *flash = g_new(MemoryRegion, 1);
>
> if (!cpu_model) {
> cpu_model = "arm926";
> @@ -1565,21 +1566,23 @@ static void musicpal_init(ram_addr_t ram_size,
> * image is smaller than 32 MB.
> */
> #ifdef TARGET_WORDS_BIGENDIAN
> - pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
> - "musicpal.flash", flash_size),
> + memory_region_init_rom_device(flash, &pflash_cfi02_ops_be,
> + NULL, "musicpal.flash", flash_size);
> + pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, flash,
> dinfo->bdrv, 0x10000,
> (flash_size + 0xffff) >> 16,
> MP_FLASH_SIZE_MAX / flash_size,
> 2, 0x00BF, 0x236D, 0x0000, 0x0000,
> - 0x5555, 0x2AAA, 1);
> + 0x5555, 0x2AAA);
> #else
> - pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
> - "musicpal.flash", flash_size),
> + memory_region_init_rom_device(flash, &pflash_cfi02_ops_le,
> + NULL, "musicpal.flash", flash_size);
> + pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, flash,
> dinfo->bdrv, 0x10000,
> (flash_size + 0xffff) >> 16,
> MP_FLASH_SIZE_MAX / flash_size,
> 2, 0x00BF, 0x236D, 0x0000, 0x0000,
> - 0x5555, 0x2AAA, 0);
> + 0x5555, 0x2AAA);
> #endif
This would deserve some reordering to reduce the code under #ifdef.
Anyway, it also breaks the musicpal (and presumably all other flash
users) because memory_region_init_rom_device is broken. It assumes
mr->ops is set, but I guess it rather should set that field itself, no?
Jan
--
Siemens AG, Corporate Technology, CT T DE IT 1
Corporate Competence Center Embedded Linux
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH v2 14/22] pflash_cfi01/pflash_cfi02: convert to memory API
2011-08-25 11:37 ` Jan Kiszka
@ 2011-08-25 11:48 ` Avi Kivity
0 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-25 11:48 UTC (permalink / raw)
To: Jan Kiszka; +Cc: qemu-devel
On 08/25/2011 02:37 PM, Jan Kiszka wrote:
> On 2011-08-24 15:40, Avi Kivity wrote:
> > cfi02 is annoying in that is ignores some address bits; we probably
> > want explicit support in the memory API for that.
>
> ...
>
> > diff --git a/hw/musicpal.c b/hw/musicpal.c
> > index 63dd391..5e74ee7 100644
> > --- a/hw/musicpal.c
> > +++ b/hw/musicpal.c
> > @@ -1502,6 +1502,7 @@ static void musicpal_init(ram_addr_t ram_size,
> > unsigned long flash_size;
> > DriveInfo *dinfo;
> > ram_addr_t sram_off;
> > + MemoryRegion *flash = g_new(MemoryRegion, 1);
> >
> > if (!cpu_model) {
> > cpu_model = "arm926";
> > @@ -1565,21 +1566,23 @@ static void musicpal_init(ram_addr_t ram_size,
> > * image is smaller than 32 MB.
> > */
> > #ifdef TARGET_WORDS_BIGENDIAN
> > - pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
> > - "musicpal.flash", flash_size),
> > + memory_region_init_rom_device(flash,&pflash_cfi02_ops_be,
> > + NULL, "musicpal.flash", flash_size);
> > + pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, flash,
> > dinfo->bdrv, 0x10000,
> > (flash_size + 0xffff)>> 16,
> > MP_FLASH_SIZE_MAX / flash_size,
> > 2, 0x00BF, 0x236D, 0x0000, 0x0000,
> > - 0x5555, 0x2AAA, 1);
> > + 0x5555, 0x2AAA);
> > #else
> > - pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
> > - "musicpal.flash", flash_size),
> > + memory_region_init_rom_device(flash,&pflash_cfi02_ops_le,
> > + NULL, "musicpal.flash", flash_size);
> > + pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, flash,
> > dinfo->bdrv, 0x10000,
> > (flash_size + 0xffff)>> 16,
> > MP_FLASH_SIZE_MAX / flash_size,
> > 2, 0x00BF, 0x236D, 0x0000, 0x0000,
> > - 0x5555, 0x2AAA, 0);
> > + 0x5555, 0x2AAA);
> > #endif
>
> This would deserve some reordering to reduce the code under #ifdef.
Sure, but I try to avoid refactoring in these conversions. We already
have too many regressions.
> Anyway, it also breaks the musicpal (and presumably all other flash
> users) because memory_region_init_rom_device is broken. It assumes
> mr->ops is set, but I guess it rather should set that field itself, no?
>
Right, thanks.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v2 15/22] dummy_m68k: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (13 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 14/22] pflash_cfi01/pflash_cfi02: convert to memory API Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 16/22] g364fb: " Avi Kivity
` (7 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/dummy_m68k.c | 7 +++++--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/dummy_m68k.c b/hw/dummy_m68k.c
index eed9e38..30146b9 100644
--- a/hw/dummy_m68k.c
+++ b/hw/dummy_m68k.c
@@ -10,6 +10,7 @@
#include "boards.h"
#include "loader.h"
#include "elf.h"
+#include "exec-memory.h"
#define KERNEL_LOAD_ADDR 0x10000
@@ -21,6 +22,8 @@ static void dummy_m68k_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
@@ -37,8 +40,8 @@ static void dummy_m68k_init(ram_addr_t ram_size,
env->vbr = 0;
/* RAM at address zero */
- cpu_register_physical_memory(0, ram_size,
- qemu_ram_alloc(NULL, "dummy_m68k.ram", ram_size) | IO_MEM_RAM);
+ memory_region_init_ram(ram, NULL, "dummy_m68k.ram", ram_size);
+ memory_region_add_subregion(address_space_mem, 0, ram);
/* Load kernel. */
if (kernel_filename) {
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 16/22] g364fb: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (14 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 15/22] dummy_m68k: " Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 17/22] lm32_boards: " Avi Kivity
` (6 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/g364fb.c | 60 ++++++++++++++++++++++++++++++-------------------------
hw/mips.h | 4 ++-
hw/mips_jazz.c | 3 +-
3 files changed, 38 insertions(+), 29 deletions(-)
diff --git a/hw/g364fb.c b/hw/g364fb.c
index b3020c5..a7731ec 100644
--- a/hw/g364fb.c
+++ b/hw/g364fb.c
@@ -36,7 +36,7 @@ do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0)
typedef struct G364State {
/* hardware */
uint8_t *vram;
- ram_addr_t vram_offset;
+ MemoryRegion vram_region;
int vram_size;
qemu_irq irq;
/* registers */
@@ -68,16 +68,17 @@ typedef struct G364State {
#define CTLA_FORCE_BLANK 0x00000400
#define CTLA_NO_CURSOR 0x00800000
-static inline int check_dirty(ram_addr_t page)
+static inline int check_dirty(G364State *s, ram_addr_t page)
{
- return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
+ return memory_region_get_dirty(&s->vram_region, page, DIRTY_MEMORY_VGA);
}
static inline void reset_dirty(G364State *s,
ram_addr_t page_min, ram_addr_t page_max)
{
- cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 1,
- VGA_DIRTY_FLAG);
+ memory_region_reset_dirty(&s->vram_region, page_min,
+ page_max + TARGET_PAGE_SIZE - 1,
+ DIRTY_MEMORY_VGA);
}
static void g364fb_draw_graphic8(G364State *s)
@@ -114,7 +115,7 @@ static void g364fb_draw_graphic8(G364State *s)
return;
}
- page = s->vram_offset;
+ page = 0;
page_min = (ram_addr_t)-1;
page_max = 0;
@@ -135,7 +136,7 @@ static void g364fb_draw_graphic8(G364State *s)
/* XXX: out of range in vram? */
data_display = dd = ds_get_data(s->ds);
while (y < s->height) {
- if (check_dirty(page)) {
+ if (check_dirty(s, page)) {
if (y < ymin)
ymin = ymax = y;
if (page_min == (ram_addr_t)-1)
@@ -275,7 +276,7 @@ static inline void g364fb_invalidate_display(void *opaque)
s->blanked = 0;
for (i = 0; i < s->vram_size; i += TARGET_PAGE_SIZE) {
- cpu_physical_memory_set_dirty(s->vram_offset + i);
+ memory_region_set_dirty(&s->vram_region, i);
}
}
@@ -411,7 +412,7 @@ static void g364_invalidate_cursor_position(G364State *s)
end = (ymax + 1) * ds_get_linesize(s->ds);
for (i = start; i < end; i += TARGET_PAGE_SIZE) {
- cpu_physical_memory_set_dirty(s->vram_offset + i);
+ memory_region_set_dirty(&s->vram_region, i);
}
}
@@ -522,16 +523,20 @@ static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t v
g364fb_ctrl_writel(opaque, addr & ~0x3, val);
}
-static CPUReadMemoryFunc * const g364fb_ctrl_read[3] = {
- g364fb_ctrl_readb,
- g364fb_ctrl_readw,
- g364fb_ctrl_readl,
-};
-
-static CPUWriteMemoryFunc * const g364fb_ctrl_write[3] = {
- g364fb_ctrl_writeb,
- g364fb_ctrl_writew,
- g364fb_ctrl_writel,
+static const MemoryRegionOps g364fb_ctrl_ops = {
+ .old_mmio = {
+ .read = {
+ g364fb_ctrl_readb,
+ g364fb_ctrl_readw,
+ g364fb_ctrl_readl,
+ },
+ .write = {
+ g364fb_ctrl_writeb,
+ g364fb_ctrl_writew,
+ g364fb_ctrl_writel,
+ },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int g364fb_load(QEMUFile *f, void *opaque, int version_id)
@@ -583,18 +588,19 @@ static void g364fb_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->height);
}
-int g364fb_mm_init(target_phys_addr_t vram_base,
+int g364fb_mm_init(MemoryRegion *system_memory,
+ target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq)
{
G364State *s;
- int io_ctrl;
+ MemoryRegion *io_ctrl = g_new(MemoryRegion, 1);
s = g_malloc0(sizeof(G364State));
s->vram_size = 8 * 1024 * 1024;
- s->vram_offset = qemu_ram_alloc(NULL, "g364fb.vram", s->vram_size);
- s->vram = qemu_get_ram_ptr(s->vram_offset);
+ memory_region_init_ram(&s->vram_region, NULL, "g364fb.vram", s->vram_size);
+ s->vram = memory_region_get_ram_ptr(&s->vram_region);
s->irq = irq;
qemu_register_reset(g364fb_reset, s);
@@ -605,11 +611,11 @@ int g364fb_mm_init(target_phys_addr_t vram_base,
g364fb_invalidate_display,
g364fb_screen_dump, NULL, s);
- cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
+ memory_region_add_subregion(system_memory, vram_base, &s->vram_region);
- io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
+ memory_region_init_io(io_ctrl, &g364fb_ctrl_ops, s,
+ "g364fb-ctrl", 0x200000);
+ memory_region_add_subregion(system_memory, ctrl_base, io_ctrl);
return 0;
}
diff --git a/hw/mips.h b/hw/mips.h
index cae5f4c..97d7b9e 100644
--- a/hw/mips.h
+++ b/hw/mips.h
@@ -2,6 +2,8 @@
#define HW_MIPS_H
/* Definitions for mips board emulation. */
+#include "memory.h"
+
/* gt64xxx.c */
PCIBus *gt64120_register(qemu_irq *pic);
@@ -9,7 +11,7 @@ PCIBus *gt64120_register(qemu_irq *pic);
PCIBus *bonito_init(qemu_irq *pic);
/* g364fb.c */
-int g364fb_mm_init(target_phys_addr_t vram_base,
+int g364fb_mm_init(MemoryRegion *system_memory, target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq);
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 84ce061..a741086 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -195,7 +195,8 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
- g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
+ g364fb_mm_init(get_system_memory(), 0x40000000, 0x60000000, 0,
+ rc4030[3]);
break;
case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 17/22] lm32_boards: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (15 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 16/22] g364fb: " Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 18/22] mainstone: " Avi Kivity
` (5 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/lm32_boards.c | 15 +++++++++------
1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c
index f032bc0..a84007b 100644
--- a/hw/lm32_boards.c
+++ b/hw/lm32_boards.c
@@ -28,6 +28,7 @@
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"
+#include "exec-memory.h"
typedef struct {
CPUState *env;
@@ -76,7 +77,8 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
{
CPUState *env;
DriveInfo *dinfo;
- ram_addr_t phys_ram;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32];
ResetInfo *reset_info;
@@ -105,8 +107,8 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
reset_info->flash_base = flash_base;
- phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
- cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
+ memory_region_init_ram(phys_ram, NULL, "lm32_evr.sdram", ram_size);
+ memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
memory_region_init_rom_device(phys_flash, &pflash_cfi02_ops_be,
NULL, "lm32_evr.flash", flash_size);
@@ -165,7 +167,8 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
{
CPUState *env;
DriveInfo *dinfo;
- ram_addr_t phys_ram;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32];
HWSetup *hw;
@@ -201,8 +204,8 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
reset_info->flash_base = flash_base;
- phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
- cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
+ memory_region_init_ram(phys_ram, NULL, "lm32_uclinux.sdram", ram_size);
+ memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
NULL, "lm32_uclinux.flash", flash_size);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 18/22] mainstone: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (16 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 17/22] lm32_boards: " Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 19/22] mcf5208: " Avi Kivity
` (4 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/mainstone.c | 13 ++++++++-----
1 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/mainstone.c b/hw/mainstone.c
index 78af41b..82e9571 100644
--- a/hw/mainstone.c
+++ b/hw/mainstone.c
@@ -17,6 +17,7 @@
#include "flash.h"
#include "blockdev.h"
#include "sysbus.h"
+#include "exec-memory.h"
/* Device addresses */
#define MST_FPGA_PHYS 0x08000000
@@ -90,7 +91,8 @@ static struct arm_boot_info mainstone_binfo = {
.ram_size = 0x04000000,
};
-static void mainstone_common_init(ram_addr_t ram_size,
+static void mainstone_common_init(MemoryRegion *address_space_mem,
+ ram_addr_t ram_size,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
@@ -101,6 +103,7 @@ static void mainstone_common_init(ram_addr_t ram_size,
DeviceState *mst_irq;
DriveInfo *dinfo;
int i;
+ MemoryRegion *rom = g_new(MemoryRegion, 1);
MemoryRegion *flashes = g_new(MemoryRegion, 2);
const MemoryRegionOps *flash_ops;
@@ -109,9 +112,9 @@ static void mainstone_common_init(ram_addr_t ram_size,
/* Setup CPU & memory */
cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model);
- cpu_register_physical_memory(0, MAINSTONE_ROM,
- qemu_ram_alloc(NULL, "mainstone.rom",
- MAINSTONE_ROM) | IO_MEM_ROM);
+ memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM);
+ memory_region_set_readonly(rom, true);
+ memory_region_add_subregion(address_space_mem, 0, rom);
#ifdef TARGET_WORDS_BIGENDIAN
flash_ops = &pflash_cfi01_ops_be;
@@ -172,7 +175,7 @@ static void mainstone_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mainstone_common_init(ram_size, kernel_filename,
+ mainstone_common_init(get_system_memory(), ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 19/22] mcf5208: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (17 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 18/22] mainstone: " Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 20/22] milkymist-minimac2: " Avi Kivity
` (3 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/mcf5208.c | 72 +++++++++++++++++++++++++--------------------------------
1 files changed, 32 insertions(+), 40 deletions(-)
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index 8fe507f..1c2c0c4 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -13,6 +13,7 @@
#include "boards.h"
#include "loader.h"
#include "elf.h"
+#include "exec-memory.h"
#define SYS_FREQ 66000000
@@ -27,6 +28,7 @@
#define PCSR_PRE_MASK 0x0f00
typedef struct {
+ MemoryRegion iomem;
qemu_irq irq;
ptimer_state *timer;
uint16_t pcsr;
@@ -43,7 +45,7 @@ static void m5208_timer_update(m5208_timer_state *s)
}
static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
int prescale;
@@ -104,7 +106,8 @@ static void m5208_timer_trigger(void *opaque)
m5208_timer_update(s);
}
-static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
+static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
switch (addr) {
@@ -120,19 +123,14 @@ static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
}
}
-static CPUReadMemoryFunc * const m5208_timer_readfn[] = {
- m5208_timer_read,
- m5208_timer_read,
- m5208_timer_read
+static const MemoryRegionOps m5208_timer_ops = {
+ .read = m5208_timer_read,
+ .write = m5208_timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
- m5208_timer_write,
- m5208_timer_write,
- m5208_timer_write
-};
-
-static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
+static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
switch (addr) {
case 0x110: /* SDCS0 */
@@ -154,45 +152,36 @@ static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
}
static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
}
-static CPUReadMemoryFunc * const m5208_sys_readfn[] = {
- m5208_sys_read,
- m5208_sys_read,
- m5208_sys_read
-};
-
-static CPUWriteMemoryFunc * const m5208_sys_writefn[] = {
- m5208_sys_write,
- m5208_sys_write,
- m5208_sys_write
+static const MemoryRegionOps m5208_sys_ops = {
+ .read = m5208_sys_read,
+ .write = m5208_sys_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static void mcf5208_sys_init(qemu_irq *pic)
+static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
{
- int iomemtype;
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);
m5208_timer_state *s;
QEMUBH *bh;
int i;
- iomemtype = cpu_register_io_memory(m5208_sys_readfn,
- m5208_sys_writefn, NULL,
- DEVICE_NATIVE_ENDIAN);
/* SDRAMC. */
- cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
+ memory_region_init_io(iomem, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
+ memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
/* Timers. */
for (i = 0; i < 2; i++) {
s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
bh = qemu_bh_new(m5208_timer_trigger, s);
s->timer = ptimer_init(bh);
- iomemtype = cpu_register_io_memory(m5208_timer_readfn,
- m5208_timer_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
- iomemtype);
+ memory_region_init_io(&s->iomem, &m5208_timer_ops, s,
+ "m5208-timer", 0x00004000);
+ memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
+ &s->iomem);
s->irq = pic[4 + i];
}
}
@@ -207,6 +196,9 @@ static void mcf5208evb_init(ram_addr_t ram_size,
uint64_t elf_entry;
target_phys_addr_t entry;
qemu_irq *pic;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model)
cpu_model = "m5208";
@@ -221,12 +213,12 @@ static void mcf5208evb_init(ram_addr_t ram_size,
/* TODO: Configure BARs. */
/* DRAM at 0x40000000 */
- cpu_register_physical_memory(0x40000000, ram_size,
- qemu_ram_alloc(NULL, "mcf5208.ram", ram_size) | IO_MEM_RAM);
+ memory_region_init_ram(ram, NULL, "mcf5208.ram", ram_size);
+ memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Internal SRAM. */
- cpu_register_physical_memory(0x80000000, 16384,
- qemu_ram_alloc(NULL, "mcf5208.sram", 16384) | IO_MEM_RAM);
+ memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384);
+ memory_region_add_subregion(address_space_mem, 0x80000000, sram);
/* Internal peripherals. */
pic = mcf_intc_init(0xfc048000, env);
@@ -235,7 +227,7 @@ static void mcf5208evb_init(ram_addr_t ram_size,
mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
- mcf5208_sys_init(pic);
+ mcf5208_sys_init(address_space_mem, pic);
if (nb_nics > 1) {
fprintf(stderr, "Too many NICs\n");
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 20/22] milkymist-minimac2: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (18 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 19/22] mcf5208: " Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 21/22] milkymist-softusb: " Avi Kivity
` (2 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/milkymist-minimac2.c | 43 +++++++++++++++++++++----------------------
1 files changed, 21 insertions(+), 22 deletions(-)
diff --git a/hw/milkymist-minimac2.c b/hw/milkymist-minimac2.c
index cd36026..fb48e37 100644
--- a/hw/milkymist-minimac2.c
+++ b/hw/milkymist-minimac2.c
@@ -97,6 +97,8 @@ struct MilkymistMinimac2State {
NICConf conf;
char *phy_model;
target_phys_addr_t buffers_base;
+ MemoryRegion buffers;
+ MemoryRegion regs_region;
qemu_irq rx_irq;
qemu_irq tx_irq;
@@ -320,8 +322,8 @@ static ssize_t minimac2_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
return size;
}
-static uint32_t
-minimac2_read(void *opaque, target_phys_addr_t addr)
+static uint64_t
+minimac2_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
MilkymistMinimac2State *s = opaque;
uint32_t r = 0;
@@ -350,7 +352,8 @@ minimac2_read(void *opaque, target_phys_addr_t addr)
}
static void
-minimac2_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+ unsigned size)
{
MilkymistMinimac2State *s = opaque;
@@ -395,16 +398,14 @@ minimac2_write(void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
-static CPUReadMemoryFunc * const minimac2_read_fn[] = {
- NULL,
- NULL,
- &minimac2_read,
-};
-
-static CPUWriteMemoryFunc * const minimac2_write_fn[] = {
- NULL,
- NULL,
- &minimac2_write,
+static const MemoryRegionOps minimac2_ops = {
+ .read = minimac2_read,
+ .write = minimac2_write,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int minimac2_can_rx(VLANClientState *nc)
@@ -457,25 +458,23 @@ static NetClientInfo net_milkymist_minimac2_info = {
static int milkymist_minimac2_init(SysBusDevice *dev)
{
MilkymistMinimac2State *s = FROM_SYSBUS(typeof(*s), dev);
- int regs;
- ram_addr_t buffers;
size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
sysbus_init_irq(dev, &s->rx_irq);
sysbus_init_irq(dev, &s->tx_irq);
- regs = cpu_register_io_memory(minimac2_read_fn, minimac2_write_fn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, R_MAX * 4, regs);
+ memory_region_init_io(&s->regs_region, &minimac2_ops, s,
+ "minimac2-mmio", R_MAX * 4);
+ sysbus_init_mmio_region(dev, &s->regs_region);
/* register buffers memory */
- buffers = qemu_ram_alloc(NULL, "milkymist_minimac2.buffers", buffers_size);
- s->rx0_buf = qemu_get_ram_ptr(buffers);
+ memory_region_init_ram(&s->buffers, NULL, "milkymist_minimac2.buffers",
+ buffers_size);
+ s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
- cpu_register_physical_memory(s->buffers_base, buffers_size,
- buffers | IO_MEM_RAM);
+ sysbus_add_memory(dev, s->buffers_base, &s->buffers);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 21/22] milkymist-softusb: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (19 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 20/22] milkymist-minimac2: " Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 22/22] milkymist: " Avi Kivity
2011-08-24 17:10 ` [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Richard Henderson
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/milkymist-softusb.c | 48 ++++++++++++++++++++++++------------------------
1 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/hw/milkymist-softusb.c b/hw/milkymist-softusb.c
index fe4eedb..ef4d9ee 100644
--- a/hw/milkymist-softusb.c
+++ b/hw/milkymist-softusb.c
@@ -49,6 +49,9 @@ struct MilkymistSoftUsbState {
HIDState hid_kbd;
HIDState hid_mouse;
+ MemoryRegion regs_region;
+ MemoryRegion pmem;
+ MemoryRegion dmem;
qemu_irq irq;
/* device properties */
@@ -68,7 +71,8 @@ struct MilkymistSoftUsbState {
};
typedef struct MilkymistSoftUsbState MilkymistSoftUsbState;
-static uint32_t softusb_read(void *opaque, target_phys_addr_t addr)
+static uint64_t softusb_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
MilkymistSoftUsbState *s = opaque;
uint32_t r = 0;
@@ -91,7 +95,8 @@ static uint32_t softusb_read(void *opaque, target_phys_addr_t addr)
}
static void
-softusb_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+softusb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+ unsigned size)
{
MilkymistSoftUsbState *s = opaque;
@@ -110,16 +115,14 @@ softusb_write(void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
-static CPUReadMemoryFunc * const softusb_read_fn[] = {
- NULL,
- NULL,
- &softusb_read,
-};
-
-static CPUWriteMemoryFunc * const softusb_write_fn[] = {
- NULL,
- NULL,
- &softusb_write,
+static const MemoryRegionOps softusb_mmio_ops = {
+ .read = softusb_read,
+ .write = softusb_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static inline void softusb_read_dmem(MilkymistSoftUsbState *s,
@@ -256,23 +259,20 @@ static void milkymist_softusb_reset(DeviceState *d)
static int milkymist_softusb_init(SysBusDevice *dev)
{
MilkymistSoftUsbState *s = FROM_SYSBUS(typeof(*s), dev);
- int softusb_regs;
- ram_addr_t pmem_ram;
- ram_addr_t dmem_ram;
sysbus_init_irq(dev, &s->irq);
- softusb_regs = cpu_register_io_memory(softusb_read_fn, softusb_write_fn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, R_MAX * 4, softusb_regs);
+ memory_region_init_io(&s->regs_region, &softusb_mmio_ops, s,
+ "milkymist-softusb", R_MAX * 4);
+ sysbus_init_mmio_region(dev, &s->regs_region);
/* register pmem and dmem */
- pmem_ram = qemu_ram_alloc(NULL, "milkymist_softusb.pmem", s->pmem_size);
- cpu_register_physical_memory(s->pmem_base, s->pmem_size,
- pmem_ram | IO_MEM_RAM);
- dmem_ram = qemu_ram_alloc(NULL, "milkymist_softusb.dmem", s->dmem_size);
- cpu_register_physical_memory(s->dmem_base, s->dmem_size,
- dmem_ram | IO_MEM_RAM);
+ memory_region_init_ram(&s->pmem, NULL, "milkymist_softusb.pmem",
+ s->pmem_size);
+ sysbus_add_memory(dev, s->pmem_base, &s->pmem);
+ memory_region_init_ram(&s->dmem, NULL, "milkymist_softusb.dmem",
+ s->dmem_size);
+ sysbus_add_memory(dev, s->dmem_base, &s->dmem);
hid_init(&s->hid_kbd, HID_KEYBOARD, softusb_kbd_hid_datain);
hid_init(&s->hid_mouse, HID_MOUSE, softusb_mouse_hid_datain);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH v2 22/22] milkymist: convert to memory API
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (20 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 21/22] milkymist-softusb: " Avi Kivity
@ 2011-08-24 13:40 ` Avi Kivity
2011-08-24 17:10 ` [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Richard Henderson
22 siblings, 0 replies; 29+ messages in thread
From: Avi Kivity @ 2011-08-24 13:40 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/milkymist.c | 9 +++++----
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/milkymist.c b/hw/milkymist.c
index 092d8b0..ef21cca 100644
--- a/hw/milkymist.c
+++ b/hw/milkymist.c
@@ -29,6 +29,7 @@
#include "blockdev.h"
#include "milkymist-hw.h"
#include "lm32.h"
+#include "exec-memory.h"
#define BIOS_FILENAME "mmone-bios.bin"
#define BIOS_OFFSET 0x00860000
@@ -81,7 +82,8 @@ milkymist_init(ram_addr_t ram_size_not_used,
CPUState *env;
int kernel_size;
DriveInfo *dinfo;
- ram_addr_t phys_sdram;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *phys_sdram = g_new(MemoryRegion, 1);
MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
int i;
@@ -109,9 +111,8 @@ milkymist_init(ram_addr_t ram_size_not_used,
cpu_lm32_set_phys_msb_ignore(env, 1);
- phys_sdram = qemu_ram_alloc(NULL, "milkymist.sdram", sdram_size);
- cpu_register_physical_memory(sdram_base, sdram_size,
- phys_sdram | IO_MEM_RAM);
+ memory_region_init_ram(phys_sdram, NULL, "milkymist.sdram", sdram_size);
+ memory_region_add_subregion(address_space_mem, sdram_base, phys_sdram);
memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
NULL, "milkymist.flash", flash_size);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5
2011-08-24 13:40 [Qemu-devel] [PATCH v2 00/22] Memory API conversions, batch 5 Avi Kivity
` (21 preceding siblings ...)
2011-08-24 13:40 ` [Qemu-devel] [PATCH v2 22/22] milkymist: " Avi Kivity
@ 2011-08-24 17:10 ` Richard Henderson
22 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2011-08-24 17:10 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel
On 08/24/2011 03:40 AM, Avi Kivity wrote:
> This is a collection of random conversions to devices to the new memory API.
> Some qemu interfaces are also update, for example machine creation and
> sysbus.
>
> Please review. If all is fine, I will post a [PULL] request for the batch
> (in git://git.kernel.org/pub/scm/virt/kvm/qemu-kvm.git memory/batch).
All except 8/22:
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread