* [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups
@ 2011-08-09 12:43 Aneesh V
2011-08-09 12:43 ` [U-Boot] [PATCH 1/3] omap4: factor out common part from board config headers Aneesh V
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Aneesh V @ 2011-08-09 12:43 UTC (permalink / raw)
To: u-boot
Aneesh V (3):
omap4: factor out common part from board config headers
omap4: make SDRAM init work for ES1.0 silicon
omap4: IO settings
arch/arm/cpu/armv7/omap4/board.c | 57 +++++++
arch/arm/cpu/armv7/omap4/emif.c | 72 +-------
arch/arm/cpu/armv7/omap4/sdram_elpida.c | 24 ++--
arch/arm/include/asm/arch-omap4/emif.h | 19 +--
arch/arm/include/asm/arch-omap4/omap4.h | 35 ++++-
include/configs/omap4_common.h | 275 +++++++++++++++++++++++++++++++
include/configs/omap4_panda.h | 245 +---------------------------
include/configs/omap4_sdp4430.h | 246 +---------------------------
8 files changed, 402 insertions(+), 571 deletions(-)
create mode 100644 include/configs/omap4_common.h
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 1/3] omap4: factor out common part from board config headers
2011-08-09 12:43 [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups Aneesh V
@ 2011-08-09 12:43 ` Aneesh V
2011-08-09 12:43 ` [U-Boot] [PATCH 2/3] omap4: make SDRAM init work for ES1.0 silicon Aneesh V
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aneesh V @ 2011-08-09 12:43 UTC (permalink / raw)
To: u-boot
Factor out common parts from omap4_sdp4430.h and omap4_panda.h
into a new file omap4_common.h
Signed-off-by: Aneesh V <aneesh@ti.com>
---
include/configs/omap4_common.h | 275 +++++++++++++++++++++++++++++++++++++++
include/configs/omap4_panda.h | 245 +----------------------------------
include/configs/omap4_sdp4430.h | 246 +----------------------------------
3 files changed, 288 insertions(+), 478 deletions(-)
create mode 100644 include/configs/omap4_common.h
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
new file mode 100644
index 0000000..ea39a39
--- /dev/null
+++ b/include/configs/omap4_common.h
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * TI OMAP4 common configuration settings
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_OMAP4_COMMON_H
+#define __CONFIG_OMAP4_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP44XX 1 /* which is a 44XX */
+#define CONFIG_OMAP4430 1 /* which is in a 4430 */
+#define CONFIG_ARCH_CPU_INIT
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap4.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 128k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+/* I2C */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER 1
+
+/* MMC */
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_SYS_MMC_SET_DEV 1
+#define CONFIG_DOS_PARTITION 1
+
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * Environment setup
+ */
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "usbtty=cdc_acm\0" \
+ "vram=16M\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "vram=${vram} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE GPT2_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310 1
+#define CONFIG_SYS_PL310_BASE 0x48242000
+#endif
+
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE 0x40304350
+#define CONFIG_SPL_MAX_SIZE (38 * 1024)
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+
+#endif /* __CONFIG_OMAP4_COMMON_H */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index e313231..67da70e 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -4,6 +4,7 @@
* Steve Sakoman <steve@sakoman.com>
*
* Configuration settings for the TI OMAP4 Panda board.
+ * See omap4_common.h for OMAP4 common part
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -24,253 +25,19 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_PANDA_H
+#define __CONFIG_PANDA_H
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP44XX 1 /* which is a 44XX */
-#define CONFIG_OMAP4430 1 /* which is in a 4430 */
#define CONFIG_PANDA 1 /* working with Panda */
-#define CONFIG_ARCH_CPU_INIT
-/* Get CPU defs */
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
-
-/* Display CPU and Board Info */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-/* Clock Defines */
-#define V_OSCK 38400000 /* Clock output from T2 */
-#define V_SCLK V_OSCK
-
-#undef CONFIG_USE_IRQ /* no support for IRQs */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-#define CONFIG_OF_LIBFDT 1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 256k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-/* Vector Base */
-#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
-
-/*
- * Hardware drivers
- */
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK 48000000
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+#include <configs/omap4_common.h>
+/* ENV related config options */
#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/* I2C */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#define CONFIG_I2C_MULTI_BUS 1
-
-/* TWL6030 */
-#define CONFIG_TWL6030_POWER 1
-
-/* MMC */
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_SYS_MMC_SET_DEV 1
-#define CONFIG_DOS_PARTITION 1
-
-/* USB */
-#define CONFIG_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH 1
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-
-/* Disabled commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
-/*
- * Environment setup
- */
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyS2,115200n8\0" \
- "usbtty=cdc_acm\0" \
- "vram=16M\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "vram=${vram} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan ${mmcdev}; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi"
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "Panda # "
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-/*
- * memtest setup
- */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
-#endif
-
-/*
- * SDRAM Memory Map
- * Even though we use two CS all the memory
- * is mapped to one contiguous block
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310 1
-#define CONFIG_SYS_PL310_BASE 0x48242000
-#endif
-
-/* Defines for SDRAM init */
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE 0x40304350
-#define CONFIG_SPL_MAX_SIZE 0x8000 /* 32 K */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80100000
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_PANDA_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 5b3110c..39d7154 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -5,6 +5,7 @@
* Steve Sakoman <steve@sakoman.com>
*
* Configuration settings for the TI SDP4430 board.
+ * See omap4_common.h for OMAP4 common part
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -25,258 +26,25 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_SDP4430_H
+#define __CONFIG_SDP4430_H
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP44XX 1 /* which is a 44XX */
-#define CONFIG_OMAP4430 1 /* which is in a 4430 */
#define CONFIG_4430SDP 1 /* working with SDP */
-#define CONFIG_ARCH_CPU_INIT
-/* Get CPU defs */
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
+#include <configs/omap4_common.h>
-/* Display CPU and Board Info */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-/* Clock Defines */
-#define V_OSCK 38400000 /* Clock output from T2 */
-#define V_SCLK V_OSCK
-
-#undef CONFIG_USE_IRQ /* no support for IRQs */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_OF_LIBFDT 1
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 128k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-/* Vector Base */
-#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
-
-/*
- * Hardware drivers
- */
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK 48000000
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-/* I2C */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#define CONFIG_I2C_MULTI_BUS 1
-
-/* TWL6030 */
-#define CONFIG_TWL6030_POWER 1
+/* Battery Charger */
#define CONFIG_CMD_BAT 1
-/* MMC */
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_SYS_MMC_SET_DEV 1
-#define CONFIG_DOS_PARTITION 1
-
-/* MMC ENV related defines */
+/* ENV related config options */
#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_ENV_OFFSET 0xE0000
-
-/* USB */
-#define CONFIG_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH 1
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_SAVEENV
-/* Disabled commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
-/*
- * Environment setup
- */
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyS2,115200n8\0" \
- "usbtty=cdc_acm\0" \
- "vram=16M\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "vram=${vram} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan ${mmcdev}; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi"
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-/*
- * memtest setup
- */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
-#endif
-
-/*
- * SDRAM Memory Map
- * Even though we use two CS all the memory
- * is mapped to one contiguous block
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310 1
-#define CONFIG_SYS_PL310_BASE 0x48242000
-#endif
-
-/* Defines for SDRAM init */
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE 0x40304350
-#define CONFIG_SPL_MAX_SIZE 0x8000 /* 32 K */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss@the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80100000
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_SDP4430_H */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/3] omap4: make SDRAM init work for ES1.0 silicon
2011-08-09 12:43 [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups Aneesh V
2011-08-09 12:43 ` [U-Boot] [PATCH 1/3] omap4: factor out common part from board config headers Aneesh V
@ 2011-08-09 12:43 ` Aneesh V
2011-08-09 12:43 ` [U-Boot] [PATCH 3/3] omap4: IO settings Aneesh V
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aneesh V @ 2011-08-09 12:43 UTC (permalink / raw)
To: u-boot
SDRAM init was not working on ES1.0 due to a programming
error. A pointer that was passed by value to a function
was set in function emif_get_device_details(), but the effect
wouldn't be seen in the calling function. The issue came
out while testing for ES1.0 because ES1.0 doesn't have any
SDRAM chips connected to CS1
Signed-off-by: Aneesh V <aneesh@ti.com>
---
arch/arm/cpu/armv7/omap4/emif.c | 47 +++++-------------------------
arch/arm/cpu/armv7/omap4/sdram_elpida.c | 24 ++++++++--------
arch/arm/include/asm/arch-omap4/emif.h | 5 +--
3 files changed, 22 insertions(+), 54 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 487ec42..8c46464 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -963,10 +963,11 @@ static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
return 1;
}
-static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
struct lpddr2_device_details *lpddr2_dev_details)
{
u32 phy;
+ u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
if (!lpddr2_dev_details)
@@ -985,40 +986,6 @@ static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
return lpddr2_dev_details;
}
-
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
-{
- u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
-
- if (running_from_sdram()) {
- /*
- * We can not do automatic discovery running from SDRAM
- * Most likely we came here by mistake. Indicate error
- * by returning NULL
- */
- cs0_device_details = NULL;
- cs1_device_details = NULL;
- } else {
- /*
- * Automatically find the device details:
- *
- * Reset the PHY after each call to get_lpddr2_details().
- * If there is nothing connected to a given chip select
- * (typically CS1) mode register reads will mess up with
- * the PHY state and subsequent initialization won't work.
- * PHY reset brings back PHY to a good state.
- */
- cs0_device_details =
- get_lpddr2_details(base, CS0, cs0_device_details);
- emif_reset_phy(base);
-
- cs1_device_details =
- get_lpddr2_details(base, CS1, cs1_device_details);
- emif_reset_phy(base);
- }
-}
#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
static void do_sdram_init(u32 base)
@@ -1051,10 +1018,12 @@ static void do_sdram_init(u32 base)
* - Obtained from user otherwise
*/
struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
- emif_get_device_details(emif_nr, &cs0_dev_details,
- &cs1_dev_details);
- dev_details.cs0_device_details = &cs0_dev_details;
- dev_details.cs1_device_details = &cs1_dev_details;
+ emif_reset_phy(base);
+ dev_details.cs0_device_details = emif_get_device_details(base, CS0,
+ &cs0_dev_details);
+ dev_details.cs1_device_details = emif_get_device_details(base, CS1,
+ &cs1_dev_details);
+ emif_reset_phy(base);
/* Return if no devices on this EMIF */
if (!dev_details.cs0_device_details &&
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index 7757aad..edc5326 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -141,24 +141,24 @@ static const struct lpddr2_device_details elpida_2G_S4_details = {
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
-static void emif_get_device_details_sdp(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
+struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details)
{
u32 omap_rev = omap_revision();
/* EMIF1 & EMIF2 have identical configuration */
- *cs0_device_details = elpida_2G_S4_details;
-
- if (omap_rev == OMAP4430_ES1_0)
- cs1_device_details = NULL;
- else
- *cs1_device_details = elpida_2G_S4_details;
+ if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
+ /* Nothing connected on CS1 for ES1.0 */
+ return NULL;
+ } else {
+ /* In all other cases Elpida 2G device */
+ *lpddr2_dev_details = elpida_2G_S4_details;
+ return lpddr2_dev_details;
+ }
}
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details)
__attribute__((weak, alias("emif_get_device_details_sdp")));
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 37ad1fd..6845c65 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -1029,9 +1029,8 @@ struct emif_regs {
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
#else
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details);
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details);
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 3/3] omap4: IO settings
2011-08-09 12:43 [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups Aneesh V
2011-08-09 12:43 ` [U-Boot] [PATCH 1/3] omap4: factor out common part from board config headers Aneesh V
2011-08-09 12:43 ` [U-Boot] [PATCH 2/3] omap4: make SDRAM init work for ES1.0 silicon Aneesh V
@ 2011-08-09 12:43 ` Aneesh V
2011-09-06 15:25 ` [U-Boot] [PATCH v2 1/3] omap4: factor out common part from board config headers Aneesh V
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aneesh V @ 2011-08-09 12:43 UTC (permalink / raw)
To: u-boot
Tuning some IO settings for better performance and power.
And consolidate all such IO settings at one place.
Signed-off-by: Aneesh V <aneesh@ti.com>
---
arch/arm/cpu/armv7/omap4/board.c | 57 +++++++++++++++++++++++++++++++
arch/arm/cpu/armv7/omap4/emif.c | 25 -------------
arch/arm/include/asm/arch-omap4/emif.h | 14 +------
arch/arm/include/asm/arch-omap4/omap4.h | 35 ++++++++++++++++++-
4 files changed, 92 insertions(+), 39 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 5943d61..bad56e3 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -70,6 +70,62 @@ u32 omap_boot_mode(void)
{
return omap4_boot_mode;
}
+
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+static void do_io_settings(void)
+{
+ u32 lpddr2io;
+ struct control_lpddr2io_regs *lpddr2io_regs =
+ (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
+ struct omap4_sys_ctrl_regs *const ctrl =
+ (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+
+ u32 omap4_rev = omap_revision();
+
+ if (omap4_rev == OMAP4430_ES1_0)
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+ else if (omap4_rev == OMAP4430_ES2_0)
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+ else
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
+
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+ /* No pull for GR10 as per hw team's recommendation */
+ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+ &lpddr2io_regs->control_lpddr2io1_2);
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+ /* No pull for GR10 as per hw team's recommendation */
+ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+ &lpddr2io_regs->control_lpddr2io2_2);
+
+ /*
+ * Some of these settings (TRIM values) come from eFuse and are
+ * in turn programmed in the eFuse at manufacturing time after
+ * calibration of the device. Do the software over-ride only if
+ * the device is not correctly trimmed
+ */
+ if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_iva_voltage_ctrl);
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_mpu_voltage_ctrl);
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_core_voltage_ctrl);
+ }
+
+ if (!readl(&ctrl->control_efuse_1))
+ writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
+
+ if (!readl(&ctrl->control_efuse_2))
+ writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
+}
#endif
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
@@ -197,6 +253,7 @@ void s_init(void)
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
preloader_console_init();
+ do_io_settings();
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 8c46464..988b205 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -1063,30 +1063,6 @@ static void do_sdram_init(u32 base)
debug("<<do_sdram_init() %x\n", base);
}
-void sdram_init_pads(void)
-{
- u32 lpddr2io;
- struct control_lpddr2io_regs *lpddr2io_regs =
- (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
- u32 omap4_rev = omap_revision();
-
- if (omap4_rev == OMAP4430_ES1_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
- else if (omap4_rev == OMAP4430_ES2_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
- else
- return; /* Post ES2.1 reset values will work */
-
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
-
- writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
-}
-
static void emif_post_init_config(u32 base)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -1243,7 +1219,6 @@ void sdram_init(void)
debug("in_sdram = %d\n", in_sdram);
if (!in_sdram) {
- sdram_init_pads();
bypass_dpll(&prcm->cm_clkmode_dpll_core);
}
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 6845c65..f24e944 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -593,17 +593,6 @@ struct dmm_lisa_map_regs {
u32 dmm_lisa_map_3;
};
-struct control_lpddr2io_regs {
- u32 control_lpddr2io1_0;
- u32 control_lpddr2io1_1;
- u32 control_lpddr2io1_2;
- u32 control_lpddr2io1_3;
- u32 control_lpddr2io2_0;
- u32 control_lpddr2io2_1;
- u32 control_lpddr2io2_2;
- u32 control_lpddr2io2_3;
-};
-
#define CS0 0
#define CS1 1
/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
@@ -826,7 +815,8 @@ struct control_lpddr2io_regs {
/* LPDDR2 IO regs */
#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
-
+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
+#define LPDDR2IO_GR10_WD_MASK (3 << 17)
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index 9aad0e6..8e499f4 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -54,8 +54,6 @@
/* LPDDR2 IO regs */
#define LPDDR2_IO_REGS_BASE 0x4A100638
-#define CONTROL_EFUSE_2 0x4A100704
-
/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE 0x4A002204
@@ -84,6 +82,9 @@
/* GPMC */
#define OMAP44XX_GPMC_BASE 0x50000000
+/* SYSTEM CONTROL MODULE */
+#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
+
/*
* Hardware Register Details
*/
@@ -108,6 +109,12 @@
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
+/* Control Module */
+#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
+#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
+#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
+#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
+
#ifndef __ASSEMBLY__
struct s32ktimer {
@@ -115,6 +122,30 @@ struct s32ktimer {
unsigned int s32k_cr; /* 0x10 */
};
+struct omap4_sys_ctrl_regs {
+ unsigned int pad1[129];
+ unsigned int control_id_code; /* 0x4A002204 */
+ unsigned int pad11[22];
+ unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
+ unsigned int pad2[47];
+ unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
+ unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
+ unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
+ unsigned int pad3[260341];
+ unsigned int control_efuse_1; /* 0x4A100700 */
+ unsigned int control_efuse_2; /* 0x4A100704 */
+};
+
+struct control_lpddr2io_regs {
+ unsigned int control_lpddr2io1_0;
+ unsigned int control_lpddr2io1_1;
+ unsigned int control_lpddr2io1_2;
+ unsigned int control_lpddr2io1_3;
+ unsigned int control_lpddr2io2_0;
+ unsigned int control_lpddr2io2_1;
+ unsigned int control_lpddr2io2_2;
+ unsigned int control_lpddr2io2_3;
+};
#endif /* __ASSEMBLY__ */
/*
--
1.7.0.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 1/3] omap4: factor out common part from board config headers
2011-08-09 12:43 [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups Aneesh V
` (2 preceding siblings ...)
2011-08-09 12:43 ` [U-Boot] [PATCH 3/3] omap4: IO settings Aneesh V
@ 2011-09-06 15:25 ` Aneesh V
2011-09-06 15:25 ` [U-Boot] [PATCH v2 2/3] omap4: make SDRAM init work for ES1.0 silicon Aneesh V
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aneesh V @ 2011-09-06 15:25 UTC (permalink / raw)
To: u-boot
Factor out common parts from omap4_sdp4430.h and omap4_panda.h
into a new file omap4_common.h
Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Rebased on latest HEAD of u-boot-ti master
---
include/configs/omap4_common.h | 275 +++++++++++++++++++++++++++++++++++++++
include/configs/omap4_panda.h | 244 +---------------------------------
include/configs/omap4_sdp4430.h | 245 +---------------------------------
3 files changed, 288 insertions(+), 476 deletions(-)
create mode 100644 include/configs/omap4_common.h
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
new file mode 100644
index 0000000..3d641fa
--- /dev/null
+++ b/include/configs/omap4_common.h
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * TI OMAP4 common configuration settings
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_OMAP4_COMMON_H
+#define __CONFIG_OMAP4_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP44XX 1 /* which is a 44XX */
+#define CONFIG_OMAP4430 1 /* which is in a 4430 */
+#define CONFIG_ARCH_CPU_INIT
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap4.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 128k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+/* I2C */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER 1
+
+/* MMC */
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_SYS_MMC_SET_DEV 1
+#define CONFIG_DOS_PARTITION 1
+
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * Environment setup
+ */
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "usbtty=cdc_acm\0" \
+ "vram=16M\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "vram=${vram} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE GPT2_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310 1
+#define CONFIG_SYS_PL310_BASE 0x48242000
+#endif
+
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE 0x40304350
+#define CONFIG_SPL_MAX_SIZE (38 * 1024)
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+
+#endif /* __CONFIG_OMAP4_COMMON_H */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 6faf0e2..4fcd725 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -4,6 +4,7 @@
* Steve Sakoman <steve@sakoman.com>
*
* Configuration settings for the TI OMAP4 Panda board.
+ * See omap4_common.h for OMAP4 common part
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -24,253 +25,20 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_PANDA_H
+#define __CONFIG_PANDA_H
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP44XX 1 /* which is a 44XX */
-#define CONFIG_OMAP4430 1 /* which is in a 4430 */
#define CONFIG_PANDA 1 /* working with Panda */
-#define CONFIG_ARCH_CPU_INIT
-/* Get CPU defs */
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
-
-/* Display CPU and Board Info */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-/* Clock Defines */
-#define V_OSCK 38400000 /* Clock output from T2 */
-#define V_SCLK V_OSCK
-
-#undef CONFIG_USE_IRQ /* no support for IRQs */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-#define CONFIG_OF_LIBFDT 1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 256k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-/* Vector Base */
-#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
-
-/*
- * Hardware drivers
- */
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK 48000000
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+#include <configs/omap4_common.h>
+/* ENV related config options */
#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/* I2C */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#define CONFIG_I2C_MULTI_BUS 1
-
-/* TWL6030 */
-#define CONFIG_TWL6030_POWER 1
-
-/* MMC */
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_SYS_MMC_SET_DEV 1
-#define CONFIG_DOS_PARTITION 1
-
-/* USB */
-#define CONFIG_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH 1
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-
-/* Disabled commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
-/*
- * Environment setup
- */
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyS2,115200n8\0" \
- "usbtty=cdc_acm\0" \
- "vram=16M\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "vram=${vram} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan ${mmcdev}; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi"
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "Panda # "
-#define CONFIG_SYS_CBSIZE 512
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-/*
- * memtest setup
- */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
-#endif
-
-/*
- * SDRAM Memory Map
- * Even though we use two CS all the memory
- * is mapped to one contiguous block
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310 1
-#define CONFIG_SYS_PL310_BASE 0x48242000
-#endif
-/* Defines for SDRAM init */
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE 0x40304350
-#define CONFIG_SPL_MAX_SIZE (38 * 1024)
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80100000
+#endif /* __CONFIG_PANDA_H */
-#endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index ba6f49d..0a9b707 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -5,6 +5,7 @@
* Steve Sakoman <steve@sakoman.com>
*
* Configuration settings for the TI SDP4430 board.
+ * See omap4_common.h for OMAP4 common part
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -25,258 +26,26 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_SDP4430_H
+#define __CONFIG_SDP4430_H
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP44XX 1 /* which is a 44XX */
-#define CONFIG_OMAP4430 1 /* which is in a 4430 */
#define CONFIG_4430SDP 1 /* working with SDP */
-#define CONFIG_ARCH_CPU_INIT
-/* Get CPU defs */
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
+#include <configs/omap4_common.h>
-/* Display CPU and Board Info */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-/* Clock Defines */
-#define V_OSCK 38400000 /* Clock output from T2 */
-#define V_SCLK V_OSCK
-
-#undef CONFIG_USE_IRQ /* no support for IRQs */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_OF_LIBFDT 1
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 128k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-/* Vector Base */
-#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
-
-/*
- * Hardware drivers
- */
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK 48000000
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-/* I2C */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#define CONFIG_I2C_MULTI_BUS 1
-
-/* TWL6030 */
-#define CONFIG_TWL6030_POWER 1
+/* Battery Charger */
#define CONFIG_CMD_BAT 1
-/* MMC */
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_SYS_MMC_SET_DEV 1
-#define CONFIG_DOS_PARTITION 1
-
-/* MMC ENV related defines */
+/* ENV related config options */
#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_ENV_OFFSET 0xE0000
-
-/* USB */
-#define CONFIG_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH 1
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_SAVEENV
-/* Disabled commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
-/*
- * Environment setup
- */
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyS2,115200n8\0" \
- "usbtty=cdc_acm\0" \
- "vram=16M\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "vram=${vram} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan ${mmcdev}; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi"
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
-#define CONFIG_SYS_CBSIZE 512
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-/*
- * memtest setup
- */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
-#endif
-
-/*
- * SDRAM Memory Map
- * Even though we use two CS all the memory
- * is mapped to one contiguous block
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310 1
-#define CONFIG_SYS_PL310_BASE 0x48242000
-#endif
-
-/* Defines for SDRAM init */
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE 0x40304350
-#define CONFIG_SPL_MAX_SIZE (38 * 1024)
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss@the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80100000
+#endif /* __CONFIG_SDP4430_H */
-#endif /* __CONFIG_H */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 2/3] omap4: make SDRAM init work for ES1.0 silicon
2011-08-09 12:43 [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups Aneesh V
` (3 preceding siblings ...)
2011-09-06 15:25 ` [U-Boot] [PATCH v2 1/3] omap4: factor out common part from board config headers Aneesh V
@ 2011-09-06 15:25 ` Aneesh V
2011-09-06 15:25 ` [U-Boot] [PATCH v2 3/3] omap4: IO settings Aneesh V
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aneesh V @ 2011-09-06 15:25 UTC (permalink / raw)
To: u-boot
SDRAM init was not working on ES1.0 due to a programming
error. A pointer that was passed by value to a function
was set in function emif_get_device_details(), but the effect
wouldn't be seen in the calling function. The issue came
out while testing for ES1.0 because ES1.0 doesn't have any
SDRAM chips connected to CS1
Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Rebased on latest HEAD of u-boot-ti master
---
arch/arm/cpu/armv7/omap4/emif.c | 47 +++++-------------------------
arch/arm/cpu/armv7/omap4/sdram_elpida.c | 24 ++++++++--------
arch/arm/include/asm/arch-omap4/emif.h | 5 +--
3 files changed, 22 insertions(+), 54 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 487ec42..8c46464 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -963,10 +963,11 @@ static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
return 1;
}
-static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
struct lpddr2_device_details *lpddr2_dev_details)
{
u32 phy;
+ u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
if (!lpddr2_dev_details)
@@ -985,40 +986,6 @@ static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
return lpddr2_dev_details;
}
-
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
-{
- u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
-
- if (running_from_sdram()) {
- /*
- * We can not do automatic discovery running from SDRAM
- * Most likely we came here by mistake. Indicate error
- * by returning NULL
- */
- cs0_device_details = NULL;
- cs1_device_details = NULL;
- } else {
- /*
- * Automatically find the device details:
- *
- * Reset the PHY after each call to get_lpddr2_details().
- * If there is nothing connected to a given chip select
- * (typically CS1) mode register reads will mess up with
- * the PHY state and subsequent initialization won't work.
- * PHY reset brings back PHY to a good state.
- */
- cs0_device_details =
- get_lpddr2_details(base, CS0, cs0_device_details);
- emif_reset_phy(base);
-
- cs1_device_details =
- get_lpddr2_details(base, CS1, cs1_device_details);
- emif_reset_phy(base);
- }
-}
#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
static void do_sdram_init(u32 base)
@@ -1051,10 +1018,12 @@ static void do_sdram_init(u32 base)
* - Obtained from user otherwise
*/
struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
- emif_get_device_details(emif_nr, &cs0_dev_details,
- &cs1_dev_details);
- dev_details.cs0_device_details = &cs0_dev_details;
- dev_details.cs1_device_details = &cs1_dev_details;
+ emif_reset_phy(base);
+ dev_details.cs0_device_details = emif_get_device_details(base, CS0,
+ &cs0_dev_details);
+ dev_details.cs1_device_details = emif_get_device_details(base, CS1,
+ &cs1_dev_details);
+ emif_reset_phy(base);
/* Return if no devices on this EMIF */
if (!dev_details.cs0_device_details &&
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index 7757aad..edc5326 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -141,24 +141,24 @@ static const struct lpddr2_device_details elpida_2G_S4_details = {
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
-static void emif_get_device_details_sdp(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
+struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details)
{
u32 omap_rev = omap_revision();
/* EMIF1 & EMIF2 have identical configuration */
- *cs0_device_details = elpida_2G_S4_details;
-
- if (omap_rev == OMAP4430_ES1_0)
- cs1_device_details = NULL;
- else
- *cs1_device_details = elpida_2G_S4_details;
+ if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
+ /* Nothing connected on CS1 for ES1.0 */
+ return NULL;
+ } else {
+ /* In all other cases Elpida 2G device */
+ *lpddr2_dev_details = elpida_2G_S4_details;
+ return lpddr2_dev_details;
+ }
}
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details)
__attribute__((weak, alias("emif_get_device_details_sdp")));
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 37ad1fd..6845c65 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -1029,9 +1029,8 @@ struct emif_regs {
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
#else
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details);
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details);
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 3/3] omap4: IO settings
2011-08-09 12:43 [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups Aneesh V
` (4 preceding siblings ...)
2011-09-06 15:25 ` [U-Boot] [PATCH v2 2/3] omap4: make SDRAM init work for ES1.0 silicon Aneesh V
@ 2011-09-06 15:25 ` Aneesh V
2011-09-07 8:16 ` [U-Boot] [PATCH v3 1/3] omap4: factor out common part from board config headers Aneesh V
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aneesh V @ 2011-09-06 15:25 UTC (permalink / raw)
To: u-boot
Tuning some IO settings for better performance and power.
And consolidate all such IO settings at one place.
Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Add one more IO setting(in CONTROL_LPDDR2IOi_3) that was
missing in the V1
* Move all LPDDR2IO regs related defines to omap4.h from
emif.h
* Rebased on latest HEAD of u-boot-ti master
---
arch/arm/cpu/armv7/omap4/board.c | 61 +++++++++++++++++++++++++++++++
arch/arm/cpu/armv7/omap4/emif.c | 25 -------------
arch/arm/include/asm/arch-omap4/emif.h | 18 ---------
arch/arm/include/asm/arch-omap4/omap4.h | 46 ++++++++++++++++++++++-
4 files changed, 105 insertions(+), 45 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 69a0ce5..13ad654 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -70,6 +70,66 @@ u32 omap_boot_mode(void)
{
return omap4_boot_mode;
}
+
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+static void do_io_settings(void)
+{
+ u32 lpddr2io;
+ struct control_lpddr2io_regs *lpddr2io_regs =
+ (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
+ struct omap4_sys_ctrl_regs *const ctrl =
+ (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+
+ u32 omap4_rev = omap_revision();
+
+ if (omap4_rev == OMAP4430_ES1_0)
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+ else if (omap4_rev == OMAP4430_ES2_0)
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+ else
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
+
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+ /* No pull for GR10 as per hw team's recommendation */
+ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+ &lpddr2io_regs->control_lpddr2io1_2);
+ clrbits_le32(&lpddr2io_regs->control_lpddr2io1_3,
+ LPDDR2_INT_VREF_EN_CA_MASK | LPDDR2_INT_VREF_EN_DQ_MASK);
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+ /* No pull for GR10 as per hw team's recommendation */
+ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+ &lpddr2io_regs->control_lpddr2io2_2);
+ clrbits_le32(&lpddr2io_regs->control_lpddr2io2_3,
+ LPDDR2_INT_VREF_EN_CA_MASK | LPDDR2_INT_VREF_EN_DQ_MASK);
+
+ /*
+ * Some of these settings (TRIM values) come from eFuse and are
+ * in turn programmed in the eFuse at manufacturing time after
+ * calibration of the device. Do the software over-ride only if
+ * the device is not correctly trimmed
+ */
+ if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_iva_voltage_ctrl);
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_mpu_voltage_ctrl);
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_core_voltage_ctrl);
+ }
+
+ if (!readl(&ctrl->control_efuse_1))
+ writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
+
+ if (!readl(&ctrl->control_efuse_2))
+ writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
+}
#endif
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
@@ -197,6 +257,7 @@ void s_init(void)
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
preloader_console_init();
+ do_io_settings();
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 8c46464..988b205 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -1063,30 +1063,6 @@ static void do_sdram_init(u32 base)
debug("<<do_sdram_init() %x\n", base);
}
-void sdram_init_pads(void)
-{
- u32 lpddr2io;
- struct control_lpddr2io_regs *lpddr2io_regs =
- (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
- u32 omap4_rev = omap_revision();
-
- if (omap4_rev == OMAP4430_ES1_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
- else if (omap4_rev == OMAP4430_ES2_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
- else
- return; /* Post ES2.1 reset values will work */
-
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
-
- writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
-}
-
static void emif_post_init_config(u32 base)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -1243,7 +1219,6 @@ void sdram_init(void)
debug("in_sdram = %d\n", in_sdram);
if (!in_sdram) {
- sdram_init_pads();
bypass_dpll(&prcm->cm_clkmode_dpll_core);
}
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 6845c65..3a549ba 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -593,17 +593,6 @@ struct dmm_lisa_map_regs {
u32 dmm_lisa_map_3;
};
-struct control_lpddr2io_regs {
- u32 control_lpddr2io1_0;
- u32 control_lpddr2io1_1;
- u32 control_lpddr2io1_2;
- u32 control_lpddr2io1_3;
- u32 control_lpddr2io2_0;
- u32 control_lpddr2io2_1;
- u32 control_lpddr2io2_2;
- u32 control_lpddr2io2_3;
-};
-
#define CS0 0
#define CS1 1
/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
@@ -823,13 +812,6 @@ struct control_lpddr2io_regs {
/* MR16 value: refresh full array(no partial array self refresh) */
#define MR16_REF_FULL_ARRAY 0
-/* LPDDR2 IO regs */
-#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
-#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
-
-/* CONTROL_EFUSE_2 */
-#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
-
/*
* Maximum number of entries we keep in our array of timing tables
* We need not keep all the speed bins supported by the device
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index 7ff46d7..6245017 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -54,8 +54,6 @@
/* LPDDR2 IO regs */
#define LPDDR2_IO_REGS_BASE 0x4A100638
-#define CONTROL_EFUSE_2 0x4A100704
-
/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE 0x4A002204
@@ -84,6 +82,9 @@
/* GPMC */
#define OMAP44XX_GPMC_BASE 0x50000000
+/* SYSTEM CONTROL MODULE */
+#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
+
/*
* Hardware Register Details
*/
@@ -108,6 +109,23 @@
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
+/* Control Module */
+#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
+#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
+#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
+#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
+#define LPDDR2IO_GR10_WD_MASK (3 << 17)
+#define LPDDR2_INT_VREF_EN_CA_MASK 0x8
+#define LPDDR2_INT_VREF_EN_DQ_MASK 0x4
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+
#ifndef __ASSEMBLY__
struct s32ktimer {
@@ -115,6 +133,30 @@ struct s32ktimer {
unsigned int s32k_cr; /* 0x10 */
};
+struct omap4_sys_ctrl_regs {
+ unsigned int pad1[129];
+ unsigned int control_id_code; /* 0x4A002204 */
+ unsigned int pad11[22];
+ unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
+ unsigned int pad2[47];
+ unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
+ unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
+ unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
+ unsigned int pad3[260341];
+ unsigned int control_efuse_1; /* 0x4A100700 */
+ unsigned int control_efuse_2; /* 0x4A100704 */
+};
+
+struct control_lpddr2io_regs {
+ unsigned int control_lpddr2io1_0;
+ unsigned int control_lpddr2io1_1;
+ unsigned int control_lpddr2io1_2;
+ unsigned int control_lpddr2io1_3;
+ unsigned int control_lpddr2io2_0;
+ unsigned int control_lpddr2io2_1;
+ unsigned int control_lpddr2io2_2;
+ unsigned int control_lpddr2io2_3;
+};
#endif /* __ASSEMBLY__ */
/*
--
1.7.0.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v3 1/3] omap4: factor out common part from board config headers
2011-08-09 12:43 [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups Aneesh V
` (5 preceding siblings ...)
2011-09-06 15:25 ` [U-Boot] [PATCH v2 3/3] omap4: IO settings Aneesh V
@ 2011-09-07 8:16 ` Aneesh V
2011-09-07 8:16 ` [U-Boot] [PATCH v3 2/3] omap4: make SDRAM init work for ES1.0 silicon Aneesh V
2011-09-07 8:16 ` [U-Boot] [PATCH v3 3/3] omap4: IO settings Aneesh V
8 siblings, 0 replies; 10+ messages in thread
From: Aneesh V @ 2011-09-07 8:16 UTC (permalink / raw)
To: u-boot
Factor out common parts from omap4_sdp4430.h and omap4_panda.h
into a new file omap4_common.h
Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Rebased on latest HEAD of u-boot-ti master
V3:
* Fixed checkpatch error
---
include/configs/omap4_common.h | 275 +++++++++++++++++++++++++++++++++++++++
include/configs/omap4_panda.h | 244 +---------------------------------
include/configs/omap4_sdp4430.h | 245 +---------------------------------
3 files changed, 288 insertions(+), 476 deletions(-)
create mode 100644 include/configs/omap4_common.h
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
new file mode 100644
index 0000000..d8ac8c0
--- /dev/null
+++ b/include/configs/omap4_common.h
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * TI OMAP4 common configuration settings
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_OMAP4_COMMON_H
+#define __CONFIG_OMAP4_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP44XX 1 /* which is a 44XX */
+#define CONFIG_OMAP4430 1 /* which is in a 4430 */
+#define CONFIG_ARCH_CPU_INIT
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap4.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 128k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+/* I2C */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER 1
+
+/* MMC */
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_SYS_MMC_SET_DEV 1
+#define CONFIG_DOS_PARTITION 1
+
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * Environment setup
+ */
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "usbtty=cdc_acm\0" \
+ "vram=16M\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "vram=${vram} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE GPT2_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310 1
+#define CONFIG_SYS_PL310_BASE 0x48242000
+#endif
+
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE 0x40304350
+#define CONFIG_SPL_MAX_SIZE (38 * 1024)
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+
+#endif /* __CONFIG_OMAP4_COMMON_H */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 6faf0e2..4fcd725 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -4,6 +4,7 @@
* Steve Sakoman <steve@sakoman.com>
*
* Configuration settings for the TI OMAP4 Panda board.
+ * See omap4_common.h for OMAP4 common part
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -24,253 +25,20 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_PANDA_H
+#define __CONFIG_PANDA_H
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP44XX 1 /* which is a 44XX */
-#define CONFIG_OMAP4430 1 /* which is in a 4430 */
#define CONFIG_PANDA 1 /* working with Panda */
-#define CONFIG_ARCH_CPU_INIT
-/* Get CPU defs */
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
-
-/* Display CPU and Board Info */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-/* Clock Defines */
-#define V_OSCK 38400000 /* Clock output from T2 */
-#define V_SCLK V_OSCK
-
-#undef CONFIG_USE_IRQ /* no support for IRQs */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-#define CONFIG_OF_LIBFDT 1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 256k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-/* Vector Base */
-#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
-
-/*
- * Hardware drivers
- */
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK 48000000
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+#include <configs/omap4_common.h>
+/* ENV related config options */
#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/* I2C */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#define CONFIG_I2C_MULTI_BUS 1
-
-/* TWL6030 */
-#define CONFIG_TWL6030_POWER 1
-
-/* MMC */
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_SYS_MMC_SET_DEV 1
-#define CONFIG_DOS_PARTITION 1
-
-/* USB */
-#define CONFIG_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH 1
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-
-/* Disabled commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
-/*
- * Environment setup
- */
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyS2,115200n8\0" \
- "usbtty=cdc_acm\0" \
- "vram=16M\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "vram=${vram} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan ${mmcdev}; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi"
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "Panda # "
-#define CONFIG_SYS_CBSIZE 512
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-/*
- * memtest setup
- */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
-#endif
-
-/*
- * SDRAM Memory Map
- * Even though we use two CS all the memory
- * is mapped to one contiguous block
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310 1
-#define CONFIG_SYS_PL310_BASE 0x48242000
-#endif
-/* Defines for SDRAM init */
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE 0x40304350
-#define CONFIG_SPL_MAX_SIZE (38 * 1024)
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80100000
+#endif /* __CONFIG_PANDA_H */
-#endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index ba6f49d..0a9b707 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -5,6 +5,7 @@
* Steve Sakoman <steve@sakoman.com>
*
* Configuration settings for the TI SDP4430 board.
+ * See omap4_common.h for OMAP4 common part
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -25,258 +26,26 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_SDP4430_H
+#define __CONFIG_SDP4430_H
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP44XX 1 /* which is a 44XX */
-#define CONFIG_OMAP4430 1 /* which is in a 4430 */
#define CONFIG_4430SDP 1 /* working with SDP */
-#define CONFIG_ARCH_CPU_INIT
-/* Get CPU defs */
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
+#include <configs/omap4_common.h>
-/* Display CPU and Board Info */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-/* Clock Defines */
-#define V_OSCK 38400000 /* Clock output from T2 */
-#define V_SCLK V_OSCK
-
-#undef CONFIG_USE_IRQ /* no support for IRQs */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_OF_LIBFDT 1
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 128k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-/* Vector Base */
-#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
-
-/*
- * Hardware drivers
- */
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK 48000000
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-/* I2C */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#define CONFIG_I2C_MULTI_BUS 1
-
-/* TWL6030 */
-#define CONFIG_TWL6030_POWER 1
+/* Battery Charger */
#define CONFIG_CMD_BAT 1
-/* MMC */
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_SYS_MMC_SET_DEV 1
-#define CONFIG_DOS_PARTITION 1
-
-/* MMC ENV related defines */
+/* ENV related config options */
#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_ENV_OFFSET 0xE0000
-
-/* USB */
-#define CONFIG_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH 1
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_SAVEENV
-/* Disabled commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
-/*
- * Environment setup
- */
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyS2,115200n8\0" \
- "usbtty=cdc_acm\0" \
- "vram=16M\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "vram=${vram} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan ${mmcdev}; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi"
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
-#define CONFIG_SYS_CBSIZE 512
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-/*
- * memtest setup
- */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
-#endif
-
-/*
- * SDRAM Memory Map
- * Even though we use two CS all the memory
- * is mapped to one contiguous block
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310 1
-#define CONFIG_SYS_PL310_BASE 0x48242000
-#endif
-
-/* Defines for SDRAM init */
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE 0x40304350
-#define CONFIG_SPL_MAX_SIZE (38 * 1024)
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss@the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80100000
+#endif /* __CONFIG_SDP4430_H */
-#endif /* __CONFIG_H */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v3 2/3] omap4: make SDRAM init work for ES1.0 silicon
2011-08-09 12:43 [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups Aneesh V
` (6 preceding siblings ...)
2011-09-07 8:16 ` [U-Boot] [PATCH v3 1/3] omap4: factor out common part from board config headers Aneesh V
@ 2011-09-07 8:16 ` Aneesh V
2011-09-07 8:16 ` [U-Boot] [PATCH v3 3/3] omap4: IO settings Aneesh V
8 siblings, 0 replies; 10+ messages in thread
From: Aneesh V @ 2011-09-07 8:16 UTC (permalink / raw)
To: u-boot
SDRAM init was not working on ES1.0 due to a programming
error. A pointer that was passed by value to a function
was set in function emif_get_device_details(), but the effect
wouldn't be seen in the calling function. The issue came
out while testing for ES1.0 because ES1.0 doesn't have any
SDRAM chips connected to CS1
Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Rebased on latest HEAD of u-boot-ti master
---
arch/arm/cpu/armv7/omap4/emif.c | 47 +++++-------------------------
arch/arm/cpu/armv7/omap4/sdram_elpida.c | 24 ++++++++--------
arch/arm/include/asm/arch-omap4/emif.h | 5 +--
3 files changed, 22 insertions(+), 54 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 487ec42..8c46464 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -963,10 +963,11 @@ static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
return 1;
}
-static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
struct lpddr2_device_details *lpddr2_dev_details)
{
u32 phy;
+ u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
if (!lpddr2_dev_details)
@@ -985,40 +986,6 @@ static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
return lpddr2_dev_details;
}
-
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
-{
- u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
-
- if (running_from_sdram()) {
- /*
- * We can not do automatic discovery running from SDRAM
- * Most likely we came here by mistake. Indicate error
- * by returning NULL
- */
- cs0_device_details = NULL;
- cs1_device_details = NULL;
- } else {
- /*
- * Automatically find the device details:
- *
- * Reset the PHY after each call to get_lpddr2_details().
- * If there is nothing connected to a given chip select
- * (typically CS1) mode register reads will mess up with
- * the PHY state and subsequent initialization won't work.
- * PHY reset brings back PHY to a good state.
- */
- cs0_device_details =
- get_lpddr2_details(base, CS0, cs0_device_details);
- emif_reset_phy(base);
-
- cs1_device_details =
- get_lpddr2_details(base, CS1, cs1_device_details);
- emif_reset_phy(base);
- }
-}
#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
static void do_sdram_init(u32 base)
@@ -1051,10 +1018,12 @@ static void do_sdram_init(u32 base)
* - Obtained from user otherwise
*/
struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
- emif_get_device_details(emif_nr, &cs0_dev_details,
- &cs1_dev_details);
- dev_details.cs0_device_details = &cs0_dev_details;
- dev_details.cs1_device_details = &cs1_dev_details;
+ emif_reset_phy(base);
+ dev_details.cs0_device_details = emif_get_device_details(base, CS0,
+ &cs0_dev_details);
+ dev_details.cs1_device_details = emif_get_device_details(base, CS1,
+ &cs1_dev_details);
+ emif_reset_phy(base);
/* Return if no devices on this EMIF */
if (!dev_details.cs0_device_details &&
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index 7757aad..edc5326 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -141,24 +141,24 @@ static const struct lpddr2_device_details elpida_2G_S4_details = {
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
-static void emif_get_device_details_sdp(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
+struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details)
{
u32 omap_rev = omap_revision();
/* EMIF1 & EMIF2 have identical configuration */
- *cs0_device_details = elpida_2G_S4_details;
-
- if (omap_rev == OMAP4430_ES1_0)
- cs1_device_details = NULL;
- else
- *cs1_device_details = elpida_2G_S4_details;
+ if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
+ /* Nothing connected on CS1 for ES1.0 */
+ return NULL;
+ } else {
+ /* In all other cases Elpida 2G device */
+ *lpddr2_dev_details = elpida_2G_S4_details;
+ return lpddr2_dev_details;
+ }
}
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details)
__attribute__((weak, alias("emif_get_device_details_sdp")));
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 37ad1fd..6845c65 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -1029,9 +1029,8 @@ struct emif_regs {
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
#else
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details);
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details);
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v3 3/3] omap4: IO settings
2011-08-09 12:43 [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups Aneesh V
` (7 preceding siblings ...)
2011-09-07 8:16 ` [U-Boot] [PATCH v3 2/3] omap4: make SDRAM init work for ES1.0 silicon Aneesh V
@ 2011-09-07 8:16 ` Aneesh V
8 siblings, 0 replies; 10+ messages in thread
From: Aneesh V @ 2011-09-07 8:16 UTC (permalink / raw)
To: u-boot
Tuning some IO settings for better performance and power.
And consolidate all such IO settings at one place.
Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Add one more IO setting(in CONTROL_LPDDR2IOi_3) that was
missing in the V1
* Move all LPDDR2IO regs related defines to omap4.h from
emif.h
* Rebased on latest HEAD of u-boot-ti master
V3:
* A more optimized value for LPDDR2IO_3 registers as per
recommendation from hw design team
---
arch/arm/cpu/armv7/omap4/board.c | 62 +++++++++++++++++++++++++++++++
arch/arm/cpu/armv7/omap4/emif.c | 25 ------------
arch/arm/include/asm/arch-omap4/emif.h | 18 ---------
arch/arm/include/asm/arch-omap4/omap4.h | 45 +++++++++++++++++++++-
4 files changed, 105 insertions(+), 45 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 69a0ce5..309b244 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -70,6 +70,67 @@ u32 omap_boot_mode(void)
{
return omap4_boot_mode;
}
+
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+static void do_io_settings(void)
+{
+ u32 lpddr2io;
+ struct control_lpddr2io_regs *lpddr2io_regs =
+ (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
+ struct omap4_sys_ctrl_regs *const ctrl =
+ (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+
+ u32 omap4_rev = omap_revision();
+
+ if (omap4_rev == OMAP4430_ES1_0)
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+ else if (omap4_rev == OMAP4430_ES2_0)
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+ else
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
+
+ /* EMIF1 */
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+ /* No pull for GR10 as per hw team's recommendation */
+ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+ &lpddr2io_regs->control_lpddr2io1_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
+
+ /* EMIF2 */
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+ /* No pull for GR10 as per hw team's recommendation */
+ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+ &lpddr2io_regs->control_lpddr2io2_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
+
+ /*
+ * Some of these settings (TRIM values) come from eFuse and are
+ * in turn programmed in the eFuse at manufacturing time after
+ * calibration of the device. Do the software over-ride only if
+ * the device is not correctly trimmed
+ */
+ if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_iva_voltage_ctrl);
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_mpu_voltage_ctrl);
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_core_voltage_ctrl);
+ }
+
+ if (!readl(&ctrl->control_efuse_1))
+ writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
+
+ if (!readl(&ctrl->control_efuse_2))
+ writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
+}
#endif
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
@@ -197,6 +258,7 @@ void s_init(void)
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
preloader_console_init();
+ do_io_settings();
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 8c46464..988b205 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -1063,30 +1063,6 @@ static void do_sdram_init(u32 base)
debug("<<do_sdram_init() %x\n", base);
}
-void sdram_init_pads(void)
-{
- u32 lpddr2io;
- struct control_lpddr2io_regs *lpddr2io_regs =
- (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
- u32 omap4_rev = omap_revision();
-
- if (omap4_rev == OMAP4430_ES1_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
- else if (omap4_rev == OMAP4430_ES2_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
- else
- return; /* Post ES2.1 reset values will work */
-
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
-
- writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
-}
-
static void emif_post_init_config(u32 base)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -1243,7 +1219,6 @@ void sdram_init(void)
debug("in_sdram = %d\n", in_sdram);
if (!in_sdram) {
- sdram_init_pads();
bypass_dpll(&prcm->cm_clkmode_dpll_core);
}
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 6845c65..3a549ba 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -593,17 +593,6 @@ struct dmm_lisa_map_regs {
u32 dmm_lisa_map_3;
};
-struct control_lpddr2io_regs {
- u32 control_lpddr2io1_0;
- u32 control_lpddr2io1_1;
- u32 control_lpddr2io1_2;
- u32 control_lpddr2io1_3;
- u32 control_lpddr2io2_0;
- u32 control_lpddr2io2_1;
- u32 control_lpddr2io2_2;
- u32 control_lpddr2io2_3;
-};
-
#define CS0 0
#define CS1 1
/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
@@ -823,13 +812,6 @@ struct control_lpddr2io_regs {
/* MR16 value: refresh full array(no partial array self refresh) */
#define MR16_REF_FULL_ARRAY 0
-/* LPDDR2 IO regs */
-#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
-#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
-
-/* CONTROL_EFUSE_2 */
-#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
-
/*
* Maximum number of entries we keep in our array of timing tables
* We need not keep all the speed bins supported by the device
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index 7ff46d7..a6e1e42 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -54,8 +54,6 @@
/* LPDDR2 IO regs */
#define LPDDR2_IO_REGS_BASE 0x4A100638
-#define CONTROL_EFUSE_2 0x4A100704
-
/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE 0x4A002204
@@ -84,6 +82,9 @@
/* GPMC */
#define OMAP44XX_GPMC_BASE 0x50000000
+/* SYSTEM CONTROL MODULE */
+#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
+
/*
* Hardware Register Details
*/
@@ -108,6 +109,22 @@
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
+/* Control Module */
+#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
+#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
+#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
+#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
+#define LPDDR2IO_GR10_WD_MASK (3 << 17)
+#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+
#ifndef __ASSEMBLY__
struct s32ktimer {
@@ -115,6 +132,30 @@ struct s32ktimer {
unsigned int s32k_cr; /* 0x10 */
};
+struct omap4_sys_ctrl_regs {
+ unsigned int pad1[129];
+ unsigned int control_id_code; /* 0x4A002204 */
+ unsigned int pad11[22];
+ unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
+ unsigned int pad2[47];
+ unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
+ unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
+ unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
+ unsigned int pad3[260341];
+ unsigned int control_efuse_1; /* 0x4A100700 */
+ unsigned int control_efuse_2; /* 0x4A100704 */
+};
+
+struct control_lpddr2io_regs {
+ unsigned int control_lpddr2io1_0;
+ unsigned int control_lpddr2io1_1;
+ unsigned int control_lpddr2io1_2;
+ unsigned int control_lpddr2io1_3;
+ unsigned int control_lpddr2io2_0;
+ unsigned int control_lpddr2io2_1;
+ unsigned int control_lpddr2io2_2;
+ unsigned int control_lpddr2io2_3;
+};
#endif /* __ASSEMBLY__ */
/*
--
1.7.0.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2011-09-07 8:16 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-08-09 12:43 [U-Boot] [PATCH 0/3] omap4: miscellaneous improvements/cleanups Aneesh V
2011-08-09 12:43 ` [U-Boot] [PATCH 1/3] omap4: factor out common part from board config headers Aneesh V
2011-08-09 12:43 ` [U-Boot] [PATCH 2/3] omap4: make SDRAM init work for ES1.0 silicon Aneesh V
2011-08-09 12:43 ` [U-Boot] [PATCH 3/3] omap4: IO settings Aneesh V
2011-09-06 15:25 ` [U-Boot] [PATCH v2 1/3] omap4: factor out common part from board config headers Aneesh V
2011-09-06 15:25 ` [U-Boot] [PATCH v2 2/3] omap4: make SDRAM init work for ES1.0 silicon Aneesh V
2011-09-06 15:25 ` [U-Boot] [PATCH v2 3/3] omap4: IO settings Aneesh V
2011-09-07 8:16 ` [U-Boot] [PATCH v3 1/3] omap4: factor out common part from board config headers Aneesh V
2011-09-07 8:16 ` [U-Boot] [PATCH v3 2/3] omap4: make SDRAM init work for ES1.0 silicon Aneesh V
2011-09-07 8:16 ` [U-Boot] [PATCH v3 3/3] omap4: IO settings Aneesh V
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