[U-Boot] Microblaze/Xilinx drivers changes

[U-Boot] Microblaze/Xilinx drivers changes

[Michal Simek]

Hi,

here is the whole package with Microblaze and Xilinx driver changes.
All patches are available in git://www.denx.de/git/u-boot-microblaze.git master branch
if you like to test them.

Thanks for your review,
Michal


Michal Simek (26):
      net: emaclite: Change driver name and add address
      net: emaclite: Remove deviceid property
      net: emaclite: Use calloc instead of malloc
      net: emaclite: Remove baseaddress from xemaclite
      net: emaclite: Use dynamic allocation
      net: emaclite: Setup RX/TX ping pong for every instance
      net: emaclite: Use unsigned long for baseaddr
      net: emaclite: Move RX/TX ping pong initialization to board
      net: emaclite: Use PKTSIZE directly
      net: emaclite: Fix coding style
      microblaze: Support CTRL+C when tftp is running
      microblaze: Support flashes on lower addresses
      microblaze: Initialize jumptable and console
      microblaze: Fix unaligned.h for endians
      microblaze: Copy bootfile from variables
      microblaze: Remove debug saving value
      microblaze: Setup MB vectors if feature is enable for u-boot
      microblaze: Save and restore first unused vector
      microblaze: Clean up reset asm code
      microblaze: Do not select NFS for platforms without ethernet
      microblaze: Remove address offset for uart16550
      microblaze: Enable FDT/FIT support
      serial: uartlite: Support for SERIAL_MULTI
      microblaze: Enable SERIAL_MULTI
      net: axi_ethernet: Add driver to u-boot
      microblaze: Wire up axi_ethernet driver initialization

 arch/microblaze/cpu/start.S                        |   67 +--
 arch/microblaze/include/asm/processor.h            |    5 +-
 arch/microblaze/include/asm/unaligned.h            |   17 +-
 arch/microblaze/lib/board.c                        |   19 +
 .../xilinx/microblaze-generic/microblaze-generic.c |   24 +-
 common/serial.c                                    |   14 +
 drivers/net/Makefile                               |    1 +
 drivers/net/xilinx_axi_emac.c                      |  664 ++++++++++++++++++++
 drivers/net/xilinx_emaclite.c                      |  250 ++++----
 drivers/serial/serial_xuartlite.c                  |  142 ++++-
 include/configs/microblaze-generic.h               |   15 +-
 include/netdev.h                                   |    5 +-
 include/serial.h                                   |    9 +-
 13 files changed, 1033 insertions(+), 199 deletions(-)
 create mode 100644 drivers/net/xilinx_axi_emac.c

[U-Boot] [PATCH 01/26] net: emaclite: Change driver name and add address

[Michal Simek]

Current xilinx emaclite use net multi registration
but doesn't support several emaclites interfaces.
Changing driver name with adding address to name
is the first step how to distiguish several drivers.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 drivers/net/xilinx_emaclite.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 3c7c250..8d170a3 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -350,7 +350,7 @@ int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
 		return -1;
 
 	memset(dev, 0, sizeof(*dev));
-	sprintf(dev->name, "Xilinx_Emaclite");
+	sprintf(dev->name, "Xelite.%x", base_addr);
 
 	dev->iobase = base_addr;
 	dev->priv = 0;
-- 
1.5.5.6

[U-Boot] [PATCH 02/26] net: emaclite: Remove deviceid property

[Michal Simek]

Cleanup structure.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 drivers/net/xilinx_emaclite.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 8d170a3..2a5c5e1 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -67,7 +67,6 @@ typedef struct {
 	u32 baseaddress;	/* Base address for device (IPIF) */
 	u32 nexttxbuffertouse;	/* Next TX buffer to write to */
 	u32 nextrxbuffertouse;	/* Next RX buffer to read from */
-	uchar deviceid;		/* Unique ID of device - for future */
 } xemaclite;
 
 static xemaclite emaclite;
-- 
1.5.5.6

[U-Boot] [PATCH 03/26] net: emaclite: Use calloc instead of malloc

[Michal Simek]

Simplify driver logic and clear eth_device structure
in one command.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 drivers/net/xilinx_emaclite.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 2a5c5e1..28aab97 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -344,11 +344,10 @@ int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
 {
 	struct eth_device *dev;
 
-	dev = malloc(sizeof(*dev));
+	dev = calloc(1, sizeof(*dev));
 	if (dev == NULL)
 		return -1;
 
-	memset(dev, 0, sizeof(*dev));
 	sprintf(dev->name, "Xelite.%x", base_addr);
 
 	dev->iobase = base_addr;
-- 
1.5.5.6

[U-Boot] [PATCH 04/26] net: emaclite: Remove baseaddress from xemaclite

[Michal Simek]

Use dev->iobase instead of baseaddress.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 drivers/net/xilinx_emaclite.c |   42 ++++++++++++++++++++--------------------
 1 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 28aab97..805da17 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -64,7 +64,6 @@
 #define XEL_RSR_RECV_IE_MASK		0x00000008UL
 
 typedef struct {
-	u32 baseaddress;	/* Base address for device (IPIF) */
 	u32 nexttxbuffertouse;	/* Next TX buffer to write to */
 	u32 nextrxbuffertouse;	/* Next RX buffer to read from */
 } xemaclite;
@@ -136,43 +135,44 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis)
 {
 	debug ("EmacLite Initialization Started\n");
 	memset (&emaclite, 0, sizeof (xemaclite));
-	emaclite.baseaddress = dev->iobase;
 
 /*
  * TX - TX_PING & TX_PONG initialization
  */
 	/* Restart PING TX */
-	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
+	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
 	/* Copy MAC address */
 	xemaclite_alignedwrite (dev->enetaddr,
-		emaclite.baseaddress, ENET_ADDR_LENGTH);
+		dev->iobase, ENET_ADDR_LENGTH);
 	/* Set the length */
-	out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
 	/* Update the MAC address in the EMAC Lite */
-	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
+	out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
 	/* Wait for EMAC Lite to finish with the MAC address update */
-	while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) &
-		XEL_TSR_PROG_MAC_ADDR) != 0) ;
+	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
+		XEL_TSR_PROG_MAC_ADDR) != 0)
+		;
 
 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
 	/* The same operation with PONG TX */
-	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
-	xemaclite_alignedwrite (dev->enetaddr, emaclite.baseaddress +
+	out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
+	xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
 		XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
-	out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
-	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
+	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+	out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
 		XEL_TSR_PROG_MAC_ADDR);
-	while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
-		XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ;
+	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
+		XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
+		;
 #endif
 
 /*
  * RX - RX_PING & RX_PONG initialization
  */
 	/* Write out the value to flush the RX buffer */
-	out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
+	out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
 #ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
-	out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
+	out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
 		XEL_RSR_RECV_IE_MASK);
 #endif
 
@@ -220,16 +220,16 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 	if (!maxtry) {
 		printf ("Error: Timeout waiting for ethernet TX buffer\n");
 		/* Restart PING TX */
-		out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
+		out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
-		out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
+		out_be32 (dev->iobase + XEL_TSR_OFFSET +
 		XEL_BUFFER_OFFSET, 0);
 #endif
 		return -1;
 	}
 
 	/* Determine the expected TX buffer address */
-	baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse);
+	baseaddress = (dev->iobase + emaclite.nexttxbuffertouse);
 
 	/* Determine if the expected buffer address is empty */
 	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
@@ -261,7 +261,7 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
 		&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
 			& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
-		debug ("Send packet from 0x%x\n", baseaddress);
+		debug("Send packet from 0x%x\n", baseaddress);
 		/* Write the frame to the buffer */
 		xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
 		out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
@@ -285,7 +285,7 @@ static int emaclite_recv(struct eth_device *dev)
 	u32 reg;
 	u32 baseaddress;
 
-	baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
+	baseaddress = dev->iobase + emaclite.nextrxbuffertouse;
 	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
 	debug ("Testing data at address 0x%x\n", baseaddress);
 	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
-- 
1.5.5.6

[U-Boot] [PATCH 05/26] net: emaclite: Use dynamic allocation

[Michal Simek]

Every emaclite instance use own setting.

Signed-off-by: Michal Simek <monstr@monstr.eu>

---
v2: Free allocated space when private data allocation failed
---
 drivers/net/xilinx_emaclite.c |   41 +++++++++++++++++++++++++----------------
 1 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 805da17..8e574cd 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -63,12 +63,10 @@
 /* Recv interrupt enable bit */
 #define XEL_RSR_RECV_IE_MASK		0x00000008UL
 
-typedef struct {
+struct xemaclite {
 	u32 nexttxbuffertouse;	/* Next TX buffer to write to */
 	u32 nextrxbuffertouse;	/* Next RX buffer to read from */
-} xemaclite;
-
-static xemaclite emaclite;
+};
 
 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
 
@@ -134,7 +132,6 @@ static void emaclite_halt(struct eth_device *dev)
 static int emaclite_init(struct eth_device *dev, bd_t *bis)
 {
 	debug ("EmacLite Initialization Started\n");
-	memset (&emaclite, 0, sizeof (xemaclite));
 
 /*
  * TX - TX_PING & TX_PONG initialization
@@ -180,22 +177,24 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis)
 	return 0;
 }
 
-static int xemaclite_txbufferavailable (xemaclite *instanceptr)
+static int xemaclite_txbufferavailable(struct eth_device *dev)
 {
 	u32 reg;
 	u32 txpingbusy;
 	u32 txpongbusy;
+	struct xemaclite *emaclite = dev->priv;
+
 	/*
 	 * Read the other buffer register
 	 * and determine if the other buffer is available
 	 */
-	reg = in_be32 (instanceptr->baseaddress +
-			instanceptr->nexttxbuffertouse + 0);
+	reg = in_be32 (dev->iobase +
+			emaclite->nexttxbuffertouse + 0);
 	txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
 			XEL_TSR_XMIT_BUSY_MASK);
 
-	reg = in_be32 (instanceptr->baseaddress +
-			(instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
+	reg = in_be32 (dev->iobase +
+			(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
 	txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
 			XEL_TSR_XMIT_BUSY_MASK);
 
@@ -206,13 +205,14 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 {
 	u32 reg;
 	u32 baseaddress;
+	struct xemaclite *emaclite = dev->priv;
 
 	u32 maxtry = 1000;
 
 	if (len > ENET_MAX_MTU)
 		len = ENET_MAX_MTU;
 
-	while (!xemaclite_txbufferavailable (&emaclite) && maxtry) {
+	while (!xemaclite_txbufferavailable(dev) && maxtry) {
 		udelay (10);
 		maxtry--;
 	}
@@ -229,7 +229,7 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 	}
 
 	/* Determine the expected TX buffer address */
-	baseaddress = (dev->iobase + emaclite.nexttxbuffertouse);
+	baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
 
 	/* Determine if the expected buffer address is empty */
 	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
@@ -238,7 +238,7 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 			& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
 
 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
-		emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
+		emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
 #endif
 		debug ("Send packet from 0x%x\n", baseaddress);
 		/* Write the frame to the buffer */
@@ -284,13 +284,14 @@ static int emaclite_recv(struct eth_device *dev)
 	u32 length;
 	u32 reg;
 	u32 baseaddress;
+	struct xemaclite *emaclite = dev->priv;
 
-	baseaddress = dev->iobase + emaclite.nextrxbuffertouse;
+	baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
 	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
 	debug ("Testing data at address 0x%x\n", baseaddress);
 	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
 #ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
-		emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
+		emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
 #endif
 	} else {
 #ifndef CONFIG_XILINX_EMACLITE_RX_PING_PONG
@@ -343,15 +344,23 @@ static int emaclite_recv(struct eth_device *dev)
 int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
 {
 	struct eth_device *dev;
+	struct xemaclite *emaclite;
 
 	dev = calloc(1, sizeof(*dev));
 	if (dev == NULL)
 		return -1;
 
+	emaclite = calloc(1, sizeof(struct xemaclite));
+	if (emaclite == NULL) {
+		free(dev);
+		return -1;
+	}
+
+	dev->priv = emaclite;
+
 	sprintf(dev->name, "Xelite.%x", base_addr);
 
 	dev->iobase = base_addr;
-	dev->priv = 0;
 	dev->init = emaclite_init;
 	dev->halt = emaclite_halt;
 	dev->send = emaclite_send;
-- 
1.5.5.6

[U-Boot] [PATCH 06/26] net: emaclite: Setup RX/TX ping pong for every instance

[Michal Simek]

Setup RX/TX ping-pong buffer for every emaclite IP separately.
The next patch move initialization directly to board code.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 drivers/net/xilinx_emaclite.c |  123 ++++++++++++++++++++++------------------
 1 files changed, 68 insertions(+), 55 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 8e574cd..9342476 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -66,6 +66,8 @@
 struct xemaclite {
 	u32 nexttxbuffertouse;	/* Next TX buffer to write to */
 	u32 nextrxbuffertouse;	/* Next RX buffer to read from */
+	u32 txpp;		/* TX ping pong buffer */
+	u32 rxpp;		/* RX ping pong buffer */
 };
 
 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
@@ -131,6 +133,7 @@ static void emaclite_halt(struct eth_device *dev)
 
 static int emaclite_init(struct eth_device *dev, bd_t *bis)
 {
+	struct xemaclite *emaclite = dev->priv;
 	debug ("EmacLite Initialization Started\n");
 
 /*
@@ -150,28 +153,28 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis)
 		XEL_TSR_PROG_MAC_ADDR) != 0)
 		;
 
-#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
-	/* The same operation with PONG TX */
-	out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
-	xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
-		XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
-	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
-	out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
-		XEL_TSR_PROG_MAC_ADDR);
-	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
-		XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
-		;
-#endif
+	if (emaclite->txpp) {
+		/* The same operation with PONG TX */
+		out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
+		xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
+			XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
+		out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+		out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
+			XEL_TSR_PROG_MAC_ADDR);
+		while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
+			XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
+			;
+	}
 
 /*
  * RX - RX_PING & RX_PONG initialization
  */
 	/* Write out the value to flush the RX buffer */
 	out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
-#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
-	out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
-		XEL_RSR_RECV_IE_MASK);
-#endif
+
+	if (emaclite->rxpp)
+		out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
+			XEL_RSR_RECV_IE_MASK);
 
 	debug ("EmacLite Initialization complete\n");
 	return 0;
@@ -221,10 +224,10 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 		printf ("Error: Timeout waiting for ethernet TX buffer\n");
 		/* Restart PING TX */
 		out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
-#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
-		out_be32 (dev->iobase + XEL_TSR_OFFSET +
-		XEL_BUFFER_OFFSET, 0);
-#endif
+		if (emaclite->txpp) {
+			out_be32 (dev->iobase + XEL_TSR_OFFSET +
+				XEL_BUFFER_OFFSET, 0);
+		}
 		return -1;
 	}
 
@@ -237,9 +240,9 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 		&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
 			& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
 
-#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
-		emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
-#endif
+		if (emaclite->txpp)
+			emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
+
 		debug ("Send packet from 0x%x\n", baseaddress);
 		/* Write the frame to the buffer */
 		xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
@@ -253,28 +256,30 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 		out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
 		return 0;
 	}
-#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
-	/* Switch to second buffer */
-	baseaddress ^= XEL_BUFFER_OFFSET;
-	/* Determine if the expected buffer address is empty */
-	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
-	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
-		&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
-			& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
-		debug("Send packet from 0x%x\n", baseaddress);
-		/* Write the frame to the buffer */
-		xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
-		out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
-			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
+
+	if (emaclite->txpp) {
+		/* Switch to second buffer */
+		baseaddress ^= XEL_BUFFER_OFFSET;
+		/* Determine if the expected buffer address is empty */
 		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
-		reg |= XEL_TSR_XMIT_BUSY_MASK;
-		if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
-			reg |= XEL_TSR_XMIT_ACTIVE_MASK;
+		if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
+			&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
+				& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
+			debug("Send packet from 0x%x\n", baseaddress);
+			/* Write the frame to the buffer */
+			xemaclite_alignedwrite((void *) ptr, baseaddress, len);
+			out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
+				(XEL_TPLR_LENGTH_MASK_HI |
+					XEL_TPLR_LENGTH_MASK_LO)));
+			reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
+			reg |= XEL_TSR_XMIT_BUSY_MASK;
+			if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
+				reg |= XEL_TSR_XMIT_ACTIVE_MASK;
+			out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
+			return 0;
 		}
-		out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
-		return 0;
 	}
-#endif
+
 	puts ("Error while sending frame\n");
 	return -1;
 }
@@ -290,23 +295,24 @@ static int emaclite_recv(struct eth_device *dev)
 	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
 	debug ("Testing data at address 0x%x\n", baseaddress);
 	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
-#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
-		emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
-#endif
+		if (emaclite->rxpp)
+			emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
 	} else {
-#ifndef CONFIG_XILINX_EMACLITE_RX_PING_PONG
-		debug ("No data was available - address 0x%x\n", baseaddress);
-		return 0;
-#else
-		baseaddress ^= XEL_BUFFER_OFFSET;
-		reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
-		if ((reg & XEL_RSR_RECV_DONE_MASK) !=
-					XEL_RSR_RECV_DONE_MASK) {
+
+		if (!emaclite->rxpp) {
 			debug ("No data was available - address 0x%x\n",
-					baseaddress);
+								baseaddress);
 			return 0;
+		} else {
+			baseaddress ^= XEL_BUFFER_OFFSET;
+			reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
+			if ((reg & XEL_RSR_RECV_DONE_MASK) !=
+						XEL_RSR_RECV_DONE_MASK) {
+				debug("No data was available - address 0x%x\n",
+						baseaddress);
+				return 0;
+			}
 		}
-#endif
 	}
 	/* Get the length of the frame that arrived */
 	switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
@@ -358,6 +364,13 @@ int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
 
 	dev->priv = emaclite;
 
+#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+	emaclite->txpp = 1;
+#endif
+#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+	emaclite->rxpp = 1;
+#endif
+
 	sprintf(dev->name, "Xelite.%x", base_addr);
 
 	dev->iobase = base_addr;
-- 
1.5.5.6

[U-Boot] [PATCH 07/26] net: emaclite: Use unsigned long for baseaddr

[Michal Simek]

Baseaddr should be unsigned long.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 drivers/net/xilinx_emaclite.c |    4 ++--
 include/netdev.h              |    2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 9342476..c4366c2 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -347,7 +347,7 @@ static int emaclite_recv(struct eth_device *dev)
 
 }
 
-int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
+int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr)
 {
 	struct eth_device *dev;
 	struct xemaclite *emaclite;
@@ -371,7 +371,7 @@ int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
 	emaclite->rxpp = 1;
 #endif
 
-	sprintf(dev->name, "Xelite.%x", base_addr);
+	sprintf(dev->name, "Xelite.%lx", base_addr);
 
 	dev->iobase = base_addr;
 	dev->init = emaclite_init;
diff --git a/include/netdev.h b/include/netdev.h
index 96c7b9b..5d78148 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -94,7 +94,7 @@ int smc911x_initialize(u8 dev_num, int base_addr);
 int tsi108_eth_initialize(bd_t *bis);
 int uec_standard_init(bd_t *bis);
 int uli526x_initialize(bd_t *bis);
-int xilinx_emaclite_initialize (bd_t *bis, int base_addr);
+int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr);
 
 /* Boards with PCI network controllers can call this from their board_eth_init()
  * function to initialize whatever's on board.
-- 
1.5.5.6

[U-Boot] [PATCH 08/26] net: emaclite: Move RX/TX ping pong initialization to board

[Michal Simek]

Init RX/TX ping pong directly from board not in the driver.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 .../xilinx/microblaze-generic/microblaze-generic.c |   18 ++++++++++++------
 drivers/net/xilinx_emaclite.c                      |   11 ++++-------
 include/netdev.h                                   |    3 ++-
 3 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index 183e4dc..9b2952f 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -71,12 +71,18 @@ int fsl_init2 (void) {
 
 int board_eth_init(bd_t *bis)
 {
-	/*
-	 * This board either has PCI NICs or uses the CPU's TSECs
-	 * pci_eth_init() will return 0 if no NICs found, so in that case
-	 * returning -1 will force cpu_eth_init() to be called.
-	 */
+	int ret = 0;
 #ifdef CONFIG_XILINX_EMACLITE
-	return xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR);
+	u32 txpp = 0;
+	u32 rxpp = 0;
+# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+	txpp = 1;
+# endif
+# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+	rxpp = 1;
+# endif
+	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
+			txpp, rxpp);
 #endif
+	return ret;
 }
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index c4366c2..eca6ef9 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -347,7 +347,8 @@ static int emaclite_recv(struct eth_device *dev)
 
 }
 
-int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr)
+int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
+							int txpp, int rxpp)
 {
 	struct eth_device *dev;
 	struct xemaclite *emaclite;
@@ -364,12 +365,8 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr)
 
 	dev->priv = emaclite;
 
-#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
-	emaclite->txpp = 1;
-#endif
-#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
-	emaclite->rxpp = 1;
-#endif
+	emaclite->txpp = txpp;
+	emaclite->rxpp = rxpp;
 
 	sprintf(dev->name, "Xelite.%lx", base_addr);
 
diff --git a/include/netdev.h b/include/netdev.h
index 5d78148..8b71011 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -94,7 +94,8 @@ int smc911x_initialize(u8 dev_num, int base_addr);
 int tsi108_eth_initialize(bd_t *bis);
 int uec_standard_init(bd_t *bis);
 int uli526x_initialize(bd_t *bis);
-int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr);
+int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
+							int txpp, int rxpp);
 
 /* Boards with PCI network controllers can call this from their board_eth_init()
  * function to initialize whatever's on board.
-- 
1.5.5.6

[U-Boot] [PATCH 09/26] net: emaclite: Use PKTSIZE directly

[Michal Simek]

Do not setup additional ENET_MAX_MTU macro.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 drivers/net/xilinx_emaclite.c |   10 ++++------
 1 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index eca6ef9..5ce95f8 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -31,8 +31,6 @@
 
 #undef DEBUG
 
-#define ENET_MAX_MTU		PKTSIZE
-#define ENET_MAX_MTU_ALIGNED	PKTSIZE_ALIGN
 #define ENET_ADDR_LENGTH	6
 
 /* EmacLite constants */
@@ -212,8 +210,8 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 
 	u32 maxtry = 1000;
 
-	if (len > ENET_MAX_MTU)
-		len = ENET_MAX_MTU;
+	if (len > PKTSIZE)
+		len = PKTSIZE;
 
 	while (!xemaclite_txbufferavailable(dev) && maxtry) {
 		udelay (10);
@@ -328,8 +326,8 @@ static int emaclite_recv(struct eth_device *dev)
 			debug ("IP Packet\n");
 			break;
 		default:
-			debug ("Other Packet\n");
-			length = ENET_MAX_MTU;
+			debug("Other Packet\n");
+			length = PKTSIZE;
 			break;
 	}
 
-- 
1.5.5.6

[U-Boot] [PATCH 10/26] net: emaclite: Fix coding style

[Michal Simek]

Coding style should follow linux coding style.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 drivers/net/xilinx_emaclite.c |   57 +++++++++++++++++++---------------------
 1 files changed, 27 insertions(+), 30 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 5ce95f8..9791b9a 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -70,7 +70,7 @@ struct xemaclite {
 
 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
 
-static void xemaclite_alignedread (u32 *srcptr, void *destptr, u32 bytecount)
+static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
 {
 	u32 i;
 	u32 alignbuffer;
@@ -90,14 +90,13 @@ static void xemaclite_alignedread (u32 *srcptr, void *destptr, u32 bytecount)
 	to8ptr = (u8 *) to32ptr;
 
 	alignbuffer = *from32ptr++;
-	from8ptr = (u8 *) & alignbuffer;
+	from8ptr = (u8 *) &alignbuffer;
 
-	for (i = 0; i < bytecount; i++) {
+	for (i = 0; i < bytecount; i++)
 		*to8ptr++ = *from8ptr++;
-	}
 }
 
-static void xemaclite_alignedwrite (void *srcptr, u32 destptr, u32 bytecount)
+static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
 {
 	u32 i;
 	u32 alignbuffer;
@@ -114,25 +113,24 @@ static void xemaclite_alignedwrite (void *srcptr, u32 destptr, u32 bytecount)
 	}
 
 	alignbuffer = 0;
-	to8ptr = (u8 *) & alignbuffer;
+	to8ptr = (u8 *) &alignbuffer;
 	from8ptr = (u8 *) from32ptr;
 
-	for (i = 0; i < bytecount; i++) {
+	for (i = 0; i < bytecount; i++)
 		*to8ptr++ = *from8ptr++;
-	}
 
 	*to32ptr++ = alignbuffer;
 }
 
 static void emaclite_halt(struct eth_device *dev)
 {
-	debug ("eth_halt\n");
+	debug("eth_halt\n");
 }
 
 static int emaclite_init(struct eth_device *dev, bd_t *bis)
 {
 	struct xemaclite *emaclite = dev->priv;
-	debug ("EmacLite Initialization Started\n");
+	debug("EmacLite Initialization Started\n");
 
 /*
  * TX - TX_PING & TX_PONG initialization
@@ -140,8 +138,7 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis)
 	/* Restart PING TX */
 	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
 	/* Copy MAC address */
-	xemaclite_alignedwrite (dev->enetaddr,
-		dev->iobase, ENET_ADDR_LENGTH);
+	xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
 	/* Set the length */
 	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
 	/* Update the MAC address in the EMAC Lite */
@@ -174,7 +171,7 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis)
 		out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
 			XEL_RSR_RECV_IE_MASK);
 
-	debug ("EmacLite Initialization complete\n");
+	debug("EmacLite Initialization complete\n");
 	return 0;
 }
 
@@ -199,10 +196,10 @@ static int xemaclite_txbufferavailable(struct eth_device *dev)
 	txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
 			XEL_TSR_XMIT_BUSY_MASK);
 
-	return (!(txpingbusy && txpongbusy));
+	return !(txpingbusy && txpongbusy);
 }
 
-static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
+static int emaclite_send(struct eth_device *dev, volatile void *ptr, int len)
 {
 	u32 reg;
 	u32 baseaddress;
@@ -214,12 +211,12 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 		len = PKTSIZE;
 
 	while (!xemaclite_txbufferavailable(dev) && maxtry) {
-		udelay (10);
+		udelay(10);
 		maxtry--;
 	}
 
 	if (!maxtry) {
-		printf ("Error: Timeout waiting for ethernet TX buffer\n");
+		printf("Error: Timeout waiting for ethernet TX buffer\n");
 		/* Restart PING TX */
 		out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
 		if (emaclite->txpp) {
@@ -241,16 +238,15 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 		if (emaclite->txpp)
 			emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
 
-		debug ("Send packet from 0x%x\n", baseaddress);
+		debug("Send packet from 0x%x\n", baseaddress);
 		/* Write the frame to the buffer */
-		xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
+		xemaclite_alignedwrite((void *) ptr, baseaddress, len);
 		out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
 			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
 		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
 		reg |= XEL_TSR_XMIT_BUSY_MASK;
-		if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
+		if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
 			reg |= XEL_TSR_XMIT_ACTIVE_MASK;
-		}
 		out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
 		return 0;
 	}
@@ -278,7 +274,7 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
 		}
 	}
 
-	puts ("Error while sending frame\n");
+	puts("Error while sending frame\n");
 	return -1;
 }
 
@@ -291,14 +287,14 @@ static int emaclite_recv(struct eth_device *dev)
 
 	baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
 	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
-	debug ("Testing data at address 0x%x\n", baseaddress);
+	debug("Testing data at address 0x%x\n", baseaddress);
 	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
 		if (emaclite->rxpp)
 			emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
 	} else {
 
 		if (!emaclite->rxpp) {
-			debug ("No data was available - address 0x%x\n",
+			debug("No data was available - address 0x%x\n",
 								baseaddress);
 			return 0;
 		} else {
@@ -317,12 +313,13 @@ static int emaclite_recv(struct eth_device *dev)
 			0xFFFF0000 ) >> 16) {
 		case 0x806:
 			length = 42 + 20; /* FIXME size of ARP */
-			debug ("ARP Packet\n");
+			debug("ARP Packet\n");
 			break;
 		case 0x800:
 			length = 14 + 14 +
-			(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10))) &
-			0xFFFF0000) >> 16); /* FIXME size of IP packet */
+			(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
+						0x10))) & 0xFFFF0000) >> 16);
+			/* FIXME size of IP packet */
 			debug ("IP Packet\n");
 			break;
 		default:
@@ -331,7 +328,7 @@ static int emaclite_recv(struct eth_device *dev)
 			break;
 	}
 
-	xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
+	xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
 			etherrxbuff, length);
 
 	/* Acknowledge the frame */
@@ -339,8 +336,8 @@ static int emaclite_recv(struct eth_device *dev)
 	reg &= ~XEL_RSR_RECV_DONE_MASK;
 	out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
 
-	debug ("Packet receive from 0x%x, length %dB\n", baseaddress, length);
-	NetReceive ((uchar *) etherrxbuff, length);
+	debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
+	NetReceive((uchar *) etherrxbuff, length);
 	return length;
 
 }
-- 
1.5.5.6

[U-Boot] [PATCH 11/26] microblaze: Support CTRL+C when tftp is running

[Michal Simek]

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 arch/microblaze/lib/board.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
index d97543b..5510c12 100644
--- a/arch/microblaze/lib/board.c
+++ b/arch/microblaze/lib/board.c
@@ -68,6 +68,7 @@ typedef int (init_fnc_t) (void);
 init_fnc_t *init_sequence[] = {
 	env_init,
 	serial_init,
+	console_init_f,
 #ifdef CONFIG_SYS_GPIO_0
 	gpio_init,
 #endif
-- 
1.5.5.6

[U-Boot] [PATCH 12/26] microblaze: Support flashes on lower addresses

[Michal Simek]

Signed-off-by: Michal Simek <monstr@monstr.eu>

---
v2: Change symbol references provided by a linker script

v3: Move externs to header
---
 arch/microblaze/include/asm/processor.h |    5 ++++-
 arch/microblaze/lib/board.c             |    4 ++++
 2 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h
index 78b8976..f35e31e 100644
--- a/arch/microblaze/include/asm/processor.h
+++ b/arch/microblaze/include/asm/processor.h
@@ -1 +1,4 @@
-/* FIXME: Implement this! */
+
+/* References to section boundaries */
+extern char __end[];
+extern char __text_start[];
diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
index 5510c12..af33a15 100644
--- a/arch/microblaze/lib/board.c
+++ b/arch/microblaze/lib/board.c
@@ -84,6 +84,8 @@ init_fnc_t *init_sequence[] = {
 	NULL,
 };
 
+unsigned long monitor_flash_len;
+
 void board_init (void)
 {
 	bd_t *bd;
@@ -105,6 +107,8 @@ void board_init (void)
 	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 	gd->flags |= GD_FLG_RELOC;      /* tell others: relocation done */
 
+	monitor_flash_len = __end - __text_start;
+
 	/*
 	 * The Malloc area is immediately below the monitor copy in DRAM
 	 * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
-- 
1.5.5.6

[U-Boot] [PATCH 13/26] microblaze: Initialize jumptable and console

[Michal Simek]

This changes were done to get support for netconsole.

Signed-off-by: Michal Simek <monstr@monstr.eu>

---
v2: Fix commit message

v3: Fix coding style
---
 arch/microblaze/lib/board.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
index af33a15..75748f3 100644
--- a/arch/microblaze/lib/board.c
+++ b/arch/microblaze/lib/board.c
@@ -165,6 +165,12 @@ void board_init (void)
 	/* Initialize stdio devices */
 	stdio_init ();
 
+	/* Initialize the jump table for applications */
+	jumptable_init();
+
+	/* Initialize the console (after the relocation and devices init) */
+	console_init_r();
+
 	if ((s = getenv ("loadaddr")) != NULL) {
 		load_addr = simple_strtoul (s, NULL, 16);
 	}
-- 
1.5.5.6

[U-Boot] [PATCH 14/26] microblaze: Fix unaligned.h for endians

[Michal Simek]

Also support little endian MB.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 arch/microblaze/include/asm/unaligned.h |   17 +----------------
 1 files changed, 1 insertions(+), 16 deletions(-)

diff --git a/arch/microblaze/include/asm/unaligned.h b/arch/microblaze/include/asm/unaligned.h
index 785c2e9..6cecbbb 100644
--- a/arch/microblaze/include/asm/unaligned.h
+++ b/arch/microblaze/include/asm/unaligned.h
@@ -1,16 +1 @@
-#ifndef _ASM_MICROBLAZE_UNALIGNED_H
-#define _ASM_MICROBLAZE_UNALIGNED_H
-
-#ifdef __KERNEL__
-
-/*
- * The Microblaze can do unaligned accesses itself in big endian mode.
- */
-#include <linux/unaligned/access_ok.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-
-#endif	/* __KERNEL__ */
-#endif	/* _ASM_MICROBLAZE_UNALIGNED_H */
+#include <asm-generic/unaligned.h>
-- 
1.5.5.6

[U-Boot] [PATCH 15/26] microblaze: Copy bootfile from variables

[Michal Simek]

Setup bootfile.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 arch/microblaze/lib/board.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
index 75748f3..8865a60 100644
--- a/arch/microblaze/lib/board.c
+++ b/arch/microblaze/lib/board.c
@@ -185,6 +185,10 @@ void board_init (void)
 	uchar enetaddr[6];
 	eth_getenv_enetaddr("ethaddr", enetaddr);
 	printf("MAC:   %pM\n", enetaddr);
+
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
 #endif
 
 	/* main_loop */
-- 
1.5.5.6

[U-Boot] [PATCH 16/26] microblaze: Remove debug saving value

[Michal Simek]

Forget to remove debug code.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 arch/microblaze/cpu/start.S |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 93a9efd..d3370c4 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -46,8 +46,6 @@ _start:
 	addik	r6, r0, 0x2 /* BIG/LITTLE endian offset */
 	swi	r6, r0, 0
 	lbui	r10, r0, 0
-	swi	r6, r0, 0x40
-	swi	r10, r0, 0x50
 
 	/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
 	addi	r6, r0, 0xb0000000	/* hex b000 opcode imm */
-- 
1.5.5.6

[U-Boot] [PATCH 17/26] microblaze: Setup MB vectors if feature is enable for u-boot

[Michal Simek]

For example: Setup reset vectors if reset address is setup.
Setup user exception vector if user exception is enabled

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 arch/microblaze/cpu/start.S |   34 ++++++++++++++++++++++------------
 1 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index d3370c4..17c0e28 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -30,6 +30,13 @@
 	.text
 	.global _start
 _start:
+	/*
+	 * reserve registers:
+	 * r10: Stores little/big endian offset for vectors
+	 * r2: Stores imm opcode
+	 * r3: Stores brai opcode
+	 */
+
 	mts	rmsr, r0	/* disable cache */
 	addi	r1, r0, CONFIG_SYS_INIT_SP_OFFSET
 	addi	r1, r1, -4	/* Decrement SP to top of memory */
@@ -47,21 +54,15 @@ _start:
 	swi	r6, r0, 0
 	lbui	r10, r0, 0
 
-	/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
-	addi	r6, r0, 0xb0000000	/* hex b000 opcode imm */
-	swi	r6, r0, 0x0	/* reset address */
-	swi	r6, r0, 0x8	/* user vector exception */
-	swi	r6, r0, 0x10	/* interrupt */
-	swi	r6, r0, 0x20	/* hardware exception */
-
-	addi	r6, r0, 0xb8080000	/* hew b808 opcode brai*/
-	swi	r6, r0, 0x4	/* reset address */
-	swi	r6, r0, 0xC	/* user vector exception */
-	swi	r6, r0, 0x14	/* interrupt */
-	swi	r6, r0, 0x24	/* hardware exception */
+	/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
+	addi	r2, r0, 0xb0000000	/* hex b000 opcode imm */
+	addi	r3, r0, 0xb8080000	/* hew b808 opcode brai */
 
 #ifdef CONFIG_SYS_RESET_ADDRESS
 	/* reset address */
+	swi	r2, r0, 0x0	/* reset address - imm opcode */
+	swi	r3, r0, 0x4	/* reset address - brai opcode */
+
 	addik	r6, r0, CONFIG_SYS_RESET_ADDRESS
 	sw	r6, r1, r0
 	lhu	r7, r1, r0
@@ -88,6 +89,9 @@ _start:
 
 #ifdef CONFIG_SYS_USR_EXCEP
 	/* user_vector_exception */
+	swi	r2, r0, 0x8	/* user vector exception - imm opcode */
+	swi	r3, r0, 0xC	/* user vector exception - brai opcode */
+
 	addik	r6, r0, _exception_handler
 	sw	r6, r1, r0
 	/*
@@ -119,6 +123,9 @@ _start:
 
 #ifdef CONFIG_SYS_INTC_0
 	/* interrupt_handler */
+	swi	r2, r0, 0x10	/* interrupt - imm opcode */
+	swi	r3, r0, 0x14	/* interrupt - brai opcode */
+
 	addik	r6, r0, _interrupt_handler
 	sw	r6, r1, r0
 	lhu	r7, r1, r10
@@ -129,6 +136,9 @@ _start:
 #endif
 
 	/* hardware exception */
+	swi	r2, r0, 0x20	/* hardware exception - imm opcode */
+	swi	r3, r0, 0x24	/* hardware exception - brai opcode */
+
 	addik	r6, r0, _hw_exception_handler
 	sw	r6, r1, r0
 	lhu	r7, r1, r10
-- 
1.5.5.6

[U-Boot] [PATCH 18/26] microblaze: Save and restore first unused vector

[Michal Simek]

Use one memory space to detect little/big endian platforms.
The first unused address(0x28) is used instead 0x0 address (reset vectors).
Detection rewrited reset vector setup from first stage bootloader.

Workflow:
1. Store 0x28 to r7
2. Do little/big endian test
3. Restore r7 to 0x28

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 arch/microblaze/cpu/start.S |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 17c0e28..42104fa 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -51,8 +51,10 @@ _start:
 	 * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
 	 */
 	addik	r6, r0, 0x2 /* BIG/LITTLE endian offset */
-	swi	r6, r0, 0
-	lbui	r10, r0, 0
+	lwi	r7, r0, 0x28
+	swi	r6, r0, 0x28 /* used first unused MB vector */
+	lbui	r10, r0, 0x28 /* used first unused MB vector */
+	swi	r7, r0, 0x28
 
 	/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
 	addi	r2, r0, 0xb0000000	/* hex b000 opcode imm */
-- 
1.5.5.6

[U-Boot] [PATCH 19/26] microblaze: Clean up reset asm code

[Michal Simek]

- Remove code copying
- Reset address is setup from first stage bootloader
- Support reset vector setup on little endian

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 arch/microblaze/cpu/start.S |   25 +++++--------------------
 1 files changed, 5 insertions(+), 20 deletions(-)

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 42104fa..9077f74 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -67,26 +67,11 @@ _start:
 
 	addik	r6, r0, CONFIG_SYS_RESET_ADDRESS
 	sw	r6, r1, r0
-	lhu	r7, r1, r0
-	shi	r7, r0, 0x2
-	shi	r6, r0, 0x6
-/*
- * Copy U-Boot code to CONFIG_SYS_TEXT_BASE
- * solve problem with sbrk_base
- */
-#if (CONFIG_SYS_RESET_ADDRESS != CONFIG_SYS_TEXT_BASE)
-	addi	r4, r0, __end
-	addi	r5, r0, __text_start
-	rsub	r4, r5, r4	/* size = __end - __text_start */
-	addi	r6, r0, CONFIG_SYS_RESET_ADDRESS	/* source address */
-	addi	r7, r0, 0	/* counter */
-4:
-	lw	r8, r6, r7
-	sw	r8, r5, r7
-	addi	r7, r7, 0x4
-	cmp	r8, r4, r7
-	blti	r8, 4b
-#endif
+	lhu	r7, r1, r10
+	rsubi	r8, r10, 0x2
+	sh	r7, r0, r8
+	rsubi	r8, r10, 0x6
+	sh	r6, r0, r8
 #endif
 
 #ifdef CONFIG_SYS_USR_EXCEP
-- 
1.5.5.6

[U-Boot] [PATCH 20/26] microblaze: Do not select NFS for platforms without ethernet

[Michal Simek]

Undefined network functionality for systems without ethernet
and disable NFS support.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 include/configs/microblaze-generic.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 090ab3b..8cdd72a 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -60,6 +60,7 @@
 /*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/
 
 /* ethernet */
+#undef CONFIG_SYS_ENET
 #ifdef XILINX_EMACLITE_BASEADDR
 # define CONFIG_XILINX_EMACLITE		1
 # define CONFIG_SYS_ENET
@@ -243,6 +244,7 @@
 #ifndef CONFIG_SYS_ENET
 # undef CONFIG_CMD_NET
 # undef CONFIG_NET_MULTI
+# undef CONFIG_CMD_NFS
 #else
 # define CONFIG_CMD_PING
 # define CONFIG_CMD_DHCP
-- 
1.5.5.6

[U-Boot] [PATCH 21/26] microblaze: Remove address offset for uart16550

[Michal Simek]

U-Boot BSP handle 0x3 offset for big endian systems.
Little endian Microblaze systems don't use any offset.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 include/configs/microblaze-generic.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 8cdd72a..a334110 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -44,7 +44,7 @@
 # define CONFIG_SYS_NS16550_REG_SIZE	-4
 # define CONFIG_CONS_INDEX		1
 # define CONFIG_SYS_NS16550_COM1 \
-			(XILINX_UART16550_BASEADDR + 0x1000 + 0x3)
+			(XILINX_UART16550_BASEADDR + 0x1000)
 # define CONFIG_SYS_NS16550_CLK	XILINX_UART16550_CLOCK_HZ
 # define CONFIG_BAUDRATE	115200
 
-- 
1.5.5.6

[U-Boot] [PATCH 22/26] microblaze: Enable FDT/FIT support

[Michal Simek]

Enable FDT and FIT support.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 include/configs/microblaze-generic.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index a334110..a811b76 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -327,4 +327,9 @@
 # define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
+/* Enable flat device tree support */
+#define CONFIG_LMB		1
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+
 #endif	/* __CONFIG_H */
-- 
1.5.5.6

[U-Boot] [PATCH 23/26] serial: uartlite: Support for SERIAL_MULTI

[Michal Simek]

Add support for SERIAL MULTI for uartlite.

Signed-off-by: Michal Simek <monstr@monstr.eu>

---
v2: Use in/out_be32 functions
    Clean coding style
---
 common/serial.c                   |   14 ++++
 drivers/serial/serial_xuartlite.c |  142 ++++++++++++++++++++++++++++++++-----
 include/serial.h                  |    7 ++
 3 files changed, 145 insertions(+), 18 deletions(-)

diff --git a/common/serial.c b/common/serial.c
index 995d268..df02fa5 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -108,6 +108,20 @@ void serial_initialize (void)
 #if defined(CONFIG_SYS_BFIN_UART)
 	serial_register_bfin_uart();
 #endif
+#if defined(CONFIG_XILINX_UARTLITE)
+# ifdef XILINX_UARTLITE_BASEADDR
+	serial_register(&uartlite_serial0_device);
+# endif /* XILINX_UARTLITE_BASEADDR */
+# ifdef XILINX_UARTLITE_BASEADDR1
+	serial_register(&uartlite_serial1_device);
+# endif /* XILINX_UARTLITE_BASEADDR1 */
+# ifdef XILINX_UARTLITE_BASEADDR2
+	serial_register(&uartlite_serial2_device);
+# endif /* XILINX_UARTLITE_BASEADDR2 */
+# ifdef XILINX_UARTLITE_BASEADDR3
+	serial_register(&uartlite_serial3_device);
+# endif /* XILINX_UARTLITE_BASEADDR3 */
+#endif /* CONFIG_XILINX_UARTLITE */
 	serial_assign (default_serial_console ()->name);
 }
 
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index 00d0eaa..6650f2a 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -25,20 +25,75 @@
  */
 
 #include <config.h>
+#include <common.h>
 #include <asm/io.h>
-
-#define RX_FIFO_OFFSET		0 /* receive FIFO, read only */
-#define TX_FIFO_OFFSET		4 /* transmit FIFO, write only */
-#define STATUS_REG_OFFSET	8 /* status register, read only */
+#include <linux/compiler.h>
+#include <serial.h>
 
 #define SR_TX_FIFO_FULL		0x08 /* transmit FIFO full */
 #define SR_RX_FIFO_VALID_DATA	0x01 /* data in receive FIFO */
 #define SR_RX_FIFO_FULL		0x02 /* receive FIFO full */
 
-#define UARTLITE_STATUS		(CONFIG_SERIAL_BASE + STATUS_REG_OFFSET)
-#define UARTLITE_TX_FIFO	(CONFIG_SERIAL_BASE + TX_FIFO_OFFSET)
-#define UARTLITE_RX_FIFO	(CONFIG_SERIAL_BASE + RX_FIFO_OFFSET)
+struct uartlite {
+	u32 rx_fifo;
+	u32 tx_fifo;
+	u32 status;
+};
+
+static struct uartlite *userial_ports[4] = {
+#ifdef XILINX_UARTLITE_BASEADDR
+	(struct uartlite *)XILINX_UARTLITE_BASEADDR,
+#else
+	NULL,
+#endif
+#ifdef XILINX_UARTLITE_BASEADDR1
+	(struct uartlite *)XILINX_UARTLITE_BASEADDR1,
+#else
+	NULL,
+#endif
+#ifdef XILINX_UARTLITE_BASEADDR2
+	(struct uartlite *)XILINX_UARTLITE_BASEADDR2,
+#else
+	NULL,
+#endif
+#ifdef XILINX_UARTLITE_BASEADDR3
+	(struct uartlite *)XILINX_UARTLITE_BASEADDR3
+#else
+	NULL
+#endif
+};
+
+void uartlite_serial_putc(const char c, const int port)
+{
+	struct uartlite *regs = userial_ports[port];
+	if (c == '\n')
+		uartlite_serial_putc('\r', port);
+	while (in_be32(&regs->status) & SR_TX_FIFO_FULL)
+		;
+	out_be32(&regs->tx_fifo, c & 0xff);
+}
+
+void uartlite_serial_puts(const char *s, const int port)
+{
+	while (*s)
+		uartlite_serial_putc(*s++, port);
+}
+
+int uartlite_serial_getc(const int port)
+{
+	struct uartlite *regs = userial_ports[port];
+	while (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA))
+		;
+	return in_be32(&regs->rx_fifo) & 0xff;
+}
+
+int uartlite_serial_tstc(const int port)
+{
+	struct uartlite *regs = userial_ports[port];
+	return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA;
+}
 
+#if !defined(CONFIG_SERIAL_MULTI)
 int serial_init(void)
 {
 	/* FIXME: Nothing for now. We should initialize fifo, etc */
@@ -52,26 +107,77 @@ void serial_setbrg(void)
 
 void serial_putc(const char c)
 {
-	if (c == '\n')
-		serial_putc('\r');
-	while (in_be32((u32 *) UARTLITE_STATUS) & SR_TX_FIFO_FULL);
-	out_be32((u32 *) UARTLITE_TX_FIFO, (unsigned char) (c & 0xff));
+	uartlite_serial_putc(c, 0);
 }
 
-void serial_puts(const char * s)
+void serial_puts(const char *s)
 {
-	while (*s) {
-		serial_putc(*s++);
-	}
+	uartlite_serial_puts(s, 0);
 }
 
 int serial_getc(void)
 {
-	while (!(in_be32((u32 *) UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA));
-	return in_be32((u32 *) UARTLITE_RX_FIFO) & 0xff;
+	return uartlite_serial_getc(0);
 }
 
 int serial_tstc(void)
 {
-	return (in_be32((u32 *) UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA);
+	return uartlite_serial_tstc(0);
+}
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+/* Multi serial device functions */
+#define DECLARE_ESERIAL_FUNCTIONS(port) \
+	int userial##port##_init(void) \
+				{ return(0); } \
+	void userial##port##_setbrg(void) {} \
+	int userial##port##_getc(void) \
+				{ return uartlite_serial_getc(port); } \
+	int userial##port##_tstc(void) \
+				{ return uartlite_serial_tstc(port); } \
+	void userial##port##_putc(const char c) \
+				{ uartlite_serial_putc(c, port); } \
+	void userial##port##_puts(const char *s) \
+				{ uartlite_serial_puts(s, port); }
+
+/* Serial device descriptor */
+#define INIT_ESERIAL_STRUCTURE(port, name) {\
+	name,\
+	userial##port##_init,\
+	NULL,\
+	userial##port##_setbrg,\
+	userial##port##_getc,\
+	userial##port##_tstc,\
+	userial##port##_putc,\
+	userial##port##_puts, }
+
+DECLARE_ESERIAL_FUNCTIONS(0);
+struct serial_device uartlite_serial0_device =
+	INIT_ESERIAL_STRUCTURE(0, "ttyUL0");
+DECLARE_ESERIAL_FUNCTIONS(1);
+struct serial_device uartlite_serial1_device =
+	INIT_ESERIAL_STRUCTURE(1, "ttyUL1");
+DECLARE_ESERIAL_FUNCTIONS(2);
+struct serial_device uartlite_serial2_device =
+	INIT_ESERIAL_STRUCTURE(2, "ttyUL2");
+DECLARE_ESERIAL_FUNCTIONS(3);
+struct serial_device uartlite_serial3_device =
+	INIT_ESERIAL_STRUCTURE(3, "ttyUL3");
+
+__weak struct serial_device *default_serial_console(void)
+{
+# ifdef XILINX_UARTLITE_BASEADDR
+	return &uartlite_serial0_device;
+# endif /* XILINX_UARTLITE_BASEADDR */
+# ifdef XILINX_UARTLITE_BASEADDR1
+	return &uartlite_serial1_device;
+# endif /* XILINX_UARTLITE_BASEADDR1 */
+# ifdef XILINX_UARTLITE_BASEADDR2
+	return &uartlite_serial2_device;
+# endif /* XILINX_UARTLITE_BASEADDR2 */
+# ifdef XILINX_UARTLITE_BASEADDR3
+	return &uartlite_serial3_device;
+# endif /* XILINX_UARTLITE_BASEADDR3 */
 }
+#endif /* CONFIG_SERIAL_MULTI */
diff --git a/include/serial.h b/include/serial.h
index ff1ce99..5926244 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -50,6 +50,13 @@ extern struct serial_device serial4_device;
 extern struct serial_device serial6_device;
 #endif
 
+#if defined(CONFIG_XILINX_UARTLITE)
+extern struct serial_device uartlite_serial0_device;
+extern struct serial_device uartlite_serial1_device;
+extern struct serial_device uartlite_serial2_device;
+extern struct serial_device uartlite_serial3_device;
+#endif
+
 #if defined(CONFIG_S3C2410)
 extern struct serial_device s3c24xx_serial0_device;
 extern struct serial_device s3c24xx_serial1_device;
-- 
1.5.5.6

[U-Boot] [PATCH 24/26] microblaze: Enable SERIAL_MULTI

[Michal Simek]

Enable support for SERIAL_MULTI.

Microblaze can use uart16550 and uartlite drivers.

Signed-off-by: Michal Simek <monstr@monstr.eu>

---
Note:
 Follow serial.h conding style.
---
 arch/microblaze/lib/board.c          |    4 ++++
 include/configs/microblaze-generic.h |    2 ++
 include/serial.h                     |    2 +-
 3 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
index 8865a60..4e195ac 100644
--- a/arch/microblaze/lib/board.c
+++ b/arch/microblaze/lib/board.c
@@ -31,6 +31,7 @@
 #include <watchdog.h>
 #include <stdio_dev.h>
 #include <net.h>
+#include <serial.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -109,6 +110,9 @@ void board_init (void)
 
 	monitor_flash_len = __end - __text_start;
 
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
 	/*
 	 * The Malloc area is immediately below the monitor copy in DRAM
 	 * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index a811b76..c526006 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -31,6 +31,8 @@
 #define	CONFIG_MICROBLAZE	1
 #define	MICROBLAZE_V5		1
 
+#define CONFIG_SERIAL_MULTI 1
+
 /* uart */
 #ifdef XILINX_UARTLITE_BASEADDR
 # define CONFIG_XILINX_UARTLITE
diff --git a/include/serial.h b/include/serial.h
index 5926244..f047d2f 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -31,7 +31,7 @@ extern struct serial_device * default_serial_console (void);
     defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
     defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
     defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
-    defined(CONFIG_TEGRA2)
+    defined(CONFIG_TEGRA2) || defined(CONFIG_MICROBLAZE)
 extern struct serial_device serial0_device;
 extern struct serial_device serial1_device;
 #if defined(CONFIG_SYS_NS16550_SERIAL)
-- 
1.5.5.6

[U-Boot] [PATCH 25/26] net: axi_ethernet: Add driver to u-boot

[Michal Simek]

Add axi_ethernet driver for little-endian Microblaze.

RX/TX BDs and rxframe buffer are shared among all axi_ethernet MACs.
Only one MAC can work in one time.

Signed-off-by: Michal Simek <monstr@monstr.eu>

---

v2: Fix cammelcase weirdness
    Create mdio_wait function with timeouts
    Synchronize debug messages
    Remove base address + offset notation -> use struct instead

v3: Fix comments
    Add timeouts/delays to waiting loops
    Use in/out_be32 for dma accesses
    Setup return values for phy functions
---
 drivers/net/Makefile          |    1 +
 drivers/net/xilinx_axi_emac.c |  664 +++++++++++++++++++++++++++++++++++++++++
 include/netdev.h              |    2 +
 3 files changed, 667 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/xilinx_axi_emac.c

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 819b197..0489ffa 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -83,6 +83,7 @@ COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
 COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
 COBJS-$(CONFIG_ULI526X) += uli526x.o
 COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
+COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
 COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
 
 COBJS	:= $(sort $(COBJS-y))
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
new file mode 100644
index 0000000..82e254b
--- /dev/null
+++ b/drivers/net/xilinx_axi_emac.c
@@ -0,0 +1,664 @@
+/*
+ * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2011 PetaLogix
+ * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <phy.h>
+#include <miiphy.h>
+
+#if !defined(CONFIG_PHYLIB)
+# error AXI_ETHERNET requires PHYLIB
+#endif
+
+/* Link setup */
+#define XAE_EMMC_LINKSPEED_MASK	0xC0000000 /* Link speed */
+#define XAE_EMMC_LINKSPD_10	0x00000000 /* Link Speed mask for 10 Mbit */
+#define XAE_EMMC_LINKSPD_100	0x40000000 /* Link Speed mask for 100 Mbit */
+#define XAE_EMMC_LINKSPD_1000	0x80000000 /* Link Speed mask for 1000 Mbit */
+
+/* Interrupt Status/Enable/Mask Registers bit definitions */
+#define XAE_INT_RXRJECT_MASK	0x00000008 /* Rx frame rejected */
+#define XAE_INT_MGTRDY_MASK	0x00000080 /* MGT clock Lock */
+
+/* Receive Configuration Word 1 (RCW1) Register bit definitions */
+#define XAE_RCW1_RX_MASK	0x10000000 /* Receiver enable */
+
+/* Transmitter Configuration (TC) Register bit definitions */
+#define XAE_TC_TX_MASK		0x10000000 /* Transmitter enable */
+
+#define XAE_UAW1_UNICASTADDR_MASK	0x0000FFFF
+
+/* MDIO Management Configuration (MC) Register bit definitions */
+#define XAE_MDIO_MC_MDIOEN_MASK		0x00000040 /* MII management enable*/
+
+/* MDIO Management Control Register (MCR) Register bit definitions */
+#define XAE_MDIO_MCR_PHYAD_MASK		0x1F000000 /* Phy Address Mask */
+#define XAE_MDIO_MCR_PHYAD_SHIFT	24	   /* Phy Address Shift */
+#define XAE_MDIO_MCR_REGAD_MASK		0x001F0000 /* Reg Address Mask */
+#define XAE_MDIO_MCR_REGAD_SHIFT	16	   /* Reg Address Shift */
+#define XAE_MDIO_MCR_OP_READ_MASK	0x00008000 /* Op Code Read Mask */
+#define XAE_MDIO_MCR_OP_WRITE_MASK	0x00004000 /* Op Code Write Mask */
+#define XAE_MDIO_MCR_INITIATE_MASK	0x00000800 /* Ready Mask */
+#define XAE_MDIO_MCR_READY_MASK		0x00000080 /* Ready Mask */
+
+#define XAE_MDIO_DIV_DFT	29	/* Default MDIO clock divisor */
+
+/* DMA macros */
+/* Bitmasks of XAXIDMA_CR_OFFSET register */
+#define XAXIDMA_CR_RUNSTOP_MASK	0x00000001 /* Start/stop DMA channel */
+#define XAXIDMA_CR_RESET_MASK	0x00000004 /* Reset DMA engine */
+
+/* Bitmasks of XAXIDMA_SR_OFFSET register */
+#define XAXIDMA_HALTED_MASK	0x00000001  /* DMA channel halted */
+
+/* Bitmask for interrupts */
+#define XAXIDMA_IRQ_IOC_MASK	0x00001000 /* Completion intr */
+#define XAXIDMA_IRQ_DELAY_MASK	0x00002000 /* Delay interrupt */
+#define XAXIDMA_IRQ_ALL_MASK	0x00007000 /* All interrupts */
+
+/* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
+#define XAXIDMA_BD_CTRL_TXSOF_MASK	0x08000000 /* First tx packet */
+#define XAXIDMA_BD_CTRL_TXEOF_MASK	0x04000000 /* Last tx packet */
+
+#define DMAALIGN	128
+
+static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
+
+/* Reflect dma offsets */
+struct axidma_reg {
+	u32 control; /* DMACR */
+	u32 status; /* DMASR */
+	u32 current; /* CURDESC */
+	u32 reserved;
+	u32 tail; /* TAILDESC */
+};
+
+/* Private driver structures */
+struct axidma_priv {
+	struct axidma_reg *dmatx;
+	struct axidma_reg *dmarx;
+	int phyaddr;
+
+	struct phy_device *phydev;
+	struct mii_dev *bus;
+};
+
+/* BD descriptors */
+struct axidma_bd {
+	u32 next;	/* Next descriptor pointer */
+	u32 reserved1;
+	u32 phys;	/* Buffer address */
+	u32 reserved2;
+	u32 reserved3;
+	u32 reserved4;
+	u32 cntrl;	/* Control */
+	u32 status;	/* Status */
+	u32 app0;
+	u32 app1;	/* TX start << 16 | insert */
+	u32 app2;	/* TX csum seed */
+	u32 app3;
+	u32 app4;
+	u32 sw_id_offset;
+	u32 reserved5;
+	u32 reserved6;
+};
+
+/* Static BDs - driver uses only one BD */
+static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
+static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
+
+struct axi_regs {
+	u32 reserved[3];
+	u32 is; /* 0xC: Interrupt status */
+	u32 reserved2;
+	u32 ie; /* 0x14: Interrupt enable */
+	u32 reserved3[251];
+	u32 rcw1; /* 0x404: Rx Configuration Word 1 */
+	u32 tc; /* 0x408: Tx Configuration */
+	u32 reserved4;
+	u32 emmc; /* 0x410: EMAC mode configuration */
+	u32 reserved5[59];
+	u32 mdio_mc; /* 0x500: MII Management Config */
+	u32 mdio_mcr; /* 0x504: MII Management Control */
+	u32 mdio_mwd; /* 0x508: MII Management Write Data */
+	u32 mdio_mrd; /* 0x50C: MII Management Read Data */
+	u32 reserved6[124];
+	u32 uaw0; /* 0x700: Unicast address word 0 */
+	u32 uaw1; /* 0x704: Unicast address word 1 */
+};
+
+/* Use MII register 1 (MII status register) to detect PHY */
+#define PHY_DETECT_REG  1
+
+/*
+ * Mask used to verify certain PHY features (or register contents)
+ * in the register above:
+ *  0x1000: 10Mbps full duplex support
+ *  0x0800: 10Mbps half duplex support
+ *  0x0008: Auto-negotiation support
+ */
+#define PHY_DETECT_MASK 0x1808
+
+static inline int mdio_wait(struct eth_device *dev)
+{
+	struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+	u32 timeout = 200;
+
+	/* Wait till MDIO interface is ready to accept a new transaction. */
+	while (timeout && (!(in_be32(&regs->mdio_mcr)
+						& XAE_MDIO_MCR_READY_MASK))) {
+		timeout--;
+		udelay(1);
+	}
+	if (!timeout) {
+		printf("%s: Timeout\n", __func__);
+		return 1;
+	}
+	return 0;
+}
+
+static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
+								u16 *val)
+{
+	struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+	u32 mdioctrlreg = 0;
+
+	if (mdio_wait(dev))
+		return 1;
+
+	mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
+			XAE_MDIO_MCR_PHYAD_MASK) |
+			((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
+			& XAE_MDIO_MCR_REGAD_MASK) |
+			XAE_MDIO_MCR_INITIATE_MASK |
+			XAE_MDIO_MCR_OP_READ_MASK;
+
+	out_be32(&regs->mdio_mcr, mdioctrlreg);
+
+	if (mdio_wait(dev))
+		return 1;
+
+	/* Read data */
+	*val = in_be32(&regs->mdio_mrd);
+	return 0;
+}
+
+static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
+								u32 data)
+{
+	struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+	u32 mdioctrlreg = 0;
+
+	if (mdio_wait(dev))
+		return 1;
+
+	mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
+			XAE_MDIO_MCR_PHYAD_MASK) |
+			((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
+			& XAE_MDIO_MCR_REGAD_MASK) |
+			XAE_MDIO_MCR_INITIATE_MASK |
+			XAE_MDIO_MCR_OP_WRITE_MASK;
+
+	/* Write data */
+	out_be32(&regs->mdio_mwd, data);
+
+	out_be32(&regs->mdio_mcr, mdioctrlreg);
+
+	if (mdio_wait(dev))
+		return 1;
+
+	return 0;
+}
+
+/* Setting axi emac and phy to proper setting */
+static int setup_phy(struct eth_device *dev)
+{
+	u16 phyreg;
+	u32 i, speed, emmc_reg, ret;
+	struct axidma_priv *priv = dev->priv;
+	struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+	struct phy_device *phydev;
+
+	u32 supported = SUPPORTED_10baseT_Half |
+			SUPPORTED_10baseT_Full |
+			SUPPORTED_100baseT_Half |
+			SUPPORTED_100baseT_Full |
+			SUPPORTED_1000baseT_Half |
+			SUPPORTED_1000baseT_Full;
+
+	if (priv->phyaddr == -1) {
+		/* Detect the PHY address */
+		for (i = 31; i >= 0; i--) {
+			ret = phyread(dev, i, PHY_DETECT_REG, &phyreg);
+			if (!ret && (phyreg != 0xFFFF) &&
+			((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+				/* Found a valid PHY address */
+				priv->phyaddr = i;
+				debug("axiemac: Found valid phy address, %x\n",
+									phyreg);
+				break;
+			}
+		}
+	}
+
+	/* Interface - look at tsec */
+	phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
+
+	phydev->supported &= supported;
+	phydev->advertising = phydev->supported;
+	priv->phydev = phydev;
+	phy_config(phydev);
+	phy_startup(phydev);
+
+	switch (phydev->speed) {
+	case 1000:
+		speed = XAE_EMMC_LINKSPD_1000;
+		break;
+	case 100:
+		speed = XAE_EMMC_LINKSPD_100;
+		break;
+	case 10:
+		speed = XAE_EMMC_LINKSPD_10;
+		break;
+	default:
+		return 0;
+	}
+
+	/* Setup the emac for the phy speed */
+	emmc_reg = in_be32(&regs->emmc);
+	emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
+	emmc_reg |= speed;
+
+	/* Write new speed setting out to Axi Ethernet */
+	out_be32(&regs->emmc, emmc_reg);
+
+	/*
+	* Setting the operating speed of the MAC needs a delay. There
+	* doesn't seem to be register to poll, so please consider this
+	* during your application design.
+	*/
+	udelay(1);
+
+	return 1;
+}
+
+/* STOP DMA transfers */
+static void axiemac_halt(struct eth_device *dev)
+{
+	struct axidma_priv *priv = dev->priv;
+	u32 temp;
+
+	/* Stop the hardware */
+	temp = in_be32(&priv->dmatx->control);
+	temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
+	out_be32(&priv->dmatx->control, temp);
+
+	temp = in_be32(&priv->dmarx->control);
+	temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
+	out_be32(&priv->dmarx->control, temp);
+
+	debug("axiemac: Halted\n");
+}
+
+static int axi_ethernet_init(struct eth_device *dev)
+{
+	struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+	u32 timeout = 200;
+
+	/*
+	 * Check the status of the MgtRdy bit in the interrupt status
+	 * registers. This must be done to allow the MGT clock to become stable
+	 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
+	 * will be valid until this bit is valid.
+	 * The bit is always a 1 for all other PHY interfaces.
+	 */
+	while (timeout && (!(in_be32(&regs->is) & XAE_INT_MGTRDY_MASK))) {
+		timeout--;
+		udelay(1);
+	}
+	if (!timeout) {
+		printf("%s: Timeout\n", __func__);
+		return 1;
+	}
+
+	/* Stop the device and reset HW */
+	/* Disable interrupts */
+	out_be32(&regs->ie, 0);
+
+	/* Disable the receiver */
+	out_be32(&regs->rcw1, in_be32(&regs->rcw1) & ~XAE_RCW1_RX_MASK);
+
+	/*
+	 * Stopping the receiver in mid-packet causes a dropped packet
+	 * indication from HW. Clear it.
+	 */
+	/* Set the interrupt status register to clear the interrupt */
+	out_be32(&regs->is, XAE_INT_RXRJECT_MASK);
+
+	/* Setup HW */
+	/* Set default MDIO divisor */
+	out_be32(&regs->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
+
+	debug("axiemac: InitHw done\n");
+	return 0;
+}
+
+static int axiemac_setup_mac(struct eth_device *dev)
+{
+	struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+
+	/* Set the MAC address */
+	int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
+		(dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
+	out_be32(&regs->uaw0, val);
+
+	val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ;
+	val |= in_be32(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
+	out_be32(&regs->uaw1, val);
+	return 0;
+}
+
+/* Reset DMA engine */
+static void axi_dma_init(struct eth_device *dev)
+{
+	struct axidma_priv *priv = dev->priv;
+	u32 timeout = 500;
+
+	/* Reset the engine so the hardware starts from a known state */
+	out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
+	out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
+
+	/* At the initialization time, hardware should finish reset quickly */
+	while (timeout--) {
+		/* Check transmit/receive channel */
+		/* Reset is done when the reset bit is low */
+		if (!(in_be32(&priv->dmatx->control) |
+				in_be32(&priv->dmarx->control))
+						& XAXIDMA_CR_RESET_MASK) {
+			break;
+		}
+	}
+	if (!timeout)
+		printf("%s: Timeout\n", __func__);
+}
+
+static int axiemac_init(struct eth_device *dev, bd_t * bis)
+{
+	struct axidma_priv *priv = dev->priv;
+	struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+	u32 temp;
+
+	debug("axiemac: Init started\n");
+	/*
+	 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
+	 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
+	 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
+	 * would ensure a reset of AxiEthernet.
+	 */
+	axi_dma_init(dev);
+
+	/* Initialize AxiEthernet hardware. */
+	if (axi_ethernet_init(dev))
+		return -1;
+
+	/* Disable all RX interrupts before RxBD space setup */
+	temp = in_be32(&priv->dmarx->control);
+	temp &= ~XAXIDMA_IRQ_ALL_MASK;
+	out_be32(&priv->dmarx->control, temp);
+
+	/* Start DMA RX channel. Now it's ready to receive data.*/
+	out_be32(&priv->dmarx->current, (u32)&rx_bd);
+
+	/* Setup the BD. */
+	memset(&rx_bd, 0, sizeof(rx_bd));
+	rx_bd.next = (u32)&rx_bd;
+	rx_bd.phys = (u32)&rxframe;
+	rx_bd.cntrl = sizeof(rxframe);
+	/* Flush the last BD so DMA core could see the updates */
+	flush_cache((u32)&rx_bd, sizeof(rx_bd));
+
+	/* It is necessary to flush rxframe because if you don't do it
+	 * then cache can contain uninitialized data */
+	flush_cache((u32)&rxframe, sizeof(rxframe));
+
+	/* Start the hardware */
+	temp = in_be32(&priv->dmarx->control);
+	temp |= XAXIDMA_CR_RUNSTOP_MASK;
+	out_be32(&priv->dmarx->control, temp);
+
+	/* Rx BD is ready - start */
+	out_be32(&priv->dmarx->tail, (u32)&rx_bd);
+
+	/* Enable TX */
+	out_be32(&regs->tc, XAE_TC_TX_MASK);
+	/* Enable RX */
+	out_be32(&regs->rcw1, XAE_RCW1_RX_MASK);
+
+	/* PHY setup */
+	if (!setup_phy(dev)) {
+		axiemac_halt(dev);
+		return -1;
+	}
+
+	debug("axiemac: Init complete\n");
+	return 0;
+}
+
+static int axiemac_send(struct eth_device *dev, volatile void *ptr, int len)
+{
+	struct axidma_priv *priv = dev->priv;
+	u32 timeout;
+
+	if (len > PKTSIZE_ALIGN)
+		len = PKTSIZE_ALIGN;
+
+	/* Flush packet to main memory to be trasfered by DMA */
+	flush_cache((u32)ptr, len);
+
+	/* Setup Tx BD */
+	memset(&tx_bd, 0, sizeof(tx_bd));
+	/* At the end of the ring, link the last BD back to the top */
+	tx_bd.next = (u32)&tx_bd;
+	tx_bd.phys = (u32)ptr;
+	/* Save len */
+	tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
+						XAXIDMA_BD_CTRL_TXEOF_MASK;
+
+	/* Flush the last BD so DMA core could see the updates */
+	flush_cache((u32)&tx_bd, sizeof(tx_bd));
+
+	if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
+		u32 temp;
+		out_be32(&priv->dmatx->current, (u32)&tx_bd);
+		/* Start the hardware */
+		temp = in_be32(&priv->dmatx->control);
+		temp |= XAXIDMA_CR_RUNSTOP_MASK;
+		out_be32(&priv->dmatx->control, temp);
+	}
+
+	/* Start transfer */
+	out_be32(&priv->dmatx->tail, (u32)&tx_bd);
+
+	/* Wait for transmission to complete */
+	debug("axiemac: Waiting for tx to be done\n");
+	timeout = 200;
+	while (timeout && (!in_be32(&priv->dmatx->status) &
+			(XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
+		timeout--;
+		udelay(1);
+	}
+	if (!timeout) {
+		printf("%s: Timeout\n", __func__);
+		return 1;
+	}
+
+	debug("axiemac: Sending complete\n");
+	return 0;
+}
+
+static int isrxready(struct eth_device *dev)
+{
+	u32 status;
+	struct axidma_priv *priv = dev->priv;
+
+	/* Read pending interrupts */
+	status = in_be32(&priv->dmarx->status);
+
+	/* Acknowledge pending interrupts */
+	out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
+
+	/*
+	 * If Reception done interrupt is asserted, call RX call back function
+	 * to handle the processed BDs and then raise the according flag.
+	 */
+	if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
+		return 1;
+
+	return 0;
+}
+
+static int axiemac_recv(struct eth_device *dev)
+{
+	u32 length;
+	struct axidma_priv *priv = dev->priv;
+	u32 temp;
+
+	/* Wait for an incoming packet */
+	if (!isrxready(dev))
+		return 0;
+
+	debug("axiemac: RX data ready\n");
+
+	/* Disable IRQ for a moment till packet is handled */
+	temp = in_be32(&priv->dmarx->control);
+	temp &= ~XAXIDMA_IRQ_ALL_MASK;
+	out_be32(&priv->dmarx->control, temp);
+
+	length = rx_bd.app4 & 0xFFFF; /* max length mask */
+#ifdef DEBUG
+	print_buffer(&rxframe, &rxframe[0], 1, length, 16);
+#endif
+	/* Pass the received frame up for processing */
+	if (length)
+		NetReceive(rxframe, length);
+
+#ifdef DEBUG
+	/* It is useful to clear buffer to be sure that it is consistent */
+	memset(rxframe, 0, sizeof(rxframe));
+#endif
+	/* Setup RxBD */
+	/* Clear the whole buffer and setup it again - all flags are cleared */
+	memset(&rx_bd, 0, sizeof(rx_bd));
+	rx_bd.next = (u32)&rx_bd;
+	rx_bd.phys = (u32)&rxframe;
+	rx_bd.cntrl = sizeof(rxframe);
+
+	/* Write bd to HW */
+	flush_cache((u32)&rx_bd, sizeof(rx_bd));
+
+	/* It is necessary to flush rxframe because if you don't do it
+	 * then cache will contain previous packet */
+	flush_cache((u32)&rxframe, sizeof(rxframe));
+
+	/* Rx BD is ready - start again */
+	out_be32(&priv->dmarx->tail, (u32)&rx_bd);
+
+	debug("axiemac: RX completed, framelength = %d\n", length);
+
+	return length;
+}
+
+static int axiemac_miiphy_read(const char *devname, uchar addr,
+							uchar reg, ushort *val)
+{
+	struct eth_device *dev = eth_get_dev();
+	u32 ret;
+
+	ret = phyread(dev, addr, reg, val);
+	debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
+	return ret;
+}
+
+static int axiemac_miiphy_write(const char *devname, uchar addr,
+							uchar reg, ushort val)
+{
+	struct eth_device *dev = eth_get_dev();
+
+	debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
+	return phywrite(dev, addr, reg, val);
+}
+
+static int axiemac_bus_reset(struct mii_dev *bus)
+{
+	debug("axiemac: Bus reset\n");
+	return 0;
+}
+
+int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
+							unsigned long dma_addr)
+{
+	struct eth_device *dev;
+	struct axidma_priv *priv;
+
+	dev = calloc(1, sizeof(struct eth_device));
+	if (dev == NULL)
+		return -1;
+
+	dev->priv = calloc(1, sizeof(struct axidma_priv));
+	if (dev->priv == NULL) {
+		free(dev);
+		return -1;
+	}
+	priv = dev->priv;
+
+	sprintf(dev->name, "aximac.%lx", base_addr);
+
+	dev->iobase = base_addr;
+	priv->dmatx = (struct axidma_reg *)dma_addr;
+	/* RX channel offset is 0x30 */
+	priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30);
+	dev->init = axiemac_init;
+	dev->halt = axiemac_halt;
+	dev->send = axiemac_send;
+	dev->recv = axiemac_recv;
+	dev->write_hwaddr = axiemac_setup_mac;
+
+#ifdef CONFIG_PHY_ADDR
+	priv->phyaddr = CONFIG_PHY_ADDR;
+#else
+	priv->phyaddr = -1;
+#endif
+
+	eth_register(dev);
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
+	miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write);
+	priv->bus = miiphy_get_dev_by_name(dev->name);
+	priv->bus->reset = axiemac_bus_reset;
+#endif
+	return 1;
+}
diff --git a/include/netdev.h b/include/netdev.h
index 8b71011..f9bbe65 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -94,6 +94,8 @@ int smc911x_initialize(u8 dev_num, int base_addr);
 int tsi108_eth_initialize(bd_t *bis);
 int uec_standard_init(bd_t *bis);
 int uli526x_initialize(bd_t *bis);
+int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
+							unsigned long dma_addr);
 int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
 							int txpp, int rxpp);
 
-- 
1.5.5.6

[U-Boot] [PATCH 26/26] microblaze: Wire up axi_ethernet driver initialization

[Michal Simek]

Initialize axi_ethernet driver.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---
 .../xilinx/microblaze-generic/microblaze-generic.c |    6 ++++++
 include/configs/microblaze-generic.h               |    4 ++++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index 9b2952f..c4c13a6 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -72,6 +72,12 @@ int fsl_init2 (void) {
 int board_eth_init(bd_t *bis)
 {
 	int ret = 0;
+
+#ifdef CONFIG_XILINX_AXIEMAC
+	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+						XILINX_AXIDMA_BASEADDR);
+#endif
+
 #ifdef CONFIG_XILINX_EMACLITE
 	u32 txpp = 0;
 	u32 rxpp = 0;
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index c526006..f010169 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -70,6 +70,10 @@
 # define CONFIG_XILINX_LL_TEMAC		1
 # define CONFIG_SYS_ENET
 #endif
+#if defined(XILINX_AXIEMAC_BASEADDR)
+# define CONFIG_XILINX_AXIEMAC	1
+# define CONFIG_SYS_ENET
+#endif
 
 #undef ET_DEBUG
 
-- 
1.5.5.6

[U-Boot] [PATCH 23/26] serial: uartlite: Support for SERIAL_MULTI

[Mike Frysinger]

On Tuesday, September 13, 2011 03:10:18 Michal Simek wrote:
> +static struct uartlite *userial_ports[4] = {

pretty sure this should be:
	static struct uartlite * const userial_ports[4] = {

> +#ifdef XILINX_UARTLITE_BASEADDR
> +	(struct uartlite *)XILINX_UARTLITE_BASEADDR,
> +#else
> +	NULL,
> +#endif

simpler code:
#ifdef XILINX_UARTLITE_BASEADDR
	[0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
#endif
-mike
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[U-Boot] [PATCH 12/26] microblaze: Support flashes on lower addresses

[Mike Frysinger]

On Tuesday, September 13, 2011 03:10:07 Michal Simek wrote:
> --- a/arch/microblaze/include/asm/processor.h
> +++ b/arch/microblaze/include/asm/processor.h
> @@ -1 +1,4 @@
> -/* FIXME: Implement this! */
> +
> +/* References to section boundaries */
> +extern char __end[];
> +extern char __text_start[];

should have proper #ifdef protection against multiple inclusion, and be nice 
to have a copyright/license comment block.
-mike
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[U-Boot] [PATCH 12/26] microblaze: Support flashes on lower addresses

[Michal Simek]

Mike Frysinger wrote:
> On Tuesday, September 13, 2011 03:10:07 Michal Simek wrote:
>> --- a/arch/microblaze/include/asm/processor.h
>> +++ b/arch/microblaze/include/asm/processor.h
>> @@ -1 +1,4 @@
>> -/* FIXME: Implement this! */
>> +
>> +/* References to section boundaries */
>> +extern char __end[];
>> +extern char __text_start[];
> 
> should have proper #ifdef protection against multiple inclusion, and be nice 
> to have a copyright/license comment block.

Fixed.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 11/26] microblaze: Support CTRL+C when tftp is running

[Mike Frysinger]

On Tuesday, September 13, 2011 03:10:06 Michal Simek wrote:
> Signed-off-by: Michal Simek <monstr@monstr.eu>
> ---
>  arch/microblaze/lib/board.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
> index d97543b..5510c12 100644
> --- a/arch/microblaze/lib/board.c
> +++ b/arch/microblaze/lib/board.c
> @@ -68,6 +68,7 @@ typedef int (init_fnc_t) (void);
>  init_fnc_t *init_sequence[] = {
>  	env_init,
>  	serial_init,
> +	console_init_f,
>  #ifdef CONFIG_SYS_GPIO_0
>  	gpio_init,
>  #endif

the summary/changelog is still confusing here.  what i'd use is:
microblaze: call common console_init_f initialization function

All arches are supposed to call the common console_init_f func when setting 
things up.  If we don't, code like tftp and netconsole don't operate 
correctly.
-mike
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[U-Boot] [PATCH 11/26] microblaze: Support CTRL+C when tftp is running

[Mike Frysinger]

On Tuesday, September 13, 2011 13:33:57 Mike Frysinger wrote:
> the summary/changelog is still confusing here

sorry, i was thinking of "microblaze: Initialize jumptable and console".  but 
my suggestion mostly still stands.
-mike
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[U-Boot] [PATCH 11/26] microblaze: Support CTRL+C when tftp is running

[Michal Simek]

Mike Frysinger wrote:
> On Tuesday, September 13, 2011 03:10:06 Michal Simek wrote:
>> Signed-off-by: Michal Simek <monstr@monstr.eu>
>> ---
>>  arch/microblaze/lib/board.c |    1 +
>>  1 files changed, 1 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
>> index d97543b..5510c12 100644
>> --- a/arch/microblaze/lib/board.c
>> +++ b/arch/microblaze/lib/board.c
>> @@ -68,6 +68,7 @@ typedef int (init_fnc_t) (void);
>>  init_fnc_t *init_sequence[] = {
>>  	env_init,
>>  	serial_init,
>> +	console_init_f,
>>  #ifdef CONFIG_SYS_GPIO_0
>>  	gpio_init,
>>  #endif
> 
> the summary/changelog is still confusing here.  what i'd use is:
> microblaze: call common console_init_f initialization function

Fixed

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] Microblaze/Xilinx drivers changes

[Wolfgang Denk]

Dear Michal Simek,

In message <1315897821-23049-1-git-send-email-monstr@monstr.eu> you wrote:
> 
> here is the whole package with Microblaze and Xilinx driver changes.
> All patches are available in git://www.denx.de/git/u-boot-microblaze.git master branch
> if you like to test them.

Arghhh.  No.  It does not work like that. And you should know it, I've
told you before.

This is not a new set of patches, some of them have been posted, and
reviewd, before.  Yet you fail to mention this in any way: there is no
"V2" or so in the Subject: lines, nor is there any comment of hwat you
changed compared to the initial submission.


I am not going to compare all this stuff myself.


Full NAK to the whole series, without even looking at it.

Please stick to the rules.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Where would we be without rhetorical questions?

[U-Boot] Microblaze/Xilinx drivers changes

[Michal Simek]

Dear Wolfgang Denk,

> In message <1315897821-23049-1-git-send-email-monstr@monstr.eu> you wrote:
>> here is the whole package with Microblaze and Xilinx driver changes.
>> All patches are available in git://www.denx.de/git/u-boot-microblaze.git master branch
>> if you like to test them.
> 
> Arghhh.  No.  It does not work like that. And you should know it, I've
> told you before.
> 
> This is not a new set of patches, some of them have been posted, and
> reviewd, before.  Yet you fail to mention this in any way: there is no
> "V2" or so in the Subject: lines, nor is there any comment of hwat you
> changed compared to the initial submission.

True that I haven't change subject for patches but version changes are in every patch.
Some of them weren't commented that's why they are just resent.

If you like, I can add version string to subject in every patch and write resent for patches
which weren't commented.

Regards,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] Microblaze/Xilinx drivers changes

[Marek Vasut]

On Tuesday, September 13, 2011 01:16:12 PM Michal Simek wrote:
> Dear Wolfgang Denk,
> 
> > In message <1315897821-23049-1-git-send-email-monstr@monstr.eu> you wrote:
> >> here is the whole package with Microblaze and Xilinx driver changes.
> >> All patches are available in git://www.denx.de/git/u-boot-microblaze.git
> >> master branch if you like to test them.
> > 
> > Arghhh.  No.  It does not work like that. And you should know it, I've
> > told you before.
> > 
> > This is not a new set of patches, some of them have been posted, and
> > reviewd, before.  Yet you fail to mention this in any way: there is no
> > "V2" or so in the Subject: lines, nor is there any comment of hwat you
> > changed compared to the initial submission.
> 
> True that I haven't change subject for patches but version changes are in
> every patch. Some of them weren't commented that's why they are just
> resent.

Please read:
http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions

> 
> If you like, I can add version string to subject in every patch and write
> resent for patches which weren't commented.
> 
> Regards,
> Michal

[U-Boot] Microblaze/Xilinx drivers changes

[Michal Simek]

Marek Vasut wrote:
> On Tuesday, September 13, 2011 01:16:12 PM Michal Simek wrote:
>> Dear Wolfgang Denk,
>>
>>> In message <1315897821-23049-1-git-send-email-monstr@monstr.eu> you wrote:
>>>> here is the whole package with Microblaze and Xilinx driver changes.
>>>> All patches are available in git://www.denx.de/git/u-boot-microblaze.git
>>>> master branch if you like to test them.
>>> Arghhh.  No.  It does not work like that. And you should know it, I've
>>> told you before.
>>>
>>> This is not a new set of patches, some of them have been posted, and
>>> reviewd, before.  Yet you fail to mention this in any way: there is no
>>> "V2" or so in the Subject: lines, nor is there any comment of hwat you
>>> changed compared to the initial submission.
>> True that I haven't change subject for patches but version changes are in
>> every patch. Some of them weren't commented that's why they are just
>> resent.
> 
> Please read:
> http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions

What about patch resubmit or resend?

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] Microblaze/Xilinx drivers changes

[Marek Vasut]

On Tuesday, September 13, 2011 03:35:15 PM Michal Simek wrote:
> Marek Vasut wrote:
> > On Tuesday, September 13, 2011 01:16:12 PM Michal Simek wrote:
> >> Dear Wolfgang Denk,
> >> 
> >>> In message <1315897821-23049-1-git-send-email-monstr@monstr.eu> you wrote:
> >>>> here is the whole package with Microblaze and Xilinx driver changes.
> >>>> All patches are available in
> >>>> git://www.denx.de/git/u-boot-microblaze.git master branch if you like
> >>>> to test them.
> >>> 
> >>> Arghhh.  No.  It does not work like that. And you should know it, I've
> >>> told you before.
> >>> 
> >>> This is not a new set of patches, some of them have been posted, and
> >>> reviewd, before.  Yet you fail to mention this in any way: there is no
> >>> "V2" or so in the Subject: lines, nor is there any comment of hwat you
> >>> changed compared to the initial submission.
> >> 
> >> True that I haven't change subject for patches but version changes are
> >> in every patch. Some of them weren't commented that's why they are just
> >> resent.
> > 
> > Please read:
> > http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_version
> > s
> 
> What about patch resubmit or resend?

Add [PATCH x/y RESEND] to the header.

Cheers
> 
> Thanks,
> Michal

[U-Boot] Microblaze/Xilinx drivers changes

[Wolfgang Denk]

Dear Michal Simek,

In message <4E6F5C13.3000005@monstr.eu> you wrote:
>
> > Please read:
> > http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
> 
> What about patch resubmit or resend?

Resending unchanged patches should be avoided, if possible.  First, it
just wastes bandwith and storage space.  Second (and more important),
PatchWork has problems with this: it locates patcehs based on their
hashes, and for reposted patches, it will always find the _oldest_
matching patch.  So even if we set N-1 of your repostings to
"Superseded" or similar, Patchwork will set the oldest of these as
"Accepted" and your Nth posting remains in state "New".

[Only the body of the patch is relevant here, so even postings of the
same patch by different people or with changed commit messages will be
handled like that.]


So only resend when you have large series of patches with very few
unchanged patches in them.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"It may be that our role on this planet is not to worship God but  to
create him."                                       - Arthur C. Clarke

[U-Boot] Microblaze/Xilinx drivers changes

[Michal Simek]

Wolfgang Denk wrote:
> Dear Michal Simek,
> 
> In message <4E6F5C13.3000005@monstr.eu> you wrote:
>>> Please read:
>>> http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
>> What about patch resubmit or resend?
> 
> Resending unchanged patches should be avoided, if possible.  First, it
> just wastes bandwith and storage space.  Second (and more important),
> PatchWork has problems with this: it locates patcehs based on their
> hashes, and for reposted patches, it will always find the _oldest_
> matching patch.  So even if we set N-1 of your repostings to
> "Superseded" or similar, Patchwork will set the oldest of these as
> "Accepted" and your Nth posting remains in state "New".
> 
> [Only the body of the patch is relevant here, so even postings of the
> same patch by different people or with changed commit messages will be
> handled like that.]
> 
> 
> So only resend when you have large series of patches with very few
> unchanged patches in them.

ok. Let's look at it.

I my repo are 4 patch series.
1. emaclite: 10 patches. At least 6 will be resubmit.
http://patchwork.ozlabs.org/patch/111768/
http://patchwork.ozlabs.org/patch/111769/
http://patchwork.ozlabs.org/patch/111770/
http://patchwork.ozlabs.org/patch/111771/

Probably not possible to apply because of v2 in 111772
http://patchwork.ozlabs.org/patch/111773/
http://patchwork.ozlabs.org/patch/111775/

2. microblaze series - 4 resubmits
http://patchwork.ozlabs.org/patch/112528/
http://patchwork.ozlabs.org/patch/112529/
http://patchwork.ozlabs.org/patch/112530/ - depend on patch from emaclite series not functional - just to avoid conflict
http://patchwork.ozlabs.org/patch/112531/

+ 3 patches which I can't see on patchwork but can see it on mailing list.

3. serial multi uartlite v3 required - 1 resubmit
+ http://patchwork.ozlabs.org/patch/113567/ - wire up for MB

4. axi ethernet v3 required - 1 resubmit
+ http://patchwork.ozlabs.org/patch/112533/ - wire up for MB


Series 3 and 4 should go together because the first patch must be driver change and then MB changes.

ok. Can I delegate patches through patchwork which are not review and probably should be reviewed or applied?
Or change subjects for every patch if is new version or resend?


Regards,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian