[U-Boot] [PATCH 1/2] powerpc/p2041rdb: updated description of cpld command

[U-Boot] [PATCH 1/2] powerpc/p2041rdb: updated description of cpld command

[Kumar Gala]

From: Shaohui Xie <Shaohui.Xie@freescale.com>

According to CPLD 2.2, the default configuration is changed, so updated the
description of CPLD command, otherwise it will confusing.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/p2041rdb/cpld.c |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c
index 37b0ed5..2ad89a8 100644
--- a/board/freescale/p2041rdb/cpld.c
+++ b/board/freescale/p2041rdb/cpld.c
@@ -159,14 +159,14 @@ U_BOOT_CMD(
 	"cpld_cmd watchdog <watchdog_period> - set the watchdog period\n"
 	"	period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n"
 	"cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
-	"	lane 6: 0 -> slot1 (Default)\n"
-	"		1 -> SGMII\n"
-	"	lane a: 0 -> slot2 (Default)\n"
-	"		1 -> AURORA\n"
-	"	lane c: 0 -> slot2 (Default)\n"
-	"		1 -> SATA0\n"
-	"	lane d: 0 -> slot2 (Default)\n"
-	"		1 -> SATA1\n"
+	"	lane 6: 0 -> slot1\n"
+	"		1 -> SGMII (Default)\n"
+	"	lane a: 0 -> slot2\n"
+	"		1 -> AURORA (Default)\n"
+	"	lane c: 0 -> slot2\n"
+	"		1 -> SATA0 (Default)\n"
+	"	lane d: 0 -> slot2\n"
+	"		1 -> SATA1 (Default)\n"
 #ifdef DEBUG
 	"cpld_cmd dump - display the CPLD registers\n"
 #endif
-- 
1.7.3.4

[U-Boot] [PATCH 2/2] powerpc/p2041rdb: remove watch dog related codes

[Kumar Gala]

From: Shaohui Xie <Shaohui.Xie@freescale.com>

CPLD 2.2 removed board watch dog support due to the limitation of CPLD
capacity after adding all the requested features, such as switch overriding.
There is no pin-compatible upgrade part available for current PCB design.
So remove codes related to it.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/p2041rdb/cpld.c |   11 -----------
 board/freescale/p2041rdb/cpld.h |    2 +-
 2 files changed, 1 insertions(+), 12 deletions(-)

diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c
index 2ad89a8..a4bcc18 100644
--- a/board/freescale/p2041rdb/cpld.c
+++ b/board/freescale/p2041rdb/cpld.c
@@ -79,7 +79,6 @@ static void cpld_dump_regs(void)
 	printf("cpld_ver_sub	= 0x%02x\n", CPLD_READ(cpld_ver_sub));
 	printf("pcba_ver	= 0x%02x\n", CPLD_READ(pcba_ver));
 	printf("system_rst	= 0x%02x\n", CPLD_READ(system_rst));
-	printf("wd_cfg		= 0x%02x\n", CPLD_READ(wd_cfg));
 	printf("sw_ctl_on	= 0x%02x\n", CPLD_READ(sw_ctl_on));
 	printf("por_cfg		= 0x%02x\n", CPLD_READ(por_cfg));
 	printf("switch_strobe	= 0x%02x\n", CPLD_READ(switch_strobe));
@@ -96,7 +95,6 @@ static void cpld_dump_regs(void)
 int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int rc = 0;
-	unsigned int i;
 
 	if (argc <= 1)
 		return cmd_usage(cmdtp);
@@ -106,13 +104,6 @@ int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			cpld_set_altbank();
 		else
 			cpld_set_defbank();
-	} else if (strcmp(argv[1], "watchdog") == 0) {
-		static char *period[8] = {"1ms", "10ms", "30ms", "disable",
-			"100ms", "1s", "10s", "60s"};
-		for (i = 0; i < ARRAY_SIZE(period); i++) {
-			if (strcmp(argv[2], period[i]) == 0)
-				CPLD_WRITE(wd_cfg, i);
-		}
 	} else if (strcmp(argv[1], "lane_mux") == 0) {
 		u32 lane = simple_strtoul(argv[2], NULL, 16);
 		u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
@@ -156,8 +147,6 @@ U_BOOT_CMD(
 	"Reset the board or pin mulexing selection using the CPLD sequencer",
 	"reset - hard reset to default bank\n"
 	"cpld_cmd reset altbank - reset to alternate bank\n"
-	"cpld_cmd watchdog <watchdog_period> - set the watchdog period\n"
-	"	period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n"
 	"cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
 	"	lane 6: 0 -> slot1\n"
 	"		1 -> SGMII (Default)\n"
diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h
index bece5dd..2e3e7b1 100644
--- a/board/freescale/p2041rdb/cpld.h
+++ b/board/freescale/p2041rdb/cpld.h
@@ -19,7 +19,7 @@ typedef struct cpld_data {
 	u8 cpld_ver_sub;	/* 0x1 - CPLD Minor Revision Register */
 	u8 pcba_ver;		/* 0x2 - PCBA Revision Register */
 	u8 system_rst;		/* 0x3 - system reset register */
-	u8 wd_cfg;		/* 0x4 - Watchdog Period Setting Register */
+	u8 res0;		/* 0x4 - not used */
 	u8 sw_ctl_on;		/* 0x5 - Switch Control Enable Register */
 	u8 por_cfg;		/* 0x6 - POR Control Register */
 	u8 switch_strobe;	/* 0x7 - Multiplexed pin Select Register */
-- 
1.7.3.4

[U-Boot] [PATCH 1/2] powerpc/p2041rdb: updated description of cpld command

[Kumar Gala]

On Sep 23, 2011, at 12:54 PM, Kumar Gala wrote:

> From: Shaohui Xie <Shaohui.Xie@freescale.com>
> 
> According to CPLD 2.2, the default configuration is changed, so updated the
> description of CPLD command, otherwise it will confusing.
> 
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/p2041rdb/cpld.c |   16 ++++++++--------
> 1 files changed, 8 insertions(+), 8 deletions(-)

applied to 85xx

- k

[U-Boot] [PATCH 2/2] powerpc/p2041rdb: remove watch dog related codes

[Kumar Gala]

On Sep 23, 2011, at 12:54 PM, Kumar Gala wrote:

> From: Shaohui Xie <Shaohui.Xie@freescale.com>
> 
> CPLD 2.2 removed board watch dog support due to the limitation of CPLD
> capacity after adding all the requested features, such as switch overriding.
> There is no pin-compatible upgrade part available for current PCB design.
> So remove codes related to it.
> 
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/p2041rdb/cpld.c |   11 -----------
> board/freescale/p2041rdb/cpld.h |    2 +-
> 2 files changed, 1 insertions(+), 12 deletions(-)

applied to 85xx

- k