* [Qemu-devel] [PATCH 0/7] MIPS64 user mode emulation in QEMU with Cavium specific instruction support
@ 2011-09-27 4:17 khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 1/7] linux-user:Support for MIPS64 user mode emulation in QEMU khansa
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: khansa @ 2011-09-27 4:17 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, riku.voipio, Khansa Butt, aurelien
From: Khansa Butt <khansa@kics.edu.pk>
This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt
from HPCN Lab KICS UET Lahore.
This Patch series add support of MIPS64 user mode emulation in QEMU.
Along with we implemented Cavium specific instructions which We will use
in SME (in sysem mode emulation of Octeon processor)
If you have any objection regarding the Implementation of
Cavium instructions please read following notes.
Notes
*****
The detail of some instructions are as follows
1)seq rd,rs,rt
seq-->rd = 1 if rs = rt
is equivalent to
xor rd,rs,rt
sltiu rd,rd,1
2)exts rt,rs,p,lenm1
rt = sign-extend(rs<p+lenm1:p>,lenm1)
>From reference manual of Cavium Networks
"Bit locations p + lenm1 to p are extracted from rs and the result is written into the
lowest bits of destination register rt. The remaining bits in rt are a sign-extension of
the most-significant bit of the bit field (i.e. rt<63:lenm1> are all duplicates of the
source-register bit rs<p+lenm1>)." so we can't use any of 8,16 or 32 bit
sign extention tcg function. To sign extend according to msb of bit field
we have our own implementation
3)dmul rd,rs,rt
This instruction is included in gen_arith() because it is three operand
double word multiply instruction.
--
1.7.3.4
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 1/7] linux-user:Support for MIPS64 user mode emulation in QEMU
2011-09-27 4:17 [Qemu-devel] [PATCH 0/7] MIPS64 user mode emulation in QEMU with Cavium specific instruction support khansa
@ 2011-09-27 4:17 ` khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 2/7] target-mips:enabling of 64 bit user mode and floating point operations khansa
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: khansa @ 2011-09-27 4:17 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, riku.voipio, Khansa Butt, aurelien
From: Khansa Butt <khansa@kics.edu.pk>
Signed-off-by: Khansa Butt <khansa@kics.edu.pk>
---
configure | 1 +
default-configs/mips64-linux-user.mak | 1 +
linux-user/main.c | 21 +++++++++++++++++++--
linux-user/mips64/syscall.h | 2 ++
linux-user/signal.c | 2 --
5 files changed, 23 insertions(+), 4 deletions(-)
create mode 100644 default-configs/mips64-linux-user.mak
diff --git a/configure b/configure
index 9ab3ab4..5e45a43 100755
--- a/configure
+++ b/configure
@@ -891,6 +891,7 @@ m68k-linux-user \
microblaze-linux-user \
microblazeel-linux-user \
mips-linux-user \
+mips64-linux-user \
mipsel-linux-user \
ppc-linux-user \
ppc64-linux-user \
diff --git a/default-configs/mips64-linux-user.mak b/default-configs/mips64-linux-user.mak
new file mode 100644
index 0000000..1598bfc
--- /dev/null
+++ b/default-configs/mips64-linux-user.mak
@@ -0,0 +1 @@
+# Default configuration for mips64-linux-user
diff --git a/linux-user/main.c b/linux-user/main.c
index 89a51d7..1cc564d 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -2068,7 +2068,8 @@ static int do_store_exclusive(CPUMIPSState *env)
void cpu_loop(CPUMIPSState *env)
{
target_siginfo_t info;
- int trapnr, ret;
+ int trapnr;
+ abi_long ret;
unsigned int syscall_num;
for(;;) {
@@ -2077,8 +2078,23 @@ void cpu_loop(CPUMIPSState *env)
cpu_exec_end(env);
switch(trapnr) {
case EXCP_SYSCALL:
- syscall_num = env->active_tc.gpr[2] - 4000;
env->active_tc.PC += 4;
+#if defined(TARGET_MIPS64)
+ syscall_num = env->active_tc.gpr[2] - 5000;
+ /* MIPS64 has eight argument registers so there is
+ * no need to get arguments from stack
+ */
+ ret = do_syscall(env, env->active_tc.gpr[2],
+ env->active_tc.gpr[4],
+ env->active_tc.gpr[5],
+ env->active_tc.gpr[6],
+ env->active_tc.gpr[7],
+ env->active_tc.gpr[8],
+ env->active_tc.gpr[9],
+ env->active_tc.gpr[10],
+ env->active_tc.gpr[11]);
+#else
+ syscall_num = env->active_tc.gpr[2] - 4000;
if (syscall_num >= sizeof(mips_syscall_args)) {
ret = -TARGET_ENOSYS;
} else {
@@ -2105,6 +2121,7 @@ void cpu_loop(CPUMIPSState *env)
env->active_tc.gpr[7],
arg5, arg6, arg7, arg8);
}
+#endif
if (ret == -TARGET_QEMU_ESIGRETURN) {
/* Returning from a successful sigreturn syscall.
Avoid clobbering register state. */
diff --git a/linux-user/mips64/syscall.h b/linux-user/mips64/syscall.h
index 668a2b9..96f03da 100644
--- a/linux-user/mips64/syscall.h
+++ b/linux-user/mips64/syscall.h
@@ -218,4 +218,6 @@ struct target_pt_regs {
+#define TARGET_QEMU_ESIGRETURN 255
+
#define UNAME_MACHINE "mips64"
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 89276eb..59c3c88 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -2415,8 +2415,6 @@ void sparc64_get_context(CPUSPARCState *env)
#endif
#elif defined(TARGET_ABI_MIPSN64)
-# warning signal handling not implemented
-
static void setup_frame(int sig, struct target_sigaction *ka,
target_sigset_t *set, CPUState *env)
{
--
1.7.3.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 2/7] target-mips:enabling of 64 bit user mode and floating point operations
2011-09-27 4:17 [Qemu-devel] [PATCH 0/7] MIPS64 user mode emulation in QEMU with Cavium specific instruction support khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 1/7] linux-user:Support for MIPS64 user mode emulation in QEMU khansa
@ 2011-09-27 4:17 ` khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 3/7] linux-user:Signal handling for MIPS64 khansa
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: khansa @ 2011-09-27 4:17 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, riku.voipio, Khansa Butt, aurelien
From: Khansa Butt <khansa@kics.edu.pk>
Signed-off-by: Khansa Butt <khansa@kics.edu.pk>
---
target-mips/translate.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d5b1c76..0550333 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12779,6 +12779,8 @@ void cpu_reset (CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_FPU;
}
#ifdef TARGET_MIPS64
+ env->hflags |= MIPS_HFLAG_UX;
+ env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
env->hflags |= MIPS_HFLAG_F64;
}
--
1.7.3.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 3/7] linux-user:Signal handling for MIPS64
2011-09-27 4:17 [Qemu-devel] [PATCH 0/7] MIPS64 user mode emulation in QEMU with Cavium specific instruction support khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 1/7] linux-user:Support for MIPS64 user mode emulation in QEMU khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 2/7] target-mips:enabling of 64 bit user mode and floating point operations khansa
@ 2011-09-27 4:17 ` khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 4/7] target-mips:Octeon cpu definition khansa
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: khansa @ 2011-09-27 4:17 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, riku.voipio, Khansa Butt, aurelien
From: Khansa Butt <khansa@kics.edu.pk>
Signed-off-by: Khansa Butt <khansa@kics.edu.pk>
---
linux-user/signal.c | 438 +++++++++++++++++++++++++++++++++++++++++++++++++--
1 files changed, 426 insertions(+), 12 deletions(-)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 59c3c88..f5f8bba 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -30,6 +30,8 @@
#include "qemu-common.h"
#include "target_signal.h"
+int sigrt;
+
//#define DEBUG_SIGNAL
static struct target_sigaltstack target_sigaltstack_used = {
@@ -596,7 +598,11 @@ int do_sigaction(int sig, const struct target_sigaction *act,
if (act) {
/* FIXME: This is not threadsafe. */
k->_sa_handler = tswapl(act->_sa_handler);
+#if defined(TARGET_MIPS64)
+ k->sa_flags = bswap32(act->sa_flags);
+#else
k->sa_flags = tswapl(act->sa_flags);
+#endif
#if !defined(TARGET_MIPS)
k->sa_restorer = tswapl(act->sa_restorer);
#endif
@@ -2415,29 +2421,435 @@ void sparc64_get_context(CPUSPARCState *env)
#endif
#elif defined(TARGET_ABI_MIPSN64)
+struct target_sigcontext {
+ uint32_t sc_regmask; /* Unused */
+ uint32_t sc_status;
+ uint64_t sc_pc;
+ uint64_t sc_regs[32];
+ uint64_t sc_fpregs[32];
+ uint32_t sc_ownedfp; /* Unused */
+ uint32_t sc_fpc_csr;
+ uint32_t sc_fpc_eir; /* Unused */
+ uint32_t sc_used_math;
+ uint32_t sc_dsp; /* dsp status, was sc_ssflags */
+ uint32_t pad0;
+ uint64_t sc_mdhi;
+ uint64_t sc_mdlo;
+ target_ulong sc_hi1; /* Was sc_cause */
+ target_ulong sc_lo1; /* Was sc_badvaddr */
+ target_ulong sc_hi2; /* Was sc_sigset[4] */
+ target_ulong sc_lo2;
+ target_ulong sc_hi3;
+ target_ulong sc_lo3;
+};
+
+struct sigframe {
+ uint32_t sf_ass[4]; /* argument save space for o32 */
+ uint32_t sf_code[2]; /* signal trampoline */
+ struct target_sigcontext sf_sc;
+ target_sigset_t sf_mask;
+};
+
+struct target_ucontext {
+ target_ulong tuc_flags;
+ target_ulong tuc_link;
+ target_stack_t tuc_stack;
+ target_ulong pad0;
+ struct target_sigcontext tuc_mcontext;
+ target_sigset_t tuc_sigmask;
+};
+
+struct target_rt_sigframe {
+ uint32_t rs_ass[4]; /* argument save space for o32 */
+ uint32_t rs_code[2]; /* signal trampoline */
+ struct target_siginfo rs_info;
+ struct target_ucontext rs_uc;
+};
+
+/* Install trampoline to jump back from signal handler */
+static inline int install_sigtramp(unsigned int *tramp, unsigned int syscall)
+{
+ int err;
+
+ /*
+ * Set up the return code ...
+ *
+ * li v0, __NR__foo_sigreturn
+ * syscall
+ */
+
+ err = __put_user(0x24020000 + syscall, tramp + 0);
+ err |= __put_user(0x0000000c , tramp + 1);
+ /* flush_cache_sigtramp((unsigned long) tramp); */
+ return err;
+}
+
+static inline int
+setup_sigcontext(CPUState *regs, struct target_sigcontext *sc)
+{
+ int err = 0;
+
+ err |= __put_user(regs->active_tc.PC, &sc->sc_pc);
+
+#define save_gp_reg(i) do { \
+ err |= __put_user(regs->active_tc.gpr[i], &sc->sc_regs[i]); \
+} while (0)
+ __put_user(0, &sc->sc_regs[0]); save_gp_reg(1); save_gp_reg(2);
+ save_gp_reg(3); save_gp_reg(4); save_gp_reg(5); save_gp_reg(6);
+ save_gp_reg(7); save_gp_reg(8); save_gp_reg(9); save_gp_reg(10);
+ save_gp_reg(11); save_gp_reg(12); save_gp_reg(13); save_gp_reg(14);
+ save_gp_reg(15); save_gp_reg(16); save_gp_reg(17); save_gp_reg(18);
+ save_gp_reg(19); save_gp_reg(20); save_gp_reg(21); save_gp_reg(22);
+ save_gp_reg(23); save_gp_reg(24); save_gp_reg(25); save_gp_reg(26);
+ save_gp_reg(27); save_gp_reg(28); save_gp_reg(29); save_gp_reg(30);
+ save_gp_reg(31);
+#undef save_gp_reg
+
+ err |= __put_user(regs->active_tc.HI[0], &sc->sc_mdhi);
+ err |= __put_user(regs->active_tc.LO[0], &sc->sc_mdlo);
+
+ /* Not used yet, but might be useful if we ever have DSP suppport */
+#if 0
+ if (cpu_has_dsp) {
+ err |= __put_user(mfhi1(), &sc->sc_hi1);
+ err |= __put_user(mflo1(), &sc->sc_lo1);
+ err |= __put_user(mfhi2(), &sc->sc_hi2);
+ err |= __put_user(mflo2(), &sc->sc_lo2);
+ err |= __put_user(mfhi3(), &sc->sc_hi3);
+ err |= __put_user(mflo3(), &sc->sc_lo3);
+ err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
+ }
+ /* same with 64 bit */
+#ifdef CONFIG_64BIT
+ err |= __put_user(regs->hi, &sc->sc_hi[0]);
+ err |= __put_user(regs->lo, &sc->sc_lo[0]);
+ if (cpu_has_dsp) {
+ err |= __put_user(mfhi1(), &sc->sc_hi[1]);
+ err |= __put_user(mflo1(), &sc->sc_lo[1]);
+ err |= __put_user(mfhi2(), &sc->sc_hi[2]);
+ err |= __put_user(mflo2(), &sc->sc_lo[2]);
+ err |= __put_user(mfhi3(), &sc->sc_hi[3]);
+ err |= __put_user(mflo3(), &sc->sc_lo[3]);
+ err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
+ }
+#endif
+#endif
+
+#if 0
+ err |= __put_user(!!used_math(), &sc->sc_used_math);
+
+ if (!used_math())
+ goto out;
+
+ /*
+ * Save FPU state to signal context. Signal handler will "inherit"
+ * current FPU state.
+ */
+ preempt_disable();
+
+ if (!is_fpu_owner()) {
+ own_fpu();
+ restore_fp(current);
+ }
+ err |= save_fp_context(sc);
+
+ preempt_enable();
+ out:
+#endif
+ return err;
+}
+
+static inline int
+restore_sigcontext(CPUState *regs, struct target_sigcontext *sc)
+{
+ int err = 0;
+
+ err |= __get_user(regs->CP0_EPC, &sc->sc_pc);
+
+ err |= __get_user(regs->active_tc.HI[0], &sc->sc_mdhi);
+ err |= __get_user(regs->active_tc.LO[0], &sc->sc_mdlo);
+
+#define restore_gp_reg(i) do { \
+ err |= __get_user(regs->active_tc.gpr[i], &sc->sc_regs[i]); \
+} while (0)
+ restore_gp_reg(1); restore_gp_reg(2); restore_gp_reg(3);
+ restore_gp_reg(4); restore_gp_reg(5); restore_gp_reg(6);
+ restore_gp_reg(7); restore_gp_reg(8); restore_gp_reg(9);
+ restore_gp_reg(10); restore_gp_reg(11); restore_gp_reg(12);
+ restore_gp_reg(13); restore_gp_reg(14); restore_gp_reg(15);
+ restore_gp_reg(16); restore_gp_reg(17); restore_gp_reg(18);
+ restore_gp_reg(19); restore_gp_reg(20); restore_gp_reg(21);
+ restore_gp_reg(22); restore_gp_reg(23); restore_gp_reg(24);
+ restore_gp_reg(25); restore_gp_reg(26); restore_gp_reg(27);
+ restore_gp_reg(28); restore_gp_reg(29); restore_gp_reg(30);
+ restore_gp_reg(31);
+#undef restore_gp_reg
+
+#if 0
+ if (cpu_has_dsp) {
+ err |= __get_user(treg, &sc->sc_hi1); mthi1(treg);
+ err |= __get_user(treg, &sc->sc_lo1); mtlo1(treg);
+ err |= __get_user(treg, &sc->sc_hi2); mthi2(treg);
+ err |= __get_user(treg, &sc->sc_lo2); mtlo2(treg);
+ err |= __get_user(treg, &sc->sc_hi3); mthi3(treg);
+ err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg);
+ err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK);
+ }
+#ifdef CONFIG_64BIT
+ err |= __get_user(regs->hi, &sc->sc_hi[0]);
+ err |= __get_user(regs->lo, &sc->sc_lo[0]);
+ if (cpu_has_dsp) {
+ err |= __get_user(treg, &sc->sc_hi[1]); mthi1(treg);
+ err |= __get_user(treg, &sc->sc_lo[1]); mthi1(treg);
+ err |= __get_user(treg, &sc->sc_hi[2]); mthi2(treg);
+ err |= __get_user(treg, &sc->sc_lo[2]); mthi2(treg);
+ err |= __get_user(treg, &sc->sc_hi[3]); mthi3(treg);
+ err |= __get_user(treg, &sc->sc_lo[3]); mthi3(treg);
+ err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK);
+ }
+#endif
+
+ err |= __get_user(used_math, &sc->sc_used_math);
+ conditional_used_math(used_math);
+
+ preempt_disable();
+
+ if (used_math()) {
+ /* restore fpu context if we have used it before */
+ own_fpu();
+ err |= restore_fp_context(sc);
+ } else {
+ /* signal handler may have used FPU. Give it up. */
+ lose_fpu();
+ }
+
+ preempt_enable();
+#endif
+ return err;
+}
+/*
+ * Determine which stack to use..
+ */
+static inline abi_ulong
+get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size)
+{
+ unsigned long sp;
+
+ /* Default to using normal stack */
+ sp = regs->active_tc.gpr[29];
+
+ /*
+ * FPU emulator may have it's own trampoline active just
+ * above the user stack, 16-bytes before the next lowest
+ * 16 byte boundary. Try to avoid trashing it.
+ */
+ sp -= 32;
+
+ /* This is the X/Open sanctioned signal stack switching. */
+ if ((ka->sa_flags & TARGET_SA_ONSTACK) && (sas_ss_flags(sp) == 0)) {
+ sp = target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_size;
+ }
+
+ return (sp - frame_size) & ~7;
+}
+
+/* compare linux/arch/mips/kernel/signal.c:setup_frame() */
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUState *regs)
{
- fprintf(stderr, "setup_frame: not implemented\n");
+ struct sigframe *frame;
+ abi_ulong frame_addr;
+ int i;
+
+ frame_addr = get_sigframe(ka, regs, sizeof(*frame));
+ if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0))
+ goto give_sigsegv;
+
+ install_sigtramp(frame->sf_code, TARGET_NR_rt_sigreturn);
+
+ if (setup_sigcontext(regs, &frame->sf_sc))
+ goto give_sigsegv;
+
+ for (i = 0; i < TARGET_NSIG_WORDS; i++) {
+ if (__put_user(set->sig[i], &frame->sf_mask.sig[i]))
+ goto give_sigsegv;
+ }
+
+ /*
+ * Arguments to signal handler:
+ *
+ * a0 = signal number
+ * a1 = 0 (should be cause)
+ * a2 = pointer to struct sigcontext
+ *
+ * $25 and PC point to the signal handler, $29 points to the
+ * struct sigframe.
+ */
+ regs->active_tc.gpr[4] = sig;
+ regs->active_tc.gpr[5] = 0;
+ regs->active_tc.gpr[6] = frame_addr + offsetof(struct sigframe, sf_sc);
+ regs->active_tc.gpr[29] = frame_addr;
+ regs->active_tc.gpr[31] = frame_addr + offsetof(struct sigframe, sf_code);
+ /* The original kernel code sets CP0_EPC to the handler
+ * since it returns to userland using eret
+ * we cannot do this here, and we must set PC directly */
+ regs->active_tc.PC = regs->active_tc.gpr[25] = ka->_sa_handler;
+ unlock_user_struct(frame, frame_addr, 1);
+ return;
+
+ give_sigsegv:
+ unlock_user_struct(frame, frame_addr, 1);
+ force_sig(TARGET_SIGSEGV/*, current*/);
+ return;
}
-static void setup_rt_frame(int sig, struct target_sigaction *ka,
- target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+long do_sigreturn(CPUState *regs)
{
- fprintf(stderr, "setup_rt_frame: not implemented\n");
+ struct sigframe *frame;
+ abi_ulong frame_addr;
+ sigset_t blocked;
+ target_sigset_t target_set;
+ int i;
+
+#if defined(DEBUG_SIGNAL)
+ fprintf(stderr, "do_sigreturn\n");
+#endif
+ frame_addr = regs->active_tc.gpr[29];
+ if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
+ goto badframe;
+
+ for (i = 0; i < TARGET_NSIG_WORDS; i++) {
+ if (__get_user(target_set.sig[i], &frame->sf_mask.sig[i]))
+ goto badframe;
+ }
+
+ target_to_host_sigset_internal(&blocked, &target_set);
+ sigprocmask(SIG_SETMASK, &blocked, NULL);
+
+ if (restore_sigcontext(regs, &frame->sf_sc))
+ goto badframe;
+
+#if 0
+ /*
+ * Don't let your children do this ...
+ */
+ __asm__ __volatile__(
+ "move\t$29, %0\n\t"
+ "j\tsyscall_exit"
+ :/* no outputs */
+ : "r" (®s));
+ /* Unreached */
+#endif
+
+ regs->active_tc.PC = regs->CP0_EPC;
+ /* I am not sure this is right, but it seems to work
+ * maybe a problem with nested signals ? */
+ regs->CP0_EPC = 0;
+ return -TARGET_QEMU_ESIGRETURN;
+
+ badframe:
+ force_sig(TARGET_SIGSEGV/*, current*/);
+ return 0;
}
-long do_sigreturn(CPUState *env)
+static void setup_rt_frame(int sig, struct target_sigaction *ka,
+ target_siginfo_t *info,
+ target_sigset_t *set, CPUState *env)
{
- fprintf(stderr, "do_sigreturn: not implemented\n");
- return -TARGET_ENOSYS;
+ struct target_rt_sigframe *frame;
+ abi_ulong frame_addr;
+ int i;
+
+ frame_addr = get_sigframe(ka, env, sizeof(*frame));
+ if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0))
+ goto give_sigsegv;
+
+ install_sigtramp(frame->rs_code, TARGET_NR_rt_sigreturn);
+
+ copy_siginfo_to_user(&frame->rs_info, info);
+
+ __put_user(0, &frame->rs_uc.tuc_flags);
+ __put_user(0, &frame->rs_uc.tuc_link);
+ __put_user(target_sigaltstack_used.ss_sp, &frame->rs_uc.tuc_stack.ss_sp);
+ __put_user(target_sigaltstack_used.ss_size, &frame->rs_uc.tuc_stack.ss_size);
+ __put_user(sas_ss_flags(get_sp_from_cpustate(env)),
+ &frame->rs_uc.tuc_stack.ss_flags);
+
+ setup_sigcontext(env, &frame->rs_uc.tuc_mcontext);
+
+ for (i = 0; i < TARGET_NSIG_WORDS; i++) {
+ __put_user(set->sig[i], &frame->rs_uc.tuc_sigmask.sig[i]);
+ }
+
+ /*
+ * Arguments to signal handler:
+ *
+ * a0 = signal number
+ * a1 = pointer to struct siginfo
+ * a2 = pointer to struct ucontext
+ *
+ * $25 and PC point to the signal handler, $29 points to the
+ * struct sigframe.
+ */
+ env->active_tc.gpr[4] = sig;
+ env->active_tc.gpr[5] = frame_addr
+ + offsetof(struct target_rt_sigframe, rs_info);
+ env->active_tc.gpr[6] = frame_addr
+ + offsetof(struct target_rt_sigframe, rs_uc);
+ env->active_tc.gpr[29] = frame_addr;
+ env->active_tc.gpr[31] = frame_addr
+ + offsetof(struct target_rt_sigframe, rs_code);
+ /* The original kernel code sets CP0_EPC to the handler
+ * since it returns to userland using eret
+ * we cannot do this here, and we must set PC directly */
+ env->active_tc.PC = env->active_tc.gpr[25] = ka->_sa_handler;
+ unlock_user_struct(frame, frame_addr, 1);
+ return;
+
+ give_sigsegv:
+ unlock_user_struct(frame, frame_addr, 1);
+ force_sig(TARGET_SIGSEGV/*, current*/);
+ return;
}
long do_rt_sigreturn(CPUState *env)
{
- fprintf(stderr, "do_rt_sigreturn: not implemented\n");
- return -TARGET_ENOSYS;
+ /* This has been done to successfully run signal syscall */
+ if (sigrt == 1)
+ return do_sigreturn(env);
+ else {
+ struct target_rt_sigframe *frame;
+ abi_ulong frame_addr;
+ sigset_t blocked;
+
+#if defined(DEBUG_SIGNAL)
+ fprintf(stderr, "do_rt_sigreturn\n");
+#endif
+ frame_addr = env->active_tc.gpr[29];
+ if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
+ goto badframe;
+
+ target_to_host_sigset(&blocked, &frame->rs_uc.tuc_sigmask);
+ sigprocmask(SIG_SETMASK, &blocked, NULL);
+
+ if (restore_sigcontext(env, &frame->rs_uc.tuc_mcontext))
+ goto badframe;
+
+ if (do_sigaltstack(frame_addr +
+ offsetof(struct target_rt_sigframe, rs_uc.tuc_stack),
+ 0, get_sp_from_cpustate(env)) == -EFAULT)
+ goto badframe;
+
+ env->active_tc.PC = env->CP0_EPC;
+ /* I am not sure this is right, but it seems to work
+ * maybe a problem with nested signals ? */
+ env->CP0_EPC = 0;
+ return -TARGET_QEMU_ESIGRETURN;
+
+ badframe:
+ force_sig(TARGET_SIGSEGV/*, current*/);
+ return 0;
+ }
}
#elif defined(TARGET_ABI_MIPSN32)
@@ -5305,8 +5717,10 @@ void process_pending_signals(CPUState *cpu_env)
/* prepare the stack frame of the virtual CPU */
if (sa->sa_flags & TARGET_SA_SIGINFO)
setup_rt_frame(sig, sa, &q->info, &target_old_set, cpu_env);
- else
+ else {
+ sigrt = 1;
setup_frame(sig, sa, &target_old_set, cpu_env);
+ }
if (sa->sa_flags & TARGET_SA_RESETHAND)
sa->_sa_handler = TARGET_SIG_DFL;
}
--
1.7.3.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 4/7] target-mips:Octeon cpu definition
2011-09-27 4:17 [Qemu-devel] [PATCH 0/7] MIPS64 user mode emulation in QEMU with Cavium specific instruction support khansa
` (2 preceding siblings ...)
2011-09-27 4:17 ` [Qemu-devel] [PATCH 3/7] linux-user:Signal handling for MIPS64 khansa
@ 2011-09-27 4:17 ` khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 5/7] target-mips:Support for Cavium specific instructions khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 6/7] Addition of Cavium instructions in disassembler khansa
5 siblings, 0 replies; 9+ messages in thread
From: khansa @ 2011-09-27 4:17 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, riku.voipio, Khansa Butt, aurelien
From: Khansa Butt <khansa@kics.edu.pk>
Signed-off-by: Khansa Butt <khansa@kics.edu.pk>
---
target-mips/mips-defs.h | 2 ++
target-mips/translate_init.c | 24 ++++++++++++++++++++++++
2 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..e1ec2b2 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -41,6 +41,7 @@
#define ASE_MICROMIPS 0x00080000
/* Chip specific instructions. */
+#define INSN_OCTEON 0x10000000
#define INSN_LOONGSON2E 0x20000000
#define INSN_LOONGSON2F 0x40000000
#define INSN_VR54XX 0x80000000
@@ -53,6 +54,7 @@
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
+#define CPU_OCTEON (CPU_MIPS64R2 | INSN_OCTEON)
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c39138f..09d2605 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -451,6 +451,30 @@ static const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000,
},
{
+ .name = "octeon",
+ .CP0_PRid = 0x0d30,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (63 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x36FBFFFF,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .SEGBITS = 49,
+ .PABITS = 49,
+ .insn_flags = CPU_OCTEON | ASE_MIPS3D,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
.name = "Loongson-2E",
.CP0_PRid = 0x6302,
/*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
--
1.7.3.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 5/7] target-mips:Support for Cavium specific instructions
2011-09-27 4:17 [Qemu-devel] [PATCH 0/7] MIPS64 user mode emulation in QEMU with Cavium specific instruction support khansa
` (3 preceding siblings ...)
2011-09-27 4:17 ` [Qemu-devel] [PATCH 4/7] target-mips:Octeon cpu definition khansa
@ 2011-09-27 4:17 ` khansa
2011-09-27 15:14 ` Richard Henderson
2011-09-28 8:29 ` Andreas Färber
2011-09-27 4:17 ` [Qemu-devel] [PATCH 6/7] Addition of Cavium instructions in disassembler khansa
5 siblings, 2 replies; 9+ messages in thread
From: khansa @ 2011-09-27 4:17 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, riku.voipio, Ehsan-ul-Haq, Abdul Qadeer,
Abdul Waheed, Khansa Butt, aurelien
From: Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt <khansa@kics.edu.pk>
Signed-off-by: Khansa Butt <khansa@kics.edu.pk>
---
target-mips/cpu.h | 7 +
target-mips/helper.h | 5 +
target-mips/machine.c | 12 ++
target-mips/op_helper.c | 72 ++++++++
target-mips/translate.c | 424 ++++++++++++++++++++++++++++++++++++++++++++++-
5 files changed, 515 insertions(+), 5 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 79e2558..9180ee9 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -173,6 +173,13 @@ struct TCState {
target_ulong CP0_TCSchedule;
target_ulong CP0_TCScheFBack;
int32_t CP0_Debug_tcstatus;
+ /* Multiplier registers for Octeon */
+ target_ulong MPL0;
+ target_ulong MPL1;
+ target_ulong MPL2;
+ target_ulong P0;
+ target_ulong P1;
+ target_ulong P2;
};
typedef struct CPUMIPSState CPUMIPSState;
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 442f684..cfaf560 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -8,7 +8,12 @@ DEF_HELPER_3(ldl, tl, tl, tl, int)
DEF_HELPER_3(ldr, tl, tl, tl, int)
DEF_HELPER_3(sdl, void, tl, tl, int)
DEF_HELPER_3(sdr, void, tl, tl, int)
+DEF_HELPER_2(v3mulu, tl, tl, tl)
+DEF_HELPER_2(vmulu, tl, tl, tl)
+DEF_HELPER_1(dpop, tl, tl)
#endif
+DEF_HELPER_1(pop, tl, tl);
+
DEF_HELPER_3(lwl, tl, tl, tl, int)
DEF_HELPER_3(lwr, tl, tl, tl, int)
DEF_HELPER_3(swl, void, tl, tl, int)
diff --git a/target-mips/machine.c b/target-mips/machine.c
index be72b36..a274ce2 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -25,6 +25,12 @@ static void save_tc(QEMUFile *f, TCState *tc)
qemu_put_betls(f, &tc->CP0_TCSchedule);
qemu_put_betls(f, &tc->CP0_TCScheFBack);
qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
+ qemu_put_betls(f, &tc->MPL0);
+ qemu_put_betls(f, &tc->MPL1);
+ qemu_put_betls(f, &tc->P0);
+ qemu_put_betls(f, &tc->P1);
+ qemu_put_betls(f, &tc->P2);
+
}
static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
@@ -173,6 +179,12 @@ static void load_tc(QEMUFile *f, TCState *tc)
qemu_get_betls(f, &tc->CP0_TCSchedule);
qemu_get_betls(f, &tc->CP0_TCScheFBack);
qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
+ qemu_get_betls(f, &tc->MPL0);
+ qemu_get_betls(f, &tc->MPL1);
+ qemu_get_betls(f, &tc->MPL2);
+ qemu_get_betls(f, &tc->P0);
+ qemu_get_betls(f, &tc->P1);
+ qemu_get_betls(f, &tc->P2);
}
static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 96e40c6..19528ee 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -320,8 +320,80 @@ void helper_dmultu (target_ulong arg1, target_ulong arg2)
{
mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
}
+
+static void addc(uint64_t res[], uint64_t a, int i)
+{
+ uint64_t c = res[i];
+ for (; i < 4; i++) {
+ res[i] = c + a;
+ if (res[i] < a) {
+ c = 1;
+ a = res[i+1];
+ } else
+ break;
+ }
+}
+
+target_ulong helper_v3mulu(target_ulong arg1, target_ulong arg2)
+{
+ uint64_t hi, lo, res[4];
+ int i;
+ for (i = 0; i < 4; i++) {
+ res[i] = 0;
+ }
+ mulu64(&res[0], &res[1], env->active_tc.MPL0, arg1);
+ mulu64(&lo, &hi, env->active_tc.MPL1, arg1);
+ res[1] = res[1] + lo;
+ if (res[1] < lo) {
+ res[2]++;
+ }
+ res[2] = res[2] + hi;
+ if (res[2] < hi) {
+ res[3]++;
+ }
+ mulu64(&lo, &hi, env->active_tc.MPL2, arg1);
+ res[2] = res[2] + lo;
+ if (res[2] < lo) {
+ res[3]++;
+ }
+ res[3] = res[3] + hi;
+ addc(res, arg2, 0);
+ addc(res, env->active_tc.P0, 0);
+ addc(res, env->active_tc.P1, 1);
+ addc(res, env->active_tc.P2, 2);
+ env->active_tc.P0 = res[1];
+ env->active_tc.P1 = res[2];
+ env->active_tc.P2 = res[3];
+ return res[0];
+}
+
+target_ulong helper_vmulu(target_ulong arg1, target_ulong arg2)
+{
+ uint64_t hi, lo;
+ mulu64(&lo, &hi, env->active_tc.MPL0, arg1);
+ lo = lo + arg2;
+ if (lo < arg2) {
+ hi++;
+ }
+ lo = lo + env->active_tc.P0;
+ if (lo < env->active_tc.P0) {
+ hi++;
+ }
+ env->active_tc.P0 = hi;
+ return lo;
+}
+
+target_ulong helper_dpop(target_ulong arg)
+{
+ return ctpop64(arg);
+}
#endif
+target_ulong helper_pop(target_ulong arg)
+{
+ return ctpop32((uint32_t)arg);
+}
+
#ifndef CONFIG_USER_ONLY
static inline target_phys_addr_t do_translate_address(target_ulong address, int rw)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 0550333..f60b229 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -69,6 +69,11 @@ enum {
OPC_JAL = (0x03 << 26),
OPC_JALS = OPC_JAL | 0x5,
OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
+ /* Cavium Specific */
+ OPC_BBIT1 = (0x3a << 26), /* jump on bit set, cavium specific */
+ OPC_BBIT132 = (0x3e << 26), /* jump on bit set (for upper 32 bits) */
+ OPC_BBIT0 = (0x32 << 26), /* jump on bit clear, cavium specific */
+ OPC_BBIT032 = (0x36 << 26), /* jump on bit clear (for upper 32 bits) */
OPC_BEQL = (0x14 << 26),
OPC_BNE = (0x05 << 26),
OPC_BNEL = (0x15 << 26),
@@ -286,6 +291,30 @@ enum {
OPC_DCLO = 0x25 | OPC_SPECIAL2,
/* Special */
OPC_SDBBP = 0x3F | OPC_SPECIAL2,
+ /* Cavium Specific Instructions */
+ OPC_BADDU = 0x28 | OPC_SPECIAL2,
+ OPC_DMUL = 0x03 | OPC_SPECIAL2,
+ OPC_EXTS = 0x3a | OPC_SPECIAL2,
+ OPC_EXTS32 = 0x3b | OPC_SPECIAL2,
+ OPC_CINS = 0x32 | OPC_SPECIAL2,
+ OPC_CINS32 = 0x33 | OPC_SPECIAL2,
+ OPC_SEQI = 0x2e | OPC_SPECIAL2,
+ OPC_SNEI = 0x2f | OPC_SPECIAL2,
+ OPC_MTM0 = 0x08 | OPC_SPECIAL2,
+ OPC_MTM1 = 0x0c | OPC_SPECIAL2,
+ OPC_MTM2 = 0x0d | OPC_SPECIAL2,
+ OPC_MTP0 = 0x09 | OPC_SPECIAL2,
+ OPC_MTP1 = 0x0a | OPC_SPECIAL2,
+ OPC_MTP2 = 0x0b | OPC_SPECIAL2,
+ OPC_V3MULU = 0x11 | OPC_SPECIAL2,
+ OPC_VMM0 = 0x10 | OPC_SPECIAL2,
+ OPC_VMULU = 0x0f | OPC_SPECIAL2,
+ OPC_POP = 0X2C | OPC_SPECIAL2,
+ OPC_DPOP = 0X2D | OPC_SPECIAL2,
+ OPC_SEQ = 0x2a | OPC_SPECIAL2,
+ OPC_SNE = 0x2b | OPC_SPECIAL2,
+ OPC_SAA = 0x18 | OPC_SPECIAL2,
+ OPC_SAAD = 0x19 | OPC_SPECIAL2,
};
/* Special3 opcodes */
@@ -1418,7 +1447,221 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
(void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
}
+#if defined(TARGET_MIPS64)
+/* set on equal/not equal immidiate */
+static void gen_set_imm(CPUState *env, uint32_t opc,
+ int rt, int rs, int16_t imm)
+{
+ target_ulong uimm = (target_long)imm;
+ TCGv t0;
+ const char *opn = "imm set";
+ if (rt == 0) {
+ /* If no destination, treat it as a NOP. */
+ MIPS_DEBUG("NOP");
+ return;
+ }
+ t0 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ tcg_gen_xori_tl(t0, t0, uimm);
+ switch (opc) {
+ case OPC_SEQI:
+ tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, 1);
+ opn = "seqi";
+ break;
+ case OPC_SNEI:
+ tcg_gen_setcondi_tl(TCG_COND_GT, cpu_gpr[rt], t0, 0);
+ opn = "snei";
+ break;
+ }
+ tcg_temp_free(t0);
+}
+/* Cavium specific Large Multiply Instructions */
+static void gen_LMI(DisasContext *ctx, uint32_t opc, int rs, int rt, int rd)
+{
+ const char *opn = "LMI";
+ TCGv t0, t1;
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ switch (opc) {
+ case OPC_MTM0:
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.MPL0));
+ tcg_gen_movi_tl(t0, 0);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P0));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P1));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P2));
+ opn = "mtm0";
+ break;
+ case OPC_MTM1:
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.MPL1));
+ tcg_gen_movi_tl(t0, 0);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P0));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P1));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P2));
+ opn = "mtm1";
+ break;
+ case OPC_MTM2:
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.MPL2));
+ tcg_gen_movi_tl(t0, 0);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P0));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P1));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P2));
+ break;
+ case OPC_MTP0:
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P0));
+ opn = "mtp0";
+ break;
+ case OPC_MTP1:
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P1));
+ opn = "mtp1";
+ break;
+ case OPC_MTP2:
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P2));
+ opn = "mtp2";
+ break;
+ case OPC_VMM0:
+ {
+ TCGv t2, t3;
+ t2 = tcg_temp_new();
+ t3 = tcg_temp_new();
+ tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUState, active_tc.MPL0));
+ tcg_gen_ld_tl(t3, cpu_env, offsetof(CPUState, active_tc.P0));
+ tcg_gen_mul_i64(t0, t0, t2);
+ tcg_gen_add_tl(t1, t1, t0);
+ tcg_gen_add_tl(t1, t1, t3);
+ gen_store_gpr(t1, rd);
+ tcg_gen_movi_tl(t0, 0);
+ tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, active_tc.MPL0));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P0));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P1));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, active_tc.P2));
+ tcg_temp_free(t2);
+ tcg_temp_free(t3);
+ opn = "vmm0";
+ break;
+ }
+ case OPC_VMULU:
+ gen_helper_vmulu(t0, t0, t1);
+ gen_store_gpr(t0, rd);
+ opn = "vmulu";
+ break;
+ case OPC_V3MULU:
+ gen_helper_v3mulu(t0, t0, t1);
+ gen_store_gpr(t0, rd);
+ opn = "v3mulu";
+ break;
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+/* set if equal/not equal */
+static void gen_set(DisasContext *ctx, uint32_t opc,
+ int rd, int rs, int rt)
+{
+ const char *opn = "seq/sne";
+ TCGv t0, t1;
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_xor_tl(t0, t0, t1);
+ switch (opc) {
+ case OPC_SEQ:
+ tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rd], t0, 1);
+ opn = "seq";
+ break;
+ case OPC_SNE:
+ tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_gpr[rd], t0, 0);
+ opn = "sne";
+ break;
+ default:
+ MIPS_INVAL(opn);
+ generate_exception(ctx, EXCP_RI);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+}
+/* Store atomic add */
+/* FIXME: something else should be done for emulating SMP system. */
+static void gen_saa(CPUState *env, DisasContext *ctx, uint32_t opc,
+ int rt, int base)
+{
+ const char *opn = "saa";
+ TCGv t0, t1, temp;
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ temp = tcg_temp_new();
+ gen_load_gpr(t1, rt);
+ gen_base_offset_addr(ctx, t0, base, 0);
+ switch (opc) {
+ case OPC_SAA:
+ save_cpu_state(ctx, 1);
+ op_ld_ll(temp, t0, ctx);
+ tcg_gen_add_tl(temp, temp, t1);
+ op_st_sc(temp, t0, rt, ctx);
+ opn = "saa";
+ break;
+ case OPC_SAAD:
+ save_cpu_state(ctx, 0);
+ op_ld_lld(temp, t0, ctx);
+ tcg_gen_add_tl(temp, temp, t1);
+ op_st_scd(temp, t0, rt, ctx);
+ opn = "saad";
+ break;
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+static void gen_pop_count(DisasContext *ctx, uint32_t opc, int rd, int rs)
+{
+ const char *opn = "pop";
+ TCGv t0;
+ t0 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ switch (opc) {
+ case OPC_DPOP:
+ gen_helper_dpop(t0, t0);
+ gen_store_gpr(t0, rd);
+ opn = "dpop";
+ break;
+ case OPC_POP:
+ gen_helper_pop(t0, t0);
+ gen_store_gpr(t0, rd);
+ opn = "pop";
+ break;
+ }
+ tcg_temp_free(t0);
+}
+/* Cavium specific extract instructions */
+static void gen_exts(CPUState *env, DisasContext *ctx, uint32_t opc, int rt,
+ int rs, int lsb, int msb)
+{
+ TCGv t0 = tcg_temp_new();
+ uint32_t lshft, rshft;
+ gen_load_gpr(t0, rs);
+ switch (opc) {
+ case OPC_EXTS:
+ lshft = 64 - msb - 1 - lsb;
+ rshft = lshft + lsb;
+ tcg_gen_shli_tl(t0, t0, lshft);
+ tcg_gen_sari_tl(t0, t0, rshft);
+ gen_store_gpr(t0, rt);
+ break;
+ case OPC_EXTS32:
+ lshft = 32 - msb - 1 - lsb;
+ rshft = 64 - msb - 1;
+ tcg_gen_shli_tl(t0, t0, lshft);
+ tcg_gen_sari_tl(t0, t0, rshft);
+ gen_store_gpr(t0, rt);
+ break;
+
+ }
+ tcg_temp_free(t0);
+}
+#endif
/* Logic with immediate operand */
static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
{
@@ -1636,6 +1879,32 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
}
opn = "addu";
break;
+ case OPC_BADDU:
+ {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_add_tl(t0, t1, t0);
+ tcg_gen_ext8u_tl(t0, t0);
+ gen_store_gpr(t0, rd);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ opn = "baddu";
+ break;
+ }
+ case OPC_DMUL:
+ {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ opn = "dmul";
+ break;
+ }
case OPC_SUB:
{
TCGv t0 = tcg_temp_local_new();
@@ -2729,6 +2998,28 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
}
btgt = ctx->pc + insn_bytes + offset;
break;
+ case OPC_BBIT0:
+ case OPC_BBIT1:
+ {
+ target_ulong maskb;
+ gen_load_gpr(t0, rs);
+ maskb = 1ULL << rt;
+ tcg_gen_andi_tl(t0, t0, maskb);
+ bcond_compute = 1;
+ btgt = ctx->pc + insn_bytes + offset;
+ break;
+ }
+ case OPC_BBIT032:
+ case OPC_BBIT132:
+ {
+ target_ulong maskb;
+ gen_load_gpr(t0, rs);
+ maskb = 1ULL << (rt + 32);
+ tcg_gen_andi_tl(t0, t0, maskb);
+ bcond_compute = 1;
+ btgt = ctx->pc + insn_bytes + offset;
+ break;
+ }
case OPC_BGEZ:
case OPC_BGEZAL:
case OPC_BGEZALS:
@@ -2887,6 +3178,14 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
regnames[rs], regnames[rt], btgt);
goto not_likely;
+ case OPC_BBIT1:
+ case OPC_BBIT132:
+ tcg_gen_setcondi_tl(TCG_COND_NE, bcond, t0, 0);
+ goto not_likely;
+ case OPC_BBIT0:
+ case OPC_BBIT032:
+ tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, t0, 0);
+ goto not_likely;
case OPC_BNEL:
tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
@@ -3062,6 +3361,22 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
tcg_gen_andi_tl(t1, t1, mask);
tcg_gen_or_tl(t0, t0, t1);
break;
+ case OPC_CINS:
+ mask = (1ULL << (msb+1))-1;
+ gen_load_gpr(t0, rt);
+ tcg_gen_andi_tl(t0, t0, 0);
+ tcg_gen_andi_tl(t1, t1, mask);
+ tcg_gen_shli_tl(t1, t1, lsb);
+ tcg_gen_or_tl(t0, t0, t1);
+ break;
+ case OPC_CINS32:
+ mask = (1ULL << (msb+1))-1;
+ gen_load_gpr(t0, rt);
+ tcg_gen_andi_tl(t0, t0, 0);
+ tcg_gen_andi_tl(t1, t1, mask);
+ tcg_gen_shli_tl(t1, t1, (lsb+32));
+ tcg_gen_or_tl(t0, t0, t1);
+ break;
#endif
default:
fail:
@@ -11948,6 +12263,57 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)
case OPC_MUL:
gen_arith(env, ctx, op1, rd, rs, rt);
break;
+#if defined(TARGET_MIPS64)
+ case OPC_DMUL:
+ check_mips_64(ctx);
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_arith(env, ctx, op1, rd, rs, rt);
+ break;
+ case OPC_CINS:
+ check_mips_64(ctx);
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_bitops(ctx, op1, rt, rs, sa, rd);
+ break;
+ case OPC_CINS32:
+ check_mips_64(ctx);
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_bitops(ctx, op1, rt, rs, sa, rd);
+ break;
+ case OPC_MTM0:
+ case OPC_MTM1:
+ case OPC_MTM2:
+ case OPC_MTP0:
+ case OPC_MTP1:
+ case OPC_MTP2:
+ case OPC_VMULU:
+ check_mips_64(ctx);
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_LMI(ctx, op1, rs, rt, rd);
+ break;
+ case OPC_BADDU:
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_arith(env, ctx, op1, rd, rs, rt);
+ break;
+ case OPC_EXTS:
+ check_mips_64(ctx);
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_exts(env, ctx, op1, rt, rs, sa, rd);
+ break;
+ case OPC_EXTS32:
+ check_mips_64(ctx);
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_exts(env, ctx, op1, rt, rs, sa, rd);
+ break;
+ case OPC_SAA:
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_saa(env, ctx, op1, rt, rs);
+ break;
+ case OPC_SAAD:
+ check_insn(env, ctx, INSN_OCTEON);
+ check_mips_64(ctx);
+ gen_saa(env, ctx, op1, rt, rs);
+ break;
+#endif
case OPC_CLO:
case OPC_CLZ:
check_insn(env, ctx, ISA_MIPS32);
@@ -11965,9 +12331,18 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)
}
/* Treat as NOP. */
break;
+ case OPC_MULT_G_2F:
+#if defined(TARGET_MIPS64)
+ /* Is Cavium Specific vmm0? */
+ if ((env->insn_flags & CPU_OCTEON)) {
+ check_mips_64(ctx);
+ gen_LMI(ctx, op1, rs, rt, rd);
+ break;
+ }
+#endif
+ /* Otherwise fall through */
case OPC_DIV_G_2F:
case OPC_DIVU_G_2F:
- case OPC_MULT_G_2F:
case OPC_MULTU_G_2F:
case OPC_MOD_G_2F:
case OPC_MODU_G_2F:
@@ -11982,6 +12357,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)
gen_cl(ctx, op1, rd, rs);
break;
case OPC_DMULT_G_2F:
+ /* Is Cavium Specific instruction v3mulu? */
+ if ((env->insn_flags & CPU_OCTEON)) {
+ check_mips_64(ctx);
+ gen_LMI(ctx, op1, rs, rt, rd);
+ break;
+ }
case OPC_DMULTU_G_2F:
case OPC_DDIV_G_2F:
case OPC_DDIVU_G_2F:
@@ -11990,6 +12371,31 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)
check_insn(env, ctx, INSN_LOONGSON2F);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
+ case OPC_SEQ:
+ case OPC_SNE:
+ check_mips_64(ctx);
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_set(ctx, op1, rd, rs, rt);
+ break;
+ case OPC_SEQI:
+ case OPC_SNEI:
+ {
+ int16_t imm10;
+ imm10 = (ctx->opcode >> 6) & 0x3ff;
+ check_mips_64(ctx);
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_set_imm(env, op1, rt, rs, imm10);
+ break;
+ }
+ case OPC_POP:
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_pop_count(ctx, op1, rd, rs);
+ break;
+ case OPC_DPOP:
+ check_mips_64(ctx);
+ check_insn(env, ctx, INSN_OCTEON);
+ gen_pop_count(ctx, op1, rd, rs);
+ break;
#endif
default: /* Invalid */
MIPS_INVAL("special2");
@@ -12281,10 +12687,18 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)
break;
/* COP2. */
- case OPC_LWC2:
- case OPC_LDC2:
- case OPC_SWC2:
- case OPC_SDC2:
+ /* Conflicting opcodes with Cavium specific branch instructions
+ if cpu_model is set to Octeon these opcodes will
+ belong to INSN_OCTEON */
+ case OPC_LWC2: /* BBIT0 */
+ case OPC_LDC2: /* BBIT032 */
+ case OPC_SWC2: /* BBIT1 */
+ case OPC_SDC2: /* BBIT132 */
+ if (env->insn_flags & INSN_OCTEON) {
+ gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
+ *is_branch = 1;
+ break;
+ }
case OPC_CP2:
/* COP2: Not implemented. */
generate_exception_err(ctx, EXCP_CpU, 2);
--
1.7.3.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 6/7] Addition of Cavium instructions in disassembler
2011-09-27 4:17 [Qemu-devel] [PATCH 0/7] MIPS64 user mode emulation in QEMU with Cavium specific instruction support khansa
` (4 preceding siblings ...)
2011-09-27 4:17 ` [Qemu-devel] [PATCH 5/7] target-mips:Support for Cavium specific instructions khansa
@ 2011-09-27 4:17 ` khansa
5 siblings, 0 replies; 9+ messages in thread
From: khansa @ 2011-09-27 4:17 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, riku.voipio, Khansa Butt, aurelien
From: Khansa Butt <khansa@kics.edu.pk>
Signed-off-by: Khansa Butt <khansa@kics.edu.pk>
---
mips-dis.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 53 insertions(+), 0 deletions(-)
diff --git a/mips-dis.c b/mips-dis.c
index e3a6e0b..96ab1e8 100644
--- a/mips-dis.c
+++ b/mips-dis.c
@@ -300,6 +300,7 @@ struct mips_opcode
Also used for immediate operands in vr5400 vector insns.
"o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA)
+ "+p" 5 bit unsigned constant describing bit position, for Octeon (OP_*_RT)
"q" 10 bit extra breakpoint code (OP_*_CODE2)
"r" 5 bit same register used as both source and target (OP_*_RS)
"s" 5 bit source register specifier (OP_*_RS)
@@ -491,6 +492,13 @@ struct mips_opcode
#define INSN_MULT 0x40000000
/* Instruction synchronize shared memory. */
#define INSN_SYNC 0x80000000
+/* Load Cavium specific multiplier registers. */
+#define INSN_WRITE_MPL0 0x100000000
+#define INSN_WRITE_MPL1 0x200000000
+#define INSN_WRITE_MPL2 0x400000000
+#define INSN_WRITE_P0 0x800000000
+#define INSN_WRITE_P1 0x1000000000
+#define INSN_WRITE_P2 0x2000000000
/* These are the bits which may be set in the pinfo2 field of an
instruction. */
@@ -569,6 +577,8 @@ struct mips_opcode
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
+/* Cavium Network's Octeon processor */
+#define INSN_CVM_OCTEON 0x100000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -1099,6 +1109,13 @@ extern const int bfd_mips16_num_opcodes;
#define RD_HI INSN_READ_HI
#define MOD_HI WR_HI|RD_HI
+#define WR_MPL0 INSN_WRITE_MPL0
+#define WR_MPL1 INSN_WRITE_MPL1
+#define WR_MPL2 INSN_WRITE_MPL2
+#define WR_P0 INSN_WRITE_P0
+#define WR_P1 INSN_WRITE_P1
+#define WR_P2 INSN_WRITE_P2
+
#define WR_LO INSN_WRITE_LO
#define RD_LO INSN_READ_LO
#define MOD_LO WR_LO|RD_LO
@@ -1137,6 +1154,8 @@ extern const int bfd_mips16_num_opcodes;
#define IL2E (INSN_LOONGSON_2E)
#define IL2F (INSN_LOONGSON_2F)
+#define ICVM (INSN_CVM_OCTEON)
+
#define P3 INSN_4650
#define L1 INSN_4010
#define V1 (INSN_4100 | INSN_4111 | INSN_4120)
@@ -2435,6 +2454,34 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 },
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 },
+/* Cavium specific instructions */
+{"baddu", "d,s,t", 0x70000028, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM },
+{"dmul", "d,s,t", 0x70000003, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM },
+{"v3mulu", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM },
+{"vmm0", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM },
+{"vmulu", "d,s,t", 0x7000000f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM },
+{"seq", "d,s,t", 0x7000002a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM },
+{"seqi", "t,r,j", 0x7000002e, 0xfc00003f, WR_t|RD_s, 0, ICVM },
+{"sne", "d,s,t", 0x7000002b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM },
+{"snei", "t,r,j", 0x7000002f, 0xfc00003f, WR_t|RD_s, 0, ICVM },
+{"bbit0", "s,+p,p", 0xc8000000, 0xfc000000, CBD|RD_s, 0, ICVM },
+{"bbit032", "s,+p,p", 0xd8000000, 0xfc000000, CBD|RD_s, 0, ICVM },
+{"bbit1", "s,+p,p", 0xe8000000, 0xfc000000, CBD|RD_s, 0, ICVM },
+{"bbit132", "s,+p,p", 0xf8000000, 0xfc000000, CBD|RD_s, 0, ICVM },
+{"saa", "t,(b)", 0x70000018, 0xfc00ffff, SM|RD_t|RD_b, 0, ICVM },
+{"saad", "t,(b)", 0x70000019, 0xfc00ffff, SM|RD_t|RD_b, 0, ICVM },
+{"exts", "t,r,+A,+C", 0x7000003a, 0xfc00003f, WR_t|RD_s, 0, ICVM },
+{"exts32", "t,r,+A,+C", 0x7c00003b, 0xfc00003f, WR_t|RD_s, 0, ICVM },
+{"cins", "t,r,+A,+B", 0x70000032, 0xfc00003f, WR_t|RD_s, 0, ICVM },
+{"cins32", "t,r,+A,+B", 0x70000033, 0xfc00003f, WR_t|RD_s, 0, ICVM },
+{"mtm0", "s", 0x70000008, 0xfc1fffff, RD_s|WR_MPL0, 0, ICVM },
+{"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_s|WR_MPL1, 0, ICVM },
+{"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_s|WR_MPL2, 0, ICVM },
+{"mtp0", "s", 0x70000009, 0xfc1fffff, RD_s|WR_P0, 0, ICVM },
+{"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_s|WR_P1, 0, ICVM },
+{"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_s|WR_P2, 0, ICVM },
+{"dpop", "d,s", 0x7000002d, 0xfc1f07ff, RD_s|WR_d, 0, ICVM },
+{"pop", "d,s", 0x7000002c, 0xfc1f07ff, RD_s|WR_d, 0, ICVM },
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
4010 any more, so move this insn out of the way. If the object
format gave us more info, we could do this right. */
@@ -3603,6 +3650,12 @@ print_insn_args (const char *d,
break;
}
+ case 'p':
+ /* Cavium specific 5 bit value describing bit position. */
+ (*info->fprintf_func) (info->stream, "0x%x",
+ (unsigned int)(l >> OP_SH_RT) & OP_MASK_RT);
+ break;
+
default:
/* xgettext:c-format */
(*info->fprintf_func) (info->stream,
--
1.7.3.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH 5/7] target-mips:Support for Cavium specific instructions
2011-09-27 4:17 ` [Qemu-devel] [PATCH 5/7] target-mips:Support for Cavium specific instructions khansa
@ 2011-09-27 15:14 ` Richard Henderson
2011-09-28 8:29 ` Andreas Färber
1 sibling, 0 replies; 9+ messages in thread
From: Richard Henderson @ 2011-09-27 15:14 UTC (permalink / raw)
To: khansa; +Cc: peter.maydell, riku.voipio, qemu-devel, aurelien
On 09/26/2011 09:17 PM, khansa@kics.edu.pk wrote:
> + switch (opc) {
> + case OPC_SEQI:
> + tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, 1);
> + opn = "seqi";
> + break;
> + case OPC_SNEI:
> + tcg_gen_setcondi_tl(TCG_COND_GT, cpu_gpr[rt], t0, 0);
> + opn = "snei";
> + break;
> + }
You didn't change anything wrt my comments from the last round.
r~
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH 5/7] target-mips:Support for Cavium specific instructions
2011-09-27 4:17 ` [Qemu-devel] [PATCH 5/7] target-mips:Support for Cavium specific instructions khansa
2011-09-27 15:14 ` Richard Henderson
@ 2011-09-28 8:29 ` Andreas Färber
1 sibling, 0 replies; 9+ messages in thread
From: Andreas Färber @ 2011-09-28 8:29 UTC (permalink / raw)
To: khansa; +Cc: peter.maydell, riku.voipio, qemu-devel, aurelien, rth
Am 27.09.2011 06:17, schrieb khansa@kics.edu.pk:
> From: Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt <khansa@kics.edu.pk>
>
>
> Signed-off-by: Khansa Butt <khansa@kics.edu.pk>
...nor all of mine from previous rounds. Including From vs.
Signed-off-by mixup (From is who sent the patch, not whom the code
originated from), Coding Style issues, misleading "Cavium specific"
comments, typos, ...
A space after the colon in the subject would be more visually pleasing, too.
Further, your patch series is completely missing versioning ([PATCH vX
n/m] and change log). Not seeing what you've actually changed for this
resubmission while still seeing unaddressed flaws we've pointed out
already becomes annoying after a while and will not help your patches
make it into the repository...
Regards,
Andreas
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2011-09-28 8:29 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-09-27 4:17 [Qemu-devel] [PATCH 0/7] MIPS64 user mode emulation in QEMU with Cavium specific instruction support khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 1/7] linux-user:Support for MIPS64 user mode emulation in QEMU khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 2/7] target-mips:enabling of 64 bit user mode and floating point operations khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 3/7] linux-user:Signal handling for MIPS64 khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 4/7] target-mips:Octeon cpu definition khansa
2011-09-27 4:17 ` [Qemu-devel] [PATCH 5/7] target-mips:Support for Cavium specific instructions khansa
2011-09-27 15:14 ` Richard Henderson
2011-09-28 8:29 ` Andreas Färber
2011-09-27 4:17 ` [Qemu-devel] [PATCH 6/7] Addition of Cavium instructions in disassembler khansa
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.