* [RFC PATCH 1/3] dt: device tree bindings for DDR memories
[not found] ` <1324128052-11220-1-git-send-email-aneesh-l0cyMroinI0@public.gmane.org>
@ 2011-12-17 13:20 ` Aneesh V
2011-12-17 13:20 ` [RFC PATCH 2/3] dt: device tree bindings for TI's EMIF sdram controller Aneesh V
2011-12-17 13:20 ` [RFC PATCH 3/3] dt: EMIF and lpddr2 device tree data for OMAP4 boards Aneesh V
2 siblings, 0 replies; 4+ messages in thread
From: Aneesh V @ 2011-12-17 13:20 UTC (permalink / raw)
To: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-patch-review-uAqBSO/uNfhBDgjK7y7TUQ
Cc: Aneesh V, santosh.shilimkar-l0cyMroinI0
device tree bindings for DDR SDRAM memories compliant
to JEDEC standards. Currently only DDR3 and LPDDR2 have
been considered for this binding. Properties for other
memory types(DDR2 etc) could be added to this binding
on a need-basis.
The 'ddr' binding in-turn uses another binding 'ddr-timings'
for specifying the AC timing parameters of the memory device
at different speed-bins.
Cc: Rajendra Nayak <rnayak-l0cyMroinI0@public.gmane.org>
Cc: Benoit Cousson <b-cousson-l0cyMroinI0@public.gmane.org>
Signed-off-by: Aneesh V <aneesh-l0cyMroinI0@public.gmane.org>
---
Documentation/devicetree/bindings/ddr/ddr.txt | 113 ++++++++++++++++++++
.../devicetree/bindings/ddr/ddr_timings.txt | 60 +++++++++++
2 files changed, 173 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ddr/ddr.txt
create mode 100644 Documentation/devicetree/bindings/ddr/ddr_timings.txt
diff --git a/Documentation/devicetree/bindings/ddr/ddr.txt b/Documentation/devicetree/bindings/ddr/ddr.txt
new file mode 100644
index 0000000..2f8e4e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/ddr/ddr.txt
@@ -0,0 +1,113 @@
+* DDR SDRAM memories compliant to JEDEC specifications JESD209-2(LPDDR2)
+ or JESD79-3(DDR3).
+
+Required properties:
+- compatible : Should be one of - "jedec,ddr3", "jedec,lpddr2-nvm",
+ "jedec,lpddr2-s2", or "jedec,lpddr2-s4"
+
+ "ti,emif-ddr3" should be listed if the memory part is DDR3 type
+
+ "ti,emif-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
+
+ "ti,emif-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
+
+ "ti,emif-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
+
+- density : string representing the density of the device in terms of
+ Mb (mega bits). Following are the allowed values: "64Mb", "128Mb",
+ "256Mb", "512Mb", "1Gb", "2Gb", "4Gb", "8Gb", "16Gb", or "32Gb"
+
+- io-width : string representing the io width: "x8", "x16" or "x32".
+
+- manufacturer : string with manufacturer name
+
+Optional properties:
+
+The following optional properties represent the minimum value of some AC
+timing parameters of the DDR device in terms of number of clock cycles.
+These values shall be obtained from the device data-sheet.
+
+- tRRD-min-tck
+- tWTR-min-tck
+- tXP-min-tck
+- tRTP-min-tck
+- tCKE-min-tck
+- tRPab-min-tck /* LPDDR2 only */
+- tRCD-min-tck /* LPDDR2 only */
+- tWR-min-tck /* LPDDR2 only */
+- tRASmin-min-tck /* LPDDR2 only */
+- tCKESR-min-tck /* LPDDR2 only */
+- tFAW-min-tck /* LPDDR2 only */
+- tZQCS-min-tck /* DDR3 only */
+- tZQoper-min-tck /* DDR3 only */
+- tZQinit-min-tck /* DDR3 only */
+- tXS-min-tck /* DDR3 only */
+
+Child nodes:
+- The ddr node may have one or more child nodes of type "ddr-timings".
+ "ddr-timings" provides AC timing parameters of the device for
+ a given speed-bin. The user may provide the timings for as many
+ speed-bins as is required. Please see Documentation/devicetree/
+ bindings/ddr/ddr-timings.txt for more information on "ddr-timings"
+
+Example:
+
+elpida_2GS4 : ddr {
+ compatible = "jedec,lpddr2-s4";
+ density = "2Gb";
+ io-width = "x32";
+ manufacturer = "Elpida";
+
+ tRPab-min-tck = <3>;
+ tRCD-min-tck = <3>;
+ tWR-min-tck = <3>;
+ tRASmin-min-tck = <3>;
+ tRRD-min-tck = <2>;
+ tWTR-min-tck = <2>;
+ tXP-min-tck = <2>;
+ tRTP-min-tck = <2>;
+ tCKE-min-tck = <3>;
+ tCKESR-min-tck = <3>;
+ tFAW-min-tck = <8>;
+
+ timings_elpida_2GS4_400mhz: ddr-timings {
+ min-freq = <10000000>;
+ max-freq = <400000000>;
+ tRP-ps = <21000>;
+ tRCD-ps = <18000>;
+ tWR-ps = <15000>;
+ tRAS-min-ps = <42000:;
+ tRRD-ps = <10000>;
+ tWTR-ps = <7500>;
+ tXP-ps = <7500>;
+ tRTP-ps = <7500>;
+ tCKESR-ps = <15000>;
+ tDQSCK-max-ps = <5500>;
+ tFAW-ps = <50000>;
+ tZQCS-ps = <90000>;
+ tZQoper-ps = <360000>;
+ tZQinit-ps = <1000000>;
+ tRAS-max-ns = <70000>;
+ };
+
+ timings_elpida_2GS4_200mhz: ddr-timings {
+ min-freq = <10000000>;
+ max-freq = <200000000>;
+ tRP-ps = <21000>;
+ tRCD-ps = <18000>;
+ tWR-ps = <15000>;
+ tRAS-min-ps = <42000:;
+ tRRD-ps = <10000>;
+ tWTR-ps = <10000>;
+ tXP-ps = <7500>;
+ tRTP-ps = <7500>;
+ tCKESR-ps = <15000>;
+ tDQSCK-max-ps = <5500>;
+ tFAW-ps = <50000>;
+ tZQCS-ps = <90000>;
+ tZQoper-ps = <360000>;
+ tZQinit-ps = <1000000>;
+ tRAS-max-ns = <70000>;
+ };
+
+}
diff --git a/Documentation/devicetree/bindings/ddr/ddr_timings.txt b/Documentation/devicetree/bindings/ddr/ddr_timings.txt
new file mode 100644
index 0000000..f3cd5e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/ddr/ddr_timings.txt
@@ -0,0 +1,60 @@
+* AC timing parameters of DDR memories for a given speed-bin
+ At the moment properties for only LPDDR2 and DDR3 have been added
+
+Required properties:
+- min-freq : minimum DDR clock frequency for the speed-bin
+- max-freq : maximum DDR clock frequency for the speed-bin
+
+Optional properties:
+
+The following properties represent AC timing parameters from the memory
+data-sheet of the device for a given speed-bin. All these properties are
+of type <u32> and "-ps", "-ns", "-nCK" etc in the name indicates the
+unit of the corresponding parameter:
+ ps - pico seconds
+ ns - nano seconds
+ nCK - number of DDR clock cycles
+
+- tRCD-ps
+- tWR-ps
+- tRAS-min-ps
+- tRRD-ps
+- tWTR-ps
+- tXP-ps
+- tRTP-ps
+- tDQSCK-max-ps
+- tFAW-ps
+- tZQCS-ps
+- tZQinit-ps
+- tRP-ps /* DDR3 only */
+- tRC-ps /* DDR3 only */
+- tXSDLL-nCK /* DDR3 only */
+- tCKE-ps /* DDR3 only */
+- tZQoper-ps /* DDR3 only */
+- tRPab-ps /* LPDDR2 only */
+- tZQCL-ps /* LPDDR2 only */
+- tCKESR-ps /* LPDDR2 only */
+- tRAS-max-ns /* LPDDR2 only */
+
+Example:
+
+timings_elpida_2GS4_400mhz: ddr-timings {
+ min-freq = <10000000>;
+ max-freq = <400000000>;
+ tRPab-ps = <21000>;
+ tRCD-ps = <18000>;
+ tWR-ps = <15000>;
+ tRAS-min-ps = <42000:;
+ tRRD-ps = <10000>;
+ tWTR-ps = <7500>;
+ tXP-ps = <7500>;
+ tRTP-ps = <7500>;
+ tCKESR-ps = <15000>;
+ tDQSCK-max-ps = <5500>;
+ tFAW-ps = <50000>;
+ tZQCS-ps = <90000>;
+ tZQCL-ps = <360000>;
+ tZQinit-ps = <1000000>;
+ tRAS-max-ns = <70000>;
+};
+
--
1.7.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [RFC PATCH 2/3] dt: device tree bindings for TI's EMIF sdram controller
[not found] ` <1324128052-11220-1-git-send-email-aneesh-l0cyMroinI0@public.gmane.org>
2011-12-17 13:20 ` [RFC PATCH 1/3] dt: device tree bindings for DDR memories Aneesh V
@ 2011-12-17 13:20 ` Aneesh V
2011-12-17 13:20 ` [RFC PATCH 3/3] dt: EMIF and lpddr2 device tree data for OMAP4 boards Aneesh V
2 siblings, 0 replies; 4+ messages in thread
From: Aneesh V @ 2011-12-17 13:20 UTC (permalink / raw)
To: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-patch-review-uAqBSO/uNfhBDgjK7y7TUQ
Cc: Aneesh V, santosh.shilimkar-l0cyMroinI0
EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it.
Cc: Rajendra Nayak <rnayak-l0cyMroinI0@public.gmane.org>
Cc: Benoit Cousson <b-cousson-l0cyMroinI0@public.gmane.org>
Signed-off-by: Aneesh V <aneesh-l0cyMroinI0@public.gmane.org>
---
.../bindings/memory-controllers/ti/emif.txt | 64 ++++++++++++++++++++
1 files changed, 64 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
new file mode 100644
index 0000000..03de3e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -0,0 +1,64 @@
+* EMIF family of TI SDRAM controllers
+
+EMIF - External Memory Interface - is an SDRAM controller used in
+TI SoCs. EMIF supports, based on the IP revision, one or more of
+DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
+of the EMIF IP and memory parts attached to it.
+
+Required properties:
+- compatible : One or more of "ti,emif-ddr2", "ti,emif-ddr3", and
+ "ti,emif-lpddr2"
+
+ "ti,emif-ddr2" should be listed of the EMIF controller on this SoC
+ supports DDR2 memories
+
+ "ti,emif-ddr3" should be listed of the EMIF controller on this SoC
+ supports DDR3 memories
+
+ "ti,emif-lpddr2" should be listed of the EMIF controller on this SoC
+ supports LPDDR2 memories
+
+- ti,hwmods : For TI hwmods processing and omap device creation
+ the value shall be "emif<n>" where <n> is the number of the EMIF
+ instance with base 1.
+
+- phy-type : string indicating the phy type. Should be one of the
+ following:
+
+ "phy-type-omap4" : PHY used in OMAP4 family of SoCs
+
+ "phy-type-dm81xx" : PHY used in DM81XX family of SoCs
+
+- ddr-handle : phandle to a "ddr" node representing the memory part
+ attached to this EMIF instance.
+
+Optional properties:
+- cs1-used : Have this property if CS1 of this EMIF
+ instance has a memory part attached to it. If there is a memory
+ part attached to CS1, it should be the same type as the one on CS0,
+ so there is no need to give the details of this memory part.
+
+- cal-resistor-per-cs : Have this property if the board has one
+ calibration resistor per chip-select.
+
+- hw-caps-read-idle-ctrl: Have this property if the controller
+ supports read idle window programming
+
+- hw-caps-ll-interface : Have this property if the controller
+ has a low latency interface and corresponding interrupt events
+
+- hw-caps-temp-alert : Have this property if the controller
+ has capability for generating SDRAM temperature alerts
+
+Example:
+
+emif1: emif@0x4c000000 {
+ compatible = "ti,emif-lpddr2";
+ ti,hwmods = "emif2";
+ phy-type = "phy-type-omap4";
+ ddr-handle = <&elpida_2GS4>;
+ cs1-used;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+};
--
1.7.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [RFC PATCH 3/3] dt: EMIF and lpddr2 device tree data for OMAP4 boards
[not found] ` <1324128052-11220-1-git-send-email-aneesh-l0cyMroinI0@public.gmane.org>
2011-12-17 13:20 ` [RFC PATCH 1/3] dt: device tree bindings for DDR memories Aneesh V
2011-12-17 13:20 ` [RFC PATCH 2/3] dt: device tree bindings for TI's EMIF sdram controller Aneesh V
@ 2011-12-17 13:20 ` Aneesh V
2 siblings, 0 replies; 4+ messages in thread
From: Aneesh V @ 2011-12-17 13:20 UTC (permalink / raw)
To: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-patch-review-uAqBSO/uNfhBDgjK7y7TUQ
Cc: Aneesh V, santosh.shilimkar-l0cyMroinI0
Device tree data for the EMIF sdram controllers in OMAP4
and DDR memories attached to OMAP4 boards.
Cc: Rajendra Nayak <rnayak-l0cyMroinI0@public.gmane.org>
Cc: Benoit Cousson <b-cousson-l0cyMroinI0@public.gmane.org>
Signed-off-by: Aneesh V <aneesh-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/omap-common-devices.dtsi | 64 ++++++++++++++++++++++++++++
arch/arm/boot/dts/omap4-panda.dts | 13 ++++++
arch/arm/boot/dts/omap4-sdp.dts | 13 ++++++
arch/arm/boot/dts/omap4.dtsi | 18 ++++++++
4 files changed, 108 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/omap-common-devices.dtsi
diff --git a/arch/arm/boot/dts/omap-common-devices.dtsi b/arch/arm/boot/dts/omap-common-devices.dtsi
new file mode 100644
index 0000000..6cf3dfa
--- /dev/null
+++ b/arch/arm/boot/dts/omap-common-devices.dtsi
@@ -0,0 +1,64 @@
+/*
+ * Common devices used in different OMAP boards
+ */
+
+/ {
+ elpida_2GS4: ddr {
+ compatible = "jedec,lpddr2-s4";
+ density = "2Gb";
+ io-width = "x32";
+ manufacturer = "Elpida";
+
+ tRPab-min-tck = <3>;
+ tRCD-min-tck = <3>;
+ tWR-min-tck = <3>;
+ tRASmin-min-tck = <3>;
+ tRRD-min-tck = <2>;
+ tWTR-min-tck = <2>;
+ tXP-min-tck = <2>;
+ tRTP-min-tck = <2>;
+ tCKE-min-tck = <3>;
+ tCKESR-min-tck = <3>;
+ tFAW-min-tck = <8>;
+
+ timings_elpida_2GS4_400mhz: ddr-timings@1 {
+ min-freq = <10000000>;
+ max-freq = <400000000>;
+ tRPab-ps = <21000>;
+ tRCD-ps = <18000>;
+ tWR-ps = <15000>;
+ tRAS-min-ps = <42000>;
+ tRRD-ps = <10000>;
+ tWTR-ps = <7500>;
+ tXP-ps = <7500>;
+ tRTP-ps = <7500>;
+ tCKESR-ps = <15000>;
+ tDQSCK-max-ps = <5500>;
+ tFAW-ps = <50000>;
+ tZQCS-ps = <90000>;
+ tZQCL-ps = <360000>;
+ tZQinit-ps = <1000000>;
+ tRAS-max-ns = <70000>;
+ };
+
+ timings_elpida_2GS4_200mhz: ddr-timings@ {
+ min-freq = <10000000>;
+ max-freq = <200000000>;
+ tRPab-ps = <21000>;
+ tRCD-ps = <18000>;
+ tWR-ps = <15000>;
+ tRAS-min-ps = <42000>;
+ tRRD-ps = <10000>;
+ tWTR-ps = <10000>;
+ tXP-ps = <7500>;
+ tRTP-ps = <7500>;
+ tCKESR-ps = <15000>;
+ tDQSCK-max-ps = <5500>;
+ tFAW-ps = <50000>;
+ tZQCS-ps = <90000>;
+ tZQCL-ps = <360000>;
+ tZQinit-ps = <1000000>;
+ tRAS-max-ns = <70000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index c702657..69ff0de 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -8,6 +8,7 @@
/dts-v1/;
/include/ "omap4.dtsi"
+/include/ "omap-common-devices.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
@@ -26,4 +27,16 @@
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
+
+ ocp {
+ emif1: emif@0x4c000000 {
+ cs1-used;
+ ddr-handle = <&elpida_2GS4>;
+ };
+
+ emif2: emif@0x4d000000 {
+ cs1-used;
+ ddr-handle = <&elpida_2GS4>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 066e28c..1481e98 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -8,6 +8,7 @@
/dts-v1/;
/include/ "omap4.dtsi"
+/include/ "omap-common-devices.dtsi"
/ {
model = "TI OMAP4 SDP board";
@@ -26,4 +27,16 @@
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
+
+ ocp {
+ emif1: emif@0x4c000000 {
+ cs1-used;
+ ddr-handle = <&elpida_2GS4>;
+ };
+
+ emif2: emif@0x4d000000 {
+ cs1-used;
+ ddr-handle = <&elpida_2GS4>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4c61c82..4e88ea5 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -99,5 +99,23 @@
reg = <0x48241000 0x1000>,
<0x48240100 0x0100>;
};
+
+ emif1: emif@0x4c000000 {
+ compatible = "ti,emif-lpddr2";
+ ti,hwmods = "emif1";
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ emif2: emif@0x4d000000 {
+ compatible = "ti,emif-lpddr2";
+ ti,hwmods = "emif2";
+ phy-type = "phy-type-omap4";
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
};
};
--
1.7.1
^ permalink raw reply related [flat|nested] 4+ messages in thread