[U-Boot] [PREVIEW] LL TEMAC v10 refactored -- for evaluation only

[U-Boot] [PREVIEW] LL TEMAC v10 refactored -- for evaluation only

[Stephan Linz]

Hi Michal,

back to your requests and objections I've built up a new patch set for
evaluation. Some of the changes relate to the Microblaze platform rather
than the network driver.

1) U-Boot configuration variables vs. xparameters.h
----------------------------------------------------------------------
I've tried to find a compromise between the U-Boot coding and
configuration style and your preference. But at least in the point of
the many many CPP conditional directives I can not reduce the code. I
can move the code only to another place. I need a converstion from the
automaticaly generated content of xparameters.h to the U-Boot
configuration space. Now you can find this conversion matrix in a new
platform header, xconversions.h -- I've placed the header in
board/xilinx/microblaze-generic/ I think, we can find a better place.

The conversion matrix avoids all the wrong configuration variables
inside U-Boot code beginning with XILINX_ (and not CONFIG_) and we can
expand the configuration to new software related options we never get
from hardware (example special interface naming). This mechanism can
also be used by other driver and platform code, for example
arch/microblaze/cpu/cache.c and arch/microblaze/lib/bootm.c (use
XILINX_USE_DCACHE instead of ex. CONFIG_XILINX_DCACHE),
common/cmd_mfsl.c (use XILINX_FSL_NUMBER instead of ex.
CONFIG_XILINX_FSL), serial_xuartlite.c (use XILINX_UARTLITE_BASEADDR,
XILINX_UARTLITE_BASEADDR1, ...), and probably also in xilinx_emaclite.c
and xilinx_axi_emac.c when we extand a multi-IP support as we have done
for the LL TEMAC now. Sure we have to work on, but it's another case (I
can make some patches if you want)

Another but not currently existing feasibility would be to generate a
U-Boot conform xparameters.h, for example
CONFIG_XILINX_LL_TEMAC0_BASE_ADDR instead of XILINX_LLTEMAC_BASEADDR.
You and I, we have it in hand. We can change the Xilinx BSP in the near
future. You in PataLinux and I in my own home-brewed BSP generator TPOS.

2) Standard initialization vs. multiple direct calls from platform
----------------------------------------------------------------------
Returning to the topic "standard" initialization. The last patch will
show the differences bwetween your prefered way to do all in board init
and my applicable standard initializition (a single call to the driver).
Please look at it in the code and decide for yourself.

We need a forward-looking decision, what kind of initialization, we want
to use. Do we want to copy and paste the standard initialization steps
from ip core to ip core (board init) and from platform to platform
(Microplace, PPC405, PPC440) or make a simple call to the driver?

My preferences is to call the driver from platform and let him run all
the necessary steps, that I do not want knowing on platform side.


-- 
Best regards,
Stephan Linz
______________________________________________________________________________
MB-Ref: http://www.li-pro.de/xilinx_mb:mbref:start
OpenDCC: http://www.li-pro.net/opendcc.phtml
PC/M: http://www.li-pro.net/pcm.phtml
Sourceforge: http://sourceforge.net/users/slz
Gitorious: https://gitorious.org/~slz

[U-Boot] [PATCH 1/8] net: ll_temac: Add LL TEMAC driver to u-boot

[Stephan Linz]

Xilinx LocalLink Tri-Mode Ether MAC driver can be
used by Xilinx Microblaze or Xilinx ppc405/440 in
SDMA and FIFO mode. DCR or XPS bus can be used.

The driver uses and requires MII and PHYLIB.

CP: 4 warnings: 'Use of volatile is usually wrong'
I won't fix this, because it depends on the network
driver subsystem.

Reported-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Stephan Linz <linz@li-pro.net>
---
 drivers/net/Makefile               |    2 +
 drivers/net/xilinx_ll_temac.c      |  433 ++++++++++++++++++++++++++++++++++++
 drivers/net/xilinx_ll_temac_fifo.c |  143 ++++++++++++
 drivers/net/xilinx_ll_temac_mdio.c |  180 +++++++++++++++
 drivers/net/xilinx_ll_temac_sdma.c |  370 ++++++++++++++++++++++++++++++
 include/netdev.h                   |    1 +
 include/xilinx_ll_temac.h          |  358 +++++++++++++++++++++++++++++
 include/xilinx_ll_temac_fifo.h     |  122 ++++++++++
 include/xilinx_ll_temac_mdio.h     |   53 +++++
 include/xilinx_ll_temac_sdma.h     |  281 +++++++++++++++++++++++
 10 files changed, 1943 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/xilinx_ll_temac.c
 create mode 100644 drivers/net/xilinx_ll_temac_fifo.c
 create mode 100644 drivers/net/xilinx_ll_temac_mdio.c
 create mode 100644 drivers/net/xilinx_ll_temac_sdma.c
 create mode 100644 include/xilinx_ll_temac.h
 create mode 100644 include/xilinx_ll_temac_fifo.h
 create mode 100644 include/xilinx_ll_temac_mdio.h
 create mode 100644 include/xilinx_ll_temac_sdma.h

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index f4f7ea3..430f90c 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -77,6 +77,8 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o
 COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
 COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
 COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
+COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
+		xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
 
 COBJS	:= $(sort $(COBJS-y))
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c
new file mode 100644
index 0000000..28bc4cd
--- /dev/null
+++ b/drivers/net/xilinx_ll_temac.c
@@ -0,0 +1,433 @@
+/*
+ * Xilinx xps_ll_temac ethernet driver for u-boot
+ *
+ * supports SDMA or FIFO access and MDIO bus communication
+ *
+ * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
+ * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2008 - 2011 PetaLogix
+ *
+ * Based on Yoshio Kashiwagi kashiwagi at co-nss.co.jp driver
+ * Copyright (C) 2008 Nissin Systems Co.,Ltd.
+ * March 2008 created
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [S]:	[0]/ip_documentation/xps_ll_temac.pdf
+ * [A]:	[0]/application_notes/xapp1041.pdf
+ */
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <miiphy.h>
+
+#include <xilinx_ll_temac.h>
+#include <xilinx_ll_temac_fifo.h>
+#include <xilinx_ll_temac_sdma.h>
+#include <xilinx_ll_temac_mdio.h>
+
+#if !defined(CONFIG_MII)
+# error "LL_TEMAC requires MII -- missing CONFIG_MII"
+#endif
+
+#if !defined(CONFIG_PHYLIB)
+# error "LL_TEMAC requires PHYLIB -- missing CONFIG_PHYLIB"
+#endif
+
+/* Ethernet interface ready status */
+int ll_temac_check_status(struct temac_reg *regs, u32 mask)
+{
+	unsigned timeout = 50;	/* 1usec * 50 = 50usec */
+
+	/*
+	 * Quote from LL TEMAC documentation: The bits in the RDY
+	 * register are asserted when there is no access in progress.
+	 * When an access is in progress, a bit corresponding to the
+	 * type of access is automatically de-asserted. The bit is
+	 * automatically re-asserted when the access is complete.
+	 */
+	while (timeout && (!(in_be32(&regs->rdy) & mask))) {
+		timeout--;
+		udelay(1);
+	}
+
+	if (!timeout) {
+		printf("%s: Timeout on 0x%08x @%p\n", __func__,
+				mask, &regs->rdy);
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Indirect write to ll_temac.
+ *
+ * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
+ * page 23, second paragraph, The use of CTL0 register or CTL1 register
+ */
+int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data)
+{
+	out_be32(&regs->lsw, (reg_data & MLSW_MASK));
+	out_be32(&regs->ctl, CTL_WEN | (regn & CTL_ADDR_MASK));
+
+	if (ll_temac_check_status(regs, RSE_CFG_WR))
+		return 0;
+
+	return 1;
+}
+
+/*
+ * Indirect read from ll_temac.
+ *
+ * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
+ * page 23, second paragraph, The use of CTL0 register or CTL1 register
+ */
+int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data)
+{
+	out_be32(&regs->ctl, (regn & CTL_ADDR_MASK));
+
+	if (ll_temac_check_status(regs, RSE_CFG_RR))
+		return 0;
+
+	*reg_data = in_be32(&regs->lsw) & MLSW_MASK;
+	return 1;
+}
+
+/* setting sub-controller and ll_temac to proper setting */
+static int ll_temac_setup_ctrl(struct eth_device *dev)
+{
+	struct ll_temac *ll_temac = dev->priv;
+	struct temac_reg *regs = (struct temac_reg *)dev->iobase;
+
+	if (ll_temac->ctrlreset && ll_temac->ctrlreset(dev))
+		return 0;
+
+	if (ll_temac->ctrlinit && ll_temac->ctrlinit(dev))
+		return 0;
+
+	/* Promiscuous mode disable */
+	if (!ll_temac_indirect_set(regs, TEMAC_AFM, 0))
+		return 0;
+
+	/* Enable Receiver - RX bit */
+	if (!ll_temac_indirect_set(regs, TEMAC_RCW1, RCW1_RX))
+		return 0;
+
+	/* Enable Transmitter - TX bit */
+	if (!ll_temac_indirect_set(regs, TEMAC_TC, TC_TX))
+		return 0;
+
+	return 1;
+}
+
+/*
+ * Configure ll_temac based on negotiated speed and duplex
+ * reported by PHY handling code
+ */
+static int ll_temac_adjust_link(struct eth_device *dev)
+{
+	unsigned int speed, emmc_reg;
+	struct temac_reg *regs = (struct temac_reg *)dev->iobase;
+	struct ll_temac *ll_temac = dev->priv;
+	struct phy_device *phydev = ll_temac->phydev;
+
+	if (!phydev->link) {
+		printf("%s: No link.\n", phydev->dev->name);
+		return 0;
+	}
+
+	switch (phydev->speed) {
+	case 1000:
+		speed = EMMC_LSPD_1000;
+		break;
+	case 100:
+		speed = EMMC_LSPD_100;
+		break;
+	case 10:
+		speed = EMMC_LSPD_10;
+		break;
+	default:
+		return 0;
+	}
+
+	if (!ll_temac_indirect_get(regs, TEMAC_EMMC, &emmc_reg))
+		return 0;
+
+	emmc_reg &= ~EMMC_LSPD_MASK;
+	emmc_reg |= speed;
+
+	if (!ll_temac_indirect_set(regs, TEMAC_EMMC, emmc_reg))
+		return 0;
+
+	printf("%s: PHY is %s with %dbase%s, %s%s\n",
+			dev->name, phydev->drv->name,
+			phydev->speed, (phydev->port == PORT_TP) ? "T" : "X",
+			(phydev->duplex) ? "FDX" : "HDX",
+			(phydev->port == PORT_OTHER) ? ", unkown mode" : "");
+
+	return 1;
+}
+
+/* setup mac addr */
+static int ll_temac_setup_mac_addr(struct eth_device *dev)
+{
+	struct temac_reg *regs = (struct temac_reg *)dev->iobase;
+	u32 val;
+
+	/* set up unicast MAC address filter */
+	val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
+			(dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
+	val &= UAW0_UADDR_MASK;
+
+	if (!ll_temac_indirect_set(regs, TEMAC_UAW0, val))
+		return 1;
+
+	val = ((dev->enetaddr[5] << 8) | dev->enetaddr[4]);
+	val &= UAW1_UADDR_MASK;
+
+	if (!ll_temac_indirect_set(regs, TEMAC_UAW1, val))
+		return 1;
+
+	return 0;
+}
+
+/* halt device */
+static void ll_temac_halt(struct eth_device *dev)
+{
+	struct ll_temac *ll_temac = dev->priv;
+	struct temac_reg *regs = (struct temac_reg *)dev->iobase;
+
+	/* Disable Receiver */
+	ll_temac_indirect_set(regs, TEMAC_RCW0, 0);
+
+	/* Disable Transmitter */
+	ll_temac_indirect_set(regs, TEMAC_TC, 0);
+
+	if (ll_temac->ctrlhalt)
+		ll_temac->ctrlhalt(dev);
+
+	/* Shut down the PHY, as needed */
+	phy_shutdown(ll_temac->phydev);
+}
+
+static int ll_temac_init(struct eth_device *dev, bd_t *bis)
+{
+	struct ll_temac *ll_temac = dev->priv;
+
+	printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n",
+		dev->name, dev->index, dev->iobase);
+
+	if (!ll_temac_setup_ctrl(dev))
+		return -1;
+
+	/* Start up the PHY */
+	phy_startup(ll_temac->phydev);
+
+	if (!ll_temac_adjust_link(dev)) {
+		ll_temac_halt(dev);
+		return -1;
+	}
+
+	/* If there's no link, fail */
+	return ll_temac->phydev->link ? 0 : -1;
+}
+
+/*
+ * Discover which PHY is attached to the device, and configure it
+ * properly.  If the PHY is not recognized, then return 0
+ * (failure).  Otherwise, return 1
+ */
+static int ll_temac_phy_init(struct eth_device *dev)
+{
+	struct ll_temac *ll_temac = dev->priv;
+	struct phy_device *phydev;
+	unsigned int supported = PHY_GBIT_FEATURES;
+
+	/* interface - look at driver/net/tsec.c */
+	phydev = phy_connect(ll_temac->bus, ll_temac->phyaddr,
+			dev, PHY_INTERFACE_MODE_NONE);
+
+	phydev->supported &= supported;
+	phydev->advertising = phydev->supported;
+
+	ll_temac->phydev = phydev;
+
+	phy_config(phydev);
+
+	return 1;
+}
+
+/*
+ * Initialize a single ll_temac devices
+ *
+ * Returns the result of ll_temac phy interface that were initialized
+ */
+int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf)
+{
+	struct eth_device *dev;
+	struct ll_temac *ll_temac;
+
+	dev = calloc(1, sizeof(*dev));
+	if (dev == NULL)
+		return 0;
+
+	ll_temac = calloc(1, sizeof(struct ll_temac));
+	if (ll_temac == NULL) {
+		free(dev);
+		return 0;
+	}
+
+	/* use given name or generate its own unique name */
+	if (devinf->devname) {
+		strncpy(dev->name, devinf->devname, NAMESIZE);
+	} else {
+		snprintf(dev->name, NAMESIZE, "lltemac.%lx", devinf->base_addr);
+		devinf->devname = dev->name;
+	}
+
+	dev->iobase = devinf->base_addr;
+
+	dev->priv = ll_temac;
+	dev->init = ll_temac_init;
+	dev->halt = ll_temac_halt;
+	dev->write_hwaddr = ll_temac_setup_mac_addr;
+
+	ll_temac->ctrladdr = devinf->ctrl_addr;
+	if (devinf->flags & LL_TEMAC_M_SDMA_PLB) {
+#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405)
+		if (devinf->flags & LL_TEMAC_M_SDMA_DCR) {
+			ll_temac_collect_xldcr_sdma_reg_addr(dev);
+			ll_temac->in32 = ll_temac_xldcr_in32;
+			ll_temac->out32 = ll_temac_xldcr_out32;
+		} else
+#endif
+		{
+			ll_temac_collect_xlplb_sdma_reg_addr(dev);
+			ll_temac->in32 = ll_temac_xlplb_in32;
+			ll_temac->out32 = ll_temac_xlplb_out32;
+		}
+		ll_temac->ctrlinit = ll_temac_init_sdma;
+		ll_temac->ctrlhalt = ll_temac_halt_sdma;
+		ll_temac->ctrlreset = ll_temac_reset_sdma;
+		dev->recv = ll_temac_recv_sdma;
+		dev->send = ll_temac_send_sdma;
+	} else {
+		ll_temac->in32 = NULL;
+		ll_temac->out32 = NULL;
+		ll_temac->ctrlinit = NULL;
+		ll_temac->ctrlhalt = NULL;
+		ll_temac->ctrlreset = ll_temac_reset_fifo;
+		dev->recv = ll_temac_recv_fifo;
+		dev->send = ll_temac_send_fifo;
+	}
+
+	/* Link to specified MDIO bus */
+	strncpy(ll_temac->mdio_busname, devinf->mdio_busname, MDIO_NAME_LEN);
+	ll_temac->bus = miiphy_get_dev_by_name(ll_temac->mdio_busname);
+
+	/* Looking for a valid PHY address if it is not yet set */
+	if (devinf->phyaddr == -1)
+		ll_temac->phyaddr = ll_temac_phy_addr(ll_temac->bus);
+	else
+		ll_temac->phyaddr = devinf->phyaddr;
+
+	eth_register(dev);
+
+	/* Try to initialize PHY here, and return */
+	return ll_temac_phy_init(dev);
+}
+
+/*
+ * Initialize a single ll_temac device with its mdio bus behind ll_temac
+ *
+ * Returns 1 if the ll_temac device and the mdio bus were initialized
+ * otherwise returns 0
+ */
+static int xilinx_ll_temac_eth_init(bd_t *bis, struct ll_temac_info *devinf)
+{
+	struct ll_temac_mdio_info mdioinf;
+	int ret;
+
+	mdioinf.name = devinf->mdio_busname;
+	mdioinf.regs = (struct temac_reg *)devinf->base_addr;
+
+	ret = xilinx_ll_temac_mdio_initialize(bis, &mdioinf);
+	if (ret >= 0) {
+
+		/*
+		 * If there was no MDIO bus name then take over the
+		 * new automaticaly generated by the MDIO init code.
+		 */
+		if (mdioinf.name != devinf->mdio_busname)
+			devinf->mdio_busname = mdioinf.name;
+
+		ret = xilinx_ll_temac_initialize(bis, devinf);
+		if (ret > 0)
+			return 1;
+
+	}
+
+	return 0;
+}
+
+/*
+ * Initialize all the ll_temac devices
+ *
+ * Returns the number of ll_temac devices that were initialized
+ */
+int xilinx_ll_temac_standard_init(bd_t *bis)
+{
+	struct ll_temac_info devinf;
+	int count = 0;
+
+#if defined(CONFIG_XILINX_LL_TEMAC0_BASE_ADDR)
+	SET_STD_LL_TEMAC_INFO(devinf, 0);
+	count += xilinx_ll_temac_eth_init(bis, &devinf);
+#endif
+
+#if defined(CONFIG_XILINX_LL_TEMAC1_BASE_ADDR)
+	SET_STD_LL_TEMAC_INFO(devinf, 1);
+	count += xilinx_ll_temac_eth_init(bis, &devinf);
+#endif
+
+#if defined(CONFIG_XILINX_LL_TEMAC2_BASE_ADDR)
+	SET_STD_LL_TEMAC_INFO(devinf, 2);
+	count += xilinx_ll_temac_eth_init(bis, &devinf);
+#endif
+
+#if defined(CONFIG_XILINX_LL_TEMAC3_BASE_ADDR)
+	SET_STD_LL_TEMAC_INFO(devinf, 3);
+	count += xilinx_ll_temac_eth_init(bis, &devinf);
+#endif
+
+#if defined(CONFIG_XILINX_LL_TEMAC4_BASE_ADDR)
+	SET_STD_LL_TEMAC_INFO(devinf, 4);
+	count += xilinx_ll_temac_eth_init(bis, &devinf);
+#endif
+
+#if defined(CONFIG_XILINX_LL_TEMAC5_BASE_ADDR)
+	SET_STD_LL_TEMAC_INFO(devinf, 5);
+	count += xilinx_ll_temac_eth_init(bis, &devinf);
+#endif
+
+#if defined(CONFIG_XILINX_LL_TEMAC6_BASE_ADDR)
+	SET_STD_LL_TEMAC_INFO(devinf, 6);
+	count += xilinx_ll_temac_eth_init(bis, &devinf);
+#endif
+
+#if defined(CONFIG_XILINX_LL_TEMAC7_BASE_ADDR)
+	SET_STD_LL_TEMAC_INFO(devinf, 7);
+	count += xilinx_ll_temac_eth_init(bis, &devinf);
+#endif
+
+	return count;
+}
diff --git a/drivers/net/xilinx_ll_temac_fifo.c b/drivers/net/xilinx_ll_temac_fifo.c
new file mode 100644
index 0000000..99a287d
--- /dev/null
+++ b/drivers/net/xilinx_ll_temac_fifo.c
@@ -0,0 +1,143 @@
+/*
+ * Xilinx xps_ll_temac ethernet driver for u-boot
+ *
+ * FIFO sub-controller
+ *
+ * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
+ * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2008 - 2011 PetaLogix
+ *
+ * Based on Yoshio Kashiwagi kashiwagi at co-nss.co.jp driver
+ * Copyright (C) 2008 Nissin Systems Co.,Ltd.
+ * March 2008 created
+ *
+ * CREDITS: tsec driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [F]:	[0]/ip_documentation/xps_ll_fifo.pdf
+ * [S]:	[0]/ip_documentation/xps_ll_temac.pdf
+ * [A]:	[0]/application_notes/xapp1041.pdf
+ */
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+
+#include <asm/types.h>
+#include <asm/io.h>
+
+#include <xilinx_ll_temac.h>
+#include <xilinx_ll_temac_fifo.h>
+
+int ll_temac_reset_fifo(struct eth_device *dev)
+{
+	struct ll_temac *ll_temac = dev->priv;
+	struct fifo_ctrl *fifo_ctrl = (void *)ll_temac->ctrladdr;
+
+	out_be32(&fifo_ctrl->tdfr, LL_FIFO_TDFR_KEY);
+	out_be32(&fifo_ctrl->rdfr, LL_FIFO_RDFR_KEY);
+	out_be32(&fifo_ctrl->isr, ~0UL);
+	out_be32(&fifo_ctrl->ier, 0);
+
+	return 0;
+}
+
+int ll_temac_recv_fifo(struct eth_device *dev)
+{
+	int i, length = 0;
+	u32 *buf = (u32 *)NetRxPackets[0];
+	struct ll_temac *ll_temac = dev->priv;
+	struct fifo_ctrl *fifo_ctrl = (void *)ll_temac->ctrladdr;
+
+	if (in_be32(&fifo_ctrl->isr) & LL_FIFO_ISR_RC) {
+
+		/* reset isr */
+		out_be32(&fifo_ctrl->isr, ~0UL);
+
+		/*
+		 * MAYBE here:
+		 *   while (fifo_ctrl->isr);
+		 */
+
+		/*
+		 * The length is written (into RLR) by the XPS LL FIFO
+		 * when the packet is received across the RX LocalLink
+		 * interface and the receive data FIFO had enough
+		 * locations that all of the packet data has been saved.
+		 * The RLR should only be read when a receive packet is
+		 * available for processing (the receive occupancy is
+		 * not zero). Once the RLR is read, the receive packet
+		 * data should be read from the receive data FIFO before
+		 * the RLR is read again.
+		 *
+		 * [F] page 17, Receive Length Register (RLR)
+		 */
+		if (in_be32(&fifo_ctrl->rdfo) & LL_FIFO_RDFO_MASK) {
+			length = in_be32(&fifo_ctrl->rlf) & LL_FIFO_RLF_MASK;
+		} else {
+			printf("%s: Got error, no receive occupancy\n",
+					__func__);
+			return -1;
+		}
+
+		if (length > PKTSIZE_ALIGN) {
+			printf("%s: Got error, receive package too big (%i)\n",
+					__func__, length);
+			ll_temac_reset_fifo(dev);
+			return -1;
+		}
+
+		for (i = 0; i < length; i += 4)
+			*buf++ = in_be32(&fifo_ctrl->rdfd);
+
+		NetReceive(NetRxPackets[0], length);
+	}
+
+	return 0;
+}
+
+int ll_temac_send_fifo(struct eth_device *dev, volatile void *packet,
+							int length)
+{
+	int i;
+	u32 *buf = (u32 *)packet;
+	struct ll_temac *ll_temac = dev->priv;
+	struct fifo_ctrl *fifo_ctrl = (void *)ll_temac->ctrladdr;
+
+	if (length < LL_FIFO_TLF_MIN) {
+		printf("%s: Got error, transmit package too small (%i)\n",
+				__func__, length);
+		return -1;
+	}
+
+	if (length > LL_FIFO_TLF_MAX) {
+		printf("%s: Got error, transmit package too big (%i)\n",
+				__func__, length);
+		return -1;
+	}
+
+	for (i = 0; i < length; i += 4)
+		out_be32(&fifo_ctrl->tdfd, *buf++);
+
+	/*
+	 * Once the packet length is written to the TLR it is
+	 * automatically moved to the transmit data FIFO with
+	 * the packet data freeing up the TLR for another value.
+	 * The packet length must be written to the TLR after
+	 * the packet data is written to the transmit data FIFO.
+	 * It is not valid to write data for multiple packets
+	 * to the transmit data FIFO before writing the packet
+	 * length values.
+	 *
+	 * [F] page 17, Transmit Length Register (TLR)
+	 */
+	out_be32(&fifo_ctrl->tlf, length);
+
+	return 0;
+}
diff --git a/drivers/net/xilinx_ll_temac_mdio.c b/drivers/net/xilinx_ll_temac_mdio.c
new file mode 100644
index 0000000..52f9c2c
--- /dev/null
+++ b/drivers/net/xilinx_ll_temac_mdio.c
@@ -0,0 +1,180 @@
+/*
+ * Xilinx xps_ll_temac ethernet driver for u-boot
+ *
+ * MDIO bus access
+ *
+ * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
+ * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2008 - 2011 PetaLogix
+ *
+ * Based on Yoshio Kashiwagi kashiwagi at co-nss.co.jp driver
+ * Copyright (C) 2008 Nissin Systems Co.,Ltd.
+ * March 2008 created
+ *
+ * CREDITS: tsec driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [S]:	[0]/ip_documentation/xps_ll_temac.pdf
+ * [A]:	[0]/application_notes/xapp1041.pdf
+ */
+
+#include <config.h>
+#include <common.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <malloc.h>
+#include <asm/io.h>
+
+#include <xilinx_ll_temac.h>
+#include <xilinx_ll_temac_mdio.h>
+
+#if !defined(CONFIG_MII)
+# error "LL_TEMAC requires MII -- missing CONFIG_MII"
+#endif
+
+#if !defined(CONFIG_PHYLIB)
+# error "LL_TEMAC requires PHYLIB -- missing CONFIG_PHYLIB"
+#endif
+
+/*
+ * Prior to PHY access, the MDIO clock must be setup. This driver will set a
+ * safe default that should work with PLB bus speeds of up to 150 MHz and keep
+ * the MDIO clock below 2.5 MHz. If the user wishes faster access to the PHY
+ * then the clock divisor can be set to a different value by setting the
+ * correct bus speed value with CONFIG_XILINX_LL_TEMAC_CLK.
+ */
+#if !defined(CONFIG_XILINX_LL_TEMAC_CLK)
+#define MDIO_CLOCK_DIV		MC_CLKDIV_10(150000000)
+#else
+#define MDIO_CLOCK_DIV		MC_CLKDIV_25(CONFIG_XILINX_LL_TEMAC_CLK)
+#endif
+
+static int ll_temac_mdio_setup(struct mii_dev *bus)
+{
+	struct temac_reg *regs = (struct temac_reg *)bus->priv;
+
+	/* setup MDIO clock */
+	ll_temac_indirect_set(regs, TEMAC_MC,
+			MC_MDIOEN | (MDIO_CLOCK_DIV & MC_CLKDIV_MASK));
+
+	return 0;
+}
+
+/*
+ * Indirect MII PHY read via ll_temac.
+ *
+ * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
+ * page 67, Using the MII Management to Access PHY Registers
+ */
+int ll_temac_local_mdio_read(struct temac_reg *regs, int addr, int devad,
+				int regnum)
+{
+	out_be32(&regs->lsw,
+		((addr << LSW_PHYAD_POS) & LSW_PHYAD_MASK) |
+		(regnum & LSW_REGAD_MASK));
+	out_be32(&regs->ctl, TEMAC_MIIMAI);
+
+	ll_temac_check_status(regs, RSE_MIIM_RR);
+
+	return in_be32(&regs->lsw) & LSW_REGDAT_MASK;
+}
+
+/*
+ * Indirect MII PHY write via ll_temac.
+ *
+ * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
+ * page 67, Using the MII Management to Access PHY Registers
+ */
+void ll_temac_local_mdio_write(struct temac_reg *regs, int addr, int devad,
+				int regnum, u16 value)
+{
+	out_be32(&regs->lsw, (value & LSW_REGDAT_MASK));
+	out_be32(&regs->ctl, CTL_WEN | TEMAC_MIIMWD);
+
+	out_be32(&regs->lsw,
+		((addr << LSW_PHYAD_POS) & LSW_PHYAD_MASK) |
+		(regnum & LSW_REGAD_MASK));
+	out_be32(&regs->ctl, CTL_WEN | TEMAC_MIIMAI);
+
+	ll_temac_check_status(regs, RSE_MIIM_WR);
+}
+
+int ll_temac_phy_read(struct mii_dev *bus, int addr, int devad, int regnum)
+{
+	struct temac_reg *regs = (struct temac_reg *)bus->priv;
+
+	return ll_temac_local_mdio_read(regs, addr, devad, regnum);
+}
+
+int ll_temac_phy_write(struct mii_dev *bus, int addr, int devad, int regnum,
+			u16 value)
+{
+	struct temac_reg *regs = (struct temac_reg *)bus->priv;
+
+	ll_temac_local_mdio_write(regs, addr, devad, regnum, value);
+
+	return 0;
+}
+
+/*
+ * Use MII register 1 (MII status register) to detect PHY
+ *
+ * A Mask used to verify certain PHY features (register content)
+ * in the PHY detection register:
+ *  Auto-negotiation support, 10Mbps half/full duplex support
+ */
+#define PHY_DETECT_REG		MII_BMSR
+#define PHY_DETECT_MASK		(BMSR_10FULL | BMSR_10HALF | BMSR_ANEGCAPABLE)
+
+/* Looking for a valid PHY address */
+int ll_temac_phy_addr(struct mii_dev *bus)
+{
+	struct temac_reg *regs = (struct temac_reg *)bus->priv;
+	unsigned short val;
+	unsigned int phy;
+
+	for (phy = PHY_MAX_ADDR; phy >= 0; phy--) {
+		val = ll_temac_local_mdio_read(regs, phy, 0, PHY_DETECT_REG);
+		if ((val != 0xFFFF) &&
+		((val & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+			/* Found a valid PHY address */
+			return phy;
+		}
+	}
+
+	return -1;
+}
+
+int xilinx_ll_temac_mdio_initialize(bd_t *bis, struct ll_temac_mdio_info *info)
+{
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate LL_TEMAC MDIO bus: %s\n",
+				info->name);
+		return -1;
+	}
+
+	bus->read = ll_temac_phy_read;
+	bus->write = ll_temac_phy_write;
+	bus->reset = NULL;
+
+	/* use given name or generate its own unique name */
+	if (info->name) {
+		strncpy(bus->name, info->name, MDIO_NAME_LEN);
+	} else {
+		snprintf(bus->name, MDIO_NAME_LEN, "lltemii.%p", info->regs);
+		info->name = bus->name;
+	}
+
+	bus->priv = info->regs;
+
+	ll_temac_mdio_setup(bus);
+	return mdio_register(bus);
+}
diff --git a/drivers/net/xilinx_ll_temac_sdma.c b/drivers/net/xilinx_ll_temac_sdma.c
new file mode 100644
index 0000000..fc17bc5
--- /dev/null
+++ b/drivers/net/xilinx_ll_temac_sdma.c
@@ -0,0 +1,370 @@
+/*
+ * Xilinx xps_ll_temac ethernet driver for u-boot
+ *
+ * SDMA sub-controller
+ *
+ * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
+ * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2008 - 2011 PetaLogix
+ *
+ * Based on Yoshio Kashiwagi kashiwagi at co-nss.co.jp driver
+ * Copyright (C) 2008 Nissin Systems Co.,Ltd.
+ * March 2008 created
+ *
+ * CREDITS: tsec driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [M]:	[0]/ip_documentation/mpmc.pdf
+ * [S]:	[0]/ip_documentation/xps_ll_temac.pdf
+ * [A]:	[0]/application_notes/xapp1041.pdf
+ */
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+
+#include <asm/types.h>
+#include <asm/io.h>
+
+#include <xilinx_ll_temac.h>
+#include <xilinx_ll_temac_sdma.h>
+
+#define TX_BUF_CNT		2
+
+static unsigned int rx_idx;	/* index of the current RX buffer */
+static unsigned int tx_idx;	/* index of the current TX buffer */
+
+struct rtx_cdmac_bd {
+	struct cdmac_bd rx[PKTBUFSRX];
+	struct cdmac_bd tx[TX_BUF_CNT];
+};
+
+/*
+ * DMA Buffer Descriptor alignment
+ *
+ * If the address contained in the Next Descriptor Pointer register is not
+ * 8-word aligned or reaches beyond the range of available memory, the SDMA
+ * halts processing and sets the CDMAC_BD_STCTRL_ERROR bit in the respective
+ * status register (tx_chnl_sts or rx_chnl_sts).
+ *
+ * [1]: [0]/ip_documentation/mpmc.pdf
+ *      page 161, Next Descriptor Pointer
+ */
+static struct rtx_cdmac_bd cdmac_bd __aligned(32);
+
+#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405)
+
+/*
+ * Indirect DCR access operations mi{ft}dcr_xilinx() espacialy
+ * for Xilinx PowerPC implementations on FPGA.
+ *
+ * FIXME: This part should go up to arch/powerpc -- but where?
+ */
+#include <asm/processor.h>
+#define XILINX_INDIRECT_DCR_ADDRESS_REG	0
+#define XILINX_INDIRECT_DCR_ACCESS_REG	1
+inline unsigned mifdcr_xilinx(const unsigned dcrn)
+{
+	mtdcr(XILINX_INDIRECT_DCR_ADDRESS_REG, dcrn);
+	return mfdcr(XILINX_INDIRECT_DCR_ACCESS_REG);
+}
+inline void mitdcr_xilinx(const unsigned dcrn, int val)
+{
+	mtdcr(XILINX_INDIRECT_DCR_ADDRESS_REG, dcrn);
+	mtdcr(XILINX_INDIRECT_DCR_ACCESS_REG, val);
+}
+
+/* Xilinx Device Control Register (DCR) in/out accessors */
+inline unsigned ll_temac_xldcr_in32(phys_addr_t addr)
+{
+	return mifdcr_xilinx((const unsigned)addr);
+}
+inline void ll_temac_xldcr_out32(phys_addr_t addr, unsigned value)
+{
+	mitdcr_xilinx((const unsigned)addr, value);
+}
+
+void ll_temac_collect_xldcr_sdma_reg_addr(struct eth_device *dev)
+{
+	struct ll_temac *ll_temac = dev->priv;
+	phys_addr_t dmac_ctrl = ll_temac->ctrladdr;
+	phys_addr_t *ra = ll_temac->sdma_reg_addr;
+
+	ra[TX_NXTDESC_PTR]   = dmac_ctrl + TX_NXTDESC_PTR;
+	ra[TX_CURBUF_ADDR]   = dmac_ctrl + TX_CURBUF_ADDR;
+	ra[TX_CURBUF_LENGTH] = dmac_ctrl + TX_CURBUF_LENGTH;
+	ra[TX_CURDESC_PTR]   = dmac_ctrl + TX_CURDESC_PTR;
+	ra[TX_TAILDESC_PTR]  = dmac_ctrl + TX_TAILDESC_PTR;
+	ra[TX_CHNL_CTRL]     = dmac_ctrl + TX_CHNL_CTRL;
+	ra[TX_IRQ_REG]       = dmac_ctrl + TX_IRQ_REG;
+	ra[TX_CHNL_STS]      = dmac_ctrl + TX_CHNL_STS;
+	ra[RX_NXTDESC_PTR]   = dmac_ctrl + RX_NXTDESC_PTR;
+	ra[RX_CURBUF_ADDR]   = dmac_ctrl + RX_CURBUF_ADDR;
+	ra[RX_CURBUF_LENGTH] = dmac_ctrl + RX_CURBUF_LENGTH;
+	ra[RX_CURDESC_PTR]   = dmac_ctrl + RX_CURDESC_PTR;
+	ra[RX_TAILDESC_PTR]  = dmac_ctrl + RX_TAILDESC_PTR;
+	ra[RX_CHNL_CTRL]     = dmac_ctrl + RX_CHNL_CTRL;
+	ra[RX_IRQ_REG]       = dmac_ctrl + RX_IRQ_REG;
+	ra[RX_CHNL_STS]      = dmac_ctrl + RX_CHNL_STS;
+	ra[DMA_CONTROL_REG]  = dmac_ctrl + DMA_CONTROL_REG;
+}
+
+#endif /* CONFIG_XILINX_440 || ONFIG_XILINX_405 */
+
+/* Xilinx Processor Local Bus (PLB) in/out accessors */
+inline unsigned ll_temac_xlplb_in32(phys_addr_t addr)
+{
+	return in_be32((void *)addr);
+}
+inline void ll_temac_xlplb_out32(phys_addr_t addr, unsigned value)
+{
+	out_be32((void *)addr, value);
+}
+
+/* collect all register addresses for Xilinx PLB in/out accessors */
+void ll_temac_collect_xlplb_sdma_reg_addr(struct eth_device *dev)
+{
+	struct ll_temac *ll_temac = dev->priv;
+	struct sdma_ctrl *sdma_ctrl = (void *)ll_temac->ctrladdr;
+	phys_addr_t *ra = ll_temac->sdma_reg_addr;
+
+	ra[TX_NXTDESC_PTR]   = (phys_addr_t)&sdma_ctrl->tx_nxtdesc_ptr;
+	ra[TX_CURBUF_ADDR]   = (phys_addr_t)&sdma_ctrl->tx_curbuf_addr;
+	ra[TX_CURBUF_LENGTH] = (phys_addr_t)&sdma_ctrl->tx_curbuf_length;
+	ra[TX_CURDESC_PTR]   = (phys_addr_t)&sdma_ctrl->tx_curdesc_ptr;
+	ra[TX_TAILDESC_PTR]  = (phys_addr_t)&sdma_ctrl->tx_taildesc_ptr;
+	ra[TX_CHNL_CTRL]     = (phys_addr_t)&sdma_ctrl->tx_chnl_ctrl;
+	ra[TX_IRQ_REG]       = (phys_addr_t)&sdma_ctrl->tx_irq_reg;
+	ra[TX_CHNL_STS]      = (phys_addr_t)&sdma_ctrl->tx_chnl_sts;
+	ra[RX_NXTDESC_PTR]   = (phys_addr_t)&sdma_ctrl->rx_nxtdesc_ptr;
+	ra[RX_CURBUF_ADDR]   = (phys_addr_t)&sdma_ctrl->rx_curbuf_addr;
+	ra[RX_CURBUF_LENGTH] = (phys_addr_t)&sdma_ctrl->rx_curbuf_length;
+	ra[RX_CURDESC_PTR]   = (phys_addr_t)&sdma_ctrl->rx_curdesc_ptr;
+	ra[RX_TAILDESC_PTR]  = (phys_addr_t)&sdma_ctrl->rx_taildesc_ptr;
+	ra[RX_CHNL_CTRL]     = (phys_addr_t)&sdma_ctrl->rx_chnl_ctrl;
+	ra[RX_IRQ_REG]       = (phys_addr_t)&sdma_ctrl->rx_irq_reg;
+	ra[RX_CHNL_STS]      = (phys_addr_t)&sdma_ctrl->rx_chnl_sts;
+	ra[DMA_CONTROL_REG]  = (phys_addr_t)&sdma_ctrl->dma_control_reg;
+}
+
+/* Check for TX and RX channel errors. */
+static inline int ll_temac_sdma_error(struct eth_device *dev)
+{
+	int err;
+	struct ll_temac *ll_temac = dev->priv;
+	phys_addr_t *ra = ll_temac->sdma_reg_addr;
+
+	err = ll_temac->in32(ra[TX_CHNL_STS]) & CHNL_STS_ERROR;
+	err |= ll_temac->in32(ra[RX_CHNL_STS]) & CHNL_STS_ERROR;
+
+	return err;
+}
+
+int ll_temac_init_sdma(struct eth_device *dev)
+{
+	struct ll_temac *ll_temac = dev->priv;
+	struct cdmac_bd *rx_dp;
+	struct cdmac_bd *tx_dp;
+	phys_addr_t *ra = ll_temac->sdma_reg_addr;
+	int i;
+
+	printf("%s: SDMA: %d Rx buffers, %d Tx buffers\n",
+			dev->name, PKTBUFSRX, TX_BUF_CNT);
+
+	/* Initialize the Rx Buffer descriptors */
+	for (i = 0; i < PKTBUFSRX; i++) {
+		rx_dp = &cdmac_bd.rx[i];
+		memset(rx_dp, 0, sizeof(*rx_dp));
+		rx_dp->next_p = rx_dp;
+		rx_dp->buf_len = PKTSIZE_ALIGN;
+		rx_dp->phys_buf_p = (u8 *)NetRxPackets[i];
+		flush_cache((u32)rx_dp->phys_buf_p, PKTSIZE_ALIGN);
+	}
+	flush_cache((u32)cdmac_bd.rx, sizeof(cdmac_bd.rx));
+
+	/* Initialize the TX Buffer Descriptors */
+	for (i = 0; i < TX_BUF_CNT; i++) {
+		tx_dp = &cdmac_bd.tx[i];
+		memset(tx_dp, 0, sizeof(*tx_dp));
+		tx_dp->next_p = tx_dp;
+	}
+	flush_cache((u32)cdmac_bd.tx, sizeof(cdmac_bd.tx));
+
+	/* Reset index counter to the Rx and Tx Buffer descriptors */
+	rx_idx = tx_idx = 0;
+
+	/* initial Rx DMA start by writing to respective TAILDESC_PTR */
+	ll_temac->out32(ra[RX_CURDESC_PTR], (int)&cdmac_bd.rx[rx_idx]);
+	ll_temac->out32(ra[RX_TAILDESC_PTR], (int)&cdmac_bd.rx[rx_idx]);
+
+	return 0;
+}
+
+int ll_temac_halt_sdma(struct eth_device *dev)
+{
+	unsigned timeout = 50;	/* 1usec * 50 = 50usec */
+	struct ll_temac *ll_temac = dev->priv;
+	phys_addr_t *ra = ll_temac->sdma_reg_addr;
+
+	/*
+	 * Soft reset the DMA
+	 *
+	 * Quote from MPMC documentation: Writing a 1 to this field
+	 * forces the DMA engine to shutdown and reset itself. After
+	 * setting this bit, software must poll it until the bit is
+	 * cleared by the DMA. This indicates that the reset process
+	 * is done and the pipeline has been flushed.
+	 */
+	ll_temac->out32(ra[DMA_CONTROL_REG], DMA_CONTROL_RESET);
+	while (timeout && (ll_temac->in32(ra[DMA_CONTROL_REG])
+					& DMA_CONTROL_RESET)) {
+		timeout--;
+		udelay(1);
+	}
+
+	if (!timeout) {
+		printf("%s: Timeout\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int ll_temac_reset_sdma(struct eth_device *dev)
+{
+	u32 r;
+	struct ll_temac *ll_temac = dev->priv;
+	phys_addr_t *ra = ll_temac->sdma_reg_addr;
+
+	/* Soft reset the DMA.  */
+	if (ll_temac_halt_sdma(dev))
+		return -1;
+
+	/* Now clear the interrupts.  */
+	r = ll_temac->in32(ra[TX_CHNL_CTRL]);
+	r &= ~CHNL_CTRL_IRQ_MASK;
+	ll_temac->out32(ra[TX_CHNL_CTRL], r);
+
+	r = ll_temac->in32(ra[RX_CHNL_CTRL]);
+	r &= ~CHNL_CTRL_IRQ_MASK;
+	ll_temac->out32(ra[RX_CHNL_CTRL], r);
+
+	/* Now ACK pending IRQs.  */
+	ll_temac->out32(ra[TX_IRQ_REG], IRQ_REG_IRQ_MASK);
+	ll_temac->out32(ra[RX_IRQ_REG], IRQ_REG_IRQ_MASK);
+
+	/* Set tail-ptr mode, disable errors for both channels.  */
+	ll_temac->out32(ra[DMA_CONTROL_REG],
+			/* Enable use of tail pointer register */
+			DMA_CONTROL_TPE |
+			/* Disable error when 2 or 4 bit coalesce cnt overfl */
+			DMA_CONTROL_RXOCEID |
+			/* Disable error when 2 or 4 bit coalesce cnt overfl */
+			DMA_CONTROL_TXOCEID);
+
+	return 0;
+}
+
+int ll_temac_recv_sdma(struct eth_device *dev)
+{
+	int length, pb_idx;
+	struct cdmac_bd *rx_dp = &cdmac_bd.rx[rx_idx];
+	struct ll_temac *ll_temac = dev->priv;
+	phys_addr_t *ra = ll_temac->sdma_reg_addr;
+
+	if (ll_temac_sdma_error(dev)) {
+
+		if (ll_temac_reset_sdma(dev))
+			return -1;
+
+		ll_temac_init_sdma(dev);
+	}
+
+	flush_cache((u32)rx_dp, sizeof(*rx_dp));
+
+	if (!(rx_dp->sca.stctrl & CDMAC_BD_STCTRL_COMPLETED))
+		return 0;
+
+	if (rx_dp->sca.stctrl & (CDMAC_BD_STCTRL_SOP | CDMAC_BD_STCTRL_EOP)) {
+		pb_idx = rx_idx;
+		length = rx_dp->sca.app[4] & CDMAC_BD_APP4_RXBYTECNT_MASK;
+	} else {
+		pb_idx = -1;
+		length = 0;
+		printf("%s: Got part of package, unsupported (%x)\n",
+				__func__, rx_dp->sca.stctrl);
+	}
+
+	/* flip the buffer */
+	flush_cache((u32)rx_dp->phys_buf_p, length);
+
+	/* reset the current descriptor */
+	rx_dp->sca.stctrl = 0;
+	rx_dp->sca.app[4] = 0;
+	flush_cache((u32)rx_dp, sizeof(*rx_dp));
+
+	/* Find next empty buffer descriptor, preparation for next iteration */
+	rx_idx = (rx_idx + 1) % PKTBUFSRX;
+	rx_dp = &cdmac_bd.rx[rx_idx];
+	flush_cache((u32)rx_dp, sizeof(*rx_dp));
+
+	/* DMA start by writing to respective TAILDESC_PTR */
+	ll_temac->out32(ra[RX_CURDESC_PTR], (int)&cdmac_bd.rx[rx_idx]);
+	ll_temac->out32(ra[RX_TAILDESC_PTR], (int)&cdmac_bd.rx[rx_idx]);
+
+	if (length > 0 && pb_idx != -1)
+		NetReceive(NetRxPackets[pb_idx], length);
+
+	return 0;
+}
+
+int ll_temac_send_sdma(struct eth_device *dev, volatile void *packet,
+							int length)
+{
+	unsigned timeout = 50;	/* 1usec * 50 = 50usec */
+	struct cdmac_bd *tx_dp = &cdmac_bd.tx[tx_idx];
+	struct ll_temac *ll_temac = dev->priv;
+	phys_addr_t *ra = ll_temac->sdma_reg_addr;
+
+	if (ll_temac_sdma_error(dev)) {
+
+		if (ll_temac_reset_sdma(dev))
+			return -1;
+
+		ll_temac_init_sdma(dev);
+	}
+
+	tx_dp->phys_buf_p = (u8 *)packet;
+	tx_dp->buf_len = length;
+	tx_dp->sca.stctrl = CDMAC_BD_STCTRL_SOP | CDMAC_BD_STCTRL_EOP |
+			CDMAC_BD_STCTRL_STOP_ON_END;
+
+	flush_cache((u32)packet, length);
+	flush_cache((u32)tx_dp, sizeof(*tx_dp));
+
+	/* DMA start by writing to respective TAILDESC_PTR */
+	ll_temac->out32(ra[TX_CURDESC_PTR], (int)tx_dp);
+	ll_temac->out32(ra[TX_TAILDESC_PTR], (int)tx_dp);
+
+	/* Find next empty buffer descriptor, preparation for next iteration */
+	tx_idx = (tx_idx + 1) % TX_BUF_CNT;
+	tx_dp = &cdmac_bd.tx[tx_idx];
+
+	do {
+		flush_cache((u32)tx_dp, sizeof(*tx_dp));
+		udelay(1);
+	} while (timeout-- && !(tx_dp->sca.stctrl & CDMAC_BD_STCTRL_COMPLETED));
+
+	if (!timeout) {
+		printf("%s: Timeout\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/include/netdev.h b/include/netdev.h
index b0c21d5..bf95f88 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -102,6 +102,7 @@ int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
 							unsigned long dma_addr);
 int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
 							int txpp, int rxpp);
+int xilinx_ll_temac_standard_init(bd_t *bis);
 
 /* Boards with PCI network controllers can call this from their board_eth_init()
  * function to initialize whatever's on board.
diff --git a/include/xilinx_ll_temac.h b/include/xilinx_ll_temac.h
new file mode 100644
index 0000000..af4a09f
--- /dev/null
+++ b/include/xilinx_ll_temac.h
@@ -0,0 +1,358 @@
+/*
+ * Xilinx xps_ll_temac ethernet driver for u-boot
+ *
+ * LL_TEMAC interface
+ *
+ * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
+ * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2008 - 2011 PetaLogix
+ *
+ * Based on Yoshio Kashiwagi kashiwagi at co-nss.co.jp driver
+ * Copyright (C) 2008 Nissin Systems Co.,Ltd.
+ * March 2008 created
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [S]:	[0]/ip_documentation/xps_ll_temac.pdf
+ * [A]:	[0]/application_notes/xapp1041.pdf
+ */
+#ifndef _XILINX_LL_TEMAC_
+#define _XILINX_LL_TEMAC_
+
+#include <config.h>
+#include <net.h>
+#include <phy.h>
+#include <miiphy.h>
+
+#include <asm/types.h>
+#include <asm/byteorder.h>
+
+#include <xilinx_ll_temac_sdma.h>
+
+#if !defined(__BIG_ENDIAN)
+# error LL_TEMAC requires big endianess
+#endif
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+/* (re-)define PHY device address on primary interface */
+#define CONFIG_PHY0_ADDR		CONFIG_PHY_ADDR
+
+/* You can use this name macros to define the dafault names. */
+#define STD_LL_TEMAC_NAME(num)		"LLTEMAC" str(num)
+#define STD_LL_TEMAC_MII_NAME(num)	"LLTEMII" str(num)
+
+/* If you plan to use this macro, then all strings have to be a pointer. */
+#define SET_STD_LL_TEMAC_INFO(x, num) \
+do { \
+	x.devname = CONFIG_XILINX_LL_TEMAC##num##_NAME; \
+	x.base_addr = CONFIG_XILINX_LL_TEMAC##num##_BASE_ADDR; \
+	x.ctrl_addr = CONFIG_XILINX_LL_TEMAC##num##_CTRL_ADDR; \
+	x.flags = CONFIG_XILINX_LL_TEMAC##num##_CTRL_MODE; \
+	x.mdio_busname = CONFIG_XILINX_LL_TEMAC##num##_MII_NAME; \
+	x.phyaddr = CONFIG_PHY##num##_ADDR; \
+} while (0)
+
+/* If you plan to use this macro, then all configuration have to be constant. */
+#define STD_LL_TEMAC_INFO(num) \
+{ \
+	.devname = CONFIG_XILINX_LL_TEMAC##num##_NAME, \
+	.base_addr = CONFIG_XILINX_LL_TEMAC##num##_BASE_ADDR, \
+	.ctrl_addr = CONFIG_XILINX_LL_TEMAC##num##_CTRL_ADDR, \
+	.flags = CONFIG_XILINX_LL_TEMAC##num##_CTRL_MODE, \
+	.mdio_busname = CONFIG_XILINX_LL_TEMAC##num##_MII_NAME, \
+	.phyaddr = CONFIG_PHY##num##_ADDR, \
+}
+
+/*
+ * TEMAC Memory and Register Definition
+ *
+ * [1]:	[0]/ip_documentation/xps_ll_temac.pdf
+ *	page 19, Memory and Register Descriptions
+ */
+struct temac_reg {
+	/* direct soft registers (low part) */
+	u32 raf;	/* Reset and Address Filter */
+	u32 tpf;	/* Transmit Pause Frame */
+	u32 ifgp;	/* Transmit Inter Frame Gap Adjustment */
+	u32 is;		/* Interrupt Status */
+	u32 ip;		/* Interrupt Pending */
+	u32 ie;		/* Interrupt Enable */
+	u32 ttag;	/* Transmit VLAN Tag */
+	u32 rtag;	/* Receive VLAN Tag */
+	/* hard TEMAC registers */
+	u32 msw;	/* Most Significant Word Data */
+	u32 lsw;	/* Least Significant Word Data */
+	u32 ctl;	/* Control */
+	u32 rdy;	/* Ready Status */
+	/* direct soft registers (high part) */
+	u32 uawl;	/* Unicast Address Word Lower */
+	u32 uawu;	/* Unicast Address Word Upper */
+	u32 tpid0;	/* VLAN TPID Word 0 */
+	u32 tpid1;	/* VLAN TPID Word 1 */
+};
+
+/* Reset and Address Filter Registers (raf), [1] p25 */
+#define RAF_SR			(1 << 13)
+#define RAF_EMFE		(1 << 12)
+#define RAF_NFE			(1 << 11)
+#define RAF_RVSTM_POS		9
+#define RAF_RVSTM_MASK		(3 << RAF_RVSTM_POS)
+#define RAF_TVSTM_POS		7
+#define RAF_TVSTM_MASK		(3 << RAF_TVSTM_POS)
+#define RAF_RVTM_POS		5
+#define RAF_RVTM_MASK		(3 << RAF_RVTM_POS)
+#define RAF_TVTM_POS		3
+#define RAF_TVTM_MASK		(3 << RAF_TVTM_POS)
+#define RAF_BCREJ		(1 << 2)
+#define RAF_MCREJ		(1 << 1)
+#define RAF_HTRST		(1 << 0)
+
+/* Transmit Pause Frame Registers (tpf), [1] p28 */
+#define TPF_TPFV_POS		0
+#define TPF_TPFV_MASK		(0xFFFF << TPF_TPFV_POS)
+
+/* Transmit Inter Frame Gap Adjustment Registers (ifgp), [1] p28 */
+#define IFGP_POS		0
+#define IFGP_MASK		(0xFF << IFGP_POS)
+
+/* Interrupt Status, Pending, Enable Registers (is, ip, ie), [1] p29-33 */
+#define ISPE_MR			(1 << 7)
+#define ISPE_RDL		(1 << 6)
+#define ISPE_TC			(1 << 5)
+#define ISPE_RFO		(1 << 4)
+#define ISPE_RR			(1 << 3)
+#define ISPE_RC			(1 << 2)
+#define ISPE_AN			(1 << 1)
+#define ISPE_HAC		(1 << 0)
+
+/* Transmit, Receive VLAN Tag Registers (ttag, rtag), [1] p34-35 */
+#define TRTAG_TPID_POS		16
+#define TRTAG_TPID_MASK		(0xFFFF << TRTAG_TPID_POS)
+#define TRTAG_PRIO_POS		13
+#define TRTAG_PRIO_MASK		(7 << TRTAG_PRIO_POS)
+#define TRTAG_CFI		(1 << 12)
+#define TRTAG_VID_POS		0
+#define TRTAG_VID_MASK		(0xFFF << TRTAG_VID_POS)
+
+/* Most, Least Significant Word Data Register (msw, lsw), [1] p46 */
+#define MLSW_POS		0
+#define MLSW_MASK		(~0UL << MLSW_POS)
+
+/* LSW Data Register for PHY addresses (lsw), [1] p66 */
+#define LSW_REGAD_POS		0
+#define LSW_REGAD_MASK		(0x1F << LSW_REGAD_POS)
+#define LSW_PHYAD_POS		5
+#define LSW_PHYAD_MASK		(0x1F << LSW_PHYAD_POS)
+
+/* LSW Data Register for PHY data (lsw), [1] p66 */
+#define LSW_REGDAT_POS		0
+#define LSW_REGDAT_MASK		(0xFFFF << LSW_REGDAT_POS)
+
+/* Control Register (ctl), [1] p47 */
+#define CTL_WEN			(1 << 15)
+#define CTL_ADDR_POS		0
+#define CTL_ADDR_MASK		(0x3FF << CTL_ADDR_POS)
+
+/* Ready Status Register Ethernet (rdy), [1] p48 */
+#define RSE_HACS_RDY		(1 << 14)
+#define RSE_CFG_WR		(1 << 6)
+#define RSE_CFG_RR		(1 << 5)
+#define RSE_AF_WR		(1 << 4)
+#define RSE_AF_RR		(1 << 3)
+#define RSE_MIIM_WR		(1 << 2)
+#define RSE_MIIM_RR		(1 << 1)
+#define RSE_FABR_RR		(1 << 0)
+
+/* Unicast Address Word Lower, Upper Registers (uawl, uawu), [1] p35-36 */
+#define UAWL_UADDR_POS		0
+#define UAWL_UADDR_MASK		(~0UL << UAWL_UADDR_POS)
+#define UAWU_UADDR_POS		0
+#define UAWU_UADDR_MASK		(0xFFFF << UAWU_UADDR_POS)
+
+/* VLAN TPID Word 0, 1 Registers (tpid0, tpid1), [1] p37 */
+#define TPID0_V0_POS		0
+#define TPID0_V0_MASK		(0xFFFF << TPID0_V0_POS)
+#define TPID0_V1_POS		16
+#define TPID0_V1_MASK		(0xFFFF << TPID0_V1_POS)
+#define TPID1_V2_POS		0
+#define TPID1_V2_MASK		(0xFFFF << TPID1_V2_POS)
+#define TPID1_V3_POS		16
+#define TPID1_V3_MASK		(0xFFFF << TPID1_V3_POS)
+
+/*
+ * TEMAC Indirectly Addressable Register Index Enumeration
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [1]:	[0]/ip_documentation/xps_ll_temac.pdf
+ *	page 23, PLB Indirectly Addressable TEMAC Registers
+ */
+enum temac_ctrl {
+	TEMAC_RCW0	= 0x200,
+	TEMAC_RCW1	= 0x240,
+	TEMAC_TC	= 0x280,
+	TEMAC_FCC	= 0x2C0,
+	TEMAC_EMMC	= 0x300,
+	TEMAC_PHYC	= 0x320,
+	TEMAC_MC	= 0x340,
+	TEMAC_UAW0	= 0x380,
+	TEMAC_UAW1	= 0x384,
+	TEMAC_MAW0	= 0x388,
+	TEMAC_MAW1	= 0x38C,
+	TEMAC_AFM	= 0x390,
+	TEMAC_TIS	= 0x3A0,
+	TEMAC_TIE	= 0x3A4,
+	TEMAC_MIIMWD	= 0x3B0,
+	TEMAC_MIIMAI	= 0x3B4
+};
+
+/* Receive Configuration Word 0, 1 Registers (RCW0, RCW1), [1] p50-51 */
+#define RCW0_PADDR_POS		0
+#define RCW0_PADDR_MASK		(~0UL << RCW_PADDR_POS)
+#define RCW1_RST		(1 << 31)
+#define RCW1_JUM		(1 << 30)
+#define RCW1_FCS		(1 << 29)
+#define RCW1_RX			(1 << 28)
+#define RCW1_VLAN		(1 << 27)
+#define RCW1_HD			(1 << 26)
+#define RCW1_LT_DIS		(1 << 25)
+#define RCW1_PADDR_POS		0
+#define RCW1_PADDR_MASK		(0xFFFF << RCW_PADDR_POS)
+
+/* Transmit Configuration Registers (TC), [1] p52 */
+#define TC_RST			(1 << 31)
+#define TC_JUM			(1 << 30)
+#define TC_FCS			(1 << 29)
+#define TC_TX			(1 << 28)
+#define TC_VLAN			(1 << 27)
+#define TC_HD			(1 << 26)
+#define TC_IFG			(1 << 25)
+
+/* Flow Control Configuration Registers (FCC), [1] p54 */
+#define FCC_FCTX		(1 << 30)
+#define FCC_FCRX		(1 << 29)
+
+/* Ethernet MAC Mode Configuration Registers (EMMC), [1] p54 */
+#define EMMC_LSPD_POS		30
+#define EMMC_LSPD_MASK		(3 << EMMC_LSPD_POS)
+#define EMMC_LSPD_1000		(2 << EMMC_LSPD_POS)
+#define EMMC_LSPD_100		(1 << EMMC_LSPD_POS)
+#define EMMC_LSPD_10		0
+#define EMMC_RGMII		(1 << 29)
+#define EMMC_SGMII		(1 << 28)
+#define EMMC_GPCS		(1 << 27)
+#define EMMC_HOST		(1 << 26)
+#define EMMC_TX16		(1 << 25)
+#define EMMC_RX16		(1 << 24)
+
+/* RGMII/SGMII Configuration Registers (PHYC), [1] p56 */
+#define PHYC_SLSPD_POS		30
+#define PHYC_SLSPD_MASK		(3 << EMMC_SLSPD_POS)
+#define PHYC_SLSPD_1000		(2 << EMMC_SLSPD_POS)
+#define PHYC_SLSPD_100		(1 << EMMC_SLSPD_POS)
+#define PHYC_SLSPD_10		0
+#define PHYC_RLSPD_POS		2
+#define PHYC_RLSPD_MASK		(3 << EMMC_RLSPD_POS)
+#define PHYC_RLSPD_1000		(2 << EMMC_RLSPD_POS)
+#define PHYC_RLSPD_100		(1 << EMMC_RLSPD_POS)
+#define PHYC_RLSPD_10		0
+#define PHYC_RGMII_HD		(1 << 1)
+#define PHYC_RGMII_LINK		(1 << 0)
+
+/* Management Configuration Registers (MC), [1] p57 */
+#define MC_MDIOEN		(1 << 6)
+#define MC_CLKDIV_POS		0
+#define MC_CLKDIV_MASK		(0x3F << MC_CLKDIV_POS)
+
+/*
+ *             fHOSTCLK          fMDC =                  fHOSTCLK
+ * fMDC = -------------------   --------->   MC_CLKDIV = -------- - 1
+ *        (1 + MC_CLKDIV) * 2    2.5 MHz                   5MHz
+ */
+#define MC_CLKDIV(f, m)		((f / (2 * m)) - 1)
+#define MC_CLKDIV_25(f)		MC_CLKDIV(f, 2500000)
+#define MC_CLKDIV_20(f)		MC_CLKDIV(f, 2000000)
+#define MC_CLKDIV_15(f)		MC_CLKDIV(f, 1500000)
+#define MC_CLKDIV_10(f)		MC_CLKDIV(f, 1000000)
+
+/* Unicast Address Word 0, 1 Registers (UAW0, UAW1), [1] p58-59 */
+#define UAW0_UADDR_POS		0
+#define UAW0_UADDR_MASK		(~0UL << UAW0_UADDR_POS)
+#define UAW1_UADDR_POS		0
+#define UAW1_UADDR_MASK		(0xFFFF << UAW1_UADDR_POS)
+
+/* Multicast Address Word 0, 1 Registers (MAW0, MAW1), [1] p60 */
+#define MAW0_MADDR_POS		0
+#define MAW0_MADDR_MASK		(~0UL << MAW0_MADDR_POS)
+#define MAW1_RNW		(1 << 23)
+#define MAW1_MAIDX_POS		16
+#define MAW1_MAIDX_MASK		(3 << MAW1_MAIDX_POS)
+#define MAW1_MADDR_POS		0
+#define MAW1_MADDR_MASK		(0xFFFF << MAW1_MADDR_POS)
+
+/* Address Filter Mode Registers (AFM), [1] p63 */
+#define AFM_PM			(1 << 31)
+
+/* Interrupt Status, Enable Registers (TIS, TIE), [1] p63-65 */
+#define TISE_CFG_W		(1 << 6)
+#define TISE_CFG_R		(1 << 5)
+#define TISE_AF_W		(1 << 4)
+#define TISE_AF_R		(1 << 3)
+#define TISE_MIIM_W		(1 << 2)
+#define TISE_MIIM_R		(1 << 1)
+#define TISE_FABR_R		(1 << 0)
+
+/* MII Management Write Data Registers (MIIMWD), [1] p66 */
+#define MIIMWD_DATA_POS		0
+#define MIIMWD_DATA_MASK	(0xFFFF << MIIMWD_DATA_POS)
+
+/* Ethernet interface ready status */
+int ll_temac_check_status(struct temac_reg *regs, u32 mask);
+
+/* Indirect write to ll_temac. */
+int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data);
+
+/* Indirect read from ll_temac. */
+int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data);
+
+struct ll_temac {
+	phys_addr_t		ctrladdr;
+	phys_addr_t		sdma_reg_addr[SDMA_CTRL_REGNUMS];
+
+	unsigned		(*in32)(phys_addr_t);
+	void			(*out32)(phys_addr_t, unsigned);
+
+	int			(*ctrlinit) (struct eth_device *);
+	int			(*ctrlhalt) (struct eth_device *);
+	int			(*ctrlreset) (struct eth_device *);
+
+	int			phyaddr;
+	struct phy_device	*phydev;
+	struct mii_dev		*bus;
+	char			mdio_busname[MDIO_NAME_LEN];
+};
+
+struct ll_temac_info {
+	int			flags;
+	unsigned long		base_addr;
+	unsigned long		ctrl_addr;
+	char			*devname;
+	unsigned int		phyaddr;
+	char			*mdio_busname;
+};
+
+/* Driver mode bit flags */
+#define LL_TEMAC_M_FIFO		0		/* use FIFO Ctrl */
+#define LL_TEMAC_M_SDMA_PLB	(1 << 0)	/* use SDMA Ctrl via PLB */
+#define LL_TEMAC_M_SDMA_DCR	(1 << 1)	/* use SDMA Ctrl via DCR */
+
+int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf);
+
+#endif /* _XILINX_LL_TEMAC_ */
diff --git a/include/xilinx_ll_temac_fifo.h b/include/xilinx_ll_temac_fifo.h
new file mode 100644
index 0000000..f0d6e68
--- /dev/null
+++ b/include/xilinx_ll_temac_fifo.h
@@ -0,0 +1,122 @@
+/*
+ * Xilinx xps_ll_temac ethernet driver for u-boot
+ *
+ * FIFO sub-controller interface
+ *
+ * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
+ * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2008 - 2011 PetaLogix
+ *
+ * Based on Yoshio Kashiwagi kashiwagi at co-nss.co.jp driver
+ * Copyright (C) 2008 Nissin Systems Co.,Ltd.
+ * March 2008 created
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [S]:	[0]/ip_documentation/xps_ll_temac.pdf
+ * [A]:	[0]/application_notes/xapp1041.pdf
+ */
+#ifndef _XILINX_LL_TEMAC_FIFO_
+#define _XILINX_LL_TEMAC_FIFO_
+
+#include <net.h>
+
+#include <asm/types.h>
+#include <asm/byteorder.h>
+
+#if !defined(__BIG_ENDIAN)
+# error LL_TEMAC requires big endianess
+#endif
+
+/*
+ * FIFO Register Definition
+ *
+ * Used for memory mapped access from and to (Rd/Td) the LocalLink (LL)
+ * Tri-Mode Ether MAC (TEMAC) via the 2 kb full duplex FIFO Controller,
+ * one for each.
+ *
+ * [1]: [0]/ip_documentation/xps_ll_fifo.pdf
+ *      page 10, Registers Definition
+ */
+struct fifo_ctrl {
+	u32 isr;	/* Interrupt Status Register (RW) */
+	u32 ier;	/* Interrupt Enable Register (RW) */
+	u32 tdfr;	/* Transmit Data FIFO Reset (WO) */
+	u32 tdfv;	/* Transmit Data FIFO Vacancy (RO) */
+	u32 tdfd;	/* Transmit Data FIFO 32bit wide Data write port (WO) */
+	u32 tlf;	/* Transmit Length FIFO (WO) */
+	u32 rdfr;	/* Receive Data FIFO Reset (WO) */
+	u32 rdfo;	/* Receive Data FIFO Occupancy (RO) */
+	u32 rdfd;	/* Receive Data FIFO 32bit wide Data read port (RO) */
+	u32 rlf;	/* Receive Length FIFO (RO) */
+	u32 llr;	/* LocalLink Reset (WO) */
+};
+
+/* Interrupt Status Register (ISR), [1] p11 */
+#define LL_FIFO_ISR_RPURE	(1 << 31) /* Receive Packet Underrun Read Err */
+#define LL_FIFO_ISR_RPORE	(1 << 30) /* Receive Packet Overrun Read Err */
+#define LL_FIFO_ISR_RPUE	(1 << 29) /* Receive Packet Underrun Error */
+#define LL_FIFO_ISR_TPOE	(1 << 28) /* Transmit Packet Overrun Error */
+#define LL_FIFO_ISR_TC		(1 << 27) /* Transmit Complete */
+#define LL_FIFO_ISR_RC		(1 << 26) /* Receive Complete */
+#define LL_FIFO_ISR_TSE		(1 << 25) /* Transmit Size Error */
+#define LL_FIFO_ISR_TRC		(1 << 24) /* Transmit Reset Complete */
+#define LL_FIFO_ISR_RRC		(1 << 23) /* Receive Reset Complete */
+
+/* Interrupt Enable Register (IER), [1] p12/p13 */
+#define LL_FIFO_IER_RPURE	(1 << 31) /* Receive Packet Underrun Read Err */
+#define LL_FIFO_IER_RPORE	(1 << 30) /* Receive Packet Overrun Read Err */
+#define LL_FIFO_IER_RPUE	(1 << 29) /* Receive Packet Underrun Error */
+#define LL_FIFO_IER_TPOE	(1 << 28) /* Transmit Packet Overrun Error */
+#define LL_FIFO_IER_TC		(1 << 27) /* Transmit Complete */
+#define LL_FIFO_IER_RC		(1 << 26) /* Receive Complete */
+#define LL_FIFO_IER_TSE		(1 << 25) /* Transmit Size Error */
+#define LL_FIFO_IER_TRC		(1 << 24) /* Transmit Reset Complete */
+#define LL_FIFO_IER_RRC		(1 << 23) /* Receive Reset Complete */
+
+/* Transmit Data FIFO Reset (TDFR), [1] p13/p14 */
+#define LL_FIFO_TDFR_KEY	0x000000A5UL
+
+/* Transmit Data FIFO Vacancy (TDFV), [1] p14 */
+#define LL_FIFO_TDFV_POS	0
+#define LL_FIFO_TDFV_MASK	(0x000001FFUL << LL_FIFO_TDFV_POS)
+
+/* Transmit Length FIFO (TLF), [1] p16/p17 */
+#define LL_FIFO_TLF_POS		0
+#define LL_FIFO_TLF_MASK	(0x000007FFUL << LL_FIFO_TLF_POS)
+#define LL_FIFO_TLF_MIN		((4 * sizeof(u32)) & LL_FIFO_TLF_MASK)
+#define LL_FIFO_TLF_MAX		((510 * sizeof(u32)) & LL_FIFO_TLF_MASK)
+
+/* Receive Data FIFO Reset (RDFR), [1] p15 */
+#define LL_FIFO_RDFR_KEY	0x000000A5UL
+
+/* Receive Data FIFO Occupancy (RDFO), [1] p16 */
+#define LL_FIFO_RDFO_POS	0
+#define LL_FIFO_RDFO_MASK	(0x000001FFUL << LL_FIFO_RDFO_POS)
+
+/* Receive Length FIFO (RLF), [1] p17/p18 */
+#define LL_FIFO_RLF_POS		0
+#define LL_FIFO_RLF_MASK	(0x000007FFUL << LL_FIFO_RLF_POS)
+#define LL_FIFO_RLF_MIN		((4 * sizeof(uint32)) & LL_FIFO_RLF_MASK)
+#define LL_FIFO_RLF_MAX		((510 * sizeof(uint32)) & LL_FIFO_RLF_MASK)
+
+/* LocalLink Reset (LLR), [1] p18 */
+#define LL_FIFO_LLR_KEY		0x000000A5UL
+
+
+/* reset FIFO and IRQ, disable interrupts */
+int ll_temac_reset_fifo(struct eth_device *dev);
+
+/* receive buffered data from FIFO (polling ISR) */
+int ll_temac_recv_fifo(struct eth_device *dev);
+
+/* send buffered data to FIFO */
+int ll_temac_send_fifo(struct eth_device *dev, volatile void *packet,
+							int length);
+
+#endif /* _XILINX_LL_TEMAC_FIFO_ */
diff --git a/include/xilinx_ll_temac_mdio.h b/include/xilinx_ll_temac_mdio.h
new file mode 100644
index 0000000..bb6e2bd
--- /dev/null
+++ b/include/xilinx_ll_temac_mdio.h
@@ -0,0 +1,53 @@
+/*
+ * Xilinx xps_ll_temac ethernet driver for u-boot
+ *
+ * MDIO bus access interface
+ *
+ * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
+ * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2008 - 2011 PetaLogix
+ *
+ * Based on Yoshio Kashiwagi kashiwagi at co-nss.co.jp driver
+ * Copyright (C) 2008 Nissin Systems Co.,Ltd.
+ * March 2008 created
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [S]:	[0]/ip_documentation/xps_ll_temac.pdf
+ * [A]:	[0]/application_notes/xapp1041.pdf
+ */
+#ifndef _XILINX_LL_TEMAC_MDIO_
+#define _XILINX_LL_TEMAC_MDIO_
+
+#include <net.h>
+#include <miiphy.h>
+
+#include <asm/types.h>
+#include <asm/byteorder.h>
+
+#include <xilinx_ll_temac.h>
+
+int ll_temac_local_mdio_read(struct temac_reg *regs, int addr, int devad,
+				int regnum);
+void ll_temac_local_mdio_write(struct temac_reg *regs, int addr, int devad,
+				int regnum, u16 value);
+
+int ll_temac_phy_read(struct mii_dev *bus, int addr, int devad, int regnum);
+int ll_temac_phy_write(struct mii_dev *bus, int addr, int devad, int regnum,
+			u16 value);
+
+int ll_temac_phy_addr(struct mii_dev *bus);
+
+struct ll_temac_mdio_info {
+	struct temac_reg *regs;
+	char *name;
+};
+
+int xilinx_ll_temac_mdio_initialize(bd_t *bis, struct ll_temac_mdio_info *info);
+
+#endif /* _XILINX_LL_TEMAC_MDIO_ */
diff --git a/include/xilinx_ll_temac_sdma.h b/include/xilinx_ll_temac_sdma.h
new file mode 100644
index 0000000..51e258d
--- /dev/null
+++ b/include/xilinx_ll_temac_sdma.h
@@ -0,0 +1,281 @@
+/*
+ * Xilinx xps_ll_temac ethernet driver for u-boot
+ *
+ * SDMA sub-controller interface
+ *
+ * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
+ * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2008 - 2011 PetaLogix
+ *
+ * Based on Yoshio Kashiwagi kashiwagi at co-nss.co.jp driver
+ * Copyright (C) 2008 Nissin Systems Co.,Ltd.
+ * March 2008 created
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [S]:	[0]/ip_documentation/xps_ll_temac.pdf
+ * [A]:	[0]/application_notes/xapp1041.pdf
+ */
+#ifndef _XILINX_LL_TEMAC_SDMA_
+#define _XILINX_LL_TEMAC_SDMA_
+
+#include <net.h>
+
+#include <asm/types.h>
+#include <asm/byteorder.h>
+
+#include <linux/compiler.h>
+
+#if !defined(__BIG_ENDIAN)
+# error LL_TEMAC requires big endianess
+#endif
+
+/*
+ * DMA Buffer Descriptor for CDMAC
+ *
+ * Used for data connection from and to (Rx/Tx) the LocalLink (LL) TEMAC via
+ * the Communications Direct Memory Access Controller (CDMAC) -- one for each.
+ *
+ * overview:
+ *      ftp://ftp.xilinx.com/pub/documentation/misc/mpmc_getting_started.pdf
+ *
+ * [1]: [0]/ip_documentation/mpmc.pdf
+ *      page 140, DMA Operation Descriptors
+ *
+ * [2]:	[0]/user_guides/ug200.pdf
+ *	page 229, DMA Controller -- Descriptor Format
+ *
+ * [3]:	[0]/ip_documentation/xps_ll_temac.pdf
+ *	page 72, Transmit LocalLink Frame Format
+ *	page 73, Receive LocalLink Frame Format
+ */
+struct cdmac_bd {
+	struct cdmac_bd *next_p;	/* Next Descriptor Pointer */
+	u8 *phys_buf_p;			/* Buffer Address */
+	u32 buf_len;			/* Buffer Length */
+	union {
+		u8 stctrl;		/* Status/Control the DMA transfer */
+		u32 app[5];		/* application specific data */
+	} __packed __aligned(1) sca;
+};
+
+/* CDMAC Descriptor Status and Control (stctrl), [1] p140, [2] p230 */
+#define CDMAC_BD_STCTRL_ERROR		(1 << 7)
+#define CDMAC_BD_STCTRL_IRQ_ON_END	(1 << 6)
+#define CDMAC_BD_STCTRL_STOP_ON_END	(1 << 5)
+#define CDMAC_BD_STCTRL_COMPLETED	(1 << 4)
+#define CDMAC_BD_STCTRL_SOP		(1 << 3)
+#define CDMAC_BD_STCTRL_EOP		(1 << 2)
+#define CDMAC_BD_STCTRL_DMACHBUSY	(1 << 1)
+
+/* CDMAC Descriptor APP0: Transmit LocalLink Footer Word 3, [3] p72 */
+#define CDMAC_BD_APP0_TXCSCNTRL		(1 << 0)
+
+/* CDMAC Descriptor APP1: Transmit LocalLink Footer Word 4, [3] p73 */
+#define CDMAC_BD_APP1_TXCSBEGIN_POS	16
+#define CDMAC_BD_APP1_TXCSBEGIN_MASK	(0xFFFF << CDMAC_BD_APP1_TXCSBEGIN_POS)
+#define CDMAC_BD_APP1_TXCSINSERT_POS	0
+#define CDMAC_BD_APP1_TXCSINSERT_MASK	(0xFFFF << CDMAC_BD_APP1_TXCSINSERT_POS)
+
+/* CDMAC Descriptor APP2: Transmit LocalLink Footer Word 5, [3] p73 */
+#define CDMAC_BD_APP2_TXCSINIT_POS	0
+#define CDMAC_BD_APP2_TXCSINIT_MASK	(0xFFFF << CDMAC_BD_APP2_TXCSINIT_POS)
+
+/* CDMAC Descriptor APP0: Receive LocalLink Footer Word 3, [3] p73 */
+#define CDMAC_BD_APP0_MADDRU_POS	0
+#define CDMAC_BD_APP0_MADDRU_MASK	(0xFFFF << CDMAC_BD_APP0_MADDRU_POS)
+
+/* CDMAC Descriptor APP1: Receive LocalLink Footer Word 4, [3] p74 */
+#define CDMAC_BD_APP1_MADDRL_POS	0
+#define CDMAC_BD_APP1_MADDRL_MASK	(~0UL << CDMAC_BD_APP1_MADDRL_POS)
+
+/* CDMAC Descriptor APP2: Receive LocalLink Footer Word 5, [3] p74 */
+#define CDMAC_BD_APP2_BCAST_FRAME	(1 << 2)
+#define CDMAC_BD_APP2_IPC_MCAST_FRAME	(1 << 1)
+#define CDMAC_BD_APP2_MAC_MCAST_FRAME	(1 << 0)
+
+/* CDMAC Descriptor APP3: Receive LocalLink Footer Word 6, [3] p74 */
+#define CDMAC_BD_APP3_TLTPID_POS	16
+#define CDMAC_BD_APP3_TLTPID_MASK	(0xFFFF << CDMAC_BD_APP3_TLTPID_POS)
+#define CDMAC_BD_APP3_RXCSRAW_POS	0
+#define CDMAC_BD_APP3_RXCSRAW_MASK	(0xFFFF << CDMAC_BD_APP3_RXCSRAW_POS)
+
+/* CDMAC Descriptor APP4: Receive LocalLink Footer Word 7, [3] p74 */
+#define CDMAC_BD_APP4_VLANTAG_POS	16
+#define CDMAC_BD_APP4_VLANTAG_MASK	(0xFFFF << CDMAC_BD_APP4_VLANTAG_POS)
+#define CDMAC_BD_APP4_RXBYTECNT_POS	0
+#define CDMAC_BD_APP4_RXBYTECNT_MASK	(0x3FFF << CDMAC_BD_APP4_RXBYTECNT_POS)
+
+/*
+ * SDMA Register Definition
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [1]:	[0]/ip_documentation/mpmc.pdf
+ *	page 54, SDMA Register Summary
+ *	page 160, SDMA Registers
+ *
+ * [2]:	[0]/user_guides/ug200.pdf
+ *	page 244, DMA Controller -- Programming Interface and Registers
+ */
+#define SDMA_CTRL_REGTYPE	u32
+#define SDMA_CTRL_REGSIZE	sizeof(SDMA_CTRL_REGTYPE)
+struct sdma_ctrl {
+	/* Transmit Registers */
+	SDMA_CTRL_REGTYPE tx_nxtdesc_ptr;   /* TX Next Description Pointer */
+	SDMA_CTRL_REGTYPE tx_curbuf_addr;   /* TX Current Buffer Address */
+	SDMA_CTRL_REGTYPE tx_curbuf_length; /* TX Current Buffer Length */
+	SDMA_CTRL_REGTYPE tx_curdesc_ptr;   /* TX Current Descriptor Pointer */
+	SDMA_CTRL_REGTYPE tx_taildesc_ptr;  /* TX Tail Descriptor Pointer */
+	SDMA_CTRL_REGTYPE tx_chnl_ctrl;     /* TX Channel Control */
+	SDMA_CTRL_REGTYPE tx_irq_reg;       /* TX Interrupt Register */
+	SDMA_CTRL_REGTYPE tx_chnl_sts;      /* TX Status Register */
+	/* Receive Registers */
+	SDMA_CTRL_REGTYPE rx_nxtdesc_ptr;   /* RX Next Descriptor Pointer */
+	SDMA_CTRL_REGTYPE rx_curbuf_addr;   /* RX Current Buffer Address */
+	SDMA_CTRL_REGTYPE rx_curbuf_length; /* RX Current Buffer Length */
+	SDMA_CTRL_REGTYPE rx_curdesc_ptr;   /* RX Current Descriptor Pointer */
+	SDMA_CTRL_REGTYPE rx_taildesc_ptr;  /* RX Tail Descriptor Pointer */
+	SDMA_CTRL_REGTYPE rx_chnl_ctrl;     /* RX Channel Control */
+	SDMA_CTRL_REGTYPE rx_irq_reg;       /* RX Interrupt Register */
+	SDMA_CTRL_REGTYPE rx_chnl_sts;      /* RX Status Register */
+	/* Control Registers */
+	SDMA_CTRL_REGTYPE dma_control_reg;  /* DMA Control Register */
+};
+
+#define SDMA_CTRL_REGNUMS	sizeof(struct sdma_ctrl)/SDMA_CTRL_REGSIZE
+
+/*
+ * DMAC Register Index Enumeration
+ *
+ * [2]:	http://www.xilinx.com/support/documentation/user_guides/ug200.pdf
+ *	page 244, DMA Controller -- Programming Interface and Registers
+ */
+enum dmac_ctrl {
+	/* Transmit Registers */
+	TX_NXTDESC_PTR = 0,	/* TX Next Description Pointer */
+	TX_CURBUF_ADDR,		/* TX Current Buffer Address */
+	TX_CURBUF_LENGTH,	/* TX Current Buffer Length */
+	TX_CURDESC_PTR,		/* TX Current Descriptor Pointer */
+	TX_TAILDESC_PTR,	/* TX Tail Descriptor Pointer */
+	TX_CHNL_CTRL,		/* TX Channel Control */
+	TX_IRQ_REG,		/* TX Interrupt Register */
+	TX_CHNL_STS,		/* TX Status Register */
+	/* Receive Registers */
+	RX_NXTDESC_PTR,		/* RX Next Descriptor Pointer */
+	RX_CURBUF_ADDR,		/* RX Current Buffer Address */
+	RX_CURBUF_LENGTH,	/* RX Current Buffer Length */
+	RX_CURDESC_PTR,		/* RX Current Descriptor Pointer */
+	RX_TAILDESC_PTR,	/* RX Tail Descriptor Pointer */
+	RX_CHNL_CTRL,		/* RX Channel Control */
+	RX_IRQ_REG,		/* RX Interrupt Register */
+	RX_CHNL_STS,		/* RX Status Register */
+	/* Control Registers */
+	DMA_CONTROL_REG		/* DMA Control Register */
+};
+
+/* Rx/Tx Channel Control Register (*_chnl_ctrl), [1] p163, [2] p246/p252 */
+#define CHNL_CTRL_ITO_POS	24
+#define CHNL_CTRL_ITO_MASK	(0xFF << CHNL_CTRL_ITO_POS)
+#define CHNL_CTRL_IC_POS	16
+#define CHNL_CTRL_IC_MASK	(0xFF << CHNL_CTRL_IC_POS)
+#define CHNL_CTRL_MSBADDR_POS	12
+#define CHNL_CTRL_MSBADDR_MASK	(0xF << CHNL_CTRL_MSBADDR_POS)
+#define CHNL_CTRL_AME		(1 << 11)
+#define CHNL_CTRL_OBWC		(1 << 10)
+#define CHNL_CTRL_IOE		(1 << 9)
+#define CHNL_CTRL_LIC		(1 << 8)
+#define CHNL_CTRL_IE		(1 << 7)
+#define CHNL_CTRL_IEE		(1 << 2)
+#define CHNL_CTRL_IDE		(1 << 1)
+#define CHNL_CTRL_ICE		(1 << 0)
+
+/* All interrupt enable bits */
+#define CHNL_CTRL_IRQ_MASK	(CHNL_CTRL_IE | \
+				 CHNL_CTRL_IEE | \
+				 CHNL_CTRL_IDE | \
+				 CHNL_CTRL_ICE)
+
+/* Rx/Tx Interrupt Status Register (*_irq_reg), [1] p164, [2] p247/p253 */
+#define IRQ_REG_DTV_POS		24
+#define IRQ_REG_DTV_MASK	(0xFF << IRQ_REG_DTV_POS)
+#define IRQ_REG_CCV_POS		16
+#define IRQ_REG_CCV_MASK	(0xFF << IRQ_REG_CCV_POS)
+#define IRQ_REG_WRCQ_EMPTY	(1 << 14)
+#define IRQ_REG_CIC_POS		10
+#define IRQ_REG_CIC_MASK	(0xF << IRQ_REG_CIC_POS)
+#define IRQ_REG_DIC_POS		8
+#define IRQ_REG_DIC_MASK	(3 << 8)
+#define IRQ_REG_PLB_RD_NMI	(1 << 4)
+#define IRQ_REG_PLB_WR_NMI	(1 << 3)
+#define IRQ_REG_EI		(1 << 2)
+#define IRQ_REG_DI		(1 << 1)
+#define IRQ_REG_CI		(1 << 0)
+
+/* All interrupt bits */
+#define IRQ_REG_IRQ_MASK	(IRQ_REG_PLB_RD_NMI | \
+				 IRQ_REG_PLB_WR_NMI | \
+				 IRQ_REG_EI | IRQ_REG_DI | IRQ_REG_CI)
+
+/* Rx/Tx Channel Status Register (*_chnl_sts), [1] p165, [2] p249/p255 */
+#define CHNL_STS_ERROR_TAIL	(1 << 21)
+#define CHNL_STS_ERROR_CMP	(1 << 20)
+#define CHNL_STS_ERROR_ADDR	(1 << 19)
+#define CHNL_STS_ERROR_NXTP	(1 << 18)
+#define CHNL_STS_ERROR_CURP	(1 << 17)
+#define CHNL_STS_ERROR_BSYWR	(1 << 16)
+#define CHNL_STS_ERROR		(1 << 7)
+#define CHNL_STS_IOE		(1 << 6)
+#define CHNL_STS_SOE		(1 << 5)
+#define CHNL_STS_CMPLT		(1 << 4)
+#define CHNL_STS_SOP		(1 << 3)
+#define CHNL_STS_EOP		(1 << 2)
+#define CHNL_STS_EBUSY		(1 << 1)
+
+/* DMA Control Register (dma_control_reg), [1] p166, [2] p256 */
+#define DMA_CONTROL_PLBED	(1 << 5)
+#define DMA_CONTROL_RXOCEID	(1 << 4)
+#define DMA_CONTROL_TXOCEID	(1 << 3)
+#define DMA_CONTROL_TPE		(1 << 2)
+#define DMA_CONTROL_RESET	(1 << 0)
+
+#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405)
+
+/* Xilinx Device Control Register (DCR) in/out accessors */
+unsigned ll_temac_xldcr_in32(phys_addr_t addr);
+void ll_temac_xldcr_out32(phys_addr_t addr, unsigned value);
+
+/* collect all register addresses for Xilinx DCR in/out accessors */
+void ll_temac_collect_xldcr_sdma_reg_addr(struct eth_device *dev);
+
+#endif /* CONFIG_XILINX_440 || CONFIG_XILINX_405 */
+
+/* Xilinx Processor Local Bus (PLB) in/out accessors */
+unsigned ll_temac_xlplb_in32(phys_addr_t base);
+void ll_temac_xlplb_out32(phys_addr_t base, unsigned value);
+
+/* collect all register addresses for Xilinx PLB in/out accessors */
+void ll_temac_collect_xlplb_sdma_reg_addr(struct eth_device *dev);
+
+/* initialize both Rx/Tx buffer descriptors */
+int ll_temac_init_sdma(struct eth_device *dev);
+
+/* halt both Rx/Tx transfers */
+int ll_temac_halt_sdma(struct eth_device *dev);
+
+/* reset SDMA and IRQ, disable interrupts and errors */
+int ll_temac_reset_sdma(struct eth_device *dev);
+
+/* receive buffered data from SDMA (polling ISR) */
+int ll_temac_recv_sdma(struct eth_device *dev);
+
+/* send buffered data to SDMA */
+int ll_temac_send_sdma(struct eth_device *dev, volatile void *packet,
+							int length);
+
+#endif /* _XILINX_LL_TEMAC_SDMA_ */
-- 
1.7.0.4

[U-Boot] [PATCH 2/8] microblaze: Enable several ethernet driver compilation

[Stephan Linz]

U-Boot's multipple network supports enables to use
several ethernet drivers but microblaze-generic
platform config file select only one driver.

Reported-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Stephan Linz <linz@li-pro.net>
---
 include/configs/microblaze-generic.h |   12 ++++++++----
 1 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 03a6f5a..09ac870 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -65,11 +65,15 @@
 
 /* ethernet */
 #undef CONFIG_SYS_ENET
-#ifdef XILINX_EMACLITE_BASEADDR
-# define CONFIG_XILINX_EMACLITE		1
+#if defined(XILINX_EMACLITE_BASEADDR)
+# define CONFIG_XILINX_EMACLITE	1
 # define CONFIG_SYS_ENET
-#elif XILINX_LLTEMAC_BASEADDR
-# define CONFIG_XILINX_LL_TEMAC		1
+#endif
+#if defined(XILINX_LLTEMAC_BASEADDR)  || defined(XILINX_LLTEMAC_BASEADDR1) || \
+    defined(XILINX_LLTEMAC_BASEADDR2) || defined(XILINX_LLTEMAC_BASEADDR3) || \
+    defined(XILINX_LLTEMAC_BASEADDR4) || defined(XILINX_LLTEMAC_BASEADDR5) || \
+    defined(XILINX_LLTEMAC_BASEADDR6) || defined(XILINX_LLTEMAC_BASEADDR7)
+# define CONFIG_XILINX_LL_TEMAC	1
 # define CONFIG_SYS_ENET
 #endif
 #if defined(XILINX_AXIEMAC_BASEADDR)
-- 
1.7.0.4

[U-Boot] [PATCH 3/8] microblaze: Enable phylib and mii support

[Stephan Linz]

From: Michal Simek <monstr@monstr.eu>

Enable phylib and mii support for LLTEMAC or AXI EMAC
ethernet drivers on Microblaze systems.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
---
 include/configs/microblaze-generic.h |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 09ac870..69fcdb6 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -342,4 +342,25 @@
 #define CONFIG_FIT		1
 #define CONFIG_OF_LIBFDT	1
 
+#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
+# define CONFIG_MII		1
+# define CONFIG_CMD_MII		1
+# define CONFIG_PHY_GIGE	1
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
+# define CONFIG_PHYLIB		1
+# define CONFIG_PHY_ATHEROS	1
+# define CONFIG_PHY_BROADCOM	1
+# define CONFIG_PHY_DAVICOM	1
+# define CONFIG_PHY_LXT		1
+# define CONFIG_PHY_MARVELL	1
+# define CONFIG_PHY_MICREL	1
+# define CONFIG_PHY_NATSEMI	1
+# define CONFIG_PHY_REALTEK	1
+# define CONFIG_PHY_VITESSE	1
+#else
+# undef CONFIG_MII
+# undef CONFIG_CMD_MII
+# undef CONFIG_PHYLIB
+#endif
+
 #endif	/* __CONFIG_H */
-- 
1.7.0.4

[U-Boot] [PATCH 4/8] microblaze: Enable TFTP put command

[Stephan Linz]

Signed-off-by: Stephan Linz <linz@li-pro.net>
---
 include/configs/microblaze-generic.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 69fcdb6..71d4767 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -259,6 +259,7 @@
 #else
 # define CONFIG_CMD_PING
 # define CONFIG_CMD_DHCP
+# define CONFIG_CMD_TFTPPUT
 #endif
 
 #if defined(CONFIG_SYSTEMACE)
-- 
1.7.0.4

[U-Boot] [PATCH 5/8] microblaze: Xilinx BSP to U-Boot conversion matrix

[Stephan Linz]

This matrix converts values from the automaticaly generated header
xparameters.h to U-Boot configuration values as needed.

Signed-off-by: Stephan Linz <linz@li-pro.net>
---
 board/xilinx/microblaze-generic/xconversions.h |  167 ++++++++++++++++++++++++
 include/configs/microblaze-generic.h           |    1 +
 2 files changed, 168 insertions(+), 0 deletions(-)
 create mode 100644 board/xilinx/microblaze-generic/xconversions.h

diff --git a/board/xilinx/microblaze-generic/xconversions.h b/board/xilinx/microblaze-generic/xconversions.h
new file mode 100644
index 0000000..1b94afc
--- /dev/null
+++ b/board/xilinx/microblaze-generic/xconversions.h
@@ -0,0 +1,167 @@
+/*
+ * This is the Xilinx BSP to U-Boot converstion matrix. You have
+ * to include this header immediately after xparameters.h in your
+ * board configuration header. All U-Boot configuration values
+ * have to become constant to avoid unexpected compilation failure.
+ *
+ * (C) Copyright 2012 Li-Pro.Net
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if (XILINX_LLTEMAC_SDMA_USE_DCR == 1)
+# define XILINX_LLTEMAC_SDMA_BUSMODE		LL_TEMAC_M_SDMA_DCR
+#else
+# define XILINX_LLTEMAC_SDMA_BUSMODE		LL_TEMAC_M_SDMA_PLB
+#endif
+
+/* default parameters for the 1st LLTEMAC */
+#if defined(XILINX_LLTEMAC_BASEADDR)
+# define CONFIG_PHY_ADDR			-1
+# define CONFIG_XILINX_LL_TEMAC0_NAME		NULL
+# define CONFIG_XILINX_LL_TEMAC0_MII_NAME	NULL
+# define CONFIG_XILINX_LL_TEMAC0_BASE_ADDR	XILINX_LLTEMAC_BASEADDR
+# if defined(XILINX_LLTEMAC_FIFO_BASEADDR)
+#  define CONFIG_XILINX_LL_TEMAC0_CTRL_ADDR	XILINX_LLTEMAC_FIFO_BASEADDR
+#  define CONFIG_XILINX_LL_TEMAC0_CTRL_MODE	LL_TEMAC_M_FIFO
+# elif defined(XILINX_LLTEMAC_SDMA_CTRL_BASEADDR)
+#  define CONFIG_XILINX_LL_TEMAC0_CTRL_ADDR	XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
+#  define CONFIG_XILINX_LL_TEMAC0_CTRL_MODE	XILINX_LLTEMAC_SDMA_BUSMODE
+# else
+#  error "missing sub-controller base address for LLTEMAC0"
+# endif
+#endif
+
+/* default parameters for the 2nd LLTEMAC */
+#if defined(XILINX_LLTEMAC_BASEADDR1)
+# define CONFIG_PHY1_ADDR			-1
+# define CONFIG_XILINX_LL_TEMAC1_NAME		NULL
+# define CONFIG_XILINX_LL_TEMAC1_MII_NAME	NULL
+# define CONFIG_XILINX_LL_TEMAC1_BASE_ADDR	XILINX_LLTEMAC_BASEADDR1
+# if defined(XILINX_LLTEMAC_FIFO_BASEADDR1)
+#  define CONFIG_XILINX_LL_TEMAC1_CTRL_ADDR	XILINX_LLTEMAC_FIFO_BASEADDR1
+#  define CONFIG_XILINX_LL_TEMAC1_CTRL_MODE	LL_TEMAC_M_FIFO
+# elif defined(XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1)
+#  define CONFIG_XILINX_LL_TEMAC1_CTRL_ADDR	XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
+#  define CONFIG_XILINX_LL_TEMAC1_CTRL_MODE	XILINX_LLTEMAC_SDMA_BUSMODE
+# else
+#  error "missing sub-controller base address for LLTEMAC1"
+# endif
+#endif
+
+/* default parameters for the 3rd LLTEMAC */
+#if defined(XILINX_LLTEMAC_BASEADDR2)
+# define CONFIG_PHY2_ADDR			-1
+# define CONFIG_XILINX_LL_TEMAC2_NAME		NULL
+# define CONFIG_XILINX_LL_TEMAC2_MII_NAME	NULL
+# define CONFIG_XILINX_LL_TEMAC2_BASE_ADDR	XILINX_LLTEMAC_BASEADDR2
+# if defined(XILINX_LLTEMAC_FIFO_BASEADDR2)
+#  define CONFIG_XILINX_LL_TEMAC2_CTRL_ADDR	XILINX_LLTEMAC_FIFO_BASEADDR2
+#  define CONFIG_XILINX_LL_TEMAC2_CTRL_MODE	LL_TEMAC_M_FIFO
+# elif defined(XILINX_LLTEMAC_SDMA_CTRL_BASEADDR2)
+#  define CONFIG_XILINX_LL_TEMAC2_CTRL_ADDR	XILINX_LLTEMAC_SDMA_CTRL_BASEADDR2
+#  define CONFIG_XILINX_LL_TEMAC2_CTRL_MODE	XILINX_LLTEMAC_SDMA_BUSMODE
+# else
+#  error "missing sub-controller base address for LLTEMAC2"
+# endif
+#endif
+
+/* default parameters for the 4th LLTEMAC */
+#if defined(XILINX_LLTEMAC_BASEADDR3)
+# define CONFIG_PHY3_ADDR			-1
+# define CONFIG_XILINX_LL_TEMAC3_NAME		NULL
+# define CONFIG_XILINX_LL_TEMAC3_MII_NAME	NULL
+# define CONFIG_XILINX_LL_TEMAC3_BASE_ADDR	XILINX_LLTEMAC_BASEADDR3
+# if defined(XILINX_LLTEMAC_FIFO_BASEADDR3)
+#  define CONFIG_XILINX_LL_TEMAC3_CTRL_ADDR	XILINX_LLTEMAC_FIFO_BASEADDR3
+#  define CONFIG_XILINX_LL_TEMAC3_CTRL_MODE	LL_TEMAC_M_FIFO
+# elif defined(XILINX_LLTEMAC_SDMA_CTRL_BASEADDR3)
+#  define CONFIG_XILINX_LL_TEMAC3_CTRL_ADDR	XILINX_LLTEMAC_SDMA_CTRL_BASEADDR3
+#  define CONFIG_XILINX_LL_TEMAC3_CTRL_MODE	XILINX_LLTEMAC_SDMA_BUSMODE
+# else
+#  error "missing sub-controller base address for LLTEMAC3"
+# endif
+#endif
+
+/* default parameters for the 5th LLTEMAC */
+#if defined(XILINX_LLTEMAC_BASEADDR4)
+# define CONFIG_PHY4_ADDR			-1
+# define CONFIG_XILINX_LL_TEMAC4_NAME		NULL
+# define CONFIG_XILINX_LL_TEMAC4_MII_NAME	NULL
+# define CONFIG_XILINX_LL_TEMAC4_BASE_ADDR	XILINX_LLTEMAC_BASEADDR4
+# if defined(XILINX_LLTEMAC_FIFO_BASEADDR4)
+#  define CONFIG_XILINX_LL_TEMAC4_CTRL_ADDR	XILINX_LLTEMAC_FIFO_BASEADDR4
+#  define CONFIG_XILINX_LL_TEMAC4_CTRL_MODE	LL_TEMAC_M_FIFO
+# elif defined(XILINX_LLTEMAC_SDMA_CTRL_BASEADDR4)
+#  define CONFIG_XILINX_LL_TEMAC4_CTRL_ADDR	XILINX_LLTEMAC_SDMA_CTRL_BASEADDR4
+#  define CONFIG_XILINX_LL_TEMAC4_CTRL_MODE	XILINX_LLTEMAC_SDMA_BUSMODE
+# else
+#  error "missing sub-controller base address for LLTEMAC4"
+# endif
+#endif
+
+/* default parameters for the 6th LLTEMAC */
+#if defined(XILINX_LLTEMAC_BASEADDR5)
+# define CONFIG_PHY5_ADDR			-1
+# define CONFIG_XILINX_LL_TEMAC5_NAME		NULL
+# define CONFIG_XILINX_LL_TEMAC5_MII_NAME	NULL
+# define CONFIG_XILINX_LL_TEMAC5_BASE_ADDR	XILINX_LLTEMAC_BASEADDR5
+# if defined(XILINX_LLTEMAC_FIFO_BASEADDR5)
+#  define CONFIG_XILINX_LL_TEMAC5_CTRL_ADDR	XILINX_LLTEMAC_FIFO_BASEADDR5
+#  define CONFIG_XILINX_LL_TEMAC5_CTRL_MODE	LL_TEMAC_M_FIFO
+# elif defined(XILINX_LLTEMAC_SDMA_CTRL_BASEADDR5)
+#  define CONFIG_XILINX_LL_TEMAC5_CTRL_ADDR	XILINX_LLTEMAC_SDMA_CTRL_BASEADDR5
+#  define CONFIG_XILINX_LL_TEMAC5_CTRL_MODE	XILINX_LLTEMAC_SDMA_BUSMODE
+# else
+#  error "missing sub-controller base address for LLTEMAC5"
+# endif
+#endif
+
+/* default parameters for the 7th LLTEMAC */
+#if defined(XILINX_LLTEMAC_BASEADDR6)
+# define CONFIG_PHY6_ADDR			-1
+# define CONFIG_XILINX_LL_TEMAC6_NAME		NULL
+# define CONFIG_XILINX_LL_TEMAC6_MII_NAME	NULL
+# define CONFIG_XILINX_LL_TEMAC6_BASE_ADDR	XILINX_LLTEMAC_BASEADDR6
+# if defined(XILINX_LLTEMAC_FIFO_BASEADDR6)
+#  define CONFIG_XILINX_LL_TEMAC6_CTRL_ADDR	XILINX_LLTEMAC_FIFO_BASEADDR6
+#  define CONFIG_XILINX_LL_TEMAC6_CTRL_MODE	LL_TEMAC_M_FIFO
+# elif defined(XILINX_LLTEMAC_SDMA_CTRL_BASEADDR6)
+#  define CONFIG_XILINX_LL_TEMAC6_CTRL_ADDR	XILINX_LLTEMAC_SDMA_CTRL_BASEADDR6
+#  define CONFIG_XILINX_LL_TEMAC6_CTRL_MODE	XILINX_LLTEMAC_SDMA_BUSMODE
+# else
+#  error "missing sub-controller base address for LLTEMAC6"
+# endif
+#endif
+
+/* default parameters for the 8th LLTEMAC */
+#if defined(XILINX_LLTEMAC_BASEADDR7)
+# define CONFIG_PHY7_ADDR			-1
+# define CONFIG_XILINX_LL_TEMAC7_NAME		NULL
+# define CONFIG_XILINX_LL_TEMAC7_MII_NAME	NULL
+# define CONFIG_XILINX_LL_TEMAC7_BASE_ADDR	XILINX_LLTEMAC_BASEADDR7
+# if defined(XILINX_LLTEMAC_FIFO_BASEADDR7)
+#  define CONFIG_XILINX_LL_TEMAC7_CTRL_ADDR	XILINX_LLTEMAC_FIFO_BASEADDR7
+#  define CONFIG_XILINX_LL_TEMAC7_CTRL_MODE	LL_TEMAC_M_FIFO
+# elif defined(XILINX_LLTEMAC_SDMA_CTRL_BASEADDR7)
+#  define CONFIG_XILINX_LL_TEMAC7_CTRL_ADDR	XILINX_LLTEMAC_SDMA_CTRL_BASEADDR7
+#  define CONFIG_XILINX_LL_TEMAC7_CTRL_MODE	XILINX_LLTEMAC_SDMA_BUSMODE
+# else
+#  error "missing sub-controller base address for LLTEMAC7"
+# endif
+#endif
+
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 71d4767..81a7905 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -26,6 +26,7 @@
 #define __CONFIG_H
 
 #include "../board/xilinx/microblaze-generic/xparameters.h"
+#include "../board/xilinx/microblaze-generic/xconversions.h"
 
 /* MicroBlaze CPU */
 #define	CONFIG_MICROBLAZE	1
-- 
1.7.0.4

[U-Boot] [PATCH 6/8] microblaze: Add faked LL_TEMAC driver configuration

[Stephan Linz]

Expand the specific configuration for the microblaze-generic
board in xparameters.h with a faked setup to enable the
LL_TEMAC driver.

Note: From now the microblaze-generic board is no longer a
valid board configuration for a real piece of hardware. Rather
than, we use the file config.mk and xparameters.h as a faked
board configuration to force the compilation of all potential
driver code for Microblaze systems.

Signed-off-by: Stephan Linz <linz@li-pro.net>
---
 board/xilinx/microblaze-generic/config.mk     |    6 ++++--
 board/xilinx/microblaze-generic/xparameters.h |   24 ++++++++++++++++++++++--
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
index f8d7e26..9fd1015 100644
--- a/board/xilinx/microblaze-generic/config.mk
+++ b/board/xilinx/microblaze-generic/config.mk
@@ -21,8 +21,10 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-# CAUTION: This file is automatically generated by libgen.
-# Version: Xilinx EDK 6.3 EDK_Gmm.12.3
+# CAUTION: This file is a faked configuration !!!
+#          There is no real target for the microblaze-generic
+#          configuration. You have to replace this file with
+#          the generated file from your Xilinx design flow.
 #
 
 CONFIG_SYS_TEXT_BASE = 0x29000000
diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
index fae03bf..69758c3 100644
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -21,8 +21,10 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  *
- * CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
+ * CAUTION: This file is a faked configuration !!!
+ *          There is no real target for the microblaze-generic
+ *          configuration. You have to replace this file with
+ *          the generated file from your Xilinx design flow.
  */
 
 #define XILINX_BOARD_NAME	microblaze-generic
@@ -69,3 +71,21 @@
 
 /* Ethernet controller is Ethernet_MAC */
 #define XILINX_EMACLITE_BASEADDR       0x40C00000
+
+/* Ethernet controller is Ethernet_MAC */
+#define XILINX_LLTEMAC_BASEADDR			0x44000000
+#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR	0x42000180
+#define XILINX_LLTEMAC_BASEADDR1		0x44000040
+#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1	0x42000200
+#define XILINX_LLTEMAC_BASEADDR2		0x44100000
+#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR2	0x42000280
+#define XILINX_LLTEMAC_BASEADDR3		0x44100040
+#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR3	0x42000300
+#define XILINX_LLTEMAC_BASEADDR4		0x44200000
+#define XILINX_LLTEMAC_FIFO_BASEADDR4		0x42100000
+#define XILINX_LLTEMAC_BASEADDR5		0x44200040
+#define XILINX_LLTEMAC_FIFO_BASEADDR5		0x42110000
+#define XILINX_LLTEMAC_BASEADDR6		0x44300000
+#define XILINX_LLTEMAC_FIFO_BASEADDR6		0x42120000
+#define XILINX_LLTEMAC_BASEADDR7		0x44300040
+#define XILINX_LLTEMAC_FIFO_BASEADDR7		0x42130000
-- 
1.7.0.4

[U-Boot] [PATCH 7/8] microblaze: Wire up LL_TEMAC driver initialization

[Stephan Linz]

Initialize ll_temac driver.

Reported-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Stephan Linz <linz@li-pro.net>
---
 .../xilinx/microblaze-generic/microblaze-generic.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index c4c13a6..517b2f1 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -90,5 +90,10 @@ int board_eth_init(bd_t *bis)
 	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
 			txpp, rxpp);
 #endif
+
+#ifdef CONFIG_XILINX_LL_TEMAC
+	ret |= xilinx_ll_temac_standard_init(bis);
+#endif
+
 	return ret;
 }
-- 
1.7.0.4

[U-Boot] [PATCH 8/8] microblaze: ll_temac: export xilinx_ll_temac_eth_init() for evaluation

[Stephan Linz]

Signed-off-by: Stephan Linz <linz@li-pro.net>
---
 .../xilinx/microblaze-generic/microblaze-generic.c |   57 ++++++++++++++++++++
 drivers/net/xilinx_ll_temac.c                      |    2 +-
 include/xilinx_ll_temac.h                          |    3 +
 3 files changed, 61 insertions(+), 1 deletions(-)

diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index 517b2f1..d2f56b9 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -31,6 +31,10 @@
 #include <asm/microblaze_intc.h>
 #include <asm/asm.h>
 
+#ifdef CONFIG_XILINX_LL_TEMAC
+#include <xilinx_ll_temac.h>
+#endif
+
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 #ifdef CONFIG_SYS_GPIO_0
@@ -92,7 +96,60 @@ int board_eth_init(bd_t *bis)
 #endif
 
 #ifdef CONFIG_XILINX_LL_TEMAC
+#if 1
+	/* This should be the preferred way to initialize
+	 * all the interfaces. */
 	ret |= xilinx_ll_temac_standard_init(bis);
+#else
+	/************************************************************
+	 * NOTE: This part is for evaluation and will help achieve
+	 *       the right way to initialize all LL TEMAC ethernet
+	 *       interfaces. There can be more than this two i/f!
+	 ************************************************************/
+	struct ll_temac_info devinf;
+
+# ifdef XILINX_LLTEMAC_BASEADDR
+	memset(&devinf, 0, sizeof(devinf));
+	devinf.phyaddr = -1;
+	devinf.base_addr = XILINX_LLTEMAC_BASEADDR;
+#  ifdef XILINX_LLTEMAC_FIFO_BASEADDR
+	devinf.flags = LL_TEMAC_M_FIFO;
+	devinf.ctrl_addr = XILINX_LLTEMAC_FIFO_BASEADDR;
+	ret |= xilinx_ll_temac_eth_init(bis, &devinf);
+#  elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
+#   if XILINX_LLTEMAC_SDMA_USE_DCR == 1
+	devinf.flags = LL_TEMAC_M_SDMA_DCR;
+	devinf.ctrl_addr = XILINX_LLTEMAC_SDMA_CTRL_BASEADDR;
+	ret |= xilinx_ll_temac_eth_init(bis, &devinf);
+#   else
+	devinf.flags = LL_TEMAC_M_SDMA_PLB;
+	devinf.ctrl_addr = XILINX_LLTEMAC_SDMA_CTRL_BASEADDR;
+	ret |= xilinx_ll_temac_eth_init(bis, &devinf);
+#   endif
+#  endif
+# endif
+
+# ifdef XILINX_LLTEMAC_BASEADDR1
+	memset(&devinf, 0, sizeof(devinf));
+	devinf.phyaddr = -1;
+	devinf.base_addr = XILINX_LLTEMAC_BASEADDR1;
+#  ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
+	devinf.flags = LL_TEMAC_M_FIFO;
+	devinf.ctrl_addr = XILINX_LLTEMAC_FIFO_BASEADDR1;
+	ret |= xilinx_ll_temac_eth_init(bis, &devinf);
+#  elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
+#   if XILINX_LLTEMAC_SDMA_USE_DCR == 1
+	devinf.flags = LL_TEMAC_M_SDMA_DCR;
+	devinf.ctrl_addr = XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1;
+	ret |= xilinx_ll_temac_eth_init(bis, &devinf);
+#   else
+	devinf.flags = LL_TEMAC_M_SDMA_PLB;
+	devinf.ctrl_addr = XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1;
+	ret |= xilinx_ll_temac_eth_init(bis, &devinf);
+#   endif
+#  endif
+# endif
+#endif /* if 0 */
 #endif
 
 	return ret;
diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c
index 28bc4cd..f6c5fc1 100644
--- a/drivers/net/xilinx_ll_temac.c
+++ b/drivers/net/xilinx_ll_temac.c
@@ -352,7 +352,7 @@ int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf)
  * Returns 1 if the ll_temac device and the mdio bus were initialized
  * otherwise returns 0
  */
-static int xilinx_ll_temac_eth_init(bd_t *bis, struct ll_temac_info *devinf)
+int xilinx_ll_temac_eth_init(bd_t *bis, struct ll_temac_info *devinf)
 {
 	struct ll_temac_mdio_info mdioinf;
 	int ret;
diff --git a/include/xilinx_ll_temac.h b/include/xilinx_ll_temac.h
index af4a09f..8fdce22 100644
--- a/include/xilinx_ll_temac.h
+++ b/include/xilinx_ll_temac.h
@@ -355,4 +355,7 @@ struct ll_temac_info {
 
 int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf);
 
+/* FIXME: xilinx_ll_temac_eth_init() must be again private ? */
+int xilinx_ll_temac_eth_init(bd_t *bis, struct ll_temac_info *devinf);
+
 #endif /* _XILINX_LL_TEMAC_ */
-- 
1.7.0.4

[U-Boot] [PATCH 2/8] microblaze: Enable several ethernet driver compilation

[Michal Simek]

Stephan Linz wrote:
> U-Boot's multipple network supports enables to use
> several ethernet drivers but microblaze-generic
> platform config file select only one driver.
> 
> Reported-by: Michal Simek <monstr@monstr.eu>
> Signed-off-by: Stephan Linz <linz@li-pro.net>
> ---
>  include/configs/microblaze-generic.h |   12 ++++++++----
>  1 files changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
> index 03a6f5a..09ac870 100644
> --- a/include/configs/microblaze-generic.h
> +++ b/include/configs/microblaze-generic.h
> @@ -65,11 +65,15 @@
>  
>  /* ethernet */
>  #undef CONFIG_SYS_ENET
> -#ifdef XILINX_EMACLITE_BASEADDR
> -# define CONFIG_XILINX_EMACLITE		1
> +#if defined(XILINX_EMACLITE_BASEADDR)
> +# define CONFIG_XILINX_EMACLITE	1
>  # define CONFIG_SYS_ENET
> -#elif XILINX_LLTEMAC_BASEADDR
> -# define CONFIG_XILINX_LL_TEMAC		1
> +#endif
> +#if defined(XILINX_LLTEMAC_BASEADDR)  || defined(XILINX_LLTEMAC_BASEADDR1) || \
> +    defined(XILINX_LLTEMAC_BASEADDR2) || defined(XILINX_LLTEMAC_BASEADDR3) || \
> +    defined(XILINX_LLTEMAC_BASEADDR4) || defined(XILINX_LLTEMAC_BASEADDR5) || \
> +    defined(XILINX_LLTEMAC_BASEADDR6) || defined(XILINX_LLTEMAC_BASEADDR7)
> +# define CONFIG_XILINX_LL_TEMAC	1

Why to do it in this way? I believe that the first lltemac driver will have XILINX_LLTEMAC_BASEADDR
and then others. But for all configurations if there is lltemac driver then will have anyone just BASEADDR.

Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 6/8] microblaze: Add faked LL_TEMAC driver configuration

[Michal Simek]

Stephan Linz wrote:
> Expand the specific configuration for the microblaze-generic
> board in xparameters.h with a faked setup to enable the
> LL_TEMAC driver.
> 
> Note: From now the microblaze-generic board is no longer a
> valid board configuration for a real piece of hardware. Rather
> than, we use the file config.mk and xparameters.h as a faked
> board configuration to force the compilation of all potential
> driver code for Microblaze systems.
> 
> Signed-off-by: Stephan Linz <linz@li-pro.net>
> ---
>  board/xilinx/microblaze-generic/config.mk     |    6 ++++--
>  board/xilinx/microblaze-generic/xparameters.h |   24 ++++++++++++++++++++++--
>  2 files changed, 26 insertions(+), 4 deletions(-)
> 
> diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
> index f8d7e26..9fd1015 100644
> --- a/board/xilinx/microblaze-generic/config.mk
> +++ b/board/xilinx/microblaze-generic/config.mk
> @@ -21,8 +21,10 @@
>  # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>  # MA 02111-1307 USA
>  #
> -# CAUTION: This file is automatically generated by libgen.
> -# Version: Xilinx EDK 6.3 EDK_Gmm.12.3
> +# CAUTION: This file is a faked configuration !!!
> +#          There is no real target for the microblaze-generic
> +#          configuration. You have to replace this file with
> +#          the generated file from your Xilinx design flow.
>  #
>  
>  CONFIG_SYS_TEXT_BASE = 0x29000000
> diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
> index fae03bf..69758c3 100644
> --- a/board/xilinx/microblaze-generic/xparameters.h
> +++ b/board/xilinx/microblaze-generic/xparameters.h
> @@ -21,8 +21,10 @@
>   * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>   * MA 02111-1307 USA
>   *
> - * CAUTION: This file is automatically generated by libgen.
> - * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
> + * CAUTION: This file is a faked configuration !!!
> + *          There is no real target for the microblaze-generic
> + *          configuration. You have to replace this file with
> + *          the generated file from your Xilinx design flow.
>   */
>  
>  #define XILINX_BOARD_NAME	microblaze-generic
> @@ -69,3 +71,21 @@
>  
>  /* Ethernet controller is Ethernet_MAC */
>  #define XILINX_EMACLITE_BASEADDR       0x40C00000
> +
> +/* Ethernet controller is Ethernet_MAC */
> +#define XILINX_LLTEMAC_BASEADDR			0x44000000
> +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR	0x42000180
> +#define XILINX_LLTEMAC_BASEADDR1		0x44000040
> +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1	0x42000200

> +#define XILINX_LLTEMAC_BASEADDR2		0x44100000
> +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR2	0x42000280
> +#define XILINX_LLTEMAC_BASEADDR3		0x44100040
> +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR3	0x42000300

Do these two options test anything?

> +#define XILINX_LLTEMAC_BASEADDR4		0x44200000
> +#define XILINX_LLTEMAC_FIFO_BASEADDR4		0x42100000
> +#define XILINX_LLTEMAC_BASEADDR5		0x44200040
> +#define XILINX_LLTEMAC_FIFO_BASEADDR5		0x42110000

> +#define XILINX_LLTEMAC_BASEADDR6		0x44300000
> +#define XILINX_LLTEMAC_FIFO_BASEADDR6		0x42120000
> +#define XILINX_LLTEMAC_BASEADDR7		0x44300040
> +#define XILINX_LLTEMAC_FIFO_BASEADDR7		0x42130000

The same here.

Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 2/8] microblaze: Enable several ethernet driver compilation

[Stephan Linz]

Am Dienstag, den 31.01.2012, 10:00 +0100 schrieb Michal Simek: 
> Stephan Linz wrote:
> > U-Boot's multipple network supports enables to use
> > several ethernet drivers but microblaze-generic
> > platform config file select only one driver.
> > 
> > Reported-by: Michal Simek <monstr@monstr.eu>
> > Signed-off-by: Stephan Linz <linz@li-pro.net>
> > ---
> >  include/configs/microblaze-generic.h |   12 ++++++++----
> >  1 files changed, 8 insertions(+), 4 deletions(-)
> > 
> > diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
> > index 03a6f5a..09ac870 100644
> > --- a/include/configs/microblaze-generic.h
> > +++ b/include/configs/microblaze-generic.h
> > @@ -65,11 +65,15 @@
> >  
> >  /* ethernet */
> >  #undef CONFIG_SYS_ENET
> > -#ifdef XILINX_EMACLITE_BASEADDR
> > -# define CONFIG_XILINX_EMACLITE		1
> > +#if defined(XILINX_EMACLITE_BASEADDR)
> > +# define CONFIG_XILINX_EMACLITE	1
> >  # define CONFIG_SYS_ENET
> > -#elif XILINX_LLTEMAC_BASEADDR
> > -# define CONFIG_XILINX_LL_TEMAC		1
> > +#endif
> > +#if defined(XILINX_LLTEMAC_BASEADDR)  || defined(XILINX_LLTEMAC_BASEADDR1) || \
> > +    defined(XILINX_LLTEMAC_BASEADDR2) || defined(XILINX_LLTEMAC_BASEADDR3) || \
> > +    defined(XILINX_LLTEMAC_BASEADDR4) || defined(XILINX_LLTEMAC_BASEADDR5) || \
> > +    defined(XILINX_LLTEMAC_BASEADDR6) || defined(XILINX_LLTEMAC_BASEADDR7)
> > +# define CONFIG_XILINX_LL_TEMAC	1
> 
> Why to do it in this way? I believe that the first lltemac driver will have XILINX_LLTEMAC_BASEADDR
> and then others.

Right, but we need a definitive agreement that it is so (Xilinx BSP
generator). Did we them? If yes I will drop this part and insert your
original condition (test only XILINX_LLTEMAC_BASEADDR).

> But for all configurations if there is lltemac driver then will have anyone just BASEADDR.
yep


br,
Stephan

[U-Boot] [PATCH 6/8] microblaze: Add faked LL_TEMAC driver configuration

[Stephan Linz]

Am Dienstag, den 31.01.2012, 10:01 +0100 schrieb Michal Simek: 
> Stephan Linz wrote:
> > Expand the specific configuration for the microblaze-generic
> > board in xparameters.h with a faked setup to enable the
> > LL_TEMAC driver.
> > 
> > Note: From now the microblaze-generic board is no longer a
> > valid board configuration for a real piece of hardware. Rather
> > than, we use the file config.mk and xparameters.h as a faked
> > board configuration to force the compilation of all potential
> > driver code for Microblaze systems.
> > 
> > Signed-off-by: Stephan Linz <linz@li-pro.net>
> > ---
> >  board/xilinx/microblaze-generic/config.mk     |    6 ++++--
> >  board/xilinx/microblaze-generic/xparameters.h |   24 ++++++++++++++++++++++--
> >  2 files changed, 26 insertions(+), 4 deletions(-)
> > 
> > diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
> > index f8d7e26..9fd1015 100644
> > --- a/board/xilinx/microblaze-generic/config.mk
> > +++ b/board/xilinx/microblaze-generic/config.mk
> > @@ -21,8 +21,10 @@
> >  # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> >  # MA 02111-1307 USA
> >  #
> > -# CAUTION: This file is automatically generated by libgen.
> > -# Version: Xilinx EDK 6.3 EDK_Gmm.12.3
> > +# CAUTION: This file is a faked configuration !!!
> > +#          There is no real target for the microblaze-generic
> > +#          configuration. You have to replace this file with
> > +#          the generated file from your Xilinx design flow.
> >  #
> >  
> >  CONFIG_SYS_TEXT_BASE = 0x29000000
> > diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
> > index fae03bf..69758c3 100644
> > --- a/board/xilinx/microblaze-generic/xparameters.h
> > +++ b/board/xilinx/microblaze-generic/xparameters.h
> > @@ -21,8 +21,10 @@
> >   * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> >   * MA 02111-1307 USA
> >   *
> > - * CAUTION: This file is automatically generated by libgen.
> > - * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
> > + * CAUTION: This file is a faked configuration !!!
> > + *          There is no real target for the microblaze-generic
> > + *          configuration. You have to replace this file with
> > + *          the generated file from your Xilinx design flow.
> >   */
> >  
> >  #define XILINX_BOARD_NAME	microblaze-generic
> > @@ -69,3 +71,21 @@
> >  
> >  /* Ethernet controller is Ethernet_MAC */
> >  #define XILINX_EMACLITE_BASEADDR       0x40C00000
> > +
> > +/* Ethernet controller is Ethernet_MAC */
> > +#define XILINX_LLTEMAC_BASEADDR			0x44000000
> > +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR	0x42000180
> > +#define XILINX_LLTEMAC_BASEADDR1		0x44000040
> > +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1	0x42000200
> 
> > +#define XILINX_LLTEMAC_BASEADDR2		0x44100000
> > +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR2	0x42000280
> > +#define XILINX_LLTEMAC_BASEADDR3		0x44100040
> > +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR3	0x42000300
> 
> Do these two options test anything?

This is a faked configuration to evaluate the preprocessor stage in
xconversions.h and the ll_temac driver setup in
xilinx_ll_temac_standard_init().

I do not known any FPGA design / board on which I could test it in real
live. But I've run a simple test with BASEADDR1 set to same value of
BASEADDR. So I could test faked memory access to a single TEMAC in
hardware by two driver instance in software -- it works.

> 
> > +#define XILINX_LLTEMAC_BASEADDR4		0x44200000
> > +#define XILINX_LLTEMAC_FIFO_BASEADDR4		0x42100000
> > +#define XILINX_LLTEMAC_BASEADDR5		0x44200040
> > +#define XILINX_LLTEMAC_FIFO_BASEADDR5		0x42110000
> 
> > +#define XILINX_LLTEMAC_BASEADDR6		0x44300000
> > +#define XILINX_LLTEMAC_FIFO_BASEADDR6		0x42120000
> > +#define XILINX_LLTEMAC_BASEADDR7		0x44300040
> > +#define XILINX_LLTEMAC_FIFO_BASEADDR7		0x42130000
> 
> The same here.

The ll_temac driver supports up to eight TEMAC entities in hardware.
That's why I've expand the faked Xilinx parameter list to eight.


br
Stephan

[U-Boot] [PATCH 2/8] microblaze: Enable several ethernet driver compilation

[Michal Simek]

Stephan Linz wrote:
> U-Boot's multipple network supports enables to use
> several ethernet drivers but microblaze-generic
> platform config file select only one driver.
> 
> Reported-by: Michal Simek <monstr@monstr.eu>
> Signed-off-by: Stephan Linz <linz@li-pro.net>
> ---
>  include/configs/microblaze-generic.h |   12 ++++++++----
>  1 files changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
> index 03a6f5a..09ac870 100644
> --- a/include/configs/microblaze-generic.h
> +++ b/include/configs/microblaze-generic.h
> @@ -65,11 +65,15 @@
>  
>  /* ethernet */
>  #undef CONFIG_SYS_ENET
> -#ifdef XILINX_EMACLITE_BASEADDR
> -# define CONFIG_XILINX_EMACLITE		1
> +#if defined(XILINX_EMACLITE_BASEADDR)
> +# define CONFIG_XILINX_EMACLITE	1
>  # define CONFIG_SYS_ENET
> -#elif XILINX_LLTEMAC_BASEADDR
> -# define CONFIG_XILINX_LL_TEMAC		1
> +#endif
> +#if defined(XILINX_LLTEMAC_BASEADDR)  || defined(XILINX_LLTEMAC_BASEADDR1) || \
> +    defined(XILINX_LLTEMAC_BASEADDR2) || defined(XILINX_LLTEMAC_BASEADDR3) || \
> +    defined(XILINX_LLTEMAC_BASEADDR4) || defined(XILINX_LLTEMAC_BASEADDR5) || \
> +    defined(XILINX_LLTEMAC_BASEADDR6) || defined(XILINX_LLTEMAC_BASEADDR7)
> +# define CONFIG_XILINX_LL_TEMAC	1
>  # define CONFIG_SYS_ENET
>  #endif
>  #if defined(XILINX_AXIEMAC_BASEADDR)

I don't agree with this. The whole reason is to enable ll_temac driver
and I believe that all system with ll_temac will starts with XILINX_LLTEMAC_BASEADDR
and then others.
Which means if XILINX_LLTEMAC_BASEADDR is there just enable the driver.

I just can't see the reason to start with BASEADDR1 or 2 or .... or 7.

Michal



-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 4/8] microblaze: Enable TFTP put command

[Michal Simek]

Stephan Linz wrote:
> Signed-off-by: Stephan Linz <linz@li-pro.net>
> ---
>  include/configs/microblaze-generic.h |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
> index 69fcdb6..71d4767 100644
> --- a/include/configs/microblaze-generic.h
> +++ b/include/configs/microblaze-generic.h
> @@ -259,6 +259,7 @@
>  #else
>  # define CONFIG_CMD_PING
>  # define CONFIG_CMD_DHCP
> +# define CONFIG_CMD_TFTPPUT
>  #endif
>  
>  #if defined(CONFIG_SYSTEMACE)

Applied to master branch.

Michal



-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 3/8] microblaze: Enable phylib and mii support

[Michal Simek]

Stephan Linz wrote:
> From: Michal Simek <monstr@monstr.eu>
> 
> Enable phylib and mii support for LLTEMAC or AXI EMAC
> ethernet drivers on Microblaze systems.
> 
> Signed-off-by: Michal Simek <monstr@monstr.eu>
> Acked-by: Stephan Linz <linz@li-pro.net>
> ---
>  include/configs/microblaze-generic.h |   21 +++++++++++++++++++++
>  1 files changed, 21 insertions(+), 0 deletions(-)
> 
> diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
> index 09ac870..69fcdb6 100644
> --- a/include/configs/microblaze-generic.h
> +++ b/include/configs/microblaze-generic.h
> @@ -342,4 +342,25 @@
>  #define CONFIG_FIT		1
>  #define CONFIG_OF_LIBFDT	1
>  
> +#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
> +# define CONFIG_MII		1
> +# define CONFIG_CMD_MII		1
> +# define CONFIG_PHY_GIGE	1
> +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
> +# define CONFIG_PHYLIB		1
> +# define CONFIG_PHY_ATHEROS	1
> +# define CONFIG_PHY_BROADCOM	1
> +# define CONFIG_PHY_DAVICOM	1
> +# define CONFIG_PHY_LXT		1
> +# define CONFIG_PHY_MARVELL	1
> +# define CONFIG_PHY_MICREL	1
> +# define CONFIG_PHY_NATSEMI	1
> +# define CONFIG_PHY_REALTEK	1
> +# define CONFIG_PHY_VITESSE	1
> +#else
> +# undef CONFIG_MII
> +# undef CONFIG_CMD_MII
> +# undef CONFIG_PHYLIB
> +#endif
> +
>  #endif	/* __CONFIG_H */

This is OK and should be enable at least for AXIEMAC even if ll_temac won't go to mainline.
Maybe make sense to do so without waiting for this patchset.

Michal



-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 6/8] microblaze: Add faked LL_TEMAC driver configuration

[Michal Simek]

Stephan Linz wrote:
> Expand the specific configuration for the microblaze-generic
> board in xparameters.h with a faked setup to enable the
> LL_TEMAC driver.
> 
> Note: From now the microblaze-generic board is no longer a
> valid board configuration for a real piece of hardware. Rather
> than, we use the file config.mk and xparameters.h as a faked
> board configuration to force the compilation of all potential
> driver code for Microblaze systems.
> 
> Signed-off-by: Stephan Linz <linz@li-pro.net>
> ---
>  board/xilinx/microblaze-generic/config.mk     |    6 ++++--
>  board/xilinx/microblaze-generic/xparameters.h |   24 ++++++++++++++++++++++--
>  2 files changed, 26 insertions(+), 4 deletions(-)
> 
> diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
> index f8d7e26..9fd1015 100644
> --- a/board/xilinx/microblaze-generic/config.mk
> +++ b/board/xilinx/microblaze-generic/config.mk
> @@ -21,8 +21,10 @@
>  # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>  # MA 02111-1307 USA
>  #
> -# CAUTION: This file is automatically generated by libgen.
> -# Version: Xilinx EDK 6.3 EDK_Gmm.12.3
> +# CAUTION: This file is a faked configuration !!!
> +#          There is no real target for the microblaze-generic
> +#          configuration. You have to replace this file with
> +#          the generated file from your Xilinx design flow.
>  #
>  
>  CONFIG_SYS_TEXT_BASE = 0x29000000
> diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
> index fae03bf..69758c3 100644
> --- a/board/xilinx/microblaze-generic/xparameters.h
> +++ b/board/xilinx/microblaze-generic/xparameters.h
> @@ -21,8 +21,10 @@
>   * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>   * MA 02111-1307 USA
>   *
> - * CAUTION: This file is automatically generated by libgen.
> - * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
> + * CAUTION: This file is a faked configuration !!!
> + *          There is no real target for the microblaze-generic
> + *          configuration. You have to replace this file with
> + *          the generated file from your Xilinx design flow.
>   */
>  
>  #define XILINX_BOARD_NAME	microblaze-generic
> @@ -69,3 +71,21 @@
>  
>  /* Ethernet controller is Ethernet_MAC */
>  #define XILINX_EMACLITE_BASEADDR       0x40C00000
> +
> +/* Ethernet controller is Ethernet_MAC */
> +#define XILINX_LLTEMAC_BASEADDR			0x44000000
> +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR	0x42000180
> +#define XILINX_LLTEMAC_BASEADDR1		0x44000040
> +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1	0x42000200
> +#define XILINX_LLTEMAC_BASEADDR2		0x44100000
> +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR2	0x42000280
> +#define XILINX_LLTEMAC_BASEADDR3		0x44100040
> +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR3	0x42000300
> +#define XILINX_LLTEMAC_BASEADDR4		0x44200000
> +#define XILINX_LLTEMAC_FIFO_BASEADDR4		0x42100000
> +#define XILINX_LLTEMAC_BASEADDR5		0x44200040
> +#define XILINX_LLTEMAC_FIFO_BASEADDR5		0x42110000
> +#define XILINX_LLTEMAC_BASEADDR6		0x44300000
> +#define XILINX_LLTEMAC_FIFO_BASEADDR6		0x42120000
> +#define XILINX_LLTEMAC_BASEADDR7		0x44300040
> +#define XILINX_LLTEMAC_FIFO_BASEADDR7		0x42130000

I can't see the reason to test 4 sdma cases and 4 fifo cases for fake system configuration.
The same thing will work with one sdma and one fifo.

Michal



-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 8/8] microblaze: ll_temac: export xilinx_ll_temac_eth_init() for evaluation

[Michal Simek]

Stephan Linz wrote:
> Signed-off-by: Stephan Linz <linz@li-pro.net>
> ---
>  .../xilinx/microblaze-generic/microblaze-generic.c |   57 ++++++++++++++++++++
>  drivers/net/xilinx_ll_temac.c                      |    2 +-
>  include/xilinx_ll_temac.h                          |    3 +
>  3 files changed, 61 insertions(+), 1 deletions(-)
> 
> diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
> index 517b2f1..d2f56b9 100644
> --- a/board/xilinx/microblaze-generic/microblaze-generic.c
> +++ b/board/xilinx/microblaze-generic/microblaze-generic.c
> @@ -31,6 +31,10 @@
>  #include <asm/microblaze_intc.h>
>  #include <asm/asm.h>
>  
> +#ifdef CONFIG_XILINX_LL_TEMAC
> +#include <xilinx_ll_temac.h>
> +#endif
> +
>  int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>  {
>  #ifdef CONFIG_SYS_GPIO_0
> @@ -92,7 +96,60 @@ int board_eth_init(bd_t *bis)
>  #endif
>  
>  #ifdef CONFIG_XILINX_LL_TEMAC
> +#if 1
> +	/* This should be the preferred way to initialize
> +	 * all the interfaces. */
>  	ret |= xilinx_ll_temac_standard_init(bis);

if 1 is not the best for mainline because it means that below is dead code.

Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 1/8] net: ll_temac: Add LL TEMAC driver to u-boot

[Michal Simek]

Stephan Linz wrote:
> Xilinx LocalLink Tri-Mode Ether MAC driver can be
> used by Xilinx Microblaze or Xilinx ppc405/440 in
> SDMA and FIFO mode. DCR or XPS bus can be used.
> 
> The driver uses and requires MII and PHYLIB.
> 
> CP: 4 warnings: 'Use of volatile is usually wrong'
> I won't fix this, because it depends on the network
> driver subsystem.
> 
> Reported-by: Michal Simek <monstr@monstr.eu>
> Signed-off-by: Stephan Linz <linz@li-pro.net>
> ---
>  drivers/net/Makefile               |    2 +
>  drivers/net/xilinx_ll_temac.c      |  433 ++++++++++++++++++++++++++++++++++++
>  drivers/net/xilinx_ll_temac_fifo.c |  143 ++++++++++++
>  drivers/net/xilinx_ll_temac_mdio.c |  180 +++++++++++++++
>  drivers/net/xilinx_ll_temac_sdma.c |  370 ++++++++++++++++++++++++++++++
>  include/netdev.h                   |    1 +
>  include/xilinx_ll_temac.h          |  358 +++++++++++++++++++++++++++++
>  include/xilinx_ll_temac_fifo.h     |  122 ++++++++++
>  include/xilinx_ll_temac_mdio.h     |   53 +++++
>  include/xilinx_ll_temac_sdma.h     |  281 +++++++++++++++++++++++
>  10 files changed, 1943 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/net/xilinx_ll_temac.c
>  create mode 100644 drivers/net/xilinx_ll_temac_fifo.c
>  create mode 100644 drivers/net/xilinx_ll_temac_mdio.c
>  create mode 100644 drivers/net/xilinx_ll_temac_sdma.c
>  create mode 100644 include/xilinx_ll_temac.h
>  create mode 100644 include/xilinx_ll_temac_fifo.h
>  create mode 100644 include/xilinx_ll_temac_mdio.h
>  create mode 100644 include/xilinx_ll_temac_sdma.h

I can't see the reason to add headers directly to include folder. It should be
fine to have them in drivers/net/ folder.

Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PREVIEW] LL TEMAC v10 refactored -- for evaluation only

[Michal Simek]

Hi Stephan,

Stephan Linz wrote:
> Hi Michal,
> 
> back to your requests and objections I've built up a new patch set for
> evaluation. Some of the changes relate to the Microblaze platform rather
> than the network driver.
> 
> 1) U-Boot configuration variables vs. xparameters.h
> ----------------------------------------------------------------------
> I've tried to find a compromise between the U-Boot coding and
> configuration style and your preference. But at least in the point of
> the many many CPP conditional directives I can not reduce the code. I
> can move the code only to another place. I need a converstion from the
> automaticaly generated content of xparameters.h to the U-Boot
> configuration space. Now you can find this conversion matrix in a new
> platform header, xconversions.h -- I've placed the header in
> board/xilinx/microblaze-generic/ I think, we can find a better place.

Sorry I don't like that idea in general. I think that make no sense to
create infrastructure for several ll_temac driver in bootloader.

The same code in different location is the same solution which I won't like.

> 
> The conversion matrix avoids all the wrong configuration variables
> inside U-Boot code beginning with XILINX_ (and not CONFIG_) and we can
> expand the configuration to new software related options we never get
> from hardware (example special interface naming). This mechanism can
> also be used by other driver and platform code, for example
> arch/microblaze/cpu/cache.c and arch/microblaze/lib/bootm.c (use
> XILINX_USE_DCACHE instead of ex. CONFIG_XILINX_DCACHE),
> common/cmd_mfsl.c (use XILINX_FSL_NUMBER instead of ex.
> CONFIG_XILINX_FSL), serial_xuartlite.c (use XILINX_UARTLITE_BASEADDR,
> XILINX_UARTLITE_BASEADDR1, ...), and probably also in xilinx_emaclite.c
> and xilinx_axi_emac.c when we extand a multi-IP support as we have done
> for the LL TEMAC now. Sure we have to work on, but it's another case (I
> can make some patches if you want)

I agree that we should use the same variable name if has to start with CONFIG_
prefix.
Based on my experience make more sense to move all functionality and configuration
thing to BSP and keep them out of mainline code because none cares in community
that we can change almost everything.
That's why u-boot uses xparamters.h, linux dts and 5 kernel parameters.

Creating any conversions out of BSPs is just wrong way and I won't agree with that.
If you want to talk about renaming some variables I am ok to do so and I can also
change my bsp to cover backward compatibility.

Pretty soon the same situation will be with u-boot for Xilinx Zynq arm platform
where we will have to use the same style to be acceptable.

> Another but not currently existing feasibility would be to generate a
> U-Boot conform xparameters.h, for example
> CONFIG_XILINX_LL_TEMAC0_BASE_ADDR instead of XILINX_LLTEMAC_BASEADDR.
> You and I, we have it in hand. We can change the Xilinx BSP in the near
> future. You in PataLinux and I in my own home-brewed BSP generator TPOS.

As I wrote above. Suggest what we should change and we can do that.

> 
> 2) Standard initialization vs. multiple direct calls from platform
> ----------------------------------------------------------------------
> Returning to the topic "standard" initialization. The last patch will
> show the differences bwetween your prefered way to do all in board init
> and my applicable standard initializition (a single call to the driver).
> Please look at it in the code and decide for yourself.

IRC. I describe you how I would like to see that configuration. It should be
the same as I use for axiemac and emaclite.

> 
> We need a forward-looking decision, what kind of initialization, we want
> to use. Do we want to copy and paste the standard initialization steps
> from ip core to ip core (board init) and from platform to platform
> (Microplace, PPC405, PPC440) or make a simple call to the driver?
> 
> My preferences is to call the driver from platform and let him run all
> the necessary steps, that I do not want knowing on platform side.

You have to know platform all the time.
I want to keep microblaze-generic platform as simple as possible.

If you are not OK with my preferred way you can of course create your new
platform with conversion tables as you like.
In PetaLinux we uses separate platform because of configuration things which lie
above of it.

Honestly if I look at patch v10 1/8 my eyes hurting me because the origin patch (v3 or so)
had ~670 line of code and yours 1943 and do the same things.
 From my point of view I am OK to keep this driver completely out of mainline because
it is based on plb which will be deprecated in near future.
I know that people will still use it for a long time but the question is if make sense
to push to mainline.
I will definitely use v3 in PetaLinux and keep things simpler.
Future is axi driver is in the mainline.

Regards,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

[U-Boot] [PATCH 8/8] microblaze: ll_temac: export xilinx_ll_temac_eth_init() for evaluation

[Stephan Linz]

Am Donnerstag, den 23.02.2012, 12:56 +0100 schrieb Michal Simek: 
> Stephan Linz wrote:
> > Signed-off-by: Stephan Linz <linz@li-pro.net>
> > ---
> >  .../xilinx/microblaze-generic/microblaze-generic.c |   57 ++++++++++++++++++++
> >  drivers/net/xilinx_ll_temac.c                      |    2 +-
> >  include/xilinx_ll_temac.h                          |    3 +
> >  3 files changed, 61 insertions(+), 1 deletions(-)
> > 
> > diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
> > index 517b2f1..d2f56b9 100644
> > --- a/board/xilinx/microblaze-generic/microblaze-generic.c
> > +++ b/board/xilinx/microblaze-generic/microblaze-generic.c
> > @@ -31,6 +31,10 @@
> >  #include <asm/microblaze_intc.h>
> >  #include <asm/asm.h>
> >  
> > +#ifdef CONFIG_XILINX_LL_TEMAC
> > +#include <xilinx_ll_temac.h>
> > +#endif
> > +
> >  int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> >  {
> >  #ifdef CONFIG_SYS_GPIO_0
> > @@ -92,7 +96,60 @@ int board_eth_init(bd_t *bis)
> >  #endif
> >  
> >  #ifdef CONFIG_XILINX_LL_TEMAC
> > +#if 1
> > +	/* This should be the preferred way to initialize
> > +	 * all the interfaces. */
> >  	ret |= xilinx_ll_temac_standard_init(bis);
> 
> if 1 is not the best for mainline because it means that below is dead code.

:) right -- This snippet was only intended for illustration of the
differences


Stephan 

[U-Boot] [PREVIEW] LL TEMAC v10 refactored -- for evaluation only

[Stephan Linz]

Am Donnerstag, den 23.02.2012, 13:22 +0100 schrieb Michal Simek: 
> Hi Stephan,

Hi Michal,

I will take your comments seriously and ar working on a solution without
a complex conversion matrix and a ll_temac standard initialization. Give
me some time to do so ...

Stephan

> 
> Stephan Linz wrote:
> > Hi Michal,
> > 
> > back to your requests and objections I've built up a new patch set for
> > evaluation. Some of the changes relate to the Microblaze platform rather
> > than the network driver.
> > 
> > 1) U-Boot configuration variables vs. xparameters.h
> > ----------------------------------------------------------------------
> > I've tried to find a compromise between the U-Boot coding and
> > configuration style and your preference. But at least in the point of
> > the many many CPP conditional directives I can not reduce the code. I
> > can move the code only to another place. I need a converstion from the
> > automaticaly generated content of xparameters.h to the U-Boot
> > configuration space. Now you can find this conversion matrix in a new
> > platform header, xconversions.h -- I've placed the header in
> > board/xilinx/microblaze-generic/ I think, we can find a better place.
> 
> Sorry I don't like that idea in general. I think that make no sense to
> create infrastructure for several ll_temac driver in bootloader.
> 
> The same code in different location is the same solution which I won't like.
> 
> > 
> > The conversion matrix avoids all the wrong configuration variables
> > inside U-Boot code beginning with XILINX_ (and not CONFIG_) and we can
> > expand the configuration to new software related options we never get
> > from hardware (example special interface naming). This mechanism can
> > also be used by other driver and platform code, for example
> > arch/microblaze/cpu/cache.c and arch/microblaze/lib/bootm.c (use
> > XILINX_USE_DCACHE instead of ex. CONFIG_XILINX_DCACHE),
> > common/cmd_mfsl.c (use XILINX_FSL_NUMBER instead of ex.
> > CONFIG_XILINX_FSL), serial_xuartlite.c (use XILINX_UARTLITE_BASEADDR,
> > XILINX_UARTLITE_BASEADDR1, ...), and probably also in xilinx_emaclite.c
> > and xilinx_axi_emac.c when we extand a multi-IP support as we have done
> > for the LL TEMAC now. Sure we have to work on, but it's another case (I
> > can make some patches if you want)
> 
> I agree that we should use the same variable name if has to start with CONFIG_
> prefix.
> Based on my experience make more sense to move all functionality and configuration
> thing to BSP and keep them out of mainline code because none cares in community
> that we can change almost everything.
> That's why u-boot uses xparamters.h, linux dts and 5 kernel parameters.
> 
> Creating any conversions out of BSPs is just wrong way and I won't agree with that.
> If you want to talk about renaming some variables I am ok to do so and I can also
> change my bsp to cover backward compatibility.
> 
> Pretty soon the same situation will be with u-boot for Xilinx Zynq arm platform
> where we will have to use the same style to be acceptable.
> 
> > Another but not currently existing feasibility would be to generate a
> > U-Boot conform xparameters.h, for example
> > CONFIG_XILINX_LL_TEMAC0_BASE_ADDR instead of XILINX_LLTEMAC_BASEADDR.
> > You and I, we have it in hand. We can change the Xilinx BSP in the near
> > future. You in PataLinux and I in my own home-brewed BSP generator TPOS.
> 
> As I wrote above. Suggest what we should change and we can do that.
> 
> > 
> > 2) Standard initialization vs. multiple direct calls from platform
> > ----------------------------------------------------------------------
> > Returning to the topic "standard" initialization. The last patch will
> > show the differences bwetween your prefered way to do all in board init
> > and my applicable standard initializition (a single call to the driver).
> > Please look at it in the code and decide for yourself.
> 
> IRC. I describe you how I would like to see that configuration. It should be
> the same as I use for axiemac and emaclite.
> 
> > 
> > We need a forward-looking decision, what kind of initialization, we want
> > to use. Do we want to copy and paste the standard initialization steps
> > from ip core to ip core (board init) and from platform to platform
> > (Microplace, PPC405, PPC440) or make a simple call to the driver?
> > 
> > My preferences is to call the driver from platform and let him run all
> > the necessary steps, that I do not want knowing on platform side.
> 
> You have to know platform all the time.
> I want to keep microblaze-generic platform as simple as possible.
> 
> If you are not OK with my preferred way you can of course create your new
> platform with conversion tables as you like.
> In PetaLinux we uses separate platform because of configuration things which lie
> above of it.
> 
> Honestly if I look at patch v10 1/8 my eyes hurting me because the origin patch (v3 or so)
> had ~670 line of code and yours 1943 and do the same things.
>  From my point of view I am OK to keep this driver completely out of mainline because
> it is based on plb which will be deprecated in near future.
> I know that people will still use it for a long time but the question is if make sense
> to push to mainline.
> I will definitely use v3 in PetaLinux and keep things simpler.
> Future is axi driver is in the mainline.
> 
> Regards,
> Michal
> 
> 

-- 
Viele Gr??e,
Stephan Linz
______________________________________________________________________________
MB-Ref: http://www.li-pro.de/xilinx_mb:mbref:start
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