* [PATCH 00/14] dmaengine: imx-dma: merge dma arch code into dmaengine.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel
The following series have to be applied on top of the following patches:
[PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
[PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
is deprecated and no new patches are accepted for it.
This series merges this code into the imx-dma.c dmaengine driver.
[PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
[PATCH 02/14] dmaengine: imx-dma: remove data member form internal structure.
[PATCH 03/14] dmaengine: imx-dma: remove dma_mode member of internal structure.
[PATCH 04/14] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
[PATCH 05/14] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
[PATCH 06/14] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
[PATCH 07/14] dmaengine: imx-dma: remove sg member from internal structure.
[PATCH 08/14] dmaengine: imx-dma: remove in_use field of internal structure.
[PATCH 09/14] dmaengine: imx-dma: remove resbytes field of internal structure.
[PATCH 10/14] dmaengine: imx-dma: remove internal structure.
[PATCH 11/14] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
[PATCH 12/14] dmaengine: imx-dma: integrate 'imx_dmav1_baseaddr' and 'dma_clk' inside dmaengine structure.
[PATCH 13/14] dmaengine: imx-dma: use dev_dbg and dev_warn for messages.
[PATCH 14/14] dmaengine: imx-dma: remove dma-v1.c and dma-v1.h
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 00/14] dmaengine: imx-dma: merge dma arch code into dmaengine.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
The following series have to be applied on top of the following patches:
[PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
[PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
is deprecated and no new patches are accepted for it.
This series merges this code into the imx-dma.c dmaengine driver.
[PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
[PATCH 02/14] dmaengine: imx-dma: remove data member form internal structure.
[PATCH 03/14] dmaengine: imx-dma: remove dma_mode member of internal structure.
[PATCH 04/14] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
[PATCH 05/14] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
[PATCH 06/14] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
[PATCH 07/14] dmaengine: imx-dma: remove sg member from internal structure.
[PATCH 08/14] dmaengine: imx-dma: remove in_use field of internal structure.
[PATCH 09/14] dmaengine: imx-dma: remove resbytes field of internal structure.
[PATCH 10/14] dmaengine: imx-dma: remove internal structure.
[PATCH 11/14] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
[PATCH 12/14] dmaengine: imx-dma: integrate 'imx_dmav1_baseaddr' and 'dma_clk' inside dmaengine structure.
[PATCH 13/14] dmaengine: imx-dma: use dev_dbg and dev_warn for messages.
[PATCH 14/14] dmaengine: imx-dma: remove dma-v1.c and dma-v1.h
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
arch/arm/mach-imx/Kconfig | 6 -
arch/arm/mach-imx/Makefile | 2 -
drivers/dma/Kconfig | 1 -
drivers/dma/imx-dma.c | 591 ++++++++++++++++++++++++++++++++++++++++----
4 files changed, 541 insertions(+), 59 deletions(-)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0e6de36..3da1421 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,3 @@
-config IMX_HAVE_DMA_V1
- bool
-
config HAVE_IMX_GPC
bool
@@ -26,7 +23,6 @@ config SOC_IMX1
bool
select ARCH_MX1
select CPU_ARM920T
- select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
@@ -35,7 +31,6 @@ config SOC_IMX21
select MACH_MX21
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
- select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
@@ -52,7 +47,6 @@ config SOC_IMX27
select MACH_MX27
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
- select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f5920c2..a62dc3a 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,5 +1,3 @@
-obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
-
obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..eb58b91 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -231,7 +231,6 @@ config IMX_SDMA
config IMX_DMA
tristate "i.MX DMA support"
- depends on IMX_HAVE_DMA_V1
select DMA_ENGINE
help
Support the i.MX DMA engine. This engine is integrated into
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index c32103f..28d716c 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -14,7 +14,6 @@
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
-
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
@@ -25,14 +24,88 @@
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
+#include <linux/clk.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <asm/irq.h>
-#include <mach/dma-v1.h>
+#include <mach/dma.h>
#include <mach/hardware.h>
#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
+#define IMX_DMA_CHANNELS 16
+
+#define DMA_MODE_READ 0
+#define DMA_MODE_WRITE 1
+#define DMA_MODE_MASK 1
+
+#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
+#define IMX_DMA_MEMSIZE_32 (0 << 4)
+#define IMX_DMA_MEMSIZE_8 (1 << 4)
+#define IMX_DMA_MEMSIZE_16 (2 << 4)
+#define IMX_DMA_TYPE_LINEAR (0 << 10)
+#define IMX_DMA_TYPE_2D (1 << 10)
+#define IMX_DMA_TYPE_FIFO (2 << 10)
+
+#define IMX_DMA_ERR_BURST (1 << 0)
+#define IMX_DMA_ERR_REQUEST (1 << 1)
+#define IMX_DMA_ERR_TRANSFER (1 << 2)
+#define IMX_DMA_ERR_BUFFER (1 << 3)
+#define IMX_DMA_ERR_TIMEOUT (1 << 4)
+
+#define DMA_DCR 0x00 /* Control Register */
+#define DMA_DISR 0x04 /* Interrupt status Register */
+#define DMA_DIMR 0x08 /* Interrupt mask Register */
+#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
+#define DMA_DRTOSR 0x10 /* Request timeout Register */
+#define DMA_DSESR 0x14 /* Transfer Error Status Register */
+#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
+#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
+#define DMA_WSRA 0x40 /* W-Size Register A */
+#define DMA_XSRA 0x44 /* X-Size Register A */
+#define DMA_YSRA 0x48 /* Y-Size Register A */
+#define DMA_WSRB 0x4c /* W-Size Register B */
+#define DMA_XSRB 0x50 /* X-Size Register B */
+#define DMA_YSRB 0x54 /* Y-Size Register B */
+#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
+#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
+#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
+#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
+#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
+#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
+#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
+#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
+#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
+
+#define DCR_DRST (1<<1)
+#define DCR_DEN (1<<0)
+#define DBTOCR_EN (1<<15)
+#define DBTOCR_CNT(x) ((x) & 0x7fff)
+#define CNTR_CNT(x) ((x) & 0xffffff)
+#define CCR_ACRPT (1<<14)
+#define CCR_DMOD_LINEAR (0x0 << 12)
+#define CCR_DMOD_2D (0x1 << 12)
+#define CCR_DMOD_FIFO (0x2 << 12)
+#define CCR_DMOD_EOBFIFO (0x3 << 12)
+#define CCR_SMOD_LINEAR (0x0 << 10)
+#define CCR_SMOD_2D (0x1 << 10)
+#define CCR_SMOD_FIFO (0x2 << 10)
+#define CCR_SMOD_EOBFIFO (0x3 << 10)
+#define CCR_MDIR_DEC (1<<9)
+#define CCR_MSEL_B (1<<8)
+#define CCR_DSIZ_32 (0x0 << 6)
+#define CCR_DSIZ_8 (0x1 << 6)
+#define CCR_DSIZ_16 (0x2 << 6)
+#define CCR_SSIZ_32 (0x0 << 4)
+#define CCR_SSIZ_8 (0x1 << 4)
+#define CCR_SSIZ_16 (0x2 << 4)
+#define CCR_REN (1<<3)
+#define CCR_RPT (1<<2)
+#define CCR_FRC (1<<1)
+#define CCR_CEN (1<<0)
+#define RTOR_EN (1<<15)
+#define RTOR_CLK (1<<14)
+#define RTOR_PSC (1<<13)
enum imxdma_prep_type {
IMXDMA_DESC_MEMCPY,
@@ -41,6 +114,39 @@ enum imxdma_prep_type {
IMXDMA_DESC_CYCLIC,
};
+/*
+ * struct imxdma_channel_internal - i.MX specific DMA extension
+ * @name: name specified by DMA client
+ * @irq_handler: client callback for end of transfer
+ * @err_handler: client callback for error condition
+ * @data: clients context data for callbacks
+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
+ * @resbytes: total residual number of bytes to transfer
+ * (it can be lower or same as sum of SG mapped chunk sizes)
+ * @sgcount: number of chunks to be read/written
+ *
+ * Structure is used for IMX DMA processing. It would be probably good
+ * @struct dma_struct in the future for external interfacing and use
+ * @struct imxdma_channel_internal only as extension to it.
+ */
+
+struct imxdma_channel_internal {
+ void *data;
+ unsigned int dma_mode;
+ struct scatterlist *sg;
+ unsigned int resbytes;
+
+ int in_use;
+
+ u32 ccr_from_device;
+ u32 ccr_to_device;
+
+ struct timer_list watchdog;
+
+ int hw_chaining;
+};
+
struct imxdma_desc {
struct list_head node;
struct dma_async_tx_descriptor desc;
@@ -63,9 +169,9 @@ struct imxdma_desc {
};
struct imxdma_channel {
+ struct imxdma_channel_internal internal;
struct imxdma_engine *imxdma;
unsigned int channel;
- unsigned int imxdma_channel;
struct tasklet_struct dma_tasklet;
struct list_head ld_free;
@@ -109,28 +215,381 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
return false;
}
-static void imxdma_irq_handler(int channel, void *data)
+/* TODO: put this inside any struct */
+static void __iomem *imx_dmav1_baseaddr;
+static struct clk *dma_clk;
+
+static void imx_dmav1_writel(unsigned val, unsigned offset)
{
- struct imxdma_channel *imxdmac = data;
+ __raw_writel(val, imx_dmav1_baseaddr + offset);
+}
- tasklet_schedule(&imxdmac->dma_tasklet);
+static unsigned imx_dmav1_readl(unsigned offset)
+{
+ return __raw_readl(imx_dmav1_baseaddr + offset);
}
-static void imxdma_err_handler(int channel, void *data, int error)
+static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
{
- struct imxdma_channel *imxdmac = data;
+ if (cpu_is_mx27())
+ return imxdma->hw_chaining;
+ else
+ return 0;
+}
+
+/*
+ * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
+ */
+static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+{
+ struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+ unsigned long now;
+
+ now = min(imxdma->resbytes, sg->length);
+ if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
+ imxdma->resbytes -= now;
+
+ if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+ imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+ else
+ imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+
+ imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+
+ pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
+ "size 0x%08x\n", imxdmac->channel,
+ imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
+ imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
+ imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+
+ return now;
+}
+
+static int
+imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+ unsigned int dma_length, unsigned int dev_addr,
+ unsigned int dmamode)
+{
+ int channel = imxdmac->channel;
+
+ imxdmac->internal.sg = NULL;
+ imxdmac->internal.dma_mode = dmamode;
+
+ if (!dma_address) {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
+ channel);
+ return -EINVAL;
+ }
+
+ if (!dma_length) {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
+ channel);
+ return -EINVAL;
+ }
+
+ if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+ pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+ "dev_addr=0x%08x for read\n",
+ channel, __func__, (unsigned int)dma_address,
+ dma_length, dev_addr);
+
+ imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+ imx_dmav1_writel(dma_address, DMA_DAR(channel));
+ imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+ } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+ pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+ "dev_addr=0x%08x for write\n",
+ channel, __func__, (unsigned int)dma_address,
+ dma_length, dev_addr);
+
+ imx_dmav1_writel(dma_address, DMA_SAR(channel));
+ imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+ imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+ DMA_CCR(channel));
+ } else {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
+ channel);
+ return -EINVAL;
+ }
+ imx_dmav1_writel(dma_length, DMA_CNTR(channel));
+
+ return 0;
+}
+
+static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+{
+ int channel = imxdmac->channel;
+ unsigned long flags;
+
+ pr_debug("imxdma%d: imx_dma_enable\n", channel);
+
+ if (imxdmac->internal.in_use)
+ return;
+
+ local_irq_save(flags);
+
+ imx_dmav1_writel(1 << channel, DMA_DISR);
+ imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
+ imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
+ CCR_ACRPT, DMA_CCR(channel));
+
+ if ((cpu_is_mx21() || cpu_is_mx27()) &&
+ imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
+ imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
+ if (imxdmac->internal.sg) {
+ u32 tmp;
+ imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+ tmp = imx_dmav1_readl(DMA_CCR(channel));
+ imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
+ DMA_CCR(channel));
+ }
+ }
+ imxdmac->internal.in_use = 1;
+
+ local_irq_restore(flags);
+}
+
+static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
+{
+ int channel = imxdmac->channel;
+ unsigned long flags;
+
+ pr_debug("imxdma%d: imx_dma_disable\n", channel);
+
+ if (imxdma_hw_chain(&imxdmac->internal))
+ del_timer(&imxdmac->internal.watchdog);
+
+ local_irq_save(flags);
+ imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
+ imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
+ DMA_CCR(channel));
+ imx_dmav1_writel(1 << channel, DMA_DISR);
+ imxdmac->internal.in_use = 0;
+ local_irq_restore(flags);
+}
+
+static int
+imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
+ unsigned int config_mem, unsigned int dmareq, int hw_chaining)
+{
+ int channel = imxdmac->channel;
+ u32 dreq = 0;
+
+ imxdmac->internal.hw_chaining = 0;
+
+ if (hw_chaining) {
+ imxdmac->internal.hw_chaining = 1;
+ if (!imxdma_hw_chain(&imxdmac->internal))
+ return -EINVAL;
+ }
+
+ if (dmareq)
+ dreq = CCR_REN;
+
+ imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
+ imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
+
+ imx_dmav1_writel(dmareq, DMA_RSSR(channel));
+
+ return 0;
+}
+
+static int
+imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+ struct scatterlist *sg, unsigned int sgcount,
+ unsigned int dma_length, unsigned int dev_addr,
+ unsigned int dmamode)
+{
+ int channel = imxdmac->channel;
+
+ if (imxdmac->internal.in_use)
+ return -EBUSY;
+
+ imxdmac->internal.sg = sg;
+ imxdmac->internal.dma_mode = dmamode;
+ imxdmac->internal.resbytes = dma_length;
+
+ if (!sg || !sgcount) {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
+ channel);
+ return -EINVAL;
+ }
+
+ if (!sg->length) {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
+ channel);
+ return -EINVAL;
+ }
+
+ if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+ pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+ "dev_addr=0x%08x for read\n",
+ channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+ imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+ imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+ } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+ pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+ "dev_addr=0x%08x for write\n",
+ channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+ imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+ imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
+ } else {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
+ channel);
+ return -EINVAL;
+ }
+
+ imxdma_sg_next(imxdmac, sg);
+
+ return 0;
+}
+
+static void imxdma_watchdog(unsigned long data)
+{
+ struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+ int channel = imxdmac->channel;
+
+ imx_dmav1_writel(0, DMA_CCR(channel));
+ imxdmac->internal.in_use = 0;
+ imxdmac->internal.sg = NULL;
+
+ /* Tasklet watchdog error handler */
tasklet_schedule(&imxdmac->dma_tasklet);
+ pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+}
+
+static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
+{
+ struct imxdma_engine *imxdma = dev_id;
+ struct imxdma_channel_internal *internal;
+ unsigned int err_mask;
+ int i, disr;
+ int errcode;
+
+ disr = imx_dmav1_readl(DMA_DISR);
+
+ err_mask = imx_dmav1_readl(DMA_DBTOSR) |
+ imx_dmav1_readl(DMA_DRTOSR) |
+ imx_dmav1_readl(DMA_DSESR) |
+ imx_dmav1_readl(DMA_DBOSR);
+
+ if (!err_mask)
+ return IRQ_HANDLED;
+
+ imx_dmav1_writel(disr & err_mask, DMA_DISR);
+
+ for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+ if (!(err_mask & (1 << i)))
+ continue;
+ internal = &imxdma->channel[i].internal;
+ errcode = 0;
+
+ if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
+ imx_dmav1_writel(1 << i, DMA_DBTOSR);
+ errcode |= IMX_DMA_ERR_BURST;
+ }
+ if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
+ imx_dmav1_writel(1 << i, DMA_DRTOSR);
+ errcode |= IMX_DMA_ERR_REQUEST;
+ }
+ if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
+ imx_dmav1_writel(1 << i, DMA_DSESR);
+ errcode |= IMX_DMA_ERR_TRANSFER;
+ }
+ if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
+ imx_dmav1_writel(1 << i, DMA_DBOSR);
+ errcode |= IMX_DMA_ERR_BUFFER;
+ }
+ /* Tasklet error handler */
+ tasklet_schedule(&imxdma->channel[i].dma_tasklet);
+
+ printk(KERN_WARNING
+ "DMA timeout on channel %d -%s%s%s%s\n", i,
+ errcode & IMX_DMA_ERR_BURST ? " burst" : "",
+ errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
+ errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
+ errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
+ }
+ return IRQ_HANDLED;
}
-static void imxdma_progression(int channel, void *data,
- struct scatterlist *sg)
+static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
{
- struct imxdma_channel *imxdmac = data;
+ struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+ int chno = imxdmac->channel;
+
+ if (imxdma->sg) {
+ u32 tmp;
+ imxdma->sg = sg_next(imxdma->sg);
+
+ if (imxdma->sg) {
+ imxdma_sg_next(imxdmac, imxdma->sg);
+
+ tmp = imx_dmav1_readl(DMA_CCR(chno));
+
+ if (imxdma_hw_chain(imxdma)) {
+ /* FIXME: The timeout should probably be
+ * configurable
+ */
+ mod_timer(&imxdma->watchdog,
+ jiffies + msecs_to_jiffies(500));
+
+ tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
+ imx_dmav1_writel(tmp, DMA_CCR(chno));
+ } else {
+ imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+ tmp |= CCR_CEN;
+ }
+
+ imx_dmav1_writel(tmp, DMA_CCR(chno));
+
+ if (imxdma_chan_is_doing_cyclic(imxdmac))
+ /* Tasklet progression */
+ tasklet_schedule(&imxdmac->dma_tasklet);
+
+ return;
+ }
+ if (imxdma_hw_chain(imxdma)) {
+ del_timer(&imxdma->watchdog);
+ return;
+ }
+ }
+
+ imx_dmav1_writel(0, DMA_CCR(chno));
+ imxdma->in_use = 0;
+ /* Tasklet irq */
tasklet_schedule(&imxdmac->dma_tasklet);
}
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+ struct imxdma_engine *imxdma = dev_id;
+ struct imxdma_channel_internal *internal;
+ int i, disr;
+
+ if (cpu_is_mx21() || cpu_is_mx27())
+ imxdma_err_handler(irq, dev_id);
+
+ disr = imx_dmav1_readl(DMA_DISR);
+
+ pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
+ disr);
+
+ imx_dmav1_writel(disr, DMA_DISR);
+ for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+ if (disr & (1 << i)) {
+ internal = &imxdma->channel[i].internal;
+ dma_irq_handle_channel(&imxdma->channel[i]);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
static int imxdma_xfer_desc(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -139,31 +598,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Configure and enable */
switch (d->type) {
case IMXDMA_DESC_MEMCPY:
- ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+ ret = imxdma_config_channel_hw(imxdmac,
d->config_port, d->config_mem, 0, 0);
if (ret < 0)
return ret;
- ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
+ ret = imxdma_setup_single_hw(imxdmac, d->src,
d->len, d->dest, d->dmamode);
if (ret < 0)
return ret;
break;
+
+ /* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
- ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
- imxdma_progression);
- if (ret < 0)
- return ret;
- /*
- * We fall through here since cyclic transfer is the same as
- * slave_sg adding a progression handler and a specific sg
- * configuration which is done in 'imxdma_prep_dma_cyclic'.
- */
case IMXDMA_DESC_SLAVE_SG:
if (d->dmamode == DMA_MODE_READ)
- ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+ ret = imxdma_setup_sg_hw(imxdmac, d->sg,
d->sgcount, d->len, d->src, d->dmamode);
else
- ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+ ret = imxdma_setup_sg_hw(imxdmac, d->sg,
d->sgcount, d->len, d->dest, d->dmamode);
if (ret < 0)
return ret;
@@ -171,7 +623,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
default:
return -EINVAL;
}
- imx_dma_enable(imxdmac->imxdma_channel);
+ imxdma_enable_hw(imxdmac);
return 0;
}
@@ -223,7 +675,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
switch (cmd) {
case DMA_TERMINATE_ALL:
- imx_dma_disable(imxdmac->imxdma_channel);
+ imxdma_disable_hw(imxdmac);
spin_lock_irqsave(&imxdmac->lock, flags);
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
@@ -253,16 +705,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
mode = IMX_DMA_MEMSIZE_32;
break;
}
- ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+ ret = imxdma_config_channel_hw(imxdmac,
mode | IMX_DMA_TYPE_FIFO,
IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
imxdmac->dma_request, 1);
if (ret)
return ret;
-
- imx_dma_config_burstlen(imxdmac->imxdma_channel,
- imxdmac->watermark_level * imxdmac->word_size);
+ /* Set burst length */
+ imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
+ DMA_BLR(imxdmac->channel));
return 0;
default:
@@ -359,7 +811,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
spin_lock_irqsave(&imxdmac->lock, flags);
- imx_dma_disable(imxdmac->imxdma_channel);
+ imxdma_disable_hw(imxdmac);
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
@@ -545,10 +997,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
}
static int __init imxdma_probe(struct platform_device *pdev)
-{
+ {
struct imxdma_engine *imxdma;
int ret, i;
+ if (cpu_is_mx1())
+ imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+ else if (cpu_is_mx21())
+ imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+ else if (cpu_is_mx27())
+ imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+ else
+ return 0;
+
+ dma_clk = clk_get(NULL, "dma");
+ if (IS_ERR(dma_clk))
+ return PTR_ERR(dma_clk);
+ clk_enable(dma_clk);
+
+ /* reset DMA module */
+ imx_dmav1_writel(DCR_DRST, DMA_DCR);
+
+ if (cpu_is_mx1()) {
+ ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
+ if (ret) {
+ pr_crit("Can't register IRQ for DMA\n");
+ return ret;
+ }
+
+ ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
+ if (ret) {
+ pr_crit("Can't register ERRIRQ for DMA\n");
+ free_irq(MX1_DMA_INT, NULL);
+ return ret;
+ }
+ }
+
+ /* enable DMA module */
+ imx_dmav1_writel(DCR_DEN, DMA_DCR);
+
+ /* clear all interrupts */
+ imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+
+ /* disable interrupts */
+ imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
+
imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
if (!imxdma)
return -ENOMEM;
@@ -562,17 +1055,20 @@ static int __init imxdma_probe(struct platform_device *pdev)
/* Initialize channel parameters */
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
- imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
- DMA_PRIO_MEDIUM);
- if ((int)imxdmac->channel < 0) {
- ret = -ENODEV;
- goto err_init;
+ memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+ if (cpu_is_mx21() || cpu_is_mx27()) {
+ ret = request_irq(MX2x_INT_DMACH0 + i,
+ dma_irq_handler, 0, "DMA", imxdma);
+ if (ret) {
+ pr_crit("Can't register IRQ %d for DMA channel %d\n",
+ MX2x_INT_DMACH0 + i, i);
+ goto err_init;
+ }
+ init_timer(&imxdmac->internal.watchdog);
+ imxdmac->internal.watchdog.function = &imxdma_watchdog;
+ imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
}
- imx_dma_setup_handlers(imxdmac->imxdma_channel,
- imxdma_irq_handler, imxdma_err_handler, imxdmac);
-
imxdmac->imxdma = imxdma;
spin_lock_init(&imxdmac->lock);
@@ -617,10 +1113,8 @@ static int __init imxdma_probe(struct platform_device *pdev)
return 0;
err_init:
- while (--i >= 0) {
- struct imxdma_channel *imxdmac = &imxdma->channel[i];
- imx_dma_free(imxdmac->imxdma_channel);
- }
+ while (--i >= 0)
+ free_irq(MX2x_INT_DMACH0 + i, NULL);
kfree(imxdma);
return ret;
@@ -633,11 +1127,8 @@ static int __exit imxdma_remove(struct platform_device *pdev)
dma_async_device_unregister(&imxdma->dma_device);
- for (i = 0; i < MAX_DMA_CHANNELS; i++) {
- struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
- imx_dma_free(imxdmac->imxdma_channel);
- }
+ for (i = 0; i < MAX_DMA_CHANNELS; i++)
+ free_irq(MX2x_INT_DMACH0 + i, NULL);
kfree(imxdma);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
arch/arm/mach-imx/Kconfig | 6 -
arch/arm/mach-imx/Makefile | 2 -
drivers/dma/Kconfig | 1 -
drivers/dma/imx-dma.c | 591 ++++++++++++++++++++++++++++++++++++++++----
4 files changed, 541 insertions(+), 59 deletions(-)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0e6de36..3da1421 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,3 @@
-config IMX_HAVE_DMA_V1
- bool
-
config HAVE_IMX_GPC
bool
@@ -26,7 +23,6 @@ config SOC_IMX1
bool
select ARCH_MX1
select CPU_ARM920T
- select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
@@ -35,7 +31,6 @@ config SOC_IMX21
select MACH_MX21
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
- select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
@@ -52,7 +47,6 @@ config SOC_IMX27
select MACH_MX27
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
- select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f5920c2..a62dc3a 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,5 +1,3 @@
-obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
-
obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..eb58b91 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -231,7 +231,6 @@ config IMX_SDMA
config IMX_DMA
tristate "i.MX DMA support"
- depends on IMX_HAVE_DMA_V1
select DMA_ENGINE
help
Support the i.MX DMA engine. This engine is integrated into
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index c32103f..28d716c 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -14,7 +14,6 @@
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
-
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
@@ -25,14 +24,88 @@
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
+#include <linux/clk.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <asm/irq.h>
-#include <mach/dma-v1.h>
+#include <mach/dma.h>
#include <mach/hardware.h>
#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
+#define IMX_DMA_CHANNELS 16
+
+#define DMA_MODE_READ 0
+#define DMA_MODE_WRITE 1
+#define DMA_MODE_MASK 1
+
+#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
+#define IMX_DMA_MEMSIZE_32 (0 << 4)
+#define IMX_DMA_MEMSIZE_8 (1 << 4)
+#define IMX_DMA_MEMSIZE_16 (2 << 4)
+#define IMX_DMA_TYPE_LINEAR (0 << 10)
+#define IMX_DMA_TYPE_2D (1 << 10)
+#define IMX_DMA_TYPE_FIFO (2 << 10)
+
+#define IMX_DMA_ERR_BURST (1 << 0)
+#define IMX_DMA_ERR_REQUEST (1 << 1)
+#define IMX_DMA_ERR_TRANSFER (1 << 2)
+#define IMX_DMA_ERR_BUFFER (1 << 3)
+#define IMX_DMA_ERR_TIMEOUT (1 << 4)
+
+#define DMA_DCR 0x00 /* Control Register */
+#define DMA_DISR 0x04 /* Interrupt status Register */
+#define DMA_DIMR 0x08 /* Interrupt mask Register */
+#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
+#define DMA_DRTOSR 0x10 /* Request timeout Register */
+#define DMA_DSESR 0x14 /* Transfer Error Status Register */
+#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
+#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
+#define DMA_WSRA 0x40 /* W-Size Register A */
+#define DMA_XSRA 0x44 /* X-Size Register A */
+#define DMA_YSRA 0x48 /* Y-Size Register A */
+#define DMA_WSRB 0x4c /* W-Size Register B */
+#define DMA_XSRB 0x50 /* X-Size Register B */
+#define DMA_YSRB 0x54 /* Y-Size Register B */
+#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
+#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
+#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
+#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
+#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
+#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
+#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
+#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
+#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
+
+#define DCR_DRST (1<<1)
+#define DCR_DEN (1<<0)
+#define DBTOCR_EN (1<<15)
+#define DBTOCR_CNT(x) ((x) & 0x7fff)
+#define CNTR_CNT(x) ((x) & 0xffffff)
+#define CCR_ACRPT (1<<14)
+#define CCR_DMOD_LINEAR (0x0 << 12)
+#define CCR_DMOD_2D (0x1 << 12)
+#define CCR_DMOD_FIFO (0x2 << 12)
+#define CCR_DMOD_EOBFIFO (0x3 << 12)
+#define CCR_SMOD_LINEAR (0x0 << 10)
+#define CCR_SMOD_2D (0x1 << 10)
+#define CCR_SMOD_FIFO (0x2 << 10)
+#define CCR_SMOD_EOBFIFO (0x3 << 10)
+#define CCR_MDIR_DEC (1<<9)
+#define CCR_MSEL_B (1<<8)
+#define CCR_DSIZ_32 (0x0 << 6)
+#define CCR_DSIZ_8 (0x1 << 6)
+#define CCR_DSIZ_16 (0x2 << 6)
+#define CCR_SSIZ_32 (0x0 << 4)
+#define CCR_SSIZ_8 (0x1 << 4)
+#define CCR_SSIZ_16 (0x2 << 4)
+#define CCR_REN (1<<3)
+#define CCR_RPT (1<<2)
+#define CCR_FRC (1<<1)
+#define CCR_CEN (1<<0)
+#define RTOR_EN (1<<15)
+#define RTOR_CLK (1<<14)
+#define RTOR_PSC (1<<13)
enum imxdma_prep_type {
IMXDMA_DESC_MEMCPY,
@@ -41,6 +114,39 @@ enum imxdma_prep_type {
IMXDMA_DESC_CYCLIC,
};
+/*
+ * struct imxdma_channel_internal - i.MX specific DMA extension
+ * @name: name specified by DMA client
+ * @irq_handler: client callback for end of transfer
+ * @err_handler: client callback for error condition
+ * @data: clients context data for callbacks
+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
+ * @resbytes: total residual number of bytes to transfer
+ * (it can be lower or same as sum of SG mapped chunk sizes)
+ * @sgcount: number of chunks to be read/written
+ *
+ * Structure is used for IMX DMA processing. It would be probably good
+ * @struct dma_struct in the future for external interfacing and use
+ * @struct imxdma_channel_internal only as extension to it.
+ */
+
+struct imxdma_channel_internal {
+ void *data;
+ unsigned int dma_mode;
+ struct scatterlist *sg;
+ unsigned int resbytes;
+
+ int in_use;
+
+ u32 ccr_from_device;
+ u32 ccr_to_device;
+
+ struct timer_list watchdog;
+
+ int hw_chaining;
+};
+
struct imxdma_desc {
struct list_head node;
struct dma_async_tx_descriptor desc;
@@ -63,9 +169,9 @@ struct imxdma_desc {
};
struct imxdma_channel {
+ struct imxdma_channel_internal internal;
struct imxdma_engine *imxdma;
unsigned int channel;
- unsigned int imxdma_channel;
struct tasklet_struct dma_tasklet;
struct list_head ld_free;
@@ -109,28 +215,381 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
return false;
}
-static void imxdma_irq_handler(int channel, void *data)
+/* TODO: put this inside any struct */
+static void __iomem *imx_dmav1_baseaddr;
+static struct clk *dma_clk;
+
+static void imx_dmav1_writel(unsigned val, unsigned offset)
{
- struct imxdma_channel *imxdmac = data;
+ __raw_writel(val, imx_dmav1_baseaddr + offset);
+}
- tasklet_schedule(&imxdmac->dma_tasklet);
+static unsigned imx_dmav1_readl(unsigned offset)
+{
+ return __raw_readl(imx_dmav1_baseaddr + offset);
}
-static void imxdma_err_handler(int channel, void *data, int error)
+static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
{
- struct imxdma_channel *imxdmac = data;
+ if (cpu_is_mx27())
+ return imxdma->hw_chaining;
+ else
+ return 0;
+}
+
+/*
+ * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
+ */
+static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+{
+ struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+ unsigned long now;
+
+ now = min(imxdma->resbytes, sg->length);
+ if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
+ imxdma->resbytes -= now;
+
+ if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+ imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+ else
+ imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+
+ imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+
+ pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
+ "size 0x%08x\n", imxdmac->channel,
+ imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
+ imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
+ imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+
+ return now;
+}
+
+static int
+imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+ unsigned int dma_length, unsigned int dev_addr,
+ unsigned int dmamode)
+{
+ int channel = imxdmac->channel;
+
+ imxdmac->internal.sg = NULL;
+ imxdmac->internal.dma_mode = dmamode;
+
+ if (!dma_address) {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
+ channel);
+ return -EINVAL;
+ }
+
+ if (!dma_length) {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
+ channel);
+ return -EINVAL;
+ }
+
+ if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+ pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+ "dev_addr=0x%08x for read\n",
+ channel, __func__, (unsigned int)dma_address,
+ dma_length, dev_addr);
+
+ imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+ imx_dmav1_writel(dma_address, DMA_DAR(channel));
+ imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+ } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+ pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+ "dev_addr=0x%08x for write\n",
+ channel, __func__, (unsigned int)dma_address,
+ dma_length, dev_addr);
+
+ imx_dmav1_writel(dma_address, DMA_SAR(channel));
+ imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+ imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+ DMA_CCR(channel));
+ } else {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
+ channel);
+ return -EINVAL;
+ }
+ imx_dmav1_writel(dma_length, DMA_CNTR(channel));
+
+ return 0;
+}
+
+static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+{
+ int channel = imxdmac->channel;
+ unsigned long flags;
+
+ pr_debug("imxdma%d: imx_dma_enable\n", channel);
+
+ if (imxdmac->internal.in_use)
+ return;
+
+ local_irq_save(flags);
+
+ imx_dmav1_writel(1 << channel, DMA_DISR);
+ imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
+ imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
+ CCR_ACRPT, DMA_CCR(channel));
+
+ if ((cpu_is_mx21() || cpu_is_mx27()) &&
+ imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
+ imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
+ if (imxdmac->internal.sg) {
+ u32 tmp;
+ imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+ tmp = imx_dmav1_readl(DMA_CCR(channel));
+ imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
+ DMA_CCR(channel));
+ }
+ }
+ imxdmac->internal.in_use = 1;
+
+ local_irq_restore(flags);
+}
+
+static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
+{
+ int channel = imxdmac->channel;
+ unsigned long flags;
+
+ pr_debug("imxdma%d: imx_dma_disable\n", channel);
+
+ if (imxdma_hw_chain(&imxdmac->internal))
+ del_timer(&imxdmac->internal.watchdog);
+
+ local_irq_save(flags);
+ imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
+ imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
+ DMA_CCR(channel));
+ imx_dmav1_writel(1 << channel, DMA_DISR);
+ imxdmac->internal.in_use = 0;
+ local_irq_restore(flags);
+}
+
+static int
+imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
+ unsigned int config_mem, unsigned int dmareq, int hw_chaining)
+{
+ int channel = imxdmac->channel;
+ u32 dreq = 0;
+
+ imxdmac->internal.hw_chaining = 0;
+
+ if (hw_chaining) {
+ imxdmac->internal.hw_chaining = 1;
+ if (!imxdma_hw_chain(&imxdmac->internal))
+ return -EINVAL;
+ }
+
+ if (dmareq)
+ dreq = CCR_REN;
+
+ imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
+ imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
+
+ imx_dmav1_writel(dmareq, DMA_RSSR(channel));
+
+ return 0;
+}
+
+static int
+imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+ struct scatterlist *sg, unsigned int sgcount,
+ unsigned int dma_length, unsigned int dev_addr,
+ unsigned int dmamode)
+{
+ int channel = imxdmac->channel;
+
+ if (imxdmac->internal.in_use)
+ return -EBUSY;
+
+ imxdmac->internal.sg = sg;
+ imxdmac->internal.dma_mode = dmamode;
+ imxdmac->internal.resbytes = dma_length;
+
+ if (!sg || !sgcount) {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
+ channel);
+ return -EINVAL;
+ }
+
+ if (!sg->length) {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
+ channel);
+ return -EINVAL;
+ }
+
+ if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+ pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+ "dev_addr=0x%08x for read\n",
+ channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+ imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+ imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+ } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+ pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+ "dev_addr=0x%08x for write\n",
+ channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+ imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+ imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
+ } else {
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
+ channel);
+ return -EINVAL;
+ }
+
+ imxdma_sg_next(imxdmac, sg);
+
+ return 0;
+}
+
+static void imxdma_watchdog(unsigned long data)
+{
+ struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+ int channel = imxdmac->channel;
+
+ imx_dmav1_writel(0, DMA_CCR(channel));
+ imxdmac->internal.in_use = 0;
+ imxdmac->internal.sg = NULL;
+
+ /* Tasklet watchdog error handler */
tasklet_schedule(&imxdmac->dma_tasklet);
+ pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+}
+
+static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
+{
+ struct imxdma_engine *imxdma = dev_id;
+ struct imxdma_channel_internal *internal;
+ unsigned int err_mask;
+ int i, disr;
+ int errcode;
+
+ disr = imx_dmav1_readl(DMA_DISR);
+
+ err_mask = imx_dmav1_readl(DMA_DBTOSR) |
+ imx_dmav1_readl(DMA_DRTOSR) |
+ imx_dmav1_readl(DMA_DSESR) |
+ imx_dmav1_readl(DMA_DBOSR);
+
+ if (!err_mask)
+ return IRQ_HANDLED;
+
+ imx_dmav1_writel(disr & err_mask, DMA_DISR);
+
+ for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+ if (!(err_mask & (1 << i)))
+ continue;
+ internal = &imxdma->channel[i].internal;
+ errcode = 0;
+
+ if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
+ imx_dmav1_writel(1 << i, DMA_DBTOSR);
+ errcode |= IMX_DMA_ERR_BURST;
+ }
+ if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
+ imx_dmav1_writel(1 << i, DMA_DRTOSR);
+ errcode |= IMX_DMA_ERR_REQUEST;
+ }
+ if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
+ imx_dmav1_writel(1 << i, DMA_DSESR);
+ errcode |= IMX_DMA_ERR_TRANSFER;
+ }
+ if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
+ imx_dmav1_writel(1 << i, DMA_DBOSR);
+ errcode |= IMX_DMA_ERR_BUFFER;
+ }
+ /* Tasklet error handler */
+ tasklet_schedule(&imxdma->channel[i].dma_tasklet);
+
+ printk(KERN_WARNING
+ "DMA timeout on channel %d -%s%s%s%s\n", i,
+ errcode & IMX_DMA_ERR_BURST ? " burst" : "",
+ errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
+ errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
+ errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
+ }
+ return IRQ_HANDLED;
}
-static void imxdma_progression(int channel, void *data,
- struct scatterlist *sg)
+static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
{
- struct imxdma_channel *imxdmac = data;
+ struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+ int chno = imxdmac->channel;
+
+ if (imxdma->sg) {
+ u32 tmp;
+ imxdma->sg = sg_next(imxdma->sg);
+
+ if (imxdma->sg) {
+ imxdma_sg_next(imxdmac, imxdma->sg);
+
+ tmp = imx_dmav1_readl(DMA_CCR(chno));
+
+ if (imxdma_hw_chain(imxdma)) {
+ /* FIXME: The timeout should probably be
+ * configurable
+ */
+ mod_timer(&imxdma->watchdog,
+ jiffies + msecs_to_jiffies(500));
+
+ tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
+ imx_dmav1_writel(tmp, DMA_CCR(chno));
+ } else {
+ imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+ tmp |= CCR_CEN;
+ }
+
+ imx_dmav1_writel(tmp, DMA_CCR(chno));
+
+ if (imxdma_chan_is_doing_cyclic(imxdmac))
+ /* Tasklet progression */
+ tasklet_schedule(&imxdmac->dma_tasklet);
+
+ return;
+ }
+ if (imxdma_hw_chain(imxdma)) {
+ del_timer(&imxdma->watchdog);
+ return;
+ }
+ }
+
+ imx_dmav1_writel(0, DMA_CCR(chno));
+ imxdma->in_use = 0;
+ /* Tasklet irq */
tasklet_schedule(&imxdmac->dma_tasklet);
}
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+ struct imxdma_engine *imxdma = dev_id;
+ struct imxdma_channel_internal *internal;
+ int i, disr;
+
+ if (cpu_is_mx21() || cpu_is_mx27())
+ imxdma_err_handler(irq, dev_id);
+
+ disr = imx_dmav1_readl(DMA_DISR);
+
+ pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
+ disr);
+
+ imx_dmav1_writel(disr, DMA_DISR);
+ for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+ if (disr & (1 << i)) {
+ internal = &imxdma->channel[i].internal;
+ dma_irq_handle_channel(&imxdma->channel[i]);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
static int imxdma_xfer_desc(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -139,31 +598,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Configure and enable */
switch (d->type) {
case IMXDMA_DESC_MEMCPY:
- ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+ ret = imxdma_config_channel_hw(imxdmac,
d->config_port, d->config_mem, 0, 0);
if (ret < 0)
return ret;
- ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
+ ret = imxdma_setup_single_hw(imxdmac, d->src,
d->len, d->dest, d->dmamode);
if (ret < 0)
return ret;
break;
+
+ /* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
- ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
- imxdma_progression);
- if (ret < 0)
- return ret;
- /*
- * We fall through here since cyclic transfer is the same as
- * slave_sg adding a progression handler and a specific sg
- * configuration which is done in 'imxdma_prep_dma_cyclic'.
- */
case IMXDMA_DESC_SLAVE_SG:
if (d->dmamode == DMA_MODE_READ)
- ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+ ret = imxdma_setup_sg_hw(imxdmac, d->sg,
d->sgcount, d->len, d->src, d->dmamode);
else
- ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+ ret = imxdma_setup_sg_hw(imxdmac, d->sg,
d->sgcount, d->len, d->dest, d->dmamode);
if (ret < 0)
return ret;
@@ -171,7 +623,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
default:
return -EINVAL;
}
- imx_dma_enable(imxdmac->imxdma_channel);
+ imxdma_enable_hw(imxdmac);
return 0;
}
@@ -223,7 +675,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
switch (cmd) {
case DMA_TERMINATE_ALL:
- imx_dma_disable(imxdmac->imxdma_channel);
+ imxdma_disable_hw(imxdmac);
spin_lock_irqsave(&imxdmac->lock, flags);
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
@@ -253,16 +705,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
mode = IMX_DMA_MEMSIZE_32;
break;
}
- ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+ ret = imxdma_config_channel_hw(imxdmac,
mode | IMX_DMA_TYPE_FIFO,
IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
imxdmac->dma_request, 1);
if (ret)
return ret;
-
- imx_dma_config_burstlen(imxdmac->imxdma_channel,
- imxdmac->watermark_level * imxdmac->word_size);
+ /* Set burst length */
+ imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
+ DMA_BLR(imxdmac->channel));
return 0;
default:
@@ -359,7 +811,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
spin_lock_irqsave(&imxdmac->lock, flags);
- imx_dma_disable(imxdmac->imxdma_channel);
+ imxdma_disable_hw(imxdmac);
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
@@ -545,10 +997,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
}
static int __init imxdma_probe(struct platform_device *pdev)
-{
+ {
struct imxdma_engine *imxdma;
int ret, i;
+ if (cpu_is_mx1())
+ imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+ else if (cpu_is_mx21())
+ imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+ else if (cpu_is_mx27())
+ imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+ else
+ return 0;
+
+ dma_clk = clk_get(NULL, "dma");
+ if (IS_ERR(dma_clk))
+ return PTR_ERR(dma_clk);
+ clk_enable(dma_clk);
+
+ /* reset DMA module */
+ imx_dmav1_writel(DCR_DRST, DMA_DCR);
+
+ if (cpu_is_mx1()) {
+ ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
+ if (ret) {
+ pr_crit("Can't register IRQ for DMA\n");
+ return ret;
+ }
+
+ ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
+ if (ret) {
+ pr_crit("Can't register ERRIRQ for DMA\n");
+ free_irq(MX1_DMA_INT, NULL);
+ return ret;
+ }
+ }
+
+ /* enable DMA module */
+ imx_dmav1_writel(DCR_DEN, DMA_DCR);
+
+ /* clear all interrupts */
+ imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+
+ /* disable interrupts */
+ imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
+
imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
if (!imxdma)
return -ENOMEM;
@@ -562,17 +1055,20 @@ static int __init imxdma_probe(struct platform_device *pdev)
/* Initialize channel parameters */
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
- imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
- DMA_PRIO_MEDIUM);
- if ((int)imxdmac->channel < 0) {
- ret = -ENODEV;
- goto err_init;
+ memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+ if (cpu_is_mx21() || cpu_is_mx27()) {
+ ret = request_irq(MX2x_INT_DMACH0 + i,
+ dma_irq_handler, 0, "DMA", imxdma);
+ if (ret) {
+ pr_crit("Can't register IRQ %d for DMA channel %d\n",
+ MX2x_INT_DMACH0 + i, i);
+ goto err_init;
+ }
+ init_timer(&imxdmac->internal.watchdog);
+ imxdmac->internal.watchdog.function = &imxdma_watchdog;
+ imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
}
- imx_dma_setup_handlers(imxdmac->imxdma_channel,
- imxdma_irq_handler, imxdma_err_handler, imxdmac);
-
imxdmac->imxdma = imxdma;
spin_lock_init(&imxdmac->lock);
@@ -617,10 +1113,8 @@ static int __init imxdma_probe(struct platform_device *pdev)
return 0;
err_init:
- while (--i >= 0) {
- struct imxdma_channel *imxdmac = &imxdma->channel[i];
- imx_dma_free(imxdmac->imxdma_channel);
- }
+ while (--i >= 0)
+ free_irq(MX2x_INT_DMACH0 + i, NULL);
kfree(imxdma);
return ret;
@@ -633,11 +1127,8 @@ static int __exit imxdma_remove(struct platform_device *pdev)
dma_async_device_unregister(&imxdma->dma_device);
- for (i = 0; i < MAX_DMA_CHANNELS; i++) {
- struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
- imx_dma_free(imxdmac->imxdma_channel);
- }
+ for (i = 0; i < MAX_DMA_CHANNELS; i++)
+ free_irq(MX2x_INT_DMACH0 + i, NULL);
kfree(imxdma);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 02/14] dmaengine: imx-dma: remove data member form internal structure.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
It is not used anywhere in the driver.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 28d716c..1a9be6d 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -132,7 +132,6 @@ enum imxdma_prep_type {
*/
struct imxdma_channel_internal {
- void *data;
unsigned int dma_mode;
struct scatterlist *sg;
unsigned int resbytes;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 02/14] dmaengine: imx-dma: remove data member form internal structure.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
It is not used anywhere in the driver.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 28d716c..1a9be6d 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -132,7 +132,6 @@ enum imxdma_prep_type {
*/
struct imxdma_channel_internal {
- void *data;
unsigned int dma_mode;
struct scatterlist *sg;
unsigned int resbytes;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 03/14] dmaengine: imx-dma: remove dma_mode member of internal structure.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Use direction field which is embedded in the descriptor structure
instead.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 103 +++++++++++++++++++++---------------------------
1 files changed, 45 insertions(+), 58 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 1a9be6d..2c524e1 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -35,10 +35,6 @@
#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
#define IMX_DMA_CHANNELS 16
-#define DMA_MODE_READ 0
-#define DMA_MODE_WRITE 1
-#define DMA_MODE_MASK 1
-
#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
#define IMX_DMA_MEMSIZE_32 (0 << 4)
#define IMX_DMA_MEMSIZE_8 (1 << 4)
@@ -132,7 +128,6 @@ enum imxdma_prep_type {
*/
struct imxdma_channel_internal {
- unsigned int dma_mode;
struct scatterlist *sg;
unsigned int resbytes;
@@ -153,7 +148,7 @@ struct imxdma_desc {
dma_addr_t src;
dma_addr_t dest;
size_t len;
- unsigned int dmamode;
+ enum dma_transfer_direction direction;
enum imxdma_prep_type type;
/* For memcpy and interleaved */
unsigned int config_port;
@@ -239,8 +234,9 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
/*
* imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
*/
-static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
{
+ struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
struct imxdma_channel_internal *imxdma = &imxdmac->internal;
unsigned long now;
@@ -248,7 +244,7 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
imxdma->resbytes -= now;
- if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+ if (d->direction == DMA_DEV_TO_MEM)
imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
else
imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
@@ -265,14 +261,12 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
}
static int
-imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
- unsigned int dma_length, unsigned int dev_addr,
- unsigned int dmamode)
+imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+ unsigned int dma_length, unsigned int dev_addr)
{
int channel = imxdmac->channel;
imxdmac->internal.sg = NULL;
- imxdmac->internal.dma_mode = dmamode;
if (!dma_address) {
printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
@@ -286,38 +280,24 @@ imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
return -EINVAL;
}
- if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
- pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
- "dev_addr=0x%08x for read\n",
- channel, __func__, (unsigned int)dma_address,
- dma_length, dev_addr);
+ pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+ "dev_addr=0x%08x for write\n",
+ channel, __func__, (unsigned int)dma_address,
+ dma_length, dev_addr);
- imx_dmav1_writel(dev_addr, DMA_SAR(channel));
- imx_dmav1_writel(dma_address, DMA_DAR(channel));
- imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
- } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
- pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
- "dev_addr=0x%08x for write\n",
- channel, __func__, (unsigned int)dma_address,
- dma_length, dev_addr);
-
- imx_dmav1_writel(dma_address, DMA_SAR(channel));
- imx_dmav1_writel(dev_addr, DMA_DAR(channel));
- imx_dmav1_writel(imxdmac->internal.ccr_to_device,
- DMA_CCR(channel));
- } else {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
- channel);
- return -EINVAL;
- }
+ imx_dmav1_writel(dma_address, DMA_SAR(channel));
+ imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+ imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+ DMA_CCR(channel));
imx_dmav1_writel(dma_length, DMA_CNTR(channel));
return 0;
}
-static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+static void imxdma_enable_hw(struct imxdma_desc *d)
{
+ struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
int channel = imxdmac->channel;
unsigned long flags;
@@ -338,7 +318,7 @@ static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
if (imxdmac->internal.sg) {
u32 tmp;
- imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+ imxdma_sg_next(d, imxdmac->internal.sg);
tmp = imx_dmav1_readl(DMA_CCR(channel));
imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
DMA_CCR(channel));
@@ -395,18 +375,18 @@ imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_por
}
static int
-imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+imxdma_setup_sg_hw(struct imxdma_desc *d,
struct scatterlist *sg, unsigned int sgcount,
unsigned int dma_length, unsigned int dev_addr,
- unsigned int dmamode)
+ enum dma_transfer_direction direction)
{
+ struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
int channel = imxdmac->channel;
if (imxdmac->internal.in_use)
return -EBUSY;
imxdmac->internal.sg = sg;
- imxdmac->internal.dma_mode = dmamode;
imxdmac->internal.resbytes = dma_length;
if (!sg || !sgcount) {
@@ -421,14 +401,14 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
return -EINVAL;
}
- if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+ if (direction == DMA_DEV_TO_MEM) {
pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
"dev_addr=0x%08x for read\n",
channel, __func__, sg, sgcount, dma_length, dev_addr);
imx_dmav1_writel(dev_addr, DMA_SAR(channel));
imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
- } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+ } else if (direction == DMA_MEM_TO_DEV) {
pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
"dev_addr=0x%08x for write\n",
channel, __func__, sg, sgcount, dma_length, dev_addr);
@@ -441,7 +421,7 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
return -EINVAL;
}
- imxdma_sg_next(imxdmac, sg);
+ imxdma_sg_next(d, sg);
return 0;
}
@@ -519,13 +499,26 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
{
struct imxdma_channel_internal *imxdma = &imxdmac->internal;
int chno = imxdmac->channel;
+ struct imxdma_desc *desc;
if (imxdma->sg) {
u32 tmp;
imxdma->sg = sg_next(imxdma->sg);
if (imxdma->sg) {
- imxdma_sg_next(imxdmac, imxdma->sg);
+
+ spin_lock(&imxdmac->lock);
+ if (list_empty(&imxdmac->ld_active)) {
+ spin_unlock(&imxdmac->lock);
+ goto out;
+ }
+
+ desc = list_first_entry(&imxdmac->ld_active,
+ struct imxdma_desc,
+ node);
+ spin_unlock(&imxdmac->lock);
+
+ imxdma_sg_next(desc, imxdma->sg);
tmp = imx_dmav1_readl(DMA_CCR(chno));
@@ -558,6 +551,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
}
}
+out:
imx_dmav1_writel(0, DMA_CCR(chno));
imxdma->in_use = 0;
/* Tasklet irq */
@@ -601,8 +595,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
d->config_port, d->config_mem, 0, 0);
if (ret < 0)
return ret;
- ret = imxdma_setup_single_hw(imxdmac, d->src,
- d->len, d->dest, d->dmamode);
+ ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
if (ret < 0)
return ret;
break;
@@ -610,19 +603,15 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
- if (d->dmamode == DMA_MODE_READ)
- ret = imxdma_setup_sg_hw(imxdmac, d->sg,
- d->sgcount, d->len, d->src, d->dmamode);
- else
- ret = imxdma_setup_sg_hw(imxdmac, d->sg,
- d->sgcount, d->len, d->dest, d->dmamode);
+ ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
+ imxdmac->per_address, d->direction);
if (ret < 0)
return ret;
break;
default:
return -EINVAL;
}
- imxdma_enable_hw(imxdmac);
+ imxdma_enable_hw(d);
return 0;
}
@@ -867,11 +856,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
desc->sg = sgl;
desc->sgcount = sg_len;
desc->len = dma_length;
+ desc->direction = direction;
if (direction == DMA_DEV_TO_MEM) {
- desc->dmamode = DMA_MODE_READ;
desc->src = imxdmac->per_address;
} else {
- desc->dmamode = DMA_MODE_WRITE;
desc->dest = imxdmac->per_address;
}
desc->desc.callback = NULL;
@@ -927,11 +915,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
desc->sg = imxdmac->sg_list;
desc->sgcount = periods;
desc->len = IMX_DMA_LENGTH_LOOP;
+ desc->direction = direction;
if (direction == DMA_DEV_TO_MEM) {
- desc->dmamode = DMA_MODE_READ;
desc->src = imxdmac->per_address;
} else {
- desc->dmamode = DMA_MODE_WRITE;
desc->dest = imxdmac->per_address;
}
desc->desc.callback = NULL;
@@ -961,7 +948,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
desc->src = src;
desc->dest = dest;
desc->len = len;
- desc->dmamode = DMA_MODE_WRITE;
+ desc->direction = DMA_MEM_TO_MEM;
desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
desc->desc.callback = NULL;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 03/14] dmaengine: imx-dma: remove dma_mode member of internal structure.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Use direction field which is embedded in the descriptor structure
instead.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 103 +++++++++++++++++++++---------------------------
1 files changed, 45 insertions(+), 58 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 1a9be6d..2c524e1 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -35,10 +35,6 @@
#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
#define IMX_DMA_CHANNELS 16
-#define DMA_MODE_READ 0
-#define DMA_MODE_WRITE 1
-#define DMA_MODE_MASK 1
-
#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
#define IMX_DMA_MEMSIZE_32 (0 << 4)
#define IMX_DMA_MEMSIZE_8 (1 << 4)
@@ -132,7 +128,6 @@ enum imxdma_prep_type {
*/
struct imxdma_channel_internal {
- unsigned int dma_mode;
struct scatterlist *sg;
unsigned int resbytes;
@@ -153,7 +148,7 @@ struct imxdma_desc {
dma_addr_t src;
dma_addr_t dest;
size_t len;
- unsigned int dmamode;
+ enum dma_transfer_direction direction;
enum imxdma_prep_type type;
/* For memcpy and interleaved */
unsigned int config_port;
@@ -239,8 +234,9 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
/*
* imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
*/
-static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
{
+ struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
struct imxdma_channel_internal *imxdma = &imxdmac->internal;
unsigned long now;
@@ -248,7 +244,7 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
imxdma->resbytes -= now;
- if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+ if (d->direction == DMA_DEV_TO_MEM)
imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
else
imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
@@ -265,14 +261,12 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
}
static int
-imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
- unsigned int dma_length, unsigned int dev_addr,
- unsigned int dmamode)
+imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+ unsigned int dma_length, unsigned int dev_addr)
{
int channel = imxdmac->channel;
imxdmac->internal.sg = NULL;
- imxdmac->internal.dma_mode = dmamode;
if (!dma_address) {
printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
@@ -286,38 +280,24 @@ imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
return -EINVAL;
}
- if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
- pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
- "dev_addr=0x%08x for read\n",
- channel, __func__, (unsigned int)dma_address,
- dma_length, dev_addr);
+ pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+ "dev_addr=0x%08x for write\n",
+ channel, __func__, (unsigned int)dma_address,
+ dma_length, dev_addr);
- imx_dmav1_writel(dev_addr, DMA_SAR(channel));
- imx_dmav1_writel(dma_address, DMA_DAR(channel));
- imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
- } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
- pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
- "dev_addr=0x%08x for write\n",
- channel, __func__, (unsigned int)dma_address,
- dma_length, dev_addr);
-
- imx_dmav1_writel(dma_address, DMA_SAR(channel));
- imx_dmav1_writel(dev_addr, DMA_DAR(channel));
- imx_dmav1_writel(imxdmac->internal.ccr_to_device,
- DMA_CCR(channel));
- } else {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
- channel);
- return -EINVAL;
- }
+ imx_dmav1_writel(dma_address, DMA_SAR(channel));
+ imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+ imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+ DMA_CCR(channel));
imx_dmav1_writel(dma_length, DMA_CNTR(channel));
return 0;
}
-static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+static void imxdma_enable_hw(struct imxdma_desc *d)
{
+ struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
int channel = imxdmac->channel;
unsigned long flags;
@@ -338,7 +318,7 @@ static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
if (imxdmac->internal.sg) {
u32 tmp;
- imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+ imxdma_sg_next(d, imxdmac->internal.sg);
tmp = imx_dmav1_readl(DMA_CCR(channel));
imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
DMA_CCR(channel));
@@ -395,18 +375,18 @@ imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_por
}
static int
-imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+imxdma_setup_sg_hw(struct imxdma_desc *d,
struct scatterlist *sg, unsigned int sgcount,
unsigned int dma_length, unsigned int dev_addr,
- unsigned int dmamode)
+ enum dma_transfer_direction direction)
{
+ struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
int channel = imxdmac->channel;
if (imxdmac->internal.in_use)
return -EBUSY;
imxdmac->internal.sg = sg;
- imxdmac->internal.dma_mode = dmamode;
imxdmac->internal.resbytes = dma_length;
if (!sg || !sgcount) {
@@ -421,14 +401,14 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
return -EINVAL;
}
- if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+ if (direction == DMA_DEV_TO_MEM) {
pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
"dev_addr=0x%08x for read\n",
channel, __func__, sg, sgcount, dma_length, dev_addr);
imx_dmav1_writel(dev_addr, DMA_SAR(channel));
imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
- } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+ } else if (direction == DMA_MEM_TO_DEV) {
pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
"dev_addr=0x%08x for write\n",
channel, __func__, sg, sgcount, dma_length, dev_addr);
@@ -441,7 +421,7 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
return -EINVAL;
}
- imxdma_sg_next(imxdmac, sg);
+ imxdma_sg_next(d, sg);
return 0;
}
@@ -519,13 +499,26 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
{
struct imxdma_channel_internal *imxdma = &imxdmac->internal;
int chno = imxdmac->channel;
+ struct imxdma_desc *desc;
if (imxdma->sg) {
u32 tmp;
imxdma->sg = sg_next(imxdma->sg);
if (imxdma->sg) {
- imxdma_sg_next(imxdmac, imxdma->sg);
+
+ spin_lock(&imxdmac->lock);
+ if (list_empty(&imxdmac->ld_active)) {
+ spin_unlock(&imxdmac->lock);
+ goto out;
+ }
+
+ desc = list_first_entry(&imxdmac->ld_active,
+ struct imxdma_desc,
+ node);
+ spin_unlock(&imxdmac->lock);
+
+ imxdma_sg_next(desc, imxdma->sg);
tmp = imx_dmav1_readl(DMA_CCR(chno));
@@ -558,6 +551,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
}
}
+out:
imx_dmav1_writel(0, DMA_CCR(chno));
imxdma->in_use = 0;
/* Tasklet irq */
@@ -601,8 +595,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
d->config_port, d->config_mem, 0, 0);
if (ret < 0)
return ret;
- ret = imxdma_setup_single_hw(imxdmac, d->src,
- d->len, d->dest, d->dmamode);
+ ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
if (ret < 0)
return ret;
break;
@@ -610,19 +603,15 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
- if (d->dmamode == DMA_MODE_READ)
- ret = imxdma_setup_sg_hw(imxdmac, d->sg,
- d->sgcount, d->len, d->src, d->dmamode);
- else
- ret = imxdma_setup_sg_hw(imxdmac, d->sg,
- d->sgcount, d->len, d->dest, d->dmamode);
+ ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
+ imxdmac->per_address, d->direction);
if (ret < 0)
return ret;
break;
default:
return -EINVAL;
}
- imxdma_enable_hw(imxdmac);
+ imxdma_enable_hw(d);
return 0;
}
@@ -867,11 +856,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
desc->sg = sgl;
desc->sgcount = sg_len;
desc->len = dma_length;
+ desc->direction = direction;
if (direction == DMA_DEV_TO_MEM) {
- desc->dmamode = DMA_MODE_READ;
desc->src = imxdmac->per_address;
} else {
- desc->dmamode = DMA_MODE_WRITE;
desc->dest = imxdmac->per_address;
}
desc->desc.callback = NULL;
@@ -927,11 +915,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
desc->sg = imxdmac->sg_list;
desc->sgcount = periods;
desc->len = IMX_DMA_LENGTH_LOOP;
+ desc->direction = direction;
if (direction == DMA_DEV_TO_MEM) {
- desc->dmamode = DMA_MODE_READ;
desc->src = imxdmac->per_address;
} else {
- desc->dmamode = DMA_MODE_WRITE;
desc->dest = imxdmac->per_address;
}
desc->desc.callback = NULL;
@@ -961,7 +948,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
desc->src = src;
desc->dest = dest;
desc->len = len;
- desc->dmamode = DMA_MODE_WRITE;
+ desc->direction = DMA_MEM_TO_MEM;
desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
desc->desc.callback = NULL;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 04/14] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 57 ++++++++++++-------------------------------------
1 files changed, 14 insertions(+), 43 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 2c524e1..8a0afb1 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -260,41 +260,6 @@ static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
return now;
}
-static int
-imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
- unsigned int dma_length, unsigned int dev_addr)
-{
- int channel = imxdmac->channel;
-
- imxdmac->internal.sg = NULL;
-
- if (!dma_address) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
- channel);
- return -EINVAL;
- }
-
- if (!dma_length) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
- channel);
- return -EINVAL;
- }
-
- pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
- "dev_addr=0x%08x for write\n",
- channel, __func__, (unsigned int)dma_address,
- dma_length, dev_addr);
-
- imx_dmav1_writel(dma_address, DMA_SAR(channel));
- imx_dmav1_writel(dev_addr, DMA_DAR(channel));
- imx_dmav1_writel(imxdmac->internal.ccr_to_device,
- DMA_CCR(channel));
-
- imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
- return 0;
-}
-
static void imxdma_enable_hw(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -586,20 +551,26 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
static int imxdma_xfer_desc(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
int ret;
/* Configure and enable */
switch (d->type) {
case IMXDMA_DESC_MEMCPY:
- ret = imxdma_config_channel_hw(imxdmac,
- d->config_port, d->config_mem, 0, 0);
- if (ret < 0)
- return ret;
- ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
- if (ret < 0)
- return ret;
- break;
+ imxdmac->internal.sg = NULL;
+
+ imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
+ imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
+ imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+ DMA_CCR(imxdmac->channel));
+ imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+
+ dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
+ "dma_length=%d\n", __func__, imxdmac->channel,
+ d->dest, d->src, d->len);
+
+ break;
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 04/14] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 57 ++++++++++++-------------------------------------
1 files changed, 14 insertions(+), 43 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 2c524e1..8a0afb1 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -260,41 +260,6 @@ static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
return now;
}
-static int
-imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
- unsigned int dma_length, unsigned int dev_addr)
-{
- int channel = imxdmac->channel;
-
- imxdmac->internal.sg = NULL;
-
- if (!dma_address) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
- channel);
- return -EINVAL;
- }
-
- if (!dma_length) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
- channel);
- return -EINVAL;
- }
-
- pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
- "dev_addr=0x%08x for write\n",
- channel, __func__, (unsigned int)dma_address,
- dma_length, dev_addr);
-
- imx_dmav1_writel(dma_address, DMA_SAR(channel));
- imx_dmav1_writel(dev_addr, DMA_DAR(channel));
- imx_dmav1_writel(imxdmac->internal.ccr_to_device,
- DMA_CCR(channel));
-
- imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
- return 0;
-}
-
static void imxdma_enable_hw(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -586,20 +551,26 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
static int imxdma_xfer_desc(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
int ret;
/* Configure and enable */
switch (d->type) {
case IMXDMA_DESC_MEMCPY:
- ret = imxdma_config_channel_hw(imxdmac,
- d->config_port, d->config_mem, 0, 0);
- if (ret < 0)
- return ret;
- ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
- if (ret < 0)
- return ret;
- break;
+ imxdmac->internal.sg = NULL;
+
+ imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
+ imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
+ imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+ DMA_CCR(imxdmac->channel));
+ imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+
+ dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
+ "dma_length=%d\n", __func__, imxdmac->channel,
+ d->dest, d->src, d->len);
+
+ break;
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 05/14] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 46 +++++++++++++---------------------------------
1 files changed, 13 insertions(+), 33 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 8a0afb1..5432b04 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -314,32 +314,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
}
static int
-imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
- unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
- int channel = imxdmac->channel;
- u32 dreq = 0;
-
- imxdmac->internal.hw_chaining = 0;
-
- if (hw_chaining) {
- imxdmac->internal.hw_chaining = 1;
- if (!imxdma_hw_chain(&imxdmac->internal))
- return -EINVAL;
- }
-
- if (dmareq)
- dreq = CCR_REN;
-
- imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
- imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
-
- imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
- return 0;
-}
-
-static int
imxdma_setup_sg_hw(struct imxdma_desc *d,
struct scatterlist *sg, unsigned int sgcount,
unsigned int dma_length, unsigned int dev_addr,
@@ -628,7 +602,6 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
{
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
struct dma_slave_config *dmaengine_cfg = (void *)arg;
- int ret;
unsigned long flags;
unsigned int mode = 0;
@@ -664,13 +637,20 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
mode = IMX_DMA_MEMSIZE_32;
break;
}
- ret = imxdma_config_channel_hw(imxdmac,
- mode | IMX_DMA_TYPE_FIFO,
- IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
- imxdmac->dma_request, 1);
- if (ret)
- return ret;
+ imxdmac->internal.hw_chaining = 1;
+ if (!imxdma_hw_chain(&imxdmac->internal))
+ return -EINVAL;
+ imxdmac->internal.ccr_from_device =
+ (mode | IMX_DMA_TYPE_FIFO) |
+ ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
+ CCR_REN;
+ imxdmac->internal.ccr_to_device =
+ (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
+ ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
+ imx_dmav1_writel(imxdmac->dma_request,
+ DMA_RSSR(imxdmac->channel));
+
/* Set burst length */
imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
DMA_BLR(imxdmac->channel));
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 05/14] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 46 +++++++++++++---------------------------------
1 files changed, 13 insertions(+), 33 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 8a0afb1..5432b04 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -314,32 +314,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
}
static int
-imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
- unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
- int channel = imxdmac->channel;
- u32 dreq = 0;
-
- imxdmac->internal.hw_chaining = 0;
-
- if (hw_chaining) {
- imxdmac->internal.hw_chaining = 1;
- if (!imxdma_hw_chain(&imxdmac->internal))
- return -EINVAL;
- }
-
- if (dmareq)
- dreq = CCR_REN;
-
- imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
- imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
-
- imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
- return 0;
-}
-
-static int
imxdma_setup_sg_hw(struct imxdma_desc *d,
struct scatterlist *sg, unsigned int sgcount,
unsigned int dma_length, unsigned int dev_addr,
@@ -628,7 +602,6 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
{
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
struct dma_slave_config *dmaengine_cfg = (void *)arg;
- int ret;
unsigned long flags;
unsigned int mode = 0;
@@ -664,13 +637,20 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
mode = IMX_DMA_MEMSIZE_32;
break;
}
- ret = imxdma_config_channel_hw(imxdmac,
- mode | IMX_DMA_TYPE_FIFO,
- IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
- imxdmac->dma_request, 1);
- if (ret)
- return ret;
+ imxdmac->internal.hw_chaining = 1;
+ if (!imxdma_hw_chain(&imxdmac->internal))
+ return -EINVAL;
+ imxdmac->internal.ccr_from_device =
+ (mode | IMX_DMA_TYPE_FIFO) |
+ ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
+ CCR_REN;
+ imxdmac->internal.ccr_to_device =
+ (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
+ ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
+ imx_dmav1_writel(imxdmac->dma_request,
+ DMA_RSSR(imxdmac->channel));
+
/* Set burst length */
imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
DMA_BLR(imxdmac->channel));
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 06/14] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Removing this function allows moving 'ccr_to_device' and
'ccr_from_device' from internal struct to channel struct.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 97 ++++++++++++++++++-------------------------------
1 files changed, 35 insertions(+), 62 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 5432b04..cb45aff 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -133,9 +133,6 @@ struct imxdma_channel_internal {
int in_use;
- u32 ccr_from_device;
- u32 ccr_to_device;
-
struct timer_list watchdog;
int hw_chaining;
@@ -180,6 +177,8 @@ struct imxdma_channel {
dma_cookie_t last_completed;
int dma_request;
struct scatterlist *sg_list;
+ u32 ccr_from_device;
+ u32 ccr_to_device;
};
#define MAX_DMA_CHANNELS 8
@@ -313,58 +312,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
local_irq_restore(flags);
}
-static int
-imxdma_setup_sg_hw(struct imxdma_desc *d,
- struct scatterlist *sg, unsigned int sgcount,
- unsigned int dma_length, unsigned int dev_addr,
- enum dma_transfer_direction direction)
-{
- struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
- int channel = imxdmac->channel;
-
- if (imxdmac->internal.in_use)
- return -EBUSY;
-
- imxdmac->internal.sg = sg;
- imxdmac->internal.resbytes = dma_length;
-
- if (!sg || !sgcount) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
- channel);
- return -EINVAL;
- }
-
- if (!sg->length) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
- channel);
- return -EINVAL;
- }
-
- if (direction == DMA_DEV_TO_MEM) {
- pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
- "dev_addr=0x%08x for read\n",
- channel, __func__, sg, sgcount, dma_length, dev_addr);
-
- imx_dmav1_writel(dev_addr, DMA_SAR(channel));
- imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
- } else if (direction == DMA_MEM_TO_DEV) {
- pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
- "dev_addr=0x%08x for write\n",
- channel, __func__, sg, sgcount, dma_length, dev_addr);
-
- imx_dmav1_writel(dev_addr, DMA_DAR(channel));
- imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
- } else {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
- channel);
- return -EINVAL;
- }
-
- imxdma_sg_next(d, sg);
-
- return 0;
-}
-
static void imxdma_watchdog(unsigned long data)
{
struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
@@ -548,10 +495,37 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
- ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
- imxdmac->per_address, d->direction);
- if (ret < 0)
- return ret;
+ imxdmac->internal.sg = d->sg;
+ imxdmac->internal.resbytes = d->len;
+
+ if (d->direction == DMA_DEV_TO_MEM) {
+ imx_dmav1_writel(imxdmac->per_address,
+ DMA_SAR(imxdmac->channel));
+ imx_dmav1_writel(imxdmac->ccr_from_device,
+ DMA_CCR(imxdmac->channel));
+
+ dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+ "total length=%d dev_addr=0x%08x (dev2mem)\n",
+ __func__, imxdmac->channel, d->sg, d->sgcount,
+ d->len, imxdmac->per_address);
+ } else if (d->direction == DMA_MEM_TO_DEV) {
+ imx_dmav1_writel(imxdmac->per_address,
+ DMA_DAR(imxdmac->channel));
+ imx_dmav1_writel(imxdmac->ccr_to_device,
+ DMA_CCR(imxdmac->channel));
+
+ dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+ "total length=%d dev_addr=0x%08x (mem2dev)\n",
+ __func__, imxdmac->channel, d->sg, d->sgcount,
+ d->len, imxdmac->per_address);
+ } else {
+ dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
+ __func__, imxdmac->channel);
+ return -EINVAL;
+ }
+
+ imxdma_sg_next(d, d->sg);
+
break;
default:
return -EINVAL;
@@ -641,11 +615,10 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
imxdmac->internal.hw_chaining = 1;
if (!imxdma_hw_chain(&imxdmac->internal))
return -EINVAL;
- imxdmac->internal.ccr_from_device =
- (mode | IMX_DMA_TYPE_FIFO) |
+ imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
CCR_REN;
- imxdmac->internal.ccr_to_device =
+ imxdmac->ccr_to_device =
(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
imx_dmav1_writel(imxdmac->dma_request,
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 06/14] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Removing this function allows moving 'ccr_to_device' and
'ccr_from_device' from internal struct to channel struct.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 97 ++++++++++++++++++-------------------------------
1 files changed, 35 insertions(+), 62 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 5432b04..cb45aff 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -133,9 +133,6 @@ struct imxdma_channel_internal {
int in_use;
- u32 ccr_from_device;
- u32 ccr_to_device;
-
struct timer_list watchdog;
int hw_chaining;
@@ -180,6 +177,8 @@ struct imxdma_channel {
dma_cookie_t last_completed;
int dma_request;
struct scatterlist *sg_list;
+ u32 ccr_from_device;
+ u32 ccr_to_device;
};
#define MAX_DMA_CHANNELS 8
@@ -313,58 +312,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
local_irq_restore(flags);
}
-static int
-imxdma_setup_sg_hw(struct imxdma_desc *d,
- struct scatterlist *sg, unsigned int sgcount,
- unsigned int dma_length, unsigned int dev_addr,
- enum dma_transfer_direction direction)
-{
- struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
- int channel = imxdmac->channel;
-
- if (imxdmac->internal.in_use)
- return -EBUSY;
-
- imxdmac->internal.sg = sg;
- imxdmac->internal.resbytes = dma_length;
-
- if (!sg || !sgcount) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
- channel);
- return -EINVAL;
- }
-
- if (!sg->length) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
- channel);
- return -EINVAL;
- }
-
- if (direction == DMA_DEV_TO_MEM) {
- pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
- "dev_addr=0x%08x for read\n",
- channel, __func__, sg, sgcount, dma_length, dev_addr);
-
- imx_dmav1_writel(dev_addr, DMA_SAR(channel));
- imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
- } else if (direction == DMA_MEM_TO_DEV) {
- pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
- "dev_addr=0x%08x for write\n",
- channel, __func__, sg, sgcount, dma_length, dev_addr);
-
- imx_dmav1_writel(dev_addr, DMA_DAR(channel));
- imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
- } else {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
- channel);
- return -EINVAL;
- }
-
- imxdma_sg_next(d, sg);
-
- return 0;
-}
-
static void imxdma_watchdog(unsigned long data)
{
struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
@@ -548,10 +495,37 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
- ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
- imxdmac->per_address, d->direction);
- if (ret < 0)
- return ret;
+ imxdmac->internal.sg = d->sg;
+ imxdmac->internal.resbytes = d->len;
+
+ if (d->direction == DMA_DEV_TO_MEM) {
+ imx_dmav1_writel(imxdmac->per_address,
+ DMA_SAR(imxdmac->channel));
+ imx_dmav1_writel(imxdmac->ccr_from_device,
+ DMA_CCR(imxdmac->channel));
+
+ dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+ "total length=%d dev_addr=0x%08x (dev2mem)\n",
+ __func__, imxdmac->channel, d->sg, d->sgcount,
+ d->len, imxdmac->per_address);
+ } else if (d->direction == DMA_MEM_TO_DEV) {
+ imx_dmav1_writel(imxdmac->per_address,
+ DMA_DAR(imxdmac->channel));
+ imx_dmav1_writel(imxdmac->ccr_to_device,
+ DMA_CCR(imxdmac->channel));
+
+ dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+ "total length=%d dev_addr=0x%08x (mem2dev)\n",
+ __func__, imxdmac->channel, d->sg, d->sgcount,
+ d->len, imxdmac->per_address);
+ } else {
+ dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
+ __func__, imxdmac->channel);
+ return -EINVAL;
+ }
+
+ imxdma_sg_next(d, d->sg);
+
break;
default:
return -EINVAL;
@@ -641,11 +615,10 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
imxdmac->internal.hw_chaining = 1;
if (!imxdma_hw_chain(&imxdmac->internal))
return -EINVAL;
- imxdmac->internal.ccr_from_device =
- (mode | IMX_DMA_TYPE_FIFO) |
+ imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
CCR_REN;
- imxdmac->internal.ccr_to_device =
+ imxdmac->ccr_to_device =
(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
imx_dmav1_writel(imxdmac->dma_request,
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 07/14] dmaengine: imx-dma: remove sg member from internal structure.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 42 ++++++++++++++++++------------------------
1 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index cb45aff..ed94207 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -128,7 +128,6 @@ enum imxdma_prep_type {
*/
struct imxdma_channel_internal {
- struct scatterlist *sg;
unsigned int resbytes;
int in_use;
@@ -278,11 +277,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
CCR_ACRPT, DMA_CCR(channel));
if ((cpu_is_mx21() || cpu_is_mx27()) &&
- imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
- imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
- if (imxdmac->internal.sg) {
+ d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+ d->sg = sg_next(d->sg);
+ if (d->sg) {
u32 tmp;
- imxdma_sg_next(d, imxdmac->internal.sg);
+ imxdma_sg_next(d, d->sg);
tmp = imx_dmav1_readl(DMA_CCR(channel));
imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
DMA_CCR(channel));
@@ -319,7 +318,6 @@ static void imxdma_watchdog(unsigned long data)
imx_dmav1_writel(0, DMA_CCR(channel));
imxdmac->internal.in_use = 0;
- imxdmac->internal.sg = NULL;
/* Tasklet watchdog error handler */
tasklet_schedule(&imxdmac->dma_tasklet);
@@ -387,24 +385,23 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
int chno = imxdmac->channel;
struct imxdma_desc *desc;
- if (imxdma->sg) {
- u32 tmp;
- imxdma->sg = sg_next(imxdma->sg);
-
- if (imxdma->sg) {
+ spin_lock(&imxdmac->lock);
+ if (list_empty(&imxdmac->ld_active)) {
+ spin_unlock(&imxdmac->lock);
+ goto out;
+ }
- spin_lock(&imxdmac->lock);
- if (list_empty(&imxdmac->ld_active)) {
- spin_unlock(&imxdmac->lock);
- goto out;
- }
+ desc = list_first_entry(&imxdmac->ld_active,
+ struct imxdma_desc,
+ node);
+ spin_unlock(&imxdmac->lock);
- desc = list_first_entry(&imxdmac->ld_active,
- struct imxdma_desc,
- node);
- spin_unlock(&imxdmac->lock);
+ if (desc->sg) {
+ u32 tmp;
+ desc->sg = sg_next(desc->sg);
- imxdma_sg_next(desc, imxdma->sg);
+ if (desc->sg) {
+ imxdma_sg_next(desc, desc->sg);
tmp = imx_dmav1_readl(DMA_CCR(chno));
@@ -478,8 +475,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Configure and enable */
switch (d->type) {
case IMXDMA_DESC_MEMCPY:
- imxdmac->internal.sg = NULL;
-
imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
imx_dmav1_writel(d->config_mem | (d->config_port << 2),
@@ -495,7 +490,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
- imxdmac->internal.sg = d->sg;
imxdmac->internal.resbytes = d->len;
if (d->direction == DMA_DEV_TO_MEM) {
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 07/14] dmaengine: imx-dma: remove sg member from internal structure.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 42 ++++++++++++++++++------------------------
1 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index cb45aff..ed94207 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -128,7 +128,6 @@ enum imxdma_prep_type {
*/
struct imxdma_channel_internal {
- struct scatterlist *sg;
unsigned int resbytes;
int in_use;
@@ -278,11 +277,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
CCR_ACRPT, DMA_CCR(channel));
if ((cpu_is_mx21() || cpu_is_mx27()) &&
- imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
- imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
- if (imxdmac->internal.sg) {
+ d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+ d->sg = sg_next(d->sg);
+ if (d->sg) {
u32 tmp;
- imxdma_sg_next(d, imxdmac->internal.sg);
+ imxdma_sg_next(d, d->sg);
tmp = imx_dmav1_readl(DMA_CCR(channel));
imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
DMA_CCR(channel));
@@ -319,7 +318,6 @@ static void imxdma_watchdog(unsigned long data)
imx_dmav1_writel(0, DMA_CCR(channel));
imxdmac->internal.in_use = 0;
- imxdmac->internal.sg = NULL;
/* Tasklet watchdog error handler */
tasklet_schedule(&imxdmac->dma_tasklet);
@@ -387,24 +385,23 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
int chno = imxdmac->channel;
struct imxdma_desc *desc;
- if (imxdma->sg) {
- u32 tmp;
- imxdma->sg = sg_next(imxdma->sg);
-
- if (imxdma->sg) {
+ spin_lock(&imxdmac->lock);
+ if (list_empty(&imxdmac->ld_active)) {
+ spin_unlock(&imxdmac->lock);
+ goto out;
+ }
- spin_lock(&imxdmac->lock);
- if (list_empty(&imxdmac->ld_active)) {
- spin_unlock(&imxdmac->lock);
- goto out;
- }
+ desc = list_first_entry(&imxdmac->ld_active,
+ struct imxdma_desc,
+ node);
+ spin_unlock(&imxdmac->lock);
- desc = list_first_entry(&imxdmac->ld_active,
- struct imxdma_desc,
- node);
- spin_unlock(&imxdmac->lock);
+ if (desc->sg) {
+ u32 tmp;
+ desc->sg = sg_next(desc->sg);
- imxdma_sg_next(desc, imxdma->sg);
+ if (desc->sg) {
+ imxdma_sg_next(desc, desc->sg);
tmp = imx_dmav1_readl(DMA_CCR(chno));
@@ -478,8 +475,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Configure and enable */
switch (d->type) {
case IMXDMA_DESC_MEMCPY:
- imxdmac->internal.sg = NULL;
-
imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
imx_dmav1_writel(d->config_mem | (d->config_port << 2),
@@ -495,7 +490,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
- imxdmac->internal.sg = d->sg;
imxdmac->internal.resbytes = d->len;
if (d->direction == DMA_DEV_TO_MEM) {
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 08/14] dmaengine: imx-dma: remove in_use field of internal structure.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 10 ----------
1 files changed, 0 insertions(+), 10 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index ed94207..1e66ee6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -130,8 +130,6 @@ enum imxdma_prep_type {
struct imxdma_channel_internal {
unsigned int resbytes;
- int in_use;
-
struct timer_list watchdog;
int hw_chaining;
@@ -266,9 +264,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
pr_debug("imxdma%d: imx_dma_enable\n", channel);
- if (imxdmac->internal.in_use)
- return;
-
local_irq_save(flags);
imx_dmav1_writel(1 << channel, DMA_DISR);
@@ -287,7 +282,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
DMA_CCR(channel));
}
}
- imxdmac->internal.in_use = 1;
local_irq_restore(flags);
}
@@ -307,7 +301,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
DMA_CCR(channel));
imx_dmav1_writel(1 << channel, DMA_DISR);
- imxdmac->internal.in_use = 0;
local_irq_restore(flags);
}
@@ -317,7 +310,6 @@ static void imxdma_watchdog(unsigned long data)
int channel = imxdmac->channel;
imx_dmav1_writel(0, DMA_CCR(channel));
- imxdmac->internal.in_use = 0;
/* Tasklet watchdog error handler */
tasklet_schedule(&imxdmac->dma_tasklet);
@@ -436,7 +428,6 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
out:
imx_dmav1_writel(0, DMA_CCR(chno));
- imxdma->in_use = 0;
/* Tasklet irq */
tasklet_schedule(&imxdmac->dma_tasklet);
}
@@ -470,7 +461,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
struct imxdma_engine *imxdma = imxdmac->imxdma;
- int ret;
/* Configure and enable */
switch (d->type) {
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 08/14] dmaengine: imx-dma: remove in_use field of internal structure.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 10 ----------
1 files changed, 0 insertions(+), 10 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index ed94207..1e66ee6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -130,8 +130,6 @@ enum imxdma_prep_type {
struct imxdma_channel_internal {
unsigned int resbytes;
- int in_use;
-
struct timer_list watchdog;
int hw_chaining;
@@ -266,9 +264,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
pr_debug("imxdma%d: imx_dma_enable\n", channel);
- if (imxdmac->internal.in_use)
- return;
-
local_irq_save(flags);
imx_dmav1_writel(1 << channel, DMA_DISR);
@@ -287,7 +282,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
DMA_CCR(channel));
}
}
- imxdmac->internal.in_use = 1;
local_irq_restore(flags);
}
@@ -307,7 +301,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
DMA_CCR(channel));
imx_dmav1_writel(1 << channel, DMA_DISR);
- imxdmac->internal.in_use = 0;
local_irq_restore(flags);
}
@@ -317,7 +310,6 @@ static void imxdma_watchdog(unsigned long data)
int channel = imxdmac->channel;
imx_dmav1_writel(0, DMA_CCR(channel));
- imxdmac->internal.in_use = 0;
/* Tasklet watchdog error handler */
tasklet_schedule(&imxdmac->dma_tasklet);
@@ -436,7 +428,6 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
out:
imx_dmav1_writel(0, DMA_CCR(chno));
- imxdma->in_use = 0;
/* Tasklet irq */
tasklet_schedule(&imxdmac->dma_tasklet);
}
@@ -470,7 +461,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
struct imxdma_engine *imxdma = imxdmac->imxdma;
- int ret;
/* Configure and enable */
switch (d->type) {
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 09/14] dmaengine: imx-dma: remove resbytes field of internal structure.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 11 +++--------
1 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 1e66ee6..d525f1e 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -128,8 +128,6 @@ enum imxdma_prep_type {
*/
struct imxdma_channel_internal {
- unsigned int resbytes;
-
struct timer_list watchdog;
int hw_chaining;
@@ -233,12 +231,11 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
- struct imxdma_channel_internal *imxdma = &imxdmac->internal;
unsigned long now;
- now = min(imxdma->resbytes, sg->length);
- if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
- imxdma->resbytes -= now;
+ now = min(d->len, sg->length);
+ if (d->len != IMX_DMA_LENGTH_LOOP)
+ d->len -= now;
if (d->direction == DMA_DEV_TO_MEM)
imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
@@ -480,8 +477,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
- imxdmac->internal.resbytes = d->len;
-
if (d->direction == DMA_DEV_TO_MEM) {
imx_dmav1_writel(imxdmac->per_address,
DMA_SAR(imxdmac->channel));
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 09/14] dmaengine: imx-dma: remove resbytes field of internal structure.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 11 +++--------
1 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 1e66ee6..d525f1e 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -128,8 +128,6 @@ enum imxdma_prep_type {
*/
struct imxdma_channel_internal {
- unsigned int resbytes;
-
struct timer_list watchdog;
int hw_chaining;
@@ -233,12 +231,11 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
- struct imxdma_channel_internal *imxdma = &imxdmac->internal;
unsigned long now;
- now = min(imxdma->resbytes, sg->length);
- if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
- imxdma->resbytes -= now;
+ now = min(d->len, sg->length);
+ if (d->len != IMX_DMA_LENGTH_LOOP)
+ d->len -= now;
if (d->direction == DMA_DEV_TO_MEM)
imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
@@ -480,8 +477,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
- imxdmac->internal.resbytes = d->len;
-
if (d->direction == DMA_DEV_TO_MEM) {
imx_dmav1_writel(imxdmac->per_address,
DMA_SAR(imxdmac->channel));
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 10/14] dmaengine: imx-dma: remove internal structure.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 64 +++++++++++++-----------------------------------
1 files changed, 18 insertions(+), 46 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d525f1e..2f72447 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -110,29 +110,6 @@ enum imxdma_prep_type {
IMXDMA_DESC_CYCLIC,
};
-/*
- * struct imxdma_channel_internal - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- * (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imxdma_channel_internal only as extension to it.
- */
-
-struct imxdma_channel_internal {
- struct timer_list watchdog;
-
- int hw_chaining;
-};
-
struct imxdma_desc {
struct list_head node;
struct dma_async_tx_descriptor desc;
@@ -155,7 +132,8 @@ struct imxdma_desc {
};
struct imxdma_channel {
- struct imxdma_channel_internal internal;
+ int hw_chaining;
+ struct timer_list watchdog;
struct imxdma_engine *imxdma;
unsigned int channel;
@@ -217,10 +195,10 @@ static unsigned imx_dmav1_readl(unsigned offset)
return __raw_readl(imx_dmav1_baseaddr + offset);
}
-static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
+static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
{
if (cpu_is_mx27())
- return imxdma->hw_chaining;
+ return imxdmac->hw_chaining;
else
return 0;
}
@@ -269,7 +247,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
CCR_ACRPT, DMA_CCR(channel));
if ((cpu_is_mx21() || cpu_is_mx27()) &&
- d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+ d->sg && imxdma_hw_chain(imxdmac)) {
d->sg = sg_next(d->sg);
if (d->sg) {
u32 tmp;
@@ -290,8 +268,8 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
pr_debug("imxdma%d: imx_dma_disable\n", channel);
- if (imxdma_hw_chain(&imxdmac->internal))
- del_timer(&imxdmac->internal.watchdog);
+ if (imxdma_hw_chain(imxdmac))
+ del_timer(&imxdmac->watchdog);
local_irq_save(flags);
imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
@@ -316,7 +294,6 @@ static void imxdma_watchdog(unsigned long data)
static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
{
struct imxdma_engine *imxdma = dev_id;
- struct imxdma_channel_internal *internal;
unsigned int err_mask;
int i, disr;
int errcode;
@@ -336,7 +313,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
if (!(err_mask & (1 << i)))
continue;
- internal = &imxdma->channel[i].internal;
errcode = 0;
if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
@@ -370,7 +346,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
{
- struct imxdma_channel_internal *imxdma = &imxdmac->internal;
int chno = imxdmac->channel;
struct imxdma_desc *desc;
@@ -394,11 +369,11 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
tmp = imx_dmav1_readl(DMA_CCR(chno));
- if (imxdma_hw_chain(imxdma)) {
+ if (imxdma_hw_chain(imxdmac)) {
/* FIXME: The timeout should probably be
* configurable
*/
- mod_timer(&imxdma->watchdog,
+ mod_timer(&imxdmac->watchdog,
jiffies + msecs_to_jiffies(500));
tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
@@ -417,8 +392,8 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
return;
}
- if (imxdma_hw_chain(imxdma)) {
- del_timer(&imxdma->watchdog);
+ if (imxdma_hw_chain(imxdmac)) {
+ del_timer(&imxdmac->watchdog);
return;
}
}
@@ -432,7 +407,6 @@ out:
static irqreturn_t dma_irq_handler(int irq, void *dev_id)
{
struct imxdma_engine *imxdma = dev_id;
- struct imxdma_channel_internal *internal;
int i, disr;
if (cpu_is_mx21() || cpu_is_mx27())
@@ -445,10 +419,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
imx_dmav1_writel(disr, DMA_DISR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
- if (disr & (1 << i)) {
- internal = &imxdma->channel[i].internal;
+ if (disr & (1 << i))
dma_irq_handle_channel(&imxdma->channel[i]);
- }
}
return IRQ_HANDLED;
@@ -591,8 +563,8 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
break;
}
- imxdmac->internal.hw_chaining = 1;
- if (!imxdma_hw_chain(&imxdmac->internal))
+ imxdmac->hw_chaining = 1;
+ if (!imxdma_hw_chain(imxdmac))
return -EINVAL;
imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
@@ -944,7 +916,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
/* Initialize channel parameters */
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
struct imxdma_channel *imxdmac = &imxdma->channel[i];
- memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+
if (cpu_is_mx21() || cpu_is_mx27()) {
ret = request_irq(MX2x_INT_DMACH0 + i,
dma_irq_handler, 0, "DMA", imxdma);
@@ -953,9 +925,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
MX2x_INT_DMACH0 + i, i);
goto err_init;
}
- init_timer(&imxdmac->internal.watchdog);
- imxdmac->internal.watchdog.function = &imxdma_watchdog;
- imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
+ init_timer(&imxdmac->watchdog);
+ imxdmac->watchdog.function = &imxdma_watchdog;
+ imxdmac->watchdog.data = (unsigned long)imxdmac;
}
imxdmac->imxdma = imxdma;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 10/14] dmaengine: imx-dma: remove internal structure.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 64 +++++++++++++-----------------------------------
1 files changed, 18 insertions(+), 46 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d525f1e..2f72447 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -110,29 +110,6 @@ enum imxdma_prep_type {
IMXDMA_DESC_CYCLIC,
};
-/*
- * struct imxdma_channel_internal - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- * (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imxdma_channel_internal only as extension to it.
- */
-
-struct imxdma_channel_internal {
- struct timer_list watchdog;
-
- int hw_chaining;
-};
-
struct imxdma_desc {
struct list_head node;
struct dma_async_tx_descriptor desc;
@@ -155,7 +132,8 @@ struct imxdma_desc {
};
struct imxdma_channel {
- struct imxdma_channel_internal internal;
+ int hw_chaining;
+ struct timer_list watchdog;
struct imxdma_engine *imxdma;
unsigned int channel;
@@ -217,10 +195,10 @@ static unsigned imx_dmav1_readl(unsigned offset)
return __raw_readl(imx_dmav1_baseaddr + offset);
}
-static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
+static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
{
if (cpu_is_mx27())
- return imxdma->hw_chaining;
+ return imxdmac->hw_chaining;
else
return 0;
}
@@ -269,7 +247,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
CCR_ACRPT, DMA_CCR(channel));
if ((cpu_is_mx21() || cpu_is_mx27()) &&
- d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+ d->sg && imxdma_hw_chain(imxdmac)) {
d->sg = sg_next(d->sg);
if (d->sg) {
u32 tmp;
@@ -290,8 +268,8 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
pr_debug("imxdma%d: imx_dma_disable\n", channel);
- if (imxdma_hw_chain(&imxdmac->internal))
- del_timer(&imxdmac->internal.watchdog);
+ if (imxdma_hw_chain(imxdmac))
+ del_timer(&imxdmac->watchdog);
local_irq_save(flags);
imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
@@ -316,7 +294,6 @@ static void imxdma_watchdog(unsigned long data)
static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
{
struct imxdma_engine *imxdma = dev_id;
- struct imxdma_channel_internal *internal;
unsigned int err_mask;
int i, disr;
int errcode;
@@ -336,7 +313,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
if (!(err_mask & (1 << i)))
continue;
- internal = &imxdma->channel[i].internal;
errcode = 0;
if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
@@ -370,7 +346,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
{
- struct imxdma_channel_internal *imxdma = &imxdmac->internal;
int chno = imxdmac->channel;
struct imxdma_desc *desc;
@@ -394,11 +369,11 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
tmp = imx_dmav1_readl(DMA_CCR(chno));
- if (imxdma_hw_chain(imxdma)) {
+ if (imxdma_hw_chain(imxdmac)) {
/* FIXME: The timeout should probably be
* configurable
*/
- mod_timer(&imxdma->watchdog,
+ mod_timer(&imxdmac->watchdog,
jiffies + msecs_to_jiffies(500));
tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
@@ -417,8 +392,8 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
return;
}
- if (imxdma_hw_chain(imxdma)) {
- del_timer(&imxdma->watchdog);
+ if (imxdma_hw_chain(imxdmac)) {
+ del_timer(&imxdmac->watchdog);
return;
}
}
@@ -432,7 +407,6 @@ out:
static irqreturn_t dma_irq_handler(int irq, void *dev_id)
{
struct imxdma_engine *imxdma = dev_id;
- struct imxdma_channel_internal *internal;
int i, disr;
if (cpu_is_mx21() || cpu_is_mx27())
@@ -445,10 +419,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
imx_dmav1_writel(disr, DMA_DISR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
- if (disr & (1 << i)) {
- internal = &imxdma->channel[i].internal;
+ if (disr & (1 << i))
dma_irq_handle_channel(&imxdma->channel[i]);
- }
}
return IRQ_HANDLED;
@@ -591,8 +563,8 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
break;
}
- imxdmac->internal.hw_chaining = 1;
- if (!imxdma_hw_chain(&imxdmac->internal))
+ imxdmac->hw_chaining = 1;
+ if (!imxdma_hw_chain(imxdmac))
return -EINVAL;
imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
@@ -944,7 +916,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
/* Initialize channel parameters */
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
struct imxdma_channel *imxdmac = &imxdma->channel[i];
- memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+
if (cpu_is_mx21() || cpu_is_mx27()) {
ret = request_irq(MX2x_INT_DMACH0 + i,
dma_irq_handler, 0, "DMA", imxdma);
@@ -953,9 +925,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
MX2x_INT_DMACH0 + i, i);
goto err_init;
}
- init_timer(&imxdmac->internal.watchdog);
- imxdmac->internal.watchdog.function = &imxdma_watchdog;
- imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
+ init_timer(&imxdmac->watchdog);
+ imxdmac->watchdog.function = &imxdma_watchdog;
+ imxdmac->watchdog.data = (unsigned long)imxdmac;
}
imxdmac->imxdma = imxdma;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 11/14] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 9 +++++----
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 2f72447..d65eec6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -206,9 +206,10 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
/*
* imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
*/
-static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+ struct scatterlist *sg = d->sg;
unsigned long now;
now = min(d->len, sg->length);
@@ -251,7 +252,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
d->sg = sg_next(d->sg);
if (d->sg) {
u32 tmp;
- imxdma_sg_next(d, d->sg);
+ imxdma_sg_next(d);
tmp = imx_dmav1_readl(DMA_CCR(channel));
imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
DMA_CCR(channel));
@@ -365,7 +366,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
desc->sg = sg_next(desc->sg);
if (desc->sg) {
- imxdma_sg_next(desc, desc->sg);
+ imxdma_sg_next(desc);
tmp = imx_dmav1_readl(DMA_CCR(chno));
@@ -475,7 +476,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
return -EINVAL;
}
- imxdma_sg_next(d, d->sg);
+ imxdma_sg_next(d);
break;
default:
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 11/14] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 9 +++++----
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 2f72447..d65eec6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -206,9 +206,10 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
/*
* imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
*/
-static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+ struct scatterlist *sg = d->sg;
unsigned long now;
now = min(d->len, sg->length);
@@ -251,7 +252,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
d->sg = sg_next(d->sg);
if (d->sg) {
u32 tmp;
- imxdma_sg_next(d, d->sg);
+ imxdma_sg_next(d);
tmp = imx_dmav1_readl(DMA_CCR(channel));
imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
DMA_CCR(channel));
@@ -365,7 +366,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
desc->sg = sg_next(desc->sg);
if (desc->sg) {
- imxdma_sg_next(desc, desc->sg);
+ imxdma_sg_next(desc);
tmp = imx_dmav1_readl(DMA_CCR(chno));
@@ -475,7 +476,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
return -EINVAL;
}
- imxdma_sg_next(d, d->sg);
+ imxdma_sg_next(d);
break;
default:
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 12/14] dmaengine: imx-dma: integrate 'imx_dmav1_baseaddr' and 'dma_clk' inside dmaengine structure.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 169 +++++++++++++++++++++++++++----------------------
1 files changed, 93 insertions(+), 76 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d65eec6..fe0f126 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -160,6 +160,8 @@ struct imxdma_engine {
struct device *dev;
struct device_dma_parameters dma_parms;
struct dma_device dma_device;
+ void __iomem *base;
+ struct clk *dma_clk;
struct imxdma_channel channel[MAX_DMA_CHANNELS];
};
@@ -181,18 +183,17 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
return false;
}
-/* TODO: put this inside any struct */
-static void __iomem *imx_dmav1_baseaddr;
-static struct clk *dma_clk;
-static void imx_dmav1_writel(unsigned val, unsigned offset)
+
+static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
+ unsigned offset)
{
- __raw_writel(val, imx_dmav1_baseaddr + offset);
+ __raw_writel(val, imxdma->base + offset);
}
-static unsigned imx_dmav1_readl(unsigned offset)
+static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
{
- return __raw_readl(imx_dmav1_baseaddr + offset);
+ return __raw_readl(imxdma->base + offset);
}
static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
@@ -209,6 +210,7 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
static inline int imxdma_sg_next(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
struct scatterlist *sg = d->sg;
unsigned long now;
@@ -217,17 +219,19 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
d->len -= now;
if (d->direction == DMA_DEV_TO_MEM)
- imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, sg->dma_address,
+ DMA_DAR(imxdmac->channel));
else
- imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, sg->dma_address,
+ DMA_SAR(imxdmac->channel));
- imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
"size 0x%08x\n", imxdmac->channel,
- imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
- imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
- imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+ imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
+ imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
+ imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
return now;
}
@@ -235,6 +239,7 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
static void imxdma_enable_hw(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
int channel = imxdmac->channel;
unsigned long flags;
@@ -242,10 +247,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
local_irq_save(flags);
- imx_dmav1_writel(1 << channel, DMA_DISR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
- CCR_ACRPT, DMA_CCR(channel));
+ imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
+ imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
+ ~(1 << channel), DMA_DIMR);
+ imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
+ CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
if ((cpu_is_mx21() || cpu_is_mx27()) &&
d->sg && imxdma_hw_chain(imxdmac)) {
@@ -253,9 +259,9 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
if (d->sg) {
u32 tmp;
imxdma_sg_next(d);
- tmp = imx_dmav1_readl(DMA_CCR(channel));
- imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
- DMA_CCR(channel));
+ tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
+ imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
+ DMA_CCR(channel));
}
}
@@ -264,6 +270,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
{
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
int channel = imxdmac->channel;
unsigned long flags;
@@ -273,19 +280,21 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
del_timer(&imxdmac->watchdog);
local_irq_save(flags);
- imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
- DMA_CCR(channel));
- imx_dmav1_writel(1 << channel, DMA_DISR);
+ imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
+ (1 << channel), DMA_DIMR);
+ imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
+ ~CCR_CEN, DMA_CCR(channel));
+ imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
local_irq_restore(flags);
}
static void imxdma_watchdog(unsigned long data)
{
struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
int channel = imxdmac->channel;
- imx_dmav1_writel(0, DMA_CCR(channel));
+ imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
/* Tasklet watchdog error handler */
tasklet_schedule(&imxdmac->dma_tasklet);
@@ -299,37 +308,37 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
int i, disr;
int errcode;
- disr = imx_dmav1_readl(DMA_DISR);
+ disr = imx_dmav1_readl(imxdma, DMA_DISR);
- err_mask = imx_dmav1_readl(DMA_DBTOSR) |
- imx_dmav1_readl(DMA_DRTOSR) |
- imx_dmav1_readl(DMA_DSESR) |
- imx_dmav1_readl(DMA_DBOSR);
+ err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
+ imx_dmav1_readl(imxdma, DMA_DRTOSR) |
+ imx_dmav1_readl(imxdma, DMA_DSESR) |
+ imx_dmav1_readl(imxdma, DMA_DBOSR);
if (!err_mask)
return IRQ_HANDLED;
- imx_dmav1_writel(disr & err_mask, DMA_DISR);
+ imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
if (!(err_mask & (1 << i)))
continue;
errcode = 0;
- if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DBTOSR);
+ if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
+ imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
errcode |= IMX_DMA_ERR_BURST;
}
- if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DRTOSR);
+ if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
+ imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
errcode |= IMX_DMA_ERR_REQUEST;
}
- if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DSESR);
+ if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
+ imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
errcode |= IMX_DMA_ERR_TRANSFER;
}
- if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DBOSR);
+ if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
+ imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
errcode |= IMX_DMA_ERR_BUFFER;
}
/* Tasklet error handler */
@@ -347,6 +356,7 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
{
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
int chno = imxdmac->channel;
struct imxdma_desc *desc;
@@ -368,7 +378,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
if (desc->sg) {
imxdma_sg_next(desc);
- tmp = imx_dmav1_readl(DMA_CCR(chno));
+ tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
if (imxdma_hw_chain(imxdmac)) {
/* FIXME: The timeout should probably be
@@ -378,13 +388,14 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
jiffies + msecs_to_jiffies(500));
tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
- imx_dmav1_writel(tmp, DMA_CCR(chno));
+ imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
} else {
- imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+ imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
+ DMA_CCR(chno));
tmp |= CCR_CEN;
}
- imx_dmav1_writel(tmp, DMA_CCR(chno));
+ imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
if (imxdma_chan_is_doing_cyclic(imxdmac))
/* Tasklet progression */
@@ -400,7 +411,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
}
out:
- imx_dmav1_writel(0, DMA_CCR(chno));
+ imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
/* Tasklet irq */
tasklet_schedule(&imxdmac->dma_tasklet);
}
@@ -413,12 +424,12 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
if (cpu_is_mx21() || cpu_is_mx27())
imxdma_err_handler(irq, dev_id);
- disr = imx_dmav1_readl(DMA_DISR);
+ disr = imx_dmav1_readl(imxdma, DMA_DISR);
pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
disr);
- imx_dmav1_writel(disr, DMA_DISR);
+ imx_dmav1_writel(imxdma, disr, DMA_DISR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
if (disr & (1 << i))
dma_irq_handle_channel(&imxdma->channel[i]);
@@ -435,12 +446,12 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Configure and enable */
switch (d->type) {
case IMXDMA_DESC_MEMCPY:
- imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
- imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
- imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+ imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
DMA_CCR(imxdmac->channel));
- imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
"dma_length=%d\n", __func__, imxdmac->channel,
@@ -451,9 +462,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
if (d->direction == DMA_DEV_TO_MEM) {
- imx_dmav1_writel(imxdmac->per_address,
+ imx_dmav1_writel(imxdma, imxdmac->per_address,
DMA_SAR(imxdmac->channel));
- imx_dmav1_writel(imxdmac->ccr_from_device,
+ imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
DMA_CCR(imxdmac->channel));
dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -461,9 +472,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
__func__, imxdmac->channel, d->sg, d->sgcount,
d->len, imxdmac->per_address);
} else if (d->direction == DMA_MEM_TO_DEV) {
- imx_dmav1_writel(imxdmac->per_address,
+ imx_dmav1_writel(imxdma, imxdmac->per_address,
DMA_DAR(imxdmac->channel));
- imx_dmav1_writel(imxdmac->ccr_to_device,
+ imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
DMA_CCR(imxdmac->channel));
dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -528,6 +539,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
{
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
struct dma_slave_config *dmaengine_cfg = (void *)arg;
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
unsigned long flags;
unsigned int mode = 0;
@@ -573,12 +585,12 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
imxdmac->ccr_to_device =
(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
- imx_dmav1_writel(imxdmac->dma_request,
+ imx_dmav1_writel(imxdma, imxdmac->dma_request,
DMA_RSSR(imxdmac->channel));
/* Set burst length */
- imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
- DMA_BLR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, imxdmac->watermark_level *
+ imxdmac->word_size, DMA_BLR(imxdmac->channel));
return 0;
default:
@@ -863,27 +875,35 @@ static int __init imxdma_probe(struct platform_device *pdev)
struct imxdma_engine *imxdma;
int ret, i;
- if (cpu_is_mx1())
- imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
- else if (cpu_is_mx21())
- imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
- else if (cpu_is_mx27())
- imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
- else
+
+ imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
+ if (!imxdma)
+ return -ENOMEM;
+
+ if (cpu_is_mx1()) {
+ imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+ } else if (cpu_is_mx21()) {
+ imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+ } else if (cpu_is_mx27()) {
+ imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+ } else {
+ kfree(imxdma);
return 0;
+ }
- dma_clk = clk_get(NULL, "dma");
- if (IS_ERR(dma_clk))
- return PTR_ERR(dma_clk);
- clk_enable(dma_clk);
+ imxdma->dma_clk = clk_get(NULL, "dma");
+ if (IS_ERR(imxdma->dma_clk))
+ return PTR_ERR(imxdma->dma_clk);
+ clk_enable(imxdma->dma_clk);
/* reset DMA module */
- imx_dmav1_writel(DCR_DRST, DMA_DCR);
+ imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
if (cpu_is_mx1()) {
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
if (ret) {
pr_crit("Can't register IRQ for DMA\n");
+ kfree(imxdma);
return ret;
}
@@ -891,22 +911,19 @@ static int __init imxdma_probe(struct platform_device *pdev)
if (ret) {
pr_crit("Can't register ERRIRQ for DMA\n");
free_irq(MX1_DMA_INT, NULL);
+ kfree(imxdma);
return ret;
}
}
/* enable DMA module */
- imx_dmav1_writel(DCR_DEN, DMA_DCR);
+ imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
/* clear all interrupts */
- imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+ imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
/* disable interrupts */
- imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
- imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
- if (!imxdma)
- return -ENOMEM;
+ imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
INIT_LIST_HEAD(&imxdma->dma_device.channels);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 12/14] dmaengine: imx-dma: integrate 'imx_dmav1_baseaddr' and 'dma_clk' inside dmaengine structure.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 169 +++++++++++++++++++++++++++----------------------
1 files changed, 93 insertions(+), 76 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d65eec6..fe0f126 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -160,6 +160,8 @@ struct imxdma_engine {
struct device *dev;
struct device_dma_parameters dma_parms;
struct dma_device dma_device;
+ void __iomem *base;
+ struct clk *dma_clk;
struct imxdma_channel channel[MAX_DMA_CHANNELS];
};
@@ -181,18 +183,17 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
return false;
}
-/* TODO: put this inside any struct */
-static void __iomem *imx_dmav1_baseaddr;
-static struct clk *dma_clk;
-static void imx_dmav1_writel(unsigned val, unsigned offset)
+
+static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
+ unsigned offset)
{
- __raw_writel(val, imx_dmav1_baseaddr + offset);
+ __raw_writel(val, imxdma->base + offset);
}
-static unsigned imx_dmav1_readl(unsigned offset)
+static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
{
- return __raw_readl(imx_dmav1_baseaddr + offset);
+ return __raw_readl(imxdma->base + offset);
}
static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
@@ -209,6 +210,7 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
static inline int imxdma_sg_next(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
struct scatterlist *sg = d->sg;
unsigned long now;
@@ -217,17 +219,19 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
d->len -= now;
if (d->direction == DMA_DEV_TO_MEM)
- imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, sg->dma_address,
+ DMA_DAR(imxdmac->channel));
else
- imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, sg->dma_address,
+ DMA_SAR(imxdmac->channel));
- imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
"size 0x%08x\n", imxdmac->channel,
- imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
- imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
- imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+ imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
+ imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
+ imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
return now;
}
@@ -235,6 +239,7 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
static void imxdma_enable_hw(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
int channel = imxdmac->channel;
unsigned long flags;
@@ -242,10 +247,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
local_irq_save(flags);
- imx_dmav1_writel(1 << channel, DMA_DISR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
- CCR_ACRPT, DMA_CCR(channel));
+ imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
+ imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
+ ~(1 << channel), DMA_DIMR);
+ imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
+ CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
if ((cpu_is_mx21() || cpu_is_mx27()) &&
d->sg && imxdma_hw_chain(imxdmac)) {
@@ -253,9 +259,9 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
if (d->sg) {
u32 tmp;
imxdma_sg_next(d);
- tmp = imx_dmav1_readl(DMA_CCR(channel));
- imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
- DMA_CCR(channel));
+ tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
+ imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
+ DMA_CCR(channel));
}
}
@@ -264,6 +270,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
{
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
int channel = imxdmac->channel;
unsigned long flags;
@@ -273,19 +280,21 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
del_timer(&imxdmac->watchdog);
local_irq_save(flags);
- imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
- DMA_CCR(channel));
- imx_dmav1_writel(1 << channel, DMA_DISR);
+ imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
+ (1 << channel), DMA_DIMR);
+ imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
+ ~CCR_CEN, DMA_CCR(channel));
+ imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
local_irq_restore(flags);
}
static void imxdma_watchdog(unsigned long data)
{
struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
int channel = imxdmac->channel;
- imx_dmav1_writel(0, DMA_CCR(channel));
+ imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
/* Tasklet watchdog error handler */
tasklet_schedule(&imxdmac->dma_tasklet);
@@ -299,37 +308,37 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
int i, disr;
int errcode;
- disr = imx_dmav1_readl(DMA_DISR);
+ disr = imx_dmav1_readl(imxdma, DMA_DISR);
- err_mask = imx_dmav1_readl(DMA_DBTOSR) |
- imx_dmav1_readl(DMA_DRTOSR) |
- imx_dmav1_readl(DMA_DSESR) |
- imx_dmav1_readl(DMA_DBOSR);
+ err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
+ imx_dmav1_readl(imxdma, DMA_DRTOSR) |
+ imx_dmav1_readl(imxdma, DMA_DSESR) |
+ imx_dmav1_readl(imxdma, DMA_DBOSR);
if (!err_mask)
return IRQ_HANDLED;
- imx_dmav1_writel(disr & err_mask, DMA_DISR);
+ imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
if (!(err_mask & (1 << i)))
continue;
errcode = 0;
- if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DBTOSR);
+ if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
+ imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
errcode |= IMX_DMA_ERR_BURST;
}
- if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DRTOSR);
+ if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
+ imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
errcode |= IMX_DMA_ERR_REQUEST;
}
- if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DSESR);
+ if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
+ imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
errcode |= IMX_DMA_ERR_TRANSFER;
}
- if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DBOSR);
+ if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
+ imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
errcode |= IMX_DMA_ERR_BUFFER;
}
/* Tasklet error handler */
@@ -347,6 +356,7 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
{
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
int chno = imxdmac->channel;
struct imxdma_desc *desc;
@@ -368,7 +378,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
if (desc->sg) {
imxdma_sg_next(desc);
- tmp = imx_dmav1_readl(DMA_CCR(chno));
+ tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
if (imxdma_hw_chain(imxdmac)) {
/* FIXME: The timeout should probably be
@@ -378,13 +388,14 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
jiffies + msecs_to_jiffies(500));
tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
- imx_dmav1_writel(tmp, DMA_CCR(chno));
+ imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
} else {
- imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+ imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
+ DMA_CCR(chno));
tmp |= CCR_CEN;
}
- imx_dmav1_writel(tmp, DMA_CCR(chno));
+ imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
if (imxdma_chan_is_doing_cyclic(imxdmac))
/* Tasklet progression */
@@ -400,7 +411,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
}
out:
- imx_dmav1_writel(0, DMA_CCR(chno));
+ imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
/* Tasklet irq */
tasklet_schedule(&imxdmac->dma_tasklet);
}
@@ -413,12 +424,12 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
if (cpu_is_mx21() || cpu_is_mx27())
imxdma_err_handler(irq, dev_id);
- disr = imx_dmav1_readl(DMA_DISR);
+ disr = imx_dmav1_readl(imxdma, DMA_DISR);
pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
disr);
- imx_dmav1_writel(disr, DMA_DISR);
+ imx_dmav1_writel(imxdma, disr, DMA_DISR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
if (disr & (1 << i))
dma_irq_handle_channel(&imxdma->channel[i]);
@@ -435,12 +446,12 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
/* Configure and enable */
switch (d->type) {
case IMXDMA_DESC_MEMCPY:
- imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
- imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
- imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+ imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
DMA_CCR(imxdmac->channel));
- imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
"dma_length=%d\n", __func__, imxdmac->channel,
@@ -451,9 +462,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
case IMXDMA_DESC_CYCLIC:
case IMXDMA_DESC_SLAVE_SG:
if (d->direction == DMA_DEV_TO_MEM) {
- imx_dmav1_writel(imxdmac->per_address,
+ imx_dmav1_writel(imxdma, imxdmac->per_address,
DMA_SAR(imxdmac->channel));
- imx_dmav1_writel(imxdmac->ccr_from_device,
+ imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
DMA_CCR(imxdmac->channel));
dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -461,9 +472,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
__func__, imxdmac->channel, d->sg, d->sgcount,
d->len, imxdmac->per_address);
} else if (d->direction == DMA_MEM_TO_DEV) {
- imx_dmav1_writel(imxdmac->per_address,
+ imx_dmav1_writel(imxdma, imxdmac->per_address,
DMA_DAR(imxdmac->channel));
- imx_dmav1_writel(imxdmac->ccr_to_device,
+ imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
DMA_CCR(imxdmac->channel));
dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -528,6 +539,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
{
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
struct dma_slave_config *dmaengine_cfg = (void *)arg;
+ struct imxdma_engine *imxdma = imxdmac->imxdma;
unsigned long flags;
unsigned int mode = 0;
@@ -573,12 +585,12 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
imxdmac->ccr_to_device =
(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
- imx_dmav1_writel(imxdmac->dma_request,
+ imx_dmav1_writel(imxdma, imxdmac->dma_request,
DMA_RSSR(imxdmac->channel));
/* Set burst length */
- imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
- DMA_BLR(imxdmac->channel));
+ imx_dmav1_writel(imxdma, imxdmac->watermark_level *
+ imxdmac->word_size, DMA_BLR(imxdmac->channel));
return 0;
default:
@@ -863,27 +875,35 @@ static int __init imxdma_probe(struct platform_device *pdev)
struct imxdma_engine *imxdma;
int ret, i;
- if (cpu_is_mx1())
- imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
- else if (cpu_is_mx21())
- imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
- else if (cpu_is_mx27())
- imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
- else
+
+ imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
+ if (!imxdma)
+ return -ENOMEM;
+
+ if (cpu_is_mx1()) {
+ imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+ } else if (cpu_is_mx21()) {
+ imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+ } else if (cpu_is_mx27()) {
+ imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+ } else {
+ kfree(imxdma);
return 0;
+ }
- dma_clk = clk_get(NULL, "dma");
- if (IS_ERR(dma_clk))
- return PTR_ERR(dma_clk);
- clk_enable(dma_clk);
+ imxdma->dma_clk = clk_get(NULL, "dma");
+ if (IS_ERR(imxdma->dma_clk))
+ return PTR_ERR(imxdma->dma_clk);
+ clk_enable(imxdma->dma_clk);
/* reset DMA module */
- imx_dmav1_writel(DCR_DRST, DMA_DCR);
+ imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
if (cpu_is_mx1()) {
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
if (ret) {
pr_crit("Can't register IRQ for DMA\n");
+ kfree(imxdma);
return ret;
}
@@ -891,22 +911,19 @@ static int __init imxdma_probe(struct platform_device *pdev)
if (ret) {
pr_crit("Can't register ERRIRQ for DMA\n");
free_irq(MX1_DMA_INT, NULL);
+ kfree(imxdma);
return ret;
}
}
/* enable DMA module */
- imx_dmav1_writel(DCR_DEN, DMA_DCR);
+ imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
/* clear all interrupts */
- imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+ imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
/* disable interrupts */
- imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
- imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
- if (!imxdma)
- return -ENOMEM;
+ imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
INIT_LIST_HEAD(&imxdma->dma_device.channels);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 13/14] dmaengine: imx-dma: use dev_dbg and dev_warn for messages.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 23 ++++++++++++-----------
1 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index fe0f126..da7cecc 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -227,8 +227,8 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
- pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
- "size 0x%08x\n", imxdmac->channel,
+ dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
+ "size 0x%08x\n", __func__, imxdmac->channel,
imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
@@ -243,7 +243,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
int channel = imxdmac->channel;
unsigned long flags;
- pr_debug("imxdma%d: imx_dma_enable\n", channel);
+ dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
local_irq_save(flags);
@@ -274,7 +274,7 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
int channel = imxdmac->channel;
unsigned long flags;
- pr_debug("imxdma%d: imx_dma_disable\n", channel);
+ pr_debug("%s channel %d\n", __func__, channel);
if (imxdma_hw_chain(imxdmac))
del_timer(&imxdmac->watchdog);
@@ -298,7 +298,8 @@ static void imxdma_watchdog(unsigned long data)
/* Tasklet watchdog error handler */
tasklet_schedule(&imxdmac->dma_tasklet);
- pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+ dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
+ imxdmac->channel);
}
static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
@@ -426,8 +427,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
disr = imx_dmav1_readl(imxdma, DMA_DISR);
- pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
- disr);
+ dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
imx_dmav1_writel(imxdma, disr, DMA_DISR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
@@ -902,14 +902,14 @@ static int __init imxdma_probe(struct platform_device *pdev)
if (cpu_is_mx1()) {
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
if (ret) {
- pr_crit("Can't register IRQ for DMA\n");
+ dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
kfree(imxdma);
return ret;
}
ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
if (ret) {
- pr_crit("Can't register ERRIRQ for DMA\n");
+ dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
free_irq(MX1_DMA_INT, NULL);
kfree(imxdma);
return ret;
@@ -939,8 +939,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
ret = request_irq(MX2x_INT_DMACH0 + i,
dma_irq_handler, 0, "DMA", imxdma);
if (ret) {
- pr_crit("Can't register IRQ %d for DMA channel %d\n",
- MX2x_INT_DMACH0 + i, i);
+ dev_warn(imxdma->dev, "Can't register IRQ %d "
+ "for DMA channel %d\n",
+ MX2x_INT_DMACH0 + i, i);
goto err_init;
}
init_timer(&imxdmac->watchdog);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 13/14] dmaengine: imx-dma: use dev_dbg and dev_warn for messages.
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
drivers/dma/imx-dma.c | 23 ++++++++++++-----------
1 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index fe0f126..da7cecc 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -227,8 +227,8 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
- pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
- "size 0x%08x\n", imxdmac->channel,
+ dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
+ "size 0x%08x\n", __func__, imxdmac->channel,
imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
@@ -243,7 +243,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
int channel = imxdmac->channel;
unsigned long flags;
- pr_debug("imxdma%d: imx_dma_enable\n", channel);
+ dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
local_irq_save(flags);
@@ -274,7 +274,7 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
int channel = imxdmac->channel;
unsigned long flags;
- pr_debug("imxdma%d: imx_dma_disable\n", channel);
+ pr_debug("%s channel %d\n", __func__, channel);
if (imxdma_hw_chain(imxdmac))
del_timer(&imxdmac->watchdog);
@@ -298,7 +298,8 @@ static void imxdma_watchdog(unsigned long data)
/* Tasklet watchdog error handler */
tasklet_schedule(&imxdmac->dma_tasklet);
- pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+ dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
+ imxdmac->channel);
}
static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
@@ -426,8 +427,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
disr = imx_dmav1_readl(imxdma, DMA_DISR);
- pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
- disr);
+ dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
imx_dmav1_writel(imxdma, disr, DMA_DISR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
@@ -902,14 +902,14 @@ static int __init imxdma_probe(struct platform_device *pdev)
if (cpu_is_mx1()) {
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
if (ret) {
- pr_crit("Can't register IRQ for DMA\n");
+ dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
kfree(imxdma);
return ret;
}
ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
if (ret) {
- pr_crit("Can't register ERRIRQ for DMA\n");
+ dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
free_irq(MX1_DMA_INT, NULL);
kfree(imxdma);
return ret;
@@ -939,8 +939,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
ret = request_irq(MX2x_INT_DMACH0 + i,
dma_irq_handler, 0, "DMA", imxdma);
if (ret) {
- pr_crit("Can't register IRQ %d for DMA channel %d\n",
- MX2x_INT_DMACH0 + i, i);
+ dev_warn(imxdma->dev, "Can't register IRQ %d "
+ "for DMA channel %d\n",
+ MX2x_INT_DMACH0 + i, i);
goto err_init;
}
init_timer(&imxdmac->watchdog);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 14/14] dmaengine: imx-dma: remove dma-v1.c and dma-v1.h
2012-03-05 16:16 ` Javier Martin
@ 2012-03-05 16:16 ` Javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, dan.j.williams, vinod.koul, linux, kernel, Javier Martin
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
arch/arm/mach-imx/dma-v1.c | 846 -------------------------------
arch/arm/mach-imx/include/mach/dma-v1.h | 103 ----
2 files changed, 0 insertions(+), 949 deletions(-)
delete mode 100644 arch/arm/mach-imx/dma-v1.c
delete mode 100644 arch/arm/mach-imx/include/mach/dma-v1.h
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
deleted file mode 100644
index 42afc29..0000000
--- a/arch/arm/mach-imx/dma-v1.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/*
- * linux/arch/arm/plat-mxc/dma-v1.c
- *
- * i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/scatterlist.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/dma-v1.h>
-
-#define DMA_DCR 0x00 /* Control Register */
-#define DMA_DISR 0x04 /* Interrupt status Register */
-#define DMA_DIMR 0x08 /* Interrupt mask Register */
-#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
-#define DMA_DRTOSR 0x10 /* Request timeout Register */
-#define DMA_DSESR 0x14 /* Transfer Error Status Register */
-#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
-#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
-#define DMA_WSRA 0x40 /* W-Size Register A */
-#define DMA_XSRA 0x44 /* X-Size Register A */
-#define DMA_YSRA 0x48 /* Y-Size Register A */
-#define DMA_WSRB 0x4c /* W-Size Register B */
-#define DMA_XSRB 0x50 /* X-Size Register B */
-#define DMA_YSRB 0x54 /* Y-Size Register B */
-#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
-#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
-#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
-#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
-#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
-#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
-#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
-#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
-#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
-
-#define DCR_DRST (1<<1)
-#define DCR_DEN (1<<0)
-#define DBTOCR_EN (1<<15)
-#define DBTOCR_CNT(x) ((x) & 0x7fff)
-#define CNTR_CNT(x) ((x) & 0xffffff)
-#define CCR_ACRPT (1<<14)
-#define CCR_DMOD_LINEAR (0x0 << 12)
-#define CCR_DMOD_2D (0x1 << 12)
-#define CCR_DMOD_FIFO (0x2 << 12)
-#define CCR_DMOD_EOBFIFO (0x3 << 12)
-#define CCR_SMOD_LINEAR (0x0 << 10)
-#define CCR_SMOD_2D (0x1 << 10)
-#define CCR_SMOD_FIFO (0x2 << 10)
-#define CCR_SMOD_EOBFIFO (0x3 << 10)
-#define CCR_MDIR_DEC (1<<9)
-#define CCR_MSEL_B (1<<8)
-#define CCR_DSIZ_32 (0x0 << 6)
-#define CCR_DSIZ_8 (0x1 << 6)
-#define CCR_DSIZ_16 (0x2 << 6)
-#define CCR_SSIZ_32 (0x0 << 4)
-#define CCR_SSIZ_8 (0x1 << 4)
-#define CCR_SSIZ_16 (0x2 << 4)
-#define CCR_REN (1<<3)
-#define CCR_RPT (1<<2)
-#define CCR_FRC (1<<1)
-#define CCR_CEN (1<<0)
-#define RTOR_EN (1<<15)
-#define RTOR_CLK (1<<14)
-#define RTOR_PSC (1<<13)
-
-/*
- * struct imx_dma_channel - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- * (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imx_dma_channel only as extension to it.
- */
-
-struct imx_dma_channel {
- const char *name;
- void (*irq_handler) (int, void *);
- void (*err_handler) (int, void *, int errcode);
- void (*prog_handler) (int, void *, struct scatterlist *);
- void *data;
- unsigned int dma_mode;
- struct scatterlist *sg;
- unsigned int resbytes;
- int dma_num;
-
- int in_use;
-
- u32 ccr_from_device;
- u32 ccr_to_device;
-
- struct timer_list watchdog;
-
- int hw_chaining;
-};
-
-static void __iomem *imx_dmav1_baseaddr;
-
-static void imx_dmav1_writel(unsigned val, unsigned offset)
-{
- __raw_writel(val, imx_dmav1_baseaddr + offset);
-}
-
-static unsigned imx_dmav1_readl(unsigned offset)
-{
- return __raw_readl(imx_dmav1_baseaddr + offset);
-}
-
-static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
-
-static struct clk *dma_clk;
-
-static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
-{
- if (cpu_is_mx27())
- return imxdma->hw_chaining;
- else
- return 0;
-}
-
-/*
- * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
- */
-static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long now;
-
- if (!imxdma->name) {
- printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __func__, channel);
- return 0;
- }
-
- now = min(imxdma->resbytes, sg->length);
- if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
- imxdma->resbytes -= now;
-
- if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
- imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
- else
- imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
-
- imx_dmav1_writel(now, DMA_CNTR(channel));
-
- pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
- "size 0x%08x\n", channel,
- imx_dmav1_readl(DMA_DAR(channel)),
- imx_dmav1_readl(DMA_SAR(channel)),
- imx_dmav1_readl(DMA_CNTR(channel)));
-
- return now;
-}
-
-/**
- * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
- * device transfer
- *
- * @channel: i.MX DMA channel number
- * @dma_address: the DMA/physical memory address of the linear data block
- * to transfer
- * @dma_length: length of the data block in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- * or %DMA_MODE_WRITE from memory to the device
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- * Zero indicates success.
- */
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
- unsigned int dma_length, unsigned int dev_addr,
- unsigned int dmamode)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
- imxdma->sg = NULL;
- imxdma->dma_mode = dmamode;
-
- if (!dma_address) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
- channel);
- return -EINVAL;
- }
-
- if (!dma_length) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
- channel);
- return -EINVAL;
- }
-
- if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
- pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
- "dev_addr=0x%08x for read\n",
- channel, __func__, (unsigned int)dma_address,
- dma_length, dev_addr);
-
- imx_dmav1_writel(dev_addr, DMA_SAR(channel));
- imx_dmav1_writel(dma_address, DMA_DAR(channel));
- imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
- } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
- pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
- "dev_addr=0x%08x for write\n",
- channel, __func__, (unsigned int)dma_address,
- dma_length, dev_addr);
-
- imx_dmav1_writel(dma_address, DMA_SAR(channel));
- imx_dmav1_writel(dev_addr, DMA_DAR(channel));
- imx_dmav1_writel(imxdma->ccr_to_device,
- DMA_CCR(channel));
- } else {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
- channel);
- return -EINVAL;
- }
-
- imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
- return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_single);
-
-/**
- * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
- * @channel: i.MX DMA channel number
- * @sg: pointer to the scatter-gather list/vector
- * @sgcount: scatter-gather list hungs count
- * @dma_length: total length of the transfer request in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- * or %DMA_MODE_WRITE from memory to the device
- *
- * The function sets up DMA channel state and registers to be ready for
- * transfer specified by provided parameters. The scatter-gather emulation
- * is set up according to the parameters.
- *
- * The full preparation of the transfer requires setup of more register
- * by the caller before imx_dma_enable() can be called.
- *
- * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
- *
- * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
- *
- * %CCR(channel) has to specify transfer parameters, the next settings is
- * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
- * specified
- *
- * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
- *
- * The typical setup for %DMA_MODE_WRITE is specified by next options
- * combination
- *
- * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
- *
- * Be careful here and do not mistakenly mix source and target device
- * port sizes constants, they are really different:
- * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
- * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- * Zero indicates success.
- */
-int
-imx_dma_setup_sg(int channel,
- struct scatterlist *sg, unsigned int sgcount,
- unsigned int dma_length, unsigned int dev_addr,
- unsigned int dmamode)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
- if (imxdma->in_use)
- return -EBUSY;
-
- imxdma->sg = sg;
- imxdma->dma_mode = dmamode;
- imxdma->resbytes = dma_length;
-
- if (!sg || !sgcount) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
- channel);
- return -EINVAL;
- }
-
- if (!sg->length) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
- channel);
- return -EINVAL;
- }
-
- if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
- pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
- "dev_addr=0x%08x for read\n",
- channel, __func__, sg, sgcount, dma_length, dev_addr);
-
- imx_dmav1_writel(dev_addr, DMA_SAR(channel));
- imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
- } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
- pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
- "dev_addr=0x%08x for write\n",
- channel, __func__, sg, sgcount, dma_length, dev_addr);
-
- imx_dmav1_writel(dev_addr, DMA_DAR(channel));
- imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
- } else {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
- channel);
- return -EINVAL;
- }
-
- imx_dma_sg_next(channel, sg);
-
- return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_sg);
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
- unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- u32 dreq = 0;
-
- imxdma->hw_chaining = 0;
-
- if (hw_chaining) {
- imxdma->hw_chaining = 1;
- if (!imx_dma_hw_chain(imxdma))
- return -EINVAL;
- }
-
- if (dmareq)
- dreq = CCR_REN;
-
- imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
- imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
-
- imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
- return 0;
-}
-EXPORT_SYMBOL(imx_dma_config_channel);
-
-void imx_dma_config_burstlen(int channel, unsigned int burstlen)
-{
- imx_dmav1_writel(burstlen, DMA_BLR(channel));
-}
-EXPORT_SYMBOL(imx_dma_config_burstlen);
-
-/**
- * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
- * handlers
- * @channel: i.MX DMA channel number
- * @irq_handler: the pointer to the function called if the transfer
- * ends successfully
- * @err_handler: the pointer to the function called if the premature
- * end caused by error occurs
- * @data: user specified value to be passed to the handlers
- */
-int
-imx_dma_setup_handlers(int channel,
- void (*irq_handler) (int, void *),
- void (*err_handler) (int, void *, int),
- void *data)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long flags;
-
- if (!imxdma->name) {
- printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __func__, channel);
- return -ENODEV;
- }
-
- local_irq_save(flags);
- imx_dmav1_writel(1 << channel, DMA_DISR);
- imxdma->irq_handler = irq_handler;
- imxdma->err_handler = err_handler;
- imxdma->data = data;
- local_irq_restore(flags);
- return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_handlers);
-
-/**
- * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
- * handlers
- * @channel: i.MX DMA channel number
- * @prog_handler: the pointer to the function called if the transfer progresses
- */
-int
-imx_dma_setup_progression_handler(int channel,
- void (*prog_handler) (int, void*, struct scatterlist*))
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long flags;
-
- if (!imxdma->name) {
- printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __func__, channel);
- return -ENODEV;
- }
-
- local_irq_save(flags);
- imxdma->prog_handler = prog_handler;
- local_irq_restore(flags);
- return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_progression_handler);
-
-/**
- * imx_dma_enable - function to start i.MX DMA channel operation
- * @channel: i.MX DMA channel number
- *
- * The channel has to be allocated by driver through imx_dma_request()
- * or imx_dma_request_by_prio() function.
- * The transfer parameters has to be set to the channel registers through
- * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
- * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
- * be set prior this function call by the channel user.
- */
-void imx_dma_enable(int channel)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long flags;
-
- pr_debug("imxdma%d: imx_dma_enable\n", channel);
-
- if (!imxdma->name) {
- printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __func__, channel);
- return;
- }
-
- if (imxdma->in_use)
- return;
-
- local_irq_save(flags);
-
- imx_dmav1_writel(1 << channel, DMA_DISR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
- CCR_ACRPT, DMA_CCR(channel));
-
- if ((cpu_is_mx21() || cpu_is_mx27()) &&
- imxdma->sg && imx_dma_hw_chain(imxdma)) {
- imxdma->sg = sg_next(imxdma->sg);
- if (imxdma->sg) {
- u32 tmp;
- imx_dma_sg_next(channel, imxdma->sg);
- tmp = imx_dmav1_readl(DMA_CCR(channel));
- imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
- DMA_CCR(channel));
- }
- }
- imxdma->in_use = 1;
-
- local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_enable);
-
-/**
- * imx_dma_disable - stop, finish i.MX DMA channel operatin
- * @channel: i.MX DMA channel number
- */
-void imx_dma_disable(int channel)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long flags;
-
- pr_debug("imxdma%d: imx_dma_disable\n", channel);
-
- if (imx_dma_hw_chain(imxdma))
- del_timer(&imxdma->watchdog);
-
- local_irq_save(flags);
- imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
- DMA_CCR(channel));
- imx_dmav1_writel(1 << channel, DMA_DISR);
- imxdma->in_use = 0;
- local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_disable);
-
-static void imx_dma_watchdog(unsigned long chno)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
- imx_dmav1_writel(0, DMA_CCR(chno));
- imxdma->in_use = 0;
- imxdma->sg = NULL;
-
- if (imxdma->err_handler)
- imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
-}
-
-static irqreturn_t dma_err_handler(int irq, void *dev_id)
-{
- int i, disr;
- struct imx_dma_channel *imxdma;
- unsigned int err_mask;
- int errcode;
-
- disr = imx_dmav1_readl(DMA_DISR);
-
- err_mask = imx_dmav1_readl(DMA_DBTOSR) |
- imx_dmav1_readl(DMA_DRTOSR) |
- imx_dmav1_readl(DMA_DSESR) |
- imx_dmav1_readl(DMA_DBOSR);
-
- if (!err_mask)
- return IRQ_HANDLED;
-
- imx_dmav1_writel(disr & err_mask, DMA_DISR);
-
- for (i = 0; i < IMX_DMA_CHANNELS; i++) {
- if (!(err_mask & (1 << i)))
- continue;
- imxdma = &imx_dma_channels[i];
- errcode = 0;
-
- if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DBTOSR);
- errcode |= IMX_DMA_ERR_BURST;
- }
- if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DRTOSR);
- errcode |= IMX_DMA_ERR_REQUEST;
- }
- if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DSESR);
- errcode |= IMX_DMA_ERR_TRANSFER;
- }
- if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DBOSR);
- errcode |= IMX_DMA_ERR_BUFFER;
- }
- if (imxdma->name && imxdma->err_handler) {
- imxdma->err_handler(i, imxdma->data, errcode);
- continue;
- }
-
- imx_dma_channels[i].sg = NULL;
-
- printk(KERN_WARNING
- "DMA timeout on channel %d (%s) -%s%s%s%s\n",
- i, imxdma->name,
- errcode & IMX_DMA_ERR_BURST ? " burst" : "",
- errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
- errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
- errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
- }
- return IRQ_HANDLED;
-}
-
-static void dma_irq_handle_channel(int chno)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
- if (!imxdma->name) {
- /*
- * IRQ for an unregistered DMA channel:
- * let's clear the interrupts and disable it.
- */
- printk(KERN_WARNING
- "spurious IRQ for DMA channel %d\n", chno);
- return;
- }
-
- if (imxdma->sg) {
- u32 tmp;
- struct scatterlist *current_sg = imxdma->sg;
- imxdma->sg = sg_next(imxdma->sg);
-
- if (imxdma->sg) {
- imx_dma_sg_next(chno, imxdma->sg);
-
- tmp = imx_dmav1_readl(DMA_CCR(chno));
-
- if (imx_dma_hw_chain(imxdma)) {
- /* FIXME: The timeout should probably be
- * configurable
- */
- mod_timer(&imxdma->watchdog,
- jiffies + msecs_to_jiffies(500));
-
- tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
- imx_dmav1_writel(tmp, DMA_CCR(chno));
- } else {
- imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
- tmp |= CCR_CEN;
- }
-
- imx_dmav1_writel(tmp, DMA_CCR(chno));
-
- if (imxdma->prog_handler)
- imxdma->prog_handler(chno, imxdma->data,
- current_sg);
-
- return;
- }
-
- if (imx_dma_hw_chain(imxdma)) {
- del_timer(&imxdma->watchdog);
- return;
- }
- }
-
- imx_dmav1_writel(0, DMA_CCR(chno));
- imxdma->in_use = 0;
- if (imxdma->irq_handler)
- imxdma->irq_handler(chno, imxdma->data);
-}
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
- int i, disr;
-
- if (cpu_is_mx21() || cpu_is_mx27())
- dma_err_handler(irq, dev_id);
-
- disr = imx_dmav1_readl(DMA_DISR);
-
- pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
- disr);
-
- imx_dmav1_writel(disr, DMA_DISR);
- for (i = 0; i < IMX_DMA_CHANNELS; i++) {
- if (disr & (1 << i))
- dma_irq_handle_channel(i);
- }
-
- return IRQ_HANDLED;
-}
-
-/**
- * imx_dma_request - request/allocate specified channel number
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- */
-int imx_dma_request(int channel, const char *name)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long flags;
- int ret = 0;
-
- /* basic sanity checks */
- if (!name)
- return -EINVAL;
-
- if (channel >= IMX_DMA_CHANNELS) {
- printk(KERN_CRIT "%s: called for non-existed channel %d\n",
- __func__, channel);
- return -EINVAL;
- }
-
- local_irq_save(flags);
- if (imxdma->name) {
- local_irq_restore(flags);
- return -EBUSY;
- }
- memset(imxdma, 0, sizeof(*imxdma));
- imxdma->name = name;
- local_irq_restore(flags); /* request_irq() can block */
-
- if (cpu_is_mx21() || cpu_is_mx27()) {
- ret = request_irq(MX2x_INT_DMACH0 + channel,
- dma_irq_handler, 0, "DMA", NULL);
- if (ret) {
- imxdma->name = NULL;
- pr_crit("Can't register IRQ %d for DMA channel %d\n",
- MX2x_INT_DMACH0 + channel, channel);
- return ret;
- }
- init_timer(&imxdma->watchdog);
- imxdma->watchdog.function = &imx_dma_watchdog;
- imxdma->watchdog.data = channel;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(imx_dma_request);
-
-/**
- * imx_dma_free - release previously acquired channel
- * @channel: i.MX DMA channel number
- */
-void imx_dma_free(int channel)
-{
- unsigned long flags;
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
- if (!imxdma->name) {
- printk(KERN_CRIT
- "%s: trying to free free channel %d\n",
- __func__, channel);
- return;
- }
-
- local_irq_save(flags);
- /* Disable interrupts */
- imx_dma_disable(channel);
- imxdma->name = NULL;
-
- if (cpu_is_mx21() || cpu_is_mx27())
- free_irq(MX2x_INT_DMACH0 + channel, NULL);
-
- local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_free);
-
-/**
- * imx_dma_request_by_prio - find and request some of free channels best
- * suiting requested priority
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- *
- * This function tries to find a free channel in the specified priority group
- * if the priority cannot be achieved it tries to look for free channel
- * in the higher and then even lower priority groups.
- *
- * Return value: If there is no free channel to allocate, -%ENODEV is returned.
- * On successful allocation channel is returned.
- */
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
-{
- int i;
- int best;
-
- switch (prio) {
- case (DMA_PRIO_HIGH):
- best = 8;
- break;
- case (DMA_PRIO_MEDIUM):
- best = 4;
- break;
- case (DMA_PRIO_LOW):
- default:
- best = 0;
- break;
- }
-
- for (i = best; i < IMX_DMA_CHANNELS; i++)
- if (!imx_dma_request(i, name))
- return i;
-
- for (i = best - 1; i >= 0; i--)
- if (!imx_dma_request(i, name))
- return i;
-
- printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
-
- return -ENODEV;
-}
-EXPORT_SYMBOL(imx_dma_request_by_prio);
-
-static int __init imx_dma_init(void)
-{
- int ret = 0;
- int i;
-
- if (cpu_is_mx1())
- imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
- else if (cpu_is_mx21())
- imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
- else if (cpu_is_mx27())
- imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
- else
- return 0;
-
- dma_clk = clk_get(NULL, "dma");
- if (IS_ERR(dma_clk))
- return PTR_ERR(dma_clk);
- clk_enable(dma_clk);
-
- /* reset DMA module */
- imx_dmav1_writel(DCR_DRST, DMA_DCR);
-
- if (cpu_is_mx1()) {
- ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
- if (ret) {
- pr_crit("Wow! Can't register IRQ for DMA\n");
- return ret;
- }
-
- ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
- if (ret) {
- pr_crit("Wow! Can't register ERRIRQ for DMA\n");
- free_irq(MX1_DMA_INT, NULL);
- return ret;
- }
- }
-
- /* enable DMA module */
- imx_dmav1_writel(DCR_DEN, DMA_DCR);
-
- /* clear all interrupts */
- imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
-
- /* disable interrupts */
- imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
- for (i = 0; i < IMX_DMA_CHANNELS; i++) {
- imx_dma_channels[i].sg = NULL;
- imx_dma_channels[i].dma_num = i;
- }
-
- return ret;
-}
-
-arch_initcall(imx_dma_init);
diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h
deleted file mode 100644
index ac6fd71..0000000
--- a/arch/arm/mach-imx/include/mach/dma-v1.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * linux/arch/arm/mach-imx/include/mach/dma-v1.h
- *
- * i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_DMA_V1_H__
-#define __MACH_DMA_V1_H__
-
-#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
-
-#include <mach/dma.h>
-
-#define IMX_DMA_CHANNELS 16
-
-#define DMA_MODE_READ 0
-#define DMA_MODE_WRITE 1
-#define DMA_MODE_MASK 1
-
-#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
-
-/* DMA Interrupt Mask Register */
-#define MX1_DMA_DIMR MX1_DMA_REG(0x08)
-
-/* Channel Control Register */
-#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6))
-
-#define IMX_DMA_MEMSIZE_32 (0 << 4)
-#define IMX_DMA_MEMSIZE_8 (1 << 4)
-#define IMX_DMA_MEMSIZE_16 (2 << 4)
-#define IMX_DMA_TYPE_LINEAR (0 << 10)
-#define IMX_DMA_TYPE_2D (1 << 10)
-#define IMX_DMA_TYPE_FIFO (2 << 10)
-
-#define IMX_DMA_ERR_BURST (1 << 0)
-#define IMX_DMA_ERR_REQUEST (1 << 1)
-#define IMX_DMA_ERR_TRANSFER (1 << 2)
-#define IMX_DMA_ERR_BUFFER (1 << 3)
-#define IMX_DMA_ERR_TIMEOUT (1 << 4)
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
- unsigned int config_mem, unsigned int dmareq, int hw_chaining);
-
-void
-imx_dma_config_burstlen(int channel, unsigned int burstlen);
-
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
- unsigned int dma_length, unsigned int dev_addr,
- unsigned int dmamode);
-
-
-/*
- * Use this flag as the dma_length argument to imx_dma_setup_sg()
- * to create an endless running dma loop. The end of the scatterlist
- * must be linked to the beginning for this to work.
- */
-#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
-
-int
-imx_dma_setup_sg(int channel, struct scatterlist *sg,
- unsigned int sgcount, unsigned int dma_length,
- unsigned int dev_addr, unsigned int dmamode);
-
-int
-imx_dma_setup_handlers(int channel,
- void (*irq_handler) (int, void *),
- void (*err_handler) (int, void *, int), void *data);
-
-int
-imx_dma_setup_progression_handler(int channel,
- void (*prog_handler) (int, void*, struct scatterlist*));
-
-void imx_dma_enable(int channel);
-
-void imx_dma_disable(int channel);
-
-int imx_dma_request(int channel, const char *name);
-
-void imx_dma_free(int channel);
-
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
-
-#endif /* __MACH_DMA_V1_H__ */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 14/14] dmaengine: imx-dma: remove dma-v1.c and dma-v1.h
@ 2012-03-05 16:16 ` Javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: Javier Martin @ 2012-03-05 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
---
arch/arm/mach-imx/dma-v1.c | 846 -------------------------------
arch/arm/mach-imx/include/mach/dma-v1.h | 103 ----
2 files changed, 0 insertions(+), 949 deletions(-)
delete mode 100644 arch/arm/mach-imx/dma-v1.c
delete mode 100644 arch/arm/mach-imx/include/mach/dma-v1.h
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
deleted file mode 100644
index 42afc29..0000000
--- a/arch/arm/mach-imx/dma-v1.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/*
- * linux/arch/arm/plat-mxc/dma-v1.c
- *
- * i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/scatterlist.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/dma-v1.h>
-
-#define DMA_DCR 0x00 /* Control Register */
-#define DMA_DISR 0x04 /* Interrupt status Register */
-#define DMA_DIMR 0x08 /* Interrupt mask Register */
-#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
-#define DMA_DRTOSR 0x10 /* Request timeout Register */
-#define DMA_DSESR 0x14 /* Transfer Error Status Register */
-#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
-#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
-#define DMA_WSRA 0x40 /* W-Size Register A */
-#define DMA_XSRA 0x44 /* X-Size Register A */
-#define DMA_YSRA 0x48 /* Y-Size Register A */
-#define DMA_WSRB 0x4c /* W-Size Register B */
-#define DMA_XSRB 0x50 /* X-Size Register B */
-#define DMA_YSRB 0x54 /* Y-Size Register B */
-#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
-#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
-#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
-#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
-#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
-#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
-#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
-#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
-#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
-
-#define DCR_DRST (1<<1)
-#define DCR_DEN (1<<0)
-#define DBTOCR_EN (1<<15)
-#define DBTOCR_CNT(x) ((x) & 0x7fff)
-#define CNTR_CNT(x) ((x) & 0xffffff)
-#define CCR_ACRPT (1<<14)
-#define CCR_DMOD_LINEAR (0x0 << 12)
-#define CCR_DMOD_2D (0x1 << 12)
-#define CCR_DMOD_FIFO (0x2 << 12)
-#define CCR_DMOD_EOBFIFO (0x3 << 12)
-#define CCR_SMOD_LINEAR (0x0 << 10)
-#define CCR_SMOD_2D (0x1 << 10)
-#define CCR_SMOD_FIFO (0x2 << 10)
-#define CCR_SMOD_EOBFIFO (0x3 << 10)
-#define CCR_MDIR_DEC (1<<9)
-#define CCR_MSEL_B (1<<8)
-#define CCR_DSIZ_32 (0x0 << 6)
-#define CCR_DSIZ_8 (0x1 << 6)
-#define CCR_DSIZ_16 (0x2 << 6)
-#define CCR_SSIZ_32 (0x0 << 4)
-#define CCR_SSIZ_8 (0x1 << 4)
-#define CCR_SSIZ_16 (0x2 << 4)
-#define CCR_REN (1<<3)
-#define CCR_RPT (1<<2)
-#define CCR_FRC (1<<1)
-#define CCR_CEN (1<<0)
-#define RTOR_EN (1<<15)
-#define RTOR_CLK (1<<14)
-#define RTOR_PSC (1<<13)
-
-/*
- * struct imx_dma_channel - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- * (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imx_dma_channel only as extension to it.
- */
-
-struct imx_dma_channel {
- const char *name;
- void (*irq_handler) (int, void *);
- void (*err_handler) (int, void *, int errcode);
- void (*prog_handler) (int, void *, struct scatterlist *);
- void *data;
- unsigned int dma_mode;
- struct scatterlist *sg;
- unsigned int resbytes;
- int dma_num;
-
- int in_use;
-
- u32 ccr_from_device;
- u32 ccr_to_device;
-
- struct timer_list watchdog;
-
- int hw_chaining;
-};
-
-static void __iomem *imx_dmav1_baseaddr;
-
-static void imx_dmav1_writel(unsigned val, unsigned offset)
-{
- __raw_writel(val, imx_dmav1_baseaddr + offset);
-}
-
-static unsigned imx_dmav1_readl(unsigned offset)
-{
- return __raw_readl(imx_dmav1_baseaddr + offset);
-}
-
-static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
-
-static struct clk *dma_clk;
-
-static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
-{
- if (cpu_is_mx27())
- return imxdma->hw_chaining;
- else
- return 0;
-}
-
-/*
- * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
- */
-static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long now;
-
- if (!imxdma->name) {
- printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __func__, channel);
- return 0;
- }
-
- now = min(imxdma->resbytes, sg->length);
- if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
- imxdma->resbytes -= now;
-
- if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
- imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
- else
- imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
-
- imx_dmav1_writel(now, DMA_CNTR(channel));
-
- pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
- "size 0x%08x\n", channel,
- imx_dmav1_readl(DMA_DAR(channel)),
- imx_dmav1_readl(DMA_SAR(channel)),
- imx_dmav1_readl(DMA_CNTR(channel)));
-
- return now;
-}
-
-/**
- * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
- * device transfer
- *
- * @channel: i.MX DMA channel number
- * @dma_address: the DMA/physical memory address of the linear data block
- * to transfer
- * @dma_length: length of the data block in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- * or %DMA_MODE_WRITE from memory to the device
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- * Zero indicates success.
- */
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
- unsigned int dma_length, unsigned int dev_addr,
- unsigned int dmamode)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
- imxdma->sg = NULL;
- imxdma->dma_mode = dmamode;
-
- if (!dma_address) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
- channel);
- return -EINVAL;
- }
-
- if (!dma_length) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
- channel);
- return -EINVAL;
- }
-
- if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
- pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
- "dev_addr=0x%08x for read\n",
- channel, __func__, (unsigned int)dma_address,
- dma_length, dev_addr);
-
- imx_dmav1_writel(dev_addr, DMA_SAR(channel));
- imx_dmav1_writel(dma_address, DMA_DAR(channel));
- imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
- } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
- pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
- "dev_addr=0x%08x for write\n",
- channel, __func__, (unsigned int)dma_address,
- dma_length, dev_addr);
-
- imx_dmav1_writel(dma_address, DMA_SAR(channel));
- imx_dmav1_writel(dev_addr, DMA_DAR(channel));
- imx_dmav1_writel(imxdma->ccr_to_device,
- DMA_CCR(channel));
- } else {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
- channel);
- return -EINVAL;
- }
-
- imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
- return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_single);
-
-/**
- * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
- * @channel: i.MX DMA channel number
- * @sg: pointer to the scatter-gather list/vector
- * @sgcount: scatter-gather list hungs count
- * @dma_length: total length of the transfer request in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- * or %DMA_MODE_WRITE from memory to the device
- *
- * The function sets up DMA channel state and registers to be ready for
- * transfer specified by provided parameters. The scatter-gather emulation
- * is set up according to the parameters.
- *
- * The full preparation of the transfer requires setup of more register
- * by the caller before imx_dma_enable() can be called.
- *
- * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
- *
- * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
- *
- * %CCR(channel) has to specify transfer parameters, the next settings is
- * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
- * specified
- *
- * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
- *
- * The typical setup for %DMA_MODE_WRITE is specified by next options
- * combination
- *
- * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
- *
- * Be careful here and do not mistakenly mix source and target device
- * port sizes constants, they are really different:
- * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
- * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- * Zero indicates success.
- */
-int
-imx_dma_setup_sg(int channel,
- struct scatterlist *sg, unsigned int sgcount,
- unsigned int dma_length, unsigned int dev_addr,
- unsigned int dmamode)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
- if (imxdma->in_use)
- return -EBUSY;
-
- imxdma->sg = sg;
- imxdma->dma_mode = dmamode;
- imxdma->resbytes = dma_length;
-
- if (!sg || !sgcount) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
- channel);
- return -EINVAL;
- }
-
- if (!sg->length) {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
- channel);
- return -EINVAL;
- }
-
- if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
- pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
- "dev_addr=0x%08x for read\n",
- channel, __func__, sg, sgcount, dma_length, dev_addr);
-
- imx_dmav1_writel(dev_addr, DMA_SAR(channel));
- imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
- } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
- pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
- "dev_addr=0x%08x for write\n",
- channel, __func__, sg, sgcount, dma_length, dev_addr);
-
- imx_dmav1_writel(dev_addr, DMA_DAR(channel));
- imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
- } else {
- printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
- channel);
- return -EINVAL;
- }
-
- imx_dma_sg_next(channel, sg);
-
- return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_sg);
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
- unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- u32 dreq = 0;
-
- imxdma->hw_chaining = 0;
-
- if (hw_chaining) {
- imxdma->hw_chaining = 1;
- if (!imx_dma_hw_chain(imxdma))
- return -EINVAL;
- }
-
- if (dmareq)
- dreq = CCR_REN;
-
- imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
- imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
-
- imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
- return 0;
-}
-EXPORT_SYMBOL(imx_dma_config_channel);
-
-void imx_dma_config_burstlen(int channel, unsigned int burstlen)
-{
- imx_dmav1_writel(burstlen, DMA_BLR(channel));
-}
-EXPORT_SYMBOL(imx_dma_config_burstlen);
-
-/**
- * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
- * handlers
- * @channel: i.MX DMA channel number
- * @irq_handler: the pointer to the function called if the transfer
- * ends successfully
- * @err_handler: the pointer to the function called if the premature
- * end caused by error occurs
- * @data: user specified value to be passed to the handlers
- */
-int
-imx_dma_setup_handlers(int channel,
- void (*irq_handler) (int, void *),
- void (*err_handler) (int, void *, int),
- void *data)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long flags;
-
- if (!imxdma->name) {
- printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __func__, channel);
- return -ENODEV;
- }
-
- local_irq_save(flags);
- imx_dmav1_writel(1 << channel, DMA_DISR);
- imxdma->irq_handler = irq_handler;
- imxdma->err_handler = err_handler;
- imxdma->data = data;
- local_irq_restore(flags);
- return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_handlers);
-
-/**
- * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
- * handlers
- * @channel: i.MX DMA channel number
- * @prog_handler: the pointer to the function called if the transfer progresses
- */
-int
-imx_dma_setup_progression_handler(int channel,
- void (*prog_handler) (int, void*, struct scatterlist*))
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long flags;
-
- if (!imxdma->name) {
- printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __func__, channel);
- return -ENODEV;
- }
-
- local_irq_save(flags);
- imxdma->prog_handler = prog_handler;
- local_irq_restore(flags);
- return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_progression_handler);
-
-/**
- * imx_dma_enable - function to start i.MX DMA channel operation
- * @channel: i.MX DMA channel number
- *
- * The channel has to be allocated by driver through imx_dma_request()
- * or imx_dma_request_by_prio() function.
- * The transfer parameters has to be set to the channel registers through
- * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
- * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
- * be set prior this function call by the channel user.
- */
-void imx_dma_enable(int channel)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long flags;
-
- pr_debug("imxdma%d: imx_dma_enable\n", channel);
-
- if (!imxdma->name) {
- printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __func__, channel);
- return;
- }
-
- if (imxdma->in_use)
- return;
-
- local_irq_save(flags);
-
- imx_dmav1_writel(1 << channel, DMA_DISR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
- CCR_ACRPT, DMA_CCR(channel));
-
- if ((cpu_is_mx21() || cpu_is_mx27()) &&
- imxdma->sg && imx_dma_hw_chain(imxdma)) {
- imxdma->sg = sg_next(imxdma->sg);
- if (imxdma->sg) {
- u32 tmp;
- imx_dma_sg_next(channel, imxdma->sg);
- tmp = imx_dmav1_readl(DMA_CCR(channel));
- imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
- DMA_CCR(channel));
- }
- }
- imxdma->in_use = 1;
-
- local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_enable);
-
-/**
- * imx_dma_disable - stop, finish i.MX DMA channel operatin
- * @channel: i.MX DMA channel number
- */
-void imx_dma_disable(int channel)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long flags;
-
- pr_debug("imxdma%d: imx_dma_disable\n", channel);
-
- if (imx_dma_hw_chain(imxdma))
- del_timer(&imxdma->watchdog);
-
- local_irq_save(flags);
- imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
- imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
- DMA_CCR(channel));
- imx_dmav1_writel(1 << channel, DMA_DISR);
- imxdma->in_use = 0;
- local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_disable);
-
-static void imx_dma_watchdog(unsigned long chno)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
- imx_dmav1_writel(0, DMA_CCR(chno));
- imxdma->in_use = 0;
- imxdma->sg = NULL;
-
- if (imxdma->err_handler)
- imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
-}
-
-static irqreturn_t dma_err_handler(int irq, void *dev_id)
-{
- int i, disr;
- struct imx_dma_channel *imxdma;
- unsigned int err_mask;
- int errcode;
-
- disr = imx_dmav1_readl(DMA_DISR);
-
- err_mask = imx_dmav1_readl(DMA_DBTOSR) |
- imx_dmav1_readl(DMA_DRTOSR) |
- imx_dmav1_readl(DMA_DSESR) |
- imx_dmav1_readl(DMA_DBOSR);
-
- if (!err_mask)
- return IRQ_HANDLED;
-
- imx_dmav1_writel(disr & err_mask, DMA_DISR);
-
- for (i = 0; i < IMX_DMA_CHANNELS; i++) {
- if (!(err_mask & (1 << i)))
- continue;
- imxdma = &imx_dma_channels[i];
- errcode = 0;
-
- if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DBTOSR);
- errcode |= IMX_DMA_ERR_BURST;
- }
- if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DRTOSR);
- errcode |= IMX_DMA_ERR_REQUEST;
- }
- if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DSESR);
- errcode |= IMX_DMA_ERR_TRANSFER;
- }
- if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
- imx_dmav1_writel(1 << i, DMA_DBOSR);
- errcode |= IMX_DMA_ERR_BUFFER;
- }
- if (imxdma->name && imxdma->err_handler) {
- imxdma->err_handler(i, imxdma->data, errcode);
- continue;
- }
-
- imx_dma_channels[i].sg = NULL;
-
- printk(KERN_WARNING
- "DMA timeout on channel %d (%s) -%s%s%s%s\n",
- i, imxdma->name,
- errcode & IMX_DMA_ERR_BURST ? " burst" : "",
- errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
- errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
- errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
- }
- return IRQ_HANDLED;
-}
-
-static void dma_irq_handle_channel(int chno)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
- if (!imxdma->name) {
- /*
- * IRQ for an unregistered DMA channel:
- * let's clear the interrupts and disable it.
- */
- printk(KERN_WARNING
- "spurious IRQ for DMA channel %d\n", chno);
- return;
- }
-
- if (imxdma->sg) {
- u32 tmp;
- struct scatterlist *current_sg = imxdma->sg;
- imxdma->sg = sg_next(imxdma->sg);
-
- if (imxdma->sg) {
- imx_dma_sg_next(chno, imxdma->sg);
-
- tmp = imx_dmav1_readl(DMA_CCR(chno));
-
- if (imx_dma_hw_chain(imxdma)) {
- /* FIXME: The timeout should probably be
- * configurable
- */
- mod_timer(&imxdma->watchdog,
- jiffies + msecs_to_jiffies(500));
-
- tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
- imx_dmav1_writel(tmp, DMA_CCR(chno));
- } else {
- imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
- tmp |= CCR_CEN;
- }
-
- imx_dmav1_writel(tmp, DMA_CCR(chno));
-
- if (imxdma->prog_handler)
- imxdma->prog_handler(chno, imxdma->data,
- current_sg);
-
- return;
- }
-
- if (imx_dma_hw_chain(imxdma)) {
- del_timer(&imxdma->watchdog);
- return;
- }
- }
-
- imx_dmav1_writel(0, DMA_CCR(chno));
- imxdma->in_use = 0;
- if (imxdma->irq_handler)
- imxdma->irq_handler(chno, imxdma->data);
-}
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
- int i, disr;
-
- if (cpu_is_mx21() || cpu_is_mx27())
- dma_err_handler(irq, dev_id);
-
- disr = imx_dmav1_readl(DMA_DISR);
-
- pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
- disr);
-
- imx_dmav1_writel(disr, DMA_DISR);
- for (i = 0; i < IMX_DMA_CHANNELS; i++) {
- if (disr & (1 << i))
- dma_irq_handle_channel(i);
- }
-
- return IRQ_HANDLED;
-}
-
-/**
- * imx_dma_request - request/allocate specified channel number
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- */
-int imx_dma_request(int channel, const char *name)
-{
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
- unsigned long flags;
- int ret = 0;
-
- /* basic sanity checks */
- if (!name)
- return -EINVAL;
-
- if (channel >= IMX_DMA_CHANNELS) {
- printk(KERN_CRIT "%s: called for non-existed channel %d\n",
- __func__, channel);
- return -EINVAL;
- }
-
- local_irq_save(flags);
- if (imxdma->name) {
- local_irq_restore(flags);
- return -EBUSY;
- }
- memset(imxdma, 0, sizeof(*imxdma));
- imxdma->name = name;
- local_irq_restore(flags); /* request_irq() can block */
-
- if (cpu_is_mx21() || cpu_is_mx27()) {
- ret = request_irq(MX2x_INT_DMACH0 + channel,
- dma_irq_handler, 0, "DMA", NULL);
- if (ret) {
- imxdma->name = NULL;
- pr_crit("Can't register IRQ %d for DMA channel %d\n",
- MX2x_INT_DMACH0 + channel, channel);
- return ret;
- }
- init_timer(&imxdma->watchdog);
- imxdma->watchdog.function = &imx_dma_watchdog;
- imxdma->watchdog.data = channel;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(imx_dma_request);
-
-/**
- * imx_dma_free - release previously acquired channel
- * @channel: i.MX DMA channel number
- */
-void imx_dma_free(int channel)
-{
- unsigned long flags;
- struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
- if (!imxdma->name) {
- printk(KERN_CRIT
- "%s: trying to free free channel %d\n",
- __func__, channel);
- return;
- }
-
- local_irq_save(flags);
- /* Disable interrupts */
- imx_dma_disable(channel);
- imxdma->name = NULL;
-
- if (cpu_is_mx21() || cpu_is_mx27())
- free_irq(MX2x_INT_DMACH0 + channel, NULL);
-
- local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_free);
-
-/**
- * imx_dma_request_by_prio - find and request some of free channels best
- * suiting requested priority
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- *
- * This function tries to find a free channel in the specified priority group
- * if the priority cannot be achieved it tries to look for free channel
- * in the higher and then even lower priority groups.
- *
- * Return value: If there is no free channel to allocate, -%ENODEV is returned.
- * On successful allocation channel is returned.
- */
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
-{
- int i;
- int best;
-
- switch (prio) {
- case (DMA_PRIO_HIGH):
- best = 8;
- break;
- case (DMA_PRIO_MEDIUM):
- best = 4;
- break;
- case (DMA_PRIO_LOW):
- default:
- best = 0;
- break;
- }
-
- for (i = best; i < IMX_DMA_CHANNELS; i++)
- if (!imx_dma_request(i, name))
- return i;
-
- for (i = best - 1; i >= 0; i--)
- if (!imx_dma_request(i, name))
- return i;
-
- printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
-
- return -ENODEV;
-}
-EXPORT_SYMBOL(imx_dma_request_by_prio);
-
-static int __init imx_dma_init(void)
-{
- int ret = 0;
- int i;
-
- if (cpu_is_mx1())
- imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
- else if (cpu_is_mx21())
- imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
- else if (cpu_is_mx27())
- imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
- else
- return 0;
-
- dma_clk = clk_get(NULL, "dma");
- if (IS_ERR(dma_clk))
- return PTR_ERR(dma_clk);
- clk_enable(dma_clk);
-
- /* reset DMA module */
- imx_dmav1_writel(DCR_DRST, DMA_DCR);
-
- if (cpu_is_mx1()) {
- ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
- if (ret) {
- pr_crit("Wow! Can't register IRQ for DMA\n");
- return ret;
- }
-
- ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
- if (ret) {
- pr_crit("Wow! Can't register ERRIRQ for DMA\n");
- free_irq(MX1_DMA_INT, NULL);
- return ret;
- }
- }
-
- /* enable DMA module */
- imx_dmav1_writel(DCR_DEN, DMA_DCR);
-
- /* clear all interrupts */
- imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
-
- /* disable interrupts */
- imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
- for (i = 0; i < IMX_DMA_CHANNELS; i++) {
- imx_dma_channels[i].sg = NULL;
- imx_dma_channels[i].dma_num = i;
- }
-
- return ret;
-}
-
-arch_initcall(imx_dma_init);
diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h
deleted file mode 100644
index ac6fd71..0000000
--- a/arch/arm/mach-imx/include/mach/dma-v1.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * linux/arch/arm/mach-imx/include/mach/dma-v1.h
- *
- * i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_DMA_V1_H__
-#define __MACH_DMA_V1_H__
-
-#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
-
-#include <mach/dma.h>
-
-#define IMX_DMA_CHANNELS 16
-
-#define DMA_MODE_READ 0
-#define DMA_MODE_WRITE 1
-#define DMA_MODE_MASK 1
-
-#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
-
-/* DMA Interrupt Mask Register */
-#define MX1_DMA_DIMR MX1_DMA_REG(0x08)
-
-/* Channel Control Register */
-#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6))
-
-#define IMX_DMA_MEMSIZE_32 (0 << 4)
-#define IMX_DMA_MEMSIZE_8 (1 << 4)
-#define IMX_DMA_MEMSIZE_16 (2 << 4)
-#define IMX_DMA_TYPE_LINEAR (0 << 10)
-#define IMX_DMA_TYPE_2D (1 << 10)
-#define IMX_DMA_TYPE_FIFO (2 << 10)
-
-#define IMX_DMA_ERR_BURST (1 << 0)
-#define IMX_DMA_ERR_REQUEST (1 << 1)
-#define IMX_DMA_ERR_TRANSFER (1 << 2)
-#define IMX_DMA_ERR_BUFFER (1 << 3)
-#define IMX_DMA_ERR_TIMEOUT (1 << 4)
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
- unsigned int config_mem, unsigned int dmareq, int hw_chaining);
-
-void
-imx_dma_config_burstlen(int channel, unsigned int burstlen);
-
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
- unsigned int dma_length, unsigned int dev_addr,
- unsigned int dmamode);
-
-
-/*
- * Use this flag as the dma_length argument to imx_dma_setup_sg()
- * to create an endless running dma loop. The end of the scatterlist
- * must be linked to the beginning for this to work.
- */
-#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
-
-int
-imx_dma_setup_sg(int channel, struct scatterlist *sg,
- unsigned int sgcount, unsigned int dma_length,
- unsigned int dev_addr, unsigned int dmamode);
-
-int
-imx_dma_setup_handlers(int channel,
- void (*irq_handler) (int, void *),
- void (*err_handler) (int, void *, int), void *data);
-
-int
-imx_dma_setup_progression_handler(int channel,
- void (*prog_handler) (int, void*, struct scatterlist*));
-
-void imx_dma_enable(int channel);
-
-void imx_dma_disable(int channel);
-
-int imx_dma_request(int channel, const char *name);
-
-void imx_dma_free(int channel);
-
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
-
-#endif /* __MACH_DMA_V1_H__ */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
2012-03-05 16:16 ` Javier Martin
@ 2012-03-07 6:42 ` Vinod Koul
-1 siblings, 0 replies; 40+ messages in thread
From: Vinod Koul @ 2012-03-07 6:42 UTC (permalink / raw)
To: Javier Martin, Sascha Hauer
Cc: linux-arm-kernel, linux, linux-kernel, kernel, dan.j.williams
On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
Sascha,
Are there any more users of dmac in mach-imx? If not then why not move
the code, rather than copy. If yes can we move them as well?
> Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
> ---
> arch/arm/mach-imx/Kconfig | 6 -
> arch/arm/mach-imx/Makefile | 2 -
> drivers/dma/Kconfig | 1 -
> drivers/dma/imx-dma.c | 591 ++++++++++++++++++++++++++++++++++++++++----
> 4 files changed, 541 insertions(+), 59 deletions(-)
>
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 0e6de36..3da1421 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -1,6 +1,3 @@
> -config IMX_HAVE_DMA_V1
> - bool
> -
> config HAVE_IMX_GPC
> bool
>
> @@ -26,7 +23,6 @@ config SOC_IMX1
> bool
> select ARCH_MX1
> select CPU_ARM920T
> - select IMX_HAVE_DMA_V1
> select IMX_HAVE_IOMUX_V1
> select MXC_AVIC
>
> @@ -35,7 +31,6 @@ config SOC_IMX21
> select MACH_MX21
> select CPU_ARM926T
> select ARCH_MXC_AUDMUX_V1
> - select IMX_HAVE_DMA_V1
> select IMX_HAVE_IOMUX_V1
> select MXC_AVIC
>
> @@ -52,7 +47,6 @@ config SOC_IMX27
> select MACH_MX27
> select CPU_ARM926T
> select ARCH_MXC_AUDMUX_V1
> - select IMX_HAVE_DMA_V1
> select IMX_HAVE_IOMUX_V1
> select MXC_AVIC
>
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index f5920c2..a62dc3a 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -1,5 +1,3 @@
> -obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
> -
> obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
> obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index f1a2749..eb58b91 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -231,7 +231,6 @@ config IMX_SDMA
>
> config IMX_DMA
> tristate "i.MX DMA support"
> - depends on IMX_HAVE_DMA_V1
> select DMA_ENGINE
> help
> Support the i.MX DMA engine. This engine is integrated into
> diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
> index c32103f..28d716c 100644
> --- a/drivers/dma/imx-dma.c
> +++ b/drivers/dma/imx-dma.c
> @@ -14,7 +14,6 @@
> * http://www.opensource.org/licenses/gpl-license.html
> * http://www.gnu.org/copyleft/gpl.html
> */
> -
> #include <linux/init.h>
> #include <linux/module.h>
> #include <linux/types.h>
> @@ -25,14 +24,88 @@
> #include <linux/dma-mapping.h>
> #include <linux/slab.h>
> #include <linux/platform_device.h>
> +#include <linux/clk.h>
> #include <linux/dmaengine.h>
> #include <linux/module.h>
>
> #include <asm/irq.h>
> -#include <mach/dma-v1.h>
> +#include <mach/dma.h>
> #include <mach/hardware.h>
>
> #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
> +#define IMX_DMA_CHANNELS 16
> +
> +#define DMA_MODE_READ 0
> +#define DMA_MODE_WRITE 1
> +#define DMA_MODE_MASK 1
> +
> +#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
> +#define IMX_DMA_MEMSIZE_32 (0 << 4)
> +#define IMX_DMA_MEMSIZE_8 (1 << 4)
> +#define IMX_DMA_MEMSIZE_16 (2 << 4)
> +#define IMX_DMA_TYPE_LINEAR (0 << 10)
> +#define IMX_DMA_TYPE_2D (1 << 10)
> +#define IMX_DMA_TYPE_FIFO (2 << 10)
> +
> +#define IMX_DMA_ERR_BURST (1 << 0)
> +#define IMX_DMA_ERR_REQUEST (1 << 1)
> +#define IMX_DMA_ERR_TRANSFER (1 << 2)
> +#define IMX_DMA_ERR_BUFFER (1 << 3)
> +#define IMX_DMA_ERR_TIMEOUT (1 << 4)
> +
> +#define DMA_DCR 0x00 /* Control Register */
> +#define DMA_DISR 0x04 /* Interrupt status Register */
> +#define DMA_DIMR 0x08 /* Interrupt mask Register */
> +#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
> +#define DMA_DRTOSR 0x10 /* Request timeout Register */
> +#define DMA_DSESR 0x14 /* Transfer Error Status Register */
> +#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
> +#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
> +#define DMA_WSRA 0x40 /* W-Size Register A */
> +#define DMA_XSRA 0x44 /* X-Size Register A */
> +#define DMA_YSRA 0x48 /* Y-Size Register A */
> +#define DMA_WSRB 0x4c /* W-Size Register B */
> +#define DMA_XSRB 0x50 /* X-Size Register B */
> +#define DMA_YSRB 0x54 /* Y-Size Register B */
> +#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
> +#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
> +#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
> +#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
> +#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
> +#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
> +#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
> +#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
> +#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
> +
> +#define DCR_DRST (1<<1)
> +#define DCR_DEN (1<<0)
> +#define DBTOCR_EN (1<<15)
> +#define DBTOCR_CNT(x) ((x) & 0x7fff)
> +#define CNTR_CNT(x) ((x) & 0xffffff)
> +#define CCR_ACRPT (1<<14)
> +#define CCR_DMOD_LINEAR (0x0 << 12)
> +#define CCR_DMOD_2D (0x1 << 12)
> +#define CCR_DMOD_FIFO (0x2 << 12)
> +#define CCR_DMOD_EOBFIFO (0x3 << 12)
> +#define CCR_SMOD_LINEAR (0x0 << 10)
> +#define CCR_SMOD_2D (0x1 << 10)
> +#define CCR_SMOD_FIFO (0x2 << 10)
> +#define CCR_SMOD_EOBFIFO (0x3 << 10)
> +#define CCR_MDIR_DEC (1<<9)
> +#define CCR_MSEL_B (1<<8)
> +#define CCR_DSIZ_32 (0x0 << 6)
> +#define CCR_DSIZ_8 (0x1 << 6)
> +#define CCR_DSIZ_16 (0x2 << 6)
> +#define CCR_SSIZ_32 (0x0 << 4)
> +#define CCR_SSIZ_8 (0x1 << 4)
> +#define CCR_SSIZ_16 (0x2 << 4)
> +#define CCR_REN (1<<3)
> +#define CCR_RPT (1<<2)
> +#define CCR_FRC (1<<1)
> +#define CCR_CEN (1<<0)
> +#define RTOR_EN (1<<15)
> +#define RTOR_CLK (1<<14)
> +#define RTOR_PSC (1<<13)
>
> enum imxdma_prep_type {
> IMXDMA_DESC_MEMCPY,
> @@ -41,6 +114,39 @@ enum imxdma_prep_type {
> IMXDMA_DESC_CYCLIC,
> };
>
> +/*
> + * struct imxdma_channel_internal - i.MX specific DMA extension
> + * @name: name specified by DMA client
> + * @irq_handler: client callback for end of transfer
> + * @err_handler: client callback for error condition
> + * @data: clients context data for callbacks
> + * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
> + * @sg: pointer to the actual read/written chunk for scatter-gather emulation
> + * @resbytes: total residual number of bytes to transfer
> + * (it can be lower or same as sum of SG mapped chunk sizes)
> + * @sgcount: number of chunks to be read/written
> + *
> + * Structure is used for IMX DMA processing. It would be probably good
> + * @struct dma_struct in the future for external interfacing and use
> + * @struct imxdma_channel_internal only as extension to it.
> + */
> +
> +struct imxdma_channel_internal {
> + void *data;
> + unsigned int dma_mode;
> + struct scatterlist *sg;
> + unsigned int resbytes;
> +
> + int in_use;
> +
> + u32 ccr_from_device;
> + u32 ccr_to_device;
> +
> + struct timer_list watchdog;
> +
> + int hw_chaining;
> +};
> +
> struct imxdma_desc {
> struct list_head node;
> struct dma_async_tx_descriptor desc;
> @@ -63,9 +169,9 @@ struct imxdma_desc {
> };
>
> struct imxdma_channel {
> + struct imxdma_channel_internal internal;
> struct imxdma_engine *imxdma;
> unsigned int channel;
> - unsigned int imxdma_channel;
>
> struct tasklet_struct dma_tasklet;
> struct list_head ld_free;
> @@ -109,28 +215,381 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
> return false;
> }
>
> -static void imxdma_irq_handler(int channel, void *data)
> +/* TODO: put this inside any struct */
> +static void __iomem *imx_dmav1_baseaddr;
> +static struct clk *dma_clk;
> +
> +static void imx_dmav1_writel(unsigned val, unsigned offset)
> {
> - struct imxdma_channel *imxdmac = data;
> + __raw_writel(val, imx_dmav1_baseaddr + offset);
> +}
>
> - tasklet_schedule(&imxdmac->dma_tasklet);
> +static unsigned imx_dmav1_readl(unsigned offset)
> +{
> + return __raw_readl(imx_dmav1_baseaddr + offset);
> }
>
> -static void imxdma_err_handler(int channel, void *data, int error)
> +static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
> {
> - struct imxdma_channel *imxdmac = data;
> + if (cpu_is_mx27())
> + return imxdma->hw_chaining;
> + else
> + return 0;
> +}
> +
> +/*
> + * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
> + */
> +static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
> +{
> + struct imxdma_channel_internal *imxdma = &imxdmac->internal;
> + unsigned long now;
> +
> + now = min(imxdma->resbytes, sg->length);
> + if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
> + imxdma->resbytes -= now;
> +
> + if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
> + imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
> + else
> + imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
> +
> + imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
> +
> + pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
> + "size 0x%08x\n", imxdmac->channel,
> + imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
> + imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
> + imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
> +
> + return now;
> +}
> +
> +static int
> +imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
> + unsigned int dma_length, unsigned int dev_addr,
> + unsigned int dmamode)
> +{
> + int channel = imxdmac->channel;
> +
> + imxdmac->internal.sg = NULL;
> + imxdmac->internal.dma_mode = dmamode;
> +
> + if (!dma_address) {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
> + channel);
> + return -EINVAL;
> + }
> +
> + if (!dma_length) {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
> + channel);
> + return -EINVAL;
> + }
> +
> + if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
> + pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
> + "dev_addr=0x%08x for read\n",
> + channel, __func__, (unsigned int)dma_address,
> + dma_length, dev_addr);
> +
> + imx_dmav1_writel(dev_addr, DMA_SAR(channel));
> + imx_dmav1_writel(dma_address, DMA_DAR(channel));
> + imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
> + } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
> + pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
> + "dev_addr=0x%08x for write\n",
> + channel, __func__, (unsigned int)dma_address,
> + dma_length, dev_addr);
> +
> + imx_dmav1_writel(dma_address, DMA_SAR(channel));
> + imx_dmav1_writel(dev_addr, DMA_DAR(channel));
> + imx_dmav1_writel(imxdmac->internal.ccr_to_device,
> + DMA_CCR(channel));
> + } else {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
> + channel);
> + return -EINVAL;
> + }
>
> + imx_dmav1_writel(dma_length, DMA_CNTR(channel));
> +
> + return 0;
> +}
> +
> +static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
> +{
> + int channel = imxdmac->channel;
> + unsigned long flags;
> +
> + pr_debug("imxdma%d: imx_dma_enable\n", channel);
> +
> + if (imxdmac->internal.in_use)
> + return;
> +
> + local_irq_save(flags);
> +
> + imx_dmav1_writel(1 << channel, DMA_DISR);
> + imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
> + imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
> + CCR_ACRPT, DMA_CCR(channel));
> +
> + if ((cpu_is_mx21() || cpu_is_mx27()) &&
> + imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
> + imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
> + if (imxdmac->internal.sg) {
> + u32 tmp;
> + imxdma_sg_next(imxdmac, imxdmac->internal.sg);
> + tmp = imx_dmav1_readl(DMA_CCR(channel));
> + imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
> + DMA_CCR(channel));
> + }
> + }
> + imxdmac->internal.in_use = 1;
> +
> + local_irq_restore(flags);
> +}
> +
> +static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
> +{
> + int channel = imxdmac->channel;
> + unsigned long flags;
> +
> + pr_debug("imxdma%d: imx_dma_disable\n", channel);
> +
> + if (imxdma_hw_chain(&imxdmac->internal))
> + del_timer(&imxdmac->internal.watchdog);
> +
> + local_irq_save(flags);
> + imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
> + imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
> + DMA_CCR(channel));
> + imx_dmav1_writel(1 << channel, DMA_DISR);
> + imxdmac->internal.in_use = 0;
> + local_irq_restore(flags);
> +}
> +
> +static int
> +imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
> + unsigned int config_mem, unsigned int dmareq, int hw_chaining)
> +{
> + int channel = imxdmac->channel;
> + u32 dreq = 0;
> +
> + imxdmac->internal.hw_chaining = 0;
> +
> + if (hw_chaining) {
> + imxdmac->internal.hw_chaining = 1;
> + if (!imxdma_hw_chain(&imxdmac->internal))
> + return -EINVAL;
> + }
> +
> + if (dmareq)
> + dreq = CCR_REN;
> +
> + imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
> + imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
> +
> + imx_dmav1_writel(dmareq, DMA_RSSR(channel));
> +
> + return 0;
> +}
> +
> +static int
> +imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
> + struct scatterlist *sg, unsigned int sgcount,
> + unsigned int dma_length, unsigned int dev_addr,
> + unsigned int dmamode)
> +{
> + int channel = imxdmac->channel;
> +
> + if (imxdmac->internal.in_use)
> + return -EBUSY;
> +
> + imxdmac->internal.sg = sg;
> + imxdmac->internal.dma_mode = dmamode;
> + imxdmac->internal.resbytes = dma_length;
> +
> + if (!sg || !sgcount) {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
> + channel);
> + return -EINVAL;
> + }
> +
> + if (!sg->length) {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
> + channel);
> + return -EINVAL;
> + }
> +
> + if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
> + pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
> + "dev_addr=0x%08x for read\n",
> + channel, __func__, sg, sgcount, dma_length, dev_addr);
> +
> + imx_dmav1_writel(dev_addr, DMA_SAR(channel));
> + imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
> + } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
> + pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
> + "dev_addr=0x%08x for write\n",
> + channel, __func__, sg, sgcount, dma_length, dev_addr);
> +
> + imx_dmav1_writel(dev_addr, DMA_DAR(channel));
> + imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
> + } else {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
> + channel);
> + return -EINVAL;
> + }
> +
> + imxdma_sg_next(imxdmac, sg);
> +
> + return 0;
> +}
> +
> +static void imxdma_watchdog(unsigned long data)
> +{
> + struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
> + int channel = imxdmac->channel;
> +
> + imx_dmav1_writel(0, DMA_CCR(channel));
> + imxdmac->internal.in_use = 0;
> + imxdmac->internal.sg = NULL;
> +
> + /* Tasklet watchdog error handler */
> tasklet_schedule(&imxdmac->dma_tasklet);
> + pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
> +}
> +
> +static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
> +{
> + struct imxdma_engine *imxdma = dev_id;
> + struct imxdma_channel_internal *internal;
> + unsigned int err_mask;
> + int i, disr;
> + int errcode;
> +
> + disr = imx_dmav1_readl(DMA_DISR);
> +
> + err_mask = imx_dmav1_readl(DMA_DBTOSR) |
> + imx_dmav1_readl(DMA_DRTOSR) |
> + imx_dmav1_readl(DMA_DSESR) |
> + imx_dmav1_readl(DMA_DBOSR);
> +
> + if (!err_mask)
> + return IRQ_HANDLED;
> +
> + imx_dmav1_writel(disr & err_mask, DMA_DISR);
> +
> + for (i = 0; i < IMX_DMA_CHANNELS; i++) {
> + if (!(err_mask & (1 << i)))
> + continue;
> + internal = &imxdma->channel[i].internal;
> + errcode = 0;
> +
> + if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
> + imx_dmav1_writel(1 << i, DMA_DBTOSR);
> + errcode |= IMX_DMA_ERR_BURST;
> + }
> + if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
> + imx_dmav1_writel(1 << i, DMA_DRTOSR);
> + errcode |= IMX_DMA_ERR_REQUEST;
> + }
> + if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
> + imx_dmav1_writel(1 << i, DMA_DSESR);
> + errcode |= IMX_DMA_ERR_TRANSFER;
> + }
> + if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
> + imx_dmav1_writel(1 << i, DMA_DBOSR);
> + errcode |= IMX_DMA_ERR_BUFFER;
> + }
> + /* Tasklet error handler */
> + tasklet_schedule(&imxdma->channel[i].dma_tasklet);
> +
> + printk(KERN_WARNING
> + "DMA timeout on channel %d -%s%s%s%s\n", i,
> + errcode & IMX_DMA_ERR_BURST ? " burst" : "",
> + errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
> + errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
> + errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
> + }
> + return IRQ_HANDLED;
> }
>
> -static void imxdma_progression(int channel, void *data,
> - struct scatterlist *sg)
> +static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
> {
> - struct imxdma_channel *imxdmac = data;
> + struct imxdma_channel_internal *imxdma = &imxdmac->internal;
> + int chno = imxdmac->channel;
> +
> + if (imxdma->sg) {
> + u32 tmp;
> + imxdma->sg = sg_next(imxdma->sg);
> +
> + if (imxdma->sg) {
> + imxdma_sg_next(imxdmac, imxdma->sg);
> +
> + tmp = imx_dmav1_readl(DMA_CCR(chno));
> +
> + if (imxdma_hw_chain(imxdma)) {
> + /* FIXME: The timeout should probably be
> + * configurable
> + */
> + mod_timer(&imxdma->watchdog,
> + jiffies + msecs_to_jiffies(500));
> +
> + tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
> + imx_dmav1_writel(tmp, DMA_CCR(chno));
> + } else {
> + imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
> + tmp |= CCR_CEN;
> + }
> +
> + imx_dmav1_writel(tmp, DMA_CCR(chno));
> +
> + if (imxdma_chan_is_doing_cyclic(imxdmac))
> + /* Tasklet progression */
> + tasklet_schedule(&imxdmac->dma_tasklet);
> +
> + return;
> + }
>
> + if (imxdma_hw_chain(imxdma)) {
> + del_timer(&imxdma->watchdog);
> + return;
> + }
> + }
> +
> + imx_dmav1_writel(0, DMA_CCR(chno));
> + imxdma->in_use = 0;
> + /* Tasklet irq */
> tasklet_schedule(&imxdmac->dma_tasklet);
> }
>
> +static irqreturn_t dma_irq_handler(int irq, void *dev_id)
> +{
> + struct imxdma_engine *imxdma = dev_id;
> + struct imxdma_channel_internal *internal;
> + int i, disr;
> +
> + if (cpu_is_mx21() || cpu_is_mx27())
> + imxdma_err_handler(irq, dev_id);
> +
> + disr = imx_dmav1_readl(DMA_DISR);
> +
> + pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
> + disr);
> +
> + imx_dmav1_writel(disr, DMA_DISR);
> + for (i = 0; i < IMX_DMA_CHANNELS; i++) {
> + if (disr & (1 << i)) {
> + internal = &imxdma->channel[i].internal;
> + dma_irq_handle_channel(&imxdma->channel[i]);
> + }
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> static int imxdma_xfer_desc(struct imxdma_desc *d)
> {
> struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> @@ -139,31 +598,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
> /* Configure and enable */
> switch (d->type) {
> case IMXDMA_DESC_MEMCPY:
> - ret = imx_dma_config_channel(imxdmac->imxdma_channel,
> + ret = imxdma_config_channel_hw(imxdmac,
> d->config_port, d->config_mem, 0, 0);
> if (ret < 0)
> return ret;
> - ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
> + ret = imxdma_setup_single_hw(imxdmac, d->src,
> d->len, d->dest, d->dmamode);
> if (ret < 0)
> return ret;
> break;
> +
> + /* Cyclic transfer is the same as slave_sg with special sg configuration. */
> case IMXDMA_DESC_CYCLIC:
> - ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
> - imxdma_progression);
> - if (ret < 0)
> - return ret;
> - /*
> - * We fall through here since cyclic transfer is the same as
> - * slave_sg adding a progression handler and a specific sg
> - * configuration which is done in 'imxdma_prep_dma_cyclic'.
> - */
> case IMXDMA_DESC_SLAVE_SG:
> if (d->dmamode == DMA_MODE_READ)
> - ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
> + ret = imxdma_setup_sg_hw(imxdmac, d->sg,
> d->sgcount, d->len, d->src, d->dmamode);
> else
> - ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
> + ret = imxdma_setup_sg_hw(imxdmac, d->sg,
> d->sgcount, d->len, d->dest, d->dmamode);
> if (ret < 0)
> return ret;
> @@ -171,7 +623,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
> default:
> return -EINVAL;
> }
> - imx_dma_enable(imxdmac->imxdma_channel);
> + imxdma_enable_hw(imxdmac);
> return 0;
> }
>
> @@ -223,7 +675,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>
> switch (cmd) {
> case DMA_TERMINATE_ALL:
> - imx_dma_disable(imxdmac->imxdma_channel);
> + imxdma_disable_hw(imxdmac);
>
> spin_lock_irqsave(&imxdmac->lock, flags);
> list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
> @@ -253,16 +705,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> mode = IMX_DMA_MEMSIZE_32;
> break;
> }
> - ret = imx_dma_config_channel(imxdmac->imxdma_channel,
> + ret = imxdma_config_channel_hw(imxdmac,
> mode | IMX_DMA_TYPE_FIFO,
> IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
> imxdmac->dma_request, 1);
>
> if (ret)
> return ret;
> -
> - imx_dma_config_burstlen(imxdmac->imxdma_channel,
> - imxdmac->watermark_level * imxdmac->word_size);
> + /* Set burst length */
> + imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
> + DMA_BLR(imxdmac->channel));
>
> return 0;
> default:
> @@ -359,7 +811,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
>
> spin_lock_irqsave(&imxdmac->lock, flags);
>
> - imx_dma_disable(imxdmac->imxdma_channel);
> + imxdma_disable_hw(imxdmac);
> list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
> list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
>
> @@ -545,10 +997,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
> }
>
> static int __init imxdma_probe(struct platform_device *pdev)
> -{
> + {
> struct imxdma_engine *imxdma;
> int ret, i;
>
> + if (cpu_is_mx1())
> + imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
> + else if (cpu_is_mx21())
> + imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
> + else if (cpu_is_mx27())
> + imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
> + else
> + return 0;
> +
> + dma_clk = clk_get(NULL, "dma");
> + if (IS_ERR(dma_clk))
> + return PTR_ERR(dma_clk);
> + clk_enable(dma_clk);
> +
> + /* reset DMA module */
> + imx_dmav1_writel(DCR_DRST, DMA_DCR);
> +
> + if (cpu_is_mx1()) {
> + ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
> + if (ret) {
> + pr_crit("Can't register IRQ for DMA\n");
> + return ret;
> + }
> +
> + ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
> + if (ret) {
> + pr_crit("Can't register ERRIRQ for DMA\n");
> + free_irq(MX1_DMA_INT, NULL);
> + return ret;
> + }
> + }
> +
> + /* enable DMA module */
> + imx_dmav1_writel(DCR_DEN, DMA_DCR);
> +
> + /* clear all interrupts */
> + imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
> +
> + /* disable interrupts */
> + imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
> +
> imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
> if (!imxdma)
> return -ENOMEM;
> @@ -562,17 +1055,20 @@ static int __init imxdma_probe(struct platform_device *pdev)
> /* Initialize channel parameters */
> for (i = 0; i < MAX_DMA_CHANNELS; i++) {
> struct imxdma_channel *imxdmac = &imxdma->channel[i];
> -
> - imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
> - DMA_PRIO_MEDIUM);
> - if ((int)imxdmac->channel < 0) {
> - ret = -ENODEV;
> - goto err_init;
> + memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
> + if (cpu_is_mx21() || cpu_is_mx27()) {
> + ret = request_irq(MX2x_INT_DMACH0 + i,
> + dma_irq_handler, 0, "DMA", imxdma);
> + if (ret) {
> + pr_crit("Can't register IRQ %d for DMA channel %d\n",
> + MX2x_INT_DMACH0 + i, i);
> + goto err_init;
> + }
> + init_timer(&imxdmac->internal.watchdog);
> + imxdmac->internal.watchdog.function = &imxdma_watchdog;
> + imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
> }
>
> - imx_dma_setup_handlers(imxdmac->imxdma_channel,
> - imxdma_irq_handler, imxdma_err_handler, imxdmac);
> -
> imxdmac->imxdma = imxdma;
> spin_lock_init(&imxdmac->lock);
>
> @@ -617,10 +1113,8 @@ static int __init imxdma_probe(struct platform_device *pdev)
> return 0;
>
> err_init:
> - while (--i >= 0) {
> - struct imxdma_channel *imxdmac = &imxdma->channel[i];
> - imx_dma_free(imxdmac->imxdma_channel);
> - }
> + while (--i >= 0)
> + free_irq(MX2x_INT_DMACH0 + i, NULL);
>
> kfree(imxdma);
> return ret;
> @@ -633,11 +1127,8 @@ static int __exit imxdma_remove(struct platform_device *pdev)
>
> dma_async_device_unregister(&imxdma->dma_device);
>
> - for (i = 0; i < MAX_DMA_CHANNELS; i++) {
> - struct imxdma_channel *imxdmac = &imxdma->channel[i];
> -
> - imx_dma_free(imxdmac->imxdma_channel);
> - }
> + for (i = 0; i < MAX_DMA_CHANNELS; i++)
> + free_irq(MX2x_INT_DMACH0 + i, NULL);
>
> kfree(imxdma);
>
--
~Vinod
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
@ 2012-03-07 6:42 ` Vinod Koul
0 siblings, 0 replies; 40+ messages in thread
From: Vinod Koul @ 2012-03-07 6:42 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
Sascha,
Are there any more users of dmac in mach-imx? If not then why not move
the code, rather than copy. If yes can we move them as well?
> Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
> ---
> arch/arm/mach-imx/Kconfig | 6 -
> arch/arm/mach-imx/Makefile | 2 -
> drivers/dma/Kconfig | 1 -
> drivers/dma/imx-dma.c | 591 ++++++++++++++++++++++++++++++++++++++++----
> 4 files changed, 541 insertions(+), 59 deletions(-)
>
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 0e6de36..3da1421 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -1,6 +1,3 @@
> -config IMX_HAVE_DMA_V1
> - bool
> -
> config HAVE_IMX_GPC
> bool
>
> @@ -26,7 +23,6 @@ config SOC_IMX1
> bool
> select ARCH_MX1
> select CPU_ARM920T
> - select IMX_HAVE_DMA_V1
> select IMX_HAVE_IOMUX_V1
> select MXC_AVIC
>
> @@ -35,7 +31,6 @@ config SOC_IMX21
> select MACH_MX21
> select CPU_ARM926T
> select ARCH_MXC_AUDMUX_V1
> - select IMX_HAVE_DMA_V1
> select IMX_HAVE_IOMUX_V1
> select MXC_AVIC
>
> @@ -52,7 +47,6 @@ config SOC_IMX27
> select MACH_MX27
> select CPU_ARM926T
> select ARCH_MXC_AUDMUX_V1
> - select IMX_HAVE_DMA_V1
> select IMX_HAVE_IOMUX_V1
> select MXC_AVIC
>
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index f5920c2..a62dc3a 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -1,5 +1,3 @@
> -obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
> -
> obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
> obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index f1a2749..eb58b91 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -231,7 +231,6 @@ config IMX_SDMA
>
> config IMX_DMA
> tristate "i.MX DMA support"
> - depends on IMX_HAVE_DMA_V1
> select DMA_ENGINE
> help
> Support the i.MX DMA engine. This engine is integrated into
> diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
> index c32103f..28d716c 100644
> --- a/drivers/dma/imx-dma.c
> +++ b/drivers/dma/imx-dma.c
> @@ -14,7 +14,6 @@
> * http://www.opensource.org/licenses/gpl-license.html
> * http://www.gnu.org/copyleft/gpl.html
> */
> -
> #include <linux/init.h>
> #include <linux/module.h>
> #include <linux/types.h>
> @@ -25,14 +24,88 @@
> #include <linux/dma-mapping.h>
> #include <linux/slab.h>
> #include <linux/platform_device.h>
> +#include <linux/clk.h>
> #include <linux/dmaengine.h>
> #include <linux/module.h>
>
> #include <asm/irq.h>
> -#include <mach/dma-v1.h>
> +#include <mach/dma.h>
> #include <mach/hardware.h>
>
> #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
> +#define IMX_DMA_CHANNELS 16
> +
> +#define DMA_MODE_READ 0
> +#define DMA_MODE_WRITE 1
> +#define DMA_MODE_MASK 1
> +
> +#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
> +#define IMX_DMA_MEMSIZE_32 (0 << 4)
> +#define IMX_DMA_MEMSIZE_8 (1 << 4)
> +#define IMX_DMA_MEMSIZE_16 (2 << 4)
> +#define IMX_DMA_TYPE_LINEAR (0 << 10)
> +#define IMX_DMA_TYPE_2D (1 << 10)
> +#define IMX_DMA_TYPE_FIFO (2 << 10)
> +
> +#define IMX_DMA_ERR_BURST (1 << 0)
> +#define IMX_DMA_ERR_REQUEST (1 << 1)
> +#define IMX_DMA_ERR_TRANSFER (1 << 2)
> +#define IMX_DMA_ERR_BUFFER (1 << 3)
> +#define IMX_DMA_ERR_TIMEOUT (1 << 4)
> +
> +#define DMA_DCR 0x00 /* Control Register */
> +#define DMA_DISR 0x04 /* Interrupt status Register */
> +#define DMA_DIMR 0x08 /* Interrupt mask Register */
> +#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
> +#define DMA_DRTOSR 0x10 /* Request timeout Register */
> +#define DMA_DSESR 0x14 /* Transfer Error Status Register */
> +#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
> +#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
> +#define DMA_WSRA 0x40 /* W-Size Register A */
> +#define DMA_XSRA 0x44 /* X-Size Register A */
> +#define DMA_YSRA 0x48 /* Y-Size Register A */
> +#define DMA_WSRB 0x4c /* W-Size Register B */
> +#define DMA_XSRB 0x50 /* X-Size Register B */
> +#define DMA_YSRB 0x54 /* Y-Size Register B */
> +#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
> +#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
> +#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
> +#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
> +#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
> +#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
> +#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
> +#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
> +#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
> +
> +#define DCR_DRST (1<<1)
> +#define DCR_DEN (1<<0)
> +#define DBTOCR_EN (1<<15)
> +#define DBTOCR_CNT(x) ((x) & 0x7fff)
> +#define CNTR_CNT(x) ((x) & 0xffffff)
> +#define CCR_ACRPT (1<<14)
> +#define CCR_DMOD_LINEAR (0x0 << 12)
> +#define CCR_DMOD_2D (0x1 << 12)
> +#define CCR_DMOD_FIFO (0x2 << 12)
> +#define CCR_DMOD_EOBFIFO (0x3 << 12)
> +#define CCR_SMOD_LINEAR (0x0 << 10)
> +#define CCR_SMOD_2D (0x1 << 10)
> +#define CCR_SMOD_FIFO (0x2 << 10)
> +#define CCR_SMOD_EOBFIFO (0x3 << 10)
> +#define CCR_MDIR_DEC (1<<9)
> +#define CCR_MSEL_B (1<<8)
> +#define CCR_DSIZ_32 (0x0 << 6)
> +#define CCR_DSIZ_8 (0x1 << 6)
> +#define CCR_DSIZ_16 (0x2 << 6)
> +#define CCR_SSIZ_32 (0x0 << 4)
> +#define CCR_SSIZ_8 (0x1 << 4)
> +#define CCR_SSIZ_16 (0x2 << 4)
> +#define CCR_REN (1<<3)
> +#define CCR_RPT (1<<2)
> +#define CCR_FRC (1<<1)
> +#define CCR_CEN (1<<0)
> +#define RTOR_EN (1<<15)
> +#define RTOR_CLK (1<<14)
> +#define RTOR_PSC (1<<13)
>
> enum imxdma_prep_type {
> IMXDMA_DESC_MEMCPY,
> @@ -41,6 +114,39 @@ enum imxdma_prep_type {
> IMXDMA_DESC_CYCLIC,
> };
>
> +/*
> + * struct imxdma_channel_internal - i.MX specific DMA extension
> + * @name: name specified by DMA client
> + * @irq_handler: client callback for end of transfer
> + * @err_handler: client callback for error condition
> + * @data: clients context data for callbacks
> + * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
> + * @sg: pointer to the actual read/written chunk for scatter-gather emulation
> + * @resbytes: total residual number of bytes to transfer
> + * (it can be lower or same as sum of SG mapped chunk sizes)
> + * @sgcount: number of chunks to be read/written
> + *
> + * Structure is used for IMX DMA processing. It would be probably good
> + * @struct dma_struct in the future for external interfacing and use
> + * @struct imxdma_channel_internal only as extension to it.
> + */
> +
> +struct imxdma_channel_internal {
> + void *data;
> + unsigned int dma_mode;
> + struct scatterlist *sg;
> + unsigned int resbytes;
> +
> + int in_use;
> +
> + u32 ccr_from_device;
> + u32 ccr_to_device;
> +
> + struct timer_list watchdog;
> +
> + int hw_chaining;
> +};
> +
> struct imxdma_desc {
> struct list_head node;
> struct dma_async_tx_descriptor desc;
> @@ -63,9 +169,9 @@ struct imxdma_desc {
> };
>
> struct imxdma_channel {
> + struct imxdma_channel_internal internal;
> struct imxdma_engine *imxdma;
> unsigned int channel;
> - unsigned int imxdma_channel;
>
> struct tasklet_struct dma_tasklet;
> struct list_head ld_free;
> @@ -109,28 +215,381 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
> return false;
> }
>
> -static void imxdma_irq_handler(int channel, void *data)
> +/* TODO: put this inside any struct */
> +static void __iomem *imx_dmav1_baseaddr;
> +static struct clk *dma_clk;
> +
> +static void imx_dmav1_writel(unsigned val, unsigned offset)
> {
> - struct imxdma_channel *imxdmac = data;
> + __raw_writel(val, imx_dmav1_baseaddr + offset);
> +}
>
> - tasklet_schedule(&imxdmac->dma_tasklet);
> +static unsigned imx_dmav1_readl(unsigned offset)
> +{
> + return __raw_readl(imx_dmav1_baseaddr + offset);
> }
>
> -static void imxdma_err_handler(int channel, void *data, int error)
> +static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
> {
> - struct imxdma_channel *imxdmac = data;
> + if (cpu_is_mx27())
> + return imxdma->hw_chaining;
> + else
> + return 0;
> +}
> +
> +/*
> + * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
> + */
> +static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
> +{
> + struct imxdma_channel_internal *imxdma = &imxdmac->internal;
> + unsigned long now;
> +
> + now = min(imxdma->resbytes, sg->length);
> + if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
> + imxdma->resbytes -= now;
> +
> + if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
> + imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
> + else
> + imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
> +
> + imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
> +
> + pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
> + "size 0x%08x\n", imxdmac->channel,
> + imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
> + imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
> + imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
> +
> + return now;
> +}
> +
> +static int
> +imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
> + unsigned int dma_length, unsigned int dev_addr,
> + unsigned int dmamode)
> +{
> + int channel = imxdmac->channel;
> +
> + imxdmac->internal.sg = NULL;
> + imxdmac->internal.dma_mode = dmamode;
> +
> + if (!dma_address) {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
> + channel);
> + return -EINVAL;
> + }
> +
> + if (!dma_length) {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
> + channel);
> + return -EINVAL;
> + }
> +
> + if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
> + pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
> + "dev_addr=0x%08x for read\n",
> + channel, __func__, (unsigned int)dma_address,
> + dma_length, dev_addr);
> +
> + imx_dmav1_writel(dev_addr, DMA_SAR(channel));
> + imx_dmav1_writel(dma_address, DMA_DAR(channel));
> + imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
> + } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
> + pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
> + "dev_addr=0x%08x for write\n",
> + channel, __func__, (unsigned int)dma_address,
> + dma_length, dev_addr);
> +
> + imx_dmav1_writel(dma_address, DMA_SAR(channel));
> + imx_dmav1_writel(dev_addr, DMA_DAR(channel));
> + imx_dmav1_writel(imxdmac->internal.ccr_to_device,
> + DMA_CCR(channel));
> + } else {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
> + channel);
> + return -EINVAL;
> + }
>
> + imx_dmav1_writel(dma_length, DMA_CNTR(channel));
> +
> + return 0;
> +}
> +
> +static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
> +{
> + int channel = imxdmac->channel;
> + unsigned long flags;
> +
> + pr_debug("imxdma%d: imx_dma_enable\n", channel);
> +
> + if (imxdmac->internal.in_use)
> + return;
> +
> + local_irq_save(flags);
> +
> + imx_dmav1_writel(1 << channel, DMA_DISR);
> + imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
> + imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
> + CCR_ACRPT, DMA_CCR(channel));
> +
> + if ((cpu_is_mx21() || cpu_is_mx27()) &&
> + imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
> + imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
> + if (imxdmac->internal.sg) {
> + u32 tmp;
> + imxdma_sg_next(imxdmac, imxdmac->internal.sg);
> + tmp = imx_dmav1_readl(DMA_CCR(channel));
> + imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
> + DMA_CCR(channel));
> + }
> + }
> + imxdmac->internal.in_use = 1;
> +
> + local_irq_restore(flags);
> +}
> +
> +static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
> +{
> + int channel = imxdmac->channel;
> + unsigned long flags;
> +
> + pr_debug("imxdma%d: imx_dma_disable\n", channel);
> +
> + if (imxdma_hw_chain(&imxdmac->internal))
> + del_timer(&imxdmac->internal.watchdog);
> +
> + local_irq_save(flags);
> + imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
> + imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
> + DMA_CCR(channel));
> + imx_dmav1_writel(1 << channel, DMA_DISR);
> + imxdmac->internal.in_use = 0;
> + local_irq_restore(flags);
> +}
> +
> +static int
> +imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
> + unsigned int config_mem, unsigned int dmareq, int hw_chaining)
> +{
> + int channel = imxdmac->channel;
> + u32 dreq = 0;
> +
> + imxdmac->internal.hw_chaining = 0;
> +
> + if (hw_chaining) {
> + imxdmac->internal.hw_chaining = 1;
> + if (!imxdma_hw_chain(&imxdmac->internal))
> + return -EINVAL;
> + }
> +
> + if (dmareq)
> + dreq = CCR_REN;
> +
> + imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
> + imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
> +
> + imx_dmav1_writel(dmareq, DMA_RSSR(channel));
> +
> + return 0;
> +}
> +
> +static int
> +imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
> + struct scatterlist *sg, unsigned int sgcount,
> + unsigned int dma_length, unsigned int dev_addr,
> + unsigned int dmamode)
> +{
> + int channel = imxdmac->channel;
> +
> + if (imxdmac->internal.in_use)
> + return -EBUSY;
> +
> + imxdmac->internal.sg = sg;
> + imxdmac->internal.dma_mode = dmamode;
> + imxdmac->internal.resbytes = dma_length;
> +
> + if (!sg || !sgcount) {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
> + channel);
> + return -EINVAL;
> + }
> +
> + if (!sg->length) {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
> + channel);
> + return -EINVAL;
> + }
> +
> + if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
> + pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
> + "dev_addr=0x%08x for read\n",
> + channel, __func__, sg, sgcount, dma_length, dev_addr);
> +
> + imx_dmav1_writel(dev_addr, DMA_SAR(channel));
> + imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
> + } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
> + pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
> + "dev_addr=0x%08x for write\n",
> + channel, __func__, sg, sgcount, dma_length, dev_addr);
> +
> + imx_dmav1_writel(dev_addr, DMA_DAR(channel));
> + imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
> + } else {
> + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
> + channel);
> + return -EINVAL;
> + }
> +
> + imxdma_sg_next(imxdmac, sg);
> +
> + return 0;
> +}
> +
> +static void imxdma_watchdog(unsigned long data)
> +{
> + struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
> + int channel = imxdmac->channel;
> +
> + imx_dmav1_writel(0, DMA_CCR(channel));
> + imxdmac->internal.in_use = 0;
> + imxdmac->internal.sg = NULL;
> +
> + /* Tasklet watchdog error handler */
> tasklet_schedule(&imxdmac->dma_tasklet);
> + pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
> +}
> +
> +static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
> +{
> + struct imxdma_engine *imxdma = dev_id;
> + struct imxdma_channel_internal *internal;
> + unsigned int err_mask;
> + int i, disr;
> + int errcode;
> +
> + disr = imx_dmav1_readl(DMA_DISR);
> +
> + err_mask = imx_dmav1_readl(DMA_DBTOSR) |
> + imx_dmav1_readl(DMA_DRTOSR) |
> + imx_dmav1_readl(DMA_DSESR) |
> + imx_dmav1_readl(DMA_DBOSR);
> +
> + if (!err_mask)
> + return IRQ_HANDLED;
> +
> + imx_dmav1_writel(disr & err_mask, DMA_DISR);
> +
> + for (i = 0; i < IMX_DMA_CHANNELS; i++) {
> + if (!(err_mask & (1 << i)))
> + continue;
> + internal = &imxdma->channel[i].internal;
> + errcode = 0;
> +
> + if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
> + imx_dmav1_writel(1 << i, DMA_DBTOSR);
> + errcode |= IMX_DMA_ERR_BURST;
> + }
> + if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
> + imx_dmav1_writel(1 << i, DMA_DRTOSR);
> + errcode |= IMX_DMA_ERR_REQUEST;
> + }
> + if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
> + imx_dmav1_writel(1 << i, DMA_DSESR);
> + errcode |= IMX_DMA_ERR_TRANSFER;
> + }
> + if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
> + imx_dmav1_writel(1 << i, DMA_DBOSR);
> + errcode |= IMX_DMA_ERR_BUFFER;
> + }
> + /* Tasklet error handler */
> + tasklet_schedule(&imxdma->channel[i].dma_tasklet);
> +
> + printk(KERN_WARNING
> + "DMA timeout on channel %d -%s%s%s%s\n", i,
> + errcode & IMX_DMA_ERR_BURST ? " burst" : "",
> + errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
> + errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
> + errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
> + }
> + return IRQ_HANDLED;
> }
>
> -static void imxdma_progression(int channel, void *data,
> - struct scatterlist *sg)
> +static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
> {
> - struct imxdma_channel *imxdmac = data;
> + struct imxdma_channel_internal *imxdma = &imxdmac->internal;
> + int chno = imxdmac->channel;
> +
> + if (imxdma->sg) {
> + u32 tmp;
> + imxdma->sg = sg_next(imxdma->sg);
> +
> + if (imxdma->sg) {
> + imxdma_sg_next(imxdmac, imxdma->sg);
> +
> + tmp = imx_dmav1_readl(DMA_CCR(chno));
> +
> + if (imxdma_hw_chain(imxdma)) {
> + /* FIXME: The timeout should probably be
> + * configurable
> + */
> + mod_timer(&imxdma->watchdog,
> + jiffies + msecs_to_jiffies(500));
> +
> + tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
> + imx_dmav1_writel(tmp, DMA_CCR(chno));
> + } else {
> + imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
> + tmp |= CCR_CEN;
> + }
> +
> + imx_dmav1_writel(tmp, DMA_CCR(chno));
> +
> + if (imxdma_chan_is_doing_cyclic(imxdmac))
> + /* Tasklet progression */
> + tasklet_schedule(&imxdmac->dma_tasklet);
> +
> + return;
> + }
>
> + if (imxdma_hw_chain(imxdma)) {
> + del_timer(&imxdma->watchdog);
> + return;
> + }
> + }
> +
> + imx_dmav1_writel(0, DMA_CCR(chno));
> + imxdma->in_use = 0;
> + /* Tasklet irq */
> tasklet_schedule(&imxdmac->dma_tasklet);
> }
>
> +static irqreturn_t dma_irq_handler(int irq, void *dev_id)
> +{
> + struct imxdma_engine *imxdma = dev_id;
> + struct imxdma_channel_internal *internal;
> + int i, disr;
> +
> + if (cpu_is_mx21() || cpu_is_mx27())
> + imxdma_err_handler(irq, dev_id);
> +
> + disr = imx_dmav1_readl(DMA_DISR);
> +
> + pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
> + disr);
> +
> + imx_dmav1_writel(disr, DMA_DISR);
> + for (i = 0; i < IMX_DMA_CHANNELS; i++) {
> + if (disr & (1 << i)) {
> + internal = &imxdma->channel[i].internal;
> + dma_irq_handle_channel(&imxdma->channel[i]);
> + }
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> static int imxdma_xfer_desc(struct imxdma_desc *d)
> {
> struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> @@ -139,31 +598,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
> /* Configure and enable */
> switch (d->type) {
> case IMXDMA_DESC_MEMCPY:
> - ret = imx_dma_config_channel(imxdmac->imxdma_channel,
> + ret = imxdma_config_channel_hw(imxdmac,
> d->config_port, d->config_mem, 0, 0);
> if (ret < 0)
> return ret;
> - ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
> + ret = imxdma_setup_single_hw(imxdmac, d->src,
> d->len, d->dest, d->dmamode);
> if (ret < 0)
> return ret;
> break;
> +
> + /* Cyclic transfer is the same as slave_sg with special sg configuration. */
> case IMXDMA_DESC_CYCLIC:
> - ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
> - imxdma_progression);
> - if (ret < 0)
> - return ret;
> - /*
> - * We fall through here since cyclic transfer is the same as
> - * slave_sg adding a progression handler and a specific sg
> - * configuration which is done in 'imxdma_prep_dma_cyclic'.
> - */
> case IMXDMA_DESC_SLAVE_SG:
> if (d->dmamode == DMA_MODE_READ)
> - ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
> + ret = imxdma_setup_sg_hw(imxdmac, d->sg,
> d->sgcount, d->len, d->src, d->dmamode);
> else
> - ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
> + ret = imxdma_setup_sg_hw(imxdmac, d->sg,
> d->sgcount, d->len, d->dest, d->dmamode);
> if (ret < 0)
> return ret;
> @@ -171,7 +623,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
> default:
> return -EINVAL;
> }
> - imx_dma_enable(imxdmac->imxdma_channel);
> + imxdma_enable_hw(imxdmac);
> return 0;
> }
>
> @@ -223,7 +675,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>
> switch (cmd) {
> case DMA_TERMINATE_ALL:
> - imx_dma_disable(imxdmac->imxdma_channel);
> + imxdma_disable_hw(imxdmac);
>
> spin_lock_irqsave(&imxdmac->lock, flags);
> list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
> @@ -253,16 +705,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> mode = IMX_DMA_MEMSIZE_32;
> break;
> }
> - ret = imx_dma_config_channel(imxdmac->imxdma_channel,
> + ret = imxdma_config_channel_hw(imxdmac,
> mode | IMX_DMA_TYPE_FIFO,
> IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
> imxdmac->dma_request, 1);
>
> if (ret)
> return ret;
> -
> - imx_dma_config_burstlen(imxdmac->imxdma_channel,
> - imxdmac->watermark_level * imxdmac->word_size);
> + /* Set burst length */
> + imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
> + DMA_BLR(imxdmac->channel));
>
> return 0;
> default:
> @@ -359,7 +811,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
>
> spin_lock_irqsave(&imxdmac->lock, flags);
>
> - imx_dma_disable(imxdmac->imxdma_channel);
> + imxdma_disable_hw(imxdmac);
> list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
> list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
>
> @@ -545,10 +997,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
> }
>
> static int __init imxdma_probe(struct platform_device *pdev)
> -{
> + {
> struct imxdma_engine *imxdma;
> int ret, i;
>
> + if (cpu_is_mx1())
> + imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
> + else if (cpu_is_mx21())
> + imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
> + else if (cpu_is_mx27())
> + imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
> + else
> + return 0;
> +
> + dma_clk = clk_get(NULL, "dma");
> + if (IS_ERR(dma_clk))
> + return PTR_ERR(dma_clk);
> + clk_enable(dma_clk);
> +
> + /* reset DMA module */
> + imx_dmav1_writel(DCR_DRST, DMA_DCR);
> +
> + if (cpu_is_mx1()) {
> + ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
> + if (ret) {
> + pr_crit("Can't register IRQ for DMA\n");
> + return ret;
> + }
> +
> + ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
> + if (ret) {
> + pr_crit("Can't register ERRIRQ for DMA\n");
> + free_irq(MX1_DMA_INT, NULL);
> + return ret;
> + }
> + }
> +
> + /* enable DMA module */
> + imx_dmav1_writel(DCR_DEN, DMA_DCR);
> +
> + /* clear all interrupts */
> + imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
> +
> + /* disable interrupts */
> + imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
> +
> imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
> if (!imxdma)
> return -ENOMEM;
> @@ -562,17 +1055,20 @@ static int __init imxdma_probe(struct platform_device *pdev)
> /* Initialize channel parameters */
> for (i = 0; i < MAX_DMA_CHANNELS; i++) {
> struct imxdma_channel *imxdmac = &imxdma->channel[i];
> -
> - imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
> - DMA_PRIO_MEDIUM);
> - if ((int)imxdmac->channel < 0) {
> - ret = -ENODEV;
> - goto err_init;
> + memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
> + if (cpu_is_mx21() || cpu_is_mx27()) {
> + ret = request_irq(MX2x_INT_DMACH0 + i,
> + dma_irq_handler, 0, "DMA", imxdma);
> + if (ret) {
> + pr_crit("Can't register IRQ %d for DMA channel %d\n",
> + MX2x_INT_DMACH0 + i, i);
> + goto err_init;
> + }
> + init_timer(&imxdmac->internal.watchdog);
> + imxdmac->internal.watchdog.function = &imxdma_watchdog;
> + imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
> }
>
> - imx_dma_setup_handlers(imxdmac->imxdma_channel,
> - imxdma_irq_handler, imxdma_err_handler, imxdmac);
> -
> imxdmac->imxdma = imxdma;
> spin_lock_init(&imxdmac->lock);
>
> @@ -617,10 +1113,8 @@ static int __init imxdma_probe(struct platform_device *pdev)
> return 0;
>
> err_init:
> - while (--i >= 0) {
> - struct imxdma_channel *imxdmac = &imxdma->channel[i];
> - imx_dma_free(imxdmac->imxdma_channel);
> - }
> + while (--i >= 0)
> + free_irq(MX2x_INT_DMACH0 + i, NULL);
>
> kfree(imxdma);
> return ret;
> @@ -633,11 +1127,8 @@ static int __exit imxdma_remove(struct platform_device *pdev)
>
> dma_async_device_unregister(&imxdma->dma_device);
>
> - for (i = 0; i < MAX_DMA_CHANNELS; i++) {
> - struct imxdma_channel *imxdmac = &imxdma->channel[i];
> -
> - imx_dma_free(imxdmac->imxdma_channel);
> - }
> + for (i = 0; i < MAX_DMA_CHANNELS; i++)
> + free_irq(MX2x_INT_DMACH0 + i, NULL);
>
> kfree(imxdma);
>
--
~Vinod
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
2012-03-07 6:42 ` Vinod Koul
@ 2012-03-07 7:52 ` javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: javier Martin @ 2012-03-07 7:52 UTC (permalink / raw)
To: Vinod Koul
Cc: Sascha Hauer, linux-arm-kernel, linux, linux-kernel, kernel,
dan.j.williams
Hi Vinod,
On 7 March 2012 07:42, Vinod Koul <vinod.koul@intel.com> wrote:
> On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
> Sascha,
> Are there any more users of dmac in mach-imx?
No, there are no other users of mach-imx. In fact, it was Sascha's
idea to make this merge [1].
> If not then why not move the code, rather than copy.
> If yes can we move them as well?
I do remove the code in mach-imx in PATCH 14/14. I considered it was
better doing this in the last patch to keep the old code available
during the whole development process.
[1] https://lkml.org/lkml/2012/2/9/171
--
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
@ 2012-03-07 7:52 ` javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: javier Martin @ 2012-03-07 7:52 UTC (permalink / raw)
To: linux-arm-kernel
Hi Vinod,
On 7 March 2012 07:42, Vinod Koul <vinod.koul@intel.com> wrote:
> On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
> Sascha,
> Are there any more users of dmac in mach-imx?
No, there are no other users of mach-imx. In fact, it was Sascha's
idea to make this merge [1].
> If not then why not move the code, rather than copy.
> If yes can we move them as well?
I do remove the code in mach-imx in PATCH 14/14. I considered it was
better doing this in the last patch to keep the old code available
during the whole development process.
[1] https://lkml.org/lkml/2012/2/9/171
--
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 04/14] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
2012-03-05 16:16 ` Javier Martin
@ 2012-03-07 8:03 ` Vinod Koul
-1 siblings, 0 replies; 40+ messages in thread
From: Vinod Koul @ 2012-03-07 8:03 UTC (permalink / raw)
To: Javier Martin
Cc: linux-arm-kernel, linux, linux-kernel, kernel, dan.j.williams
On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
will help to know in change log why you are doing this...
> Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
> ---
> drivers/dma/imx-dma.c | 57 ++++++++++++-------------------------------------
> 1 files changed, 14 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
> index 2c524e1..8a0afb1 100644
> --- a/drivers/dma/imx-dma.c
> +++ b/drivers/dma/imx-dma.c
> @@ -260,41 +260,6 @@ static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
> return now;
> }
>
> -static int
> -imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
> - unsigned int dma_length, unsigned int dev_addr)
> -{
> - int channel = imxdmac->channel;
> -
> - imxdmac->internal.sg = NULL;
> -
> - if (!dma_address) {
> - printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
> - channel);
> - return -EINVAL;
> - }
> -
> - if (!dma_length) {
> - printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
> - channel);
> - return -EINVAL;
> - }
> -
> - pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
> - "dev_addr=0x%08x for write\n",
> - channel, __func__, (unsigned int)dma_address,
> - dma_length, dev_addr);
> -
> - imx_dmav1_writel(dma_address, DMA_SAR(channel));
> - imx_dmav1_writel(dev_addr, DMA_DAR(channel));
> - imx_dmav1_writel(imxdmac->internal.ccr_to_device,
> - DMA_CCR(channel));
> -
> - imx_dmav1_writel(dma_length, DMA_CNTR(channel));
> -
> - return 0;
> -}
> -
> static void imxdma_enable_hw(struct imxdma_desc *d)
> {
> struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> @@ -586,20 +551,26 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
> static int imxdma_xfer_desc(struct imxdma_desc *d)
> {
> struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> + struct imxdma_engine *imxdma = imxdmac->imxdma;
> int ret;
>
> /* Configure and enable */
> switch (d->type) {
> case IMXDMA_DESC_MEMCPY:
> - ret = imxdma_config_channel_hw(imxdmac,
> - d->config_port, d->config_mem, 0, 0);
> - if (ret < 0)
> - return ret;
> - ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
> - if (ret < 0)
> - return ret;
> - break;
> + imxdmac->internal.sg = NULL;
> +
> + imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
> + imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
> + imx_dmav1_writel(d->config_mem | (d->config_port << 2),
> + DMA_CCR(imxdmac->channel));
>
> + imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
> +
> + dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
> + "dma_length=%d\n", __func__, imxdmac->channel,
> + d->dest, d->src, d->len);
> +
> + break;
> /* Cyclic transfer is the same as slave_sg with special sg configuration. */
> case IMXDMA_DESC_CYCLIC:
> case IMXDMA_DESC_SLAVE_SG:
--
~Vinod
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 04/14] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
@ 2012-03-07 8:03 ` Vinod Koul
0 siblings, 0 replies; 40+ messages in thread
From: Vinod Koul @ 2012-03-07 8:03 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
will help to know in change log why you are doing this...
> Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
> ---
> drivers/dma/imx-dma.c | 57 ++++++++++++-------------------------------------
> 1 files changed, 14 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
> index 2c524e1..8a0afb1 100644
> --- a/drivers/dma/imx-dma.c
> +++ b/drivers/dma/imx-dma.c
> @@ -260,41 +260,6 @@ static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
> return now;
> }
>
> -static int
> -imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
> - unsigned int dma_length, unsigned int dev_addr)
> -{
> - int channel = imxdmac->channel;
> -
> - imxdmac->internal.sg = NULL;
> -
> - if (!dma_address) {
> - printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
> - channel);
> - return -EINVAL;
> - }
> -
> - if (!dma_length) {
> - printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
> - channel);
> - return -EINVAL;
> - }
> -
> - pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
> - "dev_addr=0x%08x for write\n",
> - channel, __func__, (unsigned int)dma_address,
> - dma_length, dev_addr);
> -
> - imx_dmav1_writel(dma_address, DMA_SAR(channel));
> - imx_dmav1_writel(dev_addr, DMA_DAR(channel));
> - imx_dmav1_writel(imxdmac->internal.ccr_to_device,
> - DMA_CCR(channel));
> -
> - imx_dmav1_writel(dma_length, DMA_CNTR(channel));
> -
> - return 0;
> -}
> -
> static void imxdma_enable_hw(struct imxdma_desc *d)
> {
> struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> @@ -586,20 +551,26 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
> static int imxdma_xfer_desc(struct imxdma_desc *d)
> {
> struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> + struct imxdma_engine *imxdma = imxdmac->imxdma;
> int ret;
>
> /* Configure and enable */
> switch (d->type) {
> case IMXDMA_DESC_MEMCPY:
> - ret = imxdma_config_channel_hw(imxdmac,
> - d->config_port, d->config_mem, 0, 0);
> - if (ret < 0)
> - return ret;
> - ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
> - if (ret < 0)
> - return ret;
> - break;
> + imxdmac->internal.sg = NULL;
> +
> + imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
> + imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
> + imx_dmav1_writel(d->config_mem | (d->config_port << 2),
> + DMA_CCR(imxdmac->channel));
>
> + imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
> +
> + dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
> + "dma_length=%d\n", __func__, imxdmac->channel,
> + d->dest, d->src, d->len);
> +
> + break;
> /* Cyclic transfer is the same as slave_sg with special sg configuration. */
> case IMXDMA_DESC_CYCLIC:
> case IMXDMA_DESC_SLAVE_SG:
--
~Vinod
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
2012-03-07 7:52 ` javier Martin
@ 2012-03-07 8:15 ` Vinod Koul
-1 siblings, 0 replies; 40+ messages in thread
From: Vinod Koul @ 2012-03-07 8:15 UTC (permalink / raw)
To: javier Martin
Cc: Sascha Hauer, linux-arm-kernel, linux, linux-kernel, kernel,
dan.j.williams
On Wed, 2012-03-07 at 08:52 +0100, javier Martin wrote:
> Hi Vinod,
>
> On 7 March 2012 07:42, Vinod Koul <vinod.koul@intel.com> wrote:
> > On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
> > Sascha,
> > Are there any more users of dmac in mach-imx?
>
> No, there are no other users of mach-imx. In fact, it was Sascha's
> idea to make this merge [1].
Then please move the file in 1st patch, also it would be easily clear
what parts are added, deleted and moved.
Otherwise the series looks fine except that it needs to have a better
changelog on why you are removing certain field/struct. It helps to
document the motivation of doing certain change, you will find that you
wont remember that six months down the line :)
Also I am looking for Tested-By from people who have use imx-dma.
>
> > If not then why not move the code, rather than copy.
> > If yes can we move them as well?
>
> I do remove the code in mach-imx in PATCH 14/14. I considered it was
> better doing this in the last patch to keep the old code available
> during the whole development process.
>
> [1] https://lkml.org/lkml/2012/2/9/171
>
--
~Vinod
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
@ 2012-03-07 8:15 ` Vinod Koul
0 siblings, 0 replies; 40+ messages in thread
From: Vinod Koul @ 2012-03-07 8:15 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2012-03-07 at 08:52 +0100, javier Martin wrote:
> Hi Vinod,
>
> On 7 March 2012 07:42, Vinod Koul <vinod.koul@intel.com> wrote:
> > On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
> > Sascha,
> > Are there any more users of dmac in mach-imx?
>
> No, there are no other users of mach-imx. In fact, it was Sascha's
> idea to make this merge [1].
Then please move the file in 1st patch, also it would be easily clear
what parts are added, deleted and moved.
Otherwise the series looks fine except that it needs to have a better
changelog on why you are removing certain field/struct. It helps to
document the motivation of doing certain change, you will find that you
wont remember that six months down the line :)
Also I am looking for Tested-By from people who have use imx-dma.
>
> > If not then why not move the code, rather than copy.
> > If yes can we move them as well?
>
> I do remove the code in mach-imx in PATCH 14/14. I considered it was
> better doing this in the last patch to keep the old code available
> during the whole development process.
>
> [1] https://lkml.org/lkml/2012/2/9/171
>
--
~Vinod
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
2012-03-07 8:15 ` Vinod Koul
@ 2012-03-07 9:25 ` javier Martin
-1 siblings, 0 replies; 40+ messages in thread
From: javier Martin @ 2012-03-07 9:25 UTC (permalink / raw)
To: Vinod Koul
Cc: Sascha Hauer, linux-arm-kernel, linux, linux-kernel, kernel,
dan.j.williams
On 7 March 2012 09:15, Vinod Koul <vinod.koul@intel.com> wrote:
> On Wed, 2012-03-07 at 08:52 +0100, javier Martin wrote:
>> Hi Vinod,
>>
>> On 7 March 2012 07:42, Vinod Koul <vinod.koul@intel.com> wrote:
>> > On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
>> > Sascha,
>> > Are there any more users of dmac in mach-imx?
>>
>> No, there are no other users of mach-imx. In fact, it was Sascha's
>> idea to make this merge [1].
> Then please move the file in 1st patch, also it would be easily clear
> what parts are added, deleted and moved.
All right, I will, but I'll wait for Sascha and others to comment on
the series too.
> Otherwise the series looks fine except that it needs to have a better
> changelog on why you are removing certain field/struct. It helps to
> document the motivation of doing certain change, you will find that you
> wont remember that six months down the line :)
Thanks for the suggestion, I'll rewrite my changelogs.
> Also I am looking for Tested-By from people who have use imx-dma.
That would be awesome. I've tested this series with a test battery which covers:
- mxcmmc
- audio
- dmatest module
--
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
@ 2012-03-07 9:25 ` javier Martin
0 siblings, 0 replies; 40+ messages in thread
From: javier Martin @ 2012-03-07 9:25 UTC (permalink / raw)
To: linux-arm-kernel
On 7 March 2012 09:15, Vinod Koul <vinod.koul@intel.com> wrote:
> On Wed, 2012-03-07 at 08:52 +0100, javier Martin wrote:
>> Hi Vinod,
>>
>> On 7 March 2012 07:42, Vinod Koul <vinod.koul@intel.com> wrote:
>> > On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
>> > Sascha,
>> > Are there any more users of dmac in mach-imx?
>>
>> No, there are no other users of mach-imx. In fact, it was Sascha's
>> idea to make this merge [1].
> Then please move the file in 1st patch, also it would be easily clear
> what parts are added, deleted and moved.
All right, I will, but I'll wait for Sascha and others to comment on
the series too.
> Otherwise the series looks fine except that it needs to have a better
> changelog on why you are removing certain field/struct. It helps to
> document the motivation of doing certain change, you will find that you
> wont remember that six months down the line :)
Thanks for the suggestion, I'll rewrite my changelogs.
> Also I am looking for Tested-By from people who have use imx-dma.
That would be awesome. I've tested this series with a test battery which covers:
- mxcmmc
- audio
- dmatest module
--
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com
^ permalink raw reply [flat|nested] 40+ messages in thread
end of thread, other threads:[~2012-03-07 9:25 UTC | newest]
Thread overview: 40+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-03-05 16:16 [PATCH 00/14] dmaengine: imx-dma: merge dma arch code into dmaengine Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-07 6:42 ` Vinod Koul
2012-03-07 6:42 ` Vinod Koul
2012-03-07 7:52 ` javier Martin
2012-03-07 7:52 ` javier Martin
2012-03-07 8:15 ` Vinod Koul
2012-03-07 8:15 ` Vinod Koul
2012-03-07 9:25 ` javier Martin
2012-03-07 9:25 ` javier Martin
2012-03-05 16:16 ` [PATCH 02/14] dmaengine: imx-dma: remove data member form internal structure Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 03/14] dmaengine: imx-dma: remove dma_mode member of " Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 04/14] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-07 8:03 ` Vinod Koul
2012-03-07 8:03 ` Vinod Koul
2012-03-05 16:16 ` [PATCH 05/14] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 06/14] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 07/14] dmaengine: imx-dma: remove sg member from internal structure Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 08/14] dmaengine: imx-dma: remove in_use field of " Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 09/14] dmaengine: imx-dma: remove resbytes " Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 10/14] dmaengine: imx-dma: remove " Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 11/14] dmaengine: imx-dma: remove unused arg of imxdma_sg_next Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 12/14] dmaengine: imx-dma: integrate 'imx_dmav1_baseaddr' and 'dma_clk' inside dmaengine structure Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 13/14] dmaengine: imx-dma: use dev_dbg and dev_warn for messages Javier Martin
2012-03-05 16:16 ` Javier Martin
2012-03-05 16:16 ` [PATCH 14/14] dmaengine: imx-dma: remove dma-v1.c and dma-v1.h Javier Martin
2012-03-05 16:16 ` Javier Martin
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