[U-Boot] [PATCH v2 00/19] updates for keymile arm boards

[U-Boot] [PATCH v2 00/19] updates for keymile arm boards

[Valentin Longchamp]

This patch series updates keymile boards with Kirkwood CPU and adds
two new boards. This new boards are kmnusa and kmcoge5un. Also the
existing boards with own config files were migrated to the common
header km_kirkwood.h. Some small adaption in generic kirkwood code
was needed due to two new features on the new board. First one is
that the u-boot environment is in the SPI NOR flash and the second one
is the direct MAC/MAC connection from the mvgbe interface to an
simple switch.

Changes for v2:
	- removed the two patches "spi/kirkwood: add weak functions
	board_spi_bus_claim/release" and "mvgbe: remove warning for
	unused methods" from the series as they are were independent from
	it. The series is however dependent of these two patches.

Holger Brunck (13):
  arm/km: add board type to boards.cfg
  arm/km: add piggy mac adress offset for mgcoge3un
  arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
  arm/km: use ARRAY_SIZE macro
  arm/km: fix wrong comment in SDRAM config for mgcoge3un
  arm/km: change maintainer for mgcoge3un
  arm/km: remove CONFIG_RESET_PHY_R
  km/arm: remove spi toggle command
  arm/km: add kmnusa board support
  arm/km: add kmcoge5un board support
  arm/km: convert mgcoge3un target to km_kirkwood
  arm/km: remove portl2.h and use km_kirkwood instead
  arm/km: cleanup km_kirkwood boards

Valentin Longchamp (6):
  arm/km: enable mii cmd
  arm/km: use correct kw_gpio function for NAND/SPI switching
  arm/km: implement weak function board_spi_clam_bus/release
  arm/kirkwood: protect the ENV_SPI #defines
  arm/km: correct init of 88e6352 switch in the reset_phy function
  arm/km: enable BOCO2 FPGA download support

 MAINTAINERS                                 |    4 +-
 arch/arm/include/asm/arch-kirkwood/config.h |   12 +-
 board/keymile/common/common.h               |   12 +
 board/keymile/km_arm/128M16-1.cfg           |  290 ++++++++++++++++++++++++++
 board/keymile/km_arm/256M8-1.cfg            |  292 +++++++++++++++++++++++++++
 board/keymile/km_arm/Makefile               |    8 +
 board/keymile/km_arm/fpga_config.c          |  212 +++++++++++++++++++
 board/keymile/km_arm/km_arm.c               |  119 +++++++-----
 board/keymile/km_arm/kwbimage-memphis.cfg   |    2 +-
 board/keymile/km_arm/managed_switch.c       |  166 +++++++++++++++
 boards.cfg                                  |   10 +-
 include/configs/km/km_arm.h                 |   60 ++++--
 include/configs/km_kirkwood.h               |  157 +++++++++++++--
 include/configs/mgcoge3un.h                 |   86 --------
 include/configs/portl2.h                    |   85 --------
 15 files changed, 1256 insertions(+), 259 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg
 create mode 100644 board/keymile/km_arm/256M8-1.cfg
 create mode 100644 board/keymile/km_arm/fpga_config.c
 create mode 100644 board/keymile/km_arm/managed_switch.c
 delete mode 100644 include/configs/mgcoge3un.h
 delete mode 100644 include/configs/portl2.h

[U-Boot] [PATCH v2 01/19] arm/km: add board type to boards.cfg

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

Some other kirkwood boards from keymile will follow. They will have some
small differences, but we want to use the km_kirkwood.h for all to
distinguish them. This patch a preparation for this.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 boards.cfg                    |    4 ++--
 include/configs/km_kirkwood.h |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index ade2034..ccffd1a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -137,8 +137,8 @@ hawkboard_uart               arm         arm926ejs   da8xxevm            davinci
 enbw_cmc                     arm         arm926ejs   enbw_cmc            enbw           davinci
 calimain                     arm         arm926ejs   calimain            omicron        davinci
 dns325                       arm         arm926ejs   -                   d-link         kirkwood
-km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_DISABLE_PCI
-km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_RECONFIG_XLX
+km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
+km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index ed36124..f639edc 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -42,10 +42,10 @@
 /*
  * Version number information
  */
-#ifdef CONFIG_KM_DISABLE_PCI
+#if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_IDENT_STRING	"\nKeymile Kirkwood"
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
-#else
+#elif defined(CONFIG_KM_KIRKWOOD_PCI)
 #define CONFIG_IDENT_STRING	"\nKeymile Kirkwood PCI"
 #endif
 
-- 
1.7.1

[U-Boot] [PATCH v2 02/19] arm/km: add piggy mac adress offset for mgcoge3un

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

On mgcoge3un the piggy mac adress is at offset 3.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 include/configs/mgcoge3un.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h
index 797b0df..156821c 100644
--- a/include/configs/mgcoge3un.h
+++ b/include/configs/mgcoge3un.h
@@ -77,6 +77,7 @@
 	MVGBE_SET_MII_SPEED_TO_100)
 
 #define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
 
 /*
  * PCIe port not used on mgcoge3un
-- 
1.7.1

[U-Boot] [PATCH v2 03/19] arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

This config option sounds like the it is responsible for the
update of  the environment, but it is the u-boot update handling.
Therefore we adapt it to a more apropriate naming.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 include/configs/km/km_arm.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index c73a10c..e46b510 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -81,7 +81,7 @@
 	"boot=bootm ${load_addr_r} - -\0"				\
 	"cramfsloadfdt=true\0"						\
 	"u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0"			\
-	CONFIG_KM_DEF_ENV_UPDATE					\
+	CONFIG_KM_UPDATE_UBOOT						\
 	""
 
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
@@ -235,7 +235,7 @@ int get_scl(void);
 	"orion_nand:"							\
 		"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
 
-#define	CONFIG_KM_DEF_ENV_UPDATE					\
+#define	CONFIG_KM_UPDATE_UBOOT						\
 	"update="							\
 		"spi on;sf probe 0;sf erase 0 50000;"			\
 		"sf write ${load_addr_r} 0 ${filesize};"		\
-- 
1.7.1

[U-Boot] [PATCH v2 04/19] arm/km: use ARRAY_SIZE macro

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/km_arm.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 9e9940c..c6c9a71 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -410,7 +410,7 @@ const ulong patterns[]      = {	0x00000000,
 				0xFF00FF00,
 				0x0F0F0F0F,
 				0xF0F0F0F0};
-const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns);
+const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns);
 const ulong OFFS_PATTERN    = 3;
 const ulong REPEAT_PATTERN  = 1000;
 
-- 
1.7.1

[U-Boot] [PATCH v2 05/19] arm/km: fix wrong comment in SDRAM config for mgcoge3un

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/kwbimage-memphis.cfg |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg
index 2faaf2b..6df2ad7 100644
--- a/board/keymile/km_arm/kwbimage-memphis.cfg
+++ b/board/keymile/km_arm/kwbimage-memphis.cfg
@@ -149,7 +149,7 @@ DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
 DATA 0xFFD01428 0x00084520	# DDR2 SDRAM Timing Low
 # bit3-0  : 0000, required
 # bit7-4  : 0010, M_ODT assertion 2 cycles after read
-# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read
+# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
 # bit15-12: 0100, internal ODT assertion 4 cycles after read
 # bit19-16: 1000, internal ODT de-assertion 8 cycles after read
 # bit31-20: 0   , required
-- 
1.7.1

[U-Boot] [PATCH v2 06/19] arm/km: change maintainer for mgcoge3un

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Heiko Schocher <hs@denx.de>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 MAINTAINERS |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 46f63a0..652113f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -743,6 +743,7 @@ Sergey Lapin <slapin@ossfans.org>
 Valentin Longchamp <valentin.longchamp@keymile.com>
 
 	km_kirkwood	ARM926EJS (Kirkwood SoC)
+	mgcoge3un	ARM926EJS (Kirkwood SoC)
 	portl2		ARM926EJS (Kirkwood SoC)
 
 Nishanth Menon <nm@ti.com>
@@ -839,7 +840,6 @@ Heiko Schocher <hs@denx.de>
 
 	enbw_cmc	ARM926EJS (AM1808 SoC)
 	magnesium	i.MX27
-	mgcoge3un	ARM926EJS (Kirkwood SoC)
 
 Michael Schwingen <michael@schwingen.org>
 
-- 
1.7.1

[U-Boot] [PATCH v2 07/19] arm/km: remove CONFIG_RESET_PHY_R

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

This is already defined in the generic kirkwood header.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 include/configs/km/km_arm.h |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index e46b510..76666ef 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -164,7 +164,6 @@
 #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR	0
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R	/* use reset_phy() to init 88E1118 PHY */
 
 /*
  * UBI related stuff
-- 
1.7.1

[U-Boot] [PATCH v2 08/19] arm/km: enable mii cmd

[Valentin Longchamp]

This is useful to debug the switch initialization

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 include/configs/km/km_arm.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 76666ef..36eb765 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -159,6 +159,7 @@
  */
 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
 #define CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_CMD_MII		/* to debug mdio phy config */
 #define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
 #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
-- 
1.7.1

[U-Boot] [PATCH v2 09/19] arm/km: use correct kw_gpio function for NAND/SPI switching

[Valentin Longchamp]

This used to be done with registers direct access, which is not clear
and optimal.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/km_arm.c |   55 +++++++++++++++++++++--------------------
 include/configs/km/km_arm.h   |    2 +-
 2 files changed, 29 insertions(+), 28 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index c6c9a71..2507734 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -242,20 +242,15 @@ int misc_init_r(void)
 
 int board_early_init_f(void)
 {
-	u32 tmp;
-
 	kirkwood_mpp_conf(kwmpp_config);
 
 	/*
-	 * The FLASH_GPIO_PIN switches between using a
+	 * The KM_FLASH_GPIO_PIN switches between using a
 	 * NAND or a SPI FLASH. Set this pin on start
 	 * to NAND mode.
 	 */
-	tmp = readl(KW_GPIO0_BASE);
-	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-	tmp = readl(KW_GPIO0_BASE + 4);
-	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
-
+	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 #if defined(CONFIG_SOFT_I2C)
 	/* init the GPIO for I2C Bitbang driver */
 	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
@@ -284,35 +279,41 @@ int board_init(void)
 	return 0;
 }
 
+int km_hw_spi_bus_claim(int on)
+{
+	int gpio_value = !on;
+
+	if (on) {
+		kwmpp_config[0] = MPP0_SPI_SCn;
+		kwmpp_config[1] = MPP1_SPI_MOSI;
+		kwmpp_config[2] = MPP2_SPI_SCK;
+		kwmpp_config[3] = MPP3_SPI_MISO;
+	} else {
+		kwmpp_config[0] = MPP0_NF_IO2;
+		kwmpp_config[1] = MPP1_NF_IO3;
+		kwmpp_config[2] = MPP2_NF_IO4;
+		kwmpp_config[3] = MPP3_NF_IO5;
+	}
+
+	/* Multi-Purpose Pins Functionality configuration */
+	kirkwood_mpp_conf(kwmpp_config);
+	kw_gpio_set_value(KM_FLASH_GPIO_PIN, gpio_value);
+
+	return 0;
+}
+
 #if defined(CONFIG_CMD_SF)
 int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	u32 tmp;
 	if (argc < 2)
 		return cmd_usage(cmdtp);
 
 	if ((strcmp(argv[1], "off") == 0)) {
 		printf("SPI FLASH disabled, NAND enabled\n");
-		/* Multi-Purpose Pins Functionality configuration */
-		kwmpp_config[0] = MPP0_NF_IO2;
-		kwmpp_config[1] = MPP1_NF_IO3;
-		kwmpp_config[2] = MPP2_NF_IO4;
-		kwmpp_config[3] = MPP3_NF_IO5;
-
-		kirkwood_mpp_conf(kwmpp_config);
-		tmp = readl(KW_GPIO0_BASE);
-		writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
+		km_hw_spi_bus_claim(0);
 	} else if ((strcmp(argv[1], "on") == 0)) {
 		printf("SPI FLASH enabled, NAND disabled\n");
-		/* Multi-Purpose Pins Functionality configuration */
-		kwmpp_config[0] = MPP0_SPI_SCn;
-		kwmpp_config[1] = MPP1_SPI_MOSI;
-		kwmpp_config[2] = MPP2_SPI_SCK;
-		kwmpp_config[3] = MPP3_SPI_MISO;
-
-		kirkwood_mpp_conf(kwmpp_config);
-		tmp = readl(KW_GPIO0_BASE);
-		writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
+		km_hw_spi_bus_claim(1);
 	} else {
 		return cmd_usage(cmdtp);
 	}
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 36eb765..e2e8793 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -227,7 +227,7 @@ int get_scl(void);
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
 
-#define FLASH_GPIO_PIN			0x00010000
+#define KM_FLASH_GPIO_PIN	16
 
 #define MTDIDS_DEFAULT		"nand0=orion_nand"
 /* test-only: partitioning needs some tuning, this is just for tests */
-- 
1.7.1

[U-Boot] [PATCH v2 10/19] arm/km: implement weak function board_spi_clam_bus/release

[Valentin Longchamp]

They are needed on all km_arm boards where we have the environement
variables in the NOR Flash. This is #ifdefed by
CONFIG_KM_ENV_IS_IN_SPI_NOR. First boards using this feature are
the upcoming boards kmcoge5un and kmnusa.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/km_arm.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 2507734..dcecf83 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -33,6 +33,7 @@
 #include <nand.h>
 #include <netdev.h>
 #include <miiphy.h>
+#include <spi.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
@@ -302,6 +303,16 @@ int km_hw_spi_bus_claim(int on)
 	return 0;
 }
 
+int board_spi_claim_bus(struct spi_slave *slave)
+{
+	return km_hw_spi_bus_claim(1);
+}
+
+void board_spi_release_bus(struct spi_slave *slave)
+{
+	km_hw_spi_bus_claim(0);
+}
+
 #if defined(CONFIG_CMD_SF)
 int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-- 
1.7.1

[U-Boot] [PATCH v2 11/19] arm/kirkwood: protect the ENV_SPI #defines

[Valentin Longchamp]

So that they can be redefined by some boards specific values.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 arch/arm/include/asm/arch-kirkwood/config.h |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
index 91164eb..a9499b7 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -82,9 +82,15 @@
 #ifdef CONFIG_CMD_SF
 #define CONFIG_HARD_SPI			1
 #define CONFIG_KIRKWOOD_SPI		1
-#define CONFIG_ENV_SPI_BUS		0
-#define CONFIG_ENV_SPI_CS		0
-#define CONFIG_ENV_SPI_MAX_HZ		50000000	/*50Mhz */
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS		0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS		0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ		50000000
+#endif
 #endif
 
 /*
-- 
1.7.1

[U-Boot] [PATCH v2 12/19] km/arm: remove spi toggle command

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

Now we toggle between SPI and NAND flash automatically if
we claim the SPI bus. So we can get rid of this command.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/km_arm.c |   26 --------------------------
 include/configs/km/km_arm.h   |    5 ++---
 2 files changed, 2 insertions(+), 29 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index dcecf83..10c9a5f 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -313,32 +313,6 @@ void board_spi_release_bus(struct spi_slave *slave)
 	km_hw_spi_bus_claim(0);
 }
 
-#if defined(CONFIG_CMD_SF)
-int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	if ((strcmp(argv[1], "off") == 0)) {
-		printf("SPI FLASH disabled, NAND enabled\n");
-		km_hw_spi_bus_claim(0);
-	} else if ((strcmp(argv[1], "on") == 0)) {
-		printf("SPI FLASH enabled, NAND disabled\n");
-		km_hw_spi_bus_claim(1);
-	} else {
-		return cmd_usage(cmdtp);
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	spitoggle,	2,	0,	do_spi_toggle,
-	"En-/disable SPI FLASH access",
-	"<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
-	);
-#endif
-
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index e2e8793..edb8f4e 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -237,9 +237,8 @@ int get_scl(void);
 
 #define	CONFIG_KM_UPDATE_UBOOT						\
 	"update="							\
-		"spi on;sf probe 0;sf erase 0 50000;"			\
-		"sf write ${load_addr_r} 0 ${filesize};"		\
-		"spi off\0"
+		"sf probe 0;sf erase 0 50000;"				\
+		"sf write ${load_addr_r} 0 ${filesize};\0"
 
 /*
  * Default environment variables
-- 
1.7.1

[U-Boot] [PATCH v2 13/19] arm/km: add kmnusa board support

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

This board is similar to portl2, but it has the u-boot environment
in a SPI NOR flash and not in an i2c eeprom like portl2 have.

Some other details:
 - IVM EEPROM is at adress: pca9547:70:9
 - PCI is enabled
 - PIGGY4 is connected via MV88E6352 simple switch. There is no phy
   between the simple switch and the kirkwood.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 MAINTAINERS                       |    1 +
 board/keymile/km_arm/128M16-1.cfg |  290 +++++++++++++++++++++++++++++++++++++
 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 388 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

diff --git a/MAINTAINERS b/MAINTAINERS
index 652113f..ddf9613 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -743,6 +743,7 @@ Sergey Lapin <slapin@ossfans.org>
 Valentin Longchamp <valentin.longchamp@keymile.com>
 
 	km_kirkwood	ARM926EJS (Kirkwood SoC)
+	kmnusa		ARM926EJS (Kirkwood SoC)
 	mgcoge3un	ARM926EJS (Kirkwood SoC)
 	portl2		ARM926EJS (Kirkwood SoC)
 
diff --git a/board/keymile/km_arm/128M16-1.cfg b/board/keymile/km_arm/128M16-1.cfg
new file mode 100644
index 0000000..cef8ea6
--- /dev/null
+++ b/board/keymile/km_arm/128M16-1.cfg
@@ -0,0 +1,290 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs at denx.de.
+#
+# (C) Copyright 2012
+# Valentin Longchamp, Keymile AG, valentin.longchamp at keymile.com
+# Stefan Bigler, Keymile AG, stefan.bigler at keymile.com
+#
+# (C) Copyright 2012
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_SI   (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_SO   (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300	# MPP Control 1 Register
+# bit 3-0:   0, MPPSel8	 GPIO[8]
+# bit 7-4:   0, MPPSel9  GPIO[9]
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 UA1_TXD
+# bit 27-24: 3, MPPSel14 UA1_RXD
+# bit 31-28: 0, MPPSel15 GPIO[15]
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 12-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserve
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+# bit 15-0:  ???, Reserve
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ???,Reserve
+
+DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
+# bit 23-0:  0x000200, Addr Config tuning
+# bit 31-24: 0,        Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
+# bit 15-0:  0x1C00, Opmux Tuning
+# bit 31-16: 0,      Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+# bit 1-0:   1, addr clk tune
+# bit 3-2:   0, reserved
+# bit 5-4:   0, dtcmp clk tune
+# bit 7-6:   0, reserved
+# bit 9-8:   0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000	# DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for APX
+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
+# bit 30-28: 3, required
+# bit 31:    0,no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302444e	# DDR Timing (Low) (active cycles value +1)
+# bit 3-0:   0xE, TRAS, 15 clk (45 ns)
+# bit 7-4:   0x4, TRCD, 5 clk (15 ns)
+# bit 11-8:  0x4, TRP, 5 clk (15 ns)
+# bit 15-12: 0x4, TWR, 5 clk (15 ns)
+# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
+# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+
+DATA 0xFFD0140C 0x0000003e	#  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC, 63 clk (195 ns)
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000001	#  DDR Address Control
+# bit 1-0:    1, Cs0width=x16
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1,  DDR drive strength reduced
+# bit 2:      1,  DDR ODT control lsb, 75 ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75 ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for f > 266 MHz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00074510	# DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    1, M_ODT assertion 1 cycle after read
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT assertion
+# bit 19-16:  7, internal ODT de-assertion
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00007451	# DDR2 SDRAM Timing High
+# bit 3-0:    1, M_ODT assertion
+# bit 7-4:    5, M_ODT de-assertion
+# bit 11-8:   4, internal ODT assertion 1 cycles after write
+# bit 15-12:  7, internal ODT de-assertion 7 cycles after write
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     0, ODT1 controlled by register
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801	# CPU ODT Control
+# bit 3-0:     1, ODTRd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4:     0, ODTWr, Internal ODT not asserted during write to DRAM
+# bit 9-8:     0, ODTEn, controlled by ODTRd and ODTWr
+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 10c9a5f..ff57e60 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -134,10 +134,11 @@ int startup_allowed(void)
 }
 #endif
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
+	defined(CONFIG_KM_PIGGY4_88E6352))
 /*
- * These two boards have always ethernet present. Its connected to the mv
- * switch.
+ * All boards with PIGGY4 connected via a simple switch have ethernet always
+ * present.
  */
 int ethernet_present(void)
 {
@@ -367,7 +368,7 @@ void reset_phy(void)
 	/* reset the phy */
 	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 }
-#else
+#elif !defined(CONFIG_KM_PIGGY4_88E6352)
 /* Configure and enable MV88E1118 PHY on the piggy*/
 void reset_phy(void)
 {
diff --git a/boards.cfg b/boards.cfg
index ccffd1a..87246ac 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -139,6 +139,7 @@ calimain                     arm         arm926ejs   calimain            omicron
 dns325                       arm         arm926ejs   -                   d-link         kirkwood
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
+kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index edb8f4e..5f05e8f 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -57,6 +57,13 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SOFT_I2C		/* I2C bit-banged	*/
 
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		5000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_3
+#endif
+
 #include "asm/arch/config.h"
 
 #define CONFIG_SYS_TEXT_BASE	0x07d00000	/* code address before reloc */
@@ -211,6 +218,15 @@ int get_scl(void);
 /*
  *  Environment variables configurations
  */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH  /* use SPI-Flash for environment vars */
+#define CONFIG_ENV_OFFSET		0xc0000     /* no bracets! */
+#define CONFIG_ENV_SIZE			0x02000     /* Size of Environment */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_TOTAL_SIZE		0x20000     /* no bracets! */
+#else
 #define CONFIG_ENV_IS_IN_EEPROM		/* use EEPROM for environment vars */
 #define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
 #define CONFIG_ENV_EEPROM_IS_ON_I2C
@@ -218,11 +234,11 @@ int get_scl(void);
 #define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
 #define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
 #define CONFIG_I2C_ENV_EEPROM_BUS	KM_ENV_BUS "\0"
-
-/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
 #define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#endif
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
@@ -240,17 +256,27 @@ int get_scl(void);
 		"sf probe 0;sf erase 0 50000;"				\
 		"sf write ${load_addr_r} 0 ${filesize};\0"
 
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_KM_DEF_ENV						\
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " xstr(CONFIG_ENV_OFFSET) " "			\
+		xstr(CONFIG_ENV_TOTAL_SIZE)"\0"
+#else
+#define CONFIG_KM_NEW_ENV						\
 	"newenv=setenv addr 0x100000 && "				\
 		"i2c dev 1; mw.b ${addr} 0 4 && "			\
 		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
 		" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && "		\
 		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
-		" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"	\
+		" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"
+#endif
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_NEW_ENV						\
 	"arch=arm\0"							\
 	"EEprom_ivm=" KM_IVM_BUS "\0"					\
 	""
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index f639edc..97aa617 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -6,8 +6,9 @@
  * (C) Copyright 2009
  * Stefan Roese, DENX Software Engineering, sr at denx.de.
  *
- * (C) Copyright 2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck at keymile.de
+ * (C) Copyright 2011-2012
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck at keymile.com
+ * Valentin Longchamp, Keymile AG, valentin.longchamp at keymile.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -36,23 +37,67 @@
 #ifndef _CONFIG_KM_KIRKWOOD_H
 #define _CONFIG_KM_KIRKWOOD_H
 
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
 #if defined(CONFIG_KM_KIRKWOOD)
-#define CONFIG_IDENT_STRING	"\nKeymile Kirkwood"
+#define CONFIG_IDENT_STRING		"\nKeymile Kirkwood"
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
+#define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
-#define CONFIG_IDENT_STRING	"\nKeymile Kirkwood PCI"
+#define CONFIG_IDENT_STRING		"\nKeymile Kirkwood PCI"
+#define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
+/* KM_NUSA */
+#elif defined(CONFIG_KM_NUSA)
+#define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
+#define CONFIG_IDENT_STRING		"\nKeymile NUSA"
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+		$(SRCTREE)/$(CONFIG_BOARDDIR)/128M16-1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_FPGA_CONFIG
+#define CONFIG_KM_PIGGY4_88E6352
+
+#else
+#error ("Board unsupported")
 #endif
 
+/* include common defines/options for all arm based Keymile boards */
+#include "km/km_arm.h"
+
 #define CONFIG_HOSTNAME			km_kirkwood
 
-#define KM_IVM_BUS	"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
+#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define KM_ENV_BUS	"pca9544a:70:d"	/* I2C2 (Mux-Port 5)*/
+#endif
+
+#if defined(CONFIG_KM_PIGGY4_88E6352)
+/*
+ * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
+ * an Marvell 88E6352 simple switch.
+ * In this case we have to change the default settings for the etherent mac.
+ * There is NO ethernet phy. The ARM and Switch are conencted directly over
+ * RGMII in MAC-MAC mode
+ * In this case 1GBit full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE		( \
+	MVGBE_FORCE_LINK_PASS			    | \
+	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	MVGBE_ADV_NO_FLOW_CTRL			    | \
+	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	MVGBE_FORCE_BP_MODE_NO_JAM		    | \
+	(1 << 9) /* Reserved bit has to be 1 */	| \
+	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
+	MVGBE_DTE_ADV_0				        | \
+	MVGBE_MIIPHY_MAC_MODE			    | \
+	MVGBE_AUTO_NEG_NO_CHANGE		    | \
+	MVGBE_MAX_RX_PACKET_1552BYTE		| \
+	MVGBE_CLR_EXT_LOOPBACK			    | \
+	MVGBE_SET_FULL_DUPLEX_MODE		    | \
+	MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
+	MVGBE_SET_GMII_SPEED_TO_1000	    |\
+	MVGBE_SET_MII_SPEED_TO_100)
+
+#endif
 
 /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
 #define KM_XLX_PROGRAM_B_PIN    39
-- 
1.7.1

[U-Boot] [PATCH v3 13/19] arm/km: add kmnusa board support

[Holger Brunck]

This board is similar to portl2, but it has the u-boot environment
in a SPI NOR flash and not in an i2c eeprom like portl2 have.

Some other details:
 - IVM EEPROM is at adress: pca9547:70:9
 - PCI is enabled
 - PIGGY4 is connected via MV88E6352 simple switch. There is no phy
   between the simple switch and the kirkwood.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
Changes for v3:
  - fix ODT timings for 128M16 SDRAM config

 MAINTAINERS                       |    1 +
 board/keymile/km_arm/128M16-1.cfg |  294 +++++++++++++++++++++++++++++++++++++
 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 392 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

diff --git a/MAINTAINERS b/MAINTAINERS
index 2be0e6e..2e3c665 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -738,6 +738,7 @@ Sergey Lapin <slapin@ossfans.org>
 Valentin Longchamp <valentin.longchamp@keymile.com>
 
 	km_kirkwood	ARM926EJS (Kirkwood SoC)
+	kmnusa		ARM926EJS (Kirkwood SoC)
 	mgcoge3un	ARM926EJS (Kirkwood SoC)
 	portl2		ARM926EJS (Kirkwood SoC)
 
diff --git a/board/keymile/km_arm/128M16-1.cfg b/board/keymile/km_arm/128M16-1.cfg
new file mode 100644
index 0000000..bcce907
--- /dev/null
+++ b/board/keymile/km_arm/128M16-1.cfg
@@ -0,0 +1,294 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs at denx.de.
+#
+# (C) Copyright 2012
+# Valentin Longchamp, Keymile AG, valentin.longchamp at keymile.com
+# Stefan Bigler, Keymile AG, stefan.bigler at keymile.com
+#
+# (C) Copyright 2012
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_SI   (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_SO   (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300	# MPP Control 1 Register
+# bit 3-0:   0, MPPSel8	 GPIO[8]
+# bit 7-4:   0, MPPSel9  GPIO[9]
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 UA1_TXD
+# bit 27-24: 3, MPPSel14 UA1_RXD
+# bit 31-28: 0, MPPSel15 GPIO[15]
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 12-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserve
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+# bit 15-0:  ???, Reserve
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ???,Reserve
+
+DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
+# bit 23-0:  0x000200, Addr Config tuning
+# bit 31-24: 0,        Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
+# bit 15-0:  0x1C00, Opmux Tuning
+# bit 31-16: 0,      Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+# bit 1-0:   1, addr clk tune
+# bit 3-2:   0, reserved
+# bit 5-4:   0, dtcmp clk tune
+# bit 7-6:   0, reserved
+# bit 9-8:   0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000	# DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for APX
+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
+# bit 30-28: 3, required
+# bit 31:    0,no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302444e	# DDR Timing (Low) (active cycles value +1)
+# bit 3-0:   0xE, TRAS, 15 clk (45 ns)
+# bit 7-4:   0x4, TRCD, 5 clk (15 ns)
+# bit 11-8:  0x4, TRP, 5 clk (15 ns)
+# bit 15-12: 0x4, TWR, 5 clk (15 ns)
+# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
+# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+
+DATA 0xFFD0140C 0x0000003e	#  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC, 63 clk (195 ns)
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000001	#  DDR Address Control
+# bit 1-0:    1, Cs0width=x16
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1,  DDR drive strength reduced
+# bit 2:      1,  DDR ODT control lsb, 75 ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75 ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for f > 266 MHz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00084520	# DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start command
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT time based on bit 7-4
+#                with the considered SDRAM internal delay
+# bit 19-16:  8, internal ODT de-assertion based on bit 11-8
+#                with the considered SDRAM internal delay
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00008452	# DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   4, internal ODT assertion 2 cycles after write start command
+#                with the considered SDRAM internal delay
+# bit 15-12:  8, internal ODT de-assertion 5 cycles after write start command
+#                with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     0, ODT1 controlled by register
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801	# CPU ODT Control
+# bit 3-0:     1, ODTRd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4:     0, ODTWr, Internal ODT not asserted during write to DRAM
+# bit 9-8:     0, ODTEn, controlled by ODTRd and ODTWr
+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 10c9a5f..ff57e60 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -134,10 +134,11 @@ int startup_allowed(void)
 }
 #endif
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
+	defined(CONFIG_KM_PIGGY4_88E6352))
 /*
- * These two boards have always ethernet present. Its connected to the mv
- * switch.
+ * All boards with PIGGY4 connected via a simple switch have ethernet always
+ * present.
  */
 int ethernet_present(void)
 {
@@ -367,7 +368,7 @@ void reset_phy(void)
 	/* reset the phy */
 	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 }
-#else
+#elif !defined(CONFIG_KM_PIGGY4_88E6352)
 /* Configure and enable MV88E1118 PHY on the piggy*/
 void reset_phy(void)
 {
diff --git a/boards.cfg b/boards.cfg
index a015094..12de960 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -139,6 +139,7 @@ calimain                     arm         arm926ejs   calimain            omicron
 dns325                       arm         arm926ejs   -                   d-link         kirkwood
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
+kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index edb8f4e..5f05e8f 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -57,6 +57,13 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SOFT_I2C		/* I2C bit-banged	*/
 
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		5000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_3
+#endif
+
 #include "asm/arch/config.h"
 
 #define CONFIG_SYS_TEXT_BASE	0x07d00000	/* code address before reloc */
@@ -211,6 +218,15 @@ int get_scl(void);
 /*
  *  Environment variables configurations
  */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH  /* use SPI-Flash for environment vars */
+#define CONFIG_ENV_OFFSET		0xc0000     /* no bracets! */
+#define CONFIG_ENV_SIZE			0x02000     /* Size of Environment */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_TOTAL_SIZE		0x20000     /* no bracets! */
+#else
 #define CONFIG_ENV_IS_IN_EEPROM		/* use EEPROM for environment vars */
 #define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
 #define CONFIG_ENV_EEPROM_IS_ON_I2C
@@ -218,11 +234,11 @@ int get_scl(void);
 #define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
 #define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
 #define CONFIG_I2C_ENV_EEPROM_BUS	KM_ENV_BUS "\0"
-
-/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
 #define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#endif
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
@@ -240,17 +256,27 @@ int get_scl(void);
 		"sf probe 0;sf erase 0 50000;"				\
 		"sf write ${load_addr_r} 0 ${filesize};\0"
 
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_KM_DEF_ENV						\
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " xstr(CONFIG_ENV_OFFSET) " "			\
+		xstr(CONFIG_ENV_TOTAL_SIZE)"\0"
+#else
+#define CONFIG_KM_NEW_ENV						\
 	"newenv=setenv addr 0x100000 && "				\
 		"i2c dev 1; mw.b ${addr} 0 4 && "			\
 		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
 		" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && "		\
 		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
-		" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"	\
+		" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"
+#endif
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_NEW_ENV						\
 	"arch=arm\0"							\
 	"EEprom_ivm=" KM_IVM_BUS "\0"					\
 	""
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index f639edc..97aa617 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -6,8 +6,9 @@
  * (C) Copyright 2009
  * Stefan Roese, DENX Software Engineering, sr at denx.de.
  *
- * (C) Copyright 2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck at keymile.de
+ * (C) Copyright 2011-2012
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck at keymile.com
+ * Valentin Longchamp, Keymile AG, valentin.longchamp at keymile.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -36,23 +37,67 @@
 #ifndef _CONFIG_KM_KIRKWOOD_H
 #define _CONFIG_KM_KIRKWOOD_H
 
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
 #if defined(CONFIG_KM_KIRKWOOD)
-#define CONFIG_IDENT_STRING	"\nKeymile Kirkwood"
+#define CONFIG_IDENT_STRING		"\nKeymile Kirkwood"
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
+#define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
-#define CONFIG_IDENT_STRING	"\nKeymile Kirkwood PCI"
+#define CONFIG_IDENT_STRING		"\nKeymile Kirkwood PCI"
+#define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
+/* KM_NUSA */
+#elif defined(CONFIG_KM_NUSA)
+#define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
+#define CONFIG_IDENT_STRING		"\nKeymile NUSA"
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+		$(SRCTREE)/$(CONFIG_BOARDDIR)/128M16-1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_FPGA_CONFIG
+#define CONFIG_KM_PIGGY4_88E6352
+
+#else
+#error ("Board unsupported")
 #endif
 
+/* include common defines/options for all arm based Keymile boards */
+#include "km/km_arm.h"
+
 #define CONFIG_HOSTNAME			km_kirkwood
 
-#define KM_IVM_BUS	"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
+#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define KM_ENV_BUS	"pca9544a:70:d"	/* I2C2 (Mux-Port 5)*/
+#endif
+
+#if defined(CONFIG_KM_PIGGY4_88E6352)
+/*
+ * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
+ * an Marvell 88E6352 simple switch.
+ * In this case we have to change the default settings for the etherent mac.
+ * There is NO ethernet phy. The ARM and Switch are conencted directly over
+ * RGMII in MAC-MAC mode
+ * In this case 1GBit full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE		( \
+	MVGBE_FORCE_LINK_PASS			    | \
+	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	MVGBE_ADV_NO_FLOW_CTRL			    | \
+	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	MVGBE_FORCE_BP_MODE_NO_JAM		    | \
+	(1 << 9) /* Reserved bit has to be 1 */	| \
+	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
+	MVGBE_DTE_ADV_0				        | \
+	MVGBE_MIIPHY_MAC_MODE			    | \
+	MVGBE_AUTO_NEG_NO_CHANGE		    | \
+	MVGBE_MAX_RX_PACKET_1552BYTE		| \
+	MVGBE_CLR_EXT_LOOPBACK			    | \
+	MVGBE_SET_FULL_DUPLEX_MODE		    | \
+	MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
+	MVGBE_SET_GMII_SPEED_TO_1000	    |\
+	MVGBE_SET_MII_SPEED_TO_100)
+
+#endif
 
 /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
 #define KM_XLX_PROGRAM_B_PIN    39
-- 
1.7.1

[U-Boot] [PATCH v2 14/19] arm/km: add kmcoge5un board support

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

For u-boot this board is similar to mgcoge3un. But some differences
are present. We have a different SDRAM on it and therefore a new
SDRAM config file. Additionaly this board has a direct MAC/MAC
connection from the kirkwood to a marvell simple switch without a
phy inbetween, this needs a new configuration for the mvgbe driver.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 MAINTAINERS                      |    1 +
 board/keymile/km_arm/256M8-1.cfg |  292 ++++++++++++++++++++++++++++++++++++++
 boards.cfg                       |    1 +
 include/configs/km_kirkwood.h    |   16 ++-
 4 files changed, 308 insertions(+), 2 deletions(-)
 create mode 100644 board/keymile/km_arm/256M8-1.cfg

diff --git a/MAINTAINERS b/MAINTAINERS
index ddf9613..78a2fe1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -745,6 +745,7 @@ Valentin Longchamp <valentin.longchamp@keymile.com>
 	km_kirkwood	ARM926EJS (Kirkwood SoC)
 	kmnusa		ARM926EJS (Kirkwood SoC)
 	mgcoge3un	ARM926EJS (Kirkwood SoC)
+	kmcoge5un	ARM926EJS (Kirkwood SoC)
 	portl2		ARM926EJS (Kirkwood SoC)
 
 Nishanth Menon <nm@ti.com>
diff --git a/board/keymile/km_arm/256M8-1.cfg b/board/keymile/km_arm/256M8-1.cfg
new file mode 100644
index 0000000..0b19832
--- /dev/null
+++ b/board/keymile/km_arm/256M8-1.cfg
@@ -0,0 +1,292 @@
+#
+# (C) Copyright 2012
+# Stefan Bigler, Keymile AG, stefan.bigler at keymile.com
+# Norbert Mayer, Keymile AG, norbert.mayer at keymile.com
+# Deepak Patel, XENTECH Limited, deepak.patel at xentech.co.uk
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+# This configuration applies to COGE5 design (ARM-part)
+# Two 8-Bit devices are connected on the 16-Bit bus on the same
+# chip-select. The supported devices are
+#   MT47H256M8EB-3IT:C
+#   MT47H256M8EB-25EIT:C
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_MOSI (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_MISO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300	# MPP Control 1 Register
+# bit 3-0:   0, MPPSel8	 GPIO[8] CPU_SDA bitbanged
+# bit 7-4:   0, MPPSel9  GPIO[9] CPU_SCL bitbanged
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 GPIO[14]
+# bit 27-24: 3, MPPSel14 GPIO[15]
+# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 11-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserved
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+# bit 15-0:  ?, Reserved
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ?,Reserved
+
+DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
+# bit 23-0:  0x000200, Addr Config tuning
+# bit 31-24: 0,        Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
+# bit 15-0:  0x1C00, Opmux Tuning
+# bit 31-16: 0,      Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+# bit 1-0:   1, addr clk tune
+# bit 3-2:   0, reserved
+# bit 5-4:   0, dtcmp clk tune
+# bit 7-6:   0, reserved
+# bit 9-8:   0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000	# DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for APX
+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
+# bit 30-28: 3, required
+# bit 31:    0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202444E	# DDR Timing (Low) (active cycles value +1)
+# bit 3-0:   0xe, TRAS = 45ns -> 15 clk cycles
+# bit 7-4:   0x4, TRCD = 15ns -> 5 clk cycles
+# bit 11-8:  0x4, TRP = 15ns -> 5 clk cycles
+# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
+# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
+# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
+
+DATA 0xFFD0140C 0x0000003E	#  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC = 195ns -> 63 clk cycles
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000000	#  DDR Address Control
+# bit 1-0:    0, Cs0width=x8 (2 devices)
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1, DDR drive strenght reduced
+# bit 2:      1, DDR ODT control lsb, 75ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for > 266Mhz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00052520	# DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start command
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  2, internal ODT assertion same as bit 7-4
+# bit 19-16:  5, internal ODT de-assertion same as bit 11-8
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00005252	# DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   2, internal ODT assertion 2 cycles after write start command
+# bit 15-12:  5, internal ODT de-assertion 5 cycles after write start command
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x1FFFFFF1	# CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24:0x1F, Size (i.e. 512MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000004	#  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     1, ODT1 never active
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801	# CPU ODT Control
+# bit 3-0:     1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4:     0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
+# bit 9-8:     0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/boards.cfg b/boards.cfg
index 87246ac..c62be4a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -141,6 +141,7 @@ km_kirkwood                  arm         arm926ejs   km_arm              keymile
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
+kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KMCOGE5UN
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
 net2big_v2                   arm         arm926ejs   net2big_v2          LaCie          kirkwood	lacie_kw:NET2BIG_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 97aa617..e6f0e36 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -39,15 +39,18 @@
 
 #if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood"
+#define CONFIG_HOSTNAME			km_kirkwood
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
 #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood PCI"
+#define CONFIG_HOSTNAME			km_kirkwood_pci
 #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
 /* KM_NUSA */
 #elif defined(CONFIG_KM_NUSA)
 #define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
 #define CONFIG_IDENT_STRING		"\nKeymile NUSA"
+#define CONFIG_HOSTNAME			kmnusa
 #undef CONFIG_SYS_KWD_CONFIG
 #define CONFIG_SYS_KWD_CONFIG \
 		$(SRCTREE)/$(CONFIG_BOARDDIR)/128M16-1.cfg
@@ -55,6 +58,17 @@
 #define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_PIGGY4_88E6352
 
+#elif defined(CONFIG_KMCOGE5UN)
+#define CONFIG_IDENT_STRING		"\nKeymile COGE5UN"
+#define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
+#undef	CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+		$(SRCTREE)/$(CONFIG_BOARDDIR)/256M8-1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET	3
+#define CONFIG_HOSTNAME			kmcoge5un
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6352
 #else
 #error ("Board unsupported")
 #endif
@@ -62,8 +76,6 @@
 /* include common defines/options for all arm based Keymile boards */
 #include "km/km_arm.h"
 
-#define CONFIG_HOSTNAME			km_kirkwood
-
 #ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define KM_ENV_BUS	"pca9544a:70:d"	/* I2C2 (Mux-Port 5)*/
 #endif
-- 
1.7.1

[U-Boot] [PATCH v3 14/19] arm/km: add kmcoge5un board support

[Holger Brunck]

For u-boot this board is similar to mgcoge3un. But some differences
are present. We have a different SDRAM on it and therefore a new
SDRAM config file. Additionaly this board has a direct MAC/MAC
connection from the kirkwood to a marvell simple switch without a
phy inbetween, this needs a new configuration for the mvgbe driver.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
Changes for v3:
  - correct ODT timings for SDRAM.  The configuraion was not
    considering the SDRAM internal chip delay.

 MAINTAINERS                      |    1 +
 board/keymile/km_arm/256M8-1.cfg |  296 ++++++++++++++++++++++++++++++++++++++
 boards.cfg                       |    1 +
 include/configs/km_kirkwood.h    |   16 ++-
 4 files changed, 312 insertions(+), 2 deletions(-)
 create mode 100644 board/keymile/km_arm/256M8-1.cfg

diff --git a/MAINTAINERS b/MAINTAINERS
index 2e3c665..2bee4f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -740,6 +740,7 @@ Valentin Longchamp <valentin.longchamp@keymile.com>
 	km_kirkwood	ARM926EJS (Kirkwood SoC)
 	kmnusa		ARM926EJS (Kirkwood SoC)
 	mgcoge3un	ARM926EJS (Kirkwood SoC)
+	kmcoge5un	ARM926EJS (Kirkwood SoC)
 	portl2		ARM926EJS (Kirkwood SoC)
 
 Nishanth Menon <nm@ti.com>
diff --git a/board/keymile/km_arm/256M8-1.cfg b/board/keymile/km_arm/256M8-1.cfg
new file mode 100644
index 0000000..3e1237b
--- /dev/null
+++ b/board/keymile/km_arm/256M8-1.cfg
@@ -0,0 +1,296 @@
+#
+# (C) Copyright 2012
+# Stefan Bigler, Keymile AG, stefan.bigler at keymile.com
+# Norbert Mayer, Keymile AG, norbert.mayer at keymile.com
+# Deepak Patel, XENTECH Limited, deepak.patel at xentech.co.uk
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+# This configuration applies to COGE5 design (ARM-part)
+# Two 8-Bit devices are connected on the 16-Bit bus on the same
+# chip-select. The supported devices are
+#   MT47H256M8EB-3IT:C
+#   MT47H256M8EB-25EIT:C
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_MOSI (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_MISO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300	# MPP Control 1 Register
+# bit 3-0:   0, MPPSel8	 GPIO[8] CPU_SDA bitbanged
+# bit 7-4:   0, MPPSel9  GPIO[9] CPU_SCL bitbanged
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 GPIO[14]
+# bit 27-24: 3, MPPSel14 GPIO[15]
+# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 11-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserved
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+# bit 15-0:  ?, Reserved
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ?,Reserved
+
+DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
+# bit 23-0:  0x000200, Addr Config tuning
+# bit 31-24: 0,        Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
+# bit 15-0:  0x1C00, Opmux Tuning
+# bit 31-16: 0,      Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+# bit 1-0:   1, addr clk tune
+# bit 3-2:   0, reserved
+# bit 5-4:   0, dtcmp clk tune
+# bit 7-6:   0, reserved
+# bit 9-8:   0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000	# DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for APX
+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
+# bit 30-28: 3, required
+# bit 31:    0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202444E	# DDR Timing (Low) (active cycles value +1)
+# bit 3-0:   0xe, TRAS = 45ns -> 15 clk cycles
+# bit 7-4:   0x4, TRCD = 15ns -> 5 clk cycles
+# bit 11-8:  0x4, TRP = 15ns -> 5 clk cycles
+# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
+# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
+# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
+
+DATA 0xFFD0140C 0x0000003E	#  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC = 195ns -> 63 clk cycles
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000000	#  DDR Address Control
+# bit 1-0:    0, Cs0width=x8 (2 devices)
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1, DDR drive strenght reduced
+# bit 2:      1, DDR ODT control lsb, 75ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for > 266Mhz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00084520	# DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start command
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT time based on bit 7-4
+#                with the considered SDRAM internal delay
+# bit 19-16:  8, internal ODT de-assertion based on bit 11-8
+#                with the considered SDRAM internal delay
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00008452	# DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   4, internal ODT assertion 2 cycles after write start command
+#                with the considered SDRAM internal delay
+# bit 15-12:  8, internal ODT de-assertion 5 cycles after write start command
+#                with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x1FFFFFF1	# CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24:0x1F, Size (i.e. 512MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000004	#  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     1, ODT1 never active
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801	# CPU ODT Control
+# bit 3-0:     1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4:     0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
+# bit 9-8:     0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/boards.cfg b/boards.cfg
index 12de960..d903f03 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -141,6 +141,7 @@ km_kirkwood                  arm         arm926ejs   km_arm              keymile
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
+kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KMCOGE5UN
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
 net2big_v2                   arm         arm926ejs   net2big_v2          LaCie          kirkwood	lacie_kw:NET2BIG_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 97aa617..e6f0e36 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -39,15 +39,18 @@
 
 #if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood"
+#define CONFIG_HOSTNAME			km_kirkwood
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
 #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood PCI"
+#define CONFIG_HOSTNAME			km_kirkwood_pci
 #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
 /* KM_NUSA */
 #elif defined(CONFIG_KM_NUSA)
 #define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
 #define CONFIG_IDENT_STRING		"\nKeymile NUSA"
+#define CONFIG_HOSTNAME			kmnusa
 #undef CONFIG_SYS_KWD_CONFIG
 #define CONFIG_SYS_KWD_CONFIG \
 		$(SRCTREE)/$(CONFIG_BOARDDIR)/128M16-1.cfg
@@ -55,6 +58,17 @@
 #define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_PIGGY4_88E6352
 
+#elif defined(CONFIG_KMCOGE5UN)
+#define CONFIG_IDENT_STRING		"\nKeymile COGE5UN"
+#define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
+#undef	CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+		$(SRCTREE)/$(CONFIG_BOARDDIR)/256M8-1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET	3
+#define CONFIG_HOSTNAME			kmcoge5un
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6352
 #else
 #error ("Board unsupported")
 #endif
@@ -62,8 +76,6 @@
 /* include common defines/options for all arm based Keymile boards */
 #include "km/km_arm.h"
 
-#define CONFIG_HOSTNAME			km_kirkwood
-
 #ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define KM_ENV_BUS	"pca9544a:70:d"	/* I2C2 (Mux-Port 5)*/
 #endif
-- 
1.7.1

[U-Boot] [PATCH v2 15/19] arm/km: convert mgcoge3un target to km_kirkwood

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

Use the generic header km_kirkwood.h and get rid of the
board specific header.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/km_arm.c |    9 ++--
 boards.cfg                    |    2 +-
 include/configs/km_kirkwood.h |   46 +++++++++++++++++++++
 include/configs/mgcoge3un.h   |   87 -----------------------------------------
 4 files changed, 51 insertions(+), 93 deletions(-)
 delete mode 100644 include/configs/mgcoge3un.h

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index ff57e60..c948b13 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -114,7 +114,7 @@ u32 kwmpp_config[] = {
 	0
 };
 
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
 /*
  * Wait for startup OK from mgcoge3ne
  */
@@ -134,8 +134,7 @@ int startup_allowed(void)
 }
 #endif
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
-	defined(CONFIG_KM_PIGGY4_88E6352))
+#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
 /*
  * All boards with PIGGY4 connected via a simple switch have ethernet always
  * present.
@@ -203,7 +202,7 @@ int misc_init_r(void)
 		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
 		gd->bd->bi_arch_number = mach_type;
 	}
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
 	char *wait_for_ne;
 	wait_for_ne = getenv("waitforne");
 	if (wait_for_ne != NULL) {
@@ -334,7 +333,7 @@ void dram_init_banksize(void)
 	}
 }
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2))
 
 #define	PHY_LED_SEL	0x18
 #define PHY_LED0_LINK	(0x5)
diff --git a/boards.cfg b/boards.cfg
index c62be4a..867ac1c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -140,7 +140,7 @@ dns325                       arm         arm926ejs   -                   d-link
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
-mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
+mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_MGCOGE3UN
 kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KMCOGE5UN
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index e6f0e36..d1f3351 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -58,6 +58,20 @@
 #define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_PIGGY4_88E6352
 
+/* KM_MGCOGE3UN */
+#elif defined(CONFIG_KM_MGCOGE3UN)
+#define CONFIG_IDENT_STRING		"\nKeymile COGE3UN"
+#define CONFIG_HOSTNAME			mgcoge3un
+#define KM_IVM_BUS			"pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+#define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6061
+
+/* KMCOGE5UN */
 #elif defined(CONFIG_KMCOGE5UN)
 #define CONFIG_IDENT_STRING		"\nKeymile COGE5UN"
 #define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
@@ -111,7 +125,39 @@
 
 #endif
 
+#ifdef CONFIG_KM_PIGGY4_88E6061
+/*
+ * Some keymile boards like mgcoge3un have their PIGGY4 connected via
+ * an Marvell 88E6061 simple switch.
+ * In this case we have to change the default settings for the
+ * ethernet phy connected to the kirkwood.
+ * In this case 100MB full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE		( \
+	MVGBE_FORCE_LINK_PASS			| \
+	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	MVGBE_ADV_NO_FLOW_CTRL			| \
+	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	MVGBE_FORCE_BP_MODE_NO_JAM		| \
+	(1 << 9) /* Reserved bit has to be 1 */	| \
+	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
+	MVGBE_DTE_ADV_0				| \
+	MVGBE_MIIPHY_MAC_MODE			| \
+	MVGBE_AUTO_NEG_NO_CHANGE		| \
+	MVGBE_MAX_RX_PACKET_1552BYTE		| \
+	MVGBE_CLR_EXT_LOOPBACK			| \
+	MVGBE_SET_FULL_DUPLEX_MODE		| \
+	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
+	MVGBE_SET_GMII_SPEED_TO_10_100	|\
+	MVGBE_SET_MII_SPEED_TO_100)
+#endif
+
 /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
 #define KM_XLX_PROGRAM_B_PIN    39
 
+#ifdef CONFIG_KM_DISABLE_PCI
+#undef  CONFIG_KIRKWOOD_PCIE_INIT
+#endif
 #endif /* _CONFIG_KM_KIRKWOOD */
diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h
deleted file mode 100644
index 156821c..0000000
--- a/include/configs/mgcoge3un.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * (C) Copyright 2010-2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck at keymile.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* for linking errors see
- * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
-
-#ifndef _CONFIG_MGCOGE3UN_H
-#define _CONFIG_MGCOGE3UN_H
-
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING	"\nKeymile MGCOGE3UN"
-#define CONFIG_HOSTNAME		mgcoge3un
-#define CONFIG_MGCOGE3UN
-
-#define KM_IVM_BUS	"pca9547:70:9" /* I2C2 (Mux-Port 1)*/
-#define KM_ENV_BUS	"pca9547:70:d" /* I2C2 (Mux-Port 5)*/
-
-/* we use a new RAM type on mgcoge3un board */
-#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
-
-/*
- * mgcoge3un has a fixed link to the marvell switch
- * with 100MB full duplex and autoneg off, for this
- * reason we have to change the default settings
- */
-#define PORT_SERIAL_CONTROL_VALUE		( \
-	MVGBE_FORCE_LINK_PASS			| \
-	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
-	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
-	MVGBE_ADV_NO_FLOW_CTRL			| \
-	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
-	MVGBE_FORCE_BP_MODE_NO_JAM		| \
-	(1 << 9) /* Reserved bit has to be 1 */	| \
-	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
-	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
-	MVGBE_DTE_ADV_0				| \
-	MVGBE_MIIPHY_MAC_MODE			| \
-	MVGBE_AUTO_NEG_NO_CHANGE		| \
-	MVGBE_MAX_RX_PACKET_1552BYTE		| \
-	MVGBE_CLR_EXT_LOOPBACK			| \
-	MVGBE_SET_FULL_DUPLEX_MODE		| \
-	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
-	MVGBE_SET_GMII_SPEED_TO_10_100	|\
-	MVGBE_SET_MII_SPEED_TO_100)
-
-#define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
-#define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
-
-/*
- * PCIe port not used on mgcoge3un
- */
-#undef  CONFIG_KIRKWOOD_PCIE_INIT
-
-#endif /* _CONFIG_MGCOGE3UN_H */
-- 
1.7.1

[U-Boot] [PATCH v2 16/19] arm/km: remove portl2.h and use km_kirkwood instead

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

The additional headerfile is unneeded here, we can use the generic
km_kirkwood.h instead. And we can use the better config option
KM_PIGGY4_88E6061 for the specific features for boards with this
design in km_arm.c.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/km_arm.c |    2 +-
 boards.cfg                    |    2 +-
 include/configs/km_kirkwood.h |    8 ++++
 include/configs/portl2.h      |   85 -----------------------------------------
 4 files changed, 10 insertions(+), 87 deletions(-)
 delete mode 100644 include/configs/portl2.h

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index c948b13..4b83439 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -333,7 +333,7 @@ void dram_init_banksize(void)
 	}
 }
 
-#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_PIGGY4_88E6061))
 
 #define	PHY_LED_SEL	0x18
 #define PHY_LED0_LINK	(0x5)
diff --git a/boards.cfg b/boards.cfg
index 867ac1c..3db7b66 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -142,7 +142,7 @@ km_kirkwood_pci              arm         arm926ejs   km_arm              keymile
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_MGCOGE3UN
 kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KMCOGE5UN
-portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
+portl2                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_PORTL2
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
 net2big_v2                   arm         arm926ejs   net2big_v2          LaCie          kirkwood	lacie_kw:NET2BIG_V2
 netspace_max_v2              arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:NETSPACE_MAX_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index d1f3351..fbe714b 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -83,6 +83,14 @@
 #define CONFIG_HOSTNAME			kmcoge5un
 #define CONFIG_KM_DISABLE_PCIE
 #define CONFIG_KM_PIGGY4_88E6352
+
+/* KM_PORTL2 */
+#elif defined(CONFIG_KM_PORTL2)
+#define CONFIG_IDENT_STRING		"\nKeymile Port-L2"
+#define CONFIG_HOSTNAME			portl2
+#define KM_IVM_BUS			"pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_PIGGY4_88E6061
+
 #else
 #error ("Board unsupported")
 #endif
diff --git a/include/configs/portl2.h b/include/configs/portl2.h
deleted file mode 100644
index e436cfe..0000000
--- a/include/configs/portl2.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * (C) Copyright 2010-2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck at keymile.com.
- * Valentin Longchamp, Keymile AG Bern, valentin.longchamp at keymile.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* for linking errors see
- * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
-
-#ifndef _CONFIG_PORTL2_H
-#define _CONFIG_PORTL2_H
-
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING	"\nKeymile Port-L2"
-#define CONFIG_HOSTNAME			portl2
-#define CONFIG_PORTL2
-
-#define KM_IVM_BUS	"pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
-/*
- * Note: This is only valid for HW > P1A if you got an outdated P1A
- *       use KM_ENV_BUS  "pca9544a:70:a"
- */
-#define KM_ENV_BUS	"pca9544a:70:d"	/* I2C2 (Mux-Port 5)*/
-
-/*
- * portl2 has a fixed link to the XMPP backplane
- * with 100MB full duplex and autoneg off, for this
- * reason we have to change the default settings
- */
-#define PORT_SERIAL_CONTROL_VALUE		( \
-	MVGBE_FORCE_LINK_PASS			| \
-	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
-	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
-	MVGBE_ADV_NO_FLOW_CTRL			| \
-	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
-	MVGBE_FORCE_BP_MODE_NO_JAM		| \
-	(1 << 9) /* Reserved bit has to be 1 */	| \
-	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
-	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
-	MVGBE_DTE_ADV_0				| \
-	MVGBE_MIIPHY_MAC_MODE			| \
-	MVGBE_AUTO_NEG_NO_CHANGE		| \
-	MVGBE_MAX_RX_PACKET_1552BYTE		| \
-	MVGBE_CLR_EXT_LOOPBACK			| \
-	MVGBE_SET_FULL_DUPLEX_MODE		| \
-	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
-	MVGBE_SET_GMII_SPEED_TO_10_100	|\
-	MVGBE_SET_MII_SPEED_TO_100)
-
-/*
- * portl2 does use the PCIe Port0
- */
-#define  CONFIG_KIRKWOOD_PCIE_INIT
-
-#endif /* _CONFIG_PORTL2_H */
-- 
1.7.1

[U-Boot] [PATCH v2 17/19] arm/km: correct init of 88e6352 switch in the reset_phy function

[Valentin Longchamp]

This is achieved thanks to the support read/write regs for the external
88e6352 switch. The functions for this are added into an own file
managed_switch.c. This is compiled if the define CONFIG_KM_MANAGED_SW_ADDR
was set in the board setup. This define specifies the phy address.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/common/common.h         |    6 +
 board/keymile/km_arm/Makefile         |    4 +
 board/keymile/km_arm/km_arm.c         |   26 +++++-
 board/keymile/km_arm/managed_switch.c |  166 +++++++++++++++++++++++++++++++++
 include/configs/km_kirkwood.h         |   13 +++
 5 files changed, 214 insertions(+), 1 deletions(-)
 create mode 100644 board/keymile/km_arm/managed_switch.c

diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index 6c1f640..49225b8 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -125,6 +125,12 @@ struct bfticu_iomap {
 int ethernet_present(void);
 int ivm_read_eeprom(void);
 
+
+int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
+	u8 reg, u16 data);
+int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
+	u8 reg, u16 *data);
+
 int set_km_env(void);
 int fdt_set_node_and_value(void *blob,
 			char *nodename,
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index aa51255..06079e9 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -31,6 +31,10 @@ LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o ../common/common.o ../common/ivm.o
 
+ifdef CONFIG_KM_MANAGED_SW_ADDR
+COBJS	+= managed_switch.o
+endif
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 4b83439..f4be40f 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -9,6 +9,9 @@
  * (C) Copyright 2010
  * Heiko Schocher, DENX Software Engineering, hs at denx.de.
  *
+ * (C) Copyright 2011, 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longchamp at keymile.com
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -36,6 +39,7 @@
 #include <spi.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
+#include <asm/errno.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 
@@ -367,7 +371,27 @@ void reset_phy(void)
 	/* reset the phy */
 	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 }
-#elif !defined(CONFIG_KM_PIGGY4_88E6352)
+#elif defined(CONFIG_KM_PIGGY4_88E6352)
+
+#if defined(CONFIG_KM_MANAGED_SW_ADDR)
+void reset_phy(void)
+{
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* enable autoneg on port 0 phy */
+	ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 0, 0, 0x3300);
+
+	/* egress broadcast franes on all macs, with forwarding */
+	ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 16, 4, 0x000f);
+	ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 20, 4, 0x000f);
+	ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 21, 4, 0x000f);
+}
+#endif
+
+#else
 /* Configure and enable MV88E1118 PHY on the piggy*/
 void reset_phy(void)
 {
diff --git a/board/keymile/km_arm/managed_switch.c b/board/keymile/km_arm/managed_switch.c
new file mode 100644
index 0000000..482c18d
--- /dev/null
+++ b/board/keymile/km_arm/managed_switch.c
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longchamp at keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/errno.h>
+
+#define SMI_HDR		((0x8 | 0x1) << 12)
+#define SMI_BUSY_MASK	(0x8000)
+#define SMIRD_OP	(0x2 << 10)
+#define SMIWR_OP	(0x1 << 10)
+#define SMI_MASK	0x1f
+#define PORT_SHIFT	5
+
+#define COMMAND_REG	0
+#define DATA_REG	1
+
+static int ext_switch_wait_rdy(const char *devname, u8 phy_addr)
+{
+	u16 command;
+	u32 timeout = 100;
+	int ret;
+
+	/* wait till the SMI is not busy */
+	do {
+		/* read command register */
+		ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command);
+		if (ret < 0) {
+			printf("%s: Error reading command register\n",
+				__func__);
+			return ret;
+		}
+		if (timeout-- == 0) {
+			printf("Err..(%s) SMI busy timeout\n", __func__);
+			return -EFAULT;
+		}
+	} while (command & SMI_BUSY_MASK);
+
+	return 0;
+}
+
+int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
+	u8 reg, u16 *data)
+{
+	int ret;
+	u16 command;
+
+	ret = ext_switch_wait_rdy(devname, phy_addr);
+	if (ret)
+		return ret;
+
+	command = SMI_HDR | SMIRD_OP | ((port&SMI_MASK) << PORT_SHIFT) |
+			(reg & SMI_MASK);
+	debug("%s: write to command: %#x\n", __func__, command);
+	ret = miiphy_write(devname, phy_addr, COMMAND_REG, command);
+	if (ret)
+		return ret;
+
+	ret = ext_switch_wait_rdy(devname, phy_addr);
+	if (ret)
+		return ret;
+
+	ret = miiphy_read(devname, phy_addr, DATA_REG, data);
+
+	return ret;
+}
+
+int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
+	u8 reg, u16 data)
+{
+	int ret;
+	u16 value;
+
+	ret = ext_switch_wait_rdy(devname, phy_addr);
+	if (ret)
+		return ret;
+
+	debug("%s: write to data: %#x\n", __func__, data);
+	ret = miiphy_write(devname, phy_addr, DATA_REG, data);
+	if (ret)
+		return ret;
+
+	value = SMI_HDR | SMIWR_OP | ((port & SMI_MASK) << PORT_SHIFT) |
+			(reg & SMI_MASK);
+	debug("%s: write to command: %#x\n", __func__, value);
+	ret = miiphy_write(devname, phy_addr, COMMAND_REG, value);
+	if (ret)
+		return ret;
+
+	ret = ext_switch_wait_rdy(devname, phy_addr);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int do_sw_reg_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *name = "egiga0";
+	u16 value = 0, phyaddr, reg, port;
+	int ret;
+
+	if (argc < 4)
+		return cmd_usage(cmdtp);
+
+	phyaddr = simple_strtoul(argv[1], NULL, 16);
+	port = simple_strtoul(argv[2], NULL, 10);
+	reg = simple_strtoul(argv[3], NULL, 10);
+
+	ret = ext_switch_reg_read(name, phyaddr, port, reg, &value);
+	printf("%#x\n", value);
+
+	return ret;
+}
+
+U_BOOT_CMD(
+	sw_reg_read,	4,	1,	do_sw_reg_read,
+	"read the switch registers",
+	"<phyaddr> <port> <reg>\n"
+	);
+
+int do_sw_reg_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *name = "egiga0";
+	u16 value = 0, phyaddr, reg, port;
+	int ret;
+
+	if (argc < 5)
+		return cmd_usage(cmdtp);
+
+	phyaddr = simple_strtoul(argv[1], NULL, 16);
+	port = simple_strtoul(argv[2], NULL, 10);
+	reg = simple_strtoul(argv[3], NULL, 10);
+	value = simple_strtoul(argv[4], NULL, 16);
+
+	ret = ext_switch_reg_write(name, phyaddr, port, reg, value);
+
+	return ret;
+}
+
+U_BOOT_CMD(
+	sw_reg_write,	5,	1,	do_sw_reg_write,
+	"write the the switch registers",
+	"<phyaddr> <port> <reg> <value>\n"
+	);
+
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index fbe714b..059fdbc 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -58,6 +58,7 @@
 #define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_PIGGY4_88E6352
 
+#define CONFIG_KM_MANAGED_SW_ADDR	0x10
 /* KM_MGCOGE3UN */
 #elif defined(CONFIG_KM_MGCOGE3UN)
 #define CONFIG_IDENT_STRING		"\nKeymile COGE3UN"
@@ -131,6 +132,18 @@
 	MVGBE_SET_GMII_SPEED_TO_1000	    |\
 	MVGBE_SET_MII_SPEED_TO_100)
 
+/*
+ * There is no phy on the eth interface, but an external switch
+ * For kmcoge5un it is completely unmanaged, so we disable an access to it
+ * For km_nusa, we an MDIO(MII) interface that can configure the switch trough
+ * an indirect access, so we do not disable the MII
+ */
+#ifndef CONFIG_KM_MANAGED_SW_ADDR
+#undef CONFIG_MII
+#undef CONFIG_CMD_MII
+#undef CONFIG_RESET_PHY_R
+#endif
+
 #endif
 
 #ifdef CONFIG_KM_PIGGY4_88E6061
-- 
1.7.1

[U-Boot] [PATCH v2 18/19] arm/km: enable BOCO2 FPGA download support

[Valentin Longchamp]

This adds a first support of the FPGA download for a PCIe FPGA based
on the BOCO2 CPLD.

This takes place in 3 steps, all done accessing the SPICTRL reg of the
BOCO2:
1) start the FPGA config with an access to the FPGA_PROG bit
2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1
   for the end of the FPGA configuration (with a timeout)
3) reset the FPGA
4) finally remove the access to its config EEPROM from the FPGA so that
   the CPU can update the FPGA configuration when the kernel is running

The boards with a PCIe FPGA but without BOCO2 still are supported.

The config option name is CONFIG_KM_FPGA_CONFIG

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/common/common.h      |    6 +
 board/keymile/km_arm/Makefile      |    4 +
 board/keymile/km_arm/fpga_config.c |  212 ++++++++++++++++++++++++++++++++++++
 board/keymile/km_arm/km_arm.c      |   21 +++-
 boards.cfg                         |    2 +-
 include/configs/km/km_arm.h        |    3 +
 include/configs/km_kirkwood.h      |    8 +-
 7 files changed, 246 insertions(+), 10 deletions(-)
 create mode 100644 board/keymile/km_arm/fpga_config.c

diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index 49225b8..c58e565 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -131,6 +131,12 @@ int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
 int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
 	u8 reg, u16 *data);
 
+
+int trigger_fpga_config(void);
+int wait_for_fpga_config(void);
+int fpga_reset(void);
+int toggle_eeprom_spi_bus(void);
+
 int set_km_env(void);
 int fdt_set_node_and_value(void *blob,
 			char *nodename,
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index 06079e9..bd824e2 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -31,6 +31,10 @@ LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o ../common/common.o ../common/ivm.o
 
+ifdef CONFIG_KM_FPGA_CONFIG
+COBJS	+= fpga_config.o
+endif
+
 ifdef CONFIG_KM_MANAGED_SW_ADDR
 COBJS	+= managed_switch.o
 endif
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
new file mode 100644
index 0000000..4356b9a
--- /dev/null
+++ b/board/keymile/km_arm/fpga_config.c
@@ -0,0 +1,212 @@
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longchamp at keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
+
+/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
+#define KM_XLX_PROGRAM_B_PIN    39
+
+#define BOCO_ADDR	0x10
+
+#define ID_REG		0x00
+#define BOCO2_ID	0x5b
+
+static int check_boco2(void)
+{
+	int ret;
+	u8 id;
+
+	ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
+	if (ret) {
+		printf("%s: error reading the BOCO id !!\n", __func__);
+		return ret;
+	}
+
+	return (id == BOCO2_ID);
+}
+
+static int boco_clear_bits(u8 reg, u8 flags)
+{
+	int ret;
+	u8 regval;
+
+	/* give access to the EEPROM from FPGA */
+	ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error reading the BOCO @%#x !!\n",
+			__func__, reg);
+		return ret;
+	}
+	regval &= ~flags;
+	ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error writing the BOCO @%#x !!\n",
+			__func__, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int boco_set_bits(u8 reg, u8 flags)
+{
+	int ret;
+	u8 regval;
+
+	/* give access to the EEPROM from FPGA */
+	ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error reading the BOCO @%#x !!\n",
+			__func__, reg);
+		return ret;
+	}
+	regval |= flags;
+	ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error writing the BOCO @%#x !!\n",
+			__func__, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+#define SPI_REG		0x06
+#define CFG_EEPROM	0x02
+#define FPGA_PROG	0x04
+#define FPGA_DONE	0x20
+
+int trigger_fpga_config(void)
+{
+	int ret = 0;
+
+	if (check_boco2()) {
+		/* we have a BOCO2, this has to be triggered here */
+
+		/* make sure the FPGA_can access the EEPROM */
+		ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
+		if (ret)
+			return ret;
+
+		/* trigger the config start */
+		ret = boco_clear_bits(SPI_REG, FPGA_PROG);
+		if (ret)
+			return ret;
+
+		/* small delay for the pulse */
+		udelay(10);
+
+		/* up signal for pulse end */
+		ret = boco_set_bits(SPI_REG, FPGA_PROG);
+		if (ret)
+			return ret;
+
+	} else {
+		/* we do it the old way, with the gpio pin */
+		kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
+		kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
+		/* small delay for the pulse */
+		udelay(10);
+		kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+	}
+
+	return 0;
+}
+
+int wait_for_fpga_config(void)
+{
+	int ret = 0;
+	u8 spictrl;
+	u32 timeout = 20000;
+
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	printf("PCIe FPGA config:");
+	do {
+		ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);
+		if (ret) {
+			printf("%s: error reading the BOCO spictrl !!\n",
+				__func__);
+			return ret;
+		}
+		if (timeout-- == 0) {
+			printf(" FPGA_DONE timeout\n");
+			return -EFAULT;
+		}
+		udelay(10);
+	} while (!(spictrl & FPGA_DONE));
+
+	printf(" done\n");
+
+	return 0;
+}
+
+#define PRST1		0x4
+#define BRIDGE_RST	0x4
+
+int fpga_reset(void)
+{
+	int ret = 0;
+
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	ret = boco_clear_bits(PRST1, BRIDGE_RST);
+	if (ret)
+		return ret;
+
+	/* small delay for the pulse */
+	udelay(10);
+
+	ret = boco_set_bits(PRST1, BRIDGE_RST);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
+ * is available from the Bobcat SPI bus */
+int toggle_eeprom_spi_bus(void)
+{
+	int ret = 0;
+
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	ret = boco_set_bits(SPI_REG, CFG_EEPROM);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index f4be40f..3857c7d 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -267,12 +267,6 @@ int board_early_init_f(void)
 	kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
 	kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
 #endif
-#if defined(CONFIG_KM_RECONFIG_XLX)
-	/* trigger the reconfiguration of the xilinx fpga */
-	kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
-	kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
-	kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
-#endif
 	return 0;
 }
 
@@ -281,6 +275,21 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 
+#if defined(CONFIG_KM_FPGA_CONFIG)
+	trigger_fpga_config();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_KM_FPGA_CONFIG)
+	wait_for_fpga_config();
+	fpga_reset();
+	toggle_eeprom_spi_bus();
+#endif
+
 	return 0;
 }
 
diff --git a/boards.cfg b/boards.cfg
index 3db7b66..367647c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -138,7 +138,7 @@ enbw_cmc                     arm         arm926ejs   enbw_cmc            enbw
 calimain                     arm         arm926ejs   calimain            omicron        davinci
 dns325                       arm         arm926ejs   -                   d-link         kirkwood
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
-km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
+km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_MGCOGE3UN
 kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KMCOGE5UN
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 5f05e8f..18b114f 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -306,4 +306,7 @@ int get_scl(void);
 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
 #define CONFIG_CMD_DIAG
 
+/* we do the whole PCIe FPGA config stuff here */
+#define	BOARD_LATE_INIT
+
 #endif /* _CONFIG_KM_ARM_H */
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 059fdbc..7d38413 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -175,10 +175,12 @@
 	MVGBE_SET_MII_SPEED_TO_100)
 #endif
 
-/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
-#define KM_XLX_PROGRAM_B_PIN    39
-
 #ifdef CONFIG_KM_DISABLE_PCI
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
 #endif
+
+#ifndef CONFIG_KM_FPGA_CONFIG
+#undef  BOARD_LATE_INIT
+#endif
+
 #endif /* _CONFIG_KM_KIRKWOOD */
-- 
1.7.1

[U-Boot] [PATCH v2 19/19] arm/km: cleanup km_kirkwood boards

[Valentin Longchamp]

From: Holger Brunck <holger.brunck@keymile.com>

Remove config options from boards.cfg and simply add one switch
per board and differ afterwards in km_kirkwood.h between the features.
More boards are upcoming and therefore it's easier to have this
at one place.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 boards.cfg                    |    4 ++--
 include/configs/km_kirkwood.h |    7 ++++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index 367647c..48dbf1c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -137,8 +137,8 @@ hawkboard_uart               arm         arm926ejs   da8xxevm            davinci
 enbw_cmc                     arm         arm926ejs   enbw_cmc            enbw           davinci
 calimain                     arm         arm926ejs   calimain            omicron        davinci
 dns325                       arm         arm926ejs   -                   d-link         kirkwood
-km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
-km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG
+km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD
+km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_MGCOGE3UN
 kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KMCOGE5UN
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 7d38413..549122b 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -37,15 +37,20 @@
 #ifndef _CONFIG_KM_KIRKWOOD_H
 #define _CONFIG_KM_KIRKWOOD_H
 
+/* KM_KIRKWOOD */
 #if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood"
 #define CONFIG_HOSTNAME			km_kirkwood
-#undef  CONFIG_KIRKWOOD_PCIE_INIT
+#define CONFIG_KM_DISABLE_PCIE
 #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
+
+/* KM_KIRKWOOD_PCI */
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood PCI"
 #define CONFIG_HOSTNAME			km_kirkwood_pci
 #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_FPGA_CONFIG
+
 /* KM_NUSA */
 #elif defined(CONFIG_KM_NUSA)
 #define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
-- 
1.7.1

[U-Boot] [PATCH v2 00/19] updates for keymile arm boards

[Valentin Longchamp]

Prafulla,

On 03/26/2012 01:34 PM, Valentin Longchamp wrote:
> This patch series updates keymile boards with Kirkwood CPU and adds
> two new boards. This new boards are kmnusa and kmcoge5un. Also the
> existing boards with own config files were migrated to the common
> header km_kirkwood.h. Some small adaption in generic kirkwood code
> was needed due to two new features on the new board. First one is
> that the u-boot environment is in the SPI NOR flash and the second one
> is the direct MAC/MAC connection from the mvgbe interface to an
> simple switch.
> 
> Changes for v2:
> 	- removed the two patches "spi/kirkwood: add weak functions
> 	board_spi_bus_claim/release" and "mvgbe: remove warning for
> 	unused methods" from the series as they are were independent from
> 	it. The series is however dependent of these two patches.
> 
> Holger Brunck (13):
>   arm/km: add board type to boards.cfg
>   arm/km: add piggy mac adress offset for mgcoge3un
>   arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
>   arm/km: use ARRAY_SIZE macro
>   arm/km: fix wrong comment in SDRAM config for mgcoge3un
>   arm/km: change maintainer for mgcoge3un
>   arm/km: remove CONFIG_RESET_PHY_R
>   km/arm: remove spi toggle command
>   arm/km: add kmnusa board support
>   arm/km: add kmcoge5un board support
>   arm/km: convert mgcoge3un target to km_kirkwood
>   arm/km: remove portl2.h and use km_kirkwood instead
>   arm/km: cleanup km_kirkwood boards
> 
> Valentin Longchamp (6):
>   arm/km: enable mii cmd
>   arm/km: use correct kw_gpio function for NAND/SPI switching
>   arm/km: implement weak function board_spi_clam_bus/release
>   arm/kirkwood: protect the ENV_SPI #defines
>   arm/km: correct init of 88e6352 switch in the reset_phy function
>   arm/km: enable BOCO2 FPGA download support
> 
>  MAINTAINERS                                 |    4 +-
>  arch/arm/include/asm/arch-kirkwood/config.h |   12 +-
>  board/keymile/common/common.h               |   12 +
>  board/keymile/km_arm/128M16-1.cfg           |  290 ++++++++++++++++++++++++++
>  board/keymile/km_arm/256M8-1.cfg            |  292 +++++++++++++++++++++++++++
>  board/keymile/km_arm/Makefile               |    8 +
>  board/keymile/km_arm/fpga_config.c          |  212 +++++++++++++++++++
>  board/keymile/km_arm/km_arm.c               |  119 +++++++-----
>  board/keymile/km_arm/kwbimage-memphis.cfg   |    2 +-
>  board/keymile/km_arm/managed_switch.c       |  166 +++++++++++++++
>  boards.cfg                                  |   10 +-
>  include/configs/km/km_arm.h                 |   60 ++++--
>  include/configs/km_kirkwood.h               |  157 +++++++++++++--
>  include/configs/mgcoge3un.h                 |   86 --------
>  include/configs/portl2.h                    |   85 --------
>  15 files changed, 1256 insertions(+), 259 deletions(-)
>  create mode 100644 board/keymile/km_arm/128M16-1.cfg
>  create mode 100644 board/keymile/km_arm/256M8-1.cfg
>  create mode 100644 board/keymile/km_arm/fpga_config.c
>  create mode 100644 board/keymile/km_arm/managed_switch.c
>  delete mode 100644 include/configs/mgcoge3un.h
>  delete mode 100644 include/configs/portl2.h
> 

We would love to get a feedback from you about this series. The merge window for
2012.06 is soon over and we would like to see these in the marvell tree before
your pull request for this merge window (I guess you have a pull request planned
for the current merge window ?)

Best Regards

-- 
Valentin Longchamp
Embedded Software Engineer
Hardware and Chip Integration
______________________________________
KEYMILE AG
Schwarzenburgstr. 73
CH-3097 Liebefeld
Phone +41 31 377 1318
Fax   +41 31 377 1212
valentin.longchamp at keymile.com
www.keymile.com
______________________________________
KEYMILE: A Specialist as a Partner

[U-Boot] [PATCH v2 00/19] updates for keymile arm boards

[Prafulla Wadaskar]

> -----Original Message-----
> From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
> Sent: 27 March 2012 19:02
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de
> Subject: Re: [PATCH v2 00/19] updates for keymile arm boards
> 
> Prafulla,
> 
> On 03/26/2012 01:34 PM, Valentin Longchamp wrote:
> > This patch series updates keymile boards with Kirkwood CPU and adds
> > two new boards. This new boards are kmnusa and kmcoge5un. Also the
> > existing boards with own config files were migrated to the common
> > header km_kirkwood.h. Some small adaption in generic kirkwood code
> > was needed due to two new features on the new board. First one is
> > that the u-boot environment is in the SPI NOR flash and the second
> one
> > is the direct MAC/MAC connection from the mvgbe interface to an
> > simple switch.
> >
> > Changes for v2:
> > 	- removed the two patches "spi/kirkwood: add weak functions
> > 	board_spi_bus_claim/release" and "mvgbe: remove warning for
> > 	unused methods" from the series as they are were independent from
> > 	it. The series is however dependent of these two patches.
> >
> > Holger Brunck (13):
> >   arm/km: add board type to boards.cfg
> >   arm/km: add piggy mac adress offset for mgcoge3un
> >   arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
> >   arm/km: use ARRAY_SIZE macro
> >   arm/km: fix wrong comment in SDRAM config for mgcoge3un
> >   arm/km: change maintainer for mgcoge3un
> >   arm/km: remove CONFIG_RESET_PHY_R
> >   km/arm: remove spi toggle command
> >   arm/km: add kmnusa board support
> >   arm/km: add kmcoge5un board support
> >   arm/km: convert mgcoge3un target to km_kirkwood
> >   arm/km: remove portl2.h and use km_kirkwood instead
> >   arm/km: cleanup km_kirkwood boards
> >
> > Valentin Longchamp (6):
> >   arm/km: enable mii cmd
> >   arm/km: use correct kw_gpio function for NAND/SPI switching
> >   arm/km: implement weak function board_spi_clam_bus/release
> >   arm/kirkwood: protect the ENV_SPI #defines
> >   arm/km: correct init of 88e6352 switch in the reset_phy function
> >   arm/km: enable BOCO2 FPGA download support
> >
> >  MAINTAINERS                                 |    4 +-
> >  arch/arm/include/asm/arch-kirkwood/config.h |   12 +-
> >  board/keymile/common/common.h               |   12 +
> >  board/keymile/km_arm/128M16-1.cfg           |  290
> ++++++++++++++++++++++++++
> >  board/keymile/km_arm/256M8-1.cfg            |  292
> +++++++++++++++++++++++++++
> >  board/keymile/km_arm/Makefile               |    8 +
> >  board/keymile/km_arm/fpga_config.c          |  212
> +++++++++++++++++++
> >  board/keymile/km_arm/km_arm.c               |  119 +++++++-----
> >  board/keymile/km_arm/kwbimage-memphis.cfg   |    2 +-
> >  board/keymile/km_arm/managed_switch.c       |  166 +++++++++++++++
> >  boards.cfg                                  |   10 +-
> >  include/configs/km/km_arm.h                 |   60 ++++--
> >  include/configs/km_kirkwood.h               |  157 +++++++++++++--
> >  include/configs/mgcoge3un.h                 |   86 --------
> >  include/configs/portl2.h                    |   85 --------
> >  15 files changed, 1256 insertions(+), 259 deletions(-)
> >  create mode 100644 board/keymile/km_arm/128M16-1.cfg
> >  create mode 100644 board/keymile/km_arm/256M8-1.cfg
> >  create mode 100644 board/keymile/km_arm/fpga_config.c
> >  create mode 100644 board/keymile/km_arm/managed_switch.c
> >  delete mode 100644 include/configs/mgcoge3un.h
> >  delete mode 100644 include/configs/portl2.h
> >
> 
> We would love to get a feedback from you about this series. The merge
> window for
> 2012.06 is soon over and we would like to see these in the marvell
> tree before
> your pull request for this merge window (I guess you have a pull
> request planned
> for the current merge window ?)

Since you have posted patched within/before merge window closure, those are eligible to go on master branch.
So don't worry, I will review them.

Regards..
Prafulla . . .
 
> 
> Best Regards
> 
> --
> Valentin Longchamp
> Embedded Software Engineer
> Hardware and Chip Integration
> ______________________________________
> KEYMILE AG
> Schwarzenburgstr. 73
> CH-3097 Liebefeld
> Phone +41 31 377 1318
> Fax   +41 31 377 1212
> valentin.longchamp at keymile.com
> www.keymile.com
> ______________________________________
> KEYMILE: A Specialist as a Partner