[PATCH] drm/i915: Sanitize BIOS debugging bits from PIPECONF

[PATCH] drm/i915: Sanitize BIOS debugging bits from PIPECONF

[Chris Wilson]

Quoting the BSpec from time immemorial:

  PIPEACONF, bits 28:27: Frame Start Delay (Debug)

  Used to delay the frame start signal that is sent to the display planes.
  Care must be taken to insure that there are enough lines during VBLANK
  to support this setting.

An instance of the BIOS leaving these bits set was found in the wild,
where it caused our modesetting to go all squiffy and skewiff.

References: https://bugs.freedesktop.org/show_bug.cgi?id=47271
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |    6 ++++++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f59cd3a..e65fb20 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2385,6 +2385,7 @@
 #define   PIPECONF_DISABLE	0
 #define   PIPECONF_DOUBLE_WIDE	(1<<30)
 #define   I965_PIPECONF_ACTIVE	(1<<30)
+#define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
 #define   PIPECONF_SINGLE_WIDE	0
 #define   PIPECONF_PIPE_UNLOCKED 0
 #define   PIPECONF_PIPE_LOCKED	(1<<25)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2942e02..7ea5d4d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7673,6 +7673,12 @@ static void intel_sanitize_modesetting(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 reg, val;
 
+	/* Clear any frame start delays used for debugging left by the BIOS */
+	for_each_pipe(pipe) {
+		reg = PIPECONF(pipe);
+		I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
+	}
+
 	if (HAS_PCH_SPLIT(dev))
 		return;
 
-- 
1.7.9.1

Re: [PATCH] drm/i915: Sanitize BIOS debugging bits from PIPECONF

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 810 bytes --]

On Thu, Mar 22, 2012 at 12:00, Chris Wilson <chris@chris-wilson.co.uk>wrote:

> Quoting the BSpec from time immemorial:
>
>  PIPEACONF, bits 28:27: Frame Start Delay (Debug)
>
>  Used to delay the frame start signal that is sent to the display planes.
>  Care must be taken to insure that there are enough lines during VBLANK
>  to support this setting.
>
> An instance of the BIOS leaving these bits set was found in the wild,
> where it caused our modesetting to go all squiffy and skewiff.
>

Just complementing Chris patch and calling for some testing in the wild...

For the ones affected by the latest VBIOS update on Ivy Bridge which
resulted in somewhat strange display issues, could you please test this
patch and verify if it fixes the issue for you?

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

[-- Attachment #1.2: Type: text/html, Size: 1177 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: Sanitize BIOS debugging bits from PIPECONF

[Chris Wilson]

On Thu, 22 Mar 2012 15:00:50 +0000, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Quoting the BSpec from time immemorial:
> 
>   PIPEACONF, bits 28:27: Frame Start Delay (Debug)
> 
>   Used to delay the frame start signal that is sent to the display planes.
>   Care must be taken to insure that there are enough lines during VBLANK
>   to support this setting.
> 
> An instance of the BIOS leaving these bits set was found in the wild,
> where it caused our modesetting to go all squiffy and skewiff.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=47271
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: stable@kernel.org

Reported-and-tested-by: Carl Richell <carl@system76.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43012
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre