* [PATCH 2/5] MIPS: Clean-up GIC and vectored interrupts.
@ 2012-04-06 17:59 Steven J. Hill
2012-05-30 8:48 ` Ralf Baechle
0 siblings, 1 reply; 2+ messages in thread
From: Steven J. Hill @ 2012-04-06 17:59 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: Steven J. Hill, sjhill
From: "Steven J. Hill" <sjhill@mips.com>
This change adds macros for routing of GIC interrupts for EIC and
non-EIC hardware modes. Also added Malta GIC macros having to do
with performance and timer interrupts.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
arch/mips/include/asm/gic.h | 15 ++++++++++++++-
arch/mips/include/asm/irq.h | 1 +
arch/mips/include/asm/mips-boards/maltaint.h | 10 ++++++++++
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 86548da..991b659 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -206,7 +206,7 @@
#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
#define GIC_VPE_EIC_SS(intr) \
- (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
+ (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))
#define GIC_VPE_EIC_VEC_BASE 0x0800
#define GIC_VPE_EIC_VEC(intr) \
@@ -330,6 +330,17 @@ struct gic_intr_map {
#define GIC_FLAG_TRANSPARENT 0x02
};
+/*
+ * This is only used in EIC mode. This helps to figure out which
+ * shared interrupts we need to process when we get a vector interrupt.
+ */
+#define GIC_MAX_SHARED_INTR 0x5
+struct gic_shared_intr_map {
+ unsigned int num_shared_intr;
+ unsigned int intr_list[GIC_MAX_SHARED_INTR];
+ unsigned int local_intr_mask;
+};
+
extern void gic_init(unsigned long gic_base_addr,
unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
unsigned int intrmap_size, unsigned int irqbase);
@@ -338,5 +349,7 @@ extern unsigned int gic_get_int(void);
extern void gic_send_ipi(unsigned int intr);
extern unsigned int plat_ipi_call_int_xlate(unsigned int);
extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
+extern void gic_bind_eic_interrupt(int irq, int set);
+extern unsigned int gic_get_timer_pending(void);
#endif /* _ASM_GICREGS_H */
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index fb698dc..78dbb8a 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq);
* IE7. Since R2 their number has to be read from the c0_intctl register.
*/
#define CP0_LEGACY_COMPARE_IRQ 7
+#define CP0_LEGACY_PERFCNT_IRQ 7
extern int cp0_compare_irq;
extern int cp0_compare_irq_shift;
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index d11aa02..5447d9f 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -86,6 +86,16 @@
#define GIC_CPU_INT4 4 /* . */
#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
+/* MALTA GIC local interrupts */
+#define GIC_INT_TMR (GIC_CPU_INT5)
+#define GIC_INT_PERFCTR (GIC_CPU_INT5)
+
+/* GIC constants */
+/* Add 2 to convert non-eic hw int # to eic vector # */
+#define GIC_CPU_TO_VEC_OFFSET (2)
+/* If we map an intr to pin X, GIC will actually generate vector X+1 */
+#define GIC_PIN_TO_VEC_OFFSET (1)
+
#define GIC_EXT_INTR(x) x
/* External Interrupts used for IPI */
--
1.7.9.6
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 2/5] MIPS: Clean-up GIC and vectored interrupts.
2012-04-06 17:59 [PATCH 2/5] MIPS: Clean-up GIC and vectored interrupts Steven J. Hill
@ 2012-05-30 8:48 ` Ralf Baechle
0 siblings, 0 replies; 2+ messages in thread
From: Ralf Baechle @ 2012-05-30 8:48 UTC (permalink / raw)
To: Steven J. Hill; +Cc: linux-mips, sjhill
On Fri, Apr 06, 2012 at 12:59:00PM -0500, Steven J. Hill wrote:
> From: "Steven J. Hill" <sjhill@mips.com>
>
> This change adds macros for routing of GIC interrupts for EIC and
> non-EIC hardware modes. Also added Malta GIC macros having to do
> with performance and timer interrupts.
>
> Signed-off-by: Steven J. Hill <sjhill@mips.com>
> diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
> index fb698dc..78dbb8a 100644
> --- a/arch/mips/include/asm/irq.h
> +++ b/arch/mips/include/asm/irq.h
> @@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq);
> * IE7. Since R2 their number has to be read from the c0_intctl register.
> */
> #define CP0_LEGACY_COMPARE_IRQ 7
> +#define CP0_LEGACY_PERFCNT_IRQ 7
>
> extern int cp0_compare_irq;
> extern int cp0_compare_irq_shift;
I split of this segment into a separate commit because it appeared to
be unrelated to the rest of the patch and also made use of the symbol
in traps.c.
Thanks,
Ralf
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2012-05-30 8:48 ` Ralf Baechle
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