* [PATCH] drm/i915: re-run init_clock_gating after gpu reset
@ 2012-04-10 12:39 Daniel Vetter
2012-04-10 12:53 ` Chris Wilson
0 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2012-04-10 12:39 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Over time we've added more and more workarounds in there for render
core issues, so these register settings will revert back to their
reset state. To avoid making a bad situation worse, re-run the clock
gating code after reset so that we don't crash right away with a known
hw issue.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 96f8efc..aafb942 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -850,6 +850,9 @@ int i915_reset(struct drm_device *dev, u8 flags)
i915_gem_init_ppgtt(dev);
+ /* Clock gating also touches registers in the GT core. */
+ intel_init_clock_gating(dev);
+
mutex_unlock(&dev->struct_mutex);
drm_irq_uninstall(dev);
drm_mode_config_reset(dev);
--
1.7.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: re-run init_clock_gating after gpu reset
2012-04-10 12:39 [PATCH] drm/i915: re-run init_clock_gating after gpu reset Daniel Vetter
@ 2012-04-10 12:53 ` Chris Wilson
2012-04-10 13:46 ` [PATCH] drm/i915: re-init modeset hw state " Daniel Vetter
0 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2012-04-10 12:53 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
On Tue, 10 Apr 2012 14:39:49 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Over time we've added more and more workarounds in there for render
> core issues, so these register settings will revert back to their
> reset state. To avoid making a bad situation worse, re-run the clock
> gating code after reset so that we don't crash right away with a known
> hw issue.
>
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This shouldn't do any harm whilst we do a full modeset afterwards.
However, we also need to reset rc6 and contexts.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] drm/i915: re-init modeset hw state after gpu reset
2012-04-10 12:53 ` Chris Wilson
@ 2012-04-10 13:46 ` Daniel Vetter
2012-04-10 13:50 ` Daniel Vetter
0 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2012-04-10 13:46 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
After a gpu reset we need to re-init some of the hw state we only
initialize when modeset is enabled, like rc6, hw contexts or render/GT
core clock gating and workaround register settings.
Note that this patch has a small change in the resume code:
- rc6 on gen6+ is only restored for the modeset case (for more
consistency with other callsites). This is no problem because recent
kernels refuse to load drm/i915 without kms on gen6+
- rc6/emon on ilk is only restored for the modeset case. This is no
problem because rc6 is disabled by default on ilk, and ums on ilk
has never really been a supported option outside of horrible rhel
backports.
v2: Chris Wilson noticed that we not only fail to restore the clock
gating settings after gpu reset.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_suspend.c | 12 +-----------
drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++-----------
4 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 96f8efc..32049a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -850,6 +850,9 @@ int i915_reset(struct drm_device *dev, u8 flags)
i915_gem_init_ppgtt(dev);
+ if (drm_core_check_feature(dev, DRIVER_MODESET))
+ intel_modeset_init_hw(dev);
+
mutex_unlock(&dev->struct_mutex);
drm_irq_uninstall(dev);
drm_mode_config_reset(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7dcdccb..ed2d235 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1429,6 +1429,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */
/* modesetting */
+extern void intel_modeset_init_hw(struct drm_device *dev);
extern void intel_modeset_init(struct drm_device *dev);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 2b5eb22..0c3e3bf 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -879,17 +879,7 @@ int i915_restore_state(struct drm_device *dev)
mutex_unlock(&dev->struct_mutex);
if (drm_core_check_feature(dev, DRIVER_MODESET))
- intel_init_clock_gating(dev);
-
- if (IS_IRONLAKE_M(dev)) {
- ironlake_enable_drps(dev);
- intel_init_emon(dev);
- }
-
- if (INTEL_INFO(dev)->gen >= 6) {
- gen6_enable_rps(dev_priv);
- gen6_update_ring_freq(dev_priv);
- }
+ intel_modeset_init_hw(dev);
mutex_lock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 42dbe14..a1f2d19 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9532,6 +9532,23 @@ static void i915_disable_vga(struct drm_device *dev)
POSTING_READ(vga_reg);
}
+void intel_modeset_init_hw(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ intel_init_clock_gating(dev);
+
+ if (IS_IRONLAKE_M(dev)) {
+ ironlake_enable_drps(dev);
+ intel_init_emon(dev);
+ }
+
+ if (IS_GEN6(dev) || IS_GEN7(dev)) {
+ gen6_enable_rps(dev_priv);
+ gen6_update_ring_freq(dev_priv);
+ }
+}
+
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -9577,17 +9594,7 @@ void intel_modeset_init(struct drm_device *dev)
i915_disable_vga(dev);
intel_setup_outputs(dev);
- intel_init_clock_gating(dev);
-
- if (IS_IRONLAKE_M(dev)) {
- ironlake_enable_drps(dev);
- intel_init_emon(dev);
- }
-
- if (IS_GEN6(dev) || IS_GEN7(dev)) {
- gen6_enable_rps(dev_priv);
- gen6_update_ring_freq(dev_priv);
- }
+ intel_modeset_init_hw(dev);
INIT_WORK(&dev_priv->idle_work, intel_idle_update);
setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
--
1.7.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] drm/i915: re-init modeset hw state after gpu reset
2012-04-10 13:46 ` [PATCH] drm/i915: re-init modeset hw state " Daniel Vetter
@ 2012-04-10 13:50 ` Daniel Vetter
2012-04-10 14:10 ` Chris Wilson
0 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2012-04-10 13:50 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
After a gpu reset we need to re-init some of the hw state we only
initialize when modeset is enabled, like rc6, hw contexts or render/GT
core clock gating and workaround register settings.
Note that this patch has a small change in the resume code:
- rc6 on gen6+ is only restored for the modeset case (for more
consistency with other callsites). This is no problem because recent
kernels refuse to load drm/i915 without kms on gen6+
- rc6/emon on ilk is only restored for the modeset case. This is no
problem because rc6 is disabled by default on ilk, and ums on ilk
has never really been a supported option outside of horrible rhel
backports.
v2: Chris Wilson noticed that we not only fail to restore the clock
gating settings after gpu reset.
v3: Move the call to modeset_init_hw in _reset out of the
struct_mutext protected area - other callers don't hold it, too.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_suspend.c | 12 +-----------
drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++-----------
4 files changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 96f8efc..ccfdc81 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -851,9 +851,14 @@ int i915_reset(struct drm_device *dev, u8 flags)
i915_gem_init_ppgtt(dev);
mutex_unlock(&dev->struct_mutex);
+
+ if (drm_core_check_feature(dev, DRIVER_MODESET))
+ intel_modeset_init_hw(dev);
+
drm_irq_uninstall(dev);
drm_mode_config_reset(dev);
drm_irq_install(dev);
+
mutex_lock(&dev->struct_mutex);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7dcdccb..ed2d235 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1429,6 +1429,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */
/* modesetting */
+extern void intel_modeset_init_hw(struct drm_device *dev);
extern void intel_modeset_init(struct drm_device *dev);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 2b5eb22..0c3e3bf 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -879,17 +879,7 @@ int i915_restore_state(struct drm_device *dev)
mutex_unlock(&dev->struct_mutex);
if (drm_core_check_feature(dev, DRIVER_MODESET))
- intel_init_clock_gating(dev);
-
- if (IS_IRONLAKE_M(dev)) {
- ironlake_enable_drps(dev);
- intel_init_emon(dev);
- }
-
- if (INTEL_INFO(dev)->gen >= 6) {
- gen6_enable_rps(dev_priv);
- gen6_update_ring_freq(dev_priv);
- }
+ intel_modeset_init_hw(dev);
mutex_lock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 42dbe14..a1f2d19 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9532,6 +9532,23 @@ static void i915_disable_vga(struct drm_device *dev)
POSTING_READ(vga_reg);
}
+void intel_modeset_init_hw(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ intel_init_clock_gating(dev);
+
+ if (IS_IRONLAKE_M(dev)) {
+ ironlake_enable_drps(dev);
+ intel_init_emon(dev);
+ }
+
+ if (IS_GEN6(dev) || IS_GEN7(dev)) {
+ gen6_enable_rps(dev_priv);
+ gen6_update_ring_freq(dev_priv);
+ }
+}
+
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -9577,17 +9594,7 @@ void intel_modeset_init(struct drm_device *dev)
i915_disable_vga(dev);
intel_setup_outputs(dev);
- intel_init_clock_gating(dev);
-
- if (IS_IRONLAKE_M(dev)) {
- ironlake_enable_drps(dev);
- intel_init_emon(dev);
- }
-
- if (IS_GEN6(dev) || IS_GEN7(dev)) {
- gen6_enable_rps(dev_priv);
- gen6_update_ring_freq(dev_priv);
- }
+ intel_modeset_init_hw(dev);
INIT_WORK(&dev_priv->idle_work, intel_idle_update);
setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
--
1.7.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: re-init modeset hw state after gpu reset
2012-04-10 13:50 ` Daniel Vetter
@ 2012-04-10 14:10 ` Chris Wilson
2012-04-11 10:09 ` Daniel Vetter
0 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2012-04-10 14:10 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
On Tue, 10 Apr 2012 15:50:11 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> After a gpu reset we need to re-init some of the hw state we only
> initialize when modeset is enabled, like rc6, hw contexts or render/GT
> core clock gating and workaround register settings.
>
> Note that this patch has a small change in the resume code:
> - rc6 on gen6+ is only restored for the modeset case (for more
> consistency with other callsites). This is no problem because recent
> kernels refuse to load drm/i915 without kms on gen6+
> - rc6/emon on ilk is only restored for the modeset case. This is no
> problem because rc6 is disabled by default on ilk, and ums on ilk
> has never really been a supported option outside of horrible rhel
> backports.
>
> v2: Chris Wilson noticed that we not only fail to restore the clock
> gating settings after gpu reset.
>
> v3: Move the call to modeset_init_hw in _reset out of the
> struct_mutext protected area - other callers don't hold it, too.
>
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
I don't think it makes the locking any worse than it already is, but it
is becoming more and more suspect.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: re-init modeset hw state after gpu reset
2012-04-10 14:10 ` Chris Wilson
@ 2012-04-11 10:09 ` Daniel Vetter
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2012-04-11 10:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: Daniel Vetter, Intel Graphics Development
On Tue, Apr 10, 2012 at 03:10:23PM +0100, Chris Wilson wrote:
> On Tue, 10 Apr 2012 15:50:11 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > After a gpu reset we need to re-init some of the hw state we only
> > initialize when modeset is enabled, like rc6, hw contexts or render/GT
> > core clock gating and workaround register settings.
> >
> > Note that this patch has a small change in the resume code:
> > - rc6 on gen6+ is only restored for the modeset case (for more
> > consistency with other callsites). This is no problem because recent
> > kernels refuse to load drm/i915 without kms on gen6+
> > - rc6/emon on ilk is only restored for the modeset case. This is no
> > problem because rc6 is disabled by default on ilk, and ums on ilk
> > has never really been a supported option outside of horrible rhel
> > backports.
> >
> > v2: Chris Wilson noticed that we not only fail to restore the clock
> > gating settings after gpu reset.
> >
> > v3: Move the call to modeset_init_hw in _reset out of the
> > struct_mutext protected area - other callers don't hold it, too.
> >
> > Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> I don't think it makes the locking any worse than it already is, but it
> is becoming more and more suspect.
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Queued for -next, thanks for the review.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-04-11 10:08 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-04-10 12:39 [PATCH] drm/i915: re-run init_clock_gating after gpu reset Daniel Vetter
2012-04-10 12:53 ` Chris Wilson
2012-04-10 13:46 ` [PATCH] drm/i915: re-init modeset hw state " Daniel Vetter
2012-04-10 13:50 ` Daniel Vetter
2012-04-10 14:10 ` Chris Wilson
2012-04-11 10:09 ` Daniel Vetter
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.