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From: Eugeni Dodonov <eugeni.dodonov@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Eugeni Dodonov <eugeni.dodonov@intel.com>
Subject: [PATCH 20/29] drm/i915: do not use old code paths on Haswell
Date: Fri, 13 Apr 2012 17:08:56 -0300	[thread overview]
Message-ID: <1334347745-11743-21-git-send-email-eugeni.dodonov@intel.com> (raw)
In-Reply-To: <1334347745-11743-1-git-send-email-eugeni.dodonov@intel.com>

Haswell has a different way of accessing pipes and PCH-specific registers,
so avoid using legacy registers on it.

This patch will probably be reworked into a series of smaller patches once
the required plumbing lands and we won't hit those assertions anymore.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   59 +++++++++++++++++++++++++++-------
 1 file changed, 47 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 712bbaa..a1598a5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -949,9 +949,16 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_TX_CTL(pipe);
-	val = I915_READ(reg);
-	cur_state = !!(val & FDI_TX_ENABLE);
+	if (IS_HASWELL(dev_priv->dev)) {
+		DRM_ERROR("Attempting to check FDI_TX_CTL on Haswell, using DDI instead\n");
+		reg = DDI_FUNC_CTL(pipe);
+		val = I915_READ(reg);
+		cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
+	} else {
+		reg = FDI_TX_CTL(pipe);
+		val = I915_READ(reg);
+		cur_state = !!(val & FDI_TX_ENABLE);
+	}
 	WARN(cur_state != state,
 	     "FDI TX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
@@ -966,9 +973,14 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_RX_CTL(pipe);
-	val = I915_READ(reg);
-	cur_state = !!(val & FDI_RX_ENABLE);
+	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+			DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
+			return;
+	} else {
+		reg = FDI_RX_CTL(pipe);
+		val = I915_READ(reg);
+		cur_state = !!(val & FDI_RX_ENABLE);
+	}
 	WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
@@ -986,6 +998,11 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 	if (dev_priv->info->gen == 5)
 		return;
 
+	if (IS_HASWELL(dev_priv->dev)) {
+		DRM_ERROR("Attempting to check FDI_TX_PLL on Haswell, aborting\n");
+		return;
+	}
+
 	reg = FDI_TX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
@@ -997,6 +1014,10 @@ static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 	int reg;
 	u32 val;
 
+	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+		DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
+		return;
+	}
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
@@ -1102,6 +1123,11 @@ static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 	u32 val;
 	bool enabled;
 
+	if (HAS_PCH_LPT(dev_priv->dev)) {
+		DRM_ERROR("LPT does not has PCH refclk, skipping check\n");
+		return;
+	}
+
 	val = I915_READ(PCH_DREF_CONTROL);
 	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 			    DREF_SUPERSPREAD_SOURCE_MASK));
@@ -1445,6 +1471,10 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 	assert_fdi_tx_enabled(dev_priv, pipe);
 	assert_fdi_rx_enabled(dev_priv, pipe);
 
+	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+		DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
+		return;
+	}
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
 	pipeconf_val = I915_READ(PIPECONF(pipe));
@@ -2971,13 +3001,18 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
 	udelay(200);
 
 	/* Enable CPU FDI TX PLL, always on for Ironlake */
-	reg = FDI_TX_CTL(pipe);
-	temp = I915_READ(reg);
-	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
-		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
+	if (IS_HASWELL(dev)) {
+		DRM_ERROR("Skipping enablement of FDI_TX_PLL on Haswell\n");
+		return;
+	} else {
+		reg = FDI_TX_CTL(pipe);
+		temp = I915_READ(reg);
+		if ((temp & FDI_TX_PLL_ENABLE) == 0) {
+			I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
 
-		POSTING_READ(reg);
-		udelay(100);
+			POSTING_READ(reg);
+			udelay(100);
+		}
 	}
 }
 
-- 
1.7.10

  parent reply	other threads:[~2012-04-13 20:35 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-04-13 20:08 [PATCH 00/29] Haswell round 3 Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 01/29] drm/i915: add definition of LPT FDI port width registers Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 02/29] drm/i915: add WRPLL divider programming bits Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 03/29] drm/i915: add Haswell DIP controls registers Eugeni Dodonov
2012-04-17 10:12   ` Daniel Vetter
2012-04-17 12:02     ` Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 04/29] drm/i915: support infoframes on Haswell Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 05/29] drm/i915: prevent NULL pointer exception when using gmbus Eugeni Dodonov
2012-04-13 20:18   ` Chris Wilson
2012-04-14  0:26     ` Eugeni Dodonov
2012-04-14 15:58       ` Daniel Vetter
2012-04-14 16:01         ` Chris Wilson
2012-04-13 20:08 ` [PATCH 06/29] drm/i915: add support for SBI ops Eugeni Dodonov
2012-04-13 20:26   ` Chris Wilson
2012-04-14  0:28     ` Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 07/29] drm/i915: calculate same watermarks on Haswell as on Ivy Bridge Eugeni Dodonov
2012-04-13 20:27   ` Chris Wilson
2012-04-13 20:08 ` [PATCH 08/29] drm/i915: share forcewaking code between IVB and HSW Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 09/29] drm/i915: haswell has 3 pipes as well Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 10/29] drm/i915: reuse Ivybridge interrupts code for Haswell Eugeni Dodonov
2012-04-15 23:29   ` Daniel Vetter
2012-04-13 20:08 ` [PATCH 11/29] drm/i915: share pipe count handling with Ivybridge Eugeni Dodonov
2012-04-17 10:19   ` Daniel Vetter
2012-04-17 10:36     ` Chris Wilson
2012-04-17 11:26       ` Daniel Vetter
2012-04-17 11:38         ` Chris Wilson
2012-04-13 20:08 ` [PATCH 12/29] drm/i915: share IVB cursor routine with Haswell Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 13/29] drm/i915: show unknown sdvox registers on hdmi init Eugeni Dodonov
2012-04-17 10:20   ` Daniel Vetter
2012-04-13 20:08 ` [PATCH 14/29] drm/i915: do not use fdi_normal_train on haswell Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 15/29] drm/i915: do not enable PCH PLL on pre-haswell Eugeni Dodonov
2012-04-13 20:55   ` Chris Wilson
2012-04-14  0:31     ` Eugeni Dodonov
2012-04-15 23:52   ` Daniel Vetter
2012-04-13 20:08 ` [PATCH 16/29] drm/i915: detect PCH encoders on Haswell Eugeni Dodonov
2012-04-17 10:21   ` Daniel Vetter
2012-04-13 20:08 ` [PATCH 17/29] drm/i915: enable power wells on haswell init Eugeni Dodonov
2012-04-13 21:03   ` Chris Wilson
2012-04-14  1:26     ` Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 18/29] drm/i915: disable rc6 on haswell for now Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 19/29] drm/i915: program WM_LINETIME on Haswell Eugeni Dodonov
2012-04-13 20:08 ` Eugeni Dodonov [this message]
2012-04-13 20:08 ` [PATCH 21/29] drm/i915: initialize DDI buffer translations Eugeni Dodonov
2012-04-13 21:05   ` Chris Wilson
2012-04-13 21:11   ` Chris Wilson
2012-04-14  1:32     ` Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 22/29] drm/i915: perform Haswell DDI link training in FDI mode Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 23/29] drm/i915: disable pipe DDI function when disabling pipe Eugeni Dodonov
2012-04-13 20:09 ` [PATCH 24/29] drm/i915: program iCLKIP on Lynx Point Eugeni Dodonov
2012-04-15 23:49   ` Daniel Vetter
2012-04-16  0:44     ` Eugeni Dodonov
2012-04-16  8:26       ` Chris Wilson
2012-04-16  8:56         ` Daniel Vetter
2012-04-13 20:09 ` [PATCH 25/29] drm/i915: detect digital outputs on Haswell Eugeni Dodonov
2012-04-13 21:17   ` Chris Wilson
2012-04-14  0:37     ` Eugeni Dodonov
2012-04-15 23:36       ` Daniel Vetter
2012-04-13 20:09 ` [PATCH 26/29] drm/i915: add support for DDI-controlled digital outputs Eugeni Dodonov
2012-04-13 20:09 ` [PATCH 27/29] drm/i915: add WR PLL programming table Eugeni Dodonov
2012-04-13 20:09 ` [PATCH 28/29] drm/i915: prepare HDMI link for Haswell Eugeni Dodonov
2012-04-13 20:09 ` [PATCH 29/29] drm/i915: hook Haswell devices in place Eugeni Dodonov
2012-04-17 10:49 ` [PATCH 00/29] Haswell round 3 Daniel Vetter
2012-04-17 11:58   ` Eugeni Dodonov

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