[PATCH 1/5] ARM: tegra: Add pllc clock init table

[PATCH 1/5] ARM: tegra: Add pllc clock init table

[Stephen Warren]

From: Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

(cherry picked from commit 54f28b336f2ba3da93a459d22e32944823960d08
in the chromeos-2.6.38 kernel)

swarren adds:

pll_c will be used as a clock source. Fill in tegra_pll_c_freq_table[]
so that it's possible to explicitly initialize the PLL.

NVIDIA's downstream nv-3.1 kernel and the ChromeOS kernel have different
pll_c tables. nv-3.1 contains entries for 522MHz and 598MHz output,
whereas the ChromeOS kernel contains entries for 600MHz output. I chose
to upstream the ChromeOS values for now, since the 600MHz rate appears
to match the default rate of this PLL when the HW boots.

Signed-off-by: Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Olof Johansson <olofj-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/mach-tegra/tegra2_clocks.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index cf4999b..0bf0f2d 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1486,6 +1486,10 @@ static struct clk tegra_clk_m = {
 };
 
 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+	{ 12000000, 600000000, 600, 12, 1, 8 },
+	{ 13000000, 600000000, 600, 13, 1, 8 },
+	{ 19200000, 600000000, 500, 16, 1, 6 },
+	{ 26000000, 600000000, 600, 26, 1, 8 },
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-- 
1.7.0.4

[PATCH 1/5] ARM: tegra: Add pllc clock init table

[Stephen Warren]

From: Allen Martin <amartin@nvidia.com>

(cherry picked from commit 54f28b336f2ba3da93a459d22e32944823960d08
in the chromeos-2.6.38 kernel)

swarren adds:

pll_c will be used as a clock source. Fill in tegra_pll_c_freq_table[]
so that it's possible to explicitly initialize the PLL.

NVIDIA's downstream nv-3.1 kernel and the ChromeOS kernel have different
pll_c tables. nv-3.1 contains entries for 522MHz and 598MHz output,
whereas the ChromeOS kernel contains entries for 600MHz output. I chose
to upstream the ChromeOS values for now, since the 600MHz rate appears
to match the default rate of this PLL when the HW boots.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Olof Johansson <olofj@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/mach-tegra/tegra2_clocks.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index cf4999b..0bf0f2d 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1486,6 +1486,10 @@ static struct clk tegra_clk_m = {
 };
 
 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+	{ 12000000, 600000000, 600, 12, 1, 8 },
+	{ 13000000, 600000000, 600, 13, 1, 8 },
+	{ 19200000, 600000000, 500, 16, 1, 6 },
+	{ 26000000, 600000000, 600, 26, 1, 8 },
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-- 
1.7.0.4

[PATCH 2/5] ARM: tegra: reparent sclk to pll_c_out1

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

pll_p_out4 needs to be used for other purposes. Reparent sclk so that
it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this
is the lowest precise rate that can be achieved by dividing the pll_c
rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909...,
600/6=100).

Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/mach-tegra/common.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 22df10f..e969004 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -83,8 +83,10 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
 	{ "pll_p_out2",	"pll_p",	48000000,	true },
 	{ "pll_p_out3",	"pll_p",	72000000,	true },
 	{ "pll_p_out4",	"pll_p",	108000000,	true },
-	{ "sclk",	"pll_p_out4",	108000000,	true },
-	{ "hclk",	"sclk",		108000000,	true },
+	{ "pll_c",	"clk_m",	600000000,	true },
+	{ "pll_c_out1",	"pll_c",	120000000,	true },
+	{ "sclk",	"pll_c_out1",	120000000,	true },
+	{ "hclk",	"sclk",		120000000,	true },
 	{ "pclk",	"hclk",		54000000,	true },
 	{ "csite",	NULL,		0,		true },
 	{ "emc",	NULL,		0,		true },
-- 
1.7.0.4

[PATCH 2/5] ARM: tegra: reparent sclk to pll_c_out1

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

pll_p_out4 needs to be used for other purposes. Reparent sclk so that
it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this
is the lowest precise rate that can be achieved by dividing the pll_c
rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909...,
600/6=100).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/mach-tegra/common.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 22df10f..e969004 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -83,8 +83,10 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
 	{ "pll_p_out2",	"pll_p",	48000000,	true },
 	{ "pll_p_out3",	"pll_p",	72000000,	true },
 	{ "pll_p_out4",	"pll_p",	108000000,	true },
-	{ "sclk",	"pll_p_out4",	108000000,	true },
-	{ "hclk",	"sclk",		108000000,	true },
+	{ "pll_c",	"clk_m",	600000000,	true },
+	{ "pll_c_out1",	"pll_c",	120000000,	true },
+	{ "sclk",	"pll_c_out1",	120000000,	true },
+	{ "hclk",	"sclk",		120000000,	true },
 	{ "pclk",	"hclk",		54000000,	true },
 	{ "csite",	NULL,		0,		true },
 	{ "emc",	NULL,		0,		true },
-- 
1.7.0.4

[PATCH 3/5] ARM: tegra: change pll_p_out4's rate to 24MHz

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.

Remove board-paz00.c's now-duplicate initialization of this clock.

Reported-by: Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org>
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/mach-tegra/board-paz00.c |    1 -
 arch/arm/mach-tegra/common.c      |    2 +-
 2 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 330afdf..aebfa40 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -176,7 +176,6 @@ static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
 	{ "uarta",	"pll_p",	216000000,	true },
 	{ "uartc",	"pll_p",	216000000,	true },
 
-	{ "pll_p_out4",	"pll_p",	24000000,	true },
 	{ "usbd",	"clk_m",	12000000,	false },
 	{ "usb2",	"clk_m",	12000000,	false },
 	{ "usb3",	"clk_m",	12000000,	false },
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index e969004..c50f2ee 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -82,7 +82,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
 	{ "pll_p_out1",	"pll_p",	28800000,	true },
 	{ "pll_p_out2",	"pll_p",	48000000,	true },
 	{ "pll_p_out3",	"pll_p",	72000000,	true },
-	{ "pll_p_out4",	"pll_p",	108000000,	true },
+	{ "pll_p_out4",	"pll_p",	24000000,	true },
 	{ "pll_c",	"clk_m",	600000000,	true },
 	{ "pll_c_out1",	"pll_c",	120000000,	true },
 	{ "sclk",	"pll_c_out1",	120000000,	true },
-- 
1.7.0.4

[PATCH 3/5] ARM: tegra: change pll_p_out4's rate to 24MHz

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.

Remove board-paz00.c's now-duplicate initialization of this clock.

Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/mach-tegra/board-paz00.c |    1 -
 arch/arm/mach-tegra/common.c      |    2 +-
 2 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 330afdf..aebfa40 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -176,7 +176,6 @@ static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
 	{ "uarta",	"pll_p",	216000000,	true },
 	{ "uartc",	"pll_p",	216000000,	true },
 
-	{ "pll_p_out4",	"pll_p",	24000000,	true },
 	{ "usbd",	"clk_m",	12000000,	false },
 	{ "usb2",	"clk_m",	12000000,	false },
 	{ "usb3",	"clk_m",	12000000,	false },
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index e969004..c50f2ee 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -82,7 +82,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
 	{ "pll_p_out1",	"pll_p",	28800000,	true },
 	{ "pll_p_out2",	"pll_p",	48000000,	true },
 	{ "pll_p_out3",	"pll_p",	72000000,	true },
-	{ "pll_p_out4",	"pll_p",	108000000,	true },
+	{ "pll_p_out4",	"pll_p",	24000000,	true },
 	{ "pll_c",	"clk_m",	600000000,	true },
 	{ "pll_c_out1",	"pll_c",	120000000,	true },
 	{ "sclk",	"pll_c_out1",	120000000,	true },
-- 
1.7.0.4

[PATCH 4/5] ARM: tegra: don't hard-code USB ULPI PHY reset_gpio

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Not all boards use GPIO_PV0 as the ULPI PHY reset signal. Instead of
hard-coding this GPIO into devices.c, make the board files set it
explicitly. This will allow the PHY code to differentiate between set and
unset values, and hence know when to read the value from device tree.

Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/mach-tegra/board-paz00.c     |    2 ++
 arch/arm/mach-tegra/board-trimslice.c |    2 ++
 arch/arm/mach-tegra/devices.c         |    5 ++---
 arch/arm/mach-tegra/devices.h         |    4 ++++
 4 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index aebfa40..e31317d 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -159,6 +159,8 @@ static void paz00_i2c_init(void)
 
 static void paz00_usb_init(void)
 {
+	tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST;
+
 	platform_device_register(&tegra_ehci2_device);
 	platform_device_register(&tegra_ehci3_device);
 }
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 7a21cf5..c6edfe0 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -116,6 +116,8 @@ static void trimslice_usb_init(void)
 	pdata = tegra_ehci1_device.dev.platform_data;
 	pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
 
+	tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0;
+
 	platform_device_register(&tegra_ehci3_device);
 	platform_device_register(&tegra_ehci2_device);
 	platform_device_register(&tegra_ehci1_device);
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 2d8dfa2..c70e65f 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -439,9 +439,8 @@ static struct resource tegra_usb3_resources[] = {
 	},
 };
 
-static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
-	/* All existing boards use GPIO PV0 for phy reset */
-	.reset_gpio = TEGRA_GPIO_PV0,
+struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
+	.reset_gpio = -1,
 	.clk = "cdev2",
 };
 
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
index 138c642..4f50527 100644
--- a/arch/arm/mach-tegra/devices.h
+++ b/arch/arm/mach-tegra/devices.h
@@ -22,6 +22,10 @@
 #include <linux/platform_device.h>
 #include <linux/platform_data/tegra_usb.h>
 
+#include <mach/usb_phy.h>
+
+extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
+
 extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
 extern struct tegra_ehci_platform_data tegra_ehci2_pdata;
 extern struct tegra_ehci_platform_data tegra_ehci3_pdata;
-- 
1.7.0.4

[PATCH 4/5] ARM: tegra: don't hard-code USB ULPI PHY reset_gpio

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Not all boards use GPIO_PV0 as the ULPI PHY reset signal. Instead of
hard-coding this GPIO into devices.c, make the board files set it
explicitly. This will allow the PHY code to differentiate between set and
unset values, and hence know when to read the value from device tree.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/mach-tegra/board-paz00.c     |    2 ++
 arch/arm/mach-tegra/board-trimslice.c |    2 ++
 arch/arm/mach-tegra/devices.c         |    5 ++---
 arch/arm/mach-tegra/devices.h         |    4 ++++
 4 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index aebfa40..e31317d 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -159,6 +159,8 @@ static void paz00_i2c_init(void)
 
 static void paz00_usb_init(void)
 {
+	tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST;
+
 	platform_device_register(&tegra_ehci2_device);
 	platform_device_register(&tegra_ehci3_device);
 }
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 7a21cf5..c6edfe0 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -116,6 +116,8 @@ static void trimslice_usb_init(void)
 	pdata = tegra_ehci1_device.dev.platform_data;
 	pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
 
+	tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0;
+
 	platform_device_register(&tegra_ehci3_device);
 	platform_device_register(&tegra_ehci2_device);
 	platform_device_register(&tegra_ehci1_device);
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 2d8dfa2..c70e65f 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -439,9 +439,8 @@ static struct resource tegra_usb3_resources[] = {
 	},
 };
 
-static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
-	/* All existing boards use GPIO PV0 for phy reset */
-	.reset_gpio = TEGRA_GPIO_PV0,
+struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
+	.reset_gpio = -1,
 	.clk = "cdev2",
 };
 
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
index 138c642..4f50527 100644
--- a/arch/arm/mach-tegra/devices.h
+++ b/arch/arm/mach-tegra/devices.h
@@ -22,6 +22,10 @@
 #include <linux/platform_device.h>
 #include <linux/platform_data/tegra_usb.h>
 
+#include <mach/usb_phy.h>
+
+extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
+
 extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
 extern struct tegra_ehci_platform_data tegra_ehci2_pdata;
 extern struct tegra_ehci_platform_data tegra_ehci3_pdata;
-- 
1.7.0.4

[PATCH 5/5] ARM: tegra: add USB ULPI PHY reset GPIO to device tree

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

ULPI PHYs have a reset signal, and different boards use a different GPIO
for this task. Add a property to device tree to represent this.

I'm not sure if adding this property to the EHCI controller node is
entirely correct; perhaps eventually we should have explicit separate
nodes for the various PHYs. However, we don't have that right now, so this
binding seems like a reasonable choice.

Note: There is still some problem initializing the PHY on Harmony.
However, Seaboard, Ventana, Paz00 and TrimSlice all work OK.

Cc: <devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org>
Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
Cc: <linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/usb/tegra-usb.txt          |    3 +++
 arch/arm/boot/dts/tegra-harmony.dts                |    4 ++++
 arch/arm/boot/dts/tegra-paz00.dts                  |    4 ++++
 arch/arm/boot/dts/tegra-seaboard.dts               |    4 ++++
 arch/arm/boot/dts/tegra-trimslice.dts              |    4 ++++
 arch/arm/boot/dts/tegra-ventana.dts                |    4 ++++
 arch/arm/mach-tegra/include/mach/usb_phy.h         |    4 ++--
 arch/arm/mach-tegra/usb_phy.c                      |   15 +++++++++++++--
 drivers/usb/host/ehci-tegra.c                      |    5 +++--
 9 files changed, 41 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/tegra-usb.txt b/Documentation/devicetree/bindings/usb/tegra-usb.txt
index 007005d..e9b005d 100644
--- a/Documentation/devicetree/bindings/usb/tegra-usb.txt
+++ b/Documentation/devicetree/bindings/usb/tegra-usb.txt
@@ -12,6 +12,9 @@ Required properties :
  - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
    activated for the bus to be powered.
 
+Required properties for phy_type == ulpi:
+  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
+
 Optional properties:
   - dr_mode : dual role mode. Indicates the working mode for
    nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 1a0b1f1..59bf1cf 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -336,4 +336,8 @@
 		power-gpios = <&gpio 70 0>; /* gpio PI6 */
 		support-8bit;
 	};
+
+	usb@c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
 };
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 10943fb..fad92f2 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -351,4 +351,8 @@
 			linux,default-trigger = "rfkill0";
 		};
 	};
+
+	usb@c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+	};
 };
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index ec33116..ed0a2f5 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -415,4 +415,8 @@
 				0x00000000 0x00000000 0x00000000 0x00000000 >;
 		};
 	};
+
+	usb@c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
 };
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 98efd5b..71b73aa 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -304,4 +304,8 @@
 		cd-gpios = <&gpio 121 0>;
 		wp-gpios = <&gpio 122 0>;
 	};
+
+	usb@c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+	};
 };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 71eb2e5..bd074cf 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -335,4 +335,8 @@
 	sdhci@c8000600 {
 		support-8bit;
 	};
+
+	usb@c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
 };
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
index de1a0f6..935ce9f 100644
--- a/arch/arm/mach-tegra/include/mach/usb_phy.h
+++ b/arch/arm/mach-tegra/include/mach/usb_phy.h
@@ -61,8 +61,8 @@ struct tegra_usb_phy {
 	struct usb_phy *ulpi;
 };
 
-struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
-			void *config, enum tegra_usb_phy_mode phy_mode);
+struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
+	void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode);
 
 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy);
 
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index d71d2fe..54e353c 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -26,6 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/of_gpio.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <asm/mach-types.h>
@@ -654,8 +655,8 @@ static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
 	clk_disable(phy->clk);
 }
 
-struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
-			void *config, enum tegra_usb_phy_mode phy_mode)
+struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
+	void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
 {
 	struct tegra_usb_phy *phy;
 	struct tegra_ulpi_config *ulpi_config;
@@ -711,6 +712,16 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
 			err = -ENXIO;
 			goto err1;
 		}
+		if (!gpio_is_valid(ulpi_config->reset_gpio))
+			ulpi_config->reset_gpio =
+				of_get_named_gpio(dev->of_node,
+						  "nvidia,phy-reset-gpio", 0);
+		if (!gpio_is_valid(ulpi_config->reset_gpio)) {
+			pr_err("%s: invalid reset gpio: %d\n", __func__,
+			       ulpi_config->reset_gpio);
+			err = -EINVAL;
+			goto err1;
+		}
 		gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
 		gpio_direction_output(ulpi_config->reset_gpio, 0);
 		phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 9692bef..14532fe 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -708,8 +708,9 @@ static int tegra_ehci_probe(struct platform_device *pdev)
 		}
 	}
 
-	tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
-						TEGRA_USB_PHY_MODE_HOST);
+	tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs,
+					pdata->phy_config,
+					TEGRA_USB_PHY_MODE_HOST);
 	if (IS_ERR(tegra->phy)) {
 		dev_err(&pdev->dev, "Failed to open USB phy\n");
 		err = -ENXIO;
-- 
1.7.0.4

[PATCH 5/5] ARM: tegra: add USB ULPI PHY reset GPIO to device tree

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

ULPI PHYs have a reset signal, and different boards use a different GPIO
for this task. Add a property to device tree to represent this.

I'm not sure if adding this property to the EHCI controller node is
entirely correct; perhaps eventually we should have explicit separate
nodes for the various PHYs. However, we don't have that right now, so this
binding seems like a reasonable choice.

Note: There is still some problem initializing the PHY on Harmony.
However, Seaboard, Ventana, Paz00 and TrimSlice all work OK.

Cc: <devicetree-discuss@lists.ozlabs.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: <linux-usb@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 .../devicetree/bindings/usb/tegra-usb.txt          |    3 +++
 arch/arm/boot/dts/tegra-harmony.dts                |    4 ++++
 arch/arm/boot/dts/tegra-paz00.dts                  |    4 ++++
 arch/arm/boot/dts/tegra-seaboard.dts               |    4 ++++
 arch/arm/boot/dts/tegra-trimslice.dts              |    4 ++++
 arch/arm/boot/dts/tegra-ventana.dts                |    4 ++++
 arch/arm/mach-tegra/include/mach/usb_phy.h         |    4 ++--
 arch/arm/mach-tegra/usb_phy.c                      |   15 +++++++++++++--
 drivers/usb/host/ehci-tegra.c                      |    5 +++--
 9 files changed, 41 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/tegra-usb.txt b/Documentation/devicetree/bindings/usb/tegra-usb.txt
index 007005d..e9b005d 100644
--- a/Documentation/devicetree/bindings/usb/tegra-usb.txt
+++ b/Documentation/devicetree/bindings/usb/tegra-usb.txt
@@ -12,6 +12,9 @@ Required properties :
  - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
    activated for the bus to be powered.
 
+Required properties for phy_type == ulpi:
+  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
+
 Optional properties:
   - dr_mode : dual role mode. Indicates the working mode for
    nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 1a0b1f1..59bf1cf 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -336,4 +336,8 @@
 		power-gpios = <&gpio 70 0>; /* gpio PI6 */
 		support-8bit;
 	};
+
+	usb at c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
 };
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 10943fb..fad92f2 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -351,4 +351,8 @@
 			linux,default-trigger = "rfkill0";
 		};
 	};
+
+	usb at c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+	};
 };
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index ec33116..ed0a2f5 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -415,4 +415,8 @@
 				0x00000000 0x00000000 0x00000000 0x00000000 >;
 		};
 	};
+
+	usb at c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
 };
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 98efd5b..71b73aa 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -304,4 +304,8 @@
 		cd-gpios = <&gpio 121 0>;
 		wp-gpios = <&gpio 122 0>;
 	};
+
+	usb at c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+	};
 };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 71eb2e5..bd074cf 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -335,4 +335,8 @@
 	sdhci at c8000600 {
 		support-8bit;
 	};
+
+	usb at c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
 };
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
index de1a0f6..935ce9f 100644
--- a/arch/arm/mach-tegra/include/mach/usb_phy.h
+++ b/arch/arm/mach-tegra/include/mach/usb_phy.h
@@ -61,8 +61,8 @@ struct tegra_usb_phy {
 	struct usb_phy *ulpi;
 };
 
-struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
-			void *config, enum tegra_usb_phy_mode phy_mode);
+struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
+	void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode);
 
 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy);
 
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index d71d2fe..54e353c 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -26,6 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/of_gpio.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <asm/mach-types.h>
@@ -654,8 +655,8 @@ static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
 	clk_disable(phy->clk);
 }
 
-struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
-			void *config, enum tegra_usb_phy_mode phy_mode)
+struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
+	void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
 {
 	struct tegra_usb_phy *phy;
 	struct tegra_ulpi_config *ulpi_config;
@@ -711,6 +712,16 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
 			err = -ENXIO;
 			goto err1;
 		}
+		if (!gpio_is_valid(ulpi_config->reset_gpio))
+			ulpi_config->reset_gpio =
+				of_get_named_gpio(dev->of_node,
+						  "nvidia,phy-reset-gpio", 0);
+		if (!gpio_is_valid(ulpi_config->reset_gpio)) {
+			pr_err("%s: invalid reset gpio: %d\n", __func__,
+			       ulpi_config->reset_gpio);
+			err = -EINVAL;
+			goto err1;
+		}
 		gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
 		gpio_direction_output(ulpi_config->reset_gpio, 0);
 		phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 9692bef..14532fe 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -708,8 +708,9 @@ static int tegra_ehci_probe(struct platform_device *pdev)
 		}
 	}
 
-	tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
-						TEGRA_USB_PHY_MODE_HOST);
+	tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs,
+					pdata->phy_config,
+					TEGRA_USB_PHY_MODE_HOST);
 	if (IS_ERR(tegra->phy)) {
 		dev_err(&pdev->dev, "Failed to open USB phy\n");
 		err = -ENXIO;
-- 
1.7.0.4

Re: [PATCH 1/5] ARM: tegra: Add pllc clock init table

[Olof Johansson]

On Fri, Apr 13, 2012 at 04:42:02PM -0600, Stephen Warren wrote:
> From: Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> (cherry picked from commit 54f28b336f2ba3da93a459d22e32944823960d08
> in the chromeos-2.6.38 kernel)
> 
> swarren adds:

The above 4 lines make no sense for upstream, so you can just say "from the
Chrome OS 2.6.38 tree" or similar.

> pll_c will be used as a clock source. Fill in tegra_pll_c_freq_table[]
> so that it's possible to explicitly initialize the PLL.
> 
> NVIDIA's downstream nv-3.1 kernel and the ChromeOS kernel have different
> pll_c tables. nv-3.1 contains entries for 522MHz and 598MHz output,
> whereas the ChromeOS kernel contains entries for 600MHz output. I chose
> to upstream the ChromeOS values for now, since the 600MHz rate appears
> to match the default rate of this PLL when the HW boots.
> 
> Signed-off-by: Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Olof Johansson <olofj-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm/mach-tegra/tegra2_clocks.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
> index cf4999b..0bf0f2d 100644
> --- a/arch/arm/mach-tegra/tegra2_clocks.c
> +++ b/arch/arm/mach-tegra/tegra2_clocks.c
> @@ -1486,6 +1486,10 @@ static struct clk tegra_clk_m = {
>  };
>  
>  static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
> +	{ 12000000, 600000000, 600, 12, 1, 8 },
> +	{ 13000000, 600000000, 600, 13, 1, 8 },
> +	{ 19200000, 600000000, 500, 16, 1, 6 },
> +	{ 26000000, 600000000, 600, 26, 1, 8 },
>  	{ 0, 0, 0, 0, 0, 0 },
>  };
>  
> -- 
> 1.7.0.4
> 

[PATCH 1/5] ARM: tegra: Add pllc clock init table

[Olof Johansson]

On Fri, Apr 13, 2012 at 04:42:02PM -0600, Stephen Warren wrote:
> From: Allen Martin <amartin@nvidia.com>
> 
> (cherry picked from commit 54f28b336f2ba3da93a459d22e32944823960d08
> in the chromeos-2.6.38 kernel)
> 
> swarren adds:

The above 4 lines make no sense for upstream, so you can just say "from the
Chrome OS 2.6.38 tree" or similar.

> pll_c will be used as a clock source. Fill in tegra_pll_c_freq_table[]
> so that it's possible to explicitly initialize the PLL.
> 
> NVIDIA's downstream nv-3.1 kernel and the ChromeOS kernel have different
> pll_c tables. nv-3.1 contains entries for 522MHz and 598MHz output,
> whereas the ChromeOS kernel contains entries for 600MHz output. I chose
> to upstream the ChromeOS values for now, since the 600MHz rate appears
> to match the default rate of this PLL when the HW boots.
> 
> Signed-off-by: Allen Martin <amartin@nvidia.com>
> Signed-off-by: Olof Johansson <olofj@chromium.org>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  arch/arm/mach-tegra/tegra2_clocks.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
> index cf4999b..0bf0f2d 100644
> --- a/arch/arm/mach-tegra/tegra2_clocks.c
> +++ b/arch/arm/mach-tegra/tegra2_clocks.c
> @@ -1486,6 +1486,10 @@ static struct clk tegra_clk_m = {
>  };
>  
>  static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
> +	{ 12000000, 600000000, 600, 12, 1, 8 },
> +	{ 13000000, 600000000, 600, 13, 1, 8 },
> +	{ 19200000, 600000000, 500, 16, 1, 6 },
> +	{ 26000000, 600000000, 600, 26, 1, 8 },
>  	{ 0, 0, 0, 0, 0, 0 },
>  };
>  
> -- 
> 1.7.0.4
> 

Re: [PATCH 1/5] ARM: tegra: Add pllc clock init table

[Stephen Warren]

On 04/14/2012 06:33 PM, Olof Johansson wrote:
> On Fri, Apr 13, 2012 at 04:42:02PM -0600, Stephen Warren wrote:
>> From: Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> (cherry picked from commit 54f28b336f2ba3da93a459d22e32944823960d08
>> in the chromeos-2.6.38 kernel)
>>
>> swarren adds:
> 
> The above 4 lines make no sense for upstream, so you can just say "from the
> Chrome OS 2.6.38 tree" or similar.

I tend to disagree; I'd love to see some tie between downstream and
upstream repositories so that people working on both downstream and
upstream kernels can tie the two together much more easily. And, the
chromeos tree is well known amongst those working on Tegra, and publicly
accessible.

Still, I guess we haven't followed this practice on commits before, so
it would be inconsistent to include this, unless we resolved to be
diligent about this going forward.

So, I'll remove it.

[PATCH 1/5] ARM: tegra: Add pllc clock init table

[Stephen Warren]

On 04/14/2012 06:33 PM, Olof Johansson wrote:
> On Fri, Apr 13, 2012 at 04:42:02PM -0600, Stephen Warren wrote:
>> From: Allen Martin <amartin@nvidia.com>
>>
>> (cherry picked from commit 54f28b336f2ba3da93a459d22e32944823960d08
>> in the chromeos-2.6.38 kernel)
>>
>> swarren adds:
> 
> The above 4 lines make no sense for upstream, so you can just say "from the
> Chrome OS 2.6.38 tree" or similar.

I tend to disagree; I'd love to see some tie between downstream and
upstream repositories so that people working on both downstream and
upstream kernels can tie the two together much more easily. And, the
chromeos tree is well known amongst those working on Tegra, and publicly
accessible.

Still, I guess we haven't followed this practice on commits before, so
it would be inconsistent to include this, unless we resolved to be
diligent about this going forward.

So, I'll remove it.