* [U-Boot] [PATCH 0/6] Various gdsys ppc4xx boards revised
@ 2012-04-26 13:54 Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 1/6] powerpc/ppc4xx: Adjust environment size on neo Dirk Eibach
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Dirk Eibach @ 2012-04-26 13:54 UTC (permalink / raw)
To: u-boot
Dirk Eibach (6):
powerpc/ppc4xx: Adjust environment size on neo
powerpc/ppc4xx: Make gdsys 405ep boards reset more generic
powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes
powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20
powerpc/ppc4xx: Update gdsys board configurations
powerpc/ppc4xx: Fix typo in gdsys_fpga.h
board/gdsys/405ep/405ep.c | 42 +++++------
board/gdsys/405ep/405ep.h | 10 +++
board/gdsys/405ep/Makefile | 1 +
board/gdsys/405ep/dlvision-10g.c | 76 +++++++++++++++---
board/gdsys/405ep/io.c | 75 +++++++++++++++---
board/gdsys/405ep/iocon.c | 68 +++++++++++++----
board/gdsys/405ep/neo.c | 161 ++++++++++++++++++++++++++++++++++++++
board/gdsys/neo/Makefile | 45 -----------
board/gdsys/neo/neo.c | 102 ------------------------
boards.cfg | 2 +-
include/configs/dlvision-10g.h | 9 ++-
include/configs/gdppc440etx.h | 4 +
include/configs/intip.h | 4 +-
include/configs/io.h | 13 +++-
include/configs/io64.h | 2 +-
include/configs/iocon.h | 9 ++-
include/configs/neo.h | 96 +++++++++++++----------
include/gdsys_fpga.h | 13 +++-
18 files changed, 468 insertions(+), 264 deletions(-)
create mode 100644 board/gdsys/405ep/405ep.h
create mode 100644 board/gdsys/405ep/neo.c
delete mode 100644 board/gdsys/neo/Makefile
delete mode 100644 board/gdsys/neo/neo.c
--
1.7.2.5
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v2 1/6] powerpc/ppc4xx: Adjust environment size on neo
2012-04-26 13:54 [U-Boot] [PATCH 0/6] Various gdsys ppc4xx boards revised Dirk Eibach
@ 2012-04-26 13:54 ` Dirk Eibach
2012-04-30 13:10 ` Stefan Roese
2012-04-26 13:54 ` [U-Boot] [PATCH v2 2/6] powerpc/ppc4xx: Make gdsys 405ep boards reset more generic Dirk Eibach
` (4 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Dirk Eibach @ 2012-04-26 13:54 UTC (permalink / raw)
To: u-boot
Environment size on neo has to be 0x20000 for compatibilty reasons.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
---
Changes in v2:
- add Cc
- split up original patch series
include/configs/neo.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 8de5aaf..6559353 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -150,7 +150,7 @@
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
--
1.7.2.5
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v2 2/6] powerpc/ppc4xx: Make gdsys 405ep boards reset more generic
2012-04-26 13:54 [U-Boot] [PATCH 0/6] Various gdsys ppc4xx boards revised Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 1/6] powerpc/ppc4xx: Adjust environment size on neo Dirk Eibach
@ 2012-04-26 13:54 ` Dirk Eibach
2012-04-26 16:08 ` Stefan Roese
2012-04-26 13:54 ` [U-Boot] [PATCH v2 3/6] powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes Dirk Eibach
` (3 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Dirk Eibach @ 2012-04-26 13:54 UTC (permalink / raw)
To: u-boot
In order to add boards that have different hardware for fpga reset,
any 405ep gdsys board now provides these functions:
void gd405ep_init(void);
void gd405ep_set_fpga_reset(unsigned state);
void gd405ep_setup_hw(void);
int gd405ep_get_fpga_done(unsigned fpga);
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
---
Changes in v2:
- add Cc
- split up original patch series
board/gdsys/405ep/405ep.c | 42 +++++------
board/gdsys/405ep/405ep.h | 10 +++
board/gdsys/405ep/Makefile | 1 +
board/gdsys/405ep/dlvision-10g.c | 36 ++++++++-
board/gdsys/405ep/io.c | 34 ++++++++
board/gdsys/405ep/iocon.c | 34 ++++++++
board/gdsys/405ep/neo.c | 161 ++++++++++++++++++++++++++++++++++++++
board/gdsys/neo/Makefile | 45 -----------
board/gdsys/neo/neo.c | 102 ------------------------
boards.cfg | 2 +-
include/configs/dlvision-10g.h | 3 +-
include/configs/io.h | 5 +-
include/configs/iocon.h | 3 +-
include/configs/neo.h | 94 +++++++++++++----------
include/gdsys_fpga.h | 11 +++
15 files changed, 366 insertions(+), 217 deletions(-)
create mode 100644 board/gdsys/405ep/405ep.h
create mode 100644 board/gdsys/405ep/neo.c
delete mode 100644 board/gdsys/neo/Makefile
delete mode 100644 board/gdsys/neo/neo.c
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index 8b80533..bea671e 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -28,12 +28,9 @@
#include <asm/ppc4xx-gpio.h>
#include <asm/global_data.h>
+#include "405ep.h"
#include <gdsys_fpga.h>
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
#define REFLECTION_TESTPATTERN 0xdede
#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
@@ -55,7 +52,6 @@ void print_fpga_state(unsigned dev)
int board_early_init_f(void)
{
unsigned k;
- unsigned ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->fpga_state[k] = 0;
@@ -73,26 +69,29 @@ int board_early_init_f(void)
* -> ca. 15 us
*/
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+ return 0;
+}
- /*
- * setup io-latches for reset
- */
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+int board_early_init_r(void)
+{
+ unsigned k;
+ unsigned ctr;
- /*
- * set "startup-finished"-gpios
- */
- gpio_write_bit(21, 0);
- gpio_write_bit(22, 1);
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->fpga_state[k] = 0;
/*
- * wait for fpga-done
+ * reset FPGA
*/
+ gd405ep_init();
+
+ gd405ep_set_fpga_reset(1);
+
+ gd405ep_setup_hw();
+
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
ctr = 0;
- while (!(in_le16((void *)LATCH2_BASE)
- & CONFIG_SYS_FPGA_DONE(k))) {
+ while (!gd405ep_get_fpga_done(k)) {
udelay(100000);
if (ctr++ > 5) {
gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
@@ -101,12 +100,9 @@ int board_early_init_f(void)
}
}
- /*
- * setup io-latches for boot (stop reset)
- */
udelay(10);
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+
+ gd405ep_set_fpga_reset(0);
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
diff --git a/board/gdsys/405ep/405ep.h b/board/gdsys/405ep/405ep.h
new file mode 100644
index 0000000..5647dbc
--- /dev/null
+++ b/board/gdsys/405ep/405ep.h
@@ -0,0 +1,10 @@
+#ifndef __405EP_H_
+#define __405EP_H_
+
+/* functions to be provided by board implementation */
+void gd405ep_init(void);
+void gd405ep_set_fpga_reset(unsigned state);
+void gd405ep_setup_hw(void);
+int gd405ep_get_fpga_done(unsigned fpga);
+
+#endif /* __405EP_H_ */
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
index feb5cec..38e5ea4 100644
--- a/board/gdsys/405ep/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
+COBJS-$(CONFIG_NEO) += neo.o
COBJS-$(CONFIG_IO) += io.o
COBJS-$(CONFIG_IOCON) += iocon.o
COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index f55afbd..adaffb2 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -27,15 +27,18 @@
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
+#include "405ep.h"
#include <gdsys_fpga.h>
#include "../common/osd.h"
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-#define LATCH2_MC2_PRESENT_N 0x0080
-
#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
+#define LATCH2_MC2_PRESENT_N 0x0080
+
enum {
UNITTYPE_VIDEO_USER = 0,
UNITTYPE_MAIN_USER = 1,
@@ -261,3 +264,32 @@ int last_stage_init(void)
return 0;
}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+}
+
+void gd405ep_setup_hw(void)
+{
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+ return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index db1ea7f..ac4cefd 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -29,8 +29,13 @@
#include <miiphy.h>
+#include "405ep.h"
#include <gdsys_fpga.h>
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
#define PHYREG_CONTROL 0
#define PHYREG_PAGE_ADDRESS 22
#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
@@ -175,3 +180,32 @@ int last_stage_init(void)
return 0;
}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+}
+
+void gd405ep_setup_hw(void)
+{
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+ return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index ce53340..ed27791 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -27,10 +27,15 @@
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
+#include "405ep.h"
#include <gdsys_fpga.h>
#include "../common/osd.h"
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
enum {
UNITTYPE_MAIN_SERVER = 0,
UNITTYPE_MAIN_USER = 1,
@@ -231,3 +236,32 @@ int fpga_gpio_get(int pin)
{
return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+}
+
+void gd405ep_setup_hw(void)
+{
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+ return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}
diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c
new file mode 100644
index 0000000..f38edd2
--- /dev/null
+++ b/board/gdsys/405ep/neo.c
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+enum {
+ UNITTYPE_CCX16 = 1,
+ UNITTYPE_CCIP216 = 2,
+};
+
+enum {
+ HWVER_300 = 3,
+};
+
+int misc_init_r(void)
+{
+ /* startup fans */
+ dtt_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts("Board: CATCenter Neo");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void print_fpga_info(void)
+{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+ u16 versions = in_le16(&fpga->versions);
+ u16 fpga_version = in_le16(&fpga->fpga_version);
+ u16 fpga_features = in_le16(&fpga->fpga_features);
+ int fpga_state = get_fpga_state(0);
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_channels;
+
+ puts("FPGA: ");
+ if (fpga_state & FPGA_STATE_DONE_FAILED) {
+ printf(" done timed out\n");
+ return;
+ }
+
+ if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
+ printf(" refelectione test failed\n");
+ return;
+ }
+
+ unit_type = (versions & 0xf000) >> 12;
+ hardware_version = versions & 0x000f;
+ feature_channels = fpga_features & 0x007f;
+
+ switch (unit_type) {
+ case UNITTYPE_CCX16:
+ printf("CCX-Switch");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_300:
+ printf(" HW-Ver 3.00-3.12\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %d channel(s)\n", feature_channels);
+}
+
+int last_stage_init(void)
+{
+ print_fpga_info();
+
+ return 0;
+}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+}
+
+void gd405ep_setup_hw(void)
+{
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+ /*
+ * Neo hardware has no FPGA-DONE GPIO
+ */
+ return 1;
+}
diff --git a/board/gdsys/neo/Makefile b/board/gdsys/neo/Makefile
deleted file mode 100644
index dc5b5b8..0000000
--- a/board/gdsys/neo/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o
-SOBJS =
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c
deleted file mode 100644
index d21d599..0000000
--- a/board/gdsys/neo/neo.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#define HWTYPE_CCX16 1
-#define HWREV_300 3
-
-int board_early_init_f(void)
-{
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks
- * -> ca. 15 us
- */
- mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
- u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2);
- u8 unit_type;
- u8 hardware_cpu_ports;
- u8 hardware_con_ports;
- u8 hardware_version;
-
- printf("Board: CATCenter Neo");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- puts("\n ");
-
- unit_type = (val & 0xf000) >> 12;
- hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8;
- hardware_con_ports = ((val & 0x00f0) >> 4) * 2;
- hardware_version = val & 0x000f;
-
- switch (unit_type) {
- case HWTYPE_CCX16:
- printf("CCX16-FPGA (80 UARTs)");
- break;
-
- default:
- printf("UnitType %d, unsupported", unit_type);
- break;
- }
-
- printf(", %d cpu ports, %d console ports,",
- hardware_cpu_ports, hardware_con_ports);
-
- switch (hardware_version) {
- case HWREV_300:
- printf(" HW-Ver 3.00\n");
- break;
-
- default:
- printf(" HW-Ver %d, unsupported\n",
- hardware_version);
- break;
- }
-
- return 0;
-}
diff --git a/boards.cfg b/boards.cfg
index 3cf75c3..24c5879 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -982,7 +982,7 @@ intip powerpc ppc4xx intip gdsys
io powerpc ppc4xx 405ep gdsys
io64 powerpc ppc4xx 405ex gdsys
iocon powerpc ppc4xx 405ep gdsys
-neo powerpc ppc4xx - gdsys
+neo powerpc ppc4xx 405ep gdsys
icon powerpc ppc4xx - mosaixtech
MIP405 powerpc ppc4xx mip405 mpl
MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 1468197..cd64e3a 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -37,7 +37,8 @@
#define CONFIG_IDENT_STRING " dlvision-10g 0.02"
#include "amcc-common.h"
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
diff --git a/include/configs/io.h b/include/configs/io.h
index 9d2a87d..fe07ca5 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -37,8 +37,9 @@
#define CONFIG_IDENT_STRING " io 0.04"
#include "amcc-common.h"
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
-#define CONFIG_LAST_STAGE_INIT /* call last_stage_init */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 9fcc643..bbf79e7 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -37,7 +37,8 @@
#define CONFIG_IDENT_STRING " iocon 0.03"
#include "amcc-common.h"
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 6559353..38b5bec 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -35,9 +35,13 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME neo
+#define CONFIG_IDENT_STRING " neo 0.01"
#include "amcc-common.h"
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@@ -149,53 +153,53 @@
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR 0xFFF00000
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
/*
* PPC405 GPIO Configuration
*/
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
-} \
+#define CONFIG_SYS_4xx_GPIO_TABLE { \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \
}
/*
@@ -226,12 +230,22 @@
#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_FPGA_BASE 0x7f100000
+#define CONFIG_SYS_FPGA0_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x92015480
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
+
+#define CONFIG_SYS_FPGA_COUNT 1
+
/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE 0x7f200000
#define CONFIG_SYS_EBC_PB3AP 0x92015480
#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_LATCH0_RESET 0xffff
+#define CONFIG_SYS_LATCH0_BOOT 0xffff
+#define CONFIG_SYS_LATCH1_RESET 0xffbf
+#define CONFIG_SYS_LATCH1_BOOT 0xffff
+
#endif /* __CONFIG_H */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 949864c..555fbe2 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -58,6 +58,17 @@ typedef struct ihs_osd {
u16 y_pos;
} ihs_osd_t;
+#ifdef CONFIG_NEO
+typedef struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_features; /* 0x0004 */
+ u16 fpga_version; /* 0x0006 */
+ u16 reserved_0[8187]; /* 0x0008 */
+ u16 reflection_high; /* 0x3ffe */
+} ihs_fpga_t;
+#endif
+
#ifdef CONFIG_IO
typedef struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
--
1.7.2.5
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v2 3/6] powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes
2012-04-26 13:54 [U-Boot] [PATCH 0/6] Various gdsys ppc4xx boards revised Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 1/6] powerpc/ppc4xx: Adjust environment size on neo Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 2/6] powerpc/ppc4xx: Make gdsys 405ep boards reset more generic Dirk Eibach
@ 2012-04-26 13:54 ` Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 4/6] powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 Dirk Eibach
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Dirk Eibach @ 2012-04-26 13:54 UTC (permalink / raw)
To: u-boot
Print fpga info at last_stage_init on gdsys 405ep boards.
Use dtt_init() to startup fans.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
---
Changes in v2:
- add Cc
- split up original patch series
board/gdsys/405ep/dlvision-10g.c | 28 ++++++++++++++++---------
board/gdsys/405ep/io.c | 41 +++++++++++++++++++++++++------------
board/gdsys/405ep/iocon.c | 34 ++++++++++++++++++-------------
include/configs/dlvision-10g.h | 2 +
include/configs/io.h | 2 +
5 files changed, 70 insertions(+), 37 deletions(-)
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index adaffb2..648c2ee 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -26,6 +26,7 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
#include "405ep.h"
#include <gdsys_fpga.h>
@@ -68,6 +69,14 @@ enum {
RAM_DDR2_64 = 2,
};
+int misc_init_r(void)
+{
+ /* startup fans */
+ dtt_init();
+
+ return 0;
+}
+
static unsigned int get_hwver(void)
{
u16 latch3 = in_le16((void *)LATCH3_BASE);
@@ -226,24 +235,19 @@ static void print_fpga_info(unsigned dev)
*/
int checkboard(void)
{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
+ char *s = getenv("serial#");
- printf("Board: ");
+ puts("Board: ");
- printf("DLVision 10G");
+ puts("DLVision 10G");
- if (i > 0) {
+ if (s != NULL) {
puts(", serial# ");
- puts(buf);
+ puts(s);
}
puts("\n");
- print_fpga_info(0);
- if (get_mc2_present())
- print_fpga_info(1);
-
return 0;
}
@@ -252,6 +256,10 @@ int last_stage_init(void)
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
+ print_fpga_info(0);
+ if (get_mc2_present())
+ print_fpga_info(1);
+
if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
return 0;
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index ac4cefd..85b61f1 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -27,6 +27,7 @@
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
#include <miiphy.h>
#include "405ep.h"
@@ -52,6 +53,14 @@ enum {
HWVER_122 = 3,
};
+int misc_init_r(void)
+{
+ /* startup fans */
+ dtt_init();
+
+ return 0;
+}
+
int configure_gbit_phy(unsigned char addr)
{
unsigned short value;
@@ -92,8 +101,22 @@ err_out:
*/
int checkboard(void)
{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
+ char *s = getenv("serial#");
+
+ puts("Board: CATCenter Io");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void print_fpga_info(void)
+{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
@@ -108,15 +131,7 @@ int checkboard(void)
feature_channels = fpga_features & 0x007f;
feature_expansion = fpga_features & (1<<15);
- printf("Board: ");
-
- printf("CATCenter Io");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- puts("\n ");
+ puts("FPGA: ");
switch (unit_type) {
case UNITTYPE_CCD_SWITCH:
@@ -157,8 +172,6 @@ int checkboard(void)
printf(" %d channel(s)", feature_channels);
printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-
- return 0;
}
/*
@@ -169,6 +182,8 @@ int last_stage_init(void)
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
unsigned int k;
+ print_fpga_info();
+
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
bb_miiphy_read, bb_miiphy_write);
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index ed27791..0ffdb38 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -74,8 +74,24 @@ enum {
*/
int checkboard(void)
{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
+ char *s = getenv("serial#");
+
+ puts("Board: ");
+
+ puts("IoCon");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void print_fpga_info(void)
+{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
@@ -100,16 +116,6 @@ int checkboard(void)
feature_carriers = (fpga_features & 0x000c) >> 2;
feature_video_channels = fpga_features & 0x0003;
- printf("Board: ");
-
- printf("IoCon");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- puts("\n ");
-
switch (unit_type) {
case UNITTYPE_MAIN_USER:
printf("Mainchannel");
@@ -210,12 +216,12 @@ int checkboard(void)
printf(", %d carrier(s)", feature_carriers);
printf(", %d video channel(s)\n", feature_video_channels);
-
- return 0;
}
int last_stage_init(void)
{
+ print_fpga_info();
+
return osd_probe(0);
}
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index cd64e3a..47f1061 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -39,6 +39,7 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@@ -81,6 +82,7 @@
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
/*
diff --git a/include/configs/io.h b/include/configs/io.h
index fe07ca5..ceae3f5 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -39,6 +39,7 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@@ -77,6 +78,7 @@
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
/*
--
1.7.2.5
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v2 4/6] powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20
2012-04-26 13:54 [U-Boot] [PATCH 0/6] Various gdsys ppc4xx boards revised Dirk Eibach
` (2 preceding siblings ...)
2012-04-26 13:54 ` [U-Boot] [PATCH v2 3/6] powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes Dirk Eibach
@ 2012-04-26 13:54 ` Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 5/6] powerpc/ppc4xx: Update gdsys board configurations Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 6/6] powerpc/ppc4xx: Fix typo in gdsys_fpga.h Dirk Eibach
5 siblings, 0 replies; 9+ messages in thread
From: Dirk Eibach @ 2012-04-26 13:54 UTC (permalink / raw)
To: u-boot
In hardware revision 1.20 one more fan controller is added to dlvision-10g.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
---
Changes in v2:
- add Cc
- split up original patch series
board/gdsys/405ep/dlvision-10g.c | 12 +++++++++++-
include/configs/dlvision-10g.h | 4 ++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index 648c2ee..d7e0d66 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -50,6 +50,8 @@ enum {
enum {
HWVER_101 = 0,
HWVER_110 = 1,
+ HWVER_120 = 2,
+ HWVER_130 = 3,
};
enum {
@@ -158,7 +160,15 @@ static void print_fpga_info(unsigned dev)
break;
case HWVER_110:
- printf(" HW-Ver 1.10\n");
+ printf(" HW-Ver 1.10-1.12\n");
+ break;
+
+ case HWVER_120:
+ printf(" HW-Ver 1.20\n");
+ break;
+
+ case HWVER_130:
+ printf(" HW-Ver 1.30\n");
break;
default:
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 47f1061..2cd2027 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -34,7 +34,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME dlvsion-10g
-#define CONFIG_IDENT_STRING " dlvision-10g 0.02"
+#define CONFIG_IDENT_STRING " dlvision-10g 0.03"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
@@ -118,7 +118,7 @@
/* Temp sensor/hwmon/dtt */
#define CONFIG_DTT_LM63 1 /* National LM63 */
-#define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */
+#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
#define CONFIG_DTT_PWM_LOOKUPTABLE \
{ { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
--
1.7.2.5
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v2 5/6] powerpc/ppc4xx: Update gdsys board configurations
2012-04-26 13:54 [U-Boot] [PATCH 0/6] Various gdsys ppc4xx boards revised Dirk Eibach
` (3 preceding siblings ...)
2012-04-26 13:54 ` [U-Boot] [PATCH v2 4/6] powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 Dirk Eibach
@ 2012-04-26 13:54 ` Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 6/6] powerpc/ppc4xx: Fix typo in gdsys_fpga.h Dirk Eibach
5 siblings, 0 replies; 9+ messages in thread
From: Dirk Eibach @ 2012-04-26 13:54 UTC (permalink / raw)
To: u-boot
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
---
Changes in v2:
- add Cc
- split up original patch series
include/configs/gdppc440etx.h | 4 ++++
include/configs/intip.h | 4 ++--
include/configs/io.h | 6 +++++-
include/configs/io64.h | 2 +-
include/configs/iocon.h | 6 +++++-
5 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
index 3c59ff4..9efbb8e 100644
--- a/include/configs/gdppc440etx.h
+++ b/include/configs/gdppc440etx.h
@@ -50,6 +50,10 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 92b65af..33364a8 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -37,10 +37,10 @@
#define CONFIG_460EX 1 /* Specific PPC460EX */
#ifdef CONFIG_DEVCONCENTER
#define CONFIG_HOSTNAME devconcenter
-#define CONFIG_IDENT_STRING " devconcenter 0.05"
+#define CONFIG_IDENT_STRING " devconcenter 0.06"
#else
#define CONFIG_HOSTNAME intip
-#define CONFIG_IDENT_STRING " intip 0.05"
+#define CONFIG_IDENT_STRING " intip 0.06"
#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
diff --git a/include/configs/io.h b/include/configs/io.h
index ceae3f5..03661cc 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -34,7 +34,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME io
-#define CONFIG_IDENT_STRING " io 0.04"
+#define CONFIG_IDENT_STRING " io 0.05"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
@@ -50,6 +50,10 @@
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
diff --git a/include/configs/io64.h b/include/configs/io64.h
index 51b2dd1..887aaef 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -53,7 +53,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME io64
-#define CONFIG_IDENT_STRING " io64 0.01"
+#define CONFIG_IDENT_STRING " io64 0.02"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index bbf79e7..7f8825b 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -34,7 +34,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME iocon
-#define CONFIG_IDENT_STRING " iocon 0.03"
+#define CONFIG_IDENT_STRING " iocon 0.04"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
@@ -49,6 +49,10 @@
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
--
1.7.2.5
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v2 6/6] powerpc/ppc4xx: Fix typo in gdsys_fpga.h
2012-04-26 13:54 [U-Boot] [PATCH 0/6] Various gdsys ppc4xx boards revised Dirk Eibach
` (4 preceding siblings ...)
2012-04-26 13:54 ` [U-Boot] [PATCH v2 5/6] powerpc/ppc4xx: Update gdsys board configurations Dirk Eibach
@ 2012-04-26 13:54 ` Dirk Eibach
5 siblings, 0 replies; 9+ messages in thread
From: Dirk Eibach @ 2012-04-26 13:54 UTC (permalink / raw)
To: u-boot
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
---
Changes in v2:
- add Cc
- split up original patch series
include/gdsys_fpga.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 555fbe2..bfa656f 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -115,7 +115,7 @@ typedef struct ihs_fpga {
u16 reserved_2[93]; /* 0x0044 */
u16 reflection_high; /* 0x00fe */
ihs_osd_t osd; /* 0x0100 */
- u16 reserved_3[88]; /* 0x010e */
+ u16 reserved_3[889]; /* 0x010e */
u16 videomem; /* 0x0800 */
} ihs_fpga_t;
#endif
--
1.7.2.5
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v2 2/6] powerpc/ppc4xx: Make gdsys 405ep boards reset more generic
2012-04-26 13:54 ` [U-Boot] [PATCH v2 2/6] powerpc/ppc4xx: Make gdsys 405ep boards reset more generic Dirk Eibach
@ 2012-04-26 16:08 ` Stefan Roese
0 siblings, 0 replies; 9+ messages in thread
From: Stefan Roese @ 2012-04-26 16:08 UTC (permalink / raw)
To: u-boot
HI Dirk,
On Thursday 26 April 2012 15:54:22 Dirk Eibach wrote:
> In order to add boards that have different hardware for fpga reset,
> any 405ep gdsys board now provides these functions:
>
> void gd405ep_init(void);
> void gd405ep_set_fpga_reset(unsigned state);
> void gd405ep_setup_hw(void);
> int gd405ep_get_fpga_done(unsigned fpga);
One comment below:
<snip>
> diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
> index 949864c..555fbe2 100644
> --- a/include/gdsys_fpga.h
> +++ b/include/gdsys_fpga.h
> @@ -58,6 +58,17 @@ typedef struct ihs_osd {
> u16 y_pos;
> } ihs_osd_t;
>
> +#ifdef CONFIG_NEO
> +typedef struct ihs_fpga {
> + u16 reflection_low; /* 0x0000 */
> + u16 versions; /* 0x0002 */
> + u16 fpga_features; /* 0x0004 */
> + u16 fpga_version; /* 0x0006 */
> + u16 reserved_0[8187]; /* 0x0008 */
> + u16 reflection_high; /* 0x3ffe */
> +} ihs_fpga_t;
> +#endif
checkpatch complains about typedef's. Please don't add more of them. I know
that you already have some in your files. It would be great if you could clean
this up with an follow-up patch, to remove all your local typedef's.
Thanks,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v2 1/6] powerpc/ppc4xx: Adjust environment size on neo
2012-04-26 13:54 ` [U-Boot] [PATCH v2 1/6] powerpc/ppc4xx: Adjust environment size on neo Dirk Eibach
@ 2012-04-30 13:10 ` Stefan Roese
0 siblings, 0 replies; 9+ messages in thread
From: Stefan Roese @ 2012-04-30 13:10 UTC (permalink / raw)
To: u-boot
On Thursday 26 April 2012 15:54:21 Dirk Eibach wrote:
> Environment size on neo has to be 0x20000 for compatibilty reasons.
Patch series (1...6) applied to u-boot-ppc4xx/master.
Thanks,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2012-04-30 13:10 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-04-26 13:54 [U-Boot] [PATCH 0/6] Various gdsys ppc4xx boards revised Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 1/6] powerpc/ppc4xx: Adjust environment size on neo Dirk Eibach
2012-04-30 13:10 ` Stefan Roese
2012-04-26 13:54 ` [U-Boot] [PATCH v2 2/6] powerpc/ppc4xx: Make gdsys 405ep boards reset more generic Dirk Eibach
2012-04-26 16:08 ` Stefan Roese
2012-04-26 13:54 ` [U-Boot] [PATCH v2 3/6] powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 4/6] powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 5/6] powerpc/ppc4xx: Update gdsys board configurations Dirk Eibach
2012-04-26 13:54 ` [U-Boot] [PATCH v2 6/6] powerpc/ppc4xx: Fix typo in gdsys_fpga.h Dirk Eibach
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