[PATCH 00/10] atl1c: update hardware settings - v4

[PATCH 00/10] atl1c: update hardware settings - v4

[xiong]

This update contains a serial of patches, most of them are hardware
settings related. register definitions are refined (or removed if
meaningless) for each patch.

This is the last patch set.

The patches have addressed all sparse and checkpatch warnings.

Following NICs are tested:
AR8131/AR8132/AR8151A/AR8152A/AR8152B
Test item includes:
build/install/uninstall/dhcp/ping/iperf/wol/reboot/etc.

xiong (10):
  atl1c: add workaround for issue of bit INTX-disable for MSI interrupt
  atl1c: add PHY link event(up/down) patch
  atl1c: clear WoL status when reset pcie
  atl1c: remove code of closing register writable attribution
  atl1c: refine mac address related code
  atl1c: enlarge L1 response waiting timer
  atl1c: cancel task when interface closed
  atl1c: do MAC-reset when PHY link down
  atl1c: Disable L0S when no cable link
  atl1c: remove PHY polling from atl1c_change_mtu

 drivers/net/ethernet/atheros/atl1c/atl1c.h      |    1 +
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c   |  141 ++++++++++++---------
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h   |   35 ++---
 drivers/net/ethernet/atheros/atl1c/atl1c_main.c |  153 +++++++++++++++++------
 drivers/pci/quirks.c                            |   12 ++
 5 files changed, 220 insertions(+), 122 deletions(-)

-- 
1.7.7

[PATCH 01/10] atl1c: add workaround for issue of bit INTX-disable for MSI interrupt

[xiong]

All supported devices have one issue that msi interrupt doesn't assert
if pci command register bit (PCI_COMMAND_INTX_DISABLE) is set.
Add workaround in drivers/pci/quirks.c

Signed-off-by: xiong <xiong@qca.qualcomm.com>
---
 drivers/pci/quirks.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 4bf7102..953ec3f 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2626,6 +2626,18 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
 			quirk_msi_intx_disable_bug);
 
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
+			quirk_msi_intx_disable_bug);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
+			quirk_msi_intx_disable_bug);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
+			quirk_msi_intx_disable_bug);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
+			quirk_msi_intx_disable_bug);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
+			quirk_msi_intx_disable_bug);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
+			quirk_msi_intx_disable_bug);
 #endif /* CONFIG_PCI_MSI */
 
 /* Allow manual resource allocation for PCI hotplug bridges
-- 
1.7.7

[PATCH 02/10] atl1c: add PHY link event(up/down) patch

[xiong]

On some platforms the PHY settings need to change depending on the
cable link status to get better stability.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
 drivers/net/ethernet/atheros/atl1c/atl1c.h      |    1 +
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c   |   37 +++++++++++++++
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h   |    1 +
 drivers/net/ethernet/atheros/atl1c/atl1c_main.c |   55 +++++++++++++++++++++++
 4 files changed, 94 insertions(+), 0 deletions(-)

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c.h b/drivers/net/ethernet/atheros/atl1c/atl1c.h
index acc2956..b2bf324 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c.h
@@ -436,6 +436,7 @@ struct atl1c_hw {
 	bool phy_configured;
 	bool re_autoneg;
 	bool emi_ca;
+	bool msi_lnkpatch;	/* link patch for specific platforms */
 };
 
 /*
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
index 07f017f..209c179 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
@@ -848,3 +848,40 @@ int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc)
 
 	return 0;
 }
+
+
+/* configure phy after Link change Event */
+void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed)
+{
+	u16 phy_val;
+	bool adj_thresh = false;
+
+	if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ||
+	    hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2)
+		adj_thresh = true;
+
+	if (link_speed != SPEED_0) { /* link up */
+		/* az with brcm, half-amp */
+		if (hw->nic_type == athr_l1d_2) {
+			atl1c_read_phy_ext(hw, MIIEXT_PCS, MIIEXT_CLDCTRL6,
+				&phy_val);
+			phy_val = FIELD_GETX(phy_val, CLDCTRL6_CAB_LEN);
+			phy_val = phy_val > CLDCTRL6_CAB_LEN_SHORT ?
+				AZ_ANADECT_LONG : AZ_ANADECT_DEF;
+			atl1c_write_phy_dbg(hw, MIIDBG_AZ_ANADECT, phy_val);
+		}
+		/* threshold adjust */
+		if (adj_thresh && link_speed == SPEED_100 && hw->msi_lnkpatch) {
+			atl1c_write_phy_dbg(hw, MIIDBG_MSE16DB, L1D_MSE16DB_UP);
+			atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL,
+				L1D_SYSMODCTRL_IECHOADJ_DEF);
+		}
+	} else { /* link down */
+		if (adj_thresh && hw->msi_lnkpatch) {
+			atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL,
+				SYSMODCTRL_IECHOADJ_DEF);
+			atl1c_write_phy_dbg(hw, MIIDBG_MSE16DB,
+				L1D_MSE16DB_DOWN);
+		}
+	}
+}
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index 0adb341..ea3f520 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -63,6 +63,7 @@ int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
 			u16 reg_addr, u16 phy_data);
 int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
 int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data);
+void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
 
 /* hw-ids */
 #define PCI_DEVICE_ID_ATTANSIC_L2C      0x1062
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 25b7b00..50df437 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -258,6 +258,7 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
 			if (netif_msg_hw(adapter))
 				dev_warn(&pdev->dev, "stop mac failed\n");
 		atl1c_set_aspm(hw, SPEED_0);
+		atl1c_post_phy_linkchg(hw, SPEED_0);
 		netif_carrier_off(netdev);
 		netif_stop_queue(netdev);
 	} else {
@@ -274,6 +275,7 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
 			adapter->link_speed  = speed;
 			adapter->link_duplex = duplex;
 			atl1c_set_aspm(hw, speed);
+			atl1c_post_phy_linkchg(hw, speed);
 			atl1c_start_mac(adapter);
 			if (netif_msg_link(adapter))
 				dev_info(&pdev->dev,
@@ -697,6 +699,57 @@ static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
 		hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
 	return 0;
 }
+
+struct atl1c_platform_patch {
+	u16 pci_vid;
+	u16 pci_did;
+	u8  pci_revid;
+	u16 subsystem_vid;
+	u16 subsystem_did;
+	u32 patch_flag;
+#define ATL1C_LINK_PATCH	0x1
+};
+static struct atl1c_platform_patch plats[] = {
+{0x1969, 0x2060, 0xC1, 0x1019, 0x8152, 0x1},
+{0x1969, 0x2060, 0xC1, 0x1019, 0x2060, 0x1},
+{0x1969, 0x2060, 0xC1, 0x1019, 0xE000, 0x1},
+{0x1969, 0x2062, 0xC0, 0x1019, 0x8152, 0x1},
+{0x1969, 0x2062, 0xC0, 0x1019, 0x2062, 0x1},
+{0x1969, 0x2062, 0xC0, 0x1458, 0xE000, 0x1},
+{0x1969, 0x2062, 0xC1, 0x1019, 0x8152, 0x1},
+{0x1969, 0x2062, 0xC1, 0x1019, 0x2062, 0x1},
+{0x1969, 0x2062, 0xC1, 0x1458, 0xE000, 0x1},
+{0x1969, 0x2062, 0xC1, 0x1565, 0x2802, 0x1},
+{0x1969, 0x2062, 0xC1, 0x1565, 0x2801, 0x1},
+{0x1969, 0x1073, 0xC0, 0x1019, 0x8151, 0x1},
+{0x1969, 0x1073, 0xC0, 0x1019, 0x1073, 0x1},
+{0x1969, 0x1073, 0xC0, 0x1458, 0xE000, 0x1},
+{0x1969, 0x1083, 0xC0, 0x1458, 0xE000, 0x1},
+{0x1969, 0x1083, 0xC0, 0x1019, 0x8151, 0x1},
+{0x1969, 0x1083, 0xC0, 0x1019, 0x1083, 0x1},
+{0x1969, 0x1083, 0xC0, 0x1462, 0x7680, 0x1},
+{0x1969, 0x1083, 0xC0, 0x1565, 0x2803, 0x1},
+{0},
+};
+
+static void __devinit atl1c_patch_assign(struct atl1c_hw *hw)
+{
+	int i = 0;
+
+	hw->msi_lnkpatch = false;
+
+	while (plats[i].pci_vid != 0) {
+		if (plats[i].pci_vid == hw->vendor_id &&
+		    plats[i].pci_did == hw->device_id &&
+		    plats[i].pci_revid == hw->revision_id &&
+		    plats[i].subsystem_vid == hw->subsystem_vendor_id &&
+		    plats[i].subsystem_did == hw->subsystem_id) {
+			if (plats[i].patch_flag & ATL1C_LINK_PATCH)
+				hw->msi_lnkpatch = true;
+		}
+		i++;
+	}
+}
 /*
  * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  * @adapter: board private structure to initialize
@@ -732,6 +785,8 @@ static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
 		dev_err(&pdev->dev, "set mac function pointers failed\n");
 		return -1;
 	}
+	atl1c_patch_assign(hw);
+
 	hw->intr_mask = IMR_NORMAL_MASK;
 	hw->phy_configured = false;
 	hw->preamble_len = 7;
-- 
1.7.7

[PATCH 03/10] atl1c: clear WoL status when reset pcie

[xiong]

WoL status is read-clear and should be cleared when in S0
status.
putting it in atl1c_reset_pcie is more suitable than
in atl1c_get_permanent_address.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c   |    5 -----
 drivers/net/ethernet/atheros/atl1c/atl1c_main.c |    3 +++
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
index 209c179..49f433e 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
@@ -73,7 +73,6 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
 	u32 otp_ctrl_data;
 	u32 twsi_ctrl_data;
 	u32 ltssm_ctrl_data;
-	u32 wol_data;
 	u8  eth_addr[ETH_ALEN];
 	u16 phy_data;
 	bool raise_vol = false;
@@ -114,10 +113,6 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
 		ltssm_ctrl_data &= ~LTSSM_ID_EN_WRO;
 		AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, ltssm_ctrl_data);
 
-		/* clear any WOL settings */
-		AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
-		AT_READ_REG(hw, REG_WOL_CTRL, &wol_data);
-
 
 		AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
 		twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 50df437..6552913 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -133,6 +133,9 @@ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
 	 */
 	pci_enable_wake(pdev, PCI_D3hot, 0);
 	pci_enable_wake(pdev, PCI_D3cold, 0);
+	/* wol sts read-clear */
+	AT_READ_REG(hw, REG_WOL_CTRL, &data);
+	AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
 
 	/*
 	 * Mask some pcie error bits
-- 
1.7.7

[PATCH 04/10] atl1c: remove code of closing register writable attribution

[xiong]

The Close-action is done by atl1c_reset_pcie, remove it from
atl1c_get_permanent_address.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
index 49f433e..2522685 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
@@ -72,7 +72,6 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
 	u32 i;
 	u32 otp_ctrl_data;
 	u32 twsi_ctrl_data;
-	u32 ltssm_ctrl_data;
 	u8  eth_addr[ETH_ALEN];
 	u16 phy_data;
 	bool raise_vol = false;
@@ -108,11 +107,6 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
 			udelay(20);
 			raise_vol = true;
 		}
-		/* close open bit of ReadOnly*/
-		AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &ltssm_ctrl_data);
-		ltssm_ctrl_data &= ~LTSSM_ID_EN_WRO;
-		AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, ltssm_ctrl_data);
-
 
 		AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
 		twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
-- 
1.7.7

[PATCH 05/10] atl1c: refine mac address related code

[xiong]

On some platform with EEPROM/OTP existing, the BIOS could overwrite
a new MAC address for the NIC. so, the permanent mac address should
be from BIOS. the address is restored when driver removing.
Voltage raising isn't applicable for l1d.
Replace swab32 with htonl for big/little endian platform.
related Registers are refined as well.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c   |   93 ++++++++++-------------
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h   |   32 +++-----
 drivers/net/ethernet/atheros/atl1c/atl1c_main.c |    6 +-
 3 files changed, 57 insertions(+), 74 deletions(-)

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
index 2522685..ff9c738 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
@@ -43,7 +43,7 @@ int atl1c_check_eeprom_exist(struct atl1c_hw *hw)
 	return 0;
 }
 
-void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
+void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr)
 {
 	u32 value;
 	/*
@@ -51,33 +51,48 @@ void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
 	 * 0:  6AF600DC 1: 000B
 	 * low dword
 	 */
-	value = (((u32)hw->mac_addr[2]) << 24) |
-		(((u32)hw->mac_addr[3]) << 16) |
-		(((u32)hw->mac_addr[4]) << 8)  |
-		(((u32)hw->mac_addr[5])) ;
+	value = mac_addr[2] << 24 |
+		mac_addr[3] << 16 |
+		mac_addr[4] << 8  |
+		mac_addr[5];
 	AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
 	/* hight dword */
-	value = (((u32)hw->mac_addr[0]) << 8) |
-		(((u32)hw->mac_addr[1])) ;
+	value = mac_addr[0] << 8 |
+		mac_addr[1];
 	AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
 }
 
+/* read mac address from hardware register */
+static bool atl1c_read_current_addr(struct atl1c_hw *hw, u8 *eth_addr)
+{
+	u32 addr[2];
+
+	AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
+	AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
+
+	*(u32 *) &eth_addr[2] = htonl(addr[0]);
+	*(u16 *) &eth_addr[0] = htons((u16)addr[1]);
+
+	return is_valid_ether_addr(eth_addr);
+}
+
 /*
  * atl1c_get_permanent_address
  * return 0 if get valid mac address,
  */
 static int atl1c_get_permanent_address(struct atl1c_hw *hw)
 {
-	u32 addr[2];
 	u32 i;
 	u32 otp_ctrl_data;
 	u32 twsi_ctrl_data;
-	u8  eth_addr[ETH_ALEN];
 	u16 phy_data;
 	bool raise_vol = false;
 
+	/* MAC-address from BIOS is the 1st priority */
+	if (atl1c_read_current_addr(hw, hw->perm_mac_addr))
+		return 0;
+
 	/* init */
-	addr[0] = addr[1] = 0;
 	AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
 	if (atl1c_check_eeprom_exist(hw)) {
 		if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
@@ -89,21 +104,14 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
 				msleep(1);
 			}
 		}
-
-		if (hw->nic_type == athr_l2c_b ||
-		    hw->nic_type == athr_l2c_b2 ||
-		    hw->nic_type == athr_l1d) {
-			atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
-			if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
-				goto out;
-			phy_data &= 0xFF7F;
-			atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
-
-			atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
-			if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
-				goto out;
-			phy_data |= 0x8;
-			atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
+		/* raise voltage temporally for l2cb */
+		if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) {
+			atl1c_read_phy_dbg(hw, MIIDBG_ANACTRL, &phy_data);
+			phy_data &= ~ANACTRL_HB_EN;
+			atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, phy_data);
+			atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data);
+			phy_data |= VOLT_CTRL_SWLOWEST;
+			atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data);
 			udelay(20);
 			raise_vol = true;
 		}
@@ -127,37 +135,18 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
 		msleep(1);
 	}
 	if (raise_vol) {
-		if (hw->nic_type == athr_l2c_b ||
-		    hw->nic_type == athr_l2c_b2 ||
-		    hw->nic_type == athr_l1d ||
-		    hw->nic_type == athr_l1d_2) {
-			atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
-			if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
-				goto out;
-			phy_data |= 0x80;
-			atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
-
-			atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
-			if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
-				goto out;
-			phy_data &= 0xFFF7;
-			atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
-			udelay(20);
-		}
+		atl1c_read_phy_dbg(hw, MIIDBG_ANACTRL, &phy_data);
+		phy_data |= ANACTRL_HB_EN;
+		atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, phy_data);
+		atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data);
+		phy_data &= ~VOLT_CTRL_SWLOWEST;
+		atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data);
+		udelay(20);
 	}
 
-	/* maybe MAC-address is from BIOS */
-	AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
-	AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
-	*(u32 *) &eth_addr[2] = swab32(addr[0]);
-	*(u16 *) &eth_addr[0] = swab16(*(u16 *)&addr[1]);
-
-	if (is_valid_ether_addr(eth_addr)) {
-		memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
+	if (atl1c_read_current_addr(hw, hw->perm_mac_addr))
 		return 0;
-	}
 
-out:
 	return -1;
 }
 
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index ea3f520..21a5bc1 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -36,7 +36,7 @@ struct atl1c_hw;
 
 /* function prototype */
 void atl1c_phy_disable(struct atl1c_hw *hw);
-void atl1c_hw_set_mac_addr(struct atl1c_hw *hw);
+void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr);
 int atl1c_phy_reset(struct atl1c_hw *hw);
 int atl1c_read_mac_addr(struct atl1c_hw *hw);
 int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex);
@@ -94,25 +94,17 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
 #define REG_DEV_SERIAL_NUM_EN_SHIFT	1
 
 #define REG_TWSI_CTRL               	0x218
+#define TWSI_CTLR_FREQ_MASK		0x3UL
+#define TWSI_CTRL_FREQ_SHIFT		24
+#define TWSI_CTRL_FREQ_100K		0
+#define TWSI_CTRL_FREQ_200K		1
+#define TWSI_CTRL_FREQ_300K		2
+#define TWSI_CTRL_FREQ_400K		3
+#define TWSI_CTRL_LD_EXIST		BIT(23)
+#define TWSI_CTRL_HW_LDSTAT		BIT(12)	/* 0:finish,1:in progress */
+#define TWSI_CTRL_SW_LDSTART            BIT(11)
 #define TWSI_CTRL_LD_OFFSET_MASK        0xFF
 #define TWSI_CTRL_LD_OFFSET_SHIFT       0
-#define TWSI_CTRL_LD_SLV_ADDR_MASK      0x7
-#define TWSI_CTRL_LD_SLV_ADDR_SHIFT     8
-#define TWSI_CTRL_SW_LDSTART            0x800
-#define TWSI_CTRL_HW_LDSTART            0x1000
-#define TWSI_CTRL_SMB_SLV_ADDR_MASK     0x7F
-#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT    15
-#define TWSI_CTRL_LD_EXIST              0x400000
-#define TWSI_CTRL_READ_FREQ_SEL_MASK    0x3
-#define TWSI_CTRL_READ_FREQ_SEL_SHIFT   23
-#define TWSI_CTRL_FREQ_SEL_100K         0
-#define TWSI_CTRL_FREQ_SEL_200K         1
-#define TWSI_CTRL_FREQ_SEL_300K         2
-#define TWSI_CTRL_FREQ_SEL_400K         3
-#define TWSI_CTRL_SMB_SLV_ADDR
-#define TWSI_CTRL_WRITE_FREQ_SEL_MASK   0x3
-#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT  24
-
 
 #define REG_PCIE_DEV_MISC_CTRL      	0x21C
 #define PCIE_DEV_MISC_EXT_PIPE     	0x2
@@ -135,7 +127,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
 #define L2CB1_PCIE_PHYMISC2_CDR_BW	3
 
 #define REG_TWSI_DEBUG			0x1108
-#define TWSI_DEBUG_DEV_EXIST		0x20000000
+#define TWSI_DEBUG_DEV_EXIST		BIT(29)
 
 #define REG_DMA_DBG			0x1114
 #define DMA_DBG_VENDOR_MSG		BIT(0)
@@ -151,7 +143,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
 #define REG_EEPROM_DATA_LO		0x12C4
 
 #define REG_OTP_CTRL			0x12F0
-#define OTP_CTRL_CLK_EN			0x0002
+#define OTP_CTRL_CLK_EN			BIT(1)
 
 #define REG_PM_CTRL			0x12F8
 #define PM_CTRL_HOTRST			BIT(31)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 6552913..8fee1fc 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -463,7 +463,7 @@ static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
 	memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
 	netdev->addr_assign_type &= ~NET_ADDR_RANDOM;
 
-	atl1c_hw_set_mac_addr(&adapter->hw);
+	atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
 
 	return 0;
 }
@@ -2536,7 +2536,7 @@ static int __devinit atl1c_probe(struct pci_dev *pdev,
 		dev_dbg(&pdev->dev, "mac address : %pM\n",
 			adapter->hw.mac_addr);
 
-	atl1c_hw_set_mac_addr(&adapter->hw);
+	atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
 	INIT_WORK(&adapter->common_task, atl1c_common_task);
 	adapter->work_event = 0;
 	err = register_netdev(netdev);
@@ -2580,6 +2580,8 @@ static void __devexit atl1c_remove(struct pci_dev *pdev)
 	struct atl1c_adapter *adapter = netdev_priv(netdev);
 
 	unregister_netdev(netdev);
+	/* restore permanent address */
+	atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.perm_mac_addr);
 	atl1c_phy_disable(&adapter->hw);
 
 	iounmap(adapter->hw.hw_addr);
-- 
1.7.7

[PATCH 06/10] atl1c: enlarge L1 response waiting timer

[xiong]

The hardware incorrectly process L0S/L1 entrance if the chipset/root
response after specific/shorter timer and cause system hang.
Enlarge the timeout value to avoid this issue.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index 21a5bc1..17d935b 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -157,7 +157,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
 #define PM_CTRL_PM_REQ_TIMER_MASK	0xFUL
 #define PM_CTRL_PM_REQ_TIMER_SHIFT	20	/* pm_request_l1 time > @
 						 * ->L0s not L1 */
-#define PM_CTRL_PM_REQ_TO_DEF		0xC
+#define PM_CTRL_PM_REQ_TO_DEF		0xF
 #define PMCTRL_TXL1_AFTER_L0S		BIT(19)	/* l1dv2.0+ */
 #define L1D_PMCTRL_L1_ENTRY_TM_MASK	7UL	/* l1dv2.0+, 3bits */
 #define L1D_PMCTRL_L1_ENTRY_TM_SHIFT	16
-- 
1.7.7

[PATCH 07/10] atl1c: cancel task when interface closed

[xiong]

common_task might be running while close routine is called,
wait/cancel it.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
 drivers/net/ethernet/atheros/atl1c/atl1c_main.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 8fee1fc..e082901 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -330,6 +330,9 @@ static void atl1c_common_task(struct work_struct *work)
 	adapter = container_of(work, struct atl1c_adapter, common_task);
 	netdev = adapter->netdev;
 
+	if (test_bit(__AT_DOWN, &adapter->flags))
+		return;
+
 	if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
 		netif_device_detach(netdev);
 		atl1c_down(adapter);
@@ -2313,6 +2316,8 @@ static int atl1c_close(struct net_device *netdev)
 	struct atl1c_adapter *adapter = netdev_priv(netdev);
 
 	WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
+	set_bit(__AT_DOWN, &adapter->flags);
+	cancel_work_sync(&adapter->common_task);
 	atl1c_down(adapter);
 	atl1c_free_ring_resources(adapter);
 	return 0;
-- 
1.7.7

[PATCH 08/10] atl1c: do MAC-reset when PHY link down

[xiong]

There may be tx-skbs still pending in HW when PHY link down.
Reset MAC will make the DMA engine go to the start point.
and release all pending skbs.
Note: Reset MAC will clear any interrupt status and mask.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
 drivers/net/ethernet/atheros/atl1c/atl1c_main.c |   74 ++++++++++++++--------
 1 files changed, 47 insertions(+), 27 deletions(-)

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index e082901..f410d84 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -60,6 +60,10 @@ static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
 		   int *work_done, int work_to_do);
 static int atl1c_up(struct atl1c_adapter *adapter);
 static void atl1c_down(struct atl1c_adapter *adapter);
+static int atl1c_reset_mac(struct atl1c_hw *hw);
+static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter);
+static int atl1c_configure(struct atl1c_adapter *adapter);
+static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter);
 
 static const u16 atl1c_pay_load_size[] = {
 	128, 256, 512, 1024, 2048, 4096,
@@ -256,14 +260,16 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
 
 	if ((phy_data & BMSR_LSTATUS) == 0) {
 		/* link down */
+		netif_carrier_off(netdev);
+		netif_stop_queue(netdev);
 		hw->hibernate = true;
-		if (atl1c_stop_mac(hw) != 0)
+		if (atl1c_reset_mac(hw) != 0)
 			if (netif_msg_hw(adapter))
-				dev_warn(&pdev->dev, "stop mac failed\n");
+				dev_warn(&pdev->dev, "reset mac failed\n");
 		atl1c_set_aspm(hw, SPEED_0);
 		atl1c_post_phy_linkchg(hw, SPEED_0);
-		netif_carrier_off(netdev);
-		netif_stop_queue(netdev);
+		atl1c_reset_dma_ring(adapter);
+		atl1c_configure(adapter);
 	} else {
 		/* Link Up */
 		hw->hibernate = false;
@@ -341,8 +347,11 @@ static void atl1c_common_task(struct work_struct *work)
 	}
 
 	if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
-		&adapter->work_event))
+		&adapter->work_event)) {
+		atl1c_irq_disable(adapter);
 		atl1c_check_link_status(adapter);
+		atl1c_irq_enable(adapter);
+	}
 }
 
 
@@ -1232,9 +1241,6 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
 	struct pci_dev *pdev = adapter->pdev;
 	u32 ctrl_data = 0;
 
-	AT_WRITE_REG(hw, REG_IMR, 0);
-	AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
-
 	atl1c_stop_mac(hw);
 	/*
 	 * Issue Soft Reset to the MAC.  This will reset the chip's
@@ -1373,7 +1379,7 @@ static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
  *
  * Configure the Tx /Rx unit of the MAC after a reset.
  */
-static int atl1c_configure(struct atl1c_adapter *adapter)
+static int atl1c_configure_mac(struct atl1c_adapter *adapter)
 {
 	struct atl1c_hw *hw = &adapter->hw;
 	u32 master_ctrl_data = 0;
@@ -1436,6 +1442,25 @@ static int atl1c_configure(struct atl1c_adapter *adapter)
 	return 0;
 }
 
+static int atl1c_configure(struct atl1c_adapter *adapter)
+{
+	struct net_device *netdev = adapter->netdev;
+	int num;
+
+	atl1c_init_ring_ptrs(adapter);
+	atl1c_set_multi(netdev);
+	atl1c_restore_vlan(adapter);
+
+	num = atl1c_alloc_rx_buffer(adapter);
+	if (unlikely(num == 0))
+		return -ENOMEM;
+
+	if (atl1c_configure_mac(adapter))
+		return -EIO;
+
+	return 0;
+}
+
 static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
 {
 	u16 hw_reg_addr = 0;
@@ -2196,41 +2221,38 @@ static int atl1c_request_irq(struct atl1c_adapter *adapter)
 	return err;
 }
 
+
+static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter)
+{
+	/* release tx-pending skbs and reset tx/rx ring index */
+	atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
+	atl1c_clean_tx_ring(adapter, atl1c_trans_high);
+	atl1c_clean_rx_ring(adapter);
+}
+
 static int atl1c_up(struct atl1c_adapter *adapter)
 {
 	struct net_device *netdev = adapter->netdev;
-	int num;
 	int err;
 
 	netif_carrier_off(netdev);
-	atl1c_init_ring_ptrs(adapter);
-	atl1c_set_multi(netdev);
-	atl1c_restore_vlan(adapter);
 
-	num = atl1c_alloc_rx_buffer(adapter);
-	if (unlikely(num == 0)) {
-		err = -ENOMEM;
-		goto err_alloc_rx;
-	}
-
-	if (atl1c_configure(adapter)) {
-		err = -EIO;
+	err = atl1c_configure(adapter);
+	if (unlikely(err))
 		goto err_up;
-	}
 
 	err = atl1c_request_irq(adapter);
 	if (unlikely(err))
 		goto err_up;
 
+	atl1c_check_link_status(adapter);
 	clear_bit(__AT_DOWN, &adapter->flags);
 	napi_enable(&adapter->napi);
 	atl1c_irq_enable(adapter);
-	atl1c_check_link_status(adapter);
 	netif_start_queue(netdev);
 	return err;
 
 err_up:
-err_alloc_rx:
 	atl1c_clean_rx_ring(adapter);
 	return err;
 }
@@ -2256,9 +2278,7 @@ static void atl1c_down(struct atl1c_adapter *adapter)
 
 	adapter->link_speed = SPEED_0;
 	adapter->link_duplex = -1;
-	atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
-	atl1c_clean_tx_ring(adapter, atl1c_trans_high);
-	atl1c_clean_rx_ring(adapter);
+	atl1c_reset_dma_ring(adapter);
 }
 
 /*
-- 
1.7.7

[PATCH 09/10] atl1c: Disable L0S when no cable link

[xiong]

L0S might be unstable if no cable link, only enable it when link up.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
 drivers/net/ethernet/atheros/atl1c/atl1c_main.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index f410d84..1cdd898 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -1328,7 +1328,7 @@ static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
 	}
 
 	/* L0S/L1 enable */
-	if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
+	if ((hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT) && link_speed != SPEED_0)
 		pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
 	if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
 		pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
-- 
1.7.7

[PATCH 10/10] atl1c: remove PHY polling from atl1c_change_mtu

[xiong]

PHY polling code for FPGA is considered in every MDIO R/W API.
no need to add additional code to atl1c_change_mtu.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: David Liu <dwliu@qca.qaulcomm.com>
---
 drivers/net/ethernet/atheros/atl1c/atl1c_main.c |    8 --------
 1 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 1cdd898..86630a5 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -553,14 +553,6 @@ static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
 		netdev_update_features(netdev);
 		atl1c_up(adapter);
 		clear_bit(__AT_RESETTING, &adapter->flags);
-		if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
-			u32 phy_data;
-
-			AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
-			phy_data |= 0x10000000;
-			AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
-		}
-
 	}
 	return 0;
 }
-- 
1.7.7

Re: [PATCH 01/10] atl1c: add workaround for issue of bit INTX-disable for MSI interrupt

[Luis R. Rodriguez]

On Sat, Apr 28, 2012 at 09:58:36AM +0800, xiong wrote:
> All supported devices have one issue that msi interrupt doesn't assert
> if pci command register bit (PCI_COMMAND_INTX_DISABLE) is set.
> Add workaround in drivers/pci/quirks.c
> 
> Signed-off-by: xiong <xiong@qca.qualcomm.com>
> ---
>  drivers/pci/quirks.c |   12 ++++++++++++
>  1 files changed, 12 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 4bf7102..953ec3f 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -2626,6 +2626,18 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
>  			quirk_msi_intx_disable_bug);
>  
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
> +			quirk_msi_intx_disable_bug);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
> +			quirk_msi_intx_disable_bug);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
> +			quirk_msi_intx_disable_bug);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
> +			quirk_msi_intx_disable_bug);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
> +			quirk_msi_intx_disable_bug);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
> +			quirk_msi_intx_disable_bug);
>  #endif /* CONFIG_PCI_MSI */

Xiong -- just a heads up, I think to backport these then you can
send me patches for compat-wireless to do the work around itself on
the driver on a patch under patches/ you can say create a 
58-drivers-pci-quirks.patch which pathces your driver there.

  Luis

RE: [PATCH 01/10] atl1c: add workaround for issue of bit INTX-disable for MSI interrupt

[Huang, Xiong]

Thanks Luis,  just one question:

I don't know which kernel version contains the updated pci/quirks.c, so, 
if I write the patch file (a 58-drivers-pci-quirks.patch) as:

--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c

+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22))
+	pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
+#endif


It seems not good for the kernel with updated pci/quirks.c

Any better suggestion ? thanks


-Xiong

> -----Original Message-----
> From: Luis R. Rodriguez [mailto:mcgrof@gmail.com] On Behalf Of Luis R.
> Rodriguez
> Sent: Saturday, April 28, 2012 10:05
> To: Huang, Xiong
> Cc: davem@davemloft.net; netdev@vger.kernel.org; linux-
> kernel@vger.kernel.org; qca-linux-team; nic-devel
> Subject: Re: [PATCH 01/10] atl1c: add workaround for issue of bit INTX-disable
> for MSI interrupt
> 
> On Sat, Apr 28, 2012 at 09:58:36AM +0800, xiong wrote:
> > All supported devices have one issue that msi interrupt doesn't assert
> > if pci command register bit (PCI_COMMAND_INTX_DISABLE) is set.
> > Add workaround in drivers/pci/quirks.c
> >
> > Signed-off-by: xiong <xiong@qca.qualcomm.com>
> > ---
> >  drivers/pci/quirks.c |   12 ++++++++++++
> >  1 files changed, 12 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > 4bf7102..953ec3f 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -2626,6 +2626,18 @@
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,
> > 0x4374,  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
> >  			quirk_msi_intx_disable_bug);
> >
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
> > +			quirk_msi_intx_disable_bug);
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
> > +			quirk_msi_intx_disable_bug);
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
> > +			quirk_msi_intx_disable_bug);
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
> > +			quirk_msi_intx_disable_bug);
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
> > +			quirk_msi_intx_disable_bug);
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
> > +			quirk_msi_intx_disable_bug);
> >  #endif /* CONFIG_PCI_MSI */
> 
> Xiong -- just a heads up, I think to backport these then you can send me patches
> for compat-wireless to do the work around itself on the driver on a patch under
> patches/ you can say create a 58-drivers-pci-quirks.patch which pathces your
> driver there.
> 
>   Luis

Re: [PATCH 01/10] atl1c: add workaround for issue of bit INTX-disable for MSI interrupt

[Luis R. Rodriguez]

On Sat, Apr 28, 2012 at 2:53 AM, Huang, Xiong <xiong@qca.qualcomm.com> wrote:
> Thanks Luis,  just one question:
>
> I don't know which kernel version contains the updated pci/quirks.c, so,
> if I write the patch file (a 58-drivers-pci-quirks.patch) as:
>
> --- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
> +++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
>
> +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22))
> +       pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
> +#endif
>
>
> It seems not good for the kernel with updated pci/quirks.c
>
> Any better suggestion ? thanks

That looks good for the backport, you would just ifdef around <
KERNEL_VERSION(3,5,0)

  Luis

Re: [PATCH 02/10] atl1c: add PHY link event(up/down) patch

[Florian Fainelli]

Hi Xiong,

Le samedi 28 avril 2012 03:58:37, xiong a écrit :
> On some platforms the PHY settings need to change depending on the
> cable link status to get better stability.
> 
> Signed-off-by: xiong <xiong@qca.qualcomm.com>
> Tested-by: Liu David <dwliu@qca.qualcomm.com>
> ---
>  drivers/net/ethernet/atheros/atl1c/atl1c.h      |    1 +
>  drivers/net/ethernet/atheros/atl1c/atl1c_hw.c   |   37 +++++++++++++++
>  drivers/net/ethernet/atheros/atl1c/atl1c_hw.h   |    1 +
>  drivers/net/ethernet/atheros/atl1c/atl1c_main.c |   55
> +++++++++++++++++++++++ 4 files changed, 94 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c.h
> b/drivers/net/ethernet/atheros/atl1c/atl1c.h index acc2956..b2bf324 100644
> --- a/drivers/net/ethernet/atheros/atl1c/atl1c.h
> +++ b/drivers/net/ethernet/atheros/atl1c/atl1c.h
> @@ -436,6 +436,7 @@ struct atl1c_hw {
>  	bool phy_configured;
>  	bool re_autoneg;
>  	bool emi_ca;
> +	bool msi_lnkpatch;	/* link patch for specific platforms */
>  };
> 
>  /*
> diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
> b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c index 07f017f..209c179
> 100644
> --- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
> +++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
> @@ -848,3 +848,40 @@ int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc)
> 
>  	return 0;
>  }
> +
> +
> +/* configure phy after Link change Event */
> +void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed)
> +{
> +	u16 phy_val;
> +	bool adj_thresh = false;
> +
> +	if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ||
> +	    hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2)
> +		adj_thresh = true;
> +
> +	if (link_speed != SPEED_0) { /* link up */
> +		/* az with brcm, half-amp */
> +		if (hw->nic_type == athr_l1d_2) {
> +			atl1c_read_phy_ext(hw, MIIEXT_PCS, MIIEXT_CLDCTRL6,
> +				&phy_val);
> +			phy_val = FIELD_GETX(phy_val, CLDCTRL6_CAB_LEN);
> +			phy_val = phy_val > CLDCTRL6_CAB_LEN_SHORT ?
> +				AZ_ANADECT_LONG : AZ_ANADECT_DEF;
> +			atl1c_write_phy_dbg(hw, MIIDBG_AZ_ANADECT, phy_val);
> +		}
> +		/* threshold adjust */
> +		if (adj_thresh && link_speed == SPEED_100 && hw->msi_lnkpatch) {
> +			atl1c_write_phy_dbg(hw, MIIDBG_MSE16DB, L1D_MSE16DB_UP);
> +			atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL,
> +				L1D_SYSMODCTRL_IECHOADJ_DEF);
> +		}
> +	} else { /* link down */
> +		if (adj_thresh && hw->msi_lnkpatch) {
> +			atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL,
> +				SYSMODCTRL_IECHOADJ_DEF);
> +			atl1c_write_phy_dbg(hw, MIIDBG_MSE16DB,
> +				L1D_MSE16DB_DOWN);
> +		}
> +	}
> +}
> diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
> b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h index 0adb341..ea3f520
> 100644
> --- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
> +++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
> @@ -63,6 +63,7 @@ int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
>  			u16 reg_addr, u16 phy_data);
>  int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
>  int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data);
> +void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
> 
>  /* hw-ids */
>  #define PCI_DEVICE_ID_ATTANSIC_L2C      0x1062
> diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
> b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c index 25b7b00..50df437
> 100644
> --- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
> +++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
> @@ -258,6 +258,7 @@ static void atl1c_check_link_status(struct
> atl1c_adapter *adapter) if (netif_msg_hw(adapter))
>  				dev_warn(&pdev->dev, "stop mac failed\n");
>  		atl1c_set_aspm(hw, SPEED_0);
> +		atl1c_post_phy_linkchg(hw, SPEED_0);
>  		netif_carrier_off(netdev);
>  		netif_stop_queue(netdev);
>  	} else {
> @@ -274,6 +275,7 @@ static void atl1c_check_link_status(struct
> atl1c_adapter *adapter) adapter->link_speed  = speed;
>  			adapter->link_duplex = duplex;
>  			atl1c_set_aspm(hw, speed);
> +			atl1c_post_phy_linkchg(hw, speed);
>  			atl1c_start_mac(adapter);
>  			if (netif_msg_link(adapter))
>  				dev_info(&pdev->dev,
> @@ -697,6 +699,57 @@ static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
>  		hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
>  	return 0;
>  }
> +
> +struct atl1c_platform_patch {
> +	u16 pci_vid;
> +	u16 pci_did;
> +	u8  pci_revid;
> +	u16 subsystem_vid;
> +	u16 subsystem_did;
> +	u32 patch_flag;
> +#define ATL1C_LINK_PATCH	0x1
> +};
> +static struct atl1c_platform_patch plats[] = {

This should be static const.

> +{0x1969, 0x2060, 0xC1, 0x1019, 0x8152, 0x1},
> +{0x1969, 0x2060, 0xC1, 0x1019, 0x2060, 0x1},
> +{0x1969, 0x2060, 0xC1, 0x1019, 0xE000, 0x1},
> +{0x1969, 0x2062, 0xC0, 0x1019, 0x8152, 0x1},
> +{0x1969, 0x2062, 0xC0, 0x1019, 0x2062, 0x1},
> +{0x1969, 0x2062, 0xC0, 0x1458, 0xE000, 0x1},
> +{0x1969, 0x2062, 0xC1, 0x1019, 0x8152, 0x1},
> +{0x1969, 0x2062, 0xC1, 0x1019, 0x2062, 0x1},
> +{0x1969, 0x2062, 0xC1, 0x1458, 0xE000, 0x1},
> +{0x1969, 0x2062, 0xC1, 0x1565, 0x2802, 0x1},
> +{0x1969, 0x2062, 0xC1, 0x1565, 0x2801, 0x1},
> +{0x1969, 0x1073, 0xC0, 0x1019, 0x8151, 0x1},
> +{0x1969, 0x1073, 0xC0, 0x1019, 0x1073, 0x1},
> +{0x1969, 0x1073, 0xC0, 0x1458, 0xE000, 0x1},
> +{0x1969, 0x1083, 0xC0, 0x1458, 0xE000, 0x1},
> +{0x1969, 0x1083, 0xC0, 0x1019, 0x8151, 0x1},
> +{0x1969, 0x1083, 0xC0, 0x1019, 0x1083, 0x1},
> +{0x1969, 0x1083, 0xC0, 0x1462, 0x7680, 0x1},
> +{0x1969, 0x1083, 0xC0, 0x1565, 0x2803, 0x1},
> +{0},

Since patch_flag is always set to 0x1, just remove it, if you find a matching 
entry, apply the patch. Vendor ID is always the same, remove it as well.

Looking at the supported PCI devices table, this patching table is applicable 
to all Atheros PCI device id and none of the Attansic PCI device id, this 
suggests that your table should be reversed, and you should only list the 
devices *not* needing the patch, this should make the lookup code smaller.

> +};
> +
> +static void __devinit atl1c_patch_assign(struct atl1c_hw *hw)
> +{
> +	int i = 0;
> +
> +	hw->msi_lnkpatch = false;
> +
> +	while (plats[i].pci_vid != 0) {
> +		if (plats[i].pci_vid == hw->vendor_id &&
> +		    plats[i].pci_did == hw->device_id &&
> +		    plats[i].pci_revid == hw->revision_id &&
> +		    plats[i].subsystem_vid == hw->subsystem_vendor_id &&
> +		    plats[i].subsystem_did == hw->subsystem_id) {
> +			if (plats[i].patch_flag & ATL1C_LINK_PATCH)
> +				hw->msi_lnkpatch = true;
> +		}
> +		i++;
> +	}
> +}
>  /*
>   * atl1c_sw_init - Initialize general software structures (struct
> atl1c_adapter) * @adapter: board private structure to initialize
> @@ -732,6 +785,8 @@ static int __devinit atl1c_sw_init(struct atl1c_adapter
> *adapter) dev_err(&pdev->dev, "set mac function pointers failed\n");
>  		return -1;
>  	}
> +	atl1c_patch_assign(hw);
> +
>  	hw->intr_mask = IMR_NORMAL_MASK;
>  	hw->phy_configured = false;
>  	hw->preamble_len = 7;

-- 
Florian

RE: [PATCH 02/10] atl1c: add PHY link event(up/down) patch

[Huang, Xiong]

> > +struct atl1c_platform_patch {
> > +	u16 pci_vid;
> > +	u16 pci_did;
> > +	u8  pci_revid;
> > +	u16 subsystem_vid;
> > +	u16 subsystem_did;
> > +	u32 patch_flag;
> > +#define ATL1C_LINK_PATCH	0x1
> > +};
> > +static struct atl1c_platform_patch plats[] = {
> 
> This should be static const.

Thanks. It is.

> 
> > +{0x1969, 0x2060, 0xC1, 0x1019, 0x8152, 0x1}, {0x1969, 0x2060, 0xC1,
> > +0x1019, 0x2060, 0x1}, {0x1969, 0x2060, 0xC1, 0x1019, 0xE000, 0x1},
> > +{0x1969, 0x2062, 0xC0, 0x1019, 0x8152, 0x1}, {0x1969, 0x2062, 0xC0,
> > +0x1019, 0x2062, 0x1}, {0x1969, 0x2062, 0xC0, 0x1458, 0xE000, 0x1},
> > +{0x1969, 0x2062, 0xC1, 0x1019, 0x8152, 0x1}, {0x1969, 0x2062, 0xC1,
> > +0x1019, 0x2062, 0x1}, {0x1969, 0x2062, 0xC1, 0x1458, 0xE000, 0x1},
> > +{0x1969, 0x2062, 0xC1, 0x1565, 0x2802, 0x1}, {0x1969, 0x2062, 0xC1,
> > +0x1565, 0x2801, 0x1}, {0x1969, 0x1073, 0xC0, 0x1019, 0x8151, 0x1},
> > +{0x1969, 0x1073, 0xC0, 0x1019, 0x1073, 0x1}, {0x1969, 0x1073, 0xC0,
> > +0x1458, 0xE000, 0x1}, {0x1969, 0x1083, 0xC0, 0x1458, 0xE000, 0x1},
> > +{0x1969, 0x1083, 0xC0, 0x1019, 0x8151, 0x1}, {0x1969, 0x1083, 0xC0,
> > +0x1019, 0x1083, 0x1}, {0x1969, 0x1083, 0xC0, 0x1462, 0x7680, 0x1},
> > +{0x1969, 0x1083, 0xC0, 0x1565, 0x2803, 0x1}, {0},
> 
> Since patch_flag is always set to 0x1, just remove it, if you find a matching entry,
> apply the patch. Vendor ID is always the same, remove it as well.
> 
Thanks, Florain.
It's reasonable to remove Vendor ID since this driver only support one dedicated VID.
But for patch_flag, I'm afraid it could be used for other bug/issue, though we found 
One link issue (=flag bit 0) till now. Otherwise, I will not use ATL1C_LINK_PATCH in function
atl1c_patch_assign.

> Looking at the supported PCI devices table, this patching table is applicable to all
> Atheros PCI device id and none of the Attansic PCI device id, this suggests that

Atl1c driver only supports Atheros PCI device id, Attansic device id is supported by 
Atl1e & atlx.

> your table should be reversed, and you should only list the devices *not*
> needing the patch, this should make the lookup code smaller.
> 

It's almost impossible, there is over 200+ modules sold out, the issue is related to PCB layout,
The total percentage of issue modules is much lower than the normal.



B.R.
Xiong

答复: [PATCH 02/10] atl1c: add PHY link event(up/down) patch

[Huang, Xiong]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="big5", Size: 833 bytes --]


> +
> +struct atl1c_platform_patch {
> +     u16 pci_vid;
> +     u16 pci_did;
> +     u8  pci_revid;
> +     u16 subsystem_vid;
> +     u16 subsystem_did;
> +     u32 patch_flag;
> +#define ATL1C_LINK_PATCH     0x1
> +};
> +static struct atl1c_platform_patch plats[] = {

This should be static const.

> +{0x1969, 0x2060, 0xC1, 0x1019, 0x8152, 0x1},

-------------------------------------------------------------------------------------------------------
How about if I revise it as:

static const struct atl1c_platform_patch plats[] __devinitdata = {
....}

the array is only used by atl1c_probe function. is it appropriate to add '__devinitdata' here ?



Thanks
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答复: [PATCH 02/10] atl1c: add PHY link event(up/down) patch

[Huang, Xiong]

> +
> +struct atl1c_platform_patch {
> +     u16 pci_vid;
> +     u16 pci_did;
> +     u8  pci_revid;
> +     u16 subsystem_vid;
> +     u16 subsystem_did;
> +     u32 patch_flag;
> +#define ATL1C_LINK_PATCH     0x1
> +};
> +static struct atl1c_platform_patch plats[] = {

This should be static const.

> +{0x1969, 0x2060, 0xC1, 0x1019, 0x8152, 0x1},

-------------------------------------------------------------------------------------------------------
How about if I revise it as:

static const struct atl1c_platform_patch plats[] __devinitdata = {
....}

the array is only used by atl1c_probe function. is it appropriate to add '__devinitdata' here ?



Thanks
-Xiong

Re: [PATCH 00/10] atl1c: update hardware settings - v4

[David Miller]

Please address the feedback you've received and then repost this
entire series.

BTW, this is why you should submit as few patches at a time as
possible.  Because the more patches you submit at once, the more of
them you have to submit all over again when changes are requested for
even just one of them.

RE: [PATCH 00/10] atl1c: update hardware settings - v4

[Huang, Xiong]

thanks

-Xiong

> -----Original Message-----
> From: David Miller [mailto:davem@davemloft.net]
> Sent: Tuesday, May 01, 2012 1:36
> To: Huang, Xiong
> Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; qca-linux-team; nic-
> devel
> Subject: Re: [PATCH 00/10] atl1c: update hardware settings - v4
> 
> 
> Please address the feedback you've received and then repost this entire series.
> 
> BTW, this is why you should submit as few patches at a time as possible.
> Because the more patches you submit at once, the more of them you have to
> submit all over again when changes are requested for even just one of them.

Re: [PATCH 00/10] atl1c: update hardware settings - v4

[David Miller]

From: xiong <xiong@qca.qualcomm.com>
Date: Tue, 1 May 2012 09:38:48 +0800

> This update contains a serial of patches, most of them are hardware
> settings related. register definitions are refined (or removed if
> meaningless) for each patch.
> 
> This is the last patch set.
> 
> The patches have addressed all sparse and checkpatch warnings.
> 
> Following NICs are tested:
> AR8131/AR8132/AR8151A/AR8152A/AR8152B
> Test item includes:
> build/install/uninstall/dhcp/ping/iperf/wol/reboot/etc.

All applied, thanks.

[PATCH 00/10] atl1c: update hardware settings - v4

[xiong]

This update contains a serial of patches, most of them are hardware
settings related. register definitions are refined (or removed if
meaningless) for each patch.

This is the last patch set.

The patches have addressed all sparse and checkpatch warnings.

Following NICs are tested:
AR8131/AR8132/AR8151A/AR8152A/AR8152B
Test item includes:
build/install/uninstall/dhcp/ping/iperf/wol/reboot/etc.

xiong (10):
  atl1c: add workaround for issue of bit INTX-disable for MSI interrupt
  atl1c: add PHY link event(up/down) patch
  atl1c: clear WoL status when reset pcie
  atl1c: remove code of closing register writable attribution
  atl1c: refine mac address related code
  atl1c: enlarge L1 response waiting timer
  atl1c: cancel task when interface closed
  atl1c: do MAC-reset when PHY link down
  atl1c: Disable L0S when no cable link
  atl1c: remove PHY polling from atl1c_change_mtu

 drivers/net/ethernet/atheros/atl1c/atl1c.h      |    1 +
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c   |  141 ++++++++++++----------
 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h   |   35 ++---
 drivers/net/ethernet/atheros/atl1c/atl1c_main.c |  151 +++++++++++++++++------
 drivers/pci/quirks.c                            |   12 ++
 5 files changed, 218 insertions(+), 122 deletions(-)

-- 
1.7.7