* [PATCH v3] drm/i915: clarify semaphore-ring interaction
@ 2012-05-20 13:52 Ben Widawsky
2012-05-20 15:45 ` [PATCH v4] " Ben Widawsky
0 siblings, 1 reply; 5+ messages in thread
From: Ben Widawsky @ 2012-05-20 13:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky
After Daniel split out this code, I think this makes more sense, and
looks nicer. Also added some comments to help the situation.
v2: Make signal_mbox be all rings for symmetric-ness.
v3: submitted the wrong version of the patch before.
v2 had an issue with odd number of rings. The fix is to always emit an
even number of instructions to the ring with mbox updates.
Reviewed-by (v1): Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_reg.h | 13 ++++----
drivers/gpu/drm/i915/intel_ringbuffer.c | 54 +++++++++++++++++--------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +--
3 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb76b19..d3040d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -241,12 +241,12 @@
#define MI_SEMAPHORE_UPDATE (1<<21)
#define MI_SEMAPHORE_COMPARE (1<<20)
#define MI_SEMAPHORE_REGISTER (1<<18)
-#define MI_SEMAPHORE_SYNC_RV (2<<16)
-#define MI_SEMAPHORE_SYNC_RB (0<<16)
-#define MI_SEMAPHORE_SYNC_VR (0<<16)
-#define MI_SEMAPHORE_SYNC_VB (2<<16)
-#define MI_SEMAPHORE_SYNC_BR (2<<16)
-#define MI_SEMAPHORE_SYNC_BV (0<<16)
+#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
+#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
+#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
+#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
+#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
+#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
#define MI_SEMAPHORE_SYNC_INVALID (1<<0)
/*
* 3D instructions used by the kernel
@@ -423,6 +423,7 @@
#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
+#define GEN6_NOSYNC 0
#define RING_MAX_IDLE(base) ((base)+0x54)
#define RING_HWS_PGA(base) ((base)+0x80)
#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b59b6d5..4c1c60a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -449,6 +449,7 @@ update_mboxes(struct intel_ring_buffer *ring,
MI_SEMAPHORE_UPDATE);
intel_ring_emit(ring, seqno);
intel_ring_emit(ring, mmio_offset);
+ intel_ring_emit(ring, MI_NOOP);
}
/**
@@ -464,21 +465,23 @@ static int
gen6_add_request(struct intel_ring_buffer *ring,
u32 *seqno)
{
- u32 mbox1_reg;
- u32 mbox2_reg;
- int ret;
+ struct drm_device *dev = ring->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *useless;
+ int i, ret;
- ret = intel_ring_begin(ring, 10);
+ ret = intel_ring_begin(ring, round_up(I915_NUM_RINGS * 3, 2) + 4);
if (ret)
return ret;
- mbox1_reg = ring->signal_mbox[0];
- mbox2_reg = ring->signal_mbox[1];
-
*seqno = i915_gem_next_request_seqno(ring);
- update_mboxes(ring, *seqno, mbox1_reg);
- update_mboxes(ring, *seqno, mbox2_reg);
+ for_each_ring(useless, dev_priv, i) {
+ u32 mbox_reg = ring->signal_mbox[i];
+ if (mbox_reg != GEN6_NOSYNC)
+ update_mboxes(ring, *seqno, mbox_reg);
+ }
+
intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, *seqno);
@@ -1330,11 +1333,12 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->irq_enable_mask = GT_USER_INTERRUPT;
ring->get_seqno = gen6_ring_get_seqno;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
- ring->signal_mbox[0] = GEN6_VRSYNC;
- ring->signal_mbox[1] = GEN6_BRSYNC;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
+ ring->signal_mbox[RCS] = GEN6_NOSYNC;
+ ring->signal_mbox[VCS] = GEN6_VRSYNC;
+ ring->signal_mbox[BCS] = GEN6_BRSYNC;
} else if (IS_GEN5(dev)) {
ring->add_request = pc_render_add_request;
ring->flush = gen4_render_ring_flush;
@@ -1465,11 +1469,12 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
- ring->signal_mbox[0] = GEN6_RVSYNC;
- ring->signal_mbox[1] = GEN6_BVSYNC;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
+ ring->signal_mbox[RCS] = GEN6_RVSYNC;
+ ring->signal_mbox[VCS] = GEN6_NOSYNC;
+ ring->signal_mbox[BCS] = GEN6_BVSYNC;
} else {
ring->mmio_base = BSD_RING_BASE;
ring->flush = bsd_ring_flush;
@@ -1510,11 +1515,12 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
- ring->signal_mbox[0] = GEN6_RBSYNC;
- ring->signal_mbox[1] = GEN6_VBSYNC;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->signal_mbox[RCS] = GEN6_RBSYNC;
+ ring->signal_mbox[VCS] = GEN6_VBSYNC;
+ ring->signal_mbox[BCS] = GEN6_NOSYNC;
ring->init = init_ring_common;
return intel_init_ring_buffer(dev, ring);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 55d3da2..3db4447 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -80,8 +80,8 @@ struct intel_ring_buffer {
struct intel_ring_buffer *to,
u32 seqno);
- u32 semaphore_register[3]; /*our mbox written by others */
- u32 signal_mbox[2]; /* mboxes this ring signals to */
+ u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
+ u32 signal_mbox[I915_NUM_RINGS]; /* mboxes this ring signals to */
/**
* List of objects currently involved in rendering from the
* ringbuffer.
--
1.7.10.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4] drm/i915: clarify semaphore-ring interaction
2012-05-20 13:52 [PATCH v3] drm/i915: clarify semaphore-ring interaction Ben Widawsky
@ 2012-05-20 15:45 ` Ben Widawsky
2012-05-21 8:44 ` Chris Wilson
0 siblings, 1 reply; 5+ messages in thread
From: Ben Widawsky @ 2012-05-20 15:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky
After Daniel split out this code, I think this makes more sense, and
looks nicer. Also added some comments to help the situation.
v2: Make signal_mbox be all rings for symmetric-ness.
v3: submitted the wrong version of the patch before.
v2 had an issue with odd number of rings. The fix is to always emit an
even number of instructions to the ring with mbox updates.
v4: I suck. The code should send out mbox updates for NUM_RINGS-1 *
number of commands. Instead of NUM_RINGS * number of commands-1.
-ret = intel_ring_begin(ring, round_up((I915_NUM_RINGS) * 3, 2) + 4);
+ret = intel_ring_begin(ring, round_up((I915_NUM_RINGS-1) * 4, 2) + 4);
Reviewed-by (v1): Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_reg.h | 13 ++++----
drivers/gpu/drm/i915/intel_ringbuffer.c | 54 +++++++++++++++++--------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +--
3 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb76b19..d3040d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -241,12 +241,12 @@
#define MI_SEMAPHORE_UPDATE (1<<21)
#define MI_SEMAPHORE_COMPARE (1<<20)
#define MI_SEMAPHORE_REGISTER (1<<18)
-#define MI_SEMAPHORE_SYNC_RV (2<<16)
-#define MI_SEMAPHORE_SYNC_RB (0<<16)
-#define MI_SEMAPHORE_SYNC_VR (0<<16)
-#define MI_SEMAPHORE_SYNC_VB (2<<16)
-#define MI_SEMAPHORE_SYNC_BR (2<<16)
-#define MI_SEMAPHORE_SYNC_BV (0<<16)
+#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
+#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
+#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
+#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
+#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
+#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
#define MI_SEMAPHORE_SYNC_INVALID (1<<0)
/*
* 3D instructions used by the kernel
@@ -423,6 +423,7 @@
#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
+#define GEN6_NOSYNC 0
#define RING_MAX_IDLE(base) ((base)+0x54)
#define RING_HWS_PGA(base) ((base)+0x80)
#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b59b6d5..1d641e3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -449,6 +449,7 @@ update_mboxes(struct intel_ring_buffer *ring,
MI_SEMAPHORE_UPDATE);
intel_ring_emit(ring, seqno);
intel_ring_emit(ring, mmio_offset);
+ intel_ring_emit(ring, MI_NOOP);
}
/**
@@ -464,21 +465,23 @@ static int
gen6_add_request(struct intel_ring_buffer *ring,
u32 *seqno)
{
- u32 mbox1_reg;
- u32 mbox2_reg;
- int ret;
+ struct drm_device *dev = ring->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *useless;
+ int i, ret;
- ret = intel_ring_begin(ring, 10);
+ ret = intel_ring_begin(ring, round_up((I915_NUM_RINGS-1) * 4, 2) + 4);
if (ret)
return ret;
- mbox1_reg = ring->signal_mbox[0];
- mbox2_reg = ring->signal_mbox[1];
-
*seqno = i915_gem_next_request_seqno(ring);
- update_mboxes(ring, *seqno, mbox1_reg);
- update_mboxes(ring, *seqno, mbox2_reg);
+ for_each_ring(useless, dev_priv, i) {
+ u32 mbox_reg = ring->signal_mbox[i];
+ if (mbox_reg != GEN6_NOSYNC)
+ update_mboxes(ring, *seqno, mbox_reg);
+ }
+
intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, *seqno);
@@ -1330,11 +1333,12 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->irq_enable_mask = GT_USER_INTERRUPT;
ring->get_seqno = gen6_ring_get_seqno;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
- ring->signal_mbox[0] = GEN6_VRSYNC;
- ring->signal_mbox[1] = GEN6_BRSYNC;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
+ ring->signal_mbox[RCS] = GEN6_NOSYNC;
+ ring->signal_mbox[VCS] = GEN6_VRSYNC;
+ ring->signal_mbox[BCS] = GEN6_BRSYNC;
} else if (IS_GEN5(dev)) {
ring->add_request = pc_render_add_request;
ring->flush = gen4_render_ring_flush;
@@ -1465,11 +1469,12 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
- ring->signal_mbox[0] = GEN6_RVSYNC;
- ring->signal_mbox[1] = GEN6_BVSYNC;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
+ ring->signal_mbox[RCS] = GEN6_RVSYNC;
+ ring->signal_mbox[VCS] = GEN6_NOSYNC;
+ ring->signal_mbox[BCS] = GEN6_BVSYNC;
} else {
ring->mmio_base = BSD_RING_BASE;
ring->flush = bsd_ring_flush;
@@ -1510,11 +1515,12 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
- ring->signal_mbox[0] = GEN6_RBSYNC;
- ring->signal_mbox[1] = GEN6_VBSYNC;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->signal_mbox[RCS] = GEN6_RBSYNC;
+ ring->signal_mbox[VCS] = GEN6_VBSYNC;
+ ring->signal_mbox[BCS] = GEN6_NOSYNC;
ring->init = init_ring_common;
return intel_init_ring_buffer(dev, ring);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 55d3da2..3db4447 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -80,8 +80,8 @@ struct intel_ring_buffer {
struct intel_ring_buffer *to,
u32 seqno);
- u32 semaphore_register[3]; /*our mbox written by others */
- u32 signal_mbox[2]; /* mboxes this ring signals to */
+ u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
+ u32 signal_mbox[I915_NUM_RINGS]; /* mboxes this ring signals to */
/**
* List of objects currently involved in rendering from the
* ringbuffer.
--
1.7.10.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v4] drm/i915: clarify semaphore-ring interaction
2012-05-20 15:45 ` [PATCH v4] " Ben Widawsky
@ 2012-05-21 8:44 ` Chris Wilson
2012-05-21 21:03 ` Ben Widawsky
0 siblings, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2012-05-21 8:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky
On Sun, 20 May 2012 08:45:38 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> After Daniel split out this code, I think this makes more sense, and
> looks nicer. Also added some comments to help the situation.
>
> v2: Make signal_mbox be all rings for symmetric-ness.
> v3: submitted the wrong version of the patch before.
> v2 had an issue with odd number of rings. The fix is to always emit an
> even number of instructions to the ring with mbox updates.
> v4: I suck. The code should send out mbox updates for NUM_RINGS-1 *
> number of commands. Instead of NUM_RINGS * number of commands-1.
> -ret = intel_ring_begin(ring, round_up((I915_NUM_RINGS) * 3, 2) + 4);
> +ret = intel_ring_begin(ring, round_up((I915_NUM_RINGS-1) * 4, 2) + 4);
I'm honestly less enthralled about v4. I'd rather see that as a separate
preparatory patch so that it is put into context.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4] drm/i915: clarify semaphore-ring interaction
2012-05-21 8:44 ` Chris Wilson
@ 2012-05-21 21:03 ` Ben Widawsky
2012-05-21 21:40 ` Chris Wilson
0 siblings, 1 reply; 5+ messages in thread
From: Ben Widawsky @ 2012-05-21 21:03 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Mon, 21 May 2012 09:44:02 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Sun, 20 May 2012 08:45:38 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> > After Daniel split out this code, I think this makes more sense, and
> > looks nicer. Also added some comments to help the situation.
> >
> > v2: Make signal_mbox be all rings for symmetric-ness.
> > v3: submitted the wrong version of the patch before.
> > v2 had an issue with odd number of rings. The fix is to always emit an
> > even number of instructions to the ring with mbox updates.
> > v4: I suck. The code should send out mbox updates for NUM_RINGS-1 *
> > number of commands. Instead of NUM_RINGS * number of commands-1.
> > -ret = intel_ring_begin(ring, round_up((I915_NUM_RINGS) * 3, 2) + 4);
> > +ret = intel_ring_begin(ring, round_up((I915_NUM_RINGS-1) * 4, 2) + 4);
>
> I'm honestly less enthralled about v4. I'd rather see that as a separate
> preparatory patch so that it is put into context.
> -Chris
>
I can do that. Are you okay with the idea otherwise? This is really all
prep work for some HSW patches anyway.
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4] drm/i915: clarify semaphore-ring interaction
2012-05-21 21:03 ` Ben Widawsky
@ 2012-05-21 21:40 ` Chris Wilson
0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2012-05-21 21:40 UTC (permalink / raw)
To: Ben Widawsky; +Cc: intel-gfx
On Mon, 21 May 2012 14:03:05 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> I can do that. Are you okay with the idea otherwise? This is really all
> prep work for some HSW patches anyway.
Yes, I can see where you are going, I just need that little bit of
convincing that it will all work out in the end ;-)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2012-05-21 21:40 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-05-20 13:52 [PATCH v3] drm/i915: clarify semaphore-ring interaction Ben Widawsky
2012-05-20 15:45 ` [PATCH v4] " Ben Widawsky
2012-05-21 8:44 ` Chris Wilson
2012-05-21 21:03 ` Ben Widawsky
2012-05-21 21:40 ` Chris Wilson
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