* [PATCH 0/2] Valleyview PLL fix and cleanup
@ 2012-06-15 14:38 Vijay Purushothaman
2012-06-15 14:38 ` [PATCH 1/2] drm/i915 : fix incorrect p2 values for Valleyview Vijay Purushothaman
2012-06-15 14:38 ` [PATCH 2/2] drm/i915: cleanup Valleyview PLL calculation Vijay Purushothaman
0 siblings, 2 replies; 3+ messages in thread
From: Vijay Purushothaman @ 2012-06-15 14:38 UTC (permalink / raw)
To: Intel Graphics; +Cc: jesse.barnes
Fixed the wrong p2 PLL values and replaced all hardcoded numbers in best PLL
calculation. These two patches should be applied on top of Jesse's Jun 14
Valleyview patch set.
Tried to refactor the code to avoid so many nested loops but ended up messing
other VLV code. Any help with code refactoring, most welcome!
Thanks,
Vijay
Vijay Purushothaman (2):
drm/i915 : fix incorrect p2 values for Valleyview
drm/i915: cleanup Valleyview PLL calculation
drivers/gpu/drm/i915/intel_display.c | 58 ++++++++++++++--------------------
1 files changed, 24 insertions(+), 34 deletions(-)
--
1.7.5.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/2] drm/i915 : fix incorrect p2 values for Valleyview
2012-06-15 14:38 [PATCH 0/2] Valleyview PLL fix and cleanup Vijay Purushothaman
@ 2012-06-15 14:38 ` Vijay Purushothaman
2012-06-15 14:38 ` [PATCH 2/2] drm/i915: cleanup Valleyview PLL calculation Vijay Purushothaman
1 sibling, 0 replies; 3+ messages in thread
From: Vijay Purushothaman @ 2012-06-15 14:38 UTC (permalink / raw)
To: Intel Graphics; +Cc: jesse.barnes
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 157dcb0a..0707b7a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -374,7 +374,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
.p = { .min = 10, .max = 30 },
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 270000,
- .p2_slow = 10, .p2_fast = 5 },
+ .p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
};
@@ -388,7 +388,7 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
.p = { .min = 10, .max = 30 },
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 270000,
- .p2_slow = 10, .p2_fast = 5 },
+ .p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
};
@@ -402,7 +402,7 @@ static const intel_limit_t intel_limits_vlv_dp = {
.p = { .min = 10, .max = 30 },
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 270000,
- .p2_slow = 10, .p2_fast = 5 },
+ .p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
};
--
1.7.5.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] drm/i915: cleanup Valleyview PLL calculation
2012-06-15 14:38 [PATCH 0/2] Valleyview PLL fix and cleanup Vijay Purushothaman
2012-06-15 14:38 ` [PATCH 1/2] drm/i915 : fix incorrect p2 values for Valleyview Vijay Purushothaman
@ 2012-06-15 14:38 ` Vijay Purushothaman
1 sibling, 0 replies; 3+ messages in thread
From: Vijay Purushothaman @ 2012-06-15 14:38 UTC (permalink / raw)
To: Intel Graphics; +Cc: jesse.barnes
replaced hardcoded numbers with valid PLL limit values
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 52 +++++++++++++--------------------
1 files changed, 21 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0707b7a..e2d23a3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -865,69 +865,59 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
intel_clock_t *best_clock)
{
u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
- u32 m, n, fastclk, minvco, maxvco;
+ u32 m, n, fastclk;
u32 updrate, minupdate, fracbits, p;
unsigned long bestppm, ppm, absppm;
- int dotclk;
+ int dotclk, flag;
dotclk = target * 1000;
-
bestppm = 1000000;
- ppm = 0;
- absppm = 0;
-
+ ppm = absppm = 0;
fastclk = dotclk / (2*100);
- minvco = limit->vco.min;
- maxvco = limit->vco.max;
updrate = 0;
minupdate = 19200;
fracbits = 1;
-
n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
bestm1 = bestm2 = bestp1 = bestp2 = 0;
- for(n = 1; n <= ((refclk) / minupdate); n++) {
+ /* based on hardware requirement, prefer smaller n to precision */
+ for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
updrate = refclk / n;
- for (p1 = 3; p1 > 1; p1--) {
- for (p2 = 21; p2 > 0; p2--) {
+ for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
+ for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
if (p2 > 10)
p2 = p2 - 1;
p = p1 * p2;
-
- for( m1=2; m1 <= 3; m1++) {
+ /* based on hardware requirement, prefer bigger m1,m2 values */
+ for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
m2 = (((2*(fastclk * p * n / m1 )) +
refclk) / (2*refclk));
m = m1 * m2;
vco = updrate * m;
- if(vco >= minvco && vco < maxvco) {
- ppm = 1000000 *((vco / p) -
- fastclk) /
- fastclk;
- absppm = (ppm > 0)? ppm: (-ppm);
- if (absppm < 100 &&
- ((p1 * p2) >
- (bestp1 * bestp2))) {
+ if (vco >= limit->vco.min && vco < limit->vco.max) {
+ ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
+ absppm = (ppm > 0) ? ppm : (-ppm);
+ if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
bestppm = 0;
- bestn = n;
- bestm1 = m1;
- bestm2 = m2;
- bestp1 = p1;
- bestp2 = p2;
+ flag = 1;
}
if (absppm < bestppm - 10) {
bestppm = absppm;
+ flag = 1;
+ }
+ if (flag) {
bestn = n;
bestm1 = m1;
bestm2 = m2;
bestp1 = p1;
bestp2 = p2;
+ flag = 0;
}
}
}
- } /* Next p2 */
- } /* Next p1 */
- }/* Next n */
-
+ }
+ }
+ }
best_clock->n = bestn;
best_clock->m1 = bestm1;
best_clock->m2 = bestm2;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2012-06-15 14:37 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2012-06-15 14:38 [PATCH 0/2] Valleyview PLL fix and cleanup Vijay Purushothaman
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2012-06-15 14:38 ` [PATCH 2/2] drm/i915: cleanup Valleyview PLL calculation Vijay Purushothaman
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