[PATCH v7] arm: Add basic support for new Marvell Armada 370 and Armada XP SoC

[PATCH v7] arm: Add basic support for new Marvell Armada 370 and Armada XP SoC

[Thomas Petazzoni]

Arnd, Olof,

You'll find in this patch set the seventh version of the initial
support for a new family of ARMv7-compatible Marvell SoCs.

As for the previous releases, both the Armada 370 and the Armada XP
SoCs are supported in this directory, and we are able to build a
single kernel image that boots on both SoCs. Both SoCs use the PJ4B
processor, a Marvell-developed ARM core that implements the ARMv7
instruction set. We are currently using Marvell evaluation boards for
both of those SoCs, and the support for those boards is added in this
patch set.

We remained focused on a limited preliminary support which only
includes the necessary code for timer and IRQ support, the serial
controller is a standard 16550-compatible one. The diffstat looks
like:

 Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt      |   23 +
 Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt     |   11
 Documentation/devicetree/bindings/arm/armada-370-xp.txt           |   24 +
 Documentation/devicetree/bindings/arm/mvebu-system-controller.txt |   17
 MAINTAINERS                                                       |    8
 arch/arm/Kconfig                                                  |   14
 arch/arm/Makefile                                                 |    1
 arch/arm/boot/dts/armada-370-db.dts                               |   42 +
 arch/arm/boot/dts/armada-370-xp.dtsi                              |   68 +++
 arch/arm/boot/dts/armada-370.dtsi                                 |   35 +
 arch/arm/boot/dts/armada-xp-db.dts                                |   50 ++
 arch/arm/boot/dts/armada-xp.dtsi                                  |   55 ++
 arch/arm/configs/mvebu_defconfig                                  |   46 ++
 arch/arm/mach-mvebu/Kconfig                                       |   16
 arch/arm/mach-mvebu/Makefile                                      |    2
 arch/arm/mach-mvebu/Makefile.boot                                 |    1
 arch/arm/mach-mvebu/armada-370-xp.c                               |   63 ++
 arch/arm/mach-mvebu/common.h                                      |   23 +
 arch/arm/mach-mvebu/include/mach/armada-370-xp.h                  |   22
 arch/arm/mach-mvebu/include/mach/debug-macro.S                    |   24 +
 arch/arm/mach-mvebu/include/mach/timex.h                          |   13
 arch/arm/mach-mvebu/include/mach/uncompress.h                     |   43 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c                           |  133 +++++
 arch/arm/mach-mvebu/system-controller.c                           |  105 ++++
 drivers/clocksource/Kconfig                                       |    3
 drivers/clocksource/Makefile                                      |    3
 drivers/clocksource/time-armada-370-xp.c                          |  226 ++++++++++
 include/linux/time-armada-370-xp.h                                |   18
 28 files changed, 1088 insertions(+), 1 deletion(-)

This patch set, and the support for those SoCs, started as a
collaborative effort from Marvell engineers (who have done the initial
development work) and Free Electrons engineers (who are reshaping the
code for mainline submission, adding device tree support, etc.). This
effort has also received contributions from Ben Dooks from Codethink.

The patch set is based on your arm-soc/for-next branch (updated on
Sunday 1st July).

Changes between v6 and v7:

 * Take into account comments from Thomas Gleixner on the clocksource
   driver: don't check delta == 0, don't disable interrupts in
   ->set_next_event() and ->set_mode() as it is already done by the
   clock infrastructure, and use the clockevents_config_and_register()
   helper function to register the clockevents device with less code.

Changes between v5 and v6:

 * Clarify the error message shown when restarting but no system
   controller was configured, and use pr_err() instead of pr_warn.

 * Remove the 'asmlinkage' qualifier from common.h, since it is
   useless in a header file (thanks to Ben Dooks for noticing)

 * Integrate two patches from Ben Dooks (fixup style/indentation, and
   check result of of_match_node() in the system-controller.c
   driver). Since those patches were fixing relatively minor issues, I
   simply folded them into the original corresponding patches, in
   order to keep a nice a clean patch set.

 * Rebased on top of the latest arm-soc/for-next branch.

Changes between v4 and v5:

 * For system controller mvebu_other is renamed to orion for a better
   description of the subset including Dove, mv78xx0, Kirkwood and
   Orion5x.

 * The system controller code is improved following Arnd advices. Now
   it uses pointers to data structures instead of defines and if/else
   statements.

 * The restart function never returns anymore, even if no system
   controller was configured.

 * The listing of the MVEBU family device tree in the binding
   documentation for system controller is fixed.

Changes between v3 and v4:

 * If the system controller device is not found during initialization,
   no more warnings are issued and the function doesn't fail.

 * The system controller driver becomes more generic to handle the
   other mvebu SoCs. Inside the device tree it is now called either
   armada-370-xp-system-controller or mvebu-other-system-controller.
   Then depending of the compatibility name the driver selects the
   accurate offset and bit mask. The way to handle different variants
   of the same controller was inspired by the of_serial.c file.

 * A documentation was added for the "system-controller" binding

 * The "select CPU_V7" was moved from ARCH_MVEBU in arch/arm/Kconfig
   to MACH_ARMADA_370_XP in arch/arm/mach-mvebu/Kconfig. Thanks to this
   the other mvebu" machines will be able to use CPU_V5

 * Some armada_370_xp strings have been renamed to armada-370-xp to
   keep the coherency with other parts of the code.

Changes between v2 and v3:

 * The timer support code has been moved to drivers/clocksource/ and
   the necessary related changes have been made

 * There is now a minimal "system-controller" driver that gets
   instantiated through DT entries. This driver allows to expose the
   features made available through a set of miscellaneous registers
   that do not belong to any specific device in the SoC. For the
   moment, we only use it to implement the .restart() hook.

 * The defconfig has been changed to allow the support for up to four
   8250-compatible serial ports, since Armada XP has four such
   ports. The DTS file has been modified to enable those four ports,
   and they have all been tested successfully on the Armada XP DB
   development platform.

 * Moved the "arm: mach-mvebu: add compilation/configuration change"
   patch towards the end of the patch set

 * Marked the "serial" device as "disabled" in the .dtsi file, and
   enable the ones that are actually used in the board specific .dts
   file.

 * Dropped the _dt suffix as the device tree support is implicit now.

 * Don't use anymore a MVEBU_REGS_PHYS_BASE define and reintroduce a
   ARMADA_370_XP_REGS_PHYS_BASE define.

Changes between v1 and v2:

 * Use the mach-mvebu directory as suggested on the mailing-list. So
   far, this directory only contains the support for Armada 370/XP,
   but the plan is that it should ultimately contain the support for
   all other SoCs produced by the Marvell Engineering Business Unit.

 * Converted most the "armada" word by the "mvebu", but as some code
   remains specific to the Armada 370 and Armada XP SOC, then created
   also the aramada_370_xp suffix for this part. This suffix was
   dedicated for the irq and timer part. It was also used for the
   register related to the reset part. And of course it was also used
   for the device tree part.

 * Merged axp-dt.c and a370-dt.c files in one single
   armada_370_xp-dt.c file.

 * Deleted most of the mapping address in include/mach/armada.h and
   split it in two headers file:

  - mvebu.h which contains the virtual and physical mapping for the
    internal registers of the mvebu SOC. This ones are mainly used for
    the early print during boot.

  - armada_370_xp which contains the registers offset and mask for
    resetting the CPU.

 * Removed unused headers such as
  - hardware.h by directly including accurate header when needed
  - gpio.h by removing the dependencies to PLAT-ORION
  - io.h no more needed for CPI
  - irqs.h by using SPARSE_IRQ
  - system.h no more needed for new SOC

 * Removed the PCI related code as it was not necessary for the
  initial submission

 * Removed all the PLAT-ORION dependencies remaining

 * Ensured property reading checks for error when getting data from
   device tree in the timer file. This was a patch from Ben Dooks with
   the following comments:

  "The call to of_property_read_u32() only checks for the value that
   the clk variable is set to being non-zero, and not the return value
   of the call itself.

   This caused a system without the clock-frequency attribute to fail
   to boot as it used a random value on the stack to setup the system
   timers and thus cause an interrupt storm.

   Also ensure clk is set to zero, to avoid warnings."

 * Converted irq controller code to use SPARSE_IRQ

 * Added the following bug fixes and improvements in irq.c from Ben
   Dooks

  - MPIC: BUG_ON() if the of_iomap() fails: Ensure that if either
    resource is missing, we stop the kernel in a reasonably fatal way.

  - MPIC: Move main register base to base of MPIC registers: The
    current kernel driver had the MPIC base at the base of the block
    containing the MPIC and not the MPIC itself. Change this value in
    the driver and the .dtsi file

    Also change the register size in the .dtsi to be the size of the
    register range for the MIPC and not the block it is in.

  - MPIC: Move per-cpu register base: The current kernel driver had
    the MPIC per-cpu register base at the base of the per-cpu register
    block and not at the base of the specific per-cpu interrupt
    registers.

    Move the driver and .dtsi to use the correct base and size.

  - MPIC: number fetch should use irqd_to_hwirq(): The mask and unmask
    routines are assuming that d->irq is a 1:1 mapping with the
    interrupt hardware. Use the irqd_to_hwirq() call to map the
    irq_data to the hardware irq number directly.

  - MPIC: read number of interrupts from control register: Read the
    number of MPIC interrupts from the controller and only register
    that many.

Best regards,

Thomas Petazzoni

[PATCH 1/9] clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver

[Thomas Petazzoni]

From: Gregory Clement <gregory.clement@free-electrons.com>

Timer 0 is used as free-running clocksource, while timer 1 is used as
clock_event_device.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: John Stultz <johnstul@us.ibm.com>
---
 drivers/clocksource/Kconfig              |    3 +
 drivers/clocksource/Makefile             |    3 +-
 drivers/clocksource/time-armada-370-xp.c |  226 ++++++++++++++++++++++++++++++
 include/linux/time-armada-370-xp.h       |   18 +++
 4 files changed, 249 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clocksource/time-armada-370-xp.c
 create mode 100644 include/linux/time-armada-370-xp.h

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 99c6b20..b323631 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -16,6 +16,9 @@ config CLKSRC_MMIO
 config DW_APB_TIMER
 	bool
 
+config ARMADA_370_XP_TIMER
+	bool
+
 config CLKSRC_DBX500_PRCMU
 	bool "Clocksource PRCMU Timer"
 	depends on UX500_SOC_DB8500
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index dd3e661..022015c 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -10,4 +10,5 @@ obj-$(CONFIG_EM_TIMER_STI)	+= em_sti.o
 obj-$(CONFIG_CLKBLD_I8253)	+= i8253.o
 obj-$(CONFIG_CLKSRC_MMIO)	+= mmio.o
 obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
-obj-$(CONFIG_CLKSRC_DBX500_PRCMU)	+= clksrc-dbx500-prcmu.o
\ No newline at end of file
+obj-$(CONFIG_CLKSRC_DBX500_PRCMU)	+= clksrc-dbx500-prcmu.o
+obj-$(CONFIG_ARMADA_370_XP_TIMER)	+= time-armada-370-xp.o
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
new file mode 100644
index 0000000..1292aa3
--- /dev/null
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -0,0 +1,226 @@
+/*
+ * Marvell Armada 370/XP SoC timer handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Timer 0 is used as free-running clocksource, while timer 1 is
+ * used as clock_event_device.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <asm/sched_clock.h>
+
+/*
+ * Timer block registers.
+ */
+#define TIMER_CTRL_OFF		0x0000
+#define  TIMER0_EN		 0x0001
+#define  TIMER0_RELOAD_EN	 0x0002
+#define  TIMER0_25MHZ            0x0800
+#define  TIMER0_DIV(div)         ((div) << 19)
+#define  TIMER1_EN		 0x0004
+#define  TIMER1_RELOAD_EN	 0x0008
+#define  TIMER1_25MHZ            0x1000
+#define  TIMER1_DIV(div)         ((div) << 22)
+#define TIMER_EVENTS_STATUS	0x0004
+#define  TIMER0_CLR_MASK         (~0x1)
+#define  TIMER1_CLR_MASK         (~0x100)
+#define TIMER0_RELOAD_OFF	0x0010
+#define TIMER0_VAL_OFF		0x0014
+#define TIMER1_RELOAD_OFF	0x0018
+#define TIMER1_VAL_OFF		0x001c
+
+/* Global timers are connected to the coherency fabric clock, and the
+   below divider reduces their incrementing frequency. */
+#define TIMER_DIVIDER_SHIFT     5
+#define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)
+
+/*
+ * SoC-specific data.
+ */
+static void __iomem *timer_base;
+static int timer_irq;
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
+
+static u32 notrace armada_370_xp_read_sched_clock(void)
+{
+	return ~readl(timer_base + TIMER0_VAL_OFF);
+}
+
+/*
+ * Clockevent handling.
+ */
+static int
+armada_370_xp_clkevt_next_event(unsigned long delta,
+				struct clock_event_device *dev)
+{
+	u32 u;
+
+	/*
+	 * Clear clockevent timer interrupt.
+	 */
+	writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
+
+	/*
+	 * Setup new clockevent timer value.
+	 */
+	writel(delta, timer_base + TIMER1_VAL_OFF);
+
+	/*
+	 * Enable the timer.
+	 */
+	u = readl(timer_base + TIMER_CTRL_OFF);
+	u = ((u & ~TIMER1_RELOAD_EN) | TIMER1_EN |
+	     TIMER1_DIV(TIMER_DIVIDER_SHIFT));
+	writel(u, timer_base + TIMER_CTRL_OFF);
+
+	return 0;
+}
+
+static void
+armada_370_xp_clkevt_mode(enum clock_event_mode mode,
+			  struct clock_event_device *dev)
+{
+	u32 u;
+
+	if (mode == CLOCK_EVT_MODE_PERIODIC) {
+		/*
+		 * Setup timer to fire at 1/HZ intervals.
+		 */
+		writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
+		writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
+
+		/*
+		 * Enable timer.
+		 */
+		u = readl(timer_base + TIMER_CTRL_OFF);
+
+		writel((u | TIMER1_EN | TIMER1_RELOAD_EN |
+			TIMER1_DIV(TIMER_DIVIDER_SHIFT)),
+		       timer_base + TIMER_CTRL_OFF);
+	} else {
+		/*
+		 * Disable timer.
+		 */
+		u = readl(timer_base + TIMER_CTRL_OFF);
+		writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
+
+		/*
+		 * ACK pending timer interrupt.
+		 */
+		writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
+
+	}
+}
+
+static struct clock_event_device armada_370_xp_clkevt = {
+	.name		= "armada_370_xp_tick",
+	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+	.shift		= 32,
+	.rating		= 300,
+	.set_next_event	= armada_370_xp_clkevt_next_event,
+	.set_mode	= armada_370_xp_clkevt_mode,
+};
+
+static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
+{
+	/*
+	 * ACK timer interrupt and call event handler.
+	 */
+
+	writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
+	armada_370_xp_clkevt.event_handler(&armada_370_xp_clkevt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction armada_370_xp_timer_irq = {
+	.name		= "armada_370_xp_tick",
+	.flags		= IRQF_DISABLED | IRQF_TIMER,
+	.handler	= armada_370_xp_timer_interrupt
+};
+
+void __init armada_370_xp_timer_init(void)
+{
+	u32 u;
+	struct device_node *np;
+	unsigned int timer_clk;
+	int ret;
+	np = of_find_compatible_node(NULL, NULL, "marvell,timer");
+	timer_base = of_iomap(np, 0);
+	WARN_ON(!timer_base);
+
+	if (of_find_property(np, "marvell,timer-25Mhz", NULL)) {
+		/* The fixed 25MHz timer is available so let's use it */
+		u = readl(timer_base + TIMER_CTRL_OFF);
+		writel(u | TIMER0_25MHZ | TIMER1_25MHZ,
+		       timer_base + TIMER_CTRL_OFF);
+		timer_clk = 25000000;
+	} else {
+		u32 clk = 0;
+		ret = of_property_read_u32(np, "clock-frequency", &clk);
+		WARN_ON(!clk || ret < 0);
+		u = readl(timer_base + TIMER_CTRL_OFF);
+		writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ),
+		       timer_base + TIMER_CTRL_OFF);
+		timer_clk = clk / TIMER_DIVIDER;
+	}
+
+	/* We use timer 0 as clocksource, and timer 1 for
+	   clockevents */
+	timer_irq = irq_of_parse_and_map(np, 1);
+
+	ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
+
+	/*
+	 * Set scale and timer for sched_clock.
+	 */
+	setup_sched_clock(armada_370_xp_read_sched_clock, 32, timer_clk);
+
+	/*
+	 * Setup free-running clocksource timer (interrupts
+	 * disabled).
+	 */
+	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
+	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
+
+	u = readl(timer_base + TIMER_CTRL_OFF);
+
+	writel((u | TIMER0_EN | TIMER0_RELOAD_EN |
+		TIMER0_DIV(TIMER_DIVIDER_SHIFT)), timer_base + TIMER_CTRL_OFF);
+
+	clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
+			      "armada_370_xp_clocksource",
+			      timer_clk, 300, 32, clocksource_mmio_readl_down);
+
+	/*
+	 * Setup clockevent timer (interrupt-driven).
+	 */
+	setup_irq(timer_irq, &armada_370_xp_timer_irq);
+	armada_370_xp_clkevt.cpumask = cpumask_of(0);
+	clockevents_config_and_register(&armada_370_xp_clkevt,
+					timer_clk, 1, 0xfffffffe);
+}
+
diff --git a/include/linux/time-armada-370-xp.h b/include/linux/time-armada-370-xp.h
new file mode 100644
index 0000000..dfdfdc0
--- /dev/null
+++ b/include/linux/time-armada-370-xp.h
@@ -0,0 +1,18 @@
+/*
+ * Marvell Armada 370/XP SoC timer handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ */
+#ifndef __TIME_ARMADA_370_XPPRCMU_H
+#define __TIME_ARMADA_370_XPPRCMU_H
+
+#include <linux/init.h>
+
+void __init armada_370_xp_timer_init(void);
+
+#endif
-- 
1.7.9.5

[PATCH 2/9] arm: mach-mvebu: add header

[Thomas Petazzoni]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
---
 arch/arm/mach-mvebu/include/mach/debug-macro.S |   24 +++++++++++++
 arch/arm/mach-mvebu/include/mach/timex.h       |   13 +++++++
 arch/arm/mach-mvebu/include/mach/uncompress.h  |   43 ++++++++++++++++++++++++
 3 files changed, 80 insertions(+)
 create mode 100644 arch/arm/mach-mvebu/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-mvebu/include/mach/timex.h
 create mode 100644 arch/arm/mach-mvebu/include/mach/uncompress.h

diff --git a/arch/arm/mach-mvebu/include/mach/debug-macro.S b/arch/arm/mach-mvebu/include/mach/debug-macro.S
new file mode 100644
index 0000000..2282576
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/debug-macro.S
@@ -0,0 +1,24 @@
+/*
+ * Early serial output macro for Marvell  SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory Clement <gregory.clement@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/armada-370-xp.h>
+
+	.macro	addruart, rp, rv, tmp
+	ldr	\rp, =ARMADA_370_XP_REGS_PHYS_BASE
+	ldr	\rv, =ARMADA_370_XP_REGS_VIRT_BASE
+	orr	\rp, \rp, #0x00012000
+	orr	\rv, \rv, #0x00012000
+	.endm
+
+#define UART_SHIFT	2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-mvebu/include/mach/timex.h b/arch/arm/mach-mvebu/include/mach/timex.h
new file mode 100644
index 0000000..ab324a3
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/timex.h
@@ -0,0 +1,13 @@
+/*
+ * Marvell Armada SoC time definitions
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE		(100 * HZ)
diff --git a/arch/arm/mach-mvebu/include/mach/uncompress.h b/arch/arm/mach-mvebu/include/mach/uncompress.h
new file mode 100644
index 0000000..d6a100c
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/uncompress.h
@@ -0,0 +1,43 @@
+/*
+ * Marvell Armada SoC kernel uncompression UART routines
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/armada-370-xp.h>
+
+#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
+								+ 0x12000))
+#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
+								+ 0x12014))
+
+#define LSR_THRE	0x20
+
+static void putc(const char c)
+{
+	int i;
+
+	for (i = 0; i < 0x1000; i++) {
+		/* Transmit fifo not full? */
+		if (*UART_LSR & LSR_THRE)
+			break;
+	}
+
+	*UART_THR = c;
+}
+
+static void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
-- 
1.7.9.5

[PATCH 3/9] arm: mach-mvebu: add source files

[Thomas Petazzoni]

From: Gregory CLEMENT <gregory.clement@free-electrons.com>

[ben.dooks at codethink.co.uk: fixup style error in system-controller]
[ben.dooks at codethink.co.uk: check result of of_match_node()]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
---
 arch/arm/mach-mvebu/Kconfig             |    7 +++
 arch/arm/mach-mvebu/Makefile            |    1 +
 arch/arm/mach-mvebu/Makefile.boot       |    1 +
 arch/arm/mach-mvebu/common.h            |   20 ++++++
 arch/arm/mach-mvebu/system-controller.c |  105 +++++++++++++++++++++++++++++++
 5 files changed, 134 insertions(+)
 create mode 100644 arch/arm/mach-mvebu/Kconfig
 create mode 100644 arch/arm/mach-mvebu/Makefile
 create mode 100644 arch/arm/mach-mvebu/Makefile.boot
 create mode 100644 arch/arm/mach-mvebu/common.h
 create mode 100644 arch/arm/mach-mvebu/system-controller.c

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
new file mode 100644
index 0000000..72d39e5
--- /dev/null
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -0,0 +1,7 @@
+if ARCH_MVEBU
+
+menu "Marvell SOC with device tree"
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
new file mode 100644
index 0000000..7366ae7
--- /dev/null
+++ b/arch/arm/mach-mvebu/Makefile
@@ -0,0 +1 @@
+obj-y += system-controller.o
diff --git a/arch/arm/mach-mvebu/Makefile.boot b/arch/arm/mach-mvebu/Makefile.boot
new file mode 100644
index 0000000..b327175
--- /dev/null
+++ b/arch/arm/mach-mvebu/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y := 0x00008000
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
new file mode 100644
index 0000000..f0eaa21
--- /dev/null
+++ b/arch/arm/mach-mvebu/common.h
@@ -0,0 +1,20 @@
+/*
+ * Core functions for Marvell System On Chip
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_MVEBU_COMMON_H
+#define __ARCH_MVEBU_COMMON_H
+
+void mvebu_restart(char mode, const char *cmd);
+
+#endif
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
new file mode 100644
index 0000000..b8079df
--- /dev/null
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -0,0 +1,105 @@
+/*
+ * System controller support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada 370 and Armada XP SoCs both have a range of
+ * miscellaneous registers, that do not belong to a particular device,
+ * but rather provide system-level features. This basic
+ * system-controller driver provides a device tree binding for those
+ * registers, and implements utility functions offering various
+ * features related to those registers.
+ *
+ * For now, the feature set is limited to restarting the platform by a
+ * soft-reset, but it might be extended in the future.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+static void __iomem *system_controller_base;
+
+struct mvebu_system_controller {
+	u32 rstoutn_mask_offset;
+	u32 system_soft_reset_offset;
+
+	u32 rstoutn_mask_reset_out_en;
+	u32 system_soft_reset;
+};
+static struct mvebu_system_controller *mvebu_sc;
+
+const struct mvebu_system_controller armada_370_xp_system_controller = {
+	.rstoutn_mask_offset = 0x60,
+	.system_soft_reset_offset = 0x64,
+	.rstoutn_mask_reset_out_en = 0x1,
+	.system_soft_reset = 0x1,
+};
+
+const struct mvebu_system_controller orion_system_controller = {
+	.rstoutn_mask_offset = 0x108,
+	.system_soft_reset_offset = 0x10c,
+	.rstoutn_mask_reset_out_en = 0x4,
+	.system_soft_reset = 0x1,
+};
+
+static struct of_device_id of_system_controller_table[] = {
+	{
+		.compatible = "marvell,orion-system-controller",
+		.data = (void *) &orion_system_controller,
+	}, {
+		.compatible = "marvell,armada-370-xp-system-controller",
+		.data = (void *) &armada_370_xp_system_controller,
+	},
+	{ /* end of list */ },
+};
+
+void mvebu_restart(char mode, const char *cmd)
+{
+	if (!system_controller_base) {
+		pr_err("Cannot restart, system-controller not available: check the device tree\n");
+	} else {
+		/*
+		 * Enable soft reset to assert RSTOUTn.
+		 */
+		writel(mvebu_sc->rstoutn_mask_reset_out_en,
+			system_controller_base +
+			mvebu_sc->rstoutn_mask_offset);
+		/*
+		 * Assert soft reset.
+		 */
+		writel(mvebu_sc->system_soft_reset,
+			system_controller_base +
+			mvebu_sc->system_soft_reset_offset);
+	}
+
+	while (1)
+		;
+}
+
+static int __init mvebu_system_controller_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, of_system_controller_table);
+	if (np) {
+		const struct of_device_id *match =
+		    of_match_node(of_system_controller_table, np);
+		BUG_ON(!match);
+		system_controller_base = of_iomap(np, 0);
+		mvebu_sc = (struct mvebu_system_controller *)match->data;
+	}
+
+	return 0;
+}
+
+arch_initcall(mvebu_system_controller_init);
-- 
1.7.9.5

[PATCH 4/9] arm: mach-mvebu: add support for Armada 370 and Armada XP with DT

[Thomas Petazzoni]

[ben.dooks at codethink.co.uk: ensure error check on of_property_read_u32]
[ben.dooks at codethink.co.uk: use mpic address instead of bus-unit's ]
[ben.dooks at codethink.co.uk: BUG_ON() if the of_iomap() fails for mpic]
[ben.dooks at codethink.co.uk: move mpic per-cpu register base ]
[ben.dooks at codethink.co.uk: number fetch should use irqd_to_hwirq()]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/armada-370-db.dts              |   42 +++++++
 arch/arm/boot/dts/armada-370-xp.dtsi             |   68 +++++++++++
 arch/arm/boot/dts/armada-370.dtsi                |   35 ++++++
 arch/arm/boot/dts/armada-xp-db.dts               |   50 +++++++++
 arch/arm/boot/dts/armada-xp.dtsi                 |   55 +++++++++
 arch/arm/mach-mvebu/Kconfig                      |    9 ++
 arch/arm/mach-mvebu/Makefile                     |    1 +
 arch/arm/mach-mvebu/armada-370-xp.c              |   63 +++++++++++
 arch/arm/mach-mvebu/common.h                     |    3 +
 arch/arm/mach-mvebu/include/mach/armada-370-xp.h |   22 ++++
 arch/arm/mach-mvebu/irq-armada-370-xp.c          |  130 ++++++++++++++++++++++
 11 files changed, 478 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-370-db.dts
 create mode 100644 arch/arm/boot/dts/armada-370-xp.dtsi
 create mode 100644 arch/arm/boot/dts/armada-370.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-db.dts
 create mode 100644 arch/arm/boot/dts/armada-xp.dtsi
 create mode 100644 arch/arm/mach-mvebu/armada-370-xp.c
 create mode 100644 arch/arm/mach-mvebu/include/mach/armada-370-xp.h
 create mode 100644 arch/arm/mach-mvebu/irq-armada-370-xp.c

diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
new file mode 100644
index 0000000..fffd5c2
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -0,0 +1,42 @@
+/*
+ * Device Tree file for Marvell Armada 370 evaluation board
+ * (DB-88F6710-BP-DDR3)
+ *
+ *  Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "armada-370.dtsi"
+
+/ {
+	model = "Marvell Armada 370 Evaluation Board";
+	compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>; /* 512 MB */
+	};
+
+	soc {
+		serial at d0012000 {
+			clock-frequency = <200000000>;
+			status = "okay";
+		};
+		timer at d0020300 {
+			clock-frequency = <600000000>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
new file mode 100644
index 0000000..9b55f01
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common to the Armada
+ * 370 and Armada XP SoC.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "Marvell Armada 370 and XP SoC";
+	compatible = "marvell,armada_370_xp";
+
+	cpus {
+		cpu at 0 {
+			compatible = "marvell,sheeva-v7";
+		};
+	};
+
+	mpic: interrupt-controller at d0020000 {
+	      compatible = "marvell,mpic";
+	      #interrupt-cells = <1>;
+	      #address-cells = <1>;
+	      #size-cells = <1>;
+	      interrupt-controller;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&mpic>;
+		ranges;
+
+		serial at d0012000 {
+				compatible = "ns16550";
+				reg = <0xd0012000 0x100>;
+				reg-shift = <2>;
+				interrupts = <41>;
+				status = "disabled";
+		};
+		serial at d0012100 {
+				compatible = "ns16550";
+				reg = <0xd0012100 0x100>;
+				reg-shift = <2>;
+				interrupts = <42>;
+				status = "disabled";
+		};
+
+		timer at d0020300 {
+			       compatible = "marvell,timer";
+			       reg = <0xd0020300 0x30>;
+			       interrupts = <37>, <38>, <39>, <40>;
+		};
+	};
+};
+
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
new file mode 100644
index 0000000..3228ccc
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada 370 SoC that are not
+ * common to all Armada SoCs.
+ */
+
+/include/ "armada-370-xp.dtsi"
+
+/ {
+	model = "Marvell Armada 370 family SoC";
+	compatible = "marvell,armada370", "marvell,armada-370-xp";
+
+	mpic: interrupt-controller at d0020000 {
+	      reg = <0xd0020a00 0x1d0>,
+		    <0xd0021870 0x58>;
+	};
+
+	soc {
+		system-controller at d0018200 {
+				compatible = "marvell,armada-370-xp-system-controller";
+				reg = <0xd0018200 0x100>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
new file mode 100644
index 0000000..f97040d
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -0,0 +1,50 @@
+/*
+ * Device Tree file for Marvell Armada XP evaluation board
+ * (DB-78460-BP)
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP Evaluation Board";
+	compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000>; /* 2 GB */
+	};
+
+	soc {
+		serial at d0012000 {
+			clock-frequency = <250000000>;
+			status = "okay";
+		};
+		serial at d0012100 {
+			clock-frequency = <250000000>;
+			status = "okay";
+		};
+		serial at d0012200 {
+			clock-frequency = <250000000>;
+			status = "okay";
+		};
+		serial at d0012300 {
+			clock-frequency = <250000000>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
new file mode 100644
index 0000000..e1fa7e6
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -0,0 +1,55 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada 370 SoC that are not
+ * common to all Armada SoCs.
+ */
+
+/include/ "armada-370-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
+
+	mpic: interrupt-controller at d0020000 {
+	      reg = <0xd0020a00 0x1d0>,
+		    <0xd0021870 0x58>;
+	};
+
+	soc {
+		serial at d0012200 {
+				compatible = "ns16550";
+				reg = <0xd0012200 0x100>;
+				reg-shift = <2>;
+				interrupts = <43>;
+				status = "disabled";
+		};
+		serial at d0012300 {
+				compatible = "ns16550";
+				reg = <0xd0012300 0x100>;
+				reg-shift = <2>;
+				interrupts = <44>;
+				status = "disabled";
+		};
+
+		timer at d0020300 {
+				marvell,timer-25Mhz;
+		};
+
+		system-controller at d0018200 {
+				compatible = "marvell,armada-370-xp-system-controller";
+				reg = <0xd0018200 0x500>;
+		};
+	};
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 72d39e5..caa2c5e 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -2,6 +2,15 @@ if ARCH_MVEBU
 
 menu "Marvell SOC with device tree"
 
+config MACH_ARMADA_370_XP
+	bool "Marvell Armada 370 and Aramada XP boards"
+	select ARMADA_370_XP_TIMER
+	select CPU_V7
+	help
+
+	  Say 'Y' here if you want your kernel to support boards based on
+	  Marvell Armada 370 or Armada XP with device tree.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 7366ae7..e61d2b8 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1 +1,2 @@
 obj-y += system-controller.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
new file mode 100644
index 0000000..4ef923b
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -0,0 +1,63 @@
+/*
+ * Device Tree support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/time-armada-370-xp.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/armada-370-xp.h>
+#include "common.h"
+
+static struct map_desc armada_370_xp_io_desc[] __initdata = {
+	{
+		.virtual	= ARMADA_370_XP_REGS_VIRT_BASE,
+		.pfn		= __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
+		.length		= ARMADA_370_XP_REGS_SIZE,
+		.type		= MT_DEVICE,
+	},
+};
+
+void __init armada_370_xp_map_io(void)
+{
+	iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
+}
+
+struct sys_timer armada_370_xp_timer = {
+	.init		= armada_370_xp_timer_init,
+};
+
+static void __init armada_370_xp_dt_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const armada_370_xp_dt_board_dt_compat[] = {
+	"marvell,a370-db",
+	"marvell,axp-db",
+	NULL,
+};
+
+DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
+	.init_machine	= armada_370_xp_dt_init,
+	.map_io		= armada_370_xp_map_io,
+	.init_irq	= armada_370_xp_init_irq,
+	.handle_irq     = armada_370_xp_handle_irq,
+	.timer		= &armada_370_xp_timer,
+	.restart	= mvebu_restart,
+	.dt_compat	= armada_370_xp_dt_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index f0eaa21..02f89ea 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -17,4 +17,7 @@
 
 void mvebu_restart(char mode, const char *cmd);
 
+void armada_370_xp_init_irq(void);
+void armada_370_xp_handle_irq(struct pt_regs *regs);
+
 #endif
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
new file mode 100644
index 0000000..25f0ca8
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
@@ -0,0 +1,22 @@
+/*
+ * Generic definitions for Marvell Armada_370_XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_ARMADA_370_XP_H
+#define __MACH_ARMADA_370_XP_H
+
+#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
+#define ARMADA_370_XP_REGS_VIRT_BASE	0xfeb00000
+#define ARMADA_370_XP_REGS_SIZE		SZ_1M
+
+#endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
new file mode 100644
index 0000000..645a8d3
--- /dev/null
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -0,0 +1,130 @@
+/*
+ * Marvell Armada 370 and Armada XP SoC IRQ handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <asm/mach/arch.h>
+#include <asm/exception.h>
+
+/* Interrupt Controller Registers Map */
+#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
+#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
+
+#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
+#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
+
+#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
+
+#define ARMADA_370_XP_NR_IRQS			(115)
+
+static void __iomem *per_cpu_int_base;
+static void __iomem *main_int_base;
+static struct irq_domain *armada_370_xp_mpic_domain;
+
+static void armada_370_xp_irq_mask(struct irq_data *d)
+{
+	writel(irqd_to_hwirq(d),
+	       per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
+}
+
+static void armada_370_xp_irq_unmask(struct irq_data *d)
+{
+	writel(irqd_to_hwirq(d),
+	       per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+}
+
+static struct irq_chip armada_370_xp_irq_chip = {
+	.name		= "armada_370_xp_irq",
+	.irq_mask       = armada_370_xp_irq_mask,
+	.irq_mask_ack   = armada_370_xp_irq_mask,
+	.irq_unmask     = armada_370_xp_irq_unmask,
+};
+
+static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
+				      unsigned int virq, irq_hw_number_t hw)
+{
+	armada_370_xp_irq_mask(irq_get_irq_data(virq));
+	writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+
+	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
+				 handle_level_irq);
+	irq_set_status_flags(virq, IRQ_LEVEL);
+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
+	.map = armada_370_xp_mpic_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static int __init armada_370_xp_mpic_of_init(struct device_node *node,
+					     struct device_node *parent)
+{
+	main_int_base = of_iomap(node, 0);
+	per_cpu_int_base = of_iomap(node, 1);
+
+	BUG_ON(!main_int_base);
+	BUG_ON(!per_cpu_int_base);
+
+	armada_370_xp_mpic_domain =
+	    irq_domain_add_linear(node, ARMADA_370_XP_NR_IRQS,
+				  &armada_370_xp_mpic_irq_ops, NULL);
+
+	if (!armada_370_xp_mpic_domain)
+		panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
+
+	irq_set_default_host(armada_370_xp_mpic_domain);
+	return 0;
+}
+
+asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
+							       *regs)
+{
+	u32 irqstat, irqnr;
+
+	do {
+		irqstat = readl_relaxed(per_cpu_int_base +
+					ARMADA_370_XP_CPU_INTACK_OFFS);
+		irqnr = irqstat & 0x3FF;
+
+		if (irqnr < 1023) {
+			irqnr =
+			    irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
+			handle_IRQ(irqnr, regs);
+			continue;
+		}
+
+		break;
+	} while (1);
+}
+
+static const struct of_device_id mpic_of_match[] __initconst = {
+	{.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
+	{},
+};
+
+void __init armada_370_xp_init_irq(void)
+{
+	of_irq_init(mpic_of_match);
+}
-- 
1.7.9.5

[PATCH 5/9] arm: mach-mvebu: add documentation for new device tree bindings

[Thomas Petazzoni]

From: Gregory CLEMENT <gregory.clement@free-electrons.com>

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
---
 .../devicetree/bindings/arm/armada-370-xp-mpic.txt |   23 +++++++++++++++++++
 .../bindings/arm/armada-370-xp-timer.txt           |   11 +++++++++
 .../devicetree/bindings/arm/armada-370-xp.txt      |   24 ++++++++++++++++++++
 .../bindings/arm/mvebu-system-controller.txt       |   17 ++++++++++++++
 4 files changed, 75 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
 create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
 create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp.txt
 create mode 100644 Documentation/devicetree/bindings/arm/mvebu-system-controller.txt

diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
new file mode 100644
index 0000000..70c0dc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
@@ -0,0 +1,23 @@
+Marvell Armada 370 and Armada XP Interrupt Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible: Should be "marvell,mpic"
+- interrupt-controller: Identifies the node as an interrupt controller.
+- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
+  The cell is the IRQ number
+- reg: Should contain PMIC registers location and length. First pair
+  for the main interrupt registers, second pair for the per-CPU
+  interrupt registers
+
+Example:
+
+        mpic: interrupt-controller at d0020000 {
+              compatible = "marvell,mpic";
+              #interrupt-cells = <1>;
+              #address-cells = <1>;
+              #size-cells = <1>;
+              interrupt-controller;
+              reg = <0xd0020000 0x1000>,
+                    <0xd0021000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
new file mode 100644
index 0000000..d14dc7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
@@ -0,0 +1,11 @@
+Marvell Armada 370 and Armada XP Global Timers
+----------------------------------------------
+
+Required properties:
+- compatible: Should be "marvell,timer"
+- interrupts: Should contain the list of Global Timer interrupts
+- reg: Should contain the base address of the Global Timer registers
+
+Optional properties:
+- marvell,timer-25Mhz: Tells whether the Global timer supports the 25
+  Mhz fixed mode (available on Armada XP and not on Armada 370)
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp.txt b/Documentation/devicetree/bindings/arm/armada-370-xp.txt
new file mode 100644
index 0000000..c6ed90e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp.txt
@@ -0,0 +1,24 @@
+Marvell Armada 370 and Armada XP Platforms Device Tree Bindings
+---------------------------------------------------------------
+
+Boards with a SoC of the Marvell Armada 370 and Armada XP families
+shall have the following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armada-370-xp"
+
+In addition, boards using the Marvell Armada 370 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armada370"
+
+In addition, boards using the Marvell Armada XP SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp"
+
diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
new file mode 100644
index 0000000..081c6a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
@@ -0,0 +1,17 @@
+MVEBU System Controller
+-----------------------
+MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
+
+Required properties:
+
+- compatible: one of:
+	- "marvell,orion-system-controller"
+	- "marvell,armada-370-xp-system-controller"
+- reg: Should contain system controller registers location and length.
+
+Example:
+
+	system-controller at d0018200 {
+		compatible = "marvell,armada-370-xp-system-controller";
+		reg = <0xd0018200 0x500>;
+	};
-- 
1.7.9.5

[PATCH 6/9] arm: mach-mvebu: add defconfig

[Thomas Petazzoni]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
---
 arch/arm/configs/mvebu_defconfig |   46 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 arch/arm/configs/mvebu_defconfig

diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
new file mode 100644
index 0000000..2e86b31
--- /dev/null
+++ b/arch/arm/configs/mvebu_defconfig
@@ -0,0 +1,46 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_MACH_ARMADA_370_XP=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_USE_OF=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_VFP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_UTF8=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
-- 
1.7.9.5

[PATCH 7/9] arm: mach-mvebu: add compilation/configuration change

[Thomas Petazzoni]

From: Gregory CLEMENT <gregory.clement@free-electrons.com>

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
---
 arch/arm/Kconfig  |   14 ++++++++++++++
 arch/arm/Makefile |    1 +
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8e02882..519b5e0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -533,6 +533,18 @@ config ARCH_IXP4XX
 	help
 	  Support for Intel's IXP4XX (XScale) family of processors.
 
+config ARCH_MVEBU
+	bool "Marvell SOCs with Device Tree support"
+	select GENERIC_CLOCKEVENTS
+	select MULTI_IRQ_HANDLER
+	select SPARSE_IRQ
+	select CLKSRC_MMIO
+	select GENERIC_IRQ_CHIP
+	select IRQ_DOMAIN
+	select COMMON_CLK
+	help
+	  Support for the Marvell SoC Family with device tree support
+
 config ARCH_DOVE
 	bool "Marvell Dove"
 	select CPU_V7
@@ -987,6 +999,8 @@ endchoice
 # Kconfigs may be included either alphabetically (according to the
 # plat- suffix) or along side the corresponding mach-* source.
 #
+source "arch/arm/mach-mvebu/Kconfig"
+
 source "arch/arm/mach-at91/Kconfig"
 
 source "arch/arm/mach-bcmring/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0298b00..f1a1a71 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -157,6 +157,7 @@ machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
 machine-$(CONFIG_ARCH_IMX_V4_V5)	:= imx
 machine-$(CONFIG_ARCH_IMX_V6_V7)	:= imx
 machine-$(CONFIG_ARCH_MXS)		:= mxs
+machine-$(CONFIG_ARCH_MVEBU)		:= mvebu
 machine-$(CONFIG_ARCH_NETX)		:= netx
 machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik
 machine-$(CONFIG_ARCH_OMAP1)		:= omap1
-- 
1.7.9.5

[PATCH 8/9] arm: mach-mvebu: add entry to MAINTAINERS

[Thomas Petazzoni]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
---
 MAINTAINERS |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index eb22272..050b7fe 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -894,6 +894,14 @@ ARM/MAGICIAN MACHINE SUPPORT
 M:	Philipp Zabel <philipp.zabel@gmail.com>
 S:	Maintained
 
+ARM/Marvell Armada 370 and Armada XP SOC support
+M:	Gregory Clement <gregory.clement@free-electrons.com>
+M:	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+M:	Lior Amsalem <alior@marvell.com>
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	arch/arm/mach-mvebu/
+
 ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
 M:	Jason Cooper <jason@lakedaemon.net>
 M:	Andrew Lunn <andrew@lunn.ch>
-- 
1.7.9.5

[PATCH 9/9] ARM: mvebu: MPIC: read number of interrupts from control register

[Thomas Petazzoni]

From: Ben Dooks <ben.dooks@codethink.co.uk>

Read the number of MPIC interrupts from the controller and only register
that many.

[gregory.clement at free-electrons.com: rename armada symbol name to fit
with new name: armada_370_xp]

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
---
 arch/arm/mach-mvebu/irq-armada-370-xp.c |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 645a8d3..5f5f939 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -29,13 +29,12 @@
 #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
 
+#define ARMADA_370_XP_INT_CONTROL		(0x00)
 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
 
 #define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
 
-#define ARMADA_370_XP_NR_IRQS			(115)
-
 static void __iomem *per_cpu_int_base;
 static void __iomem *main_int_base;
 static struct irq_domain *armada_370_xp_mpic_domain;
@@ -81,14 +80,18 @@ static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 					     struct device_node *parent)
 {
+	u32 control;
+
 	main_int_base = of_iomap(node, 0);
 	per_cpu_int_base = of_iomap(node, 1);
 
 	BUG_ON(!main_int_base);
 	BUG_ON(!per_cpu_int_base);
 
+	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
+
 	armada_370_xp_mpic_domain =
-	    irq_domain_add_linear(node, ARMADA_370_XP_NR_IRQS,
+	    irq_domain_add_linear(node, (control >> 2) & 0x3ff,
 				  &armada_370_xp_mpic_irq_ops, NULL);
 
 	if (!armada_370_xp_mpic_domain)
-- 
1.7.9.5

[PATCH 1/9] clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver

[Thomas Gleixner]

On Mon, 2 Jul 2012, Thomas Petazzoni wrote:

> From: Gregory Clement <gregory.clement@free-electrons.com>
> 
> Timer 0 is used as free-running clocksource, while timer 1 is used as
> clock_event_device.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Lior Amsalem <alior@marvell.com>

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>

[PATCH 2/9] arm: mach-mvebu: add header

[Andrew Lunn]

> +++ b/arch/arm/mach-mvebu/include/mach/uncompress.h
> @@ -0,0 +1,43 @@
> +/*
> + * Marvell Armada SoC kernel uncompression UART routines
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <mach/armada-370-xp.h>
> +
> +#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
> +								+ 0x12000))
> +#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
> +								+ 0x12014))
> +

Hi Thomas

What physical address does this come out to? All Orion platforms have
the serial port at the same place, 0xf1012000. If 370/XP is the same,
i suggest dropping this #include, hard code the address, and we share
the implementation for all SoCs. 

If however, the ASIC engineers have decided to move it, we need some
extra logic to handle different base addresses for Dove and 370/XP
which should be supportable in one kernel binary.

      Andrew

[PATCH 2/9] arm: mach-mvebu: add header

[Thomas Petazzoni]

Hello Andrew,

Le Mon, 2 Jul 2012 20:33:30 +0200,
Andrew Lunn <andrew@lunn.ch> a ?crit :

> What physical address does this come out to? All Orion platforms have
> the serial port at the same place, 0xf1012000. If 370/XP is the same,
> i suggest dropping this #include, hard code the address, and we share
> the implementation for all SoCs. 
> 
> If however, the ASIC engineers have decided to move it, we need some
> extra logic to handle different base addresses for Dove and 370/XP
> which should be supportable in one kernel binary.

As per armada-370-xp.h:

#define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000

The physical address of the internal registers is 0xd0000000. It does
not seem to be configurable using the address decoding mechanism.

OMAP has some logic to handle this kind of problems, see
plat-omap/include/plat/uncompress.h. We can quite certainly overcome
this problem somehow.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 2/9] arm: mach-mvebu: add header

[Andrew Lunn]

> OMAP has some logic to handle this kind of problems, see
> plat-omap/include/plat/uncompress.h. We can quite certainly overcome
> this problem somehow.

That file says:

         * Initialize the port based on the machine ID from the bootloader.

Which when using DT we don't have.

As you said, we can overcome this somehow. We just need to be aware
there will be changes here.

It would also be nice if Marvell ASIC engineers didn't randomly move
things around in the address space....

       Andrew

[PATCH 2/9] arm: mach-mvebu: add header

[Arnd Bergmann]

On Monday 02 July 2012, Andrew Lunn wrote:
> > OMAP has some logic to handle this kind of problems, see
> > plat-omap/include/plat/uncompress.h. We can quite certainly overcome
> > this problem somehow.
> 
> That file says:
> 
>          * Initialize the port based on the machine ID from the bootloader.
> 
> Which when using DT we don't have.
> 
> As you said, we can overcome this somehow. We just need to be aware
> there will be changes here.
> 
> It would also be nice if Marvell ASIC engineers didn't randomly move
> things around in the address space....

For now, I'd suggest you don't try too hard to make this work for the
a combination of the mvebu platforms. There has been some discussion
about a solution that will work across multiple platform directories.
While that might take a little longer, I assume that we will find some
way to do it, so let's first unify all the other header files within
mvebu.

	Arnd

[PATCH 2/9] arm: mach-mvebu: add header

[Nicolas Pitre]

On Mon, 2 Jul 2012, Andrew Lunn wrote:

> It would also be nice if Marvell ASIC engineers didn't randomly move
> things around in the address space....

They didn't.  The _software_ engineers did.

As you might know, the Orion and Kirkwood SOCs have programmable 
physical windows for most things, including PCI IO window, PCI mem 
window, SDRAM window, NAND controller window, bridge peripheral window, 
etc.  

So you can change your physical address space as you wish.  This was 
made to accommodate whether you are a PCI host or a PCI client (think 
wifi cards which are in the later category but still with this window 
control block).  This is also how the various SDRAM banks are remapped to 
appear as a contiguous chunk of physical memory regardless of the 
populated memory size in each bank.

Most of this is being partly set up (or set again) in the various 
addr-map.c files.

Now it seems that all the u-Boot implementations for Orion/Kirkwood out 
there have always moved the window containing the serial ports from its 
default 0xd0000000 address to 0xf1000000.  Why they did that I have no 
idea.  And Linux simply took those remapped physical addresses as 
authoritative.

And whether or not Armada 370/XP still have this physical remap ability 
I don't know.  And if it does, then why didn't it follow the same 
0xf1000000 tradition as all the other mvebu targets before them I don't 
know either.  Maybe this could be considered?


Nicolas

[PATCH 2/9] arm: mach-mvebu: add header

[Andrew Lunn]

On Mon, Jul 02, 2012 at 11:48:42PM -0400, Nicolas Pitre wrote:
> On Mon, 2 Jul 2012, Andrew Lunn wrote:
> 
> > It would also be nice if Marvell ASIC engineers didn't randomly move
> > things around in the address space....
> 
> They didn't.  The _software_ engineers did.

Ah, interesting. I never got that deep into the address mapping, i
just mechanically refactered it across all Orions without take too
much time to really understand what its doing.

> Now it seems that all the u-Boot implementations for Orion/Kirkwood out 
> there have always moved the window containing the serial ports from its 
> default 0xd0000000 address to 0xf1000000.  Why they did that I have no 
> idea.  And Linux simply took those remapped physical addresses as 
> authoritative.
> 
> And whether or not Armada 370/XP still have this physical remap ability 
> I don't know.  And if it does, then why didn't it follow the same 
> 0xf1000000 tradition as all the other mvebu targets before them I don't 
> know either.  Maybe this could be considered?

Thomas, Gregory, could you look at this?

Are the uboot source open, or are you using a proprietary Marvell
version?

When Arnd first proposed moving everything into one directory, i had a
quick look at the memory map. The Orions have more than just the
serial ports at the same address. If i remember correctly, I2C, SPI,
PCIE0, USB0, XOR, and ETH0 are all at the same physical
address. Unfortunately, they have different virtual addresses. So I
played around unifying the virtual address map.

Doing this will allow some code simplification, header file
simplification, and sharing of some .dtsi and DT across all Orion
systems.

Its not something i want to do right now, but having 370/XP the same
as Orion would be a step towards this.

	Andrew

[PATCH 2/9] arm: mach-mvebu: add header

[Thomas Petazzoni]

Hello,

Le Tue, 3 Jul 2012 09:09:27 +0200,
Andrew Lunn <andrew@lunn.ch> a ?crit :

> > Now it seems that all the u-Boot implementations for Orion/Kirkwood out 
> > there have always moved the window containing the serial ports from its 
> > default 0xd0000000 address to 0xf1000000.  Why they did that I have no 
> > idea.  And Linux simply took those remapped physical addresses as 
> > authoritative.
> > 
> > And whether or not Armada 370/XP still have this physical remap ability 
> > I don't know.  And if it does, then why didn't it follow the same 
> > 0xf1000000 tradition as all the other mvebu targets before them I don't 
> > know either.  Maybe this could be considered?
> 
> Thomas, Gregory, could you look at this?

Yes, we will look into this with Marvell engineers.

> Are the uboot source open, or are you using a proprietary Marvell
> version?

As far as I know, there is no support in upstream U-Boot for Armada 370
and XP. We're currently using the internal Marvell U-Boot.

> When Arnd first proposed moving everything into one directory, i had a
> quick look at the memory map. The Orions have more than just the
> serial ports at the same address. If i remember correctly, I2C, SPI,
> PCIE0, USB0, XOR, and ETH0 are all at the same physical
> address. Unfortunately, they have different virtual addresses. So I
> played around unifying the virtual address map.
> 
> Doing this will allow some code simplification, header file
> simplification, and sharing of some .dtsi and DT across all Orion
> systems.
> 
> Its not something i want to do right now, but having 370/XP the same
> as Orion would be a step towards this.

That sounds like a good idea of course, if possible.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 1/9] clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver

[Andrew Lunn]

> +{
> +	u32 u;
> +	struct device_node *np;
> +	unsigned int timer_clk;
> +	int ret;
> +	np = of_find_compatible_node(NULL, NULL, "marvell,timer");

Hi Thomas

"marvell,timer" is too generic. I would suggest using
marvell,armada-370-xp-timer, the same prefix as for the system
controller. It allows us to extend the code to handle Orion platforms,
in the same way the system controller does.

   Andrew

[PATCH 2/9] arm: mach-mvebu: add header

[Andrew Lunn]

On Mon, Jul 02, 2012 at 05:39:27PM +0200, Thomas Petazzoni wrote:
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Lior Amsalem <alior@marvell.com>
> ---
>  arch/arm/mach-mvebu/include/mach/debug-macro.S |   24 +++++++++++++
>  arch/arm/mach-mvebu/include/mach/timex.h       |   13 +++++++
>  arch/arm/mach-mvebu/include/mach/uncompress.h  |   43 ++++++++++++++++++++++++
>  3 files changed, 80 insertions(+)
>  create mode 100644 arch/arm/mach-mvebu/include/mach/debug-macro.S
>  create mode 100644 arch/arm/mach-mvebu/include/mach/timex.h
>  create mode 100644 arch/arm/mach-mvebu/include/mach/uncompress.h
> 
> diff --git a/arch/arm/mach-mvebu/include/mach/debug-macro.S b/arch/arm/mach-mvebu/include/mach/debug-macro.S
> new file mode 100644
> index 0000000..2282576
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/include/mach/debug-macro.S
> @@ -0,0 +1,24 @@
> +/*
> + * Early serial output macro for Marvell  SoC
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory Clement <gregory.clement@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <mach/armada-370-xp.h>
> +
> +	.macro	addruart, rp, rv, tmp
> +	ldr	\rp, =ARMADA_370_XP_REGS_PHYS_BASE
> +	ldr	\rv, =ARMADA_370_XP_REGS_VIRT_BASE
> +	orr	\rp, \rp, #0x00012000
> +	orr	\rv, \rv, #0x00012000
> +	.endm
> +
> +#define UART_SHIFT	2
> +#include <asm/hardware/debug-8250.S>
> diff --git a/arch/arm/mach-mvebu/include/mach/timex.h b/arch/arm/mach-mvebu/include/mach/timex.h
> new file mode 100644
> index 0000000..ab324a3
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/include/mach/timex.h
> @@ -0,0 +1,13 @@
> +/*
> + * Marvell Armada SoC time definitions
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#define CLOCK_TICK_RATE		(100 * HZ)
> diff --git a/arch/arm/mach-mvebu/include/mach/uncompress.h b/arch/arm/mach-mvebu/include/mach/uncompress.h
> new file mode 100644
> index 0000000..d6a100c
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/include/mach/uncompress.h
> @@ -0,0 +1,43 @@
> +/*
> + * Marvell Armada SoC kernel uncompression UART routines
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <mach/armada-370-xp.h>
> +
> +#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
> +								+ 0x12000))
> +#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
> +								+ 0x12014))
> +
> +#define LSR_THRE	0x20
> +
> +static void putc(const char c)
> +{
> +	int i;
> +
> +	for (i = 0; i < 0x1000; i++) {
> +		/* Transmit fifo not full? */
> +		if (*UART_LSR & LSR_THRE)
> +			break;
> +	}
> +
> +	*UART_THR = c;
> +}
> +
> +static void flush(void)
> +{
> +}
> +
> +/*
> + * nothing to do
> + */
> +#define arch_decomp_setup()
> +#define arch_decomp_wdog()
> -- 
> 1.7.9.5
> 

Acked-by: Andrew Lunn <andrew@lunn.ch>

[PATCH 3/9] arm: mach-mvebu: add source files

[Andrew Lunn]

On Mon, Jul 02, 2012 at 05:39:28PM +0200, Thomas Petazzoni wrote:
> From: Gregory CLEMENT <gregory.clement@free-electrons.com>
> 
> [ben.dooks at codethink.co.uk: fixup style error in system-controller]
> [ben.dooks at codethink.co.uk: check result of of_match_node()]
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Lior Amsalem <alior@marvell.com>
> ---
>  arch/arm/mach-mvebu/Kconfig             |    7 +++
>  arch/arm/mach-mvebu/Makefile            |    1 +
>  arch/arm/mach-mvebu/Makefile.boot       |    1 +
>  arch/arm/mach-mvebu/common.h            |   20 ++++++
>  arch/arm/mach-mvebu/system-controller.c |  105 +++++++++++++++++++++++++++++++
>  5 files changed, 134 insertions(+)
>  create mode 100644 arch/arm/mach-mvebu/Kconfig
>  create mode 100644 arch/arm/mach-mvebu/Makefile
>  create mode 100644 arch/arm/mach-mvebu/Makefile.boot
>  create mode 100644 arch/arm/mach-mvebu/common.h
>  create mode 100644 arch/arm/mach-mvebu/system-controller.c
> 
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> new file mode 100644
> index 0000000..72d39e5
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -0,0 +1,7 @@
> +if ARCH_MVEBU
> +
> +menu "Marvell SOC with device tree"
> +
> +endmenu
> +
> +endif
> diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
> new file mode 100644
> index 0000000..7366ae7
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/Makefile
> @@ -0,0 +1 @@
> +obj-y += system-controller.o
> diff --git a/arch/arm/mach-mvebu/Makefile.boot b/arch/arm/mach-mvebu/Makefile.boot
> new file mode 100644
> index 0000000..b327175
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/Makefile.boot
> @@ -0,0 +1 @@
> +zreladdr-y := 0x00008000
> diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
> new file mode 100644
> index 0000000..f0eaa21
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/common.h
> @@ -0,0 +1,20 @@
> +/*
> + * Core functions for Marvell System On Chip
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __ARCH_MVEBU_COMMON_H
> +#define __ARCH_MVEBU_COMMON_H
> +
> +void mvebu_restart(char mode, const char *cmd);
> +
> +#endif
> diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
> new file mode 100644
> index 0000000..b8079df
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/system-controller.c
> @@ -0,0 +1,105 @@
> +/*
> + * System controller support for Armada 370 and XP platforms.
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + *
> + * The Armada 370 and Armada XP SoCs both have a range of
> + * miscellaneous registers, that do not belong to a particular device,
> + * but rather provide system-level features. This basic
> + * system-controller driver provides a device tree binding for those
> + * registers, and implements utility functions offering various
> + * features related to those registers.
> + *
> + * For now, the feature set is limited to restarting the platform by a
> + * soft-reset, but it might be extended in the future.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/of_address.h>
> +#include <linux/io.h>
> +
> +static void __iomem *system_controller_base;
> +
> +struct mvebu_system_controller {
> +	u32 rstoutn_mask_offset;
> +	u32 system_soft_reset_offset;
> +
> +	u32 rstoutn_mask_reset_out_en;
> +	u32 system_soft_reset;
> +};
> +static struct mvebu_system_controller *mvebu_sc;
> +
> +const struct mvebu_system_controller armada_370_xp_system_controller = {
> +	.rstoutn_mask_offset = 0x60,
> +	.system_soft_reset_offset = 0x64,
> +	.rstoutn_mask_reset_out_en = 0x1,
> +	.system_soft_reset = 0x1,
> +};
> +
> +const struct mvebu_system_controller orion_system_controller = {
> +	.rstoutn_mask_offset = 0x108,
> +	.system_soft_reset_offset = 0x10c,
> +	.rstoutn_mask_reset_out_en = 0x4,
> +	.system_soft_reset = 0x1,
> +};
> +
> +static struct of_device_id of_system_controller_table[] = {
> +	{
> +		.compatible = "marvell,orion-system-controller",
> +		.data = (void *) &orion_system_controller,
> +	}, {
> +		.compatible = "marvell,armada-370-xp-system-controller",
> +		.data = (void *) &armada_370_xp_system_controller,
> +	},
> +	{ /* end of list */ },
> +};
> +
> +void mvebu_restart(char mode, const char *cmd)
> +{
> +	if (!system_controller_base) {
> +		pr_err("Cannot restart, system-controller not available: check the device tree\n");
> +	} else {
> +		/*
> +		 * Enable soft reset to assert RSTOUTn.
> +		 */
> +		writel(mvebu_sc->rstoutn_mask_reset_out_en,
> +			system_controller_base +
> +			mvebu_sc->rstoutn_mask_offset);
> +		/*
> +		 * Assert soft reset.
> +		 */
> +		writel(mvebu_sc->system_soft_reset,
> +			system_controller_base +
> +			mvebu_sc->system_soft_reset_offset);
> +	}
> +
> +	while (1)
> +		;
> +}
> +
> +static int __init mvebu_system_controller_init(void)
> +{
> +	struct device_node *np;
> +
> +	np = of_find_matching_node(NULL, of_system_controller_table);
> +	if (np) {
> +		const struct of_device_id *match =
> +		    of_match_node(of_system_controller_table, np);
> +		BUG_ON(!match);
> +		system_controller_base = of_iomap(np, 0);
> +		mvebu_sc = (struct mvebu_system_controller *)match->data;
> +	}
> +
> +	return 0;
> +}
> +
> +arch_initcall(mvebu_system_controller_init);
> -- 
> 1.7.9.5
> 

Acked-by: Andrew Lunn <andrew@lunn.ch>

I also already sent a tested-by: which you failed to add. I don't
think the changed are particularly significant, so please keep it.

      Andrew

[PATCH 4/9] arm: mach-mvebu: add support for Armada 370 and Armada XP with DT

[Andrew Lunn]

On Mon, Jul 02, 2012 at 05:39:29PM +0200, Thomas Petazzoni wrote:
> [ben.dooks at codethink.co.uk: ensure error check on of_property_read_u32]
> [ben.dooks at codethink.co.uk: use mpic address instead of bus-unit's ]
> [ben.dooks at codethink.co.uk: BUG_ON() if the of_iomap() fails for mpic]
> [ben.dooks at codethink.co.uk: move mpic per-cpu register base ]
> [ben.dooks at codethink.co.uk: number fetch should use irqd_to_hwirq()]
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Lior Amsalem <alior@marvell.com>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
>  arch/arm/boot/dts/armada-370-db.dts              |   42 +++++++
>  arch/arm/boot/dts/armada-370-xp.dtsi             |   68 +++++++++++
>  arch/arm/boot/dts/armada-370.dtsi                |   35 ++++++
>  arch/arm/boot/dts/armada-xp-db.dts               |   50 +++++++++
>  arch/arm/boot/dts/armada-xp.dtsi                 |   55 +++++++++
>  arch/arm/mach-mvebu/Kconfig                      |    9 ++
>  arch/arm/mach-mvebu/Makefile                     |    1 +
>  arch/arm/mach-mvebu/armada-370-xp.c              |   63 +++++++++++
>  arch/arm/mach-mvebu/common.h                     |    3 +
>  arch/arm/mach-mvebu/include/mach/armada-370-xp.h |   22 ++++
>  arch/arm/mach-mvebu/irq-armada-370-xp.c          |  130 ++++++++++++++++++++++
>  11 files changed, 478 insertions(+)
>  create mode 100644 arch/arm/boot/dts/armada-370-db.dts
>  create mode 100644 arch/arm/boot/dts/armada-370-xp.dtsi
>  create mode 100644 arch/arm/boot/dts/armada-370.dtsi
>  create mode 100644 arch/arm/boot/dts/armada-xp-db.dts
>  create mode 100644 arch/arm/boot/dts/armada-xp.dtsi
>  create mode 100644 arch/arm/mach-mvebu/armada-370-xp.c
>  create mode 100644 arch/arm/mach-mvebu/include/mach/armada-370-xp.h
>  create mode 100644 arch/arm/mach-mvebu/irq-armada-370-xp.c

Acked-by: Andrew Lunn <andrew@lunn.ch>


> 
> diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
> new file mode 100644
> index 0000000..fffd5c2
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-370-db.dts
> @@ -0,0 +1,42 @@
> +/*
> + * Device Tree file for Marvell Armada 370 evaluation board
> + * (DB-88F6710-BP-DDR3)
> + *
> + *  Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +/include/ "armada-370.dtsi"
> +
> +/ {
> +	model = "Marvell Armada 370 Evaluation Board";
> +	compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200 earlyprintk";
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x20000000>; /* 512 MB */
> +	};
> +
> +	soc {
> +		serial at d0012000 {
> +			clock-frequency = <200000000>;
> +			status = "okay";
> +		};
> +		timer at d0020300 {
> +			clock-frequency = <600000000>;
> +			status = "okay";
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
> new file mode 100644
> index 0000000..9b55f01
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -0,0 +1,68 @@
> +/*
> + * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + * Ben Dooks <ben.dooks@codethink.co.uk>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + *
> + * This file contains the definitions that are common to the Armada
> + * 370 and Armada XP SoC.
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	model = "Marvell Armada 370 and XP SoC";
> +	compatible = "marvell,armada_370_xp";
> +
> +	cpus {
> +		cpu at 0 {
> +			compatible = "marvell,sheeva-v7";
> +		};
> +	};
> +
> +	mpic: interrupt-controller at d0020000 {
> +	      compatible = "marvell,mpic";
> +	      #interrupt-cells = <1>;
> +	      #address-cells = <1>;
> +	      #size-cells = <1>;
> +	      interrupt-controller;
> +	};
> +
> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&mpic>;
> +		ranges;
> +
> +		serial at d0012000 {
> +				compatible = "ns16550";
> +				reg = <0xd0012000 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <41>;
> +				status = "disabled";
> +		};
> +		serial at d0012100 {
> +				compatible = "ns16550";
> +				reg = <0xd0012100 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <42>;
> +				status = "disabled";
> +		};
> +
> +		timer at d0020300 {
> +			       compatible = "marvell,timer";
> +			       reg = <0xd0020300 0x30>;
> +			       interrupts = <37>, <38>, <39>, <40>;
> +		};
> +	};
> +};
> +
> diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
> new file mode 100644
> index 0000000..3228ccc
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-370.dtsi
> @@ -0,0 +1,35 @@
> +/*
> + * Device Tree Include file for Marvell Armada 370 family SoC
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + *
> + * Contains definitions specific to the Armada 370 SoC that are not
> + * common to all Armada SoCs.
> + */
> +
> +/include/ "armada-370-xp.dtsi"
> +
> +/ {
> +	model = "Marvell Armada 370 family SoC";
> +	compatible = "marvell,armada370", "marvell,armada-370-xp";
> +
> +	mpic: interrupt-controller at d0020000 {
> +	      reg = <0xd0020a00 0x1d0>,
> +		    <0xd0021870 0x58>;
> +	};
> +
> +	soc {
> +		system-controller at d0018200 {
> +				compatible = "marvell,armada-370-xp-system-controller";
> +				reg = <0xd0018200 0x100>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
> new file mode 100644
> index 0000000..f97040d
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-db.dts
> @@ -0,0 +1,50 @@
> +/*
> + * Device Tree file for Marvell Armada XP evaluation board
> + * (DB-78460-BP)
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +/include/ "armada-xp.dtsi"
> +
> +/ {
> +	model = "Marvell Armada XP Evaluation Board";
> +	compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200 earlyprintk";
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x80000000>; /* 2 GB */
> +	};
> +
> +	soc {
> +		serial at d0012000 {
> +			clock-frequency = <250000000>;
> +			status = "okay";
> +		};
> +		serial at d0012100 {
> +			clock-frequency = <250000000>;
> +			status = "okay";
> +		};
> +		serial at d0012200 {
> +			clock-frequency = <250000000>;
> +			status = "okay";
> +		};
> +		serial at d0012300 {
> +			clock-frequency = <250000000>;
> +			status = "okay";
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
> new file mode 100644
> index 0000000..e1fa7e6
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp.dtsi
> @@ -0,0 +1,55 @@
> +/*
> + * Device Tree Include file for Marvell Armada XP family SoC
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + * Ben Dooks <ben.dooks@codethink.co.uk>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + *
> + * Contains definitions specific to the Armada 370 SoC that are not
> + * common to all Armada SoCs.
> + */
> +
> +/include/ "armada-370-xp.dtsi"
> +
> +/ {
> +	model = "Marvell Armada XP family SoC";
> +	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
> +
> +	mpic: interrupt-controller at d0020000 {
> +	      reg = <0xd0020a00 0x1d0>,
> +		    <0xd0021870 0x58>;
> +	};
> +
> +	soc {
> +		serial at d0012200 {
> +				compatible = "ns16550";
> +				reg = <0xd0012200 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <43>;
> +				status = "disabled";
> +		};
> +		serial at d0012300 {
> +				compatible = "ns16550";
> +				reg = <0xd0012300 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <44>;
> +				status = "disabled";
> +		};
> +
> +		timer at d0020300 {
> +				marvell,timer-25Mhz;
> +		};
> +
> +		system-controller at d0018200 {
> +				compatible = "marvell,armada-370-xp-system-controller";
> +				reg = <0xd0018200 0x500>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 72d39e5..caa2c5e 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -2,6 +2,15 @@ if ARCH_MVEBU
>  
>  menu "Marvell SOC with device tree"
>  
> +config MACH_ARMADA_370_XP
> +	bool "Marvell Armada 370 and Aramada XP boards"
> +	select ARMADA_370_XP_TIMER
> +	select CPU_V7
> +	help
> +
> +	  Say 'Y' here if you want your kernel to support boards based on
> +	  Marvell Armada 370 or Armada XP with device tree.
> +
>  endmenu
>  
>  endif
> diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
> index 7366ae7..e61d2b8 100644
> --- a/arch/arm/mach-mvebu/Makefile
> +++ b/arch/arm/mach-mvebu/Makefile
> @@ -1 +1,2 @@
>  obj-y += system-controller.o
> +obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
> diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
> new file mode 100644
> index 0000000..4ef923b
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/armada-370-xp.c
> @@ -0,0 +1,63 @@
> +/*
> + * Device Tree support for Armada 370 and XP platforms.
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/of_platform.h>
> +#include <linux/io.h>
> +#include <linux/time-armada-370-xp.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
> +#include <asm/mach/time.h>
> +#include <mach/armada-370-xp.h>
> +#include "common.h"
> +
> +static struct map_desc armada_370_xp_io_desc[] __initdata = {
> +	{
> +		.virtual	= ARMADA_370_XP_REGS_VIRT_BASE,
> +		.pfn		= __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
> +		.length		= ARMADA_370_XP_REGS_SIZE,
> +		.type		= MT_DEVICE,
> +	},
> +};
> +
> +void __init armada_370_xp_map_io(void)
> +{
> +	iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
> +}
> +
> +struct sys_timer armada_370_xp_timer = {
> +	.init		= armada_370_xp_timer_init,
> +};
> +
> +static void __init armada_370_xp_dt_init(void)
> +{
> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +}
> +
> +static const char * const armada_370_xp_dt_board_dt_compat[] = {
> +	"marvell,a370-db",
> +	"marvell,axp-db",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
> +	.init_machine	= armada_370_xp_dt_init,
> +	.map_io		= armada_370_xp_map_io,
> +	.init_irq	= armada_370_xp_init_irq,
> +	.handle_irq     = armada_370_xp_handle_irq,
> +	.timer		= &armada_370_xp_timer,
> +	.restart	= mvebu_restart,
> +	.dt_compat	= armada_370_xp_dt_board_dt_compat,
> +MACHINE_END
> diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
> index f0eaa21..02f89ea 100644
> --- a/arch/arm/mach-mvebu/common.h
> +++ b/arch/arm/mach-mvebu/common.h
> @@ -17,4 +17,7 @@
>  
>  void mvebu_restart(char mode, const char *cmd);
>  
> +void armada_370_xp_init_irq(void);
> +void armada_370_xp_handle_irq(struct pt_regs *regs);
> +
>  #endif
> diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
> new file mode 100644
> index 0000000..25f0ca8
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
> @@ -0,0 +1,22 @@
> +/*
> + * Generic definitions for Marvell Armada_370_XP SoCs
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __MACH_ARMADA_370_XP_H
> +#define __MACH_ARMADA_370_XP_H
> +
> +#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
> +#define ARMADA_370_XP_REGS_VIRT_BASE	0xfeb00000
> +#define ARMADA_370_XP_REGS_SIZE		SZ_1M
> +
> +#endif /* __MACH_ARMADA_370_XP_H */
> diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
> new file mode 100644
> index 0000000..645a8d3
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
> @@ -0,0 +1,130 @@
> +/*
> + * Marvell Armada 370 and Armada XP SoC IRQ handling
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + * Ben Dooks <ben.dooks@codethink.co.uk>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/irq.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/irqdomain.h>
> +#include <asm/mach/arch.h>
> +#include <asm/exception.h>
> +
> +/* Interrupt Controller Registers Map */
> +#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
> +#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
> +
> +#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
> +#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
> +
> +#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
> +
> +#define ARMADA_370_XP_NR_IRQS			(115)
> +
> +static void __iomem *per_cpu_int_base;
> +static void __iomem *main_int_base;
> +static struct irq_domain *armada_370_xp_mpic_domain;
> +
> +static void armada_370_xp_irq_mask(struct irq_data *d)
> +{
> +	writel(irqd_to_hwirq(d),
> +	       per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
> +}
> +
> +static void armada_370_xp_irq_unmask(struct irq_data *d)
> +{
> +	writel(irqd_to_hwirq(d),
> +	       per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
> +}
> +
> +static struct irq_chip armada_370_xp_irq_chip = {
> +	.name		= "armada_370_xp_irq",
> +	.irq_mask       = armada_370_xp_irq_mask,
> +	.irq_mask_ack   = armada_370_xp_irq_mask,
> +	.irq_unmask     = armada_370_xp_irq_unmask,
> +};
> +
> +static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
> +				      unsigned int virq, irq_hw_number_t hw)
> +{
> +	armada_370_xp_irq_mask(irq_get_irq_data(virq));
> +	writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
> +
> +	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
> +				 handle_level_irq);
> +	irq_set_status_flags(virq, IRQ_LEVEL);
> +	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
> +
> +	return 0;
> +}
> +
> +static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
> +	.map = armada_370_xp_mpic_irq_map,
> +	.xlate = irq_domain_xlate_onecell,
> +};
> +
> +static int __init armada_370_xp_mpic_of_init(struct device_node *node,
> +					     struct device_node *parent)
> +{
> +	main_int_base = of_iomap(node, 0);
> +	per_cpu_int_base = of_iomap(node, 1);
> +
> +	BUG_ON(!main_int_base);
> +	BUG_ON(!per_cpu_int_base);
> +
> +	armada_370_xp_mpic_domain =
> +	    irq_domain_add_linear(node, ARMADA_370_XP_NR_IRQS,
> +				  &armada_370_xp_mpic_irq_ops, NULL);
> +
> +	if (!armada_370_xp_mpic_domain)
> +		panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
> +
> +	irq_set_default_host(armada_370_xp_mpic_domain);
> +	return 0;
> +}
> +
> +asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
> +							       *regs)
> +{
> +	u32 irqstat, irqnr;
> +
> +	do {
> +		irqstat = readl_relaxed(per_cpu_int_base +
> +					ARMADA_370_XP_CPU_INTACK_OFFS);
> +		irqnr = irqstat & 0x3FF;
> +
> +		if (irqnr < 1023) {
> +			irqnr =
> +			    irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
> +			handle_IRQ(irqnr, regs);
> +			continue;
> +		}
> +
> +		break;
> +	} while (1);
> +}
> +
> +static const struct of_device_id mpic_of_match[] __initconst = {
> +	{.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
> +	{},
> +};
> +
> +void __init armada_370_xp_init_irq(void)
> +{
> +	of_irq_init(mpic_of_match);
> +}
> -- 
> 1.7.9.5
> 

[PATCH 7/9] arm: mach-mvebu: add compilation/configuration change

[Andrew Lunn]

On Mon, Jul 02, 2012 at 05:39:32PM +0200, Thomas Petazzoni wrote:
> From: Gregory CLEMENT <gregory.clement@free-electrons.com>
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Lior Amsalem <alior@marvell.com>
> ---
>  arch/arm/Kconfig  |   14 ++++++++++++++
>  arch/arm/Makefile |    1 +
>  2 files changed, 15 insertions(+)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 8e02882..519b5e0 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -533,6 +533,18 @@ config ARCH_IXP4XX
>  	help
>  	  Support for Intel's IXP4XX (XScale) family of processors.
>  
> +config ARCH_MVEBU
> +	bool "Marvell SOCs with Device Tree support"
> +	select GENERIC_CLOCKEVENTS
> +	select MULTI_IRQ_HANDLER
> +	select SPARSE_IRQ
> +	select CLKSRC_MMIO
> +	select GENERIC_IRQ_CHIP
> +	select IRQ_DOMAIN
> +	select COMMON_CLK
> +	help
> +	  Support for the Marvell SoC Family with device tree support
> +
>  config ARCH_DOVE
>  	bool "Marvell Dove"
>  	select CPU_V7
> @@ -987,6 +999,8 @@ endchoice
>  # Kconfigs may be included either alphabetically (according to the
>  # plat- suffix) or along side the corresponding mach-* source.
>  #
> +source "arch/arm/mach-mvebu/Kconfig"
> +
>  source "arch/arm/mach-at91/Kconfig"
>  
>  source "arch/arm/mach-bcmring/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 0298b00..f1a1a71 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -157,6 +157,7 @@ machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
>  machine-$(CONFIG_ARCH_IMX_V4_V5)	:= imx
>  machine-$(CONFIG_ARCH_IMX_V6_V7)	:= imx
>  machine-$(CONFIG_ARCH_MXS)		:= mxs
> +machine-$(CONFIG_ARCH_MVEBU)		:= mvebu
>  machine-$(CONFIG_ARCH_NETX)		:= netx
>  machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik
>  machine-$(CONFIG_ARCH_OMAP1)		:= omap1
> -- 
> 1.7.9.5
> 

Acked-by: Andrew Lunn <andrew@lunn.ch>

[PATCH v7] arm: Add basic support for new Marvell Armada 370 and Armada XP SoC

[Ben Dooks]

On 02/07/12 16:39, Thomas Petazzoni wrote:
> Arnd, Olof,
>
> You'll find in this patch set the seventh version of the initial
> support for a new family of ARMv7-compatible Marvell SoCs.
>
> As for the previous releases, both the Armada 370 and the Armada XP
> SoCs are supported in this directory, and we are able to build a
> single kernel image that boots on both SoCs. Both SoCs use the PJ4B
> processor, a Marvell-developed ARM core that implements the ARMv7
> instruction set. We are currently using Marvell evaluation boards for
> both of those SoCs, and the support for those boards is added in this
> patch set.
>
> We remained focused on a limited preliminary support which only
> includes the necessary code for timer and IRQ support, the serial
> controller is a standard 16550-compatible one. The diffstat looks
> like:

I've built and it got to looking for a root-fs.

Tested-by: Ben Dooks <ben.dooks@codethink.co.uk>

I will have another run through the series tomorrow and do a last
pass review.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

[PATCH v7] arm: Add basic support for new Marvell Armada 370 and Armada XP SoC

[Yehuda Yitschak]

> -----Original Message-----
> From: Thomas Petazzoni [mailto:thomas.petazzoni at free-electrons.com]
> Sent: Monday, July 02, 2012 6:39 PM
> To: Arnd Bergmann; Olof Johansson
> Cc: Ben Dooks; Jason Cooper; Andrew Lunn; Nicolas Pitre; Lior Amsalem;
> Maen Suleiman; linux-arm-kernel at lists.infradead.org; Thomas Petazzoni;
> Gregory Clement; Jon Masters; David Marlin; Tawfik Bayouk; Shadi
> Ammouri; Eran Ben-Avi; Yehuda Yitschak; Nadav Haklai; Eric Miao
> Subject: [PATCH v7] arm: Add basic support for new Marvell Armada 370 and
> Armada XP SoC
> 
> Arnd, Olof,
> 
> You'll find in this patch set the seventh version of the initial support for a
> new family of ARMv7-compatible Marvell SoCs.
> 
> As for the previous releases, both the Armada 370 and the Armada XP SoCs
> are supported in this directory, and we are able to build a single kernel
> image that boots on both SoCs. Both SoCs use the PJ4B processor, a Marvell-
> developed ARM core that implements the ARMv7 instruction set. We are
> currently using Marvell evaluation boards for both of those SoCs, and the
> support for those boards is added in this patch set.
> 
Hi, tested by me on Armada XP board. So,
Tested-By: Yehuda Yitschak <yehuday@marvell.com>


[snip]
> 
> Best regards,
> 
> Thomas Petazzoni

Regards,
Yehuda Yitschak

[PATCH v7] arm: Add basic support for new Marvell Armada 370 and Armada XP SoC

[Lior Amsalem]

> -----Original Message-----
> From: Yehuda Yitschak
> Sent: Wednesday, July 04, 2012 3:11 PM
> To: Thomas Petazzoni; Arnd Bergmann; Olof Johansson
> Cc: Ben Dooks; Jason Cooper; Andrew Lunn; Nicolas Pitre; Lior Amsalem;
> Maen Suleiman; linux-arm-kernel at lists.infradead.org; Gregory Clement; Jon
> Masters; David Marlin; Tawfik Bayouk; Shadi Ammouri; Eran Ben-Avi; Nadav
> Haklai; Eric Miao
> Subject: RE: [PATCH v7] arm: Add basic support for new Marvell Armada 370
> and Armada XP SoC
> 
> 
> 
> > -----Original Message-----
> > From: Thomas Petazzoni [mailto:thomas.petazzoni at free-electrons.com]
> > Sent: Monday, July 02, 2012 6:39 PM
> > To: Arnd Bergmann; Olof Johansson
> > Cc: Ben Dooks; Jason Cooper; Andrew Lunn; Nicolas Pitre; Lior Amsalem;
> > Maen Suleiman; linux-arm-kernel at lists.infradead.org; Thomas Petazzoni;
> > Gregory Clement; Jon Masters; David Marlin; Tawfik Bayouk; Shadi
> > Ammouri; Eran Ben-Avi; Yehuda Yitschak; Nadav Haklai; Eric Miao
> > Subject: [PATCH v7] arm: Add basic support for new Marvell Armada 370
> and
> > Armada XP SoC
> >
> > Arnd, Olof,
> >
> > You'll find in this patch set the seventh version of the initial support for a
> > new family of ARMv7-compatible Marvell SoCs.
> >
> > As for the previous releases, both the Armada 370 and the Armada XP SoCs
> > are supported in this directory, and we are able to build a single kernel
> > image that boots on both SoCs. Both SoCs use the PJ4B processor, a
> Marvell-
> > developed ARM core that implements the ARMv7 instruction set. We are
> > currently using Marvell evaluation boards for both of those SoCs, and the
> > support for those boards is added in this patch set.
> >
> Hi, tested by me on Armada XP board. So,
> Tested-By: Yehuda Yitschak <yehuday@marvell.com>
> 


Hi Thomas, Thanks!
Tested by me on both Armada XP and 370 DB boards.

Tested-By: Lior Amsalem <alior@marvell.com>

> 
> [snip]
> >
> > Best regards,
> >
> > Thomas Petazzoni
> 
> Regards,
> Yehuda Yitschak

Regards,
Lior Amsalem

[PATCH 5/9] arm: mach-mvebu: add documentation for new device tree bindings

[Thomas Petazzoni]

From: Gregory CLEMENT <gregory.clement@free-electrons.com>

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
---
 .../devicetree/bindings/arm/armada-370-xp-mpic.txt |   23 +++++++++++++++++++
 .../bindings/arm/armada-370-xp-timer.txt           |   11 +++++++++
 .../devicetree/bindings/arm/armada-370-xp.txt      |   24 ++++++++++++++++++++
 .../bindings/arm/mvebu-system-controller.txt       |   17 ++++++++++++++
 4 files changed, 75 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
 create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
 create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp.txt
 create mode 100644 Documentation/devicetree/bindings/arm/mvebu-system-controller.txt

diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
new file mode 100644
index 0000000..70c0dc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
@@ -0,0 +1,23 @@
+Marvell Armada 370 and Armada XP Interrupt Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible: Should be "marvell,mpic"
+- interrupt-controller: Identifies the node as an interrupt controller.
+- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
+  The cell is the IRQ number
+- reg: Should contain PMIC registers location and length. First pair
+  for the main interrupt registers, second pair for the per-CPU
+  interrupt registers
+
+Example:
+
+        mpic: interrupt-controller at d0020000 {
+              compatible = "marvell,mpic";
+              #interrupt-cells = <1>;
+              #address-cells = <1>;
+              #size-cells = <1>;
+              interrupt-controller;
+              reg = <0xd0020000 0x1000>,
+                    <0xd0021000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
new file mode 100644
index 0000000..d14dc7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
@@ -0,0 +1,11 @@
+Marvell Armada 370 and Armada XP Global Timers
+----------------------------------------------
+
+Required properties:
+- compatible: Should be "marvell,timer"
+- interrupts: Should contain the list of Global Timer interrupts
+- reg: Should contain the base address of the Global Timer registers
+
+Optional properties:
+- marvell,timer-25Mhz: Tells whether the Global timer supports the 25
+  Mhz fixed mode (available on Armada XP and not on Armada 370)
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp.txt b/Documentation/devicetree/bindings/arm/armada-370-xp.txt
new file mode 100644
index 0000000..c6ed90e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp.txt
@@ -0,0 +1,24 @@
+Marvell Armada 370 and Armada XP Platforms Device Tree Bindings
+---------------------------------------------------------------
+
+Boards with a SoC of the Marvell Armada 370 and Armada XP families
+shall have the following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armada-370-xp"
+
+In addition, boards using the Marvell Armada 370 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armada370"
+
+In addition, boards using the Marvell Armada XP SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp"
+
diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
new file mode 100644
index 0000000..081c6a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
@@ -0,0 +1,17 @@
+MVEBU System Controller
+-----------------------
+MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
+
+Required properties:
+
+- compatible: one of:
+	- "marvell,orion-system-controller"
+	- "marvell,armada-370-xp-system-controller"
+- reg: Should contain system controller registers location and length.
+
+Example:
+
+	system-controller at d0018200 {
+		compatible = "marvell,armada-370-xp-system-controller";
+		reg = <0xd0018200 0x500>;
+	};
-- 
1.7.9.5