[U-Boot] [RESEND 01/11] snowball: Add support for ux500 based snowball board

[mathieu.poirier at linaro.org <mathieu.poirier@linaro.org>]

From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org>

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
---
Changes for v2:
   - White space cleanup.
   - Cleaned #defines.
   - Removal of unnecessary defines.
---
 arch/arm/include/asm/arch-u8500/db8500_gpio.h   |   42 ++
 arch/arm/include/asm/arch-u8500/db8500_pincfg.h |  172 ++++++
 board/st-ericsson/snowball/Makefile             |   51 ++
 board/st-ericsson/snowball/db8500_pins.h        |  745 +++++++++++++++++++++++
 board/st-ericsson/snowball/snowball.c           |  185 ++++++
 boards.cfg                                      |    1 +
 drivers/gpio/Makefile                           |    1 +
 drivers/gpio/db8500_gpio.c                      |  225 +++++++
 drivers/serial/serial_pl01x.c                   |    2 +
 include/configs/snowball.h                      |  258 ++++++++
 10 files changed, 1682 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-u8500/db8500_gpio.h b/arch/arm/include/asm/arch-u8500/db8500_gpio.h
new file mode 100644
index 0000000..7c85a89
--- /dev/null
+++ b/arch/arm/include/asm/arch-u8500/db8500_gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Structures and registers for GPIO access in the Nomadik SoC
+ *
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot.
+ *
+ * Ported to U-boot by:
+ * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ * Copyright (C) 2008 STMicroelectronics
+ *     Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
+ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DB8500_GPIO_H__
+#define __DB8500_GPIO_H__
+
+/* Alternate functions: function C is set in hw by setting both A and B */
+enum db8500_gpio_alt {
+	DB8500_GPIO_ALT_GPIO = 0,
+	DB8500_GPIO_ALT_A = 1,
+	DB8500_GPIO_ALT_B = 2,
+	DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B)
+};
+
+enum db8500_gpio_pull {
+	DB8500_GPIO_PULL_NONE,
+	DB8500_GPIO_PULL_UP,
+	DB8500_GPIO_PULL_DOWN
+};
+
+void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull);
+void db8500_gpio_make_input(unsigned gpio);
+int db8500_gpio_get_input(unsigned gpio);
+void db8500_gpio_make_output(unsigned gpio, int val);
+void db8500_gpio_set_output(unsigned gpio, int val);
+
+#endif /* __DB8500_GPIO_H__ */
diff --git a/arch/arm/include/asm/arch-u8500/db8500_pincfg.h b/arch/arm/include/asm/arch-u8500/db8500_pincfg.h
new file mode 100644
index 0000000..137377d
--- /dev/null
+++ b/arch/arm/include/asm/arch-u8500/db8500_pincfg.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot. Ported 2010 to U-boot by:
+ * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ *
+ *
+ * Based on arch/arm/mach-pxa/include/mach/mfp.h:
+ *   Copyright (C) 2007 Marvell International Ltd.
+ *   eric miao <eric.miao@marvell.com>
+ */
+
+#ifndef __DB8500_PINCFG_H
+#define __DB8500_PINCFG_H
+
+#include "db8500_gpio.h"
+
+/*
+ * U-boot info:
+ * SLPM (sleep mode) config will be ignored by U-boot but it is still
+ * possible to configure it in order to keep cut-n-paste compability
+ * with Linux kernel config.
+ *
+ * pin configurations are represented by 32-bit integers:
+ *
+ *	bit  0.. 8 - Pin Number (512 Pins Maximum)
+ *	bit  9..10 - Alternate Function Selection
+ *	bit 11..12 - Pull up/down state
+ *	bit     13 - Sleep mode behaviour (not used in U-boot)
+ *	bit     14 - Direction
+ *	bit     15 - Value (if output)
+ *	bit 16..18 - SLPM pull up/down state (not used in U-boot)
+ *	bit 19..20 - SLPM direction (not used in U-boot)
+ *	bit 21..22 - SLPM Value (if output) (not used in U-boot)
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * PIN_CFG_DEFAULT - default config (0):
+ *		     pull up/down = disabled
+ *		     sleep mode = input/wakeup
+ *		     direction = input
+ *		     value = low
+ *		     SLPM direction = same as normal
+ *		     SLPM pull = same as normal
+ *		     SLPM value = same as normal
+ *
+ * PIN_CFG	   - default config with alternate function
+ * PIN_CFG_PULL	   - default config with alternate function and pull up/down
+ */
+
+typedef unsigned long pin_cfg_t;
+
+/* Sleep mode */
+enum db8500_gpio_slpm {
+	DB8500_GPIO_SLPM_INPUT,
+	DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT,
+	DB8500_GPIO_SLPM_NOCHANGE,
+	DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE,
+};
+
+#define PIN_NUM_MASK		0x1ff
+#define PIN_NUM(x)		((x) & PIN_NUM_MASK)
+
+#define PIN_ALT_SHIFT		9
+#define PIN_ALT_MASK		(0x3 << PIN_ALT_SHIFT)
+#define PIN_ALT(x)		(((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
+#define PIN_GPIO		(DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
+#define PIN_ALT_A		(DB8500_GPIO_ALT_A << PIN_ALT_SHIFT)
+#define PIN_ALT_B		(DB8500_GPIO_ALT_B << PIN_ALT_SHIFT)
+#define PIN_ALT_C		(DB8500_GPIO_ALT_C << PIN_ALT_SHIFT)
+
+#define PIN_PULL_SHIFT		11
+#define PIN_PULL_MASK		(0x3 << PIN_PULL_SHIFT)
+#define PIN_PULL(x)		(((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
+#define PIN_PULL_NONE		(DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT)
+#define PIN_PULL_UP		(DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT)
+#define PIN_PULL_DOWN		(DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
+
+#define PIN_SLPM_SHIFT		13
+#define PIN_SLPM_MASK		(0x1 << PIN_SLPM_SHIFT)
+#define PIN_SLPM(x)		(((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
+#define PIN_SLPM_MAKE_INPUT	(DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
+#define PIN_SLPM_NOCHANGE	(DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
+/* These two replace the above in DB8500v2+ */
+#define PIN_SLPM_WAKEUP_ENABLE \
+	(DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
+#define PIN_SLPM_WAKEUP_DISABLE \
+	(DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
+
+#define PIN_DIR_SHIFT		14
+#define PIN_DIR_MASK		(0x1 << PIN_DIR_SHIFT)
+#define PIN_DIR(x)		(((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
+#define PIN_DIR_INPUT		(0 << PIN_DIR_SHIFT)
+#define PIN_DIR_OUTPUT		(1 << PIN_DIR_SHIFT)
+
+#define PIN_VAL_SHIFT		15
+#define PIN_VAL_MASK		(0x1 << PIN_VAL_SHIFT)
+#define PIN_VAL(x)		(((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
+#define PIN_VAL_LOW		(0 << PIN_VAL_SHIFT)
+#define PIN_VAL_HIGH		(1 << PIN_VAL_SHIFT)
+
+#define PIN_SLPM_PULL_SHIFT	16
+#define PIN_SLPM_PULL_MASK	(0x7 << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL(x)	\
+	(((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_NONE	\
+	((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_UP	\
+	((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_DOWN	\
+	((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
+
+#define PIN_SLPM_DIR_SHIFT	19
+#define PIN_SLPM_DIR_MASK	(0x3 << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR(x)		\
+	(((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_INPUT	((1 + 0) << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_OUTPUT	((1 + 1) << PIN_SLPM_DIR_SHIFT)
+
+#define PIN_SLPM_VAL_SHIFT	21
+#define PIN_SLPM_VAL_MASK	(0x3 << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL(x)		\
+	(((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_LOW	((1 + 0) << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_HIGH	((1 + 1) << PIN_SLPM_VAL_SHIFT)
+
+/* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
+#define PIN_INPUT_PULLDOWN	(PIN_DIR_INPUT | PIN_PULL_DOWN)
+#define PIN_INPUT_PULLUP	(PIN_DIR_INPUT | PIN_PULL_UP)
+#define PIN_INPUT_NOPULL	(PIN_DIR_INPUT | PIN_PULL_NONE)
+#define PIN_OUTPUT_LOW		(PIN_DIR_OUTPUT | PIN_VAL_LOW)
+#define PIN_OUTPUT_HIGH		(PIN_DIR_OUTPUT | PIN_VAL_HIGH)
+
+#define PIN_SLPM_INPUT_PULLDOWN	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
+#define PIN_SLPM_INPUT_PULLUP	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
+#define PIN_SLPM_INPUT_NOPULL	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
+#define PIN_SLPM_OUTPUT_LOW	(PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
+#define PIN_SLPM_OUTPUT_HIGH	(PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
+
+#define PIN_CFG_DEFAULT		(0)
+
+#define PIN_CFG(num, alt)		\
+	(PIN_CFG_DEFAULT |\
+	 (PIN_NUM(num) | PIN_##alt))
+
+#define PIN_CFG_INPUT(num, alt, pull)		\
+	(PIN_CFG_DEFAULT |\
+	 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
+
+#define PIN_CFG_OUTPUT(num, alt, val)		\
+	(PIN_CFG_DEFAULT |\
+	 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
+
+#define PIN_CFG_PULL(num, alt, pull)	\
+	((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
+	 (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
+
+/**
+ * db8500_gpio_config_pins - configure several pins@once
+ * @cfgs: array of pin configurations
+ * @num: number of elments in the array
+ *
+ * Configures several GPIO pins.
+ */
+void db8500_gpio_config_pins(pin_cfg_t *cfgs, size_t num);
+
+#endif
diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile
new file mode 100644
index 0000000..6138296
--- /dev/null
+++ b/board/st-ericsson/snowball/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright (C) ST-Ericsson SA 2009
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+CFLAGS += -D__RELEASE -D__STN_8500
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= snowball.o
+
+#prcmu.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/st-ericsson/snowball/db8500_pins.h b/board/st-ericsson/snowball/db8500_pins.h
new file mode 100644
index 0000000..e339cb8
--- /dev/null
+++ b/board/st-ericsson/snowball/db8500_pins.h
@@ -0,0 +1,745 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot.
+ *
+ * Ported to U-boot by:
+ * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ **
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ */
+
+#ifndef __DB8500_PINS_H
+#define __DB8500_PINS_H
+
+#include <asm/arch/db8500_pincfg.h>
+
+#define GPIO0_GPIO		PIN_CFG(0, GPIO)
+#define GPIO0_U0_CTSn		PIN_CFG(0, ALT_A)
+#define GPIO0_TRIG_OUT		PIN_CFG(0, ALT_B)
+#define GPIO0_IP_TDO		PIN_CFG(0, ALT_C)
+
+#define GPIO1_GPIO		PIN_CFG(1, GPIO)
+#define GPIO1_U0_RTSn		PIN_CFG(1, ALT_A)
+#define GPIO1_TRIG_IN		PIN_CFG(1, ALT_B)
+#define GPIO1_IP_TDI		PIN_CFG(1, ALT_C)
+
+#define GPIO2_GPIO		PIN_CFG(2, GPIO)
+#define GPIO2_U0_RXD		PIN_CFG(2, ALT_A)
+#define GPIO2_NONE		PIN_CFG(2, ALT_B)
+#define GPIO2_IP_TMS		PIN_CFG(2, ALT_C)
+
+#define GPIO3_GPIO		PIN_CFG(3, GPIO)
+#define GPIO3_U0_TXD		PIN_CFG(3, ALT_A)
+#define GPIO3_NONE		PIN_CFG(3, ALT_B)
+#define GPIO3_IP_TCK		PIN_CFG(3, ALT_C)
+
+#define GPIO4_GPIO		PIN_CFG(4, GPIO)
+#define GPIO4_U1_RXD		PIN_CFG(4, ALT_A)
+#define GPIO4_I2C4_SCL		PIN_CFG_PULL(4, ALT_B, UP)
+#define GPIO4_IP_TRSTn		PIN_CFG(4, ALT_C)
+
+#define GPIO5_GPIO		PIN_CFG(5, GPIO)
+#define GPIO5_U1_TXD		PIN_CFG(5, ALT_A)
+#define GPIO5_I2C4_SDA		PIN_CFG_PULL(5, ALT_B, UP)
+#define GPIO5_IP_GPIO6		PIN_CFG(5, ALT_C)
+
+#define GPIO6_GPIO		PIN_CFG(6, GPIO)
+#define GPIO6_U1_CTSn		PIN_CFG(6, ALT_A)
+#define GPIO6_I2C1_SCL		PIN_CFG_PULL(6, ALT_B, UP)
+#define GPIO6_IP_GPIO0		PIN_CFG(6, ALT_C)
+
+#define GPIO7_GPIO		PIN_CFG(7, GPIO)
+#define GPIO7_U1_RTSn		PIN_CFG(7, ALT_A)
+#define GPIO7_I2C1_SDA		PIN_CFG_PULL(7, ALT_B, UP)
+#define GPIO7_IP_GPIO1		PIN_CFG(7, ALT_C)
+
+#define GPIO8_GPIO		PIN_CFG(8, GPIO)
+#define GPIO8_IPI2C_SDA		PIN_CFG_PULL(8, ALT_A, UP)
+#define GPIO8_I2C2_SDA		PIN_CFG_PULL(8, ALT_B, UP)
+
+#define GPIO9_GPIO		PIN_CFG(9, GPIO)
+#define GPIO9_IPI2C_SCL		PIN_CFG_PULL(9, ALT_A, UP)
+#define GPIO9_I2C2_SCL		PIN_CFG_PULL(9, ALT_B, UP)
+
+#define GPIO10_GPIO		PIN_CFG(10, GPIO)
+#define GPIO10_IPI2C_SDA	PIN_CFG_PULL(10, ALT_A, UP)
+#define GPIO10_I2C2_SDA		PIN_CFG_PULL(10, ALT_B, UP)
+#define GPIO10_IP_GPIO3		PIN_CFG(10, ALT_C)
+
+#define GPIO11_GPIO		PIN_CFG(11, GPIO)
+#define GPIO11_IPI2C_SCL	PIN_CFG_PULL(11, ALT_A, UP)
+#define GPIO11_I2C2_SCL		PIN_CFG_PULL(11, ALT_B, UP)
+#define GPIO11_IP_GPIO2		PIN_CFG(11, ALT_C)
+
+#define GPIO12_GPIO		PIN_CFG(12, GPIO)
+#define GPIO12_MSP0_TXD		PIN_CFG(12, ALT_A)
+#define GPIO12_MSP0_RXD		PIN_CFG(12, ALT_B)
+
+#define GPIO13_GPIO		PIN_CFG(13, GPIO)
+#define GPIO13_MSP0_TFS		PIN_CFG(13, ALT_A)
+
+#define GPIO14_GPIO		PIN_CFG(14, GPIO)
+#define GPIO14_MSP0_TCK		PIN_CFG(14, ALT_A)
+
+#define GPIO15_GPIO		PIN_CFG(15, GPIO)
+#define GPIO15_MSP0_RXD		PIN_CFG(15, ALT_A)
+#define GPIO15_MSP0_TXD		PIN_CFG(15, ALT_B)
+
+#define GPIO16_GPIO		PIN_CFG(16, GPIO)
+#define GPIO16_MSP0_RFS		PIN_CFG(16, ALT_A)
+#define GPIO16_I2C1_SCL		PIN_CFG_PULL(16, ALT_B, UP)
+#define GPIO16_SLIM0_DAT	PIN_CFG(16, ALT_C)
+
+#define GPIO17_GPIO		PIN_CFG(17, GPIO)
+#define GPIO17_MSP0_RCK		PIN_CFG(17, ALT_A)
+#define GPIO17_I2C1_SDA		PIN_CFG_PULL(17, ALT_B, UP)
+#define GPIO17_SLIM0_CLK	PIN_CFG(17, ALT_C)
+
+#define GPIO18_GPIO		PIN_CFG(18, GPIO)
+#define GPIO18_MC0_CMDDIR	PIN_CFG(18, ALT_A)
+#define GPIO18_U2_RXD		PIN_CFG(18, ALT_B)
+#define GPIO18_MS_IEP		PIN_CFG(18, ALT_C)
+
+#define GPIO19_GPIO		PIN_CFG(19, GPIO)
+#define GPIO19_MC0_DAT0DIR	PIN_CFG(19, ALT_A)
+#define GPIO19_U2_TXD		PIN_CFG(19, ALT_B)
+#define GPIO19_MS_DAT0DIR	PIN_CFG(19, ALT_C)
+
+#define GPIO20_GPIO		PIN_CFG(20, GPIO)
+#define GPIO20_MC0_DAT2DIR	PIN_CFG(20, ALT_A)
+#define GPIO20_UARTMOD_TXD	PIN_CFG(20, ALT_B)
+#define GPIO20_IP_TRIGOUT	PIN_CFG(20, ALT_C)
+
+#define GPIO21_GPIO		PIN_CFG(21, GPIO)
+#define GPIO21_MC0_DAT31DIR	PIN_CFG(21, ALT_A)
+#define GPIO21_MSP0_SCK		PIN_CFG(21, ALT_B)
+#define GPIO21_MS_DAT31DIR	PIN_CFG(21, ALT_C)
+
+#define GPIO22_GPIO		PIN_CFG(22, GPIO)
+#define GPIO22_MC0_FBCLK	PIN_CFG(22, ALT_A)
+#define GPIO22_UARTMOD_RXD	PIN_CFG(22, ALT_B)
+#define GPIO22_MS_FBCLK		PIN_CFG(22, ALT_C)
+
+#define GPIO23_GPIO		PIN_CFG(23, GPIO)
+#define GPIO23_MC0_CLK		PIN_CFG(23, ALT_A)
+#define GPIO23_STMMOD_CLK	PIN_CFG(23, ALT_B)
+#define GPIO23_MS_CLK		PIN_CFG(23, ALT_C)
+
+#define GPIO24_GPIO		PIN_CFG(24, GPIO)
+#define GPIO24_MC0_CMD		PIN_CFG(24, ALT_A)
+#define GPIO24_UARTMOD_RXD	PIN_CFG(24, ALT_B)
+#define GPIO24_MS_BS		PIN_CFG(24, ALT_C)
+
+#define GPIO25_GPIO		PIN_CFG(25, GPIO)
+#define GPIO25_MC0_DAT0		PIN_CFG(25, ALT_A)
+#define GPIO25_STMMOD_DAT0	PIN_CFG(25, ALT_B)
+#define GPIO25_MS_DAT0		PIN_CFG(25, ALT_C)
+
+#define GPIO26_GPIO		PIN_CFG(26, GPIO)
+#define GPIO26_MC0_DAT1		PIN_CFG(26, ALT_A)
+#define GPIO26_STMMOD_DAT1	PIN_CFG(26, ALT_B)
+#define GPIO26_MS_DAT1		PIN_CFG(26, ALT_C)
+
+#define GPIO27_GPIO		PIN_CFG(27, GPIO)
+#define GPIO27_MC0_DAT2		PIN_CFG(27, ALT_A)
+#define GPIO27_STMMOD_DAT2	PIN_CFG(27, ALT_B)
+#define GPIO27_MS_DAT2		PIN_CFG(27, ALT_C)
+
+#define GPIO28_GPIO		PIN_CFG(28, GPIO)
+#define GPIO28_MC0_DAT3		PIN_CFG(28, ALT_A)
+#define GPIO28_STMMOD_DAT3	PIN_CFG(28, ALT_B)
+#define GPIO28_MS_DAT3		PIN_CFG(28, ALT_C)
+
+#define GPIO29_GPIO		PIN_CFG(29, GPIO)
+#define GPIO29_MC0_DAT4		PIN_CFG(29, ALT_A)
+#define GPIO29_SPI3_CLK		PIN_CFG(29, ALT_B)
+#define GPIO29_U2_RXD		PIN_CFG(29, ALT_C)
+
+#define GPIO30_GPIO		PIN_CFG(30, GPIO)
+#define GPIO30_MC0_DAT5		PIN_CFG(30, ALT_A)
+#define GPIO30_SPI3_RXD		PIN_CFG(30, ALT_B)
+#define GPIO30_U2_TXD		PIN_CFG(30, ALT_C)
+
+#define GPIO31_GPIO		PIN_CFG(31, GPIO)
+#define GPIO31_MC0_DAT6		PIN_CFG(31, ALT_A)
+#define GPIO31_SPI3_FRM		PIN_CFG(31, ALT_B)
+#define GPIO31_U2_CTSn		PIN_CFG(31, ALT_C)
+
+#define GPIO32_GPIO		PIN_CFG(32, GPIO)
+#define GPIO32_MC0_DAT7		PIN_CFG(32, ALT_A)
+#define GPIO32_SPI3_TXD		PIN_CFG(32, ALT_B)
+#define GPIO32_U2_RTSn		PIN_CFG(32, ALT_C)
+
+#define GPIO33_GPIO		PIN_CFG(33, GPIO)
+#define GPIO33_MSP1_TXD		PIN_CFG(33, ALT_A)
+#define GPIO33_MSP1_RXD		PIN_CFG(33, ALT_B)
+#define GPIO33_U0_DTRn		PIN_CFG(33, ALT_C)
+
+#define GPIO34_GPIO		PIN_CFG(34, GPIO)
+#define GPIO34_MSP1_TFS		PIN_CFG(34, ALT_A)
+#define GPIO34_NONE		PIN_CFG(34, ALT_B)
+#define GPIO34_U0_DCDn		PIN_CFG(34, ALT_C)
+
+#define GPIO35_GPIO		PIN_CFG(35, GPIO)
+#define GPIO35_MSP1_TCK		PIN_CFG(35, ALT_A)
+#define GPIO35_NONE		PIN_CFG(35, ALT_B)
+#define GPIO35_U0_DSRn		PIN_CFG(35, ALT_C)
+
+#define GPIO36_GPIO		PIN_CFG(36, GPIO)
+#define GPIO36_MSP1_RXD		PIN_CFG(36, ALT_A)
+#define GPIO36_MSP1_TXD		PIN_CFG(36, ALT_B)
+#define GPIO36_U0_RIn		PIN_CFG(36, ALT_C)
+
+#define GPIO64_GPIO		PIN_CFG(64, GPIO)
+#define GPIO64_LCDB_DE		PIN_CFG(64, ALT_A)
+#define GPIO64_KP_O1		PIN_CFG(64, ALT_B)
+#define GPIO64_IP_GPIO4		PIN_CFG(64, ALT_C)
+
+#define GPIO65_GPIO		PIN_CFG(65, GPIO)
+#define GPIO65_LCDB_HSO		PIN_CFG(65, ALT_A)
+#define GPIO65_KP_O0		PIN_CFG(65, ALT_B)
+#define GPIO65_IP_GPIO5		PIN_CFG(65, ALT_C)
+
+#define GPIO66_GPIO		PIN_CFG(66, GPIO)
+#define GPIO66_LCDB_VSO		PIN_CFG(66, ALT_A)
+#define GPIO66_KP_I1		PIN_CFG(66, ALT_B)
+#define GPIO66_IP_GPIO6		PIN_CFG(66, ALT_C)
+
+#define GPIO67_GPIO		PIN_CFG(67, GPIO)
+#define GPIO67_LCDB_CLK		PIN_CFG(67, ALT_A)
+#define GPIO67_KP_I0		PIN_CFG(67, ALT_B)
+#define GPIO67_IP_GPIO7		PIN_CFG(67, ALT_C)
+
+#define GPIO68_GPIO		PIN_CFG(68, GPIO)
+#define GPIO68_LCD_VSI0		PIN_CFG(68, ALT_A)
+#define GPIO68_KP_O7		PIN_CFG(68, ALT_B)
+#define GPIO68_SM_CLE		PIN_CFG(68, ALT_C)
+
+#define GPIO69_GPIO		PIN_CFG(69, GPIO)
+#define GPIO69_LCD_VSI1		PIN_CFG(69, ALT_A)
+#define GPIO69_KP_I7		PIN_CFG(69, ALT_B)
+#define GPIO69_SM_ALE		PIN_CFG(69, ALT_C)
+
+#define GPIO70_GPIO		PIN_CFG(70, GPIO)
+#define GPIO70_LCD_D0		PIN_CFG(70, ALT_A)
+#define GPIO70_KP_O5		PIN_CFG(70, ALT_B)
+#define GPIO70_STMAPE_CLK	PIN_CFG(70, ALT_C)
+
+#define GPIO71_GPIO		PIN_CFG(71, GPIO)
+#define GPIO71_LCD_D1		PIN_CFG(71, ALT_A)
+#define GPIO71_KP_O4		PIN_CFG(71, ALT_B)
+#define GPIO71_STMAPE_DAT3	PIN_CFG(71, ALT_C)
+
+#define GPIO72_GPIO		PIN_CFG(72, GPIO)
+#define GPIO72_LCD_D2		PIN_CFG(72, ALT_A)
+#define GPIO72_KP_O3		PIN_CFG(72, ALT_B)
+#define GPIO72_STMAPE_DAT2	PIN_CFG(72, ALT_C)
+
+#define GPIO73_GPIO		PIN_CFG(73, GPIO)
+#define GPIO73_LCD_D3		PIN_CFG(73, ALT_A)
+#define GPIO73_KP_O2		PIN_CFG(73, ALT_B)
+#define GPIO73_STMAPE_DAT1	PIN_CFG(73, ALT_C)
+
+#define GPIO74_GPIO		PIN_CFG(74, GPIO)
+#define GPIO74_LCD_D4		PIN_CFG(74, ALT_A)
+#define GPIO74_KP_I5		PIN_CFG(74, ALT_B)
+#define GPIO74_STMAPE_DAT0	PIN_CFG(74, ALT_C)
+
+#define GPIO75_GPIO		PIN_CFG(75, GPIO)
+#define GPIO75_LCD_D5		PIN_CFG(75, ALT_A)
+#define GPIO75_KP_I4		PIN_CFG(75, ALT_B)
+#define GPIO75_U2_RXD		PIN_CFG(75, ALT_C)
+
+#define GPIO76_GPIO		PIN_CFG(76, GPIO)
+#define GPIO76_LCD_D6		PIN_CFG(76, ALT_A)
+#define GPIO76_KP_I3		PIN_CFG(76, ALT_B)
+#define GPIO76_U2_TXD		PIN_CFG(76, ALT_C)
+
+#define GPIO77_GPIO		PIN_CFG(77, GPIO)
+#define GPIO77_LCD_D7		PIN_CFG(77, ALT_A)
+#define GPIO77_KP_I2		PIN_CFG(77, ALT_B)
+#define GPIO77_NONE		PIN_CFG(77, ALT_C)
+
+#define GPIO78_GPIO		PIN_CFG(78, GPIO)
+#define GPIO78_LCD_D8		PIN_CFG(78, ALT_A)
+#define GPIO78_KP_O6		PIN_CFG(78, ALT_B)
+#define GPIO78_IP_GPIO2		PIN_CFG(78, ALT_C)
+
+#define GPIO79_GPIO		PIN_CFG(79, GPIO)
+#define GPIO79_LCD_D9		PIN_CFG(79, ALT_A)
+#define GPIO79_KP_I6		PIN_CFG(79, ALT_B)
+#define GPIO79_IP_GPIO3		PIN_CFG(79, ALT_C)
+
+#define GPIO80_GPIO		PIN_CFG(80, GPIO)
+#define GPIO80_LCD_D10		PIN_CFG(80, ALT_A)
+#define GPIO80_KP_SKA0		PIN_CFG(80, ALT_B)
+#define GPIO80_IP_GPIO4		PIN_CFG(80, ALT_C)
+
+#define GPIO81_GPIO		PIN_CFG(81, GPIO)
+#define GPIO81_LCD_D11		PIN_CFG(81, ALT_A)
+#define GPIO81_KP_SKB0		PIN_CFG(81, ALT_B)
+#define GPIO81_IP_GPIO5		PIN_CFG(81, ALT_C)
+
+#define GPIO82_GPIO		PIN_CFG(82, GPIO)
+#define GPIO82_LCD_D12		PIN_CFG(82, ALT_A)
+#define GPIO82_KP_O5		PIN_CFG(82, ALT_B)
+
+#define GPIO83_GPIO		PIN_CFG(83, GPIO)
+#define GPIO83_LCD_D13		PIN_CFG(83, ALT_A)
+#define GPIO83_KP_O4		PIN_CFG(83, ALT_B)
+
+#define GPIO84_GPIO		PIN_CFG_PULL(84, GPIO, UP)
+#define GPIO84_LCD_D14		PIN_CFG(84, ALT_A)
+#define GPIO84_KP_I5		PIN_CFG(84, ALT_B)
+
+#define GPIO85_GPIO		PIN_CFG(85, GPIO)
+#define GPIO85_LCD_D15		PIN_CFG(85, ALT_A)
+#define GPIO85_KP_I4		PIN_CFG(85, ALT_B)
+
+#define GPIO86_GPIO		PIN_CFG(86, GPIO)
+#define GPIO86_LCD_D16		PIN_CFG(86, ALT_A)
+#define GPIO86_SM_ADQ0		PIN_CFG(86, ALT_B)
+#define GPIO86_MC5_DAT0		PIN_CFG(86, ALT_C)
+
+#define GPIO87_GPIO		PIN_CFG(87, GPIO)
+#define GPIO87_LCD_D17		PIN_CFG(87, ALT_A)
+#define GPIO87_SM_ADQ1		PIN_CFG(87, ALT_B)
+#define GPIO87_MC5_DAT1		PIN_CFG(87, ALT_C)
+
+#define GPIO88_GPIO		PIN_CFG(88, GPIO)
+#define GPIO88_LCD_D18		PIN_CFG(88, ALT_A)
+#define GPIO88_SM_ADQ2		PIN_CFG(88, ALT_B)
+#define GPIO88_MC5_DAT2		PIN_CFG(88, ALT_C)
+
+#define GPIO89_GPIO		PIN_CFG(89, GPIO)
+#define GPIO89_LCD_D19		PIN_CFG(89, ALT_A)
+#define GPIO89_SM_ADQ3		PIN_CFG(89, ALT_B)
+#define GPIO89_MC5_DAT3		PIN_CFG(89, ALT_C)
+
+#define GPIO90_GPIO		PIN_CFG(90, GPIO)
+#define GPIO90_LCD_D20		PIN_CFG(90, ALT_A)
+#define GPIO90_SM_ADQ4		PIN_CFG(90, ALT_B)
+#define GPIO90_MC5_CMD		PIN_CFG(90, ALT_C)
+
+#define GPIO91_GPIO		PIN_CFG(91, GPIO)
+#define GPIO91_LCD_D21		PIN_CFG(91, ALT_A)
+#define GPIO91_SM_ADQ5		PIN_CFG(91, ALT_B)
+#define GPIO91_MC5_FBCLK	PIN_CFG(91, ALT_C)
+
+#define GPIO92_GPIO		PIN_CFG(92, GPIO)
+#define GPIO92_LCD_D22		PIN_CFG(92, ALT_A)
+#define GPIO92_SM_ADQ6		PIN_CFG(92, ALT_B)
+#define GPIO92_MC5_CLK		PIN_CFG(92, ALT_C)
+
+#define GPIO93_GPIO		PIN_CFG(93, GPIO)
+#define GPIO93_LCD_D23		PIN_CFG(93, ALT_A)
+#define GPIO93_SM_ADQ7		PIN_CFG(93, ALT_B)
+#define GPIO93_MC5_DAT4		PIN_CFG(93, ALT_C)
+
+#define GPIO94_GPIO		PIN_CFG(94, GPIO)
+#define GPIO94_KP_O7		PIN_CFG(94, ALT_A)
+#define GPIO94_SM_ADVn		PIN_CFG(94, ALT_B)
+#define GPIO94_MC5_DAT5		PIN_CFG(94, ALT_C)
+
+#define GPIO95_GPIO		PIN_CFG(95, GPIO)
+#define GPIO95_KP_I7		PIN_CFG(95, ALT_A)
+#define GPIO95_SM_CS0n		PIN_CFG(95, ALT_B)
+#define GPIO95_SM_PS0n		PIN_CFG(95, ALT_C)
+
+#define GPIO96_GPIO		PIN_CFG(96, GPIO)
+#define GPIO96_KP_O6		PIN_CFG(96, ALT_A)
+#define GPIO96_SM_OEn		PIN_CFG(96, ALT_B)
+#define GPIO96_MC5_DAT6		PIN_CFG(96, ALT_C)
+
+#define GPIO97_GPIO		PIN_CFG(97, GPIO)
+#define GPIO97_KP_I6		PIN_CFG(97, ALT_A)
+#define GPIO97_SM_WEn		PIN_CFG(97, ALT_B)
+#define GPIO97_MC5_DAT7		PIN_CFG(97, ALT_C)
+
+#define GPIO128_GPIO		PIN_CFG(128, GPIO)
+#define GPIO128_MC2_CLK		PIN_CFG(128, ALT_A)
+#define GPIO128_SM_CKO		PIN_CFG(128, ALT_B)
+
+#define GPIO129_GPIO		PIN_CFG(129, GPIO)
+#define GPIO129_MC2_CMD		PIN_CFG(129, ALT_A)
+#define GPIO129_SM_WAIT0n	PIN_CFG(129, ALT_B)
+
+#define GPIO130_GPIO		PIN_CFG(130, GPIO)
+#define GPIO130_MC2_FBCLK	PIN_CFG(130, ALT_A)
+#define GPIO130_SM_FBCLK	PIN_CFG(130, ALT_B)
+#define GPIO130_MC2_RSTN	PIN_CFG(130, ALT_C)
+
+#define GPIO131_GPIO		PIN_CFG(131, GPIO)
+#define GPIO131_MC2_DAT0	PIN_CFG(131, ALT_A)
+#define GPIO131_SM_ADQ8		PIN_CFG(131, ALT_B)
+
+#define GPIO132_GPIO		PIN_CFG(132, GPIO)
+#define GPIO132_MC2_DAT1	PIN_CFG(132, ALT_A)
+#define GPIO132_SM_ADQ9		PIN_CFG(132, ALT_B)
+
+#define GPIO133_GPIO		PIN_CFG(133, GPIO)
+#define GPIO133_MC2_DAT2	PIN_CFG(133, ALT_A)
+#define GPIO133_SM_ADQ10	PIN_CFG(133, ALT_B)
+
+#define GPIO134_GPIO		PIN_CFG(134, GPIO)
+#define GPIO134_MC2_DAT3	PIN_CFG(134, ALT_A)
+#define GPIO134_SM_ADQ11	PIN_CFG(134, ALT_B)
+
+#define GPIO135_GPIO		PIN_CFG(135, GPIO)
+#define GPIO135_MC2_DAT4	PIN_CFG(135, ALT_A)
+#define GPIO135_SM_ADQ12	PIN_CFG(135, ALT_B)
+
+#define GPIO136_GPIO		PIN_CFG(136, GPIO)
+#define GPIO136_MC2_DAT5	PIN_CFG(136, ALT_A)
+#define GPIO136_SM_ADQ13	PIN_CFG(136, ALT_B)
+
+#define GPIO137_GPIO		PIN_CFG(137, GPIO)
+#define GPIO137_MC2_DAT6	PIN_CFG(137, ALT_A)
+#define GPIO137_SM_ADQ14	PIN_CFG(137, ALT_B)
+
+#define GPIO138_GPIO		PIN_CFG(138, GPIO)
+#define GPIO138_MC2_DAT7	PIN_CFG(138, ALT_A)
+#define GPIO138_SM_ADQ15	PIN_CFG(138, ALT_B)
+
+#define GPIO139_GPIO		PIN_CFG(139, GPIO)
+#define GPIO139_SSP1_RXD	PIN_CFG(139, ALT_A)
+#define GPIO139_SM_WAIT1n	PIN_CFG(139, ALT_B)
+#define GPIO139_KP_O8		PIN_CFG(139, ALT_C)
+
+#define GPIO140_GPIO		PIN_CFG(140, GPIO)
+#define GPIO140_SSP1_TXD	PIN_CFG(140, ALT_A)
+#define GPIO140_IP_GPIO7	PIN_CFG(140, ALT_B)
+#define GPIO140_KP_SKA1		PIN_CFG(140, ALT_C)
+
+#define GPIO141_GPIO		PIN_CFG(141, GPIO)
+#define GPIO141_SSP1_CLK	PIN_CFG(141, ALT_A)
+#define GPIO141_IP_GPIO2	PIN_CFG(141, ALT_B)
+#define GPIO141_KP_O9		PIN_CFG(141, ALT_C)
+
+#define GPIO142_GPIO		PIN_CFG(142, GPIO)
+#define GPIO142_SSP1_FRM	PIN_CFG(142, ALT_A)
+#define GPIO142_IP_GPIO3	PIN_CFG(142, ALT_B)
+#define GPIO142_KP_SKB1		PIN_CFG(142, ALT_C)
+
+#define GPIO143_GPIO		PIN_CFG(143, GPIO)
+#define GPIO143_SSP0_CLK	PIN_CFG(143, ALT_A)
+
+#define GPIO144_GPIO		PIN_CFG(144, GPIO)
+#define GPIO144_SSP0_FRM	PIN_CFG(144, ALT_A)
+
+#define GPIO145_GPIO		PIN_CFG(145, GPIO)
+#define GPIO145_SSP0_RXD	PIN_CFG(145, ALT_A)
+
+#define GPIO146_GPIO		PIN_CFG(146, GPIO)
+#define GPIO146_SSP0_TXD	PIN_CFG(146, ALT_A)
+
+#define GPIO147_GPIO		PIN_CFG(147, GPIO)
+#define GPIO147_I2C0_SCL	PIN_CFG_PULL(147, ALT_A, UP)
+
+#define GPIO148_GPIO		PIN_CFG(148, GPIO)
+#define GPIO148_I2C0_SDA	PIN_CFG_PULL(148, ALT_A, UP)
+
+#define GPIO149_GPIO		PIN_CFG(149, GPIO)
+#define GPIO149_IP_GPIO0	PIN_CFG(149, ALT_A)
+#define GPIO149_SM_CS1n		PIN_CFG(149, ALT_B)
+#define GPIO149_SM_PS1n		PIN_CFG(149, ALT_C)
+
+#define GPIO150_GPIO		PIN_CFG(150, GPIO)
+#define GPIO150_IP_GPIO1	PIN_CFG(150, ALT_A)
+#define GPIO150_LCDA_CLK	PIN_CFG(150, ALT_B)
+
+#define GPIO151_GPIO		PIN_CFG(151, GPIO)
+#define GPIO151_KP_SKA0		PIN_CFG(151, ALT_A)
+#define GPIO151_LCD_VSI0	PIN_CFG(151, ALT_B)
+#define GPIO151_KP_O8		PIN_CFG(151, ALT_C)
+
+#define GPIO152_GPIO		PIN_CFG(152, GPIO)
+#define GPIO152_KP_SKB0		PIN_CFG(152, ALT_A)
+#define GPIO152_LCD_VSI1	PIN_CFG(152, ALT_B)
+#define GPIO152_KP_O9		PIN_CFG(152, ALT_C)
+
+#define GPIO153_GPIO		PIN_CFG(153, GPIO)
+#define GPIO153_KP_I7		PIN_CFG_PULL(153, ALT_A, DOWN)
+#define GPIO153_LCD_D24		PIN_CFG(153, ALT_B)
+#define GPIO153_U2_RXD		PIN_CFG(153, ALT_C)
+
+#define GPIO154_GPIO		PIN_CFG(154, GPIO)
+#define GPIO154_KP_I6		PIN_CFG_PULL(154, ALT_A, DOWN)
+#define GPIO154_LCD_D25		PIN_CFG(154, ALT_B)
+#define GPIO154_U2_TXD		PIN_CFG(154, ALT_C)
+
+#define GPIO155_GPIO		PIN_CFG(155, GPIO)
+#define GPIO155_KP_I5		PIN_CFG_PULL(155, ALT_A, DOWN)
+#define GPIO155_LCD_D26		PIN_CFG(155, ALT_B)
+#define GPIO155_STMAPE_CLK	PIN_CFG(155, ALT_C)
+
+#define GPIO156_GPIO		PIN_CFG(156, GPIO)
+#define GPIO156_KP_I4		PIN_CFG_PULL(156, ALT_A, DOWN)
+#define GPIO156_LCD_D27		PIN_CFG(156, ALT_B)
+#define GPIO156_STMAPE_DAT3	PIN_CFG(156, ALT_C)
+
+#define GPIO157_GPIO		PIN_CFG(157, GPIO)
+#define GPIO157_KP_O7		PIN_CFG_PULL(157, ALT_A, UP)
+#define GPIO157_LCD_D28		PIN_CFG(157, ALT_B)
+#define GPIO157_STMAPE_DAT2	PIN_CFG(157, ALT_C)
+
+#define GPIO158_GPIO		PIN_CFG(158, GPIO)
+#define GPIO158_KP_O6		PIN_CFG_PULL(158, ALT_A, UP)
+#define GPIO158_LCD_D29		PIN_CFG(158, ALT_B)
+#define GPIO158_STMAPE_DAT1	PIN_CFG(158, ALT_C)
+
+#define GPIO159_GPIO		PIN_CFG(159, GPIO)
+#define GPIO159_KP_O5		PIN_CFG_PULL(159, ALT_A, UP)
+#define GPIO159_LCD_D30		PIN_CFG(159, ALT_B)
+#define GPIO159_STMAPE_DAT0	PIN_CFG(159, ALT_C)
+
+#define GPIO160_GPIO		PIN_CFG(160, GPIO)
+#define GPIO160_KP_O4		PIN_CFG_PULL(160, ALT_A, UP)
+#define GPIO160_LCD_D31		PIN_CFG(160, ALT_B)
+#define GPIO160_NONE		PIN_CFG(160, ALT_C)
+
+#define GPIO161_GPIO		PIN_CFG(161, GPIO)
+#define GPIO161_KP_I3		PIN_CFG_PULL(161, ALT_A, DOWN)
+#define GPIO161_LCD_D32		PIN_CFG(161, ALT_B)
+#define GPIO161_UARTMOD_RXD	PIN_CFG(161, ALT_C)
+
+#define GPIO162_GPIO		PIN_CFG(162, GPIO)
+#define GPIO162_KP_I2		PIN_CFG_PULL(162, ALT_A, DOWN)
+#define GPIO162_LCD_D33		PIN_CFG(162, ALT_B)
+#define GPIO162_UARTMOD_TXD	PIN_CFG(162, ALT_C)
+
+#define GPIO163_GPIO		PIN_CFG(163, GPIO)
+#define GPIO163_KP_I1		PIN_CFG_PULL(163, ALT_A, DOWN)
+#define GPIO163_LCD_D34		PIN_CFG(163, ALT_B)
+#define GPIO163_STMMOD_CLK	PIN_CFG(163, ALT_C)
+
+#define GPIO164_GPIO		PIN_CFG(164, GPIO)
+#define GPIO164_KP_I0		PIN_CFG_PULL(164, ALT_A, UP)
+#define GPIO164_LCD_D35		PIN_CFG(164, ALT_B)
+#define GPIO164_STMMOD_DAT3	PIN_CFG(164, ALT_C)
+
+#define GPIO165_GPIO		PIN_CFG(165, GPIO)
+#define GPIO165_KP_O3		PIN_CFG_PULL(165, ALT_A, UP)
+#define GPIO165_LCD_D36		PIN_CFG(165, ALT_B)
+#define GPIO165_STMMOD_DAT2	PIN_CFG(165, ALT_C)
+
+#define GPIO166_GPIO		PIN_CFG(166, GPIO)
+#define GPIO166_KP_O2		PIN_CFG_PULL(166, ALT_A, UP)
+#define GPIO166_LCD_D37		PIN_CFG(166, ALT_B)
+#define GPIO166_STMMOD_DAT1	PIN_CFG(166, ALT_C)
+
+#define GPIO167_GPIO		PIN_CFG(167, GPIO)
+#define GPIO167_KP_O1		PIN_CFG_PULL(167, ALT_A, UP)
+#define GPIO167_LCD_D38		PIN_CFG(167, ALT_B)
+#define GPIO167_STMMOD_DAT0	PIN_CFG(167, ALT_C)
+
+#define GPIO168_GPIO		PIN_CFG(168, GPIO)
+#define GPIO168_KP_O0		PIN_CFG_PULL(168, ALT_A, UP)
+#define GPIO168_LCD_D39		PIN_CFG(168, ALT_B)
+#define GPIO168_NONE		PIN_CFG(168, ALT_C)
+
+#define GPIO169_GPIO		PIN_CFG(169, GPIO)
+#define GPIO169_RF_PURn		PIN_CFG(169, ALT_A)
+#define GPIO169_LCDA_DE		PIN_CFG(169, ALT_B)
+#define GPIO169_USBSIM_PDC	PIN_CFG(169, ALT_C)
+
+#define GPIO170_GPIO		PIN_CFG(170, GPIO)
+#define GPIO170_MODEM_STATE	PIN_CFG(170, ALT_A)
+#define GPIO170_LCDA_VSO	PIN_CFG(170, ALT_B)
+#define GPIO170_KP_SKA1		PIN_CFG(170, ALT_C)
+
+#define GPIO171_GPIO		PIN_CFG(171, GPIO)
+#define GPIO171_MODEM_PWREN	PIN_CFG(171, ALT_A)
+#define GPIO171_LCDA_HSO	PIN_CFG(171, ALT_B)
+#define GPIO171_KP_SKB1		PIN_CFG(171, ALT_C)
+
+#define GPIO192_GPIO		PIN_CFG(192, GPIO)
+#define GPIO192_MSP2_SCK	PIN_CFG(192, ALT_A)
+
+#define GPIO193_GPIO		PIN_CFG(193, GPIO)
+#define GPIO193_MSP2_TXD	PIN_CFG(193, ALT_A)
+
+#define GPIO194_GPIO		PIN_CFG(194, GPIO)
+#define GPIO194_MSP2_TCK	PIN_CFG(194, ALT_A)
+
+#define GPIO195_GPIO		PIN_CFG(195, GPIO)
+#define GPIO195_MSP2_TFS	PIN_CFG(195, ALT_A)
+
+#define GPIO196_GPIO		PIN_CFG(196, GPIO)
+#define GPIO196_MSP2_RXD	PIN_CFG(196, ALT_A)
+
+#define GPIO197_GPIO		PIN_CFG(197, GPIO)
+#define GPIO197_MC4_DAT3	PIN_CFG(197, ALT_A)
+
+#define GPIO198_GPIO		PIN_CFG(198, GPIO)
+#define GPIO198_MC4_DAT2	PIN_CFG(198, ALT_A)
+
+#define GPIO199_GPIO		PIN_CFG(199, GPIO)
+#define GPIO199_MC4_DAT1	PIN_CFG(199, ALT_A)
+
+#define GPIO200_GPIO		PIN_CFG(200, GPIO)
+#define GPIO200_MC4_DAT0	PIN_CFG(200, ALT_A)
+
+#define GPIO201_GPIO		PIN_CFG(201, GPIO)
+#define GPIO201_MC4_CMD		PIN_CFG(201, ALT_A)
+
+#define GPIO202_GPIO		PIN_CFG(202, GPIO)
+#define GPIO202_MC4_FBCLK	PIN_CFG(202, ALT_A)
+#define GPIO202_PWL		PIN_CFG(202, ALT_B)
+#define GPIO202_MC4_RSTN	PIN_CFG(202, ALT_C)
+
+#define GPIO203_GPIO		PIN_CFG(203, GPIO)
+#define GPIO203_MC4_CLK		PIN_CFG(203, ALT_A)
+
+#define GPIO204_GPIO		PIN_CFG(204, GPIO)
+#define GPIO204_MC4_DAT7	PIN_CFG(204, ALT_A)
+
+#define GPIO205_GPIO		PIN_CFG(205, GPIO)
+#define GPIO205_MC4_DAT6	PIN_CFG(205, ALT_A)
+
+#define GPIO206_GPIO		PIN_CFG(206, GPIO)
+#define GPIO206_MC4_DAT5	PIN_CFG(206, ALT_A)
+
+#define GPIO207_GPIO		PIN_CFG(207, GPIO)
+#define GPIO207_MC4_DAT4	PIN_CFG(207, ALT_A)
+
+#define GPIO208_GPIO		PIN_CFG(208, GPIO)
+#define GPIO208_MC1_CLK		PIN_CFG(208, ALT_A)
+
+#define GPIO209_GPIO		PIN_CFG(209, GPIO)
+#define GPIO209_MC1_FBCLK	PIN_CFG(209, ALT_A)
+#define GPIO209_SPI1_CLK	PIN_CFG(209, ALT_B)
+
+#define GPIO210_GPIO		PIN_CFG(210, GPIO)
+#define GPIO210_MC1_CMD		PIN_CFG(210, ALT_A)
+
+#define GPIO211_GPIO		PIN_CFG(211, GPIO)
+#define GPIO211_MC1_DAT0	PIN_CFG(211, ALT_A)
+
+#define GPIO212_GPIO		PIN_CFG(212, GPIO)
+#define GPIO212_MC1_DAT1	PIN_CFG(212, ALT_A)
+#define GPIO212_SPI1_FRM	PIN_CFG(212, ALT_B)
+
+#define GPIO213_GPIO		PIN_CFG(213, GPIO)
+#define GPIO213_MC1_DAT2	PIN_CFG(213, ALT_A)
+#define GPIO213_SPI1_TXD	PIN_CFG(213, ALT_B)
+
+#define GPIO214_GPIO		PIN_CFG(214, GPIO)
+#define GPIO214_MC1_DAT3	PIN_CFG(214, ALT_A)
+#define GPIO214_SPI1_RXD	PIN_CFG(214, ALT_B)
+
+#define GPIO215_GPIO		PIN_CFG(215, GPIO)
+#define GPIO215_MC1_CMDDIR	PIN_CFG(215, ALT_A)
+#define GPIO215_MC3_DAT2DIR	PIN_CFG(215, ALT_B)
+#define GPIO215_CLKOUT1		PIN_CFG(215, ALT_C)
+
+#define GPIO216_GPIO		PIN_CFG(216, GPIO)
+#define GPIO216_MC1_DAT2DIR	PIN_CFG(216, ALT_A)
+#define GPIO216_MC3_CMDDIR	PIN_CFG(216, ALT_B)
+#define GPIO216_I2C3_SDA	PIN_CFG_PULL(216, ALT_C, UP)
+
+#define GPIO217_GPIO		PIN_CFG(217, GPIO)
+#define GPIO217_MC1_DAT0DIR	PIN_CFG(217, ALT_A)
+#define GPIO217_MC3_DAT31DIR	PIN_CFG(217, ALT_B)
+#define GPIO217_CLKOUT2		PIN_CFG(217, ALT_C)
+
+#define GPIO218_GPIO		PIN_CFG(218, GPIO)
+#define GPIO218_MC1_DAT31DIR	PIN_CFG(218, ALT_A)
+#define GPIO218_MC3_DAT0DIR	PIN_CFG(218, ALT_B)
+#define GPIO218_I2C3_SCL	PIN_CFG_PULL(218, ALT_C, UP)
+
+#define GPIO219_GPIO		PIN_CFG(219, GPIO)
+#define GPIO219_HSIR_FLA0	PIN_CFG(219, ALT_A)
+#define GPIO219_MC3_CLK		PIN_CFG(219, ALT_B)
+
+#define GPIO220_GPIO		PIN_CFG(220, GPIO)
+#define GPIO220_HSIR_DAT0	PIN_CFG(220, ALT_A)
+#define GPIO220_MC3_FBCLK	PIN_CFG(220, ALT_B)
+#define GPIO220_SPI0_CLK	PIN_CFG(220, ALT_C)
+
+#define GPIO221_GPIO		PIN_CFG(221, GPIO)
+#define GPIO221_HSIR_RDY0	PIN_CFG(221, ALT_A)
+#define GPIO221_MC3_CMD		PIN_CFG(221, ALT_B)
+
+#define GPIO222_GPIO		PIN_CFG(222, GPIO)
+#define GPIO222_HSIT_FLA0	PIN_CFG(222, ALT_A)
+#define GPIO222_MC3_DAT0	PIN_CFG(222, ALT_B)
+
+#define GPIO223_GPIO		PIN_CFG(223, GPIO)
+#define GPIO223_HSIT_DAT0	PIN_CFG(223, ALT_A)
+#define GPIO223_MC3_DAT1	PIN_CFG(223, ALT_B)
+#define GPIO223_SPI0_FRM	PIN_CFG(223, ALT_C)
+
+#define GPIO224_GPIO		PIN_CFG(224, GPIO)
+#define GPIO224_HSIT_RDY0	PIN_CFG(224, ALT_A)
+#define GPIO224_MC3_DAT2	PIN_CFG(224, ALT_B)
+#define GPIO224_SPI0_TXD	PIN_CFG(224, ALT_C)
+
+#define GPIO225_GPIO		PIN_CFG(225, GPIO)
+#define GPIO225_HSIT_CAWAKE0	PIN_CFG(225, ALT_A)
+#define GPIO225_MC3_DAT3	PIN_CFG(225, ALT_B)
+#define GPIO225_SPI0_RXD	PIN_CFG(225, ALT_C)
+
+#define GPIO226_GPIO		PIN_CFG(226, GPIO)
+#define GPIO226_HSIT_ACWAKE0	PIN_CFG(226, ALT_A)
+#define GPIO226_PWL		PIN_CFG(226, ALT_B)
+#define GPIO226_USBSIM_PDC	PIN_CFG(226, ALT_C)
+
+#define GPIO227_GPIO		PIN_CFG(227, GPIO)
+#define GPIO227_CLKOUT1		PIN_CFG(227, ALT_A)
+
+#define GPIO228_GPIO		PIN_CFG(228, GPIO)
+#define GPIO228_CLKOUT2		PIN_CFG(228, ALT_A)
+
+#define GPIO229_GPIO		PIN_CFG(229, GPIO)
+#define GPIO229_CLKOUT1		PIN_CFG(229, ALT_A)
+#define GPIO229_PWL		PIN_CFG(229, ALT_B)
+#define GPIO229_I2C3_SDA	PIN_CFG_PULL(229, ALT_C, UP)
+
+#define GPIO230_GPIO		PIN_CFG(230, GPIO)
+#define GPIO230_CLKOUT2		PIN_CFG(230, ALT_A)
+#define GPIO230_PWL		PIN_CFG(230, ALT_B)
+#define GPIO230_I2C3_SCL	PIN_CFG_PULL(230, ALT_C, UP)
+
+#define GPIO256_GPIO		PIN_CFG(256, GPIO)
+#define GPIO256_USB_NXT		PIN_CFG(256, ALT_A)
+
+#define GPIO257_GPIO		PIN_CFG(257, GPIO)
+#define GPIO257_USB_STP		PIN_CFG(257, ALT_A)
+
+#define GPIO258_GPIO		PIN_CFG(258, GPIO)
+#define GPIO258_USB_XCLK	PIN_CFG(258, ALT_A)
+#define GPIO258_NONE		PIN_CFG(258, ALT_B)
+#define GPIO258_DDR_TRIG	PIN_CFG(258, ALT_C)
+
+#define GPIO259_GPIO		PIN_CFG(259, GPIO)
+#define GPIO259_USB_DIR		PIN_CFG(259, ALT_A)
+
+#define GPIO260_GPIO		PIN_CFG(260, GPIO)
+#define GPIO260_USB_DAT7	PIN_CFG(260, ALT_A)
+
+#define GPIO261_GPIO		PIN_CFG(261, GPIO)
+#define GPIO261_USB_DAT6	PIN_CFG(261, ALT_A)
+
+#define GPIO262_GPIO		PIN_CFG(262, GPIO)
+#define GPIO262_USB_DAT5	PIN_CFG(262, ALT_A)
+
+#define GPIO263_GPIO		PIN_CFG(263, GPIO)
+#define GPIO263_USB_DAT4	PIN_CFG(263, ALT_A)
+
+#define GPIO264_GPIO		PIN_CFG(264, GPIO)
+#define GPIO264_USB_DAT3	PIN_CFG(264, ALT_A)
+
+#define GPIO265_GPIO		PIN_CFG(265, GPIO)
+#define GPIO265_USB_DAT2	PIN_CFG(265, ALT_A)
+
+#define GPIO266_GPIO		PIN_CFG(266, GPIO)
+#define GPIO266_USB_DAT1	PIN_CFG(266, ALT_A)
+
+#define GPIO267_GPIO		PIN_CFG(267, GPIO)
+#define GPIO267_USB_DAT0	PIN_CFG(267, ALT_A)
+
+#endif
diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c
new file mode 100644
index 0000000..79c86df
--- /dev/null
+++ b/board/st-ericsson/snowball/snowball.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/db8500_pincfg.h>
+
+#include "db8500_pins.h"
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Memory controller register
+ */
+#define DMC_BASE_ADDR			0x80156000
+#define DMC_CTL_97			(DMC_BASE_ADDR + 0x184)
+
+/*
+ * GPIO pin config common for MOP500/HREF boards
+ */
+pin_cfg_t gpio_cfg_common[] = {
+	/* I2C */
+	GPIO147_I2C0_SCL,
+	GPIO148_I2C0_SDA,
+	GPIO16_I2C1_SCL,
+	GPIO17_I2C1_SDA,
+	GPIO10_I2C2_SDA,
+	GPIO11_I2C2_SCL,
+	GPIO229_I2C3_SDA,
+	GPIO230_I2C3_SCL,
+
+	/* SSP0, to AB8500 */
+	GPIO143_SSP0_CLK,
+	GPIO144_SSP0_FRM,
+	GPIO145_SSP0_RXD | PIN_PULL_DOWN,
+	GPIO146_SSP0_TXD,
+
+	/* MMC0 (MicroSD card) */
+	GPIO18_MC0_CMDDIR	| PIN_OUTPUT_HIGH,
+	GPIO19_MC0_DAT0DIR	| PIN_OUTPUT_HIGH,
+	GPIO20_MC0_DAT2DIR	| PIN_OUTPUT_HIGH,
+	GPIO21_MC0_DAT31DIR	| PIN_OUTPUT_HIGH,
+	GPIO22_MC0_FBCLK	| PIN_INPUT_NOPULL,
+	GPIO23_MC0_CLK		| PIN_OUTPUT_LOW,
+	GPIO24_MC0_CMD		| PIN_INPUT_PULLUP,
+	GPIO25_MC0_DAT0		| PIN_INPUT_PULLUP,
+	GPIO26_MC0_DAT1		| PIN_INPUT_PULLUP,
+	GPIO27_MC0_DAT2		| PIN_INPUT_PULLUP,
+	GPIO28_MC0_DAT3		| PIN_INPUT_PULLUP,
+
+	/* MMC4 (On-board eMMC) */
+	GPIO197_MC4_DAT3	| PIN_INPUT_PULLUP,
+	GPIO198_MC4_DAT2	| PIN_INPUT_PULLUP,
+	GPIO199_MC4_DAT1	| PIN_INPUT_PULLUP,
+	GPIO200_MC4_DAT0	| PIN_INPUT_PULLUP,
+	GPIO201_MC4_CMD		| PIN_INPUT_PULLUP,
+	GPIO202_MC4_FBCLK	| PIN_INPUT_NOPULL,
+	GPIO203_MC4_CLK		| PIN_OUTPUT_LOW,
+	GPIO204_MC4_DAT7	| PIN_INPUT_PULLUP,
+	GPIO205_MC4_DAT6	| PIN_INPUT_PULLUP,
+	GPIO206_MC4_DAT5	| PIN_INPUT_PULLUP,
+	GPIO207_MC4_DAT4	| PIN_INPUT_PULLUP,
+
+	/* UART2, console */
+	GPIO29_U2_RXD	| PIN_INPUT_PULLUP,
+	GPIO30_U2_TXD	| PIN_OUTPUT_HIGH,
+	GPIO31_U2_CTSn	| PIN_INPUT_PULLUP,
+	GPIO32_U2_RTSn	| PIN_OUTPUT_HIGH,
+
+	/*
+	 * USB, pin 256-267 USB, Is probably already setup correctly from
+	 * BootROM/boot stages, but we don't trust that and set it up anyway
+	 */
+	GPIO256_USB_NXT,
+	GPIO257_USB_STP,
+	GPIO258_USB_XCLK,
+	GPIO259_USB_DIR,
+	GPIO260_USB_DAT7,
+	GPIO261_USB_DAT6,
+	GPIO262_USB_DAT5,
+	GPIO263_USB_DAT4,
+	GPIO264_USB_DAT3,
+	GPIO265_USB_DAT2,
+	GPIO266_USB_DAT1,
+	GPIO267_USB_DAT0,
+};
+
+pin_cfg_t gpio_cfg_snowball[] = {
+	/* MMC0 (MicroSD card) */
+	GPIO217_GPIO    | PIN_OUTPUT_HIGH,      /* MMC_EN */
+	GPIO218_GPIO    | PIN_INPUT_NOPULL,     /* MMC_CD */
+	GPIO228_GPIO    | PIN_OUTPUT_HIGH,      /* SD_SEL */
+
+	/* eMMC */
+	GPIO167_GPIO    | PIN_OUTPUT_HIGH,      /* RSTn_MLC */
+
+	/* LAN */
+	GPIO131_SM_ADQ8,
+	GPIO132_SM_ADQ9,
+	GPIO133_SM_ADQ10,
+	GPIO134_SM_ADQ11,
+	GPIO135_SM_ADQ12,
+	GPIO136_SM_ADQ13,
+	GPIO137_SM_ADQ14,
+	GPIO138_SM_ADQ15,
+
+	/* RSTn_LAN */
+	GPIO141_GPIO	| PIN_OUTPUT_HIGH,
+};
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	/*
+	 * Setup board (bd) and board-info (bi).
+	 * bi_arch_number: Unique id for this board. It will passed in r1 to
+	 *    Linux startup code and is the machine_id.
+	 * bi_boot_params: Where this board expects params.
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL;
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* Configure GPIO pins needed by U-boot */
+	db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common));
+
+	db8500_gpio_config_pins(gpio_cfg_snowball,
+						ARRAY_SIZE(gpio_cfg_snowball));
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	uint32_t unused_cols_rows;
+	unsigned int nrows;
+	unsigned int ncols;
+
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = PHYS_SDRAM_SIZE_1;
+
+	/*
+	 * Assumption: 2 CS active, both CS have same layout.
+	 *             15 rows max, 11 cols max (controller spec).
+	 *             memory chip has 8 banks, I/O width 32 bit.
+	 * The correct way would be to read MR#8: I/O width and density,
+	 * but this requires locking against the PRCMU firmware.
+	 * Simplified approach:
+	 * Read number of unused rows and columns from mem controller.
+	 * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes
+	 */
+	unused_cols_rows = readl(DMC_CTL_97);
+	nrows = 15 - (unused_cols_rows & 0x07);
+	ncols = 11 - ((unused_cols_rows & 0x0700) >> 8);
+	gd->ram_size = gd->bd->bi_dram[0].size =
+					2 * (1 << (nrows + ncols)) * 8 * 4;
+
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index a723f67..b28052d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -232,6 +232,7 @@ harmony                      arm         armv7       harmony             nvidia
 seaboard                     arm         armv7       seaboard            nvidia         tegra2
 ventana                      arm         armv7       ventana             nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+snowball		     arm	 armv7	     snowball		 st-ericsson	u8500
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb3b09a..36a0ff3 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO)	+= tegra2_gpio.o
 COBJS-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
 COBJS-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
 COBJS-$(CONFIG_MPC83XX_GPIO)	+= mpc83xx_gpio.o
+COBJS-$(CONFIG_DB8500_GPIO)	+= db8500_gpio.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
diff --git a/drivers/gpio/db8500_gpio.c b/drivers/gpio/db8500_gpio.c
new file mode 100644
index 0000000..5eb6361
--- /dev/null
+++ b/drivers/gpio/db8500_gpio.c
@@ -0,0 +1,225 @@
+/*
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot.
+ *
+ * Original Linux authors:
+ * Copyright (C) 2008,2009 STMicroelectronics
+ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
+ *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
+ *
+ * Ported to U-boot by:
+ * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include <asm/arch/db8500_gpio.h>
+#include <asm/arch/db8500_pincfg.h>
+
+/*
+ * Macros to work with IO space
+ * Not actually used?
+ */
+#define __iomem
+#define IO_ADDR(x) (void *) (x)
+
+/*
+ * The GPIO module in the db8500 Systems-on-Chip is an
+ * AMBA device, managing 32 pins and alternate functions. The logic block
+ * is currently only used in the db8500.
+ */
+
+#define GPIO_TOTAL_PINS		268
+#define GPIO_PINS_PER_BLOCK	32
+#define GPIO_BLOCKS_COUNT	(GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
+#define GPIO_BLOCK(pin)		(((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
+#define GPIO_PIN_WITHIN_BLOCK(pin)	((pin)%(GPIO_PINS_PER_BLOCK))
+
+/* Register in the logic block */
+#define DB8500_GPIO_DAT		0x00
+#define DB8500_GPIO_DATS	0x04
+#define DB8500_GPIO_DATC	0x08
+#define DB8500_GPIO_PDIS	0x0c
+#define DB8500_GPIO_DIR		0x10
+#define DB8500_GPIO_DIRS	0x14
+#define DB8500_GPIO_DIRC	0x18
+#define DB8500_GPIO_SLPC	0x1c
+#define DB8500_GPIO_AFSLA	0x20
+#define DB8500_GPIO_AFSLB	0x24
+
+#define DB8500_GPIO_RIMSC	0x40
+#define DB8500_GPIO_FIMSC	0x44
+#define DB8500_GPIO_IS		0x48
+#define DB8500_GPIO_IC		0x4c
+#define DB8500_GPIO_RWIMSC	0x50
+#define DB8500_GPIO_FWIMSC	0x54
+#define DB8500_GPIO_WKS		0x58
+
+static void __iomem *get_gpio_addr(unsigned gpio)
+{
+	/* Our list of GPIO chips */
+	static void __iomem *gpio_addrs[GPIO_BLOCKS_COUNT] = {
+		IO_ADDR(CFG_GPIO_0_BASE),
+		IO_ADDR(CFG_GPIO_1_BASE),
+		IO_ADDR(CFG_GPIO_2_BASE),
+		IO_ADDR(CFG_GPIO_3_BASE),
+		IO_ADDR(CFG_GPIO_4_BASE),
+		IO_ADDR(CFG_GPIO_5_BASE),
+		IO_ADDR(CFG_GPIO_6_BASE),
+		IO_ADDR(CFG_GPIO_7_BASE),
+		IO_ADDR(CFG_GPIO_8_BASE)
+	};
+
+	return gpio_addrs[GPIO_BLOCK(gpio)];
+}
+
+static unsigned get_gpio_offset(unsigned gpio)
+{
+	return GPIO_PIN_WITHIN_BLOCK(gpio);
+}
+
+/* Can only be called from config_pin. Don't configure alt-mode directly */
+static void gpio_set_mode(unsigned gpio, enum db8500_gpio_alt mode)
+{
+	void __iomem *addr = get_gpio_addr(gpio);
+	unsigned offset = get_gpio_offset(gpio);
+	u32 bit = 1 << offset;
+	u32 afunc, bfunc;
+
+	afunc = readl(addr + DB8500_GPIO_AFSLA) & ~bit;
+	bfunc = readl(addr + DB8500_GPIO_AFSLB) & ~bit;
+	if (mode & DB8500_GPIO_ALT_A)
+		afunc |= bit;
+	if (mode & DB8500_GPIO_ALT_B)
+		bfunc |= bit;
+	writel(afunc, addr + DB8500_GPIO_AFSLA);
+	writel(bfunc, addr + DB8500_GPIO_AFSLB);
+}
+
+/**
+ * db8500_gpio_set_pull() - enable/disable pull up/down on a gpio
+ * @gpio: pin number
+ * @pull: one of DB8500_GPIO_PULL_DOWN, DB8500_GPIO_PULL_UP,
+ *  and DB8500_GPIO_PULL_NONE
+ *
+ * Enables/disables pull up/down on a specified pin.  This only takes effect if
+ * the pin is configured as an input (either explicitly or by the alternate
+ * function).
+ *
+ * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
+ * configured as an input.  Otherwise, due to the way the controller registers
+ * work, this function will change the value output on the pin.
+ */
+void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull)
+{
+	void __iomem *addr = get_gpio_addr(gpio);
+	unsigned offset = get_gpio_offset(gpio);
+	u32 bit = 1 << offset;
+	u32 pdis;
+
+	pdis = readl(addr + DB8500_GPIO_PDIS);
+	if (pull == DB8500_GPIO_PULL_NONE)
+		pdis |= bit;
+	else
+		pdis &= ~bit;
+	writel(pdis, addr + DB8500_GPIO_PDIS);
+
+	if (pull == DB8500_GPIO_PULL_UP)
+		writel(bit, addr + DB8500_GPIO_DATS);
+	else if (pull == DB8500_GPIO_PULL_DOWN)
+		writel(bit, addr + DB8500_GPIO_DATC);
+}
+
+void db8500_gpio_make_input(unsigned gpio)
+{
+	void __iomem *addr = get_gpio_addr(gpio);
+	unsigned offset = get_gpio_offset(gpio);
+
+	writel(1 << offset, addr + DB8500_GPIO_DIRC);
+}
+
+int db8500_gpio_get_input(unsigned gpio)
+{
+	void __iomem *addr = get_gpio_addr(gpio);
+	unsigned offset = get_gpio_offset(gpio);
+	u32 bit = 1 << offset;
+
+	printf("db8500_gpio_get_input gpio=%u addr=%p offset=%u bit=%#x\n",
+		gpio, addr, offset, bit);
+
+	return (readl(addr + DB8500_GPIO_DAT) & bit) != 0;
+}
+
+void db8500_gpio_make_output(unsigned gpio, int val)
+{
+	void __iomem *addr = get_gpio_addr(gpio);
+	unsigned offset = get_gpio_offset(gpio);
+
+	writel(1 << offset, addr + DB8500_GPIO_DIRS);
+	db8500_gpio_set_output(gpio, val);
+}
+
+void db8500_gpio_set_output(unsigned gpio, int val)
+{
+	void __iomem *addr = get_gpio_addr(gpio);
+	unsigned offset = get_gpio_offset(gpio);
+
+	if (val)
+		writel(1 << offset, addr + DB8500_GPIO_DATS);
+	else
+		writel(1 << offset, addr + DB8500_GPIO_DATC);
+}
+
+/**
+ * config_pin - configure a pin's mux attributes
+ * @cfg: pin confguration
+ *
+ * Configures a pin's mode (alternate function or GPIO), its pull up status,
+ * and its sleep mode based on the specified configuration.  The @cfg is
+ * usually one of the SoC specific macros defined in mach/<soc>-pins.h.  These
+ * are constructed using, and can be further enhanced with, the macros in
+ * plat/pincfg.h.
+ *
+ * If a pin's mode is set to GPIO, it is configured as an input to avoid
+ * side-effects.  The gpio can be manipulated later using standard GPIO API
+ * calls.
+ */
+static void config_pin(pin_cfg_t cfg)
+{
+	int pin = PIN_NUM(cfg);
+	int pull = PIN_PULL(cfg);
+	int af = PIN_ALT(cfg);
+	int output = PIN_DIR(cfg);
+	int val = PIN_VAL(cfg);
+
+	if (output)
+		db8500_gpio_make_output(pin, val);
+	else {
+		db8500_gpio_make_input(pin);
+		db8500_gpio_set_pull(pin, pull);
+	}
+
+	gpio_set_mode(pin, af);
+}
+
+/**
+ * db8500_config_pins - configure several pins at once
+ * @cfgs: array of pin configurations
+ * @num: number of elments in the array
+ *
+ * Configures several pins using config_pin(). Refer to that function for
+ * further information.
+ */
+void db8500_gpio_config_pins(pin_cfg_t *cfgs, size_t num)
+{
+	size_t i;
+
+	for (i = 0; i < num; i++)
+		config_pin(cfgs[i]);
+}
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index ed581ae..d4c5137 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -156,6 +156,8 @@ int serial_init (void)
 			writel(lcr, &regs->fr);
 
 		writel(lcr, &regs->pl011_rlcr);
+		/* lcrh needs to be set again for change to be effective */
+		writel(lcr, &regs->pl011_lcrh);
 	}
 #endif
 	/* Finally, enable the UART */
diff --git a/include/configs/snowball.h b/include/configs/snowball.h
new file mode 100644
index 0000000..148d6ee
--- /dev/null
+++ b/include/configs/snowball.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * #define DEBUG 1
+ */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SNOWBALL
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_U8500
+#define CONFIG_L2_OFF
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END	0x1FFFFFFF
+#define CONFIG_SYS_HZ		1000		/* must be 1000 */
+
+/*-----------------------------------------------------------------------
+ * Size of environment and malloc() pool
+ */
+/*
+ * If you use U-Boot as crash kernel, make sure that it does not overwrite
+ * information saved by kexec during panic. Kexec expects the start
+ * address of the executable 32K above "crashkernel" address.
+ */
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE		(128*1024)
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 256*1024)
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* for initial data */
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_OFFSET		0x0118000
+#define CONFIG_SYS_MMC_ENV_DEV          0              /* SLOT2: eMMC */
+
+/*
+ * PL011 Configuration
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_SERIAL_RLCR
+#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+
+/*
+ * U8500 UART registers base for 3 serial devices
+ */
+#define CFG_UART0_BASE		0x80120000
+#define CFG_UART1_BASE		0x80121000
+#define CFG_UART2_BASE		0x80007000
+#define CFG_SERIAL0		CFG_UART0_BASE
+#define CFG_SERIAL1		CFG_UART1_BASE
+#define CFG_SERIAL2		CFG_UART2_BASE
+#define CONFIG_PL011_CLOCK	38400000
+#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
+				  (void *)CFG_SERIAL2 }
+#define CONFIG_CONS_INDEX	2
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Devices and file systems
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Commands
+ */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_SOURCE
+
+#ifndef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY	1
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev 1; "								\
+		"if run loadbootscript; "					\
+			"then run bootscript; "					\
+		"else "								\
+			"if run mmcload; "					\
+				"then run mmcboot; "				\
+			"else "							\
+				"mmc dev 0; "					\
+				"if run emmcloadbootscript; "			\
+					"then run bootscript; "			\
+				"else "						\
+					"if run emmcload; "			\
+						"then run emmcboot; "		\
+					"else "					\
+						"echo No media to boot from; "	\
+					"fi; "					\
+				"fi; "						\
+			"fi; "							\
+		"fi; "
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0"							\
+	"loadaddr=0x00100000\0"						\
+	"console=ttyAMA2,115200n8\0"					\
+	"loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0"		\
+	"emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0"	\
+	"bootscript=echo Running bootscript "				\
+		"from mmc ...; source ${loadaddr}\0"			\
+	"memargs256=mem=96M at 0 mem_modem=32M at 96M mem=32M at 128M "		\
+		"hwmem=22M at 160M pmem_hwb=42M at 182M mem_mali=32 at 224M\0"	\
+	"memargs512=mem=96M at 0 mem_modem=32M at 96M hwmem=32M at 128M "	\
+		"mem=64M at 160M mem_mali=32M at 224M "			\
+		"pmem_hwb=128M at 256M mem=128M at 384M\0"			\
+	"memargs1024=mem=128M at 0 mali.mali_mem=32M at 128M "		\
+		"hwmem=168M at M160M mem=48M at 328M "			\
+		"mem_issw=1M at 383M mem=640M at 384M\0"			\
+	"memargs=setenv bootargs ${bootargs} ${memargs1024}\0"		\
+	"emmcload=fatload mmc 0:2 ${loadaddr} uImage\0"			\
+	"mmcload=fatload mmc 1:1 ${loadaddr} uImage\0"			\
+	"commonargs=setenv bootargs console=${console} "		\
+	"vmalloc=300M\0"						\
+	"emmcargs=setenv bootargs ${bootargs} "				\
+		"root=/dev/mmcblk0p3 "					\
+		"rootwait\0"						\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=${console}\0"					\
+	"emmcboot=echo Booting from eMMC ...; "				\
+		"run commonargs emmcargs memargs; "			\
+		"bootm ${loadaddr}\0"					\
+	"mmcargs=setenv bootargs ${bootargs} "				\
+		"root=/dev/mmcblk1p2 "					\
+		"rootwait earlyprintk\0"				\
+	"mmcboot=echo Booting from external MMC ...; "			\
+		"run commonargs mmcargs memargs; "			\
+		"bootm ${loadaddr}\0"					\
+	"fdt_high=0x2BC00000\0"						\
+	"stdout=serial,usbtty\0"					\
+	"stdin=serial,usbtty\0"						\
+	"stderr=serial,usbtty\0"
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP			/* undef to save memory     */
+#define CONFIG_SYS_PROMPT	"U8500 $ "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
+
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR		0x00100000 /* default load address */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
+
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SETUP_MEMORY_TAGS	2
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x00000000	/* DDR-SDRAM Bank #1 */
+#define PHYS_SDRAM_SIZE_1		0x10000000	/* 256 MB */
+
+/*
+ * additions for new relocation code
+ */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE	0x100000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
+
+/* landing address before relocation */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE            0x0
+#endif
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * base register values for U8500
+ */
+#define CFG_PRCMU_BASE		0x80157000	/* Power, reset and clock */
+
+
+/*
+ * U8500 GPIO register base for 9 banks
+ */
+#define CONFIG_DB8500_GPIO
+#define CFG_GPIO_0_BASE			0x8012E000
+#define CFG_GPIO_1_BASE			0x8012E080
+#define CFG_GPIO_2_BASE			0x8000E000
+#define CFG_GPIO_3_BASE			0x8000E080
+#define CFG_GPIO_4_BASE			0x8000E100
+#define CFG_GPIO_5_BASE			0x8000E180
+#define CFG_GPIO_6_BASE			0x8011E000
+#define CFG_GPIO_7_BASE			0x8011E080
+#define CFG_GPIO_8_BASE			0xA03FE000
+
+#define CFG_FSMC_BASE		0x80000000	/* FSMC Controller */
+
+#endif	/* __CONFIG_H */
-- 
1.7.5.4