[U-Boot] [PATCH V3 1/3] arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138

[U-Boot] [PATCH V3 1/3] arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138

[Mikhail Kshevetskiy]

follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of
OMAP-L138 DSP+ARM Processor Technical Reference Manual

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
---
Change for v3:
 * split DDR and UART bugfixes to separate patch series (series 1/3)
Change for v2:
 * fix checkpatch warnings
---
 arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c |   26 +++++++++++++++++------
 arch/arm/include/asm/arch-davinci/hardware.h    |    1 +
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index df7d6a2..ff2e2e3 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -190,13 +190,21 @@ int da850_ddr_setup(void)
 
 		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
 		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
-
-		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
 	}
-
+	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
 	writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-	clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
-		(1 << DDR_SLEW_CMOSEN_BIT));
+
+	if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
+		/* DDR2 */
+		clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
+			(1 << DDR_SLEW_DDR_PDENA_BIT) |
+			(1 << DDR_SLEW_CMOSEN_BIT));
+	} else {
+		/* MOBILE DDR */
+		setbits_le32(&davinci_syscfg1_regs->ddr_slew,
+			(1 << DDR_SLEW_DDR_PDENA_BIT) |
+			(1 << DDR_SLEW_CMOSEN_BIT));
+	}
 
 	/*
 	 * SDRAM Configuration Register (SDCR):
@@ -216,7 +224,11 @@ int da850_ddr_setup(void)
 	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 
 	/* write memory configuration and timing */
-	writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
+	if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
+		/* MOBILE DDR only*/
+		writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+			&dv_ddr2_regs_ctrl->sdbcr2);
+	}
 	writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
 	writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
 
@@ -240,7 +252,7 @@ int da850_ddr_setup(void)
 
 	/* disable self refresh */
 	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
-		DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+		DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
 	writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
 
 	return 0;
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..56e5743 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -505,6 +505,7 @@ struct davinci_syscfg1_regs {
 	((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
 
 #define DDR_SLEW_CMOSEN_BIT	4
+#define DDR_SLEW_DDR_PDENA_BIT	5
 
 #define VTP_POWERDWN		(1 << 6)
 #define VTP_LOCK		(1 << 7)
-- 
1.7.10.4

[U-Boot] [PATCH V3 2/3] arm/davinci/da850: add uart0 pinmux

[Mikhail Kshevetskiy]

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
---
Change for v3:
 * split DDR and UART bugfixes to separate patch series (series 1/3)
Change for v2:
 * fix checkpatch warnings
---
 arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c   |    5 +++++
 arch/arm/include/asm/arch-davinci/hardware.h    |    1 +
 arch/arm/include/asm/arch-davinci/pinmux_defs.h |    1 +
 3 files changed, 7 insertions(+)

diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
index fa07fb5..dbae5fa 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
@@ -35,6 +35,11 @@ const struct pinmux_config spi1_pins_scs0[] = {
 };
 
 /* UART pin muxer settings */
+const struct pinmux_config uart0_pins_txrx[] = {
+	{ pinmux(3), 2, 4 }, /* UART0_RXD */
+	{ pinmux(3), 2, 5 }, /* UART0_TXD */
+};
+
 const struct pinmux_config uart1_pins_txrx[] = {
 	{ pinmux(4), 2, 6 }, /* UART1_RXD */
 	{ pinmux(4), 2, 7 }, /* UART1_TXD */
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 56e5743..76aca24 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -447,6 +447,7 @@ struct davinci_pllc_regs {
 /* Clock IDs */
 enum davinci_clk_ids {
 	DAVINCI_SPI0_CLKID = 2,
+	DAVINCI_UART0_CLKID = 2,
 	DAVINCI_UART2_CLKID = 2,
 	DAVINCI_MMC_CLKID = 2,
 	DAVINCI_MDIO_CLKID = 4,
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
index 07aceaa..eddb3f7 100644
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
@@ -28,6 +28,7 @@ extern const struct pinmux_config spi1_pins_base[3];
 extern const struct pinmux_config spi1_pins_scs0[1];
 
 /* UART pin muxer settings */
+extern const struct pinmux_config uart0_pins_txrx[2];
 extern const struct pinmux_config uart1_pins_txrx[2];
 extern const struct pinmux_config uart2_pins_txrx[2];
 extern const struct pinmux_config uart2_pins_rtscts[2];
-- 
1.7.10.4

[U-Boot] [PATCH V3 3/3] serial/ns16550: ns16550 has a different register layout on SOC_DA8XX

[Mikhail Kshevetskiy]

also fix NS16550_init() as we need 16x divider

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
---
Change for v3:
 * split DDR and UART bugfixes to separate patch series (series 1/3)
Change for v2:
 * fix checkpatch warnings
---
 drivers/serial/ns16550.c |    2 +-
 include/ns16550.h        |    9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 0c23955..facadd2 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -52,7 +52,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 	serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
 	serial_out(UART_LCRVAL, &com_port->lcr);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
-					defined(CONFIG_AM33XX)
+	defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
 
 #if defined(CONFIG_APTIX)
 	/* /13 mode so Aptix 6MHz can hit 115200 */
diff --git a/include/ns16550.h b/include/ns16550.h
index e9d2eda..51cb5b4 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -46,6 +46,14 @@ struct NS16550 {
 	UART_REG(lsr);		/* 5 */
 	UART_REG(msr);		/* 6 */
 	UART_REG(spr);		/* 7 */
+#ifdef CONFIG_SOC_DA8XX
+	UART_REG(reg8);		/* 8 */
+	UART_REG(reg9);		/* 9 */
+	UART_REG(revid1);	/* A */
+	UART_REG(revid2);	/* B */
+	UART_REG(pwr_mgmt);	/* C */
+	UART_REG(mdr1);		/* D */
+#else
 	UART_REG(mdr1);		/* 8 */
 	UART_REG(reg9);		/* 9 */
 	UART_REG(regA);		/* A */
@@ -58,6 +66,7 @@ struct NS16550 {
 	UART_REG(ssr);		/* 11*/
 	UART_REG(reg12);	/* 12*/
 	UART_REG(osc_12m_sel);	/* 13*/
+#endif
 };
 
 #define thr rbr
-- 
1.7.10.4

[U-Boot] [PATCH V3 3/3] serial/ns16550: ns16550 has a different register layout on SOC_DA8XX

[Sughosh Ganu]

On Mon Jul 09, 2012 at 10:52:43PM +0400, Mikhail Kshevetskiy wrote:
> also fix NS16550_init() as we need 16x divider
> 
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
> Acked-by: Christian Riesch <christian.riesch@omicron.at>
> Tested-by: Christian Riesch <christian.riesch@omicron.at>
> ---
> Change for v3:
>  * split DDR and UART bugfixes to separate patch series (series 1/3)
> Change for v2:
>  * fix checkpatch warnings
> ---
>  drivers/serial/ns16550.c |    2 +-
>  include/ns16550.h        |    9 +++++++++
>  2 files changed, 10 insertions(+), 1 deletion(-)

Tested on hawkboard. Board boots up fine.

Acked-by: Sughosh Ganu <urwithsughosh@gmail.com>
Tested-by: Sughosh Ganu <urwithsughosh@gmail.com>

-sughosh

[U-Boot] [PATCH V3 2/3] arm/davinci/da850: add uart0 pinmux

[Sughosh Ganu]

On Mon Jul 09, 2012 at 10:52:42PM +0400, Mikhail Kshevetskiy wrote:
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
> ---
> Change for v3:
>  * split DDR and UART bugfixes to separate patch series (series 1/3)
> Change for v2:
>  * fix checkpatch warnings
> ---
>  arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c   |    5 +++++
>  arch/arm/include/asm/arch-davinci/hardware.h    |    1 +
>  arch/arm/include/asm/arch-davinci/pinmux_defs.h |    1 +
>  3 files changed, 7 insertions(+)

Tested on hawkboard. Board boots up fine.

Tested-by: Sughosh Ganu <urwithsughosh@gmail.com>

-sughosh