* [PATCH RESEND v2 0/2] Add device tree and clock support for Gscaler.
@ 2012-07-16 5:33 Shaik Ameer Basha
2012-07-16 5:33 ` [PATCH RESEND v2 1/2] ARM: EXYNOS: Add " Shaik Ameer Basha
2012-07-16 5:33 ` [PATCH RESEND v2 2/2] ARM: EXYNOS: Add gscaler device from DT Shaik Ameer Basha
0 siblings, 2 replies; 6+ messages in thread
From: Shaik Ameer Basha @ 2012-07-16 5:33 UTC (permalink / raw)
To: linux-samsung-soc, devicetree-discuss
Cc: kgene.kim, olofj, thomas.ab, sylvester.nawrocki, sachin.kamat,
joshi, ameersk, shaik.ameer
This patch series adds clock support for Gscaler and device node
entries for Gscaler on exynos5.
This patch is based on Kukjin Kim's (linux-samsung) for-next branch.
https://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
changes since v1:
- Addressed review comments from Sylwester Nawrocki
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg11177.html
- Addressed review comments from Sachin Kamat
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg11176.html
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg11178.html
Resending this patch for posting to devicetree-discuss@lists.ozlabs.org
Shaik Ameer Basha (2):
ARM: EXYNOS: Add clock support for Gscaler
ARM: EXYNOS: Add gscaler device from DT
.../devicetree/bindings/media/exynos5-gsc.txt | 16 ++++
arch/arm/boot/dts/exynos5250.dtsi | 31 ++++++++
arch/arm/mach-exynos/clock-exynos5.c | 79 ++++++++++++++++++++
arch/arm/mach-exynos/include/mach/map.h | 3 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 8 ++
5 files changed, 137 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/exynos5-gsc.txt
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH RESEND v2 1/2] ARM: EXYNOS: Add clock support for Gscaler 2012-07-16 5:33 [PATCH RESEND v2 0/2] Add device tree and clock support for Gscaler Shaik Ameer Basha @ 2012-07-16 5:33 ` Shaik Ameer Basha 2012-07-16 22:38 ` Kukjin Kim 2012-07-16 5:33 ` [PATCH RESEND v2 2/2] ARM: EXYNOS: Add gscaler device from DT Shaik Ameer Basha 1 sibling, 1 reply; 6+ messages in thread From: Shaik Ameer Basha @ 2012-07-16 5:33 UTC (permalink / raw) To: linux-samsung-soc, devicetree-discuss Cc: kgene.kim, olofj, thomas.ab, sylvester.nawrocki, sachin.kamat, joshi, ameersk, shaik.ameer Add required clock support for Gscaler for exynos5 Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Prathyush K <prathyush.k@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> --- arch/arm/mach-exynos/clock-exynos5.c | 79 ++++++++++++++++++++++++++++++++++ 1 files changed, 79 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index fefa336..c8293a3 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -741,6 +741,26 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_peric_ctrl, .ctrlbit = (1 << 14), }, { + .name = "gscl", + .devname = "exynos-gsc.0", + .enable = exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "gscl", + .devname = "exynos-gsc.1", + .enable = exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "gscl", + .devname = "exynos-gsc.2", + .enable = exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "gscl", + .devname = "exynos-gsc.3", + .enable = exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 3), + }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), .enable = &exynos5_clk_ip_mfc_ctrl, @@ -1116,6 +1136,61 @@ static struct clksrc_clk exynos5_clksrcs[] = { }, }; +/* For ACLK_300_gscl_mid */ +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = { + .clk = { + .name = "mout_aclk_300_gscl_mid", + }, + .sources = &exynos5_clkset_aclk, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 }, +}; + +/* For ACLK_300_gscl */ +struct clk *exynos5_clkset_aclk_300_gscl_list[] = { + [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk, + [1] = &exynos5_clk_sclk_vpll.clk, +}; + +struct clksrc_sources exynos5_clkset_aclk_300_gscl = { + .sources = exynos5_clkset_aclk_300_gscl_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list), +}; + +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = { + .clk = { + .name = "mout_aclk_300_gscl", + }, + .sources = &exynos5_clkset_aclk_300_gscl, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 }, +}; + +static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = { + .clk = { + .name = "dout_aclk_300_gscl", + .parent = &exynos5_clk_mout_aclk_300_gscl.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 }, +}; + +/* Possible clock sources for aclk_300_gscl_sub Mux */ +static struct clk *clk_src_gscl_300_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &exynos5_clk_dout_aclk_300_gscl.clk, +}; + +static struct clksrc_sources clk_src_gscl_300 = { + .sources = clk_src_gscl_300_list, + .nr_sources = ARRAY_SIZE(clk_src_gscl_300_list), +}; + +static struct clksrc_clk exynos5_clk_aclk_300_gscl = { + .clk = { + .name = "aclk_300_gscl", + }, + .sources = &clk_src_gscl_300, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 }, +}; + /* Clock initialization code */ static struct clksrc_clk *exynos5_sysclks[] = { &exynos5_clk_mout_apll, @@ -1139,6 +1214,10 @@ static struct clksrc_clk *exynos5_sysclks[] = { &exynos5_clk_aclk_266, &exynos5_clk_aclk_200, &exynos5_clk_aclk_166, + &exynos5_clk_aclk_300_gscl, + &exynos5_clk_dout_aclk_300_gscl, + &exynos5_clk_mout_aclk_300_gscl, + &exynos5_clk_mout_aclk_300_gscl_mid, &exynos5_clk_aclk_66_pre, &exynos5_clk_aclk_66, &exynos5_clk_dout_mmc0, -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* RE: [PATCH RESEND v2 1/2] ARM: EXYNOS: Add clock support for Gscaler 2012-07-16 5:33 ` [PATCH RESEND v2 1/2] ARM: EXYNOS: Add " Shaik Ameer Basha @ 2012-07-16 22:38 ` Kukjin Kim 2012-07-18 8:44 ` Sunyoung Kang 0 siblings, 1 reply; 6+ messages in thread From: Kukjin Kim @ 2012-07-16 22:38 UTC (permalink / raw) To: 'Shaik Ameer Basha', linux-samsung-soc, devicetree-discuss Cc: olofj, thomas.ab, sylvester.nawrocki, sachin.kamat, joshi, ameersk, sy0816.kang Shaik Ameer Basha wrote: > > Add required clock support for Gscaler for exynos5 > Hi, Cc'ed Sunyoung Kang who knows gscaler well in my team. > Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> > Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> > Signed-off-by: Prathyush K <prathyush.k@samsung.com> > Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> > --- > arch/arm/mach-exynos/clock-exynos5.c | 79 > ++++++++++++++++++++++++++++++++++ > 1 files changed, 79 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach- > exynos/clock-exynos5.c > index fefa336..c8293a3 100644 > --- a/arch/arm/mach-exynos/clock-exynos5.c > +++ b/arch/arm/mach-exynos/clock-exynos5.c > @@ -741,6 +741,26 @@ static struct clk exynos5_init_clocks_off[] = { > .enable = exynos5_clk_ip_peric_ctrl, > .ctrlbit = (1 << 14), > }, { > + .name = "gscl", > + .devname = "exynos-gsc.0", > + .enable = exynos5_clk_ip_gscl_ctrl, > + .ctrlbit = (1 << 0), Sunyoung, I've seen (1 << 15) | (1 << 0) here instead, which one is right? [snip] I think, following part should be moved between --- static struct clksrc_clk exynos5_clk_aclk_66 = { [snip] }; <<<HERE>>> static struct clk exynos5_init_clocks_off[] = { --- Please don't put your clock code without any checking the clock code. > +/* For ACLK_300_gscl_mid */ > +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = { > + .clk = { > + .name = "mout_aclk_300_gscl_mid", > + }, > + .sources = &exynos5_clkset_aclk, > + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 }, > +}; > + > +/* For ACLK_300_gscl */ > +struct clk *exynos5_clkset_aclk_300_gscl_list[] = { > + [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk, > + [1] = &exynos5_clk_sclk_vpll.clk, As I know, this is wrong. Its [1] should be &exynos5_clk_mout_aclk_300_gscl_mid1.clk > +}; > + > +struct clksrc_sources exynos5_clkset_aclk_300_gscl = { > + .sources = exynos5_clkset_aclk_300_gscl_list, > + .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list), > +}; > + > +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = { > + .clk = { > + .name = "mout_aclk_300_gscl", > + }, > + .sources = &exynos5_clkset_aclk_300_gscl, > + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 }, > +}; > + > +static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = { > + .clk = { > + .name = "dout_aclk_300_gscl", > + .parent = &exynos5_clk_mout_aclk_300_gscl.clk, > + }, > + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 }, > +}; > + > +/* Possible clock sources for aclk_300_gscl_sub Mux */ > +static struct clk *clk_src_gscl_300_list[] = { > + [0] = &clk_ext_xtal_mux, > + [1] = &exynos5_clk_dout_aclk_300_gscl.clk, > +}; > + > +static struct clksrc_sources clk_src_gscl_300 = { > + .sources = clk_src_gscl_300_list, > + .nr_sources = ARRAY_SIZE(clk_src_gscl_300_list), > +}; > + > +static struct clksrc_clk exynos5_clk_aclk_300_gscl = { > + .clk = { > + .name = "aclk_300_gscl", > + }, > + .sources = &clk_src_gscl_300, > + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 }, > +}; > + [snip] Thanks. Best regards, Kgene. -- Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH RESEND v2 1/2] ARM: EXYNOS: Add clock support for Gscaler 2012-07-16 22:38 ` Kukjin Kim @ 2012-07-18 8:44 ` Sunyoung Kang 0 siblings, 0 replies; 6+ messages in thread From: Sunyoung Kang @ 2012-07-18 8:44 UTC (permalink / raw) To: 'Kukjin Kim', 'Shaik Ameer Basha', linux-samsung-soc, devicetree-discuss Cc: olofj, thomas.ab, sylvester.nawrocki, sachin.kamat, joshi, ameersk Kukjin Kim wrote: > >Shaik Ameer Basha wrote: >> >> Add required clock support for Gscaler for exynos5 >> >Hi, > >Cc'ed Sunyoung Kang who knows gscaler well in my team. > >> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> >> Signed-off-by: Prathyush K <prathyush.k@samsung.com> >> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> >> --- >> arch/arm/mach-exynos/clock-exynos5.c | 79 >> ++++++++++++++++++++++++++++++++++ >> 1 files changed, 79 insertions(+), 0 deletions(-) >> >> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach- >> exynos/clock-exynos5.c >> index fefa336..c8293a3 100644 >> --- a/arch/arm/mach-exynos/clock-exynos5.c >> +++ b/arch/arm/mach-exynos/clock-exynos5.c >> @@ -741,6 +741,26 @@ static struct clk exynos5_init_clocks_off[] = { >> .enable = exynos5_clk_ip_peric_ctrl, >> .ctrlbit = (1 << 14), >> }, { >> + .name = "gscl", >> + .devname = "exynos-gsc.0", >> + .enable = exynos5_clk_ip_gscl_ctrl, >> + .ctrlbit = (1 << 0), > >Sunyoung, I've seen (1 << 15) | (1 << 0) here instead, which one is right? > Actually, the ctrl bit, (1 << 0) is correct. The 15th bit Kukjin said is used for another purpose. >[snip] > >I think, following part should be moved between > >--- >static struct clksrc_clk exynos5_clk_aclk_66 = { >[snip] >}; > ><<<HERE>>> > >static struct clk exynos5_init_clocks_off[] = { >--- > >Please don't put your clock code without any checking the clock code. > > >> +/* For ACLK_300_gscl_mid */ >> +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = { >> + .clk = { >> + .name = "mout_aclk_300_gscl_mid", >> + }, >> + .sources = &exynos5_clkset_aclk, >> + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 }, >> +}; >> + >> +/* For ACLK_300_gscl */ >> +struct clk *exynos5_clkset_aclk_300_gscl_list[] = { >> + [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk, >> + [1] = &exynos5_clk_sclk_vpll.clk, > >As I know, this is wrong. Its [1] should be >&exynos5_clk_mout_aclk_300_gscl_mid1.clk > Yes, right. It should be 'exynos5_clk_mout_aclk_300_gscl_mid1.clk' which is generated by CPLL. The VPLL shouldn't be used here. It means you need to implement CPLL for gscaler. As a note, CPLL can be used for fimd as well. [snip] Thanks. BRs Sunyoung ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH RESEND v2 2/2] ARM: EXYNOS: Add gscaler device from DT 2012-07-16 5:33 [PATCH RESEND v2 0/2] Add device tree and clock support for Gscaler Shaik Ameer Basha 2012-07-16 5:33 ` [PATCH RESEND v2 1/2] ARM: EXYNOS: Add " Shaik Ameer Basha @ 2012-07-16 5:33 ` Shaik Ameer Basha 2012-07-16 20:33 ` Sylwester Nawrocki 1 sibling, 1 reply; 6+ messages in thread From: Shaik Ameer Basha @ 2012-07-16 5:33 UTC (permalink / raw) To: linux-samsung-soc, devicetree-discuss Cc: kgene.kim, olofj, thomas.ab, sylvester.nawrocki, sachin.kamat, joshi, ameersk, shaik.ameer This patch adds, - 4 Gscaler devices to the DT device list - Gscaler specific entries to the machine file - binding documentation for Gscaler entries Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> --- .../devicetree/bindings/media/exynos5-gsc.txt | 16 ++++++++++ arch/arm/boot/dts/exynos5250.dtsi | 31 ++++++++++++++++++++ arch/arm/mach-exynos/include/mach/map.h | 3 ++ arch/arm/mach-exynos/mach-exynos5-dt.c | 8 +++++ 4 files changed, 58 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/exynos5-gsc.txt diff --git a/Documentation/devicetree/bindings/media/exynos5-gsc.txt b/Documentation/devicetree/bindings/media/exynos5-gsc.txt new file mode 100644 index 0000000..f743c60 --- /dev/null +++ b/Documentation/devicetree/bindings/media/exynos5-gsc.txt @@ -0,0 +1,16 @@ +* Samsung Exynos5 Gscaler device + +Gscaler is used for scaling and color space conversion on EXYNOS5 SoCs. + +Required properties: +- compatible: should be "samsung,exynos-gsc" +- reg: should contian Gsaler physical address location and length. +- interrupts: should contain Gscaler interrupt number + +Example: + +gsc_0: gsc@0x13e00000 { + compatible = "samsung,exynos-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = <0 85 0>; +}; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 4272b29..b945c00 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -23,6 +23,13 @@ compatible = "samsung,exynos5250"; interrupt-parent = <&gic>; + aliases { + gsc0 = &gsc_0; + gsc1 = &gsc_1; + gsc2 = &gsc_2; + gsc3 = &gsc_3; + }; + gic:interrupt-controller@10481000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -424,4 +431,28 @@ #gpio-cells = <4>; }; }; + + gsc_0: gsc@0x13e00000 { + compatible = "samsung,exynos-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = <0 85 0>; + }; + + gsc_1: gsc@0x13e10000 { + compatible = "samsung,exynos-gsc"; + reg = <0x13e10000 0x1000>; + interrupts = <0 86 0>; + }; + + gsc_2: gsc@0x13e20000 { + compatible = "samsung,exynos-gsc"; + reg = <0x13e20000 0x1000>; + interrupts = <0 87 0>; + }; + + gsc_3: gsc@0x13e30000 { + compatible = "samsung,exynos-gsc"; + reg = <0x13e30000 0x1000>; + interrupts = <0 88 0>; + }; }; diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index ca4aa89..e68d249 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -121,6 +121,9 @@ #define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 #define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 +/* x = 0...3 */ +#define EXYNOS5_PA_GSC(x) (0x13e00000 + ((x) * 0x10000)) + #define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000 #define EXYNOS5_PA_SYSMMU_SSS 0x10A50000 #define EXYNOS5_PA_SYSMMU_2D 0x10A60000 diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 7b1e11a..9eb83b6 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -50,6 +50,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), + OF_DEV_AUXDATA("samsung,exynos-gsc", EXYNOS5_PA_GSC(0), + "exynos-gsc.0", NULL), + OF_DEV_AUXDATA("samsung,exynos-gsc", EXYNOS5_PA_GSC(1), + "exynos-gsc.1", NULL), + OF_DEV_AUXDATA("samsung,exynos-gsc", EXYNOS5_PA_GSC(2), + "exynos-gsc.2", NULL), + OF_DEV_AUXDATA("samsung,exynos-gsc", EXYNOS5_PA_GSC(3), + "exynos-gsc.3", NULL), {}, }; -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH RESEND v2 2/2] ARM: EXYNOS: Add gscaler device from DT 2012-07-16 5:33 ` [PATCH RESEND v2 2/2] ARM: EXYNOS: Add gscaler device from DT Shaik Ameer Basha @ 2012-07-16 20:33 ` Sylwester Nawrocki 0 siblings, 0 replies; 6+ messages in thread From: Sylwester Nawrocki @ 2012-07-16 20:33 UTC (permalink / raw) To: Shaik Ameer Basha Cc: linux-samsung-soc, devicetree-discuss, kgene.kim, olofj, thomas.ab, sylvester.nawrocki, sachin.kamat, joshi, ameersk Hi Shaik, On 07/16/2012 07:33 AM, Shaik Ameer Basha wrote: > +++ b/Documentation/devicetree/bindings/media/exynos5-gsc.txt > @@ -0,0 +1,16 @@ > +* Samsung Exynos5 Gscaler device > + > +Gscaler is used for scaling and color space conversion on EXYNOS5 SoCs. > + > +Required properties: > +- compatible: should be "samsung,exynos-gsc" Shouldn't there rather be a specific "compatible" property for each SoC, e.g. - compatible: should be one of: "samsung5250,exynos-gsc", "samsung5450,exynos-gsc", etc. ? > +- reg: should contian Gsaler physical address location and length. contian -> contain, Gsaler -> Gscaler > +- interrupts: should contain Gscaler interrupt number > + > +Example: > + > +gsc_0: gsc@0x13e00000 { > + compatible = "samsung,exynos-gsc"; compatible = "samsung5250,exynos-gsc"; > + reg =<0x13e00000 0x1000>; > + interrupts =<0 85 0>; > +}; The aliases are still undocumented. How about adding something along the lines of: "Each Gscaler node should have a numbered alias in the aliases node, in the form of gscN, N = 0...3." ? > diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi > index 4272b29..b945c00 100644 > --- a/arch/arm/boot/dts/exynos5250.dtsi > +++ b/arch/arm/boot/dts/exynos5250.dtsi > @@ -23,6 +23,13 @@ > compatible = "samsung,exynos5250"; > interrupt-parent =<&gic>; > > + aliases { > + gsc0 =&gsc_0; > + gsc1 =&gsc_1; > + gsc2 =&gsc_2; > + gsc3 =&gsc_3; > + }; > + > gic:interrupt-controller@10481000 { > compatible = "arm,cortex-a9-gic"; > #interrupt-cells =<3>; -- Regards, Sylwester ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-07-18 8:44 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-07-16 5:33 [PATCH RESEND v2 0/2] Add device tree and clock support for Gscaler Shaik Ameer Basha 2012-07-16 5:33 ` [PATCH RESEND v2 1/2] ARM: EXYNOS: Add " Shaik Ameer Basha 2012-07-16 22:38 ` Kukjin Kim 2012-07-18 8:44 ` Sunyoung Kang 2012-07-16 5:33 ` [PATCH RESEND v2 2/2] ARM: EXYNOS: Add gscaler device from DT Shaik Ameer Basha 2012-07-16 20:33 ` Sylwester Nawrocki
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