* [PATCH 0/8] EXYNOS5: USB: Add USB 2.0 and USB 3.0 support for exynos5
@ 2012-07-18 13:45 ` Vivek Gautam
0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski
Cc: a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov, joshi, olofj,
prashanth.g
This patchset adds arch support for USB 2.0(EHCI and OHCI)
and USB 3.0(DWC3) on exynos5.
Below patch modifies few functions to enable supporting
exynos5 later.
EXYNOS4: USB: Generalising setup-usb-phy driver for exynos
Based and tested on 'for-next' branch.
Ajay Kumar (2):
ARM: EXYNOS5: Add machine data for USB 2.0
ARM: EXYNOS5: Add OHCI device from device tree
Vivek Gautam (6):
EXYNOS4: USB: Generalising setup-usb-phy driver for exynos
ARM: EXYNOS5: Add EHCI device from device tree
ARM: EXYNOS5: Add PHY initialization code for usb 2.0
ARM: EXYNOS5: Add machine data for USB3.0
ARM: EXYNOS5: Add XHCI device from device tree
ARM: EXYNOS5: Add PHY initialization code for usb 3.0
.../devicetree/bindings/usb/exynos-usb.txt | 60 +++
arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 +
arch/arm/boot/dts/exynos5250.dtsi | 18 +
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/clock-exynos5.c | 24 ++
arch/arm/mach-exynos/common.c | 10 +
arch/arm/mach-exynos/include/mach/map.h | 3 +
arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 +
arch/arm/mach-exynos/include/mach/regs-usb-phy.h | 86 ++++
arch/arm/mach-exynos/mach-exynos5-dt.c | 26 ++
arch/arm/mach-exynos/setup-usb-phy.c | 413 ++++++++++++++++++--
arch/arm/plat-samsung/include/plat/map-s5p.h | 2 +
.../include/plat/regs-usb3-exynos-drd-phy.h | 75 ++++
arch/arm/plat-samsung/include/plat/usb-phy.h | 1 +
drivers/usb/Kconfig | 1 +
15 files changed, 695 insertions(+), 33 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/exynos-usb.txt
create mode 100644 arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 0/8] EXYNOS5: USB: Add USB 2.0 and USB 3.0 support for exynos5
@ 2012-07-18 13:45 ` Vivek Gautam
0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds arch support for USB 2.0(EHCI and OHCI)
and USB 3.0(DWC3) on exynos5.
Below patch modifies few functions to enable supporting
exynos5 later.
EXYNOS4: USB: Generalising setup-usb-phy driver for exynos
Based and tested on 'for-next' branch.
Ajay Kumar (2):
ARM: EXYNOS5: Add machine data for USB 2.0
ARM: EXYNOS5: Add OHCI device from device tree
Vivek Gautam (6):
EXYNOS4: USB: Generalising setup-usb-phy driver for exynos
ARM: EXYNOS5: Add EHCI device from device tree
ARM: EXYNOS5: Add PHY initialization code for usb 2.0
ARM: EXYNOS5: Add machine data for USB3.0
ARM: EXYNOS5: Add XHCI device from device tree
ARM: EXYNOS5: Add PHY initialization code for usb 3.0
.../devicetree/bindings/usb/exynos-usb.txt | 60 +++
arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 +
arch/arm/boot/dts/exynos5250.dtsi | 18 +
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/clock-exynos5.c | 24 ++
arch/arm/mach-exynos/common.c | 10 +
arch/arm/mach-exynos/include/mach/map.h | 3 +
arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 +
arch/arm/mach-exynos/include/mach/regs-usb-phy.h | 86 ++++
arch/arm/mach-exynos/mach-exynos5-dt.c | 26 ++
arch/arm/mach-exynos/setup-usb-phy.c | 413 ++++++++++++++++++--
arch/arm/plat-samsung/include/plat/map-s5p.h | 2 +
.../include/plat/regs-usb3-exynos-drd-phy.h | 75 ++++
arch/arm/plat-samsung/include/plat/usb-phy.h | 1 +
drivers/usb/Kconfig | 1 +
15 files changed, 695 insertions(+), 33 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/exynos-usb.txt
create mode 100644 arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/8] EXYNOS4: USB: Generalising setup-usb-phy driver for exynos
2012-07-18 13:45 ` Vivek Gautam
@ 2012-07-18 13:45 ` Vivek Gautam
-1 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski
Cc: a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov, joshi, olofj,
prashanth.g
This patch updates the setup-usb-phy in order to accomodate
exynos5 support later.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index b81cc56..bfc1367 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -26,10 +26,31 @@ static int exynos4_usb_host_phy_is_on(void)
return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
}
-static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
+struct clk *exynos_usb_clock_enable(struct platform_device *pdev)
+{
+ struct clk *usb_clk = NULL;
+ int err = 0;
+
+ if (!usb_clk) {
+ usb_clk = clk_get(&pdev->dev, "otg");
+ if (IS_ERR(usb_clk)) {
+ dev_err(&pdev->dev, "Failed to get otg clock\n");
+ return NULL;
+ }
+
+ err = clk_enable(usb_clk);
+ if (err) {
+ clk_put(usb_clk);
+ return NULL;
+ }
+ }
+ return usb_clk;
+}
+
+static int exynos4210_usb_phy_clkset(struct platform_device *pdev)
{
struct clk *xusbxti_clk;
- u32 phyclk;
+ u32 phyclk = 0;
xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
@@ -80,6 +101,7 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
}
clk_put(xusbxti_clk);
}
+ return phyclk;
}
static int exynos4210_usb_phy0_init(struct platform_device *pdev)
@@ -120,21 +142,12 @@ static int exynos4210_usb_phy1_init(struct platform_device *pdev)
{
struct clk *otg_clk;
u32 rstcon;
- int err;
atomic_inc(&host_usage);
- otg_clk = clk_get(&pdev->dev, "otg");
- if (IS_ERR(otg_clk)) {
- dev_err(&pdev->dev, "Failed to get otg clock\n");
- return PTR_ERR(otg_clk);
- }
-
- err = clk_enable(otg_clk);
- if (err) {
- clk_put(otg_clk);
- return err;
- }
+ otg_clk = exynos_usb_clock_enable(pdev);
+ if (otg_clk == NULL)
+ dev_err(&pdev->dev, "Failed to enable otg clock\n");
if (exynos4_usb_host_phy_is_on())
return 0;
@@ -173,22 +186,13 @@ static int exynos4210_usb_phy1_init(struct platform_device *pdev)
static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
{
struct clk *otg_clk;
- int err;
if (atomic_dec_return(&host_usage) > 0)
return 0;
- otg_clk = clk_get(&pdev->dev, "otg");
- if (IS_ERR(otg_clk)) {
- dev_err(&pdev->dev, "Failed to get otg clock\n");
- return PTR_ERR(otg_clk);
- }
-
- err = clk_enable(otg_clk);
- if (err) {
- clk_put(otg_clk);
- return err;
- }
+ otg_clk = exynos_usb_clock_enable(pdev);
+ if (otg_clk == NULL)
+ dev_err(&pdev->dev, "Failed to enable otg clock\n");
writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
EXYNOS4_PHYPWR);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 1/8] EXYNOS4: USB: Generalising setup-usb-phy driver for exynos
@ 2012-07-18 13:45 ` Vivek Gautam
0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the setup-usb-phy in order to accomodate
exynos5 support later.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index b81cc56..bfc1367 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -26,10 +26,31 @@ static int exynos4_usb_host_phy_is_on(void)
return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
}
-static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
+struct clk *exynos_usb_clock_enable(struct platform_device *pdev)
+{
+ struct clk *usb_clk = NULL;
+ int err = 0;
+
+ if (!usb_clk) {
+ usb_clk = clk_get(&pdev->dev, "otg");
+ if (IS_ERR(usb_clk)) {
+ dev_err(&pdev->dev, "Failed to get otg clock\n");
+ return NULL;
+ }
+
+ err = clk_enable(usb_clk);
+ if (err) {
+ clk_put(usb_clk);
+ return NULL;
+ }
+ }
+ return usb_clk;
+}
+
+static int exynos4210_usb_phy_clkset(struct platform_device *pdev)
{
struct clk *xusbxti_clk;
- u32 phyclk;
+ u32 phyclk = 0;
xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
@@ -80,6 +101,7 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
}
clk_put(xusbxti_clk);
}
+ return phyclk;
}
static int exynos4210_usb_phy0_init(struct platform_device *pdev)
@@ -120,21 +142,12 @@ static int exynos4210_usb_phy1_init(struct platform_device *pdev)
{
struct clk *otg_clk;
u32 rstcon;
- int err;
atomic_inc(&host_usage);
- otg_clk = clk_get(&pdev->dev, "otg");
- if (IS_ERR(otg_clk)) {
- dev_err(&pdev->dev, "Failed to get otg clock\n");
- return PTR_ERR(otg_clk);
- }
-
- err = clk_enable(otg_clk);
- if (err) {
- clk_put(otg_clk);
- return err;
- }
+ otg_clk = exynos_usb_clock_enable(pdev);
+ if (otg_clk == NULL)
+ dev_err(&pdev->dev, "Failed to enable otg clock\n");
if (exynos4_usb_host_phy_is_on())
return 0;
@@ -173,22 +186,13 @@ static int exynos4210_usb_phy1_init(struct platform_device *pdev)
static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
{
struct clk *otg_clk;
- int err;
if (atomic_dec_return(&host_usage) > 0)
return 0;
- otg_clk = clk_get(&pdev->dev, "otg");
- if (IS_ERR(otg_clk)) {
- dev_err(&pdev->dev, "Failed to get otg clock\n");
- return PTR_ERR(otg_clk);
- }
-
- err = clk_enable(otg_clk);
- if (err) {
- clk_put(otg_clk);
- return err;
- }
+ otg_clk = exynos_usb_clock_enable(pdev);
+ if (otg_clk == NULL)
+ dev_err(&pdev->dev, "Failed to enable otg clock\n");
writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
EXYNOS4_PHYPWR);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/8] ARM: EXYNOS5: Add machine data for USB 2.0
2012-07-18 13:45 ` Vivek Gautam
@ 2012-07-18 13:45 ` Vivek Gautam
-1 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski
Cc: a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov, joshi, olofj,
prashanth.g, Ajay Kumar
From: Ajay Kumar <ajaykumar.rs@samsung.com>
This patch adds address mapping of USB 2.0 PHY for exynos5
Signed-off-by: Banajit Goswami <banajit.g@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..92d5e61 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -275,6 +275,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
.length = SZ_4K,
.type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C_VA_USB_HSPHY,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_USB_PHY),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
},
};
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..331ae57 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -192,6 +192,8 @@
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS5_PA_UART 0x12C00000
+#define EXYNOS5_PA_USB_PHY 0x12130000
+
#define EXYNOS4_PA_VP 0x12C00000
#define EXYNOS4_PA_MIXER 0x12C10000
#define EXYNOS4_PA_SDO 0x12C20000
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/8] ARM: EXYNOS5: Add machine data for USB 2.0
@ 2012-07-18 13:45 ` Vivek Gautam
0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: linux-arm-kernel
From: Ajay Kumar <ajaykumar.rs@samsung.com>
This patch adds address mapping of USB 2.0 PHY for exynos5
Signed-off-by: Banajit Goswami <banajit.g@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..92d5e61 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -275,6 +275,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
.length = SZ_4K,
.type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C_VA_USB_HSPHY,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_USB_PHY),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
},
};
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..331ae57 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -192,6 +192,8 @@
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS5_PA_UART 0x12C00000
+#define EXYNOS5_PA_USB_PHY 0x12130000
+
#define EXYNOS4_PA_VP 0x12C00000
#define EXYNOS4_PA_MIXER 0x12C10000
#define EXYNOS4_PA_SDO 0x12C20000
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/8] ARM: EXYNOS5: Add OHCI device from device tree
2012-07-18 13:45 ` Vivek Gautam
@ 2012-07-18 13:45 ` Vivek Gautam
-1 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski
Cc: a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov, joshi, olofj,
prashanth.g, Ajay Kumar
From: Ajay Kumar <ajaykumar.rs@samsung.com>
This patch adds OHCI device from device tree for exynos5
and adds platform data.
Signed-off-by: Banajit Goswami <banajit.g@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
new file mode 100644
index 0000000..63b80b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -0,0 +1,19 @@
+Samsung Exynos SoC USB controller
+
+The device node for USB controller for Samsung SOC have
+following properties
+
+OHCI
+Required properties:
+ - compatible: should be "samsung,exynos-ohci" for USB 2.0
+ OHCI companion controller in host mode.
+ - reg: physical base address of the controller and length
+ of memory mapped.
+ - interrupts: interrupt number to the cpu.
+
+ohci {
+ compatible = "samsung,exynos-ohci";
+ reg = <0x12120000 0x100>;
+ interrupts = <0 71 0>;
+};
+
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index a3a2eb2..3c73d15 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,6 +58,12 @@
interrupts = <0 42 0>;
};
+ ohci {
+ compatible = "samsung,exynos-ohci";
+ reg = <0x12120000 0x100>;
+ interrupts = <0 71 0>;
+ };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc..39a4b34 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -15,12 +15,19 @@
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <mach/map.h>
+#include <mach/ohci.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
+#include <plat/usb-phy.h>
#include "common.h"
+static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
+ .phy_init = s5p_usb_phy_init,
+ .phy_exit = s5p_usb_phy_exit,
+};
+
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -56,6 +63,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
+ "exynos-ohci", &smdk5250_ohci_pdata),
{},
};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/8] ARM: EXYNOS5: Add OHCI device from device tree
@ 2012-07-18 13:45 ` Vivek Gautam
0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: linux-arm-kernel
From: Ajay Kumar <ajaykumar.rs@samsung.com>
This patch adds OHCI device from device tree for exynos5
and adds platform data.
Signed-off-by: Banajit Goswami <banajit.g@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
new file mode 100644
index 0000000..63b80b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -0,0 +1,19 @@
+Samsung Exynos SoC USB controller
+
+The device node for USB controller for Samsung SOC have
+following properties
+
+OHCI
+Required properties:
+ - compatible: should be "samsung,exynos-ohci" for USB 2.0
+ OHCI companion controller in host mode.
+ - reg: physical base address of the controller and length
+ of memory mapped.
+ - interrupts: interrupt number to the cpu.
+
+ohci {
+ compatible = "samsung,exynos-ohci";
+ reg = <0x12120000 0x100>;
+ interrupts = <0 71 0>;
+};
+
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index a3a2eb2..3c73d15 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,6 +58,12 @@
interrupts = <0 42 0>;
};
+ ohci {
+ compatible = "samsung,exynos-ohci";
+ reg = <0x12120000 0x100>;
+ interrupts = <0 71 0>;
+ };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc..39a4b34 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -15,12 +15,19 @@
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <mach/map.h>
+#include <mach/ohci.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
+#include <plat/usb-phy.h>
#include "common.h"
+static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
+ .phy_init = s5p_usb_phy_init,
+ .phy_exit = s5p_usb_phy_exit,
+};
+
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -56,6 +63,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
+ "exynos-ohci", &smdk5250_ohci_pdata),
{},
};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/8] ARM: EXYNOS5: Add EHCI device from device tree
2012-07-18 13:45 ` Vivek Gautam
@ 2012-07-18 13:45 ` Vivek Gautam
-1 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski
Cc: a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov, joshi, olofj,
prashanth.g
This patch adds EHCI device from device tree for exynos5
and adds platform data.
Signed-off-by: Banajit Goswami <banajit.g@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index 63b80b9..45dadca 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -17,3 +17,25 @@ ohci {
interrupts = <0 71 0>;
};
+EHCI
+Required properties:
+ - compatible: should be "samsung,exynos-ehci" for USB 2.0
+ EHCI controller in host mode.
+ - reg: physical base address of the controller and length
+ of memory mapped.
+ - interrupts: interrupt number to the cpu.
+
+Optional properties:
+ - samsung,vbus-gpio: if present, specifies the GPIO
+ that needs to be pulled up for the bus to be powered.
+
+ehci {
+ compatible = "samsung,exynos-ehci";
+ reg = <0x12110000 0x100>;
+ interrupts = <0 71 0>;
+};
+
+ehci {
+ samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+};
+
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..bf18286 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -109,4 +109,8 @@
spi_2: spi@12d40000 {
status = "disabled";
};
+
+ ehci {
+ samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 3c73d15..988f52a 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -64,6 +64,12 @@
interrupts = <0 71 0>;
};
+ ehci {
+ compatible = "samsung,exynos-ehci";
+ reg = <0x12110000 0x100>;
+ interrupts = <0 71 0>;
+ };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 39a4b34..0cc626e 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -20,6 +20,7 @@
#include <plat/cpu.h>
#include <plat/regs-serial.h>
#include <plat/usb-phy.h>
+#include <plat/ehci.h>
#include "common.h"
@@ -28,6 +29,11 @@ static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
.phy_exit = s5p_usb_phy_exit,
};
+static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
+ .phy_init = s5p_usb_phy_init,
+ .phy_exit = s5p_usb_phy_exit,
+};
+
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -65,6 +71,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
"exynos-ohci", &smdk5250_ohci_pdata),
+ OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
+ "s5p-ehci", &smdk5250_ehci_pdata),
{},
};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/8] ARM: EXYNOS5: Add EHCI device from device tree
@ 2012-07-18 13:45 ` Vivek Gautam
0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds EHCI device from device tree for exynos5
and adds platform data.
Signed-off-by: Banajit Goswami <banajit.g@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index 63b80b9..45dadca 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -17,3 +17,25 @@ ohci {
interrupts = <0 71 0>;
};
+EHCI
+Required properties:
+ - compatible: should be "samsung,exynos-ehci" for USB 2.0
+ EHCI controller in host mode.
+ - reg: physical base address of the controller and length
+ of memory mapped.
+ - interrupts: interrupt number to the cpu.
+
+Optional properties:
+ - samsung,vbus-gpio: if present, specifies the GPIO
+ that needs to be pulled up for the bus to be powered.
+
+ehci {
+ compatible = "samsung,exynos-ehci";
+ reg = <0x12110000 0x100>;
+ interrupts = <0 71 0>;
+};
+
+ehci {
+ samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+};
+
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..bf18286 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -109,4 +109,8 @@
spi_2: spi at 12d40000 {
status = "disabled";
};
+
+ ehci {
+ samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 3c73d15..988f52a 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -64,6 +64,12 @@
interrupts = <0 71 0>;
};
+ ehci {
+ compatible = "samsung,exynos-ehci";
+ reg = <0x12110000 0x100>;
+ interrupts = <0 71 0>;
+ };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 39a4b34..0cc626e 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -20,6 +20,7 @@
#include <plat/cpu.h>
#include <plat/regs-serial.h>
#include <plat/usb-phy.h>
+#include <plat/ehci.h>
#include "common.h"
@@ -28,6 +29,11 @@ static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
.phy_exit = s5p_usb_phy_exit,
};
+static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
+ .phy_init = s5p_usb_phy_init,
+ .phy_exit = s5p_usb_phy_exit,
+};
+
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -65,6 +71,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
"exynos-ohci", &smdk5250_ohci_pdata),
+ OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
+ "s5p-ehci", &smdk5250_ehci_pdata),
{},
};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 5/8] ARM: EXYNOS5: Add PHY initialization code for usb 2.0
2012-07-18 13:45 ` Vivek Gautam
@ 2012-07-18 13:45 ` Vivek Gautam
-1 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski
Cc: a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov, joshi, olofj,
prashanth.g
This patch adds PHY setup functions usb 2.0 support on exynos5
Signed-off-by: Yulgon Kim <yulgon.kim@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e698ca0..e0bc441 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -416,6 +416,7 @@ config MACH_EXYNOS5_DT
select SOC_EXYNOS5250
select USE_OF
select ARM_AMBA
+ select EXYNOS4_SETUP_USB_PHY
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS4 SoC based board.
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
index 0727773..2df4bd7 100644
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -13,6 +13,7 @@
#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
+/* Exynos 4 */
#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
#define PHY1_HSIC1_SLEEP (1 << 12)
@@ -71,4 +72,89 @@
#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
#define FPENABLEN (1 << 0)
+/* Exynos 5 */
+#define EXYNOS5_PHY_HOST_CTRL0 EXYNOS4_HSOTG_PHYREG(0x00)
+#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31)
+
+#define HOST_CTRL0_REFCLKSEL_XTAL (0x0)
+#define HOST_CTRL0_REFCLKSEL_EXTL (0x1)
+#define HOST_CTRL0_REFCLKSEL_CLK_CORE (0x2)
+#define HOST_CTRL0_REFCLKSEL_MASK (0x3)
+#define HOST_CTRL0_REFCLKSEL_SHIFT (19)
+
+#define EXYNOS5_CLKSEL_50M (0x7)
+#define EXYNOS5_CLKSEL_24M (0x5)
+#define EXYNOS5_CLKSEL_20M (0x4)
+#define EXYNOS5_CLKSEL_19200K (0x3)
+#define EXYNOS5_CLKSEL_12M (0x2)
+#define EXYNOS5_CLKSEL_10M (0x1)
+#define EXYNOS5_CLKSEL_9600K (0x0)
+#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
+#define HOST_CTRL0_CLKSEL_SHIFT (16)
+
+#define HOST_CTRL0_COMMONON_N (0x1 << 9)
+#define HOST_CTRL0_SIDDQ (0x1 << 6)
+#define HOST_CTRL0_FORCESLEEP (0x1 << 5)
+#define HOST_CTRL0_FORCESUSPEND (0x1 << 4)
+#define HOST_CTRL0_WORDINTERFACE (0x1 << 3)
+#define HOST_CTRL0_UTMISWRST (0x1 << 2)
+#define HOST_CTRL0_LINKSWRST (0x1 << 1)
+#define HOST_CTRL0_PHYSWRST (0x1 << 0)
+
+#define EXYNOS5_PHY_HOST_TUNE0 EXYNOS4_HSOTG_PHYREG(0x04)
+#define EXYNOS5_PHY_HOST_TEST0 EXYNOS4_HSOTG_PHYREG(0x08)
+
+#define EXYNOS5_PHY_HSIC_CTRL1 EXYNOS4_HSOTG_PHYREG(0x10)
+#define EXYNOS5_PHY_HSIC_CTRL2 EXYNOS4_HSOTG_PHYREG(0x20)
+#define HSIC_CTRL_REFCLKSEL (0x2)
+#define HSIC_CTRL_REFCLKSEL_MASK (0x3)
+#define HSIC_CTRL_REFCLKSEL_SHIFT (23)
+
+#define HSIC_CTRL_REFCLKDIV_12 (0x24)
+#define HSIC_CTRL_REFCLKDIV_15 (0x1C)
+#define HSIC_CTRL_REFCLKDIV_16 (0x1A)
+#define HSIC_CTRL_REFCLKDIV_19_2 (0x15)
+#define HSIC_CTRL_REFCLKDIV_20 (0x14)
+#define HSIC_CTRL_REFCLKDIV_MASK (0x7f)
+#define HSIC_CTRL_REFCLKDIV_SHIFT (16)
+
+#define HSIC_CTRL_SIDDQ (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
+#define HSIC_CTRL_WORDINTERFACE (0x1 << 3)
+#define HSIC_CTRL_UTMISWRST (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST (0x1 << 0)
+
+#define EXYNOS5_PHY_HOST_EHCICTRL EXYNOS4_HSOTG_PHYREG(0x30)
+#define EHCICTRL_ENAINCRXALIGN (0x1 << 29)
+#define EHCICTRL_ENAINCR4 (0x1 << 28)
+#define EHCICTRL_ENAINCR8 (0x1 << 27)
+#define EHCICTRL_ENAINCR16 (0x1 << 26)
+
+#define EXYNOS5_PHY_HOST_OHCICTRL EXYNOS4_HSOTG_PHYREG(0x34)
+#define OHCICTRL_SUSPLGCY (0x1 << 3)
+#define OHCICTRL_APPSTARTCLK (0x1 << 2)
+#define OHCICTRL_CNTSEL (0x1 << 1)
+#define OHCICTRL_CLKCKTRST (0x1 << 0)
+
+#define EXYNOS5_PHY_OTG_SYS EXYNOS4_HSOTG_PHYREG(0x38)
+#define OTG_SYS_PHYLINK_SW_RESET (0x1 << 14)
+#define OTG_SYS_LINK_SW_RST_UOTG (0x1 << 13)
+#define OTG_SYS_PHY0_SW_RST (0x1 << 12)
+
+#define OTG_SYS_REF_CLK_SEL_XTAL (0x0)
+#define OTG_SYS_REF_CLK_SEL_EXTL (0x1)
+#define OTG_SYS_REF_CLK_SEL_CLKCORE (0x2)
+#define OTG_SYS_REF_CLK_SEL_MASK (0x3)
+#define OTG_SYS_REF_CLK_SEL_SHIFT (9)
+
+#define OTG_SYS_IP_PULLUP_UOTG (0x1 << 8)
+#define OTG_SYS_COMMON_ON (0x1 << 7)
+#define OTG_SYS_CLKSEL_SHIFT (4)
+#define OTG_SYS_CTRL0_FSEL_MASK (0x7 << 4)
+#define OTG_SYS_FORCE_SLEEP (0x1 << 3)
+#define OTG_SYS_OTGDISABLE (0x1 << 2)
+#define OTG_SYS_SIDDQ_UOTG (0x1 << 1)
+#define OTG_SYS_FORCE_SUSPEND (0x1 << 0)
+
#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index bfc1367..3f7a26a 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -19,11 +19,36 @@
#include <plat/cpu.h>
#include <plat/usb-phy.h>
+#define PHY_ENABLE 1
+#define PHY_DISABLE 0
+
+enum usb_phy_type {
+ USB_PHY = (0x1 << 0),
+};
+
static atomic_t host_usage;
static int exynos4_usb_host_phy_is_on(void)
{
- return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
+ if (soc_is_exynos5250()) {
+ return (readl(EXYNOS5_PHY_HOST_CTRL0) &
+ HOST_CTRL0_PHYSWRSTALL) ? 0 : 1;
+ } else {
+ return (readl(EXYNOS4_PHYPWR) &
+ PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
+ }
+}
+
+static void exynos_usb_mux_change(struct platform_device *pdev, int val)
+{
+ u32 is_host;
+ if (soc_is_exynos5250()) {
+ is_host = readl(EXYNOS5_USB_CFG);
+ writel(val, EXYNOS5_USB_CFG);
+ }
+ if (is_host != val)
+ dev_dbg(&pdev->dev, "Change USB MUX from %s to %s",
+ is_host ? "Host" : "Device", val ? "Host" : "Device");
}
struct clk *exynos_usb_clock_enable(struct platform_device *pdev)
@@ -32,7 +57,10 @@ struct clk *exynos_usb_clock_enable(struct platform_device *pdev)
int err = 0;
if (!usb_clk) {
- usb_clk = clk_get(&pdev->dev, "otg");
+ if (soc_is_exynos5250())
+ usb_clk = clk_get(&pdev->dev, "usbhost");
+ else
+ usb_clk = clk_get(&pdev->dev, "otg");
if (IS_ERR(usb_clk)) {
dev_err(&pdev->dev, "Failed to get otg clock\n");
return NULL;
@@ -52,7 +80,11 @@ static int exynos4210_usb_phy_clkset(struct platform_device *pdev)
struct clk *xusbxti_clk;
u32 phyclk = 0;
- xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
+ if (soc_is_exynos5250())
+ xusbxti_clk = clk_get(&pdev->dev, "ext_xtal");
+ else
+ xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
+
if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
if (soc_is_exynos4210()) {
/* set clock frequency for PLL */
@@ -98,12 +130,47 @@ static int exynos4210_usb_phy_clkset(struct platform_device *pdev)
break;
}
writel(phyclk, EXYNOS4_PHYCLK);
+ } else if (soc_is_exynos5250()) {
+ /* set clock frequency for PLL */
+ switch (clk_get_rate(xusbxti_clk)) {
+ case 96 * 100000:
+ phyclk |= EXYNOS5_CLKSEL_9600K;
+ break;
+ case 10 * MHZ:
+ phyclk |= EXYNOS5_CLKSEL_10M;
+ break;
+ case 12 * MHZ:
+ phyclk |= EXYNOS5_CLKSEL_12M;
+ break;
+ case 192 * 100000:
+ phyclk |= EXYNOS5_CLKSEL_19200K;
+ break;
+ case 20 * MHZ:
+ phyclk |= EXYNOS5_CLKSEL_20M;
+ break;
+ case 50 * MHZ:
+ phyclk |= EXYNOS5_CLKSEL_50M;
+ break;
+ case 24 * MHZ:
+ default:
+ /* default reference clock */
+ phyclk |= EXYNOS5_CLKSEL_24M;
+ break;
+ }
}
clk_put(xusbxti_clk);
}
return phyclk;
}
+static void exynos_usb_phy_control(enum usb_phy_type phy_type , int on)
+{
+ if (soc_is_exynos5250()) {
+ if (phy_type & USB_PHY)
+ writel(on, S5P_USBHOST_PHY_CONTROL);
+ }
+}
+
static int exynos4210_usb_phy0_init(struct platform_device *pdev)
{
u32 rstcon;
@@ -206,12 +273,158 @@ static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
return 0;
}
+static int exynos5_usb_phy20_init(struct platform_device *pdev)
+{
+ struct clk *host_clk;
+ u32 refclk_freq;
+ u32 hostphy_ctrl0;
+ u32 otgphy_sys;
+ u32 hsic_ctrl;
+ u32 ehcictrl;
+ u32 ohcictrl;
+
+ atomic_inc(&host_usage);
+ host_clk = exynos_usb_clock_enable(pdev);
+ if (host_clk == NULL) {
+ dev_err(&pdev->dev, "Failed to enable USB2.0 host clock\n");
+ return -1;
+ }
+
+ if (exynos4_usb_host_phy_is_on()) {
+ dev_err(&pdev->dev, "Already power on PHY\n");
+ return 0;
+ }
+
+ exynos_usb_mux_change(pdev, 1);
+
+ exynos_usb_phy_control(USB_PHY, PHY_ENABLE);
+
+ /* Host and Device should be set at the same time */
+ hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
+ hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK);
+ otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
+ otgphy_sys &= ~(OTG_SYS_CTRL0_FSEL_MASK);
+
+ /* 2.0 phy reference clock configuration */
+ refclk_freq = exynos4210_usb_phy_clkset(pdev);
+ hostphy_ctrl0 |= (refclk_freq << HOST_CTRL0_CLKSEL_SHIFT);
+ otgphy_sys |= (refclk_freq << OTG_SYS_CLKSEL_SHIFT);
+
+ /* COMMON Block configuration during suspend */
+ hostphy_ctrl0 &= ~(HOST_CTRL0_COMMONON_N);
+ otgphy_sys |= (OTG_SYS_COMMON_ON);
+
+ /* otg phy reset */
+ otgphy_sys &= ~(OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG
+ | OTG_SYS_FORCE_SLEEP);
+ otgphy_sys &= ~(OTG_SYS_REF_CLK_SEL_MASK << OTG_SYS_REF_CLK_SEL_SHIFT);
+ otgphy_sys |= (((OTG_SYS_REF_CLK_SEL_CLKCORE & OTG_SYS_REF_CLK_SEL_MASK)
+ << OTG_SYS_REF_CLK_SEL_SHIFT)
+ | OTG_SYS_OTGDISABLE);
+ otgphy_sys |= (OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG
+ | OTG_SYS_PHYLINK_SW_RESET);
+ writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+ udelay(10);
+ otgphy_sys &= ~(OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG
+ | OTG_SYS_PHYLINK_SW_RESET);
+ writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+
+ /* host phy reset */
+ hostphy_ctrl0 &= ~(HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL
+ | HOST_CTRL0_SIDDQ);
+ hostphy_ctrl0 &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
+ hostphy_ctrl0 |= (HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
+ writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+ udelay(10);
+ hostphy_ctrl0 &= ~(HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
+ writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+
+ /* HSIC phy reset */
+ hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
+ << HSIC_CTRL_REFCLKDIV_SHIFT)
+ | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
+ << HSIC_CTRL_REFCLKSEL_SHIFT)
+ | HSIC_CTRL_PHYSWRST);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+ udelay(10);
+ hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+
+ udelay(80);
+
+ /* enable EHCI DMA burst */
+ ehcictrl = readl(EXYNOS5_PHY_HOST_EHCICTRL);
+ ehcictrl |= (EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4
+ | EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16);
+ writel(ehcictrl, EXYNOS5_PHY_HOST_EHCICTRL);
+
+ /* set ohci_suspend_on_n */
+ ohcictrl = readl(EXYNOS5_PHY_HOST_OHCICTRL);
+ ohcictrl |= OHCICTRL_SUSPLGCY;
+ writel(ohcictrl, EXYNOS5_PHY_HOST_OHCICTRL);
+
+ clk_disable(host_clk);
+ clk_put(host_clk);
+ return 0;
+}
+
+static int exynos5_usb_phy20_exit(struct platform_device *pdev)
+{
+ struct clk *host_clk;
+ u32 hostphy_ctrl0;
+ u32 otgphy_sys;
+ u32 hsic_ctrl;
+
+ if (atomic_dec_return(&host_usage) > 0) {
+ dev_info(&pdev->dev, "still being used\n");
+ return -EBUSY;
+ }
+
+ host_clk = exynos_usb_clock_enable(pdev);
+ if (host_clk == NULL) {
+ dev_err(&pdev->dev, "Failed to enable otg clock this time\n");
+ return -1;
+ }
+
+ hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
+ << HSIC_CTRL_REFCLKDIV_SHIFT)
+ | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
+ << HSIC_CTRL_REFCLKSEL_SHIFT)
+ | HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP
+ | HSIC_CTRL_FORCESUSPEND);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+
+ hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
+ hostphy_ctrl0 |= (HOST_CTRL0_SIDDQ);
+ hostphy_ctrl0 |= (HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
+ hostphy_ctrl0 |= (HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL);
+ writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+
+ otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
+ otgphy_sys |= (OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG
+ | OTG_SYS_FORCE_SLEEP);
+ writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+
+ exynos_usb_phy_control(USB_PHY, PHY_DISABLE);
+
+ clk_disable(host_clk);
+ clk_put(host_clk);
+ return 0;
+}
+
int s5p_usb_phy_init(struct platform_device *pdev, int type)
{
if (type == S5P_USB_PHY_DEVICE)
return exynos4210_usb_phy0_init(pdev);
- else if (type == S5P_USB_PHY_HOST)
- return exynos4210_usb_phy1_init(pdev);
+ else if (type == S5P_USB_PHY_HOST) {
+ if (soc_is_exynos5250())
+ return exynos5_usb_phy20_init(pdev);
+ else
+ return exynos4210_usb_phy1_init(pdev);
+ }
return -EINVAL;
}
@@ -220,8 +433,11 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
{
if (type == S5P_USB_PHY_DEVICE)
return exynos4210_usb_phy0_exit(pdev);
- else if (type == S5P_USB_PHY_HOST)
- return exynos4210_usb_phy1_exit(pdev);
-
+ else if (type == S5P_USB_PHY_HOST) {
+ if (soc_is_exynos5250())
+ return exynos5_usb_phy20_exit(pdev);
+ else
+ return exynos4210_usb_phy1_exit(pdev);
+ }
return -EINVAL;
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 5/8] ARM: EXYNOS5: Add PHY initialization code for usb 2.0
@ 2012-07-18 13:45 ` Vivek Gautam
0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds PHY setup functions usb 2.0 support on exynos5
Signed-off-by: Yulgon Kim <yulgon.kim@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e698ca0..e0bc441 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -416,6 +416,7 @@ config MACH_EXYNOS5_DT
select SOC_EXYNOS5250
select USE_OF
select ARM_AMBA
+ select EXYNOS4_SETUP_USB_PHY
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS4 SoC based board.
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
index 0727773..2df4bd7 100644
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -13,6 +13,7 @@
#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
+/* Exynos 4 */
#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
#define PHY1_HSIC1_SLEEP (1 << 12)
@@ -71,4 +72,89 @@
#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
#define FPENABLEN (1 << 0)
+/* Exynos 5 */
+#define EXYNOS5_PHY_HOST_CTRL0 EXYNOS4_HSOTG_PHYREG(0x00)
+#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31)
+
+#define HOST_CTRL0_REFCLKSEL_XTAL (0x0)
+#define HOST_CTRL0_REFCLKSEL_EXTL (0x1)
+#define HOST_CTRL0_REFCLKSEL_CLK_CORE (0x2)
+#define HOST_CTRL0_REFCLKSEL_MASK (0x3)
+#define HOST_CTRL0_REFCLKSEL_SHIFT (19)
+
+#define EXYNOS5_CLKSEL_50M (0x7)
+#define EXYNOS5_CLKSEL_24M (0x5)
+#define EXYNOS5_CLKSEL_20M (0x4)
+#define EXYNOS5_CLKSEL_19200K (0x3)
+#define EXYNOS5_CLKSEL_12M (0x2)
+#define EXYNOS5_CLKSEL_10M (0x1)
+#define EXYNOS5_CLKSEL_9600K (0x0)
+#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
+#define HOST_CTRL0_CLKSEL_SHIFT (16)
+
+#define HOST_CTRL0_COMMONON_N (0x1 << 9)
+#define HOST_CTRL0_SIDDQ (0x1 << 6)
+#define HOST_CTRL0_FORCESLEEP (0x1 << 5)
+#define HOST_CTRL0_FORCESUSPEND (0x1 << 4)
+#define HOST_CTRL0_WORDINTERFACE (0x1 << 3)
+#define HOST_CTRL0_UTMISWRST (0x1 << 2)
+#define HOST_CTRL0_LINKSWRST (0x1 << 1)
+#define HOST_CTRL0_PHYSWRST (0x1 << 0)
+
+#define EXYNOS5_PHY_HOST_TUNE0 EXYNOS4_HSOTG_PHYREG(0x04)
+#define EXYNOS5_PHY_HOST_TEST0 EXYNOS4_HSOTG_PHYREG(0x08)
+
+#define EXYNOS5_PHY_HSIC_CTRL1 EXYNOS4_HSOTG_PHYREG(0x10)
+#define EXYNOS5_PHY_HSIC_CTRL2 EXYNOS4_HSOTG_PHYREG(0x20)
+#define HSIC_CTRL_REFCLKSEL (0x2)
+#define HSIC_CTRL_REFCLKSEL_MASK (0x3)
+#define HSIC_CTRL_REFCLKSEL_SHIFT (23)
+
+#define HSIC_CTRL_REFCLKDIV_12 (0x24)
+#define HSIC_CTRL_REFCLKDIV_15 (0x1C)
+#define HSIC_CTRL_REFCLKDIV_16 (0x1A)
+#define HSIC_CTRL_REFCLKDIV_19_2 (0x15)
+#define HSIC_CTRL_REFCLKDIV_20 (0x14)
+#define HSIC_CTRL_REFCLKDIV_MASK (0x7f)
+#define HSIC_CTRL_REFCLKDIV_SHIFT (16)
+
+#define HSIC_CTRL_SIDDQ (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
+#define HSIC_CTRL_WORDINTERFACE (0x1 << 3)
+#define HSIC_CTRL_UTMISWRST (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST (0x1 << 0)
+
+#define EXYNOS5_PHY_HOST_EHCICTRL EXYNOS4_HSOTG_PHYREG(0x30)
+#define EHCICTRL_ENAINCRXALIGN (0x1 << 29)
+#define EHCICTRL_ENAINCR4 (0x1 << 28)
+#define EHCICTRL_ENAINCR8 (0x1 << 27)
+#define EHCICTRL_ENAINCR16 (0x1 << 26)
+
+#define EXYNOS5_PHY_HOST_OHCICTRL EXYNOS4_HSOTG_PHYREG(0x34)
+#define OHCICTRL_SUSPLGCY (0x1 << 3)
+#define OHCICTRL_APPSTARTCLK (0x1 << 2)
+#define OHCICTRL_CNTSEL (0x1 << 1)
+#define OHCICTRL_CLKCKTRST (0x1 << 0)
+
+#define EXYNOS5_PHY_OTG_SYS EXYNOS4_HSOTG_PHYREG(0x38)
+#define OTG_SYS_PHYLINK_SW_RESET (0x1 << 14)
+#define OTG_SYS_LINK_SW_RST_UOTG (0x1 << 13)
+#define OTG_SYS_PHY0_SW_RST (0x1 << 12)
+
+#define OTG_SYS_REF_CLK_SEL_XTAL (0x0)
+#define OTG_SYS_REF_CLK_SEL_EXTL (0x1)
+#define OTG_SYS_REF_CLK_SEL_CLKCORE (0x2)
+#define OTG_SYS_REF_CLK_SEL_MASK (0x3)
+#define OTG_SYS_REF_CLK_SEL_SHIFT (9)
+
+#define OTG_SYS_IP_PULLUP_UOTG (0x1 << 8)
+#define OTG_SYS_COMMON_ON (0x1 << 7)
+#define OTG_SYS_CLKSEL_SHIFT (4)
+#define OTG_SYS_CTRL0_FSEL_MASK (0x7 << 4)
+#define OTG_SYS_FORCE_SLEEP (0x1 << 3)
+#define OTG_SYS_OTGDISABLE (0x1 << 2)
+#define OTG_SYS_SIDDQ_UOTG (0x1 << 1)
+#define OTG_SYS_FORCE_SUSPEND (0x1 << 0)
+
#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index bfc1367..3f7a26a 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -19,11 +19,36 @@
#include <plat/cpu.h>
#include <plat/usb-phy.h>
+#define PHY_ENABLE 1
+#define PHY_DISABLE 0
+
+enum usb_phy_type {
+ USB_PHY = (0x1 << 0),
+};
+
static atomic_t host_usage;
static int exynos4_usb_host_phy_is_on(void)
{
- return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
+ if (soc_is_exynos5250()) {
+ return (readl(EXYNOS5_PHY_HOST_CTRL0) &
+ HOST_CTRL0_PHYSWRSTALL) ? 0 : 1;
+ } else {
+ return (readl(EXYNOS4_PHYPWR) &
+ PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
+ }
+}
+
+static void exynos_usb_mux_change(struct platform_device *pdev, int val)
+{
+ u32 is_host;
+ if (soc_is_exynos5250()) {
+ is_host = readl(EXYNOS5_USB_CFG);
+ writel(val, EXYNOS5_USB_CFG);
+ }
+ if (is_host != val)
+ dev_dbg(&pdev->dev, "Change USB MUX from %s to %s",
+ is_host ? "Host" : "Device", val ? "Host" : "Device");
}
struct clk *exynos_usb_clock_enable(struct platform_device *pdev)
@@ -32,7 +57,10 @@ struct clk *exynos_usb_clock_enable(struct platform_device *pdev)
int err = 0;
if (!usb_clk) {
- usb_clk = clk_get(&pdev->dev, "otg");
+ if (soc_is_exynos5250())
+ usb_clk = clk_get(&pdev->dev, "usbhost");
+ else
+ usb_clk = clk_get(&pdev->dev, "otg");
if (IS_ERR(usb_clk)) {
dev_err(&pdev->dev, "Failed to get otg clock\n");
return NULL;
@@ -52,7 +80,11 @@ static int exynos4210_usb_phy_clkset(struct platform_device *pdev)
struct clk *xusbxti_clk;
u32 phyclk = 0;
- xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
+ if (soc_is_exynos5250())
+ xusbxti_clk = clk_get(&pdev->dev, "ext_xtal");
+ else
+ xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
+
if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
if (soc_is_exynos4210()) {
/* set clock frequency for PLL */
@@ -98,12 +130,47 @@ static int exynos4210_usb_phy_clkset(struct platform_device *pdev)
break;
}
writel(phyclk, EXYNOS4_PHYCLK);
+ } else if (soc_is_exynos5250()) {
+ /* set clock frequency for PLL */
+ switch (clk_get_rate(xusbxti_clk)) {
+ case 96 * 100000:
+ phyclk |= EXYNOS5_CLKSEL_9600K;
+ break;
+ case 10 * MHZ:
+ phyclk |= EXYNOS5_CLKSEL_10M;
+ break;
+ case 12 * MHZ:
+ phyclk |= EXYNOS5_CLKSEL_12M;
+ break;
+ case 192 * 100000:
+ phyclk |= EXYNOS5_CLKSEL_19200K;
+ break;
+ case 20 * MHZ:
+ phyclk |= EXYNOS5_CLKSEL_20M;
+ break;
+ case 50 * MHZ:
+ phyclk |= EXYNOS5_CLKSEL_50M;
+ break;
+ case 24 * MHZ:
+ default:
+ /* default reference clock */
+ phyclk |= EXYNOS5_CLKSEL_24M;
+ break;
+ }
}
clk_put(xusbxti_clk);
}
return phyclk;
}
+static void exynos_usb_phy_control(enum usb_phy_type phy_type , int on)
+{
+ if (soc_is_exynos5250()) {
+ if (phy_type & USB_PHY)
+ writel(on, S5P_USBHOST_PHY_CONTROL);
+ }
+}
+
static int exynos4210_usb_phy0_init(struct platform_device *pdev)
{
u32 rstcon;
@@ -206,12 +273,158 @@ static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
return 0;
}
+static int exynos5_usb_phy20_init(struct platform_device *pdev)
+{
+ struct clk *host_clk;
+ u32 refclk_freq;
+ u32 hostphy_ctrl0;
+ u32 otgphy_sys;
+ u32 hsic_ctrl;
+ u32 ehcictrl;
+ u32 ohcictrl;
+
+ atomic_inc(&host_usage);
+ host_clk = exynos_usb_clock_enable(pdev);
+ if (host_clk == NULL) {
+ dev_err(&pdev->dev, "Failed to enable USB2.0 host clock\n");
+ return -1;
+ }
+
+ if (exynos4_usb_host_phy_is_on()) {
+ dev_err(&pdev->dev, "Already power on PHY\n");
+ return 0;
+ }
+
+ exynos_usb_mux_change(pdev, 1);
+
+ exynos_usb_phy_control(USB_PHY, PHY_ENABLE);
+
+ /* Host and Device should be set at the same time */
+ hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
+ hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK);
+ otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
+ otgphy_sys &= ~(OTG_SYS_CTRL0_FSEL_MASK);
+
+ /* 2.0 phy reference clock configuration */
+ refclk_freq = exynos4210_usb_phy_clkset(pdev);
+ hostphy_ctrl0 |= (refclk_freq << HOST_CTRL0_CLKSEL_SHIFT);
+ otgphy_sys |= (refclk_freq << OTG_SYS_CLKSEL_SHIFT);
+
+ /* COMMON Block configuration during suspend */
+ hostphy_ctrl0 &= ~(HOST_CTRL0_COMMONON_N);
+ otgphy_sys |= (OTG_SYS_COMMON_ON);
+
+ /* otg phy reset */
+ otgphy_sys &= ~(OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG
+ | OTG_SYS_FORCE_SLEEP);
+ otgphy_sys &= ~(OTG_SYS_REF_CLK_SEL_MASK << OTG_SYS_REF_CLK_SEL_SHIFT);
+ otgphy_sys |= (((OTG_SYS_REF_CLK_SEL_CLKCORE & OTG_SYS_REF_CLK_SEL_MASK)
+ << OTG_SYS_REF_CLK_SEL_SHIFT)
+ | OTG_SYS_OTGDISABLE);
+ otgphy_sys |= (OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG
+ | OTG_SYS_PHYLINK_SW_RESET);
+ writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+ udelay(10);
+ otgphy_sys &= ~(OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG
+ | OTG_SYS_PHYLINK_SW_RESET);
+ writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+
+ /* host phy reset */
+ hostphy_ctrl0 &= ~(HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL
+ | HOST_CTRL0_SIDDQ);
+ hostphy_ctrl0 &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
+ hostphy_ctrl0 |= (HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
+ writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+ udelay(10);
+ hostphy_ctrl0 &= ~(HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
+ writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+
+ /* HSIC phy reset */
+ hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
+ << HSIC_CTRL_REFCLKDIV_SHIFT)
+ | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
+ << HSIC_CTRL_REFCLKSEL_SHIFT)
+ | HSIC_CTRL_PHYSWRST);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+ udelay(10);
+ hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+
+ udelay(80);
+
+ /* enable EHCI DMA burst */
+ ehcictrl = readl(EXYNOS5_PHY_HOST_EHCICTRL);
+ ehcictrl |= (EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4
+ | EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16);
+ writel(ehcictrl, EXYNOS5_PHY_HOST_EHCICTRL);
+
+ /* set ohci_suspend_on_n */
+ ohcictrl = readl(EXYNOS5_PHY_HOST_OHCICTRL);
+ ohcictrl |= OHCICTRL_SUSPLGCY;
+ writel(ohcictrl, EXYNOS5_PHY_HOST_OHCICTRL);
+
+ clk_disable(host_clk);
+ clk_put(host_clk);
+ return 0;
+}
+
+static int exynos5_usb_phy20_exit(struct platform_device *pdev)
+{
+ struct clk *host_clk;
+ u32 hostphy_ctrl0;
+ u32 otgphy_sys;
+ u32 hsic_ctrl;
+
+ if (atomic_dec_return(&host_usage) > 0) {
+ dev_info(&pdev->dev, "still being used\n");
+ return -EBUSY;
+ }
+
+ host_clk = exynos_usb_clock_enable(pdev);
+ if (host_clk == NULL) {
+ dev_err(&pdev->dev, "Failed to enable otg clock this time\n");
+ return -1;
+ }
+
+ hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
+ << HSIC_CTRL_REFCLKDIV_SHIFT)
+ | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
+ << HSIC_CTRL_REFCLKSEL_SHIFT)
+ | HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP
+ | HSIC_CTRL_FORCESUSPEND);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+ writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+
+ hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
+ hostphy_ctrl0 |= (HOST_CTRL0_SIDDQ);
+ hostphy_ctrl0 |= (HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
+ hostphy_ctrl0 |= (HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL);
+ writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+
+ otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
+ otgphy_sys |= (OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG
+ | OTG_SYS_FORCE_SLEEP);
+ writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+
+ exynos_usb_phy_control(USB_PHY, PHY_DISABLE);
+
+ clk_disable(host_clk);
+ clk_put(host_clk);
+ return 0;
+}
+
int s5p_usb_phy_init(struct platform_device *pdev, int type)
{
if (type == S5P_USB_PHY_DEVICE)
return exynos4210_usb_phy0_init(pdev);
- else if (type == S5P_USB_PHY_HOST)
- return exynos4210_usb_phy1_init(pdev);
+ else if (type == S5P_USB_PHY_HOST) {
+ if (soc_is_exynos5250())
+ return exynos5_usb_phy20_init(pdev);
+ else
+ return exynos4210_usb_phy1_init(pdev);
+ }
return -EINVAL;
}
@@ -220,8 +433,11 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
{
if (type == S5P_USB_PHY_DEVICE)
return exynos4210_usb_phy0_exit(pdev);
- else if (type == S5P_USB_PHY_HOST)
- return exynos4210_usb_phy1_exit(pdev);
-
+ else if (type == S5P_USB_PHY_HOST) {
+ if (soc_is_exynos5250())
+ return exynos5_usb_phy20_exit(pdev);
+ else
+ return exynos4210_usb_phy1_exit(pdev);
+ }
return -EINVAL;
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 6/8] ARM: EXYNOS5: Add machine data for USB3.0
2012-07-18 13:45 ` Vivek Gautam
@ 2012-07-18 13:45 ` Vivek Gautam
-1 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski
Cc: a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov, joshi, olofj,
prashanth.g
This patch adds clock definitions and address mapping of PHY
for USB3.0 in exynos5
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c..af1b917 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -668,6 +668,11 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 18),
}, {
+ .name = "usbdrd30",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 19),
+ }, {
.name = "usbotg",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
@@ -909,6 +914,16 @@ struct clksrc_sources exynos5_clkset_group = {
.nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
};
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+ [0] = &exynos5_clk_mout_mpll.clk,
+ [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+ .sources = exynos5_clkset_usbdrd30_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
/* Possible clock sources for aclk_266_gscl_sub Mux */
static struct clk *clk_src_gscl_266_list[] = {
[0] = &clk_ext_xtal_mux,
@@ -1199,6 +1214,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.parent = &exynos5_clk_mout_cpll.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+ }, {
+ .clk = {
+ .name = "sclk_usbdrd30",
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 28),
+ },
+ .sources = &exynos5_clkset_usbdrd30,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
},
};
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 92d5e61..c17f1df 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -280,6 +280,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS5_PA_USB_PHY),
.length = SZ_4K,
.type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_DRD_PHY,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_DRD_PHY),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
},
};
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 331ae57..b95b245 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -193,6 +193,7 @@
#define EXYNOS5_PA_UART 0x12C00000
#define EXYNOS5_PA_USB_PHY 0x12130000
+#define EXYNOS5_PA_DRD_PHY 0x12100000
#define EXYNOS4_PA_VP 0x12C00000
#define EXYNOS4_PA_MIXER 0x12C10000
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index d4e392b..67132b4 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -39,6 +39,10 @@
#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
#define S5P_HDMI_PHY_ENABLE (1 << 0)
+/* only for EXYNOS5250*/
+#define S5P_USBDRD_PHY_CONTROL S5P_PMUREG(0x0704)
+#define S5P_USBDRD_PHY_ENABLE (1 << 0)
+
#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
#define S5P_DAC_PHY_ENABLE (1 << 0)
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c2d7bda..836863a 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -40,6 +40,8 @@
#define S5P_VA_GIC_CPU S3C_ADDR(0x02810000)
#define S5P_VA_GIC_DIST S3C_ADDR(0x02820000)
+#define S5P_VA_DRD_PHY S3C_ADDR(0x03000000)
+
#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
#define VA_VIC0 VA_VIC(0)
#define VA_VIC1 VA_VIC(1)
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index a7773a3..e9cbe34 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -53,6 +53,7 @@ config USB_ARCH_HAS_EHCI
# some non-PCI HCDs implement xHCI
config USB_ARCH_HAS_XHCI
boolean
+ default y if ARCH_EXYNOS5
default PCI
menuconfig USB_SUPPORT
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 6/8] ARM: EXYNOS5: Add machine data for USB3.0
@ 2012-07-18 13:45 ` Vivek Gautam
0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds clock definitions and address mapping of PHY
for USB3.0 in exynos5
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c..af1b917 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -668,6 +668,11 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 18),
}, {
+ .name = "usbdrd30",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 19),
+ }, {
.name = "usbotg",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
@@ -909,6 +914,16 @@ struct clksrc_sources exynos5_clkset_group = {
.nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
};
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+ [0] = &exynos5_clk_mout_mpll.clk,
+ [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+ .sources = exynos5_clkset_usbdrd30_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
/* Possible clock sources for aclk_266_gscl_sub Mux */
static struct clk *clk_src_gscl_266_list[] = {
[0] = &clk_ext_xtal_mux,
@@ -1199,6 +1214,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.parent = &exynos5_clk_mout_cpll.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+ }, {
+ .clk = {
+ .name = "sclk_usbdrd30",
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 28),
+ },
+ .sources = &exynos5_clkset_usbdrd30,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
},
};
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 92d5e61..c17f1df 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -280,6 +280,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS5_PA_USB_PHY),
.length = SZ_4K,
.type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_DRD_PHY,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_DRD_PHY),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
},
};
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 331ae57..b95b245 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -193,6 +193,7 @@
#define EXYNOS5_PA_UART 0x12C00000
#define EXYNOS5_PA_USB_PHY 0x12130000
+#define EXYNOS5_PA_DRD_PHY 0x12100000
#define EXYNOS4_PA_VP 0x12C00000
#define EXYNOS4_PA_MIXER 0x12C10000
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index d4e392b..67132b4 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -39,6 +39,10 @@
#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
#define S5P_HDMI_PHY_ENABLE (1 << 0)
+/* only for EXYNOS5250*/
+#define S5P_USBDRD_PHY_CONTROL S5P_PMUREG(0x0704)
+#define S5P_USBDRD_PHY_ENABLE (1 << 0)
+
#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
#define S5P_DAC_PHY_ENABLE (1 << 0)
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c2d7bda..836863a 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -40,6 +40,8 @@
#define S5P_VA_GIC_CPU S3C_ADDR(0x02810000)
#define S5P_VA_GIC_DIST S3C_ADDR(0x02820000)
+#define S5P_VA_DRD_PHY S3C_ADDR(0x03000000)
+
#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
#define VA_VIC0 VA_VIC(0)
#define VA_VIC1 VA_VIC(1)
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index a7773a3..e9cbe34 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -53,6 +53,7 @@ config USB_ARCH_HAS_EHCI
# some non-PCI HCDs implement xHCI
config USB_ARCH_HAS_XHCI
boolean
+ default y if ARCH_EXYNOS5
default PCI
menuconfig USB_SUPPORT
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 7/8] ARM: EXYNOS5: Add XHCI device from device tree
2012-07-18 13:45 ` Vivek Gautam
@ 2012-07-18 13:45 ` Vivek Gautam
-1 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski
Cc: a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov, joshi, olofj,
prashanth.g
This patch adds EHCI device from device tree for exynos5
and adds platform data.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index 45dadca..b2349fe 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -39,3 +39,22 @@ ehci {
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
};
+XHCI
+Required properties:
+ - compatible: should be "samsung,exynos-xhci" for USB 3.0
+ DWC3 controller in host mode.
+ - reg: physical base address of the controller and length
+ of memory mapped.
+ - interrupts: interrupt number to the cpu.
+ - samsung,vbus-gpio: if present, specifies the GPIO
+ that needs to be pulled up for the bus to be powered.
+
+Optional properties:
+ - samsung,vbus-gpio: if present, specifies the GPIO
+ that needs to be pulled up for the bus to be powered.
+
+xhci {
+ compatible = "samsung,exynos-xhci";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 988f52a..bc36584 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -70,6 +70,12 @@
interrupts = <0 71 0>;
};
+ xhci {
+ compatible = "samsung,exynos-xhci";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+ };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 0cc626e..fc1ed3f 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -10,6 +10,7 @@
*/
#include <linux/of_platform.h>
+#include <linux/platform_data/dwc3-exynos.h>
#include <linux/serial_core.h>
#include <asm/mach/arch.h>
@@ -34,6 +35,12 @@ static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
.phy_exit = s5p_usb_phy_exit,
};
+static struct dwc3_exynos_data smdk5250_xhci_pdata = {
+ .phy_type = S5P_USB_PHY_DRD,
+ .phy_init = s5p_usb_phy_init,
+ .phy_exit = s5p_usb_phy_exit,
+};
+
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -73,6 +80,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"exynos-ohci", &smdk5250_ohci_pdata),
OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
"s5p-ehci", &smdk5250_ehci_pdata),
+ OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
+ "exynos-dwc3", &smdk5250_xhci_pdata),
{},
};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 7/8] ARM: EXYNOS5: Add XHCI device from device tree
@ 2012-07-18 13:45 ` Vivek Gautam
0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds EHCI device from device tree for exynos5
and adds platform data.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index 45dadca..b2349fe 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -39,3 +39,22 @@ ehci {
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
};
+XHCI
+Required properties:
+ - compatible: should be "samsung,exynos-xhci" for USB 3.0
+ DWC3 controller in host mode.
+ - reg: physical base address of the controller and length
+ of memory mapped.
+ - interrupts: interrupt number to the cpu.
+ - samsung,vbus-gpio: if present, specifies the GPIO
+ that needs to be pulled up for the bus to be powered.
+
+Optional properties:
+ - samsung,vbus-gpio: if present, specifies the GPIO
+ that needs to be pulled up for the bus to be powered.
+
+xhci {
+ compatible = "samsung,exynos-xhci";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 988f52a..bc36584 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -70,6 +70,12 @@
interrupts = <0 71 0>;
};
+ xhci {
+ compatible = "samsung,exynos-xhci";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+ };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 0cc626e..fc1ed3f 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -10,6 +10,7 @@
*/
#include <linux/of_platform.h>
+#include <linux/platform_data/dwc3-exynos.h>
#include <linux/serial_core.h>
#include <asm/mach/arch.h>
@@ -34,6 +35,12 @@ static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
.phy_exit = s5p_usb_phy_exit,
};
+static struct dwc3_exynos_data smdk5250_xhci_pdata = {
+ .phy_type = S5P_USB_PHY_DRD,
+ .phy_init = s5p_usb_phy_init,
+ .phy_exit = s5p_usb_phy_exit,
+};
+
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -73,6 +80,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"exynos-ohci", &smdk5250_ohci_pdata),
OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
"s5p-ehci", &smdk5250_ehci_pdata),
+ OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
+ "exynos-dwc3", &smdk5250_xhci_pdata),
{},
};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 8/8] ARM: EXYNOS5: Add PHY initialization code for usb 3.0
2012-07-18 13:45 ` Vivek Gautam
@ 2012-07-18 13:45 ` Vivek Gautam
-1 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski
Cc: a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov, joshi, olofj,
prashanth.g
This patch adds PHY setup functions for usb 3.0 support on exynos5
Signed-off-by: Yulgon Kim <yulgon.kim@samsung.com>
Signed-off-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 3f7a26a..f8f64c8 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -18,12 +18,14 @@
#include <mach/regs-usb-phy.h>
#include <plat/cpu.h>
#include <plat/usb-phy.h>
+#include <plat/regs-usb3-exynos-drd-phy.h>
#define PHY_ENABLE 1
#define PHY_DISABLE 0
enum usb_phy_type {
USB_PHY = (0x1 << 0),
+ USB_PHY_DRD = (0x1 << 1),
};
static atomic_t host_usage;
@@ -163,11 +165,44 @@ static int exynos4210_usb_phy_clkset(struct platform_device *pdev)
return phyclk;
}
+static u32 exynos_usb_phy30_set_clock(struct platform_device *pdev)
+{
+ u32 reg, refclk;
+
+ refclk = exynos4210_usb_phy_clkset(pdev);
+ reg = EXYNOS_USB3_PHYCLKRST_REFCLKSEL(3) |
+ EXYNOS_USB3_PHYCLKRST_FSEL(refclk);
+
+ switch (refclk) {
+ case EXYNOS5_CLKSEL_50M:
+ reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x02) |
+ EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x00));
+ break;
+ case EXYNOS5_CLKSEL_20M:
+ reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x7d) |
+ EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x00));
+ break;
+ case EXYNOS5_CLKSEL_19200K:
+ reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x02) |
+ EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x88));
+ break;
+ case EXYNOS5_CLKSEL_24M:
+ default:
+ reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x68) |
+ EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x88));
+ break;
+ }
+
+ return reg;
+}
+
static void exynos_usb_phy_control(enum usb_phy_type phy_type , int on)
{
if (soc_is_exynos5250()) {
if (phy_type & USB_PHY)
writel(on, S5P_USBHOST_PHY_CONTROL);
+ if (phy_type & USB_PHY_DRD)
+ writel(on, S5P_USBDRD_PHY_CONTROL);
}
}
@@ -415,6 +450,88 @@ static int exynos5_usb_phy20_exit(struct platform_device *pdev)
return 0;
}
+static int exynos5_usb_phy30_init(struct platform_device *pdev)
+{
+ struct clk *host_clk;
+ u32 reg;
+
+ host_clk = exynos_usb_clock_enable(pdev);
+ if (host_clk == NULL) {
+ dev_err(&pdev->dev, "Failed to enable USB3.0 host clock this time\n");
+ return -1;
+ }
+
+ exynos_usb_phy_control(USB_PHY_DRD, PHY_ENABLE);
+
+ /* Reset USB 3.0 PHY */
+ writel(0x00000000, EXYNOS_USB3_PHYREG0);
+ writel(0x24d4e6e4, EXYNOS_USB3_PHYPARAM0);
+ writel(0x03fff81c, EXYNOS_USB3_PHYPARAM1);
+ writel(0x00000000, EXYNOS_USB3_PHYRESUME);
+
+ writel(0x08000040, EXYNOS_USB3_LINKSYSTEM);
+ writel(0x00000004, EXYNOS_USB3_PHYBATCHG);
+
+ /* PHYTEST POWERDOWN Control */
+ reg = readl(EXYNOS_USB3_PHYTEST);
+ reg &= ~(EXYNOS_USB3_PHYTEST_POWERDOWN_SSP |
+ EXYNOS_USB3_PHYTEST_POWERDOWN_HSP);
+ writel(reg, EXYNOS_USB3_PHYTEST);
+
+ /* UTMI Power Control */
+ writel(EXYNOS_USB3_PHYUTMI_OTGDISABLE, EXYNOS_USB3_PHYUTMI);
+
+ reg = exynos_usb_phy30_set_clock(pdev);
+
+ reg |= (EXYNOS_USB3_PHYCLKRST_PORTRESET |
+ /* Digital power supply in normal operating mode */
+ EXYNOS_USB3_PHYCLKRST_RETENABLEN |
+ /* Enable ref clock for SS function */
+ EXYNOS_USB3_PHYCLKRST_REF_SSP_EN |
+ /* Enable spread spectrum */
+ EXYNOS_USB3_PHYCLKRST_SSC_EN) |
+ EXYNOS_USB3_PHYCLKRST_COMMONONN;
+ writel(reg, EXYNOS_USB3_PHYCLKRST);
+
+ udelay(10);
+
+ reg &= ~(EXYNOS_USB3_PHYCLKRST_PORTRESET);
+ writel(reg, EXYNOS_USB3_PHYCLKRST);
+
+ clk_disable(host_clk);
+ clk_put(host_clk);
+ return 0;
+}
+
+static int exynos5_usb_phy30_exit(struct platform_device *pdev)
+{
+ struct clk *host_clk;
+ u32 reg;
+
+ host_clk = exynos_usb_clock_enable(pdev);
+ if (host_clk == NULL) {
+ dev_err(&pdev->dev, "Failed to enable USB3.0 host clock this time\n");
+ return -1;
+ }
+
+ reg = EXYNOS_USB3_PHYUTMI_OTGDISABLE |
+ EXYNOS_USB3_PHYUTMI_FORCESUSPEND |
+ EXYNOS_USB3_PHYUTMI_FORCESLEEP;
+ writel(reg, EXYNOS_USB3_PHYUTMI);
+
+ /* Control PHYTEST to remove leakage current */
+ reg = readl(EXYNOS_USB3_PHYTEST);
+ reg |= (EXYNOS_USB3_PHYTEST_POWERDOWN_SSP |
+ EXYNOS_USB3_PHYTEST_POWERDOWN_HSP);
+ writel(reg, EXYNOS_USB3_PHYTEST);
+
+ exynos_usb_phy_control(USB_PHY_DRD, PHY_DISABLE);
+
+ clk_disable(host_clk);
+ clk_put(host_clk);
+ return 0;
+}
+
int s5p_usb_phy_init(struct platform_device *pdev, int type)
{
if (type == S5P_USB_PHY_DEVICE)
@@ -424,6 +541,11 @@ int s5p_usb_phy_init(struct platform_device *pdev, int type)
return exynos5_usb_phy20_init(pdev);
else
return exynos4210_usb_phy1_init(pdev);
+ } else if (type == S5P_USB_PHY_DRD) {
+ if (soc_is_exynos5250())
+ return exynos5_usb_phy30_init(pdev);
+ else
+ dev_err(&pdev->dev, "USB 3.0 DRD not present\n");
}
return -EINVAL;
@@ -438,6 +560,11 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
return exynos5_usb_phy20_exit(pdev);
else
return exynos4210_usb_phy1_exit(pdev);
+ } else if (type == S5P_USB_PHY_DRD) {
+ if (soc_is_exynos5250())
+ return exynos5_usb_phy30_exit(pdev);
+ else
+ dev_err(&pdev->dev, "USB 3.0 DRD not present\n");
}
return -EINVAL;
}
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h
new file mode 100644
index 0000000..8efd5c7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co. Ltd
+ *
+ * Exynos SuperSpeed USB 3.0 DRD Controller PHY registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H
+#define __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H __FILE__
+
+#define EXYNOS_USB3_PHYREG(x) ((x) + S5P_VA_DRD_PHY)
+
+#define EXYNOS_USB3_LINKSYSTEM EXYNOS_USB3_PHYREG(0x04)
+#define EXYNOS_USB3_PHYUTMI EXYNOS_USB3_PHYREG(0x08)
+
+#define EXYNOS_USB3_PHYUTMI_OTGDISABLE (1 << 6)
+#define EXYNOS_USB3_PHYUTMI_FORCESUSPEND (1 << 1)
+#define EXYNOS_USB3_PHYUTMI_FORCESLEEP (1 << 0)
+
+#define EXYNOS_USB3_PHYPIPE EXYNOS_USB3_PHYREG(0x0C)
+#define EXYNOS_USB3_PHYCLKRST EXYNOS_USB3_PHYREG(0x10)
+
+#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_MASK (0xff << 23)
+#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_SHIFT (23)
+#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_LIMIT (0xff)
+#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(_x) ((_x) << 23)
+
+#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_SHIFT (21)
+#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_LIMIT (0x03)
+#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define EXYNOS_USB3_PHYCLKRST_SSC_EN (1 << 20)
+#define EXYNOS_USB3_PHYCLKRST_REF_SSP_EN (1 << 19)
+#define EXYNOS_USB3_PHYCLKRST_REF_CLKDIV2 (1 << 18)
+
+#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_SHIFT (11)
+#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_LIMIT (0x7f)
+#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(_x) ((_x) << 11)
+
+#define EXYNOS_USB3_PHYCLKRST_FSEL_MASK (0x3f << 5)
+#define EXYNOS_USB3_PHYCLKRST_FSEL_SHIFT (5)
+#define EXYNOS_USB3_PHYCLKRST_FSEL_LIMIT (0x3f)
+#define EXYNOS_USB3_PHYCLKRST_FSEL(_x) ((_x) << 5)
+
+#define EXYNOS_USB3_PHYCLKRST_RETENABLEN (1 << 4)
+
+#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_SHIFT (2)
+#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_LIMIT (0x03)
+#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL(_x) ((_x) << 2)
+
+#define EXYNOS_USB3_PHYCLKRST_PORTRESET (1 << 1)
+#define EXYNOS_USB3_PHYCLKRST_COMMONONN (1 << 0)
+
+#define EXYNOS_USB3_PHYREG0 EXYNOS_USB3_PHYREG(0x14)
+#define EXYNOS_USB3_PHYREG1 EXYNOS_USB3_PHYREG(0x18)
+#define EXYNOS_USB3_PHYPARAM0 EXYNOS_USB3_PHYREG(0x1C)
+#define EXYNOS_USB3_PHYPARAM1 EXYNOS_USB3_PHYREG(0x20)
+#define EXYNOS_USB3_PHYTERM EXYNOS_USB3_PHYREG(0x24)
+
+#define EXYNOS_USB3_PHYTEST EXYNOS_USB3_PHYREG(0x28)
+
+#define EXYNOS_USB3_PHYTEST_POWERDOWN_SSP (1 << 3)
+#define EXYNOS_USB3_PHYTEST_POWERDOWN_HSP (1 << 3)
+
+#define EXYNOS_USB3_PHYADP EXYNOS_USB3_PHYREG(0x2C)
+#define EXYNOS_USB3_PHYBATCHG EXYNOS_USB3_PHYREG(0x30)
+#define EXYNOS_USB3_PHYRESUME EXYNOS_USB3_PHYREG(0x34)
+#define EXYNOS_USB3_LINKPORT EXYNOS_USB3_PHYREG(0x44)
+#endif /* __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H */
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 959bcdb..f784101 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -14,6 +14,7 @@
enum s5p_usb_phy_type {
S5P_USB_PHY_DEVICE,
S5P_USB_PHY_HOST,
+ S5P_USB_PHY_DRD,
};
extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 8/8] ARM: EXYNOS5: Add PHY initialization code for usb 3.0
@ 2012-07-18 13:45 ` Vivek Gautam
0 siblings, 0 replies; 22+ messages in thread
From: Vivek Gautam @ 2012-07-18 13:45 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds PHY setup functions for usb 3.0 support on exynos5
Signed-off-by: Yulgon Kim <yulgon.kim@samsung.com>
Signed-off-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 3f7a26a..f8f64c8 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -18,12 +18,14 @@
#include <mach/regs-usb-phy.h>
#include <plat/cpu.h>
#include <plat/usb-phy.h>
+#include <plat/regs-usb3-exynos-drd-phy.h>
#define PHY_ENABLE 1
#define PHY_DISABLE 0
enum usb_phy_type {
USB_PHY = (0x1 << 0),
+ USB_PHY_DRD = (0x1 << 1),
};
static atomic_t host_usage;
@@ -163,11 +165,44 @@ static int exynos4210_usb_phy_clkset(struct platform_device *pdev)
return phyclk;
}
+static u32 exynos_usb_phy30_set_clock(struct platform_device *pdev)
+{
+ u32 reg, refclk;
+
+ refclk = exynos4210_usb_phy_clkset(pdev);
+ reg = EXYNOS_USB3_PHYCLKRST_REFCLKSEL(3) |
+ EXYNOS_USB3_PHYCLKRST_FSEL(refclk);
+
+ switch (refclk) {
+ case EXYNOS5_CLKSEL_50M:
+ reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x02) |
+ EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x00));
+ break;
+ case EXYNOS5_CLKSEL_20M:
+ reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x7d) |
+ EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x00));
+ break;
+ case EXYNOS5_CLKSEL_19200K:
+ reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x02) |
+ EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x88));
+ break;
+ case EXYNOS5_CLKSEL_24M:
+ default:
+ reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x68) |
+ EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x88));
+ break;
+ }
+
+ return reg;
+}
+
static void exynos_usb_phy_control(enum usb_phy_type phy_type , int on)
{
if (soc_is_exynos5250()) {
if (phy_type & USB_PHY)
writel(on, S5P_USBHOST_PHY_CONTROL);
+ if (phy_type & USB_PHY_DRD)
+ writel(on, S5P_USBDRD_PHY_CONTROL);
}
}
@@ -415,6 +450,88 @@ static int exynos5_usb_phy20_exit(struct platform_device *pdev)
return 0;
}
+static int exynos5_usb_phy30_init(struct platform_device *pdev)
+{
+ struct clk *host_clk;
+ u32 reg;
+
+ host_clk = exynos_usb_clock_enable(pdev);
+ if (host_clk == NULL) {
+ dev_err(&pdev->dev, "Failed to enable USB3.0 host clock this time\n");
+ return -1;
+ }
+
+ exynos_usb_phy_control(USB_PHY_DRD, PHY_ENABLE);
+
+ /* Reset USB 3.0 PHY */
+ writel(0x00000000, EXYNOS_USB3_PHYREG0);
+ writel(0x24d4e6e4, EXYNOS_USB3_PHYPARAM0);
+ writel(0x03fff81c, EXYNOS_USB3_PHYPARAM1);
+ writel(0x00000000, EXYNOS_USB3_PHYRESUME);
+
+ writel(0x08000040, EXYNOS_USB3_LINKSYSTEM);
+ writel(0x00000004, EXYNOS_USB3_PHYBATCHG);
+
+ /* PHYTEST POWERDOWN Control */
+ reg = readl(EXYNOS_USB3_PHYTEST);
+ reg &= ~(EXYNOS_USB3_PHYTEST_POWERDOWN_SSP |
+ EXYNOS_USB3_PHYTEST_POWERDOWN_HSP);
+ writel(reg, EXYNOS_USB3_PHYTEST);
+
+ /* UTMI Power Control */
+ writel(EXYNOS_USB3_PHYUTMI_OTGDISABLE, EXYNOS_USB3_PHYUTMI);
+
+ reg = exynos_usb_phy30_set_clock(pdev);
+
+ reg |= (EXYNOS_USB3_PHYCLKRST_PORTRESET |
+ /* Digital power supply in normal operating mode */
+ EXYNOS_USB3_PHYCLKRST_RETENABLEN |
+ /* Enable ref clock for SS function */
+ EXYNOS_USB3_PHYCLKRST_REF_SSP_EN |
+ /* Enable spread spectrum */
+ EXYNOS_USB3_PHYCLKRST_SSC_EN) |
+ EXYNOS_USB3_PHYCLKRST_COMMONONN;
+ writel(reg, EXYNOS_USB3_PHYCLKRST);
+
+ udelay(10);
+
+ reg &= ~(EXYNOS_USB3_PHYCLKRST_PORTRESET);
+ writel(reg, EXYNOS_USB3_PHYCLKRST);
+
+ clk_disable(host_clk);
+ clk_put(host_clk);
+ return 0;
+}
+
+static int exynos5_usb_phy30_exit(struct platform_device *pdev)
+{
+ struct clk *host_clk;
+ u32 reg;
+
+ host_clk = exynos_usb_clock_enable(pdev);
+ if (host_clk == NULL) {
+ dev_err(&pdev->dev, "Failed to enable USB3.0 host clock this time\n");
+ return -1;
+ }
+
+ reg = EXYNOS_USB3_PHYUTMI_OTGDISABLE |
+ EXYNOS_USB3_PHYUTMI_FORCESUSPEND |
+ EXYNOS_USB3_PHYUTMI_FORCESLEEP;
+ writel(reg, EXYNOS_USB3_PHYUTMI);
+
+ /* Control PHYTEST to remove leakage current */
+ reg = readl(EXYNOS_USB3_PHYTEST);
+ reg |= (EXYNOS_USB3_PHYTEST_POWERDOWN_SSP |
+ EXYNOS_USB3_PHYTEST_POWERDOWN_HSP);
+ writel(reg, EXYNOS_USB3_PHYTEST);
+
+ exynos_usb_phy_control(USB_PHY_DRD, PHY_DISABLE);
+
+ clk_disable(host_clk);
+ clk_put(host_clk);
+ return 0;
+}
+
int s5p_usb_phy_init(struct platform_device *pdev, int type)
{
if (type == S5P_USB_PHY_DEVICE)
@@ -424,6 +541,11 @@ int s5p_usb_phy_init(struct platform_device *pdev, int type)
return exynos5_usb_phy20_init(pdev);
else
return exynos4210_usb_phy1_init(pdev);
+ } else if (type == S5P_USB_PHY_DRD) {
+ if (soc_is_exynos5250())
+ return exynos5_usb_phy30_init(pdev);
+ else
+ dev_err(&pdev->dev, "USB 3.0 DRD not present\n");
}
return -EINVAL;
@@ -438,6 +560,11 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
return exynos5_usb_phy20_exit(pdev);
else
return exynos4210_usb_phy1_exit(pdev);
+ } else if (type == S5P_USB_PHY_DRD) {
+ if (soc_is_exynos5250())
+ return exynos5_usb_phy30_exit(pdev);
+ else
+ dev_err(&pdev->dev, "USB 3.0 DRD not present\n");
}
return -EINVAL;
}
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h
new file mode 100644
index 0000000..8efd5c7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co. Ltd
+ *
+ * Exynos SuperSpeed USB 3.0 DRD Controller PHY registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H
+#define __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H __FILE__
+
+#define EXYNOS_USB3_PHYREG(x) ((x) + S5P_VA_DRD_PHY)
+
+#define EXYNOS_USB3_LINKSYSTEM EXYNOS_USB3_PHYREG(0x04)
+#define EXYNOS_USB3_PHYUTMI EXYNOS_USB3_PHYREG(0x08)
+
+#define EXYNOS_USB3_PHYUTMI_OTGDISABLE (1 << 6)
+#define EXYNOS_USB3_PHYUTMI_FORCESUSPEND (1 << 1)
+#define EXYNOS_USB3_PHYUTMI_FORCESLEEP (1 << 0)
+
+#define EXYNOS_USB3_PHYPIPE EXYNOS_USB3_PHYREG(0x0C)
+#define EXYNOS_USB3_PHYCLKRST EXYNOS_USB3_PHYREG(0x10)
+
+#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_MASK (0xff << 23)
+#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_SHIFT (23)
+#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_LIMIT (0xff)
+#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(_x) ((_x) << 23)
+
+#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_SHIFT (21)
+#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_LIMIT (0x03)
+#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define EXYNOS_USB3_PHYCLKRST_SSC_EN (1 << 20)
+#define EXYNOS_USB3_PHYCLKRST_REF_SSP_EN (1 << 19)
+#define EXYNOS_USB3_PHYCLKRST_REF_CLKDIV2 (1 << 18)
+
+#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_SHIFT (11)
+#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_LIMIT (0x7f)
+#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(_x) ((_x) << 11)
+
+#define EXYNOS_USB3_PHYCLKRST_FSEL_MASK (0x3f << 5)
+#define EXYNOS_USB3_PHYCLKRST_FSEL_SHIFT (5)
+#define EXYNOS_USB3_PHYCLKRST_FSEL_LIMIT (0x3f)
+#define EXYNOS_USB3_PHYCLKRST_FSEL(_x) ((_x) << 5)
+
+#define EXYNOS_USB3_PHYCLKRST_RETENABLEN (1 << 4)
+
+#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_SHIFT (2)
+#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_LIMIT (0x03)
+#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL(_x) ((_x) << 2)
+
+#define EXYNOS_USB3_PHYCLKRST_PORTRESET (1 << 1)
+#define EXYNOS_USB3_PHYCLKRST_COMMONONN (1 << 0)
+
+#define EXYNOS_USB3_PHYREG0 EXYNOS_USB3_PHYREG(0x14)
+#define EXYNOS_USB3_PHYREG1 EXYNOS_USB3_PHYREG(0x18)
+#define EXYNOS_USB3_PHYPARAM0 EXYNOS_USB3_PHYREG(0x1C)
+#define EXYNOS_USB3_PHYPARAM1 EXYNOS_USB3_PHYREG(0x20)
+#define EXYNOS_USB3_PHYTERM EXYNOS_USB3_PHYREG(0x24)
+
+#define EXYNOS_USB3_PHYTEST EXYNOS_USB3_PHYREG(0x28)
+
+#define EXYNOS_USB3_PHYTEST_POWERDOWN_SSP (1 << 3)
+#define EXYNOS_USB3_PHYTEST_POWERDOWN_HSP (1 << 3)
+
+#define EXYNOS_USB3_PHYADP EXYNOS_USB3_PHYREG(0x2C)
+#define EXYNOS_USB3_PHYBATCHG EXYNOS_USB3_PHYREG(0x30)
+#define EXYNOS_USB3_PHYRESUME EXYNOS_USB3_PHYREG(0x34)
+#define EXYNOS_USB3_LINKPORT EXYNOS_USB3_PHYREG(0x44)
+#endif /* __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H */
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 959bcdb..f784101 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -14,6 +14,7 @@
enum s5p_usb_phy_type {
S5P_USB_PHY_DEVICE,
S5P_USB_PHY_HOST,
+ S5P_USB_PHY_DRD,
};
extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 3/8] ARM: EXYNOS5: Add OHCI device from device tree
2012-07-18 13:45 ` Vivek Gautam
@ 2012-07-19 4:06 ` Sachin Kamat
-1 siblings, 0 replies; 22+ messages in thread
From: Sachin Kamat @ 2012-07-19 4:06 UTC (permalink / raw)
To: Vivek Gautam
Cc: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski, a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov,
joshi, olofj, prashanth.g, Ajay Kumar
On 18/07/2012, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> From: Ajay Kumar <ajaykumar.rs@samsung.com>
>
> This patch adds OHCI device from device tree for exynos5
> and adds platform data.
>
> Signed-off-by: Banajit Goswami <banajit.g@samsung.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
This patch seems to be from Ajay Kumar, but his signed-off is missing.
>
> diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
> b/Documentation/devicetree/bindings/usb/exynos-usb.txt
> new file mode 100644
> index 0000000..63b80b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
> @@ -0,0 +1,19 @@
> +Samsung Exynos SoC USB controller
> +
> +The device node for USB controller for Samsung SOC have
> +following properties
> +
> +OHCI
> +Required properties:
> + - compatible: should be "samsung,exynos-ohci" for USB 2.0
> + OHCI companion controller in host mode.
> + - reg: physical base address of the controller and length
> + of memory mapped.
> + - interrupts: interrupt number to the cpu.
> +
> +ohci {
> + compatible = "samsung,exynos-ohci";
> + reg = <0x12120000 0x100>;
> + interrupts = <0 71 0>;
> +};
> +
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
> b/arch/arm/boot/dts/exynos5250.dtsi
> index a3a2eb2..3c73d15 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -58,6 +58,12 @@
> interrupts = <0 42 0>;
> };
>
> + ohci {
> + compatible = "samsung,exynos-ohci";
> + reg = <0x12120000 0x100>;
> + interrupts = <0 71 0>;
> + };
> +
> rtc {
> compatible = "samsung,s3c6410-rtc";
> reg = <0x101E0000 0x100>;
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
> b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index ef770bc..39a4b34 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -15,12 +15,19 @@
> #include <asm/mach/arch.h>
> #include <asm/hardware/gic.h>
> #include <mach/map.h>
> +#include <mach/ohci.h>
>
> #include <plat/cpu.h>
> #include <plat/regs-serial.h>
> +#include <plat/usb-phy.h>
>
> #include "common.h"
>
> +static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
> + .phy_init = s5p_usb_phy_init,
> + .phy_exit = s5p_usb_phy_exit,
> +};
> +
> /*
> * The following lookup table is used to override device names when
> devices
> * are registered from device tree. This is temporarily added to enable
> @@ -56,6 +63,8 @@ static const struct of_dev_auxdata
> exynos5250_auxdata_lookup[] __initconst = {
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
> + OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
A macro would make it more readable instead of this magic number?
> + "exynos-ohci", &smdk5250_ohci_pdata),
> {},
> };
>
> --
> 1.7.0.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/8] ARM: EXYNOS5: Add OHCI device from device tree
@ 2012-07-19 4:06 ` Sachin Kamat
0 siblings, 0 replies; 22+ messages in thread
From: Sachin Kamat @ 2012-07-19 4:06 UTC (permalink / raw)
To: linux-arm-kernel
On 18/07/2012, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> From: Ajay Kumar <ajaykumar.rs@samsung.com>
>
> This patch adds OHCI device from device tree for exynos5
> and adds platform data.
>
> Signed-off-by: Banajit Goswami <banajit.g@samsung.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
This patch seems to be from Ajay Kumar, but his signed-off is missing.
>
> diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
> b/Documentation/devicetree/bindings/usb/exynos-usb.txt
> new file mode 100644
> index 0000000..63b80b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
> @@ -0,0 +1,19 @@
> +Samsung Exynos SoC USB controller
> +
> +The device node for USB controller for Samsung SOC have
> +following properties
> +
> +OHCI
> +Required properties:
> + - compatible: should be "samsung,exynos-ohci" for USB 2.0
> + OHCI companion controller in host mode.
> + - reg: physical base address of the controller and length
> + of memory mapped.
> + - interrupts: interrupt number to the cpu.
> +
> +ohci {
> + compatible = "samsung,exynos-ohci";
> + reg = <0x12120000 0x100>;
> + interrupts = <0 71 0>;
> +};
> +
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
> b/arch/arm/boot/dts/exynos5250.dtsi
> index a3a2eb2..3c73d15 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -58,6 +58,12 @@
> interrupts = <0 42 0>;
> };
>
> + ohci {
> + compatible = "samsung,exynos-ohci";
> + reg = <0x12120000 0x100>;
> + interrupts = <0 71 0>;
> + };
> +
> rtc {
> compatible = "samsung,s3c6410-rtc";
> reg = <0x101E0000 0x100>;
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
> b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index ef770bc..39a4b34 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -15,12 +15,19 @@
> #include <asm/mach/arch.h>
> #include <asm/hardware/gic.h>
> #include <mach/map.h>
> +#include <mach/ohci.h>
>
> #include <plat/cpu.h>
> #include <plat/regs-serial.h>
> +#include <plat/usb-phy.h>
>
> #include "common.h"
>
> +static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
> + .phy_init = s5p_usb_phy_init,
> + .phy_exit = s5p_usb_phy_exit,
> +};
> +
> /*
> * The following lookup table is used to override device names when
> devices
> * are registered from device tree. This is temporarily added to enable
> @@ -56,6 +63,8 @@ static const struct of_dev_auxdata
> exynos5250_auxdata_lookup[] __initconst = {
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
> + OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
A macro would make it more readable instead of this magic number?
> + "exynos-ohci", &smdk5250_ohci_pdata),
> {},
> };
>
> --
> 1.7.0.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/8] EXYNOS4: USB: Generalising setup-usb-phy driver for exynos
2012-07-18 13:45 ` Vivek Gautam
@ 2012-07-19 4:23 ` Pankaj Jangra
-1 siblings, 0 replies; 22+ messages in thread
From: Pankaj Jangra @ 2012-07-19 4:23 UTC (permalink / raw)
To: Vivek Gautam
Cc: kgene.kim, l.majewski, kyungmin.park, thomas.abraham,
linux-samsung-soc, linux-arm-kernel, devicetree-discuss,
m.szyprowski, a.kesavan, yulgon.kim, boyko.lee, av.tikhomirov,
joshi, olofj, prashanth.g
Hi,
On Wed, Jul 18, 2012 at 7:15 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> This patch updates the setup-usb-phy in order to accomodate
> exynos5 support later.
>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>
> diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
> index b81cc56..bfc1367 100644
> --- a/arch/arm/mach-exynos/setup-usb-phy.c
> +++ b/arch/arm/mach-exynos/setup-usb-phy.c
> @@ -26,10 +26,31 @@ static int exynos4_usb_host_phy_is_on(void)
> return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
> }
>
> -static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
> +struct clk *exynos_usb_clock_enable(struct platform_device *pdev)
You might want to make it static struct clk * ?
> +{
> + struct clk *usb_clk = NULL;
> + int err = 0;
> +
> + if (!usb_clk) {
What is the purpose of this condition check? usb_clk will always be
NULL here, right?
> + usb_clk = clk_get(&pdev->dev, "otg");
> + if (IS_ERR(usb_clk)) {
> + dev_err(&pdev->dev, "Failed to get otg clock\n");
> + return NULL;
> + }
Regards,
Pankaj Jangra
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/8] EXYNOS4: USB: Generalising setup-usb-phy driver for exynos
@ 2012-07-19 4:23 ` Pankaj Jangra
0 siblings, 0 replies; 22+ messages in thread
From: Pankaj Jangra @ 2012-07-19 4:23 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Wed, Jul 18, 2012 at 7:15 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> This patch updates the setup-usb-phy in order to accomodate
> exynos5 support later.
>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>
> diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
> index b81cc56..bfc1367 100644
> --- a/arch/arm/mach-exynos/setup-usb-phy.c
> +++ b/arch/arm/mach-exynos/setup-usb-phy.c
> @@ -26,10 +26,31 @@ static int exynos4_usb_host_phy_is_on(void)
> return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
> }
>
> -static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
> +struct clk *exynos_usb_clock_enable(struct platform_device *pdev)
You might want to make it static struct clk * ?
> +{
> + struct clk *usb_clk = NULL;
> + int err = 0;
> +
> + if (!usb_clk) {
What is the purpose of this condition check? usb_clk will always be
NULL here, right?
> + usb_clk = clk_get(&pdev->dev, "otg");
> + if (IS_ERR(usb_clk)) {
> + dev_err(&pdev->dev, "Failed to get otg clock\n");
> + return NULL;
> + }
Regards,
Pankaj Jangra
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2012-07-19 4:23 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-07-18 13:45 [PATCH 0/8] EXYNOS5: USB: Add USB 2.0 and USB 3.0 support for exynos5 Vivek Gautam
2012-07-18 13:45 ` Vivek Gautam
2012-07-18 13:45 ` [PATCH 1/8] EXYNOS4: USB: Generalising setup-usb-phy driver for exynos Vivek Gautam
2012-07-18 13:45 ` Vivek Gautam
2012-07-19 4:23 ` Pankaj Jangra
2012-07-19 4:23 ` Pankaj Jangra
2012-07-18 13:45 ` [PATCH 2/8] ARM: EXYNOS5: Add machine data for USB 2.0 Vivek Gautam
2012-07-18 13:45 ` Vivek Gautam
2012-07-18 13:45 ` [PATCH 3/8] ARM: EXYNOS5: Add OHCI device from device tree Vivek Gautam
2012-07-18 13:45 ` Vivek Gautam
2012-07-19 4:06 ` Sachin Kamat
2012-07-19 4:06 ` Sachin Kamat
2012-07-18 13:45 ` [PATCH 4/8] ARM: EXYNOS5: Add EHCI " Vivek Gautam
2012-07-18 13:45 ` Vivek Gautam
2012-07-18 13:45 ` [PATCH 5/8] ARM: EXYNOS5: Add PHY initialization code for usb 2.0 Vivek Gautam
2012-07-18 13:45 ` Vivek Gautam
2012-07-18 13:45 ` [PATCH 6/8] ARM: EXYNOS5: Add machine data for USB3.0 Vivek Gautam
2012-07-18 13:45 ` Vivek Gautam
2012-07-18 13:45 ` [PATCH 7/8] ARM: EXYNOS5: Add XHCI device from device tree Vivek Gautam
2012-07-18 13:45 ` Vivek Gautam
2012-07-18 13:45 ` [PATCH 8/8] ARM: EXYNOS5: Add PHY initialization code for usb 3.0 Vivek Gautam
2012-07-18 13:45 ` Vivek Gautam
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