* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-07-25 11:07 ` Vaibhav Hiremath
0 siblings, 0 replies; 28+ messages in thread
From: Vaibhav Hiremath @ 2012-07-25 11:07 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, Vaibhav Hiremath, Afzal Mohammed,
Vaibhav Bedia, Paul Walmsley, Benoit Cousson, Tony Lindgren,
Kevin Hilman, Rajendra Nayak
This patch adds HWMOD data for all the peripherals of
AM335X device and also hooks up to the existing OMAP framework.
hwmod data has been already been cleaned up for the recent
changes in clocktree, where all leaf nodes have been removed,
since with modulemode based control, both clock and hwmod
interface does same thing. This reduces the code size to large
extent and also avoids duplication of same control.
So instead of specifying module's leaf node as a main_clk,
now we are relying on parent clock of module's functional clock.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
Due to lack of automated script for generating such a huge hwmod
database file, it takes lot of manual effort and time to generate
this file.
All the patches are also available at (required to boot):
https://github.com/hvaibhav/am335x-linux am335x-upstream-staging
Changes from V2 -
- Add missing terminator for few omap_hwmod_irq_info structures.
- Add missing RTC alarm interrupt number to omap_hwmod_irq_info,
required by driver.
- Add CPSW_WR Address space, required by driver.
Changes from V1 -
- Rebased on top of KevinH's function pointer based approach for
hwmod api's, so that we don't have to put cpu_is_xxx check
for am33xx support.
- migrated to new clocktree changes, where all all leaf nodes
have been removed now.
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/io.c | 2 +
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3381 ++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
4 files changed, 3385 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f6a24b3..b360328 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -194,6 +194,7 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4d2d981..408b3f0 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -523,6 +523,8 @@ void __init am33xx_init_early(void)
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
+ am33xx_hwmod_init();
+ omap_hwmod_init_postsetup();
am33xx_clk_init();
}
#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
new file mode 100644
index 0000000..de7a3ab
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -0,0 +1,3381 @@
+/*
+ * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
+ *
+ * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+#include <plat/gpio.h>
+#include <plat/dma.h>
+#include <plat/mmc.h>
+#include <plat/mcspi.h>
+#include <plat/i2c.h>
+
+#include "omap_hwmod_common_data.h"
+
+#include "control.h"
+#include "cm33xx.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'emif_fw' class
+ * instance(s): emif_fw
+ */
+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
+ .name = "emif_fw",
+};
+
+/* emif_fw */
+static struct omap_hwmod am33xx_emif_fw_hwmod = {
+ .name = "emif_fw",
+ .class = &am33xx_emif_fw_hwmod_class,
+ .clkdm_name = "l4fw_clkdm",
+ .main_clk = "l4fw_gclk",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'emif' class
+ * instance(s): emif
+ */
+static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
+ .rev_offs = 0x0000,
+};
+
+static struct omap_hwmod_class am33xx_emif_hwmod_class = {
+ .name = "emif",
+ .sysc = &am33xx_emif_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
+ { .name = "ddrerr0", .irq = 101 },
+ { .irq = -1 }
+};
+
+/* emif */
+static struct omap_hwmod am33xx_emif_hwmod = {
+ .name = "emif",
+ .class = &am33xx_emif_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_emif_irqs,
+ .main_clk = "dpll_ddr_m2_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_main, l3_s, l3_instr
+ */
+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+ .name = "l3",
+};
+
+/* l3_main (l3_fast) */
+static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
+ { .name = "l3debug", .irq = 9 },
+ { .name = "l3appint", .irq = 10 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_l3_main_hwmod = {
+ .name = "l3_main",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_l3_main_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l3_s */
+static struct omap_hwmod am33xx_l3_s_hwmod = {
+ .name = "l3_s",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+};
+
+/* l3_instr */
+static struct omap_hwmod am33xx_l3_instr_hwmod = {
+ .name = "l3_instr",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
+ */
+static struct omap_hwmod_class am33xx_l4_hwmod_class = {
+ .name = "l4",
+};
+
+/* l4_ls */
+static struct omap_hwmod am33xx_l4_ls_hwmod = {
+ .name = "l4_ls",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_hs */
+static struct omap_hwmod am33xx_l4_hs_hwmod = {
+ .name = "l4_hs",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4hs_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l4hs_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/* l4_wkup */
+static struct omap_hwmod am33xx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_fw */
+static struct omap_hwmod am33xx_l4_fw_hwmod = {
+ .name = "l4_fw",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4fw_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mpu' class
+ */
+static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
+ .name = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
+ { .name = "emuint", .irq = 0 },
+ { .name = "commtx", .irq = 1 },
+ { .name = "commrx", .irq = 2 },
+ { .name = "bench", .irq = 3 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &am33xx_mpu_hwmod_class,
+ .clkdm_name = "mpu_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_mpu_irqs,
+ .main_clk = "dpll_mpu_m2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'wakeup m3' class
+ * Wakeup controller sub-system under wakeup domain
+ */
+static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+ .name = "wkup_m3",
+};
+
+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+ { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+};
+
+static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
+ { .name = "txev", .irq = 78 },
+ { .irq = -1 }
+};
+
+/* wkup_m3 */
+static struct omap_hwmod am33xx_wkup_m3_hwmod = {
+ .name = "wkup_m3",
+ .class = &am33xx_wkup_m3_hwmod_class,
+ .clkdm_name = "l4_wkup_aon_clkdm",
+ .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
+ .mpu_irqs = am33xx_wkup_m3_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_wkup_m3_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
+};
+
+/*
+ * 'pru-icss' class
+ * Programmable Real-Time Unit and Industrial Communication Subsystem
+ */
+static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
+ .name = "pruss",
+};
+
+static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
+ { .name = "pruss", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
+ { .name = "evtout0", .irq = 20 },
+ { .name = "evtout1", .irq = 21 },
+ { .name = "evtout2", .irq = 22 },
+ { .name = "evtout3", .irq = 23 },
+ { .name = "evtout4", .irq = 24 },
+ { .name = "evtout5", .irq = 25 },
+ { .name = "evtout6", .irq = 26 },
+ { .name = "evtout7", .irq = 27 },
+ { .irq = -1 }
+};
+
+/* pru-icss */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod am33xx_pruss_hwmod = {
+ .name = "pruss",
+ .class = &am33xx_pruss_hwmod_class,
+ .clkdm_name = "pruss_ocp_clkdm",
+ .mpu_irqs = am33xx_pruss_irqs,
+ .main_clk = "pruss_ocp_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_pruss_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
+};
+
+/* gfx */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
+ .name = "gfx",
+};
+
+static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
+ { .name = "gfx", .rst_shift = 0 },
+};
+
+static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
+ { .name = "gfxint", .irq = 37 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gfx_hwmod = {
+ .name = "gfx",
+ .class = &am33xx_gfx_hwmod_class,
+ .clkdm_name = "gfx_l3_clkdm",
+ .mpu_irqs = am33xx_gfx_irqs,
+ .main_clk = "gfx_fck_div_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_gfx_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
+};
+
+/*
+ * 'prcm' class
+ * power and reset manager (whole prcm infrastructure)
+ */
+static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
+ .name = "prcm",
+};
+
+/* prcm */
+static struct omap_hwmod am33xx_prcm_hwmod = {
+ .name = "prcm",
+ .class = &am33xx_prcm_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+};
+
+/*
+ * 'adc/tsc' class
+ * TouchScreen Controller (Anolog-To-Digital Converter)
+ */
+static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x10,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
+ .name = "adc_tsc",
+ .sysc = &am33xx_adc_tsc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
+ { .irq = 16 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_adc_tsc_hwmod = {
+ .name = "adc_tsc",
+ .class = &am33xx_adc_tsc_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_adc_tsc_irqs,
+ .main_clk = "adc_tsc_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * Modules omap_hwmod structures
+ *
+ * The following IPs are excluded for the moment because:
+ * - They do not need an explicit SW control using omap_hwmod API.
+ * - They still need to be validated with the driver
+ * properly adapted to omap_hwmod / omap_device
+ *
+ * - cEFUSE (doesn't fall under any ocp_if)
+ * - clkdiv32k
+ * - debugss
+ * - ocmc ram
+ * - ocp watch point
+ * - aes0
+ * - sha0
+ */
+#if 0
+/*
+ * 'cefuse' class
+ */
+static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
+ .name = "cefuse",
+};
+
+static struct omap_hwmod am33xx_cefuse_hwmod = {
+ .name = "cefuse",
+ .class = &am33xx_cefuse_hwmod_class,
+ .clkdm_name = "l4_cefuse_clkdm",
+ .main_clk = "cefuse_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'clkdiv32k' class
+ */
+static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
+ .name = "clkdiv32k",
+};
+
+static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
+ .name = "clkdiv32k",
+ .class = &am33xx_clkdiv32k_hwmod_class,
+ .clkdm_name = "clk_24mhz_clkdm",
+ .main_clk = "clkdiv32k_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'debugss' class
+ * debug sub system
+ */
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+ .name = "debugss",
+};
+
+static struct omap_hwmod am33xx_debugss_hwmod = {
+ .name = "debugss",
+ .class = &am33xx_debugss_hwmod_class,
+ .clkdm_name = "l3_aon_clkdm",
+ .main_clk = "debugss_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+ .name = "ocmcram",
+};
+
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+ .name = "ocmcram",
+ .class = &am33xx_ocmcram_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ocpwp */
+static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
+ .name = "ocpwp",
+};
+
+static struct omap_hwmod am33xx_ocpwp_hwmod = {
+ .name = "ocpwp",
+ .class = &am33xx_ocpwp_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'aes' class
+ */
+static struct omap_hwmod_class am33xx_aes_hwmod_class = {
+ .name = "aes",
+};
+
+static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
+ { .irq = 102 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_aes0_hwmod = {
+ .name = "aes0",
+ .class = &am33xx_aes_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_aes0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* sha0 */
+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+ .name = "sha0",
+};
+
+static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
+ { .irq = 108 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_sha0_hwmod = {
+ .name = "sha0",
+ .class = &am33xx_sha0_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_sha0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+#endif
+
+/* 'smartreflex' class */
+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+ .name = "smartreflex",
+};
+
+/* smartreflex0 */
+static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
+ { .irq = 120 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_smartreflex0_hwmod = {
+ .name = "smartreflex0",
+ .class = &am33xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_smartreflex0_irqs,
+ .main_clk = "smartreflex0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* smartreflex1 */
+static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
+ { .irq = 121 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_smartreflex1_hwmod = {
+ .name = "smartreflex1",
+ .class = &am33xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_smartreflex1_irqs,
+ .main_clk = "smartreflex1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'control' module class
+ */
+static struct omap_hwmod_class am33xx_control_hwmod_class = {
+ .name = "control",
+};
+
+static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
+ { .irq = 8 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_control_hwmod = {
+ .name = "control",
+ .class = &am33xx_control_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_control_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'cpgmac' class
+ * cpsw/cpgmac sub system
+ */
+static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x8,
+ .syss_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+ MSTANDBY_NO),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+ .name = "cpgmac0",
+ .sysc = &am33xx_cpgmac_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
+ { .name = "c0_rx_thresh_pend", .irq = 40 },
+ { .name = "c0_rx_pend", .irq = 41 },
+ { .name = "c0_tx_pend", .irq = 42 },
+ { .name = "c0_misc_pend", .irq = 43 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_cpgmac0_hwmod = {
+ .name = "cpgmac0",
+ .class = &am33xx_cpgmac0_hwmod_class,
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .mpu_irqs = am33xx_cpgmac0_irqs,
+ .main_clk = "cpsw_125mhz_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * dcan class
+ */
+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+ .name = "d_can",
+};
+
+/* dcan0 */
+static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
+ { .name = "d_can_ms", .irq = 52 },
+ { .name = "d_can_mo", .irq = 53 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_dcan0_hwmod = {
+ .name = "d_can0",
+ .class = &am33xx_dcan_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_dcan0_irqs,
+ .main_clk = "dcan0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* dcan1 */
+static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
+ { .name = "d_can_ms", .irq = 55 },
+ { .name = "d_can_mo", .irq = 56 },
+ { .irq = -1 }
+};
+static struct omap_hwmod am33xx_dcan1_hwmod = {
+ .name = "d_can1",
+ .class = &am33xx_dcan_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_dcan1_irqs,
+ .main_clk = "dcan1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* elm */
+static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+ .name = "elm",
+ .sysc = &am33xx_elm_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
+ { .irq = 4 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_elm_hwmod = {
+ .name = "elm",
+ .class = &am33xx_elm_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_elm_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
+ */
+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+ .name = "epwmss",
+ .sysc = &am33xx_epwmss_sysc,
+};
+
+/* ehrpwm0 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
+ { .name = "int", .irq = 86 },
+ { .name = "tzint", .irq = 58 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+ .name = "ehrpwm.0",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm0_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ehrpwm1 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+ { .name = "int", .irq = 87 },
+ { .name = "tzint", .irq = 59 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+ .name = "ehrpwm.1",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ehrpwm2 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+ { .name = "int", .irq = 39 },
+ { .name = "tzint", .irq = 60 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+ .name = "ehrpwm.2",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm2_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap0 */
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+ { .irq = 31 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap0_hwmod = {
+ .name = "ecap.0",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ecap0_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap1 */
+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
+ { .irq = 47 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap1_hwmod = {
+ .name = "ecap.1",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ecap1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap2 */
+static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
+ { .irq = 61 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap2_hwmod = {
+ .name = "ecap.2",
+ .mpu_irqs = am33xx_ecap2_irqs,
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'gpio' class: for gpio 0,1,2,3
+ */
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &am33xx_gpio_sysc,
+ .rev = 2,
+};
+
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio0 */
+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio0_dbclk" },
+};
+
+static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
+ { .irq = 96 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gpio0_hwmod = {
+ .name = "gpio1",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio0_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio0_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
+ { .irq = 98 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio1_hwmod = {
+ .name = "gpio2",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
+ { .irq = 32 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio2_hwmod = {
+ .name = "gpio3",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio2_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
+ { .irq = 62 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio3_hwmod = {
+ .name = "gpio4",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio3_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpmc */
+static struct omap_hwmod_class_sysconfig gpmc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+ .name = "gpmc",
+ .sysc = &gpmc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
+ { .irq = 100 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gpmc_hwmod = {
+ .name = "gpmc",
+ .class = &am33xx_gpmc_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_gpmc_irqs,
+ .main_clk = "l3s_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'i2c' class */
+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0090,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &am33xx_i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_2,
+ .reset = &omap_i2c_reset,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = 70 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &i2c_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_wkupdm_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = 71 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &i2c_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+ { .irq = 30 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &i2c_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = i2c3_mpu_irqs,
+ .sdma_reqs = i2c3_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+
+/* lcdc */
+static struct omap_hwmod_class_sysconfig lcdc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x54,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
+ .name = "lcdc",
+ .sysc = &lcdc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
+ { .irq = 36 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_lcdc_hwmod = {
+ .name = "lcdc",
+ .class = &am33xx_lcdc_hwmod_class,
+ .clkdm_name = "lcdc_clkdm",
+ .mpu_irqs = am33xx_lcdc_irqs,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "lcd_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &am33xx_mailbox_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
+ { .irq = 77 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &am33xx_mailbox_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mailbox_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mcasp' class
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+ .name = "mcasp",
+ .sysc = &am33xx_mcasp_sysc,
+};
+
+/* mcasp0 */
+static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
+ { .name = "ax", .irq = 80, },
+ { .name = "ar", .irq = 81, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
+ { .name = "tx", .dma_req = 8, },
+ { .name = "rx", .dma_req = 9, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp0_hwmod = {
+ .name = "mcasp0",
+ .class = &am33xx_mcasp_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mcasp0_irqs,
+ .sdma_reqs = am33xx_mcasp0_edma_reqs,
+ .main_clk = "mcasp0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp1 */
+static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
+ { .name = "ax", .irq = 82, },
+ { .name = "ar", .irq = 83, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 10, },
+ { .name = "rx", .dma_req = 11, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp1_hwmod = {
+ .name = "mcasp1",
+ .class = &am33xx_mcasp_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mcasp1_irqs,
+ .sdma_reqs = am33xx_mcasp1_edma_reqs,
+ .main_clk = "mcasp1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'mmc' class */
+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+ .rev_offs = 0x1fc,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+ .name = "mmc",
+ .sysc = &am33xx_mmc_sysc,
+};
+
+/* mmc0 */
+static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
+ { .irq = 64 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
+ { .name = "tx", .dma_req = 24, },
+ { .name = "rx", .dma_req = 25, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc0_hwmod = {
+ .name = "mmc1",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mmc0_irqs,
+ .sdma_reqs = am33xx_mmc0_edma_reqs,
+ .main_clk = "mmc_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc0_dev_attr,
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
+ { .irq = 28 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 2, },
+ { .name = "rx", .dma_req = 3, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc1_hwmod = {
+ .name = "mmc2",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mmc1_irqs,
+ .sdma_reqs = am33xx_mmc1_edma_reqs,
+ .main_clk = "mmc_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
+ { .irq = 29 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 64, },
+ { .name = "rx", .dma_req = 65, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc2_hwmod = {
+ .name = "mmc3",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mmc2_irqs,
+ .sdma_reqs = am33xx_mmc2_edma_reqs,
+ .main_clk = "mmc2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc2_dev_attr,
+};
+
+/*
+ * 'rtc' class
+ * rtc subsystem
+ */
+static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
+ .rev_offs = 0x0074,
+ .sysc_offs = 0x0078,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO |
+ SIDLE_SMART | SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+ .name = "rtc",
+ .sysc = &am33xx_rtc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
+ { .name = "rtcint", .irq = 75 },
+ { .name = "rtcalarmint", .irq = 76 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_rtc_hwmod = {
+ .name = "rtc",
+ .class = &am33xx_rtc_hwmod_class,
+ .clkdm_name = "l4_rtc_clkdm",
+ .mpu_irqs = am33xx_rtc_irqs,
+ .main_clk = "clk_32768_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'spi' class */
+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0110,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_spi_hwmod_class = {
+ .name = "mcspi",
+ .sysc = &am33xx_mcspi_sysc,
+ .rev = OMAP4_MCSPI_REV,
+};
+
+/* spi0 */
+static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
+ { .irq = 65 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
+ { .name = "rx0", .dma_req = 17 },
+ { .name = "tx0", .dma_req = 16 },
+ { .name = "rx1", .dma_req = 19 },
+ { .name = "tx1", .dma_req = 18 },
+ { .dma_req = -1 }
+};
+
+static struct omap2_mcspi_dev_attr mcspi_attrib = {
+ .num_chipselect = 2,
+};
+static struct omap_hwmod am33xx_spi0_hwmod = {
+ .name = "spi0",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_spi0_irqs,
+ .sdma_reqs = am33xx_mcspi0_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+/* spi1 */
+static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
+ { .irq = 125 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
+ { .name = "rx0", .dma_req = 43 },
+ { .name = "tx0", .dma_req = 42 },
+ { .name = "rx1", .dma_req = 45 },
+ { .name = "tx1", .dma_req = 44 },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_spi1_hwmod = {
+ .name = "spi1",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_spi1_irqs,
+ .sdma_reqs = am33xx_mcspi1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+/*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the
+ * processes running on multiple processors
+ */
+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+ .name = "spinlock",
+};
+
+static struct omap_hwmod am33xx_spinlock_hwmod = {
+ .name = "spinlock",
+ .class = &am33xx_spinlock_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'timer 2-7' class */
+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &am33xx_timer_sysc,
+};
+
+/* timer1 1ms */
+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &am33xx_timer1ms_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
+ { .irq = 67 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &am33xx_timer1ms_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_timer1_irqs,
+ .main_clk = "timer1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
+ { .irq = 68 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer2_irqs,
+ .main_clk = "timer2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
+ { .irq = 69 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer3_irqs,
+ .main_clk = "timer3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
+ { .irq = 92 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer4_irqs,
+ .main_clk = "timer4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
+ { .irq = 93 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer5_irqs,
+ .main_clk = "timer5_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
+ { .irq = 94 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer6_irqs,
+ .main_clk = "timer6_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
+ { .irq = 95 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer7_irqs,
+ .main_clk = "timer7_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tpcc */
+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+ .name = "tpcc",
+};
+
+static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
+ { .name = "edma0", .irq = 12 },
+ { .name = "edma0_mperr", .irq = 13, },
+ { .name = "edma0_err", .irq = 14 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tpcc_hwmod = {
+ .name = "tpcc",
+ .class = &am33xx_tpcc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tpcc_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+/* 'tptc' class */
+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+ .name = "tptc",
+ .sysc = &am33xx_tptc_sysc,
+};
+
+/* tptc0 */
+static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
+ { .irq = 112 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc0_hwmod = {
+ .name = "tptc0",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc1 */
+static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
+ { .irq = 113 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc1_hwmod = {
+ .name = "tptc1",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc1_irqs,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc2 */
+static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
+ { .irq = 114 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc2_hwmod = {
+ .name = "tptc2",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc2_irqs,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'uart' class */
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+ .rev_offs = 0x50,
+ .sysc_offs = 0x54,
+ .syss_offs = 0x58,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+ .name = "uart",
+ .sysc = &uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 26, },
+ { .name = "rx", .dma_req = 27, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
+ { .irq = 72 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart1_hwmod = {
+ .name = "uart1",
+ .class = &uart_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_uart1_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_wkupdm_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
+ { .irq = 73 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart2_hwmod = {
+ .name = "uart2",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart2_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart3 */
+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 30, },
+ { .name = "rx", .dma_req = 31, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
+ { .irq = 74 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart3_hwmod = {
+ .name = "uart3",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart3_irqs,
+ .sdma_reqs = uart3_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
+ { .irq = 44 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart4_hwmod = {
+ .name = "uart4",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart4_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
+ { .irq = 45 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart5_hwmod = {
+ .name = "uart5",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart5_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
+ { .irq = 46 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart6_hwmod = {
+ .name = "uart6",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart6_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'wd_timer' class */
+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+};
+
+/*
+ * XXX: device.c file uses hardcoded name for watchdog timer
+ * driver "wd_timer2, so we are also using same name as of now...
+ */
+static struct omap_hwmod am33xx_wd_timer1_hwmod = {
+ .name = "wd_timer2",
+ .class = &am33xx_wd_timer_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .main_clk = "wdt1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'usb_otg' class
+ * high-speed on-the-go universal serial bus (usb_otg) controller
+ */
+static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_usbotg_class = {
+ .name = "usbotg",
+ .sysc = &am33xx_usbhsotg_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
+ { .name = "usbss-irq", .irq = 17, },
+ { .name = "musb0-irq", .irq = 18, },
+ { .name = "musb1-irq", .irq = 19, },
+ { .irq = -1, },
+};
+
+static struct omap_hwmod am33xx_usbss_hwmod = {
+ .name = "usb_otg_hs",
+ .class = &am33xx_usbotg_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_usbss_mpu_irqs,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "usbotg_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l4 fw -> emif fw */
+static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
+ .master = &am33xx_l4_fw_hwmod,
+ .slave = &am33xx_emif_fw_hwmod,
+ .clk = "l4fw_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
+ {
+ .pa_start = 0x4c000000,
+ .pa_end = 0x4c000fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+/* l3 main -> emif */
+static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_emif_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_emif_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
+ .master = &am33xx_mpu_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "dpll_mpu_m2_ck",
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> l4 hs */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l4_hs_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 s */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l3_s_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 per/ls */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_ls_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_wkup_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 fw */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_fw_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 instr */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l3_instr_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> prcm */
+static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
+ .master = &am33xx_mpu_hwmod,
+ .slave = &am33xx_prcm_hwmod,
+ .clk = "dpll_mpu_m2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l3 main*/
+static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* pru-icss -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
+ .master = &am33xx_pruss_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "l3_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* wkup m3 -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
+ .master = &am33xx_wkup_m3_hwmod,
+ .slave = &am33xx_l4_wkup_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gfx -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
+ .master = &am33xx_gfx_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> wkup m3 */
+static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
+ {
+ .name = "umem",
+ .pa_start = 0x44d00000,
+ .pa_end = 0x44d00000 + SZ_16K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "dmem",
+ .pa_start = 0x44d80000,
+ .pa_end = 0x44d80000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_wkup_m3_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_wkup_m3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 hs -> pru-icss */
+static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
+ {
+ .pa_start = 0x4a300000,
+ .pa_end = 0x4a300000 + SZ_512K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
+ .master = &am33xx_l4_hs_hwmod,
+ .slave = &am33xx_pruss_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_pruss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> gfx */
+static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
+ {
+ .pa_start = 0x56000000,
+ .pa_end = 0x56000000 + SZ_16M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_gfx_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_gfx_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> smartreflex0 */
+static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
+ {
+ .pa_start = 0x44e37000,
+ .pa_end = 0x44e37000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_smartreflex0_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_smartreflex0_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> smartreflex1 */
+static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
+ {
+ .pa_start = 0x44e39000,
+ .pa_end = 0x44e39000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_smartreflex1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_smartreflex1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> control */
+static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
+ {
+ .pa_start = 0x44e10000,
+ .pa_end = 0x44e10000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_control_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_control_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> rtc */
+static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
+ {
+ .pa_start = 0x44e3e000,
+ .pa_end = 0x44e3e000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_rtc_hwmod,
+ .clk = "clkdiv32k_ick",
+ .addr = am33xx_rtc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per/ls -> DCAN0 */
+static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
+ {
+ .pa_start = 0x481CC000,
+ .pa_end = 0x481CC000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_dcan0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_dcan0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> DCAN1 */
+static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
+ {
+ .pa_start = 0x481D0000,
+ .pa_end = 0x481D0000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_dcan1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_dcan1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> GPIO2 */
+static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
+ {
+ .pa_start = 0x4804C000,
+ .pa_end = 0x4804C000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio3 */
+static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
+ {
+ .pa_start = 0x481AC000,
+ .pa_end = 0x481AC000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio4 */
+static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
+ {
+ .pa_start = 0x481AE000,
+ .pa_end = 0x481AE000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> I2C1 */
+static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
+ {
+ .pa_start = 0x44E0B000,
+ .pa_end = 0x44E0B000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_i2c1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_i2c1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* L4 WKUP -> GPIO1 */
+static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
+ {
+ .pa_start = 0x44E07000,
+ .pa_end = 0x44E07000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_gpio0_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_gpio0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> ADC_TSC */
+static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
+ {
+ .pa_start = 0x44E0D000,
+ .pa_end = 0x44E0D000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_adc_tsc_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_adc_tsc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+ /* cpsw ss */
+ {
+ .pa_start = 0x4a100000,
+ .pa_end = 0x4a100000 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ /* cpsw wr */
+ {
+ .pa_start = 0x4a101200,
+ .pa_end = 0x4a101200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
+ .master = &am33xx_l4_hs_hwmod,
+ .slave = &am33xx_cpgmac0_hwmod,
+ .clk = "cpsw_125mhz_gclk",
+ .addr = am33xx_cpgmac0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
+ {
+ .pa_start = 0x48080000,
+ .pa_end = 0x48080000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_elm_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_elm_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
+ {
+ .pa_start = 0x48300000,
+ .pa_end = 0x48300000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48300200,
+ .pa_end = 0x48300200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
+ {
+ .pa_start = 0x48302000,
+ .pa_end = 0x48302000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48302200,
+ .pa_end = 0x48302200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+ {
+ .pa_start = 0x48304000,
+ .pa_end = 0x48304000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48304200,
+ .pa_end = 0x48304200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
+ {
+ .pa_start = 0x48300000,
+ .pa_end = 0x48300000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48300100,
+ .pa_end = 0x48300100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
+ {
+ .pa_start = 0x48302000,
+ .pa_end = 0x48302000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48302100,
+ .pa_end = 0x48302100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+ {
+ .pa_start = 0x48304000,
+ .pa_end = 0x48304000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48304100,
+ .pa_end = 0x48304100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3s cfg -> gpmc */
+static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
+ {
+ .pa_start = 0x50000000,
+ .pa_end = 0x50000000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_gpmc_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_gpmc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* i2c2 */
+static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
+ {
+ .pa_start = 0x4802A000,
+ .pa_end = 0x4802A000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_i2c2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_i2c2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
+ {
+ .pa_start = 0x4819C000,
+ .pa_end = 0x4819C000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_i2c3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_i2c3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
+ {
+ .pa_start = 0x4830E000,
+ .pa_end = 0x4830E000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_lcdc_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_lcdc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x480C8000,
+ .pa_end = 0x480C8000 + (SZ_4K - 1),
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4 ls -> mailbox */
+static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mailbox_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mailbox_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> spinlock */
+static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
+ {
+ .pa_start = 0x480Ca000,
+ .pa_end = 0x480Ca000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spinlock_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_spinlock_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcasp0 */
+static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
+ {
+ .pa_start = 0x48038000,
+ .pa_end = 0x48038000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mcasp0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcasp0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp0 data */
+static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
+ {
+ .pa_start = 0x46000000,
+ .pa_end = 0x46000000 + SZ_4M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mcasp0_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mcasp0_data_addr_space,
+ .user = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mcasp1 */
+static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
+ {
+ .pa_start = 0x4803C000,
+ .pa_end = 0x4803C000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mcasp1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcasp1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp1 data */
+static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
+ {
+ .pa_start = 0x46400000,
+ .pa_end = 0x46400000 + SZ_4M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mcasp1_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mcasp1_data_addr_space,
+ .user = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mmc0 */
+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+ {
+ .pa_start = 0x48060100,
+ .pa_end = 0x48060100 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mmc0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mmc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mmc1 */
+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+ {
+ .pa_start = 0x481d8100,
+ .pa_end = 0x481d8100 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mmc1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mmc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mmc2 */
+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+ {
+ .pa_start = 0x47810100,
+ .pa_end = 0x47810100 + SZ_64K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mmc2_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mmc2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi0 */
+static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
+ {
+ .pa_start = 0x48030000,
+ .pa_end = 0x48030000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spi0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcspi0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi1 */
+static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
+ {
+ .pa_start = 0x481A0000,
+ .pa_end = 0x481A0000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spi1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcspi1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> timer1 */
+static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
+ {
+ .pa_start = 0x44E31000,
+ .pa_end = 0x44E31000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_timer1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_timer1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer2 */
+static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
+ {
+ .pa_start = 0x48040000,
+ .pa_end = 0x48040000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer3 */
+static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
+ {
+ .pa_start = 0x48042000,
+ .pa_end = 0x48042000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer4 */
+static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
+ {
+ .pa_start = 0x48044000,
+ .pa_end = 0x48044000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer4_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer4_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer5 */
+static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
+ {
+ .pa_start = 0x48046000,
+ .pa_end = 0x48046000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer5_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer5_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer6 */
+static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
+ {
+ .pa_start = 0x48048000,
+ .pa_end = 0x48048000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer6_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer6_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer7 */
+static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
+ {
+ .pa_start = 0x4804A000,
+ .pa_end = 0x4804A000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer7_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer7_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc */
+static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
+ {
+ .pa_start = 0x49000000,
+ .pa_end = 0x49000000 + SZ_32K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tpcc_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tpcc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc0 */
+static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
+ {
+ .pa_start = 0x49800000,
+ .pa_end = 0x49800000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc0_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc1 */
+static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
+ {
+ .pa_start = 0x49900000,
+ .pa_end = 0x49900000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc1_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc2 */
+static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
+ {
+ .pa_start = 0x49a00000,
+ .pa_end = 0x49a00000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc2_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> uart1 */
+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
+ {
+ .pa_start = 0x44E09000,
+ .pa_end = 0x44E09000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_uart1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_uart1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart2 */
+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
+ {
+ .pa_start = 0x48022000,
+ .pa_end = 0x48022000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart3 */
+static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
+ {
+ .pa_start = 0x48024000,
+ .pa_end = 0x48024000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart4 */
+static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
+ {
+ .pa_start = 0x481A6000,
+ .pa_end = 0x481A6000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart4_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart4_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart5 */
+static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
+ {
+ .pa_start = 0x481A8000,
+ .pa_end = 0x481A8000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart5_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart5_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart6 */
+static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
+ {
+ .pa_start = 0x481aa000,
+ .pa_end = 0x481aa000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart6_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart6_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> wd_timer1 */
+static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
+ {
+ .pa_start = 0x44e35000,
+ .pa_end = 0x44e35000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_wd_timer1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_wd_timer1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* usbss */
+/* l3 s -> USBSS interface */
+static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
+ {
+ .name = "usbss",
+ .pa_start = 0x47400000,
+ .pa_end = 0x47400000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb0",
+ .pa_start = 0x47401000,
+ .pa_end = 0x47401000 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb1",
+ .pa_start = 0x47401800,
+ .pa_end = 0x47401800 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_usbss_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_usbss_addr_space,
+ .user = OCP_USER_MPU,
+ .flags = OCPIF_SWSUP_IDLE,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
+ &am33xx_l4_fw__emif_fw,
+ &am33xx_l3_main__emif,
+ &am33xx_mpu__l3_main,
+ &am33xx_mpu__prcm,
+ &am33xx_l3_s__l4_ls,
+ &am33xx_l3_s__l4_wkup,
+ &am33xx_l3_s__l4_fw,
+ &am33xx_l3_main__l4_hs,
+ &am33xx_l3_main__l3_s,
+ &am33xx_l3_main__l3_instr,
+ &am33xx_l3_main__gfx,
+ &am33xx_l3_s__l3_main,
+ &am33xx_pruss__l3_main,
+ &am33xx_wkup_m3__l4_wkup,
+ &am33xx_gfx__l3_main,
+ &am33xx_l4_wkup__wkup_m3,
+ &am33xx_l4_wkup__control,
+ &am33xx_l4_wkup__smartreflex0,
+ &am33xx_l4_wkup__smartreflex1,
+ &am33xx_l4_wkup__uart1,
+ &am33xx_l4_wkup__timer1,
+ &am33xx_l4_wkup__rtc,
+ &am33xx_l4_wkup__i2c1,
+ &am33xx_l4_wkup__gpio0,
+ &am33xx_l4_wkup__adc_tsc,
+ &am33xx_l4_wkup__wd_timer1,
+ &am33xx_l4_hs__pruss,
+ &am33xx_l4_per__dcan0,
+ &am33xx_l4_per__dcan1,
+ &am33xx_l4_per__gpio1,
+ &am33xx_l4_per__gpio2,
+ &am33xx_l4_per__gpio3,
+ &am33xx_l4_per__i2c2,
+ &am33xx_l4_per__i2c3,
+ &am33xx_l4_per__mailbox,
+ &am33xx_l4_ls__mcasp0,
+ &am33xx_l3_s__mcasp0_data,
+ &am33xx_l4_ls__mcasp1,
+ &am33xx_l3_s__mcasp1_data,
+ &am33xx_l4_ls__mmc0,
+ &am33xx_l4_ls__mmc1,
+ &am33xx_l3_s__mmc2,
+ &am33xx_l4_ls__timer2,
+ &am33xx_l4_ls__timer3,
+ &am33xx_l4_ls__timer4,
+ &am33xx_l4_ls__timer5,
+ &am33xx_l4_ls__timer6,
+ &am33xx_l4_ls__timer7,
+ &am33xx_l3_main__tpcc,
+ &am33xx_l4_ls__uart2,
+ &am33xx_l4_ls__uart3,
+ &am33xx_l4_ls__uart4,
+ &am33xx_l4_ls__uart5,
+ &am33xx_l4_ls__uart6,
+ &am33xx_l4_ls__spinlock,
+ &am33xx_l4_ls__elm,
+ &am33xx_l4_ls__ehrpwm0,
+ &am33xx_l4_ls__ehrpwm1,
+ &am33xx_l4_ls__ehrpwm2,
+ &am33xx_l4_ls__ecap0,
+ &am33xx_l4_ls__ecap1,
+ &am33xx_l4_ls__ecap2,
+ &am33xx_l3_s__gpmc,
+ &am33xx_l3_main__lcdc,
+ &am33xx_l4_ls__mcspi0,
+ &am33xx_l4_ls__mcspi1,
+ &am33xx_l3_main__tptc0,
+ &am33xx_l3_main__tptc1,
+ &am33xx_l3_main__tptc2,
+ &am33xx_l3_s__usbss,
+ &am33xx_l4_hs__cpgmac0,
+ NULL,
+};
+
+int __init am33xx_hwmod_init(void)
+{
+ omap_hwmod_init();
+ return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 6132972..9b9646c 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -658,6 +658,7 @@ extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
+extern int am33xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-07-25 11:07 ` Vaibhav Hiremath
0 siblings, 0 replies; 28+ messages in thread
From: Vaibhav Hiremath @ 2012-07-25 11:07 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds HWMOD data for all the peripherals of
AM335X device and also hooks up to the existing OMAP framework.
hwmod data has been already been cleaned up for the recent
changes in clocktree, where all leaf nodes have been removed,
since with modulemode based control, both clock and hwmod
interface does same thing. This reduces the code size to large
extent and also avoids duplication of same control.
So instead of specifying module's leaf node as a main_clk,
now we are relying on parent clock of module's functional clock.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
Due to lack of automated script for generating such a huge hwmod
database file, it takes lot of manual effort and time to generate
this file.
All the patches are also available at (required to boot):
https://github.com/hvaibhav/am335x-linux am335x-upstream-staging
Changes from V2 -
- Add missing terminator for few omap_hwmod_irq_info structures.
- Add missing RTC alarm interrupt number to omap_hwmod_irq_info,
required by driver.
- Add CPSW_WR Address space, required by driver.
Changes from V1 -
- Rebased on top of KevinH's function pointer based approach for
hwmod api's, so that we don't have to put cpu_is_xxx check
for am33xx support.
- migrated to new clocktree changes, where all all leaf nodes
have been removed now.
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/io.c | 2 +
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3381 ++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
4 files changed, 3385 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f6a24b3..b360328 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -194,6 +194,7 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4d2d981..408b3f0 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -523,6 +523,8 @@ void __init am33xx_init_early(void)
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
+ am33xx_hwmod_init();
+ omap_hwmod_init_postsetup();
am33xx_clk_init();
}
#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
new file mode 100644
index 0000000..de7a3ab
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -0,0 +1,3381 @@
+/*
+ * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
+ *
+ * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+#include <plat/gpio.h>
+#include <plat/dma.h>
+#include <plat/mmc.h>
+#include <plat/mcspi.h>
+#include <plat/i2c.h>
+
+#include "omap_hwmod_common_data.h"
+
+#include "control.h"
+#include "cm33xx.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'emif_fw' class
+ * instance(s): emif_fw
+ */
+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
+ .name = "emif_fw",
+};
+
+/* emif_fw */
+static struct omap_hwmod am33xx_emif_fw_hwmod = {
+ .name = "emif_fw",
+ .class = &am33xx_emif_fw_hwmod_class,
+ .clkdm_name = "l4fw_clkdm",
+ .main_clk = "l4fw_gclk",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'emif' class
+ * instance(s): emif
+ */
+static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
+ .rev_offs = 0x0000,
+};
+
+static struct omap_hwmod_class am33xx_emif_hwmod_class = {
+ .name = "emif",
+ .sysc = &am33xx_emif_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
+ { .name = "ddrerr0", .irq = 101 },
+ { .irq = -1 }
+};
+
+/* emif */
+static struct omap_hwmod am33xx_emif_hwmod = {
+ .name = "emif",
+ .class = &am33xx_emif_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_emif_irqs,
+ .main_clk = "dpll_ddr_m2_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_main, l3_s, l3_instr
+ */
+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+ .name = "l3",
+};
+
+/* l3_main (l3_fast) */
+static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
+ { .name = "l3debug", .irq = 9 },
+ { .name = "l3appint", .irq = 10 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_l3_main_hwmod = {
+ .name = "l3_main",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_l3_main_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l3_s */
+static struct omap_hwmod am33xx_l3_s_hwmod = {
+ .name = "l3_s",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+};
+
+/* l3_instr */
+static struct omap_hwmod am33xx_l3_instr_hwmod = {
+ .name = "l3_instr",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
+ */
+static struct omap_hwmod_class am33xx_l4_hwmod_class = {
+ .name = "l4",
+};
+
+/* l4_ls */
+static struct omap_hwmod am33xx_l4_ls_hwmod = {
+ .name = "l4_ls",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_hs */
+static struct omap_hwmod am33xx_l4_hs_hwmod = {
+ .name = "l4_hs",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4hs_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l4hs_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/* l4_wkup */
+static struct omap_hwmod am33xx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_fw */
+static struct omap_hwmod am33xx_l4_fw_hwmod = {
+ .name = "l4_fw",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4fw_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mpu' class
+ */
+static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
+ .name = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
+ { .name = "emuint", .irq = 0 },
+ { .name = "commtx", .irq = 1 },
+ { .name = "commrx", .irq = 2 },
+ { .name = "bench", .irq = 3 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &am33xx_mpu_hwmod_class,
+ .clkdm_name = "mpu_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_mpu_irqs,
+ .main_clk = "dpll_mpu_m2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'wakeup m3' class
+ * Wakeup controller sub-system under wakeup domain
+ */
+static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+ .name = "wkup_m3",
+};
+
+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+ { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+};
+
+static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
+ { .name = "txev", .irq = 78 },
+ { .irq = -1 }
+};
+
+/* wkup_m3 */
+static struct omap_hwmod am33xx_wkup_m3_hwmod = {
+ .name = "wkup_m3",
+ .class = &am33xx_wkup_m3_hwmod_class,
+ .clkdm_name = "l4_wkup_aon_clkdm",
+ .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
+ .mpu_irqs = am33xx_wkup_m3_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_wkup_m3_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
+};
+
+/*
+ * 'pru-icss' class
+ * Programmable Real-Time Unit and Industrial Communication Subsystem
+ */
+static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
+ .name = "pruss",
+};
+
+static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
+ { .name = "pruss", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
+ { .name = "evtout0", .irq = 20 },
+ { .name = "evtout1", .irq = 21 },
+ { .name = "evtout2", .irq = 22 },
+ { .name = "evtout3", .irq = 23 },
+ { .name = "evtout4", .irq = 24 },
+ { .name = "evtout5", .irq = 25 },
+ { .name = "evtout6", .irq = 26 },
+ { .name = "evtout7", .irq = 27 },
+ { .irq = -1 }
+};
+
+/* pru-icss */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod am33xx_pruss_hwmod = {
+ .name = "pruss",
+ .class = &am33xx_pruss_hwmod_class,
+ .clkdm_name = "pruss_ocp_clkdm",
+ .mpu_irqs = am33xx_pruss_irqs,
+ .main_clk = "pruss_ocp_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_pruss_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
+};
+
+/* gfx */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
+ .name = "gfx",
+};
+
+static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
+ { .name = "gfx", .rst_shift = 0 },
+};
+
+static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
+ { .name = "gfxint", .irq = 37 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gfx_hwmod = {
+ .name = "gfx",
+ .class = &am33xx_gfx_hwmod_class,
+ .clkdm_name = "gfx_l3_clkdm",
+ .mpu_irqs = am33xx_gfx_irqs,
+ .main_clk = "gfx_fck_div_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_gfx_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
+};
+
+/*
+ * 'prcm' class
+ * power and reset manager (whole prcm infrastructure)
+ */
+static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
+ .name = "prcm",
+};
+
+/* prcm */
+static struct omap_hwmod am33xx_prcm_hwmod = {
+ .name = "prcm",
+ .class = &am33xx_prcm_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+};
+
+/*
+ * 'adc/tsc' class
+ * TouchScreen Controller (Anolog-To-Digital Converter)
+ */
+static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x10,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
+ .name = "adc_tsc",
+ .sysc = &am33xx_adc_tsc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
+ { .irq = 16 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_adc_tsc_hwmod = {
+ .name = "adc_tsc",
+ .class = &am33xx_adc_tsc_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_adc_tsc_irqs,
+ .main_clk = "adc_tsc_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * Modules omap_hwmod structures
+ *
+ * The following IPs are excluded for the moment because:
+ * - They do not need an explicit SW control using omap_hwmod API.
+ * - They still need to be validated with the driver
+ * properly adapted to omap_hwmod / omap_device
+ *
+ * - cEFUSE (doesn't fall under any ocp_if)
+ * - clkdiv32k
+ * - debugss
+ * - ocmc ram
+ * - ocp watch point
+ * - aes0
+ * - sha0
+ */
+#if 0
+/*
+ * 'cefuse' class
+ */
+static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
+ .name = "cefuse",
+};
+
+static struct omap_hwmod am33xx_cefuse_hwmod = {
+ .name = "cefuse",
+ .class = &am33xx_cefuse_hwmod_class,
+ .clkdm_name = "l4_cefuse_clkdm",
+ .main_clk = "cefuse_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'clkdiv32k' class
+ */
+static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
+ .name = "clkdiv32k",
+};
+
+static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
+ .name = "clkdiv32k",
+ .class = &am33xx_clkdiv32k_hwmod_class,
+ .clkdm_name = "clk_24mhz_clkdm",
+ .main_clk = "clkdiv32k_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'debugss' class
+ * debug sub system
+ */
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+ .name = "debugss",
+};
+
+static struct omap_hwmod am33xx_debugss_hwmod = {
+ .name = "debugss",
+ .class = &am33xx_debugss_hwmod_class,
+ .clkdm_name = "l3_aon_clkdm",
+ .main_clk = "debugss_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+ .name = "ocmcram",
+};
+
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+ .name = "ocmcram",
+ .class = &am33xx_ocmcram_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ocpwp */
+static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
+ .name = "ocpwp",
+};
+
+static struct omap_hwmod am33xx_ocpwp_hwmod = {
+ .name = "ocpwp",
+ .class = &am33xx_ocpwp_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'aes' class
+ */
+static struct omap_hwmod_class am33xx_aes_hwmod_class = {
+ .name = "aes",
+};
+
+static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
+ { .irq = 102 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_aes0_hwmod = {
+ .name = "aes0",
+ .class = &am33xx_aes_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_aes0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* sha0 */
+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+ .name = "sha0",
+};
+
+static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
+ { .irq = 108 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_sha0_hwmod = {
+ .name = "sha0",
+ .class = &am33xx_sha0_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_sha0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+#endif
+
+/* 'smartreflex' class */
+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+ .name = "smartreflex",
+};
+
+/* smartreflex0 */
+static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
+ { .irq = 120 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_smartreflex0_hwmod = {
+ .name = "smartreflex0",
+ .class = &am33xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_smartreflex0_irqs,
+ .main_clk = "smartreflex0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* smartreflex1 */
+static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
+ { .irq = 121 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_smartreflex1_hwmod = {
+ .name = "smartreflex1",
+ .class = &am33xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_smartreflex1_irqs,
+ .main_clk = "smartreflex1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'control' module class
+ */
+static struct omap_hwmod_class am33xx_control_hwmod_class = {
+ .name = "control",
+};
+
+static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
+ { .irq = 8 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_control_hwmod = {
+ .name = "control",
+ .class = &am33xx_control_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_control_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'cpgmac' class
+ * cpsw/cpgmac sub system
+ */
+static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x8,
+ .syss_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+ MSTANDBY_NO),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+ .name = "cpgmac0",
+ .sysc = &am33xx_cpgmac_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
+ { .name = "c0_rx_thresh_pend", .irq = 40 },
+ { .name = "c0_rx_pend", .irq = 41 },
+ { .name = "c0_tx_pend", .irq = 42 },
+ { .name = "c0_misc_pend", .irq = 43 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_cpgmac0_hwmod = {
+ .name = "cpgmac0",
+ .class = &am33xx_cpgmac0_hwmod_class,
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .mpu_irqs = am33xx_cpgmac0_irqs,
+ .main_clk = "cpsw_125mhz_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * dcan class
+ */
+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+ .name = "d_can",
+};
+
+/* dcan0 */
+static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
+ { .name = "d_can_ms", .irq = 52 },
+ { .name = "d_can_mo", .irq = 53 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_dcan0_hwmod = {
+ .name = "d_can0",
+ .class = &am33xx_dcan_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_dcan0_irqs,
+ .main_clk = "dcan0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* dcan1 */
+static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
+ { .name = "d_can_ms", .irq = 55 },
+ { .name = "d_can_mo", .irq = 56 },
+ { .irq = -1 }
+};
+static struct omap_hwmod am33xx_dcan1_hwmod = {
+ .name = "d_can1",
+ .class = &am33xx_dcan_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_dcan1_irqs,
+ .main_clk = "dcan1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* elm */
+static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+ .name = "elm",
+ .sysc = &am33xx_elm_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
+ { .irq = 4 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_elm_hwmod = {
+ .name = "elm",
+ .class = &am33xx_elm_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_elm_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
+ */
+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+ .name = "epwmss",
+ .sysc = &am33xx_epwmss_sysc,
+};
+
+/* ehrpwm0 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
+ { .name = "int", .irq = 86 },
+ { .name = "tzint", .irq = 58 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+ .name = "ehrpwm.0",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm0_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ehrpwm1 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+ { .name = "int", .irq = 87 },
+ { .name = "tzint", .irq = 59 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+ .name = "ehrpwm.1",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ehrpwm2 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+ { .name = "int", .irq = 39 },
+ { .name = "tzint", .irq = 60 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+ .name = "ehrpwm.2",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm2_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap0 */
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+ { .irq = 31 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap0_hwmod = {
+ .name = "ecap.0",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ecap0_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap1 */
+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
+ { .irq = 47 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap1_hwmod = {
+ .name = "ecap.1",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ecap1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap2 */
+static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
+ { .irq = 61 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap2_hwmod = {
+ .name = "ecap.2",
+ .mpu_irqs = am33xx_ecap2_irqs,
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'gpio' class: for gpio 0,1,2,3
+ */
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &am33xx_gpio_sysc,
+ .rev = 2,
+};
+
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio0 */
+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio0_dbclk" },
+};
+
+static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
+ { .irq = 96 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gpio0_hwmod = {
+ .name = "gpio1",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio0_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio0_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
+ { .irq = 98 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio1_hwmod = {
+ .name = "gpio2",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
+ { .irq = 32 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio2_hwmod = {
+ .name = "gpio3",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio2_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
+ { .irq = 62 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio3_hwmod = {
+ .name = "gpio4",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio3_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpmc */
+static struct omap_hwmod_class_sysconfig gpmc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+ .name = "gpmc",
+ .sysc = &gpmc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
+ { .irq = 100 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gpmc_hwmod = {
+ .name = "gpmc",
+ .class = &am33xx_gpmc_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_gpmc_irqs,
+ .main_clk = "l3s_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'i2c' class */
+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0090,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &am33xx_i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_2,
+ .reset = &omap_i2c_reset,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = 70 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &i2c_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_wkupdm_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = 71 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &i2c_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+ { .irq = 30 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &i2c_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = i2c3_mpu_irqs,
+ .sdma_reqs = i2c3_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+
+/* lcdc */
+static struct omap_hwmod_class_sysconfig lcdc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x54,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
+ .name = "lcdc",
+ .sysc = &lcdc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
+ { .irq = 36 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_lcdc_hwmod = {
+ .name = "lcdc",
+ .class = &am33xx_lcdc_hwmod_class,
+ .clkdm_name = "lcdc_clkdm",
+ .mpu_irqs = am33xx_lcdc_irqs,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "lcd_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &am33xx_mailbox_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
+ { .irq = 77 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &am33xx_mailbox_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mailbox_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mcasp' class
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+ .name = "mcasp",
+ .sysc = &am33xx_mcasp_sysc,
+};
+
+/* mcasp0 */
+static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
+ { .name = "ax", .irq = 80, },
+ { .name = "ar", .irq = 81, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
+ { .name = "tx", .dma_req = 8, },
+ { .name = "rx", .dma_req = 9, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp0_hwmod = {
+ .name = "mcasp0",
+ .class = &am33xx_mcasp_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mcasp0_irqs,
+ .sdma_reqs = am33xx_mcasp0_edma_reqs,
+ .main_clk = "mcasp0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp1 */
+static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
+ { .name = "ax", .irq = 82, },
+ { .name = "ar", .irq = 83, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 10, },
+ { .name = "rx", .dma_req = 11, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp1_hwmod = {
+ .name = "mcasp1",
+ .class = &am33xx_mcasp_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mcasp1_irqs,
+ .sdma_reqs = am33xx_mcasp1_edma_reqs,
+ .main_clk = "mcasp1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'mmc' class */
+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+ .rev_offs = 0x1fc,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+ .name = "mmc",
+ .sysc = &am33xx_mmc_sysc,
+};
+
+/* mmc0 */
+static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
+ { .irq = 64 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
+ { .name = "tx", .dma_req = 24, },
+ { .name = "rx", .dma_req = 25, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc0_hwmod = {
+ .name = "mmc1",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mmc0_irqs,
+ .sdma_reqs = am33xx_mmc0_edma_reqs,
+ .main_clk = "mmc_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc0_dev_attr,
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
+ { .irq = 28 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 2, },
+ { .name = "rx", .dma_req = 3, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc1_hwmod = {
+ .name = "mmc2",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mmc1_irqs,
+ .sdma_reqs = am33xx_mmc1_edma_reqs,
+ .main_clk = "mmc_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
+ { .irq = 29 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 64, },
+ { .name = "rx", .dma_req = 65, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc2_hwmod = {
+ .name = "mmc3",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mmc2_irqs,
+ .sdma_reqs = am33xx_mmc2_edma_reqs,
+ .main_clk = "mmc2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc2_dev_attr,
+};
+
+/*
+ * 'rtc' class
+ * rtc subsystem
+ */
+static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
+ .rev_offs = 0x0074,
+ .sysc_offs = 0x0078,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO |
+ SIDLE_SMART | SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+ .name = "rtc",
+ .sysc = &am33xx_rtc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
+ { .name = "rtcint", .irq = 75 },
+ { .name = "rtcalarmint", .irq = 76 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_rtc_hwmod = {
+ .name = "rtc",
+ .class = &am33xx_rtc_hwmod_class,
+ .clkdm_name = "l4_rtc_clkdm",
+ .mpu_irqs = am33xx_rtc_irqs,
+ .main_clk = "clk_32768_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'spi' class */
+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0110,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_spi_hwmod_class = {
+ .name = "mcspi",
+ .sysc = &am33xx_mcspi_sysc,
+ .rev = OMAP4_MCSPI_REV,
+};
+
+/* spi0 */
+static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
+ { .irq = 65 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
+ { .name = "rx0", .dma_req = 17 },
+ { .name = "tx0", .dma_req = 16 },
+ { .name = "rx1", .dma_req = 19 },
+ { .name = "tx1", .dma_req = 18 },
+ { .dma_req = -1 }
+};
+
+static struct omap2_mcspi_dev_attr mcspi_attrib = {
+ .num_chipselect = 2,
+};
+static struct omap_hwmod am33xx_spi0_hwmod = {
+ .name = "spi0",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_spi0_irqs,
+ .sdma_reqs = am33xx_mcspi0_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+/* spi1 */
+static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
+ { .irq = 125 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
+ { .name = "rx0", .dma_req = 43 },
+ { .name = "tx0", .dma_req = 42 },
+ { .name = "rx1", .dma_req = 45 },
+ { .name = "tx1", .dma_req = 44 },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_spi1_hwmod = {
+ .name = "spi1",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_spi1_irqs,
+ .sdma_reqs = am33xx_mcspi1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+/*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the
+ * processes running on multiple processors
+ */
+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+ .name = "spinlock",
+};
+
+static struct omap_hwmod am33xx_spinlock_hwmod = {
+ .name = "spinlock",
+ .class = &am33xx_spinlock_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'timer 2-7' class */
+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &am33xx_timer_sysc,
+};
+
+/* timer1 1ms */
+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &am33xx_timer1ms_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
+ { .irq = 67 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &am33xx_timer1ms_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_timer1_irqs,
+ .main_clk = "timer1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
+ { .irq = 68 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer2_irqs,
+ .main_clk = "timer2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
+ { .irq = 69 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer3_irqs,
+ .main_clk = "timer3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
+ { .irq = 92 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer4_irqs,
+ .main_clk = "timer4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
+ { .irq = 93 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer5_irqs,
+ .main_clk = "timer5_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
+ { .irq = 94 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer6_irqs,
+ .main_clk = "timer6_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
+ { .irq = 95 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer7_irqs,
+ .main_clk = "timer7_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tpcc */
+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+ .name = "tpcc",
+};
+
+static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
+ { .name = "edma0", .irq = 12 },
+ { .name = "edma0_mperr", .irq = 13, },
+ { .name = "edma0_err", .irq = 14 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tpcc_hwmod = {
+ .name = "tpcc",
+ .class = &am33xx_tpcc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tpcc_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+/* 'tptc' class */
+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+ .name = "tptc",
+ .sysc = &am33xx_tptc_sysc,
+};
+
+/* tptc0 */
+static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
+ { .irq = 112 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc0_hwmod = {
+ .name = "tptc0",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc1 */
+static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
+ { .irq = 113 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc1_hwmod = {
+ .name = "tptc1",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc1_irqs,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc2 */
+static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
+ { .irq = 114 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc2_hwmod = {
+ .name = "tptc2",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc2_irqs,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'uart' class */
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+ .rev_offs = 0x50,
+ .sysc_offs = 0x54,
+ .syss_offs = 0x58,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+ .name = "uart",
+ .sysc = &uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 26, },
+ { .name = "rx", .dma_req = 27, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
+ { .irq = 72 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart1_hwmod = {
+ .name = "uart1",
+ .class = &uart_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_uart1_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_wkupdm_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
+ { .irq = 73 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart2_hwmod = {
+ .name = "uart2",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart2_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart3 */
+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 30, },
+ { .name = "rx", .dma_req = 31, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
+ { .irq = 74 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart3_hwmod = {
+ .name = "uart3",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart3_irqs,
+ .sdma_reqs = uart3_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
+ { .irq = 44 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart4_hwmod = {
+ .name = "uart4",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart4_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
+ { .irq = 45 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart5_hwmod = {
+ .name = "uart5",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart5_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
+ { .irq = 46 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart6_hwmod = {
+ .name = "uart6",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart6_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'wd_timer' class */
+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+};
+
+/*
+ * XXX: device.c file uses hardcoded name for watchdog timer
+ * driver "wd_timer2, so we are also using same name as of now...
+ */
+static struct omap_hwmod am33xx_wd_timer1_hwmod = {
+ .name = "wd_timer2",
+ .class = &am33xx_wd_timer_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .main_clk = "wdt1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'usb_otg' class
+ * high-speed on-the-go universal serial bus (usb_otg) controller
+ */
+static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_usbotg_class = {
+ .name = "usbotg",
+ .sysc = &am33xx_usbhsotg_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
+ { .name = "usbss-irq", .irq = 17, },
+ { .name = "musb0-irq", .irq = 18, },
+ { .name = "musb1-irq", .irq = 19, },
+ { .irq = -1, },
+};
+
+static struct omap_hwmod am33xx_usbss_hwmod = {
+ .name = "usb_otg_hs",
+ .class = &am33xx_usbotg_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_usbss_mpu_irqs,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "usbotg_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l4 fw -> emif fw */
+static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
+ .master = &am33xx_l4_fw_hwmod,
+ .slave = &am33xx_emif_fw_hwmod,
+ .clk = "l4fw_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
+ {
+ .pa_start = 0x4c000000,
+ .pa_end = 0x4c000fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+/* l3 main -> emif */
+static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_emif_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_emif_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
+ .master = &am33xx_mpu_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "dpll_mpu_m2_ck",
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> l4 hs */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l4_hs_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 s */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l3_s_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 per/ls */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_ls_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_wkup_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 fw */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_fw_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 instr */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l3_instr_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> prcm */
+static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
+ .master = &am33xx_mpu_hwmod,
+ .slave = &am33xx_prcm_hwmod,
+ .clk = "dpll_mpu_m2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l3 main*/
+static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* pru-icss -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
+ .master = &am33xx_pruss_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "l3_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* wkup m3 -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
+ .master = &am33xx_wkup_m3_hwmod,
+ .slave = &am33xx_l4_wkup_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gfx -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
+ .master = &am33xx_gfx_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> wkup m3 */
+static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
+ {
+ .name = "umem",
+ .pa_start = 0x44d00000,
+ .pa_end = 0x44d00000 + SZ_16K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "dmem",
+ .pa_start = 0x44d80000,
+ .pa_end = 0x44d80000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_wkup_m3_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_wkup_m3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 hs -> pru-icss */
+static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
+ {
+ .pa_start = 0x4a300000,
+ .pa_end = 0x4a300000 + SZ_512K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
+ .master = &am33xx_l4_hs_hwmod,
+ .slave = &am33xx_pruss_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_pruss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> gfx */
+static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
+ {
+ .pa_start = 0x56000000,
+ .pa_end = 0x56000000 + SZ_16M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_gfx_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_gfx_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> smartreflex0 */
+static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
+ {
+ .pa_start = 0x44e37000,
+ .pa_end = 0x44e37000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_smartreflex0_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_smartreflex0_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> smartreflex1 */
+static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
+ {
+ .pa_start = 0x44e39000,
+ .pa_end = 0x44e39000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_smartreflex1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_smartreflex1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> control */
+static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
+ {
+ .pa_start = 0x44e10000,
+ .pa_end = 0x44e10000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_control_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_control_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> rtc */
+static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
+ {
+ .pa_start = 0x44e3e000,
+ .pa_end = 0x44e3e000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_rtc_hwmod,
+ .clk = "clkdiv32k_ick",
+ .addr = am33xx_rtc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per/ls -> DCAN0 */
+static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
+ {
+ .pa_start = 0x481CC000,
+ .pa_end = 0x481CC000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_dcan0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_dcan0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> DCAN1 */
+static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
+ {
+ .pa_start = 0x481D0000,
+ .pa_end = 0x481D0000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_dcan1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_dcan1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> GPIO2 */
+static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
+ {
+ .pa_start = 0x4804C000,
+ .pa_end = 0x4804C000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio3 */
+static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
+ {
+ .pa_start = 0x481AC000,
+ .pa_end = 0x481AC000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio4 */
+static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
+ {
+ .pa_start = 0x481AE000,
+ .pa_end = 0x481AE000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> I2C1 */
+static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
+ {
+ .pa_start = 0x44E0B000,
+ .pa_end = 0x44E0B000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_i2c1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_i2c1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* L4 WKUP -> GPIO1 */
+static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
+ {
+ .pa_start = 0x44E07000,
+ .pa_end = 0x44E07000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_gpio0_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_gpio0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> ADC_TSC */
+static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
+ {
+ .pa_start = 0x44E0D000,
+ .pa_end = 0x44E0D000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_adc_tsc_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_adc_tsc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+ /* cpsw ss */
+ {
+ .pa_start = 0x4a100000,
+ .pa_end = 0x4a100000 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ /* cpsw wr */
+ {
+ .pa_start = 0x4a101200,
+ .pa_end = 0x4a101200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
+ .master = &am33xx_l4_hs_hwmod,
+ .slave = &am33xx_cpgmac0_hwmod,
+ .clk = "cpsw_125mhz_gclk",
+ .addr = am33xx_cpgmac0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
+ {
+ .pa_start = 0x48080000,
+ .pa_end = 0x48080000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_elm_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_elm_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
+ {
+ .pa_start = 0x48300000,
+ .pa_end = 0x48300000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48300200,
+ .pa_end = 0x48300200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
+ {
+ .pa_start = 0x48302000,
+ .pa_end = 0x48302000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48302200,
+ .pa_end = 0x48302200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+ {
+ .pa_start = 0x48304000,
+ .pa_end = 0x48304000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48304200,
+ .pa_end = 0x48304200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
+ {
+ .pa_start = 0x48300000,
+ .pa_end = 0x48300000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48300100,
+ .pa_end = 0x48300100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
+ {
+ .pa_start = 0x48302000,
+ .pa_end = 0x48302000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48302100,
+ .pa_end = 0x48302100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+ {
+ .pa_start = 0x48304000,
+ .pa_end = 0x48304000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48304100,
+ .pa_end = 0x48304100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3s cfg -> gpmc */
+static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
+ {
+ .pa_start = 0x50000000,
+ .pa_end = 0x50000000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_gpmc_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_gpmc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* i2c2 */
+static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
+ {
+ .pa_start = 0x4802A000,
+ .pa_end = 0x4802A000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_i2c2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_i2c2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
+ {
+ .pa_start = 0x4819C000,
+ .pa_end = 0x4819C000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_i2c3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_i2c3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
+ {
+ .pa_start = 0x4830E000,
+ .pa_end = 0x4830E000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_lcdc_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_lcdc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x480C8000,
+ .pa_end = 0x480C8000 + (SZ_4K - 1),
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4 ls -> mailbox */
+static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mailbox_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mailbox_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> spinlock */
+static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
+ {
+ .pa_start = 0x480Ca000,
+ .pa_end = 0x480Ca000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spinlock_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_spinlock_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcasp0 */
+static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
+ {
+ .pa_start = 0x48038000,
+ .pa_end = 0x48038000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mcasp0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcasp0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp0 data */
+static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
+ {
+ .pa_start = 0x46000000,
+ .pa_end = 0x46000000 + SZ_4M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mcasp0_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mcasp0_data_addr_space,
+ .user = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mcasp1 */
+static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
+ {
+ .pa_start = 0x4803C000,
+ .pa_end = 0x4803C000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mcasp1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcasp1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp1 data */
+static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
+ {
+ .pa_start = 0x46400000,
+ .pa_end = 0x46400000 + SZ_4M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mcasp1_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mcasp1_data_addr_space,
+ .user = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mmc0 */
+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+ {
+ .pa_start = 0x48060100,
+ .pa_end = 0x48060100 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mmc0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mmc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mmc1 */
+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+ {
+ .pa_start = 0x481d8100,
+ .pa_end = 0x481d8100 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mmc1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mmc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mmc2 */
+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+ {
+ .pa_start = 0x47810100,
+ .pa_end = 0x47810100 + SZ_64K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mmc2_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mmc2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi0 */
+static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
+ {
+ .pa_start = 0x48030000,
+ .pa_end = 0x48030000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spi0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcspi0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi1 */
+static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
+ {
+ .pa_start = 0x481A0000,
+ .pa_end = 0x481A0000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spi1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcspi1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> timer1 */
+static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
+ {
+ .pa_start = 0x44E31000,
+ .pa_end = 0x44E31000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_timer1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_timer1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer2 */
+static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
+ {
+ .pa_start = 0x48040000,
+ .pa_end = 0x48040000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer3 */
+static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
+ {
+ .pa_start = 0x48042000,
+ .pa_end = 0x48042000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer4 */
+static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
+ {
+ .pa_start = 0x48044000,
+ .pa_end = 0x48044000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer4_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer4_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer5 */
+static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
+ {
+ .pa_start = 0x48046000,
+ .pa_end = 0x48046000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer5_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer5_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer6 */
+static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
+ {
+ .pa_start = 0x48048000,
+ .pa_end = 0x48048000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer6_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer6_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer7 */
+static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
+ {
+ .pa_start = 0x4804A000,
+ .pa_end = 0x4804A000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer7_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer7_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc */
+static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
+ {
+ .pa_start = 0x49000000,
+ .pa_end = 0x49000000 + SZ_32K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tpcc_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tpcc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc0 */
+static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
+ {
+ .pa_start = 0x49800000,
+ .pa_end = 0x49800000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc0_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc1 */
+static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
+ {
+ .pa_start = 0x49900000,
+ .pa_end = 0x49900000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc1_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc2 */
+static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
+ {
+ .pa_start = 0x49a00000,
+ .pa_end = 0x49a00000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc2_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> uart1 */
+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
+ {
+ .pa_start = 0x44E09000,
+ .pa_end = 0x44E09000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_uart1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_uart1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart2 */
+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
+ {
+ .pa_start = 0x48022000,
+ .pa_end = 0x48022000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart3 */
+static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
+ {
+ .pa_start = 0x48024000,
+ .pa_end = 0x48024000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart4 */
+static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
+ {
+ .pa_start = 0x481A6000,
+ .pa_end = 0x481A6000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart4_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart4_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart5 */
+static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
+ {
+ .pa_start = 0x481A8000,
+ .pa_end = 0x481A8000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart5_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart5_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart6 */
+static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
+ {
+ .pa_start = 0x481aa000,
+ .pa_end = 0x481aa000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart6_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart6_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> wd_timer1 */
+static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
+ {
+ .pa_start = 0x44e35000,
+ .pa_end = 0x44e35000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_wd_timer1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_wd_timer1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* usbss */
+/* l3 s -> USBSS interface */
+static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
+ {
+ .name = "usbss",
+ .pa_start = 0x47400000,
+ .pa_end = 0x47400000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb0",
+ .pa_start = 0x47401000,
+ .pa_end = 0x47401000 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb1",
+ .pa_start = 0x47401800,
+ .pa_end = 0x47401800 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_usbss_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_usbss_addr_space,
+ .user = OCP_USER_MPU,
+ .flags = OCPIF_SWSUP_IDLE,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
+ &am33xx_l4_fw__emif_fw,
+ &am33xx_l3_main__emif,
+ &am33xx_mpu__l3_main,
+ &am33xx_mpu__prcm,
+ &am33xx_l3_s__l4_ls,
+ &am33xx_l3_s__l4_wkup,
+ &am33xx_l3_s__l4_fw,
+ &am33xx_l3_main__l4_hs,
+ &am33xx_l3_main__l3_s,
+ &am33xx_l3_main__l3_instr,
+ &am33xx_l3_main__gfx,
+ &am33xx_l3_s__l3_main,
+ &am33xx_pruss__l3_main,
+ &am33xx_wkup_m3__l4_wkup,
+ &am33xx_gfx__l3_main,
+ &am33xx_l4_wkup__wkup_m3,
+ &am33xx_l4_wkup__control,
+ &am33xx_l4_wkup__smartreflex0,
+ &am33xx_l4_wkup__smartreflex1,
+ &am33xx_l4_wkup__uart1,
+ &am33xx_l4_wkup__timer1,
+ &am33xx_l4_wkup__rtc,
+ &am33xx_l4_wkup__i2c1,
+ &am33xx_l4_wkup__gpio0,
+ &am33xx_l4_wkup__adc_tsc,
+ &am33xx_l4_wkup__wd_timer1,
+ &am33xx_l4_hs__pruss,
+ &am33xx_l4_per__dcan0,
+ &am33xx_l4_per__dcan1,
+ &am33xx_l4_per__gpio1,
+ &am33xx_l4_per__gpio2,
+ &am33xx_l4_per__gpio3,
+ &am33xx_l4_per__i2c2,
+ &am33xx_l4_per__i2c3,
+ &am33xx_l4_per__mailbox,
+ &am33xx_l4_ls__mcasp0,
+ &am33xx_l3_s__mcasp0_data,
+ &am33xx_l4_ls__mcasp1,
+ &am33xx_l3_s__mcasp1_data,
+ &am33xx_l4_ls__mmc0,
+ &am33xx_l4_ls__mmc1,
+ &am33xx_l3_s__mmc2,
+ &am33xx_l4_ls__timer2,
+ &am33xx_l4_ls__timer3,
+ &am33xx_l4_ls__timer4,
+ &am33xx_l4_ls__timer5,
+ &am33xx_l4_ls__timer6,
+ &am33xx_l4_ls__timer7,
+ &am33xx_l3_main__tpcc,
+ &am33xx_l4_ls__uart2,
+ &am33xx_l4_ls__uart3,
+ &am33xx_l4_ls__uart4,
+ &am33xx_l4_ls__uart5,
+ &am33xx_l4_ls__uart6,
+ &am33xx_l4_ls__spinlock,
+ &am33xx_l4_ls__elm,
+ &am33xx_l4_ls__ehrpwm0,
+ &am33xx_l4_ls__ehrpwm1,
+ &am33xx_l4_ls__ehrpwm2,
+ &am33xx_l4_ls__ecap0,
+ &am33xx_l4_ls__ecap1,
+ &am33xx_l4_ls__ecap2,
+ &am33xx_l3_s__gpmc,
+ &am33xx_l3_main__lcdc,
+ &am33xx_l4_ls__mcspi0,
+ &am33xx_l4_ls__mcspi1,
+ &am33xx_l3_main__tptc0,
+ &am33xx_l3_main__tptc1,
+ &am33xx_l3_main__tptc2,
+ &am33xx_l3_s__usbss,
+ &am33xx_l4_hs__cpgmac0,
+ NULL,
+};
+
+int __init am33xx_hwmod_init(void)
+{
+ omap_hwmod_init();
+ return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 6132972..9b9646c 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -658,6 +658,7 @@ extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
+extern int am33xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-07-25 11:07 ` Vaibhav Hiremath
@ 2012-07-25 20:41 ` Paul Walmsley
-1 siblings, 0 replies; 28+ messages in thread
From: Paul Walmsley @ 2012-07-25 20:41 UTC (permalink / raw)
To: Vaibhav Hiremath
Cc: linux-omap, linux-arm-kernel, Afzal Mohammed, Vaibhav Bedia,
Benoit Cousson, Tony Lindgren, Kevin Hilman, Rajendra Nayak
Hello Vaibhav,
On Wed, 25 Jul 2012, Vaibhav Hiremath wrote:
> This patch adds HWMOD data for all the peripherals of
> AM335X device and also hooks up to the existing OMAP framework.
Looks pretty good. One question:
> +static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
> + .name = "ehrpwm.0",
These IP blocks and the ECAP IP blocks have periods in their names.
The rest of the IP block named in the file don't use periods -- which
is also the style used by the rest of the OMAP SoCs. Is there
some reason that these have periods in their names?
- Paul
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-07-25 20:41 ` Paul Walmsley
0 siblings, 0 replies; 28+ messages in thread
From: Paul Walmsley @ 2012-07-25 20:41 UTC (permalink / raw)
To: linux-arm-kernel
Hello Vaibhav,
On Wed, 25 Jul 2012, Vaibhav Hiremath wrote:
> This patch adds HWMOD data for all the peripherals of
> AM335X device and also hooks up to the existing OMAP framework.
Looks pretty good. One question:
> +static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
> + .name = "ehrpwm.0",
These IP blocks and the ECAP IP blocks have periods in their names.
The rest of the IP block named in the file don't use periods -- which
is also the style used by the rest of the OMAP SoCs. Is there
some reason that these have periods in their names?
- Paul
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-07-25 20:41 ` Paul Walmsley
@ 2012-07-26 20:02 ` Paul Walmsley
-1 siblings, 0 replies; 28+ messages in thread
From: Paul Walmsley @ 2012-07-26 20:02 UTC (permalink / raw)
To: Vaibhav Hiremath
Cc: linux-omap, linux-arm-kernel, Afzal Mohammed, Vaibhav Bedia,
Benoit Cousson, Tony Lindgren, Kevin Hilman, Rajendra Nayak
On Wed, 25 Jul 2012, Paul Walmsley wrote:
> These IP blocks and the ECAP IP blocks have periods in their names.
> The rest of the IP block named in the file don't use periods -- which
> is also the style used by the rest of the OMAP SoCs. Is there
> some reason that these have periods in their names?
I've changed those to match the rest of the names, and queued the
following for 3.7.
Thanks again for all the hard work you all put into this. I realize that
with all the upstream changes, this was probably a little painful for you.
But from my perspective you've been a pleasure to work with through the
process.
- Paul
From: Vaibhav Hiremath <hvaibhav@ti.com>
Date: Wed, 25 Jul 2012 13:51:13 -0600
Subject: [PATCH] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
This patch adds HWMOD data for all the peripherals of
AM335X device and also hooks up to the existing OMAP framework.
hwmod data has been already been cleaned up for the recent
changes in clocktree, where all leaf nodes have been removed,
since with modulemode based control, both clock and hwmod
interface does same thing. This reduces the code size to large
extent and also avoids duplication of same control.
So instead of specifying module's leaf node as a main_clk,
now we are relying on parent clock of module's functional clock.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/io.c | 2 +
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3381 ++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
4 files changed, 3385 insertions(+)
create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f6a24b3..b360328 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -194,6 +194,7 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4d2d981..408b3f0 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -523,6 +523,8 @@ void __init am33xx_init_early(void)
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
+ am33xx_hwmod_init();
+ omap_hwmod_init_postsetup();
am33xx_clk_init();
}
#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
new file mode 100644
index 0000000..16d8543
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -0,0 +1,3381 @@
+/*
+ * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
+ *
+ * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+#include <plat/gpio.h>
+#include <plat/dma.h>
+#include <plat/mmc.h>
+#include <plat/mcspi.h>
+#include <plat/i2c.h>
+
+#include "omap_hwmod_common_data.h"
+
+#include "control.h"
+#include "cm33xx.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'emif_fw' class
+ * instance(s): emif_fw
+ */
+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
+ .name = "emif_fw",
+};
+
+/* emif_fw */
+static struct omap_hwmod am33xx_emif_fw_hwmod = {
+ .name = "emif_fw",
+ .class = &am33xx_emif_fw_hwmod_class,
+ .clkdm_name = "l4fw_clkdm",
+ .main_clk = "l4fw_gclk",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'emif' class
+ * instance(s): emif
+ */
+static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
+ .rev_offs = 0x0000,
+};
+
+static struct omap_hwmod_class am33xx_emif_hwmod_class = {
+ .name = "emif",
+ .sysc = &am33xx_emif_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
+ { .name = "ddrerr0", .irq = 101 },
+ { .irq = -1 }
+};
+
+/* emif */
+static struct omap_hwmod am33xx_emif_hwmod = {
+ .name = "emif",
+ .class = &am33xx_emif_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_emif_irqs,
+ .main_clk = "dpll_ddr_m2_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_main, l3_s, l3_instr
+ */
+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+ .name = "l3",
+};
+
+/* l3_main (l3_fast) */
+static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
+ { .name = "l3debug", .irq = 9 },
+ { .name = "l3appint", .irq = 10 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_l3_main_hwmod = {
+ .name = "l3_main",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_l3_main_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l3_s */
+static struct omap_hwmod am33xx_l3_s_hwmod = {
+ .name = "l3_s",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+};
+
+/* l3_instr */
+static struct omap_hwmod am33xx_l3_instr_hwmod = {
+ .name = "l3_instr",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
+ */
+static struct omap_hwmod_class am33xx_l4_hwmod_class = {
+ .name = "l4",
+};
+
+/* l4_ls */
+static struct omap_hwmod am33xx_l4_ls_hwmod = {
+ .name = "l4_ls",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_hs */
+static struct omap_hwmod am33xx_l4_hs_hwmod = {
+ .name = "l4_hs",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4hs_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l4hs_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/* l4_wkup */
+static struct omap_hwmod am33xx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_fw */
+static struct omap_hwmod am33xx_l4_fw_hwmod = {
+ .name = "l4_fw",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4fw_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mpu' class
+ */
+static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
+ .name = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
+ { .name = "emuint", .irq = 0 },
+ { .name = "commtx", .irq = 1 },
+ { .name = "commrx", .irq = 2 },
+ { .name = "bench", .irq = 3 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &am33xx_mpu_hwmod_class,
+ .clkdm_name = "mpu_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_mpu_irqs,
+ .main_clk = "dpll_mpu_m2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'wakeup m3' class
+ * Wakeup controller sub-system under wakeup domain
+ */
+static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+ .name = "wkup_m3",
+};
+
+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+ { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+};
+
+static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
+ { .name = "txev", .irq = 78 },
+ { .irq = -1 }
+};
+
+/* wkup_m3 */
+static struct omap_hwmod am33xx_wkup_m3_hwmod = {
+ .name = "wkup_m3",
+ .class = &am33xx_wkup_m3_hwmod_class,
+ .clkdm_name = "l4_wkup_aon_clkdm",
+ .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
+ .mpu_irqs = am33xx_wkup_m3_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_wkup_m3_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
+};
+
+/*
+ * 'pru-icss' class
+ * Programmable Real-Time Unit and Industrial Communication Subsystem
+ */
+static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
+ .name = "pruss",
+};
+
+static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
+ { .name = "pruss", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
+ { .name = "evtout0", .irq = 20 },
+ { .name = "evtout1", .irq = 21 },
+ { .name = "evtout2", .irq = 22 },
+ { .name = "evtout3", .irq = 23 },
+ { .name = "evtout4", .irq = 24 },
+ { .name = "evtout5", .irq = 25 },
+ { .name = "evtout6", .irq = 26 },
+ { .name = "evtout7", .irq = 27 },
+ { .irq = -1 }
+};
+
+/* pru-icss */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod am33xx_pruss_hwmod = {
+ .name = "pruss",
+ .class = &am33xx_pruss_hwmod_class,
+ .clkdm_name = "pruss_ocp_clkdm",
+ .mpu_irqs = am33xx_pruss_irqs,
+ .main_clk = "pruss_ocp_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_pruss_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
+};
+
+/* gfx */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
+ .name = "gfx",
+};
+
+static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
+ { .name = "gfx", .rst_shift = 0 },
+};
+
+static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
+ { .name = "gfxint", .irq = 37 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gfx_hwmod = {
+ .name = "gfx",
+ .class = &am33xx_gfx_hwmod_class,
+ .clkdm_name = "gfx_l3_clkdm",
+ .mpu_irqs = am33xx_gfx_irqs,
+ .main_clk = "gfx_fck_div_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_gfx_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
+};
+
+/*
+ * 'prcm' class
+ * power and reset manager (whole prcm infrastructure)
+ */
+static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
+ .name = "prcm",
+};
+
+/* prcm */
+static struct omap_hwmod am33xx_prcm_hwmod = {
+ .name = "prcm",
+ .class = &am33xx_prcm_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+};
+
+/*
+ * 'adc/tsc' class
+ * TouchScreen Controller (Anolog-To-Digital Converter)
+ */
+static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x10,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
+ .name = "adc_tsc",
+ .sysc = &am33xx_adc_tsc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
+ { .irq = 16 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_adc_tsc_hwmod = {
+ .name = "adc_tsc",
+ .class = &am33xx_adc_tsc_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_adc_tsc_irqs,
+ .main_clk = "adc_tsc_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * Modules omap_hwmod structures
+ *
+ * The following IPs are excluded for the moment because:
+ * - They do not need an explicit SW control using omap_hwmod API.
+ * - They still need to be validated with the driver
+ * properly adapted to omap_hwmod / omap_device
+ *
+ * - cEFUSE (doesn't fall under any ocp_if)
+ * - clkdiv32k
+ * - debugss
+ * - ocmc ram
+ * - ocp watch point
+ * - aes0
+ * - sha0
+ */
+#if 0
+/*
+ * 'cefuse' class
+ */
+static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
+ .name = "cefuse",
+};
+
+static struct omap_hwmod am33xx_cefuse_hwmod = {
+ .name = "cefuse",
+ .class = &am33xx_cefuse_hwmod_class,
+ .clkdm_name = "l4_cefuse_clkdm",
+ .main_clk = "cefuse_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'clkdiv32k' class
+ */
+static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
+ .name = "clkdiv32k",
+};
+
+static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
+ .name = "clkdiv32k",
+ .class = &am33xx_clkdiv32k_hwmod_class,
+ .clkdm_name = "clk_24mhz_clkdm",
+ .main_clk = "clkdiv32k_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'debugss' class
+ * debug sub system
+ */
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+ .name = "debugss",
+};
+
+static struct omap_hwmod am33xx_debugss_hwmod = {
+ .name = "debugss",
+ .class = &am33xx_debugss_hwmod_class,
+ .clkdm_name = "l3_aon_clkdm",
+ .main_clk = "debugss_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+ .name = "ocmcram",
+};
+
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+ .name = "ocmcram",
+ .class = &am33xx_ocmcram_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ocpwp */
+static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
+ .name = "ocpwp",
+};
+
+static struct omap_hwmod am33xx_ocpwp_hwmod = {
+ .name = "ocpwp",
+ .class = &am33xx_ocpwp_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'aes' class
+ */
+static struct omap_hwmod_class am33xx_aes_hwmod_class = {
+ .name = "aes",
+};
+
+static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
+ { .irq = 102 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_aes0_hwmod = {
+ .name = "aes0",
+ .class = &am33xx_aes_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_aes0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* sha0 */
+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+ .name = "sha0",
+};
+
+static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
+ { .irq = 108 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_sha0_hwmod = {
+ .name = "sha0",
+ .class = &am33xx_sha0_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_sha0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+#endif
+
+/* 'smartreflex' class */
+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+ .name = "smartreflex",
+};
+
+/* smartreflex0 */
+static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
+ { .irq = 120 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_smartreflex0_hwmod = {
+ .name = "smartreflex0",
+ .class = &am33xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_smartreflex0_irqs,
+ .main_clk = "smartreflex0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* smartreflex1 */
+static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
+ { .irq = 121 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_smartreflex1_hwmod = {
+ .name = "smartreflex1",
+ .class = &am33xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_smartreflex1_irqs,
+ .main_clk = "smartreflex1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'control' module class
+ */
+static struct omap_hwmod_class am33xx_control_hwmod_class = {
+ .name = "control",
+};
+
+static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
+ { .irq = 8 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_control_hwmod = {
+ .name = "control",
+ .class = &am33xx_control_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_control_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'cpgmac' class
+ * cpsw/cpgmac sub system
+ */
+static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x8,
+ .syss_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+ MSTANDBY_NO),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+ .name = "cpgmac0",
+ .sysc = &am33xx_cpgmac_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
+ { .name = "c0_rx_thresh_pend", .irq = 40 },
+ { .name = "c0_rx_pend", .irq = 41 },
+ { .name = "c0_tx_pend", .irq = 42 },
+ { .name = "c0_misc_pend", .irq = 43 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_cpgmac0_hwmod = {
+ .name = "cpgmac0",
+ .class = &am33xx_cpgmac0_hwmod_class,
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .mpu_irqs = am33xx_cpgmac0_irqs,
+ .main_clk = "cpsw_125mhz_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * dcan class
+ */
+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+ .name = "d_can",
+};
+
+/* dcan0 */
+static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
+ { .name = "d_can_ms", .irq = 52 },
+ { .name = "d_can_mo", .irq = 53 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_dcan0_hwmod = {
+ .name = "d_can0",
+ .class = &am33xx_dcan_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_dcan0_irqs,
+ .main_clk = "dcan0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* dcan1 */
+static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
+ { .name = "d_can_ms", .irq = 55 },
+ { .name = "d_can_mo", .irq = 56 },
+ { .irq = -1 }
+};
+static struct omap_hwmod am33xx_dcan1_hwmod = {
+ .name = "d_can1",
+ .class = &am33xx_dcan_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_dcan1_irqs,
+ .main_clk = "dcan1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* elm */
+static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+ .name = "elm",
+ .sysc = &am33xx_elm_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
+ { .irq = 4 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_elm_hwmod = {
+ .name = "elm",
+ .class = &am33xx_elm_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_elm_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
+ */
+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+ .name = "epwmss",
+ .sysc = &am33xx_epwmss_sysc,
+};
+
+/* ehrpwm0 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
+ { .name = "int", .irq = 86 },
+ { .name = "tzint", .irq = 58 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+ .name = "ehrpwm0",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm0_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ehrpwm1 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+ { .name = "int", .irq = 87 },
+ { .name = "tzint", .irq = 59 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+ .name = "ehrpwm1",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ehrpwm2 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+ { .name = "int", .irq = 39 },
+ { .name = "tzint", .irq = 60 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+ .name = "ehrpwm2",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm2_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap0 */
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+ { .irq = 31 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap0_hwmod = {
+ .name = "ecap0",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ecap0_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap1 */
+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
+ { .irq = 47 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap1_hwmod = {
+ .name = "ecap1",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ecap1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap2 */
+static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
+ { .irq = 61 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap2_hwmod = {
+ .name = "ecap2",
+ .mpu_irqs = am33xx_ecap2_irqs,
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'gpio' class: for gpio 0,1,2,3
+ */
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &am33xx_gpio_sysc,
+ .rev = 2,
+};
+
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio0 */
+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio0_dbclk" },
+};
+
+static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
+ { .irq = 96 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gpio0_hwmod = {
+ .name = "gpio1",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio0_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio0_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
+ { .irq = 98 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio1_hwmod = {
+ .name = "gpio2",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
+ { .irq = 32 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio2_hwmod = {
+ .name = "gpio3",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio2_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
+ { .irq = 62 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio3_hwmod = {
+ .name = "gpio4",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio3_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpmc */
+static struct omap_hwmod_class_sysconfig gpmc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+ .name = "gpmc",
+ .sysc = &gpmc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
+ { .irq = 100 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gpmc_hwmod = {
+ .name = "gpmc",
+ .class = &am33xx_gpmc_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_gpmc_irqs,
+ .main_clk = "l3s_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'i2c' class */
+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0090,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &am33xx_i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_2,
+ .reset = &omap_i2c_reset,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = 70 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &i2c_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_wkupdm_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = 71 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &i2c_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+ { .irq = 30 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &i2c_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = i2c3_mpu_irqs,
+ .sdma_reqs = i2c3_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+
+/* lcdc */
+static struct omap_hwmod_class_sysconfig lcdc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x54,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
+ .name = "lcdc",
+ .sysc = &lcdc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
+ { .irq = 36 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_lcdc_hwmod = {
+ .name = "lcdc",
+ .class = &am33xx_lcdc_hwmod_class,
+ .clkdm_name = "lcdc_clkdm",
+ .mpu_irqs = am33xx_lcdc_irqs,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "lcd_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &am33xx_mailbox_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
+ { .irq = 77 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &am33xx_mailbox_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mailbox_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mcasp' class
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+ .name = "mcasp",
+ .sysc = &am33xx_mcasp_sysc,
+};
+
+/* mcasp0 */
+static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
+ { .name = "ax", .irq = 80, },
+ { .name = "ar", .irq = 81, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
+ { .name = "tx", .dma_req = 8, },
+ { .name = "rx", .dma_req = 9, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp0_hwmod = {
+ .name = "mcasp0",
+ .class = &am33xx_mcasp_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mcasp0_irqs,
+ .sdma_reqs = am33xx_mcasp0_edma_reqs,
+ .main_clk = "mcasp0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp1 */
+static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
+ { .name = "ax", .irq = 82, },
+ { .name = "ar", .irq = 83, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 10, },
+ { .name = "rx", .dma_req = 11, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp1_hwmod = {
+ .name = "mcasp1",
+ .class = &am33xx_mcasp_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mcasp1_irqs,
+ .sdma_reqs = am33xx_mcasp1_edma_reqs,
+ .main_clk = "mcasp1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'mmc' class */
+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+ .rev_offs = 0x1fc,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+ .name = "mmc",
+ .sysc = &am33xx_mmc_sysc,
+};
+
+/* mmc0 */
+static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
+ { .irq = 64 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
+ { .name = "tx", .dma_req = 24, },
+ { .name = "rx", .dma_req = 25, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc0_hwmod = {
+ .name = "mmc1",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mmc0_irqs,
+ .sdma_reqs = am33xx_mmc0_edma_reqs,
+ .main_clk = "mmc_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc0_dev_attr,
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
+ { .irq = 28 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 2, },
+ { .name = "rx", .dma_req = 3, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc1_hwmod = {
+ .name = "mmc2",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mmc1_irqs,
+ .sdma_reqs = am33xx_mmc1_edma_reqs,
+ .main_clk = "mmc_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
+ { .irq = 29 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 64, },
+ { .name = "rx", .dma_req = 65, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc2_hwmod = {
+ .name = "mmc3",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mmc2_irqs,
+ .sdma_reqs = am33xx_mmc2_edma_reqs,
+ .main_clk = "mmc2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc2_dev_attr,
+};
+
+/*
+ * 'rtc' class
+ * rtc subsystem
+ */
+static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
+ .rev_offs = 0x0074,
+ .sysc_offs = 0x0078,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO |
+ SIDLE_SMART | SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+ .name = "rtc",
+ .sysc = &am33xx_rtc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
+ { .name = "rtcint", .irq = 75 },
+ { .name = "rtcalarmint", .irq = 76 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_rtc_hwmod = {
+ .name = "rtc",
+ .class = &am33xx_rtc_hwmod_class,
+ .clkdm_name = "l4_rtc_clkdm",
+ .mpu_irqs = am33xx_rtc_irqs,
+ .main_clk = "clk_32768_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'spi' class */
+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0110,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_spi_hwmod_class = {
+ .name = "mcspi",
+ .sysc = &am33xx_mcspi_sysc,
+ .rev = OMAP4_MCSPI_REV,
+};
+
+/* spi0 */
+static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
+ { .irq = 65 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
+ { .name = "rx0", .dma_req = 17 },
+ { .name = "tx0", .dma_req = 16 },
+ { .name = "rx1", .dma_req = 19 },
+ { .name = "tx1", .dma_req = 18 },
+ { .dma_req = -1 }
+};
+
+static struct omap2_mcspi_dev_attr mcspi_attrib = {
+ .num_chipselect = 2,
+};
+static struct omap_hwmod am33xx_spi0_hwmod = {
+ .name = "spi0",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_spi0_irqs,
+ .sdma_reqs = am33xx_mcspi0_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+/* spi1 */
+static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
+ { .irq = 125 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
+ { .name = "rx0", .dma_req = 43 },
+ { .name = "tx0", .dma_req = 42 },
+ { .name = "rx1", .dma_req = 45 },
+ { .name = "tx1", .dma_req = 44 },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_spi1_hwmod = {
+ .name = "spi1",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_spi1_irqs,
+ .sdma_reqs = am33xx_mcspi1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+/*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the
+ * processes running on multiple processors
+ */
+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+ .name = "spinlock",
+};
+
+static struct omap_hwmod am33xx_spinlock_hwmod = {
+ .name = "spinlock",
+ .class = &am33xx_spinlock_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'timer 2-7' class */
+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &am33xx_timer_sysc,
+};
+
+/* timer1 1ms */
+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &am33xx_timer1ms_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
+ { .irq = 67 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &am33xx_timer1ms_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_timer1_irqs,
+ .main_clk = "timer1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
+ { .irq = 68 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer2_irqs,
+ .main_clk = "timer2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
+ { .irq = 69 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer3_irqs,
+ .main_clk = "timer3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
+ { .irq = 92 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer4_irqs,
+ .main_clk = "timer4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
+ { .irq = 93 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer5_irqs,
+ .main_clk = "timer5_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
+ { .irq = 94 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer6_irqs,
+ .main_clk = "timer6_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
+ { .irq = 95 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer7_irqs,
+ .main_clk = "timer7_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tpcc */
+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+ .name = "tpcc",
+};
+
+static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
+ { .name = "edma0", .irq = 12 },
+ { .name = "edma0_mperr", .irq = 13, },
+ { .name = "edma0_err", .irq = 14 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tpcc_hwmod = {
+ .name = "tpcc",
+ .class = &am33xx_tpcc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tpcc_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+/* 'tptc' class */
+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+ .name = "tptc",
+ .sysc = &am33xx_tptc_sysc,
+};
+
+/* tptc0 */
+static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
+ { .irq = 112 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc0_hwmod = {
+ .name = "tptc0",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc1 */
+static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
+ { .irq = 113 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc1_hwmod = {
+ .name = "tptc1",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc1_irqs,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc2 */
+static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
+ { .irq = 114 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc2_hwmod = {
+ .name = "tptc2",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc2_irqs,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'uart' class */
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+ .rev_offs = 0x50,
+ .sysc_offs = 0x54,
+ .syss_offs = 0x58,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+ .name = "uart",
+ .sysc = &uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 26, },
+ { .name = "rx", .dma_req = 27, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
+ { .irq = 72 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart1_hwmod = {
+ .name = "uart1",
+ .class = &uart_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_uart1_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_wkupdm_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
+ { .irq = 73 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart2_hwmod = {
+ .name = "uart2",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart2_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart3 */
+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 30, },
+ { .name = "rx", .dma_req = 31, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
+ { .irq = 74 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart3_hwmod = {
+ .name = "uart3",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart3_irqs,
+ .sdma_reqs = uart3_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
+ { .irq = 44 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart4_hwmod = {
+ .name = "uart4",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart4_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
+ { .irq = 45 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart5_hwmod = {
+ .name = "uart5",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart5_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
+ { .irq = 46 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart6_hwmod = {
+ .name = "uart6",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart6_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'wd_timer' class */
+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+};
+
+/*
+ * XXX: device.c file uses hardcoded name for watchdog timer
+ * driver "wd_timer2, so we are also using same name as of now...
+ */
+static struct omap_hwmod am33xx_wd_timer1_hwmod = {
+ .name = "wd_timer2",
+ .class = &am33xx_wd_timer_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .main_clk = "wdt1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'usb_otg' class
+ * high-speed on-the-go universal serial bus (usb_otg) controller
+ */
+static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_usbotg_class = {
+ .name = "usbotg",
+ .sysc = &am33xx_usbhsotg_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
+ { .name = "usbss-irq", .irq = 17, },
+ { .name = "musb0-irq", .irq = 18, },
+ { .name = "musb1-irq", .irq = 19, },
+ { .irq = -1, },
+};
+
+static struct omap_hwmod am33xx_usbss_hwmod = {
+ .name = "usb_otg_hs",
+ .class = &am33xx_usbotg_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_usbss_mpu_irqs,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "usbotg_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l4 fw -> emif fw */
+static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
+ .master = &am33xx_l4_fw_hwmod,
+ .slave = &am33xx_emif_fw_hwmod,
+ .clk = "l4fw_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
+ {
+ .pa_start = 0x4c000000,
+ .pa_end = 0x4c000fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+/* l3 main -> emif */
+static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_emif_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_emif_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
+ .master = &am33xx_mpu_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "dpll_mpu_m2_ck",
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> l4 hs */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l4_hs_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 s */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l3_s_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 per/ls */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_ls_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_wkup_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 fw */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_fw_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 instr */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l3_instr_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> prcm */
+static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
+ .master = &am33xx_mpu_hwmod,
+ .slave = &am33xx_prcm_hwmod,
+ .clk = "dpll_mpu_m2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l3 main*/
+static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* pru-icss -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
+ .master = &am33xx_pruss_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "l3_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* wkup m3 -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
+ .master = &am33xx_wkup_m3_hwmod,
+ .slave = &am33xx_l4_wkup_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gfx -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
+ .master = &am33xx_gfx_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> wkup m3 */
+static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
+ {
+ .name = "umem",
+ .pa_start = 0x44d00000,
+ .pa_end = 0x44d00000 + SZ_16K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "dmem",
+ .pa_start = 0x44d80000,
+ .pa_end = 0x44d80000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_wkup_m3_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_wkup_m3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 hs -> pru-icss */
+static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
+ {
+ .pa_start = 0x4a300000,
+ .pa_end = 0x4a300000 + SZ_512K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
+ .master = &am33xx_l4_hs_hwmod,
+ .slave = &am33xx_pruss_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_pruss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> gfx */
+static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
+ {
+ .pa_start = 0x56000000,
+ .pa_end = 0x56000000 + SZ_16M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_gfx_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_gfx_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> smartreflex0 */
+static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
+ {
+ .pa_start = 0x44e37000,
+ .pa_end = 0x44e37000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_smartreflex0_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_smartreflex0_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> smartreflex1 */
+static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
+ {
+ .pa_start = 0x44e39000,
+ .pa_end = 0x44e39000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_smartreflex1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_smartreflex1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> control */
+static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
+ {
+ .pa_start = 0x44e10000,
+ .pa_end = 0x44e10000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_control_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_control_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> rtc */
+static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
+ {
+ .pa_start = 0x44e3e000,
+ .pa_end = 0x44e3e000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_rtc_hwmod,
+ .clk = "clkdiv32k_ick",
+ .addr = am33xx_rtc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per/ls -> DCAN0 */
+static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
+ {
+ .pa_start = 0x481CC000,
+ .pa_end = 0x481CC000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_dcan0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_dcan0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> DCAN1 */
+static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
+ {
+ .pa_start = 0x481D0000,
+ .pa_end = 0x481D0000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_dcan1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_dcan1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> GPIO2 */
+static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
+ {
+ .pa_start = 0x4804C000,
+ .pa_end = 0x4804C000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio3 */
+static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
+ {
+ .pa_start = 0x481AC000,
+ .pa_end = 0x481AC000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio4 */
+static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
+ {
+ .pa_start = 0x481AE000,
+ .pa_end = 0x481AE000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> I2C1 */
+static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
+ {
+ .pa_start = 0x44E0B000,
+ .pa_end = 0x44E0B000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_i2c1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_i2c1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* L4 WKUP -> GPIO1 */
+static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
+ {
+ .pa_start = 0x44E07000,
+ .pa_end = 0x44E07000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_gpio0_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_gpio0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> ADC_TSC */
+static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
+ {
+ .pa_start = 0x44E0D000,
+ .pa_end = 0x44E0D000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_adc_tsc_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_adc_tsc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+ /* cpsw ss */
+ {
+ .pa_start = 0x4a100000,
+ .pa_end = 0x4a100000 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ /* cpsw wr */
+ {
+ .pa_start = 0x4a101200,
+ .pa_end = 0x4a101200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
+ .master = &am33xx_l4_hs_hwmod,
+ .slave = &am33xx_cpgmac0_hwmod,
+ .clk = "cpsw_125mhz_gclk",
+ .addr = am33xx_cpgmac0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
+ {
+ .pa_start = 0x48080000,
+ .pa_end = 0x48080000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_elm_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_elm_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
+ {
+ .pa_start = 0x48300000,
+ .pa_end = 0x48300000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48300200,
+ .pa_end = 0x48300200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
+ {
+ .pa_start = 0x48302000,
+ .pa_end = 0x48302000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48302200,
+ .pa_end = 0x48302200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+ {
+ .pa_start = 0x48304000,
+ .pa_end = 0x48304000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48304200,
+ .pa_end = 0x48304200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
+ {
+ .pa_start = 0x48300000,
+ .pa_end = 0x48300000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48300100,
+ .pa_end = 0x48300100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
+ {
+ .pa_start = 0x48302000,
+ .pa_end = 0x48302000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48302100,
+ .pa_end = 0x48302100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+ {
+ .pa_start = 0x48304000,
+ .pa_end = 0x48304000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48304100,
+ .pa_end = 0x48304100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3s cfg -> gpmc */
+static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
+ {
+ .pa_start = 0x50000000,
+ .pa_end = 0x50000000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_gpmc_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_gpmc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* i2c2 */
+static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
+ {
+ .pa_start = 0x4802A000,
+ .pa_end = 0x4802A000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_i2c2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_i2c2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
+ {
+ .pa_start = 0x4819C000,
+ .pa_end = 0x4819C000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_i2c3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_i2c3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
+ {
+ .pa_start = 0x4830E000,
+ .pa_end = 0x4830E000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_lcdc_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_lcdc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x480C8000,
+ .pa_end = 0x480C8000 + (SZ_4K - 1),
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4 ls -> mailbox */
+static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mailbox_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mailbox_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> spinlock */
+static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
+ {
+ .pa_start = 0x480Ca000,
+ .pa_end = 0x480Ca000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spinlock_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_spinlock_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcasp0 */
+static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
+ {
+ .pa_start = 0x48038000,
+ .pa_end = 0x48038000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mcasp0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcasp0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp0 data */
+static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
+ {
+ .pa_start = 0x46000000,
+ .pa_end = 0x46000000 + SZ_4M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mcasp0_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mcasp0_data_addr_space,
+ .user = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mcasp1 */
+static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
+ {
+ .pa_start = 0x4803C000,
+ .pa_end = 0x4803C000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mcasp1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcasp1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp1 data */
+static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
+ {
+ .pa_start = 0x46400000,
+ .pa_end = 0x46400000 + SZ_4M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mcasp1_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mcasp1_data_addr_space,
+ .user = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mmc0 */
+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+ {
+ .pa_start = 0x48060100,
+ .pa_end = 0x48060100 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mmc0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mmc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mmc1 */
+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+ {
+ .pa_start = 0x481d8100,
+ .pa_end = 0x481d8100 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mmc1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mmc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mmc2 */
+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+ {
+ .pa_start = 0x47810100,
+ .pa_end = 0x47810100 + SZ_64K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mmc2_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mmc2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi0 */
+static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
+ {
+ .pa_start = 0x48030000,
+ .pa_end = 0x48030000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spi0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcspi0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi1 */
+static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
+ {
+ .pa_start = 0x481A0000,
+ .pa_end = 0x481A0000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spi1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcspi1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> timer1 */
+static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
+ {
+ .pa_start = 0x44E31000,
+ .pa_end = 0x44E31000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_timer1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_timer1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer2 */
+static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
+ {
+ .pa_start = 0x48040000,
+ .pa_end = 0x48040000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer3 */
+static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
+ {
+ .pa_start = 0x48042000,
+ .pa_end = 0x48042000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer4 */
+static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
+ {
+ .pa_start = 0x48044000,
+ .pa_end = 0x48044000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer4_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer4_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer5 */
+static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
+ {
+ .pa_start = 0x48046000,
+ .pa_end = 0x48046000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer5_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer5_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer6 */
+static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
+ {
+ .pa_start = 0x48048000,
+ .pa_end = 0x48048000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer6_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer6_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer7 */
+static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
+ {
+ .pa_start = 0x4804A000,
+ .pa_end = 0x4804A000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer7_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer7_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc */
+static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
+ {
+ .pa_start = 0x49000000,
+ .pa_end = 0x49000000 + SZ_32K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tpcc_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tpcc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc0 */
+static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
+ {
+ .pa_start = 0x49800000,
+ .pa_end = 0x49800000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc0_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc1 */
+static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
+ {
+ .pa_start = 0x49900000,
+ .pa_end = 0x49900000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc1_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc2 */
+static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
+ {
+ .pa_start = 0x49a00000,
+ .pa_end = 0x49a00000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc2_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> uart1 */
+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
+ {
+ .pa_start = 0x44E09000,
+ .pa_end = 0x44E09000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_uart1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_uart1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart2 */
+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
+ {
+ .pa_start = 0x48022000,
+ .pa_end = 0x48022000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart3 */
+static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
+ {
+ .pa_start = 0x48024000,
+ .pa_end = 0x48024000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart4 */
+static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
+ {
+ .pa_start = 0x481A6000,
+ .pa_end = 0x481A6000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart4_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart4_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart5 */
+static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
+ {
+ .pa_start = 0x481A8000,
+ .pa_end = 0x481A8000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart5_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart5_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart6 */
+static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
+ {
+ .pa_start = 0x481aa000,
+ .pa_end = 0x481aa000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart6_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart6_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> wd_timer1 */
+static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
+ {
+ .pa_start = 0x44e35000,
+ .pa_end = 0x44e35000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_wd_timer1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_wd_timer1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* usbss */
+/* l3 s -> USBSS interface */
+static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
+ {
+ .name = "usbss",
+ .pa_start = 0x47400000,
+ .pa_end = 0x47400000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb0",
+ .pa_start = 0x47401000,
+ .pa_end = 0x47401000 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb1",
+ .pa_start = 0x47401800,
+ .pa_end = 0x47401800 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_usbss_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_usbss_addr_space,
+ .user = OCP_USER_MPU,
+ .flags = OCPIF_SWSUP_IDLE,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
+ &am33xx_l4_fw__emif_fw,
+ &am33xx_l3_main__emif,
+ &am33xx_mpu__l3_main,
+ &am33xx_mpu__prcm,
+ &am33xx_l3_s__l4_ls,
+ &am33xx_l3_s__l4_wkup,
+ &am33xx_l3_s__l4_fw,
+ &am33xx_l3_main__l4_hs,
+ &am33xx_l3_main__l3_s,
+ &am33xx_l3_main__l3_instr,
+ &am33xx_l3_main__gfx,
+ &am33xx_l3_s__l3_main,
+ &am33xx_pruss__l3_main,
+ &am33xx_wkup_m3__l4_wkup,
+ &am33xx_gfx__l3_main,
+ &am33xx_l4_wkup__wkup_m3,
+ &am33xx_l4_wkup__control,
+ &am33xx_l4_wkup__smartreflex0,
+ &am33xx_l4_wkup__smartreflex1,
+ &am33xx_l4_wkup__uart1,
+ &am33xx_l4_wkup__timer1,
+ &am33xx_l4_wkup__rtc,
+ &am33xx_l4_wkup__i2c1,
+ &am33xx_l4_wkup__gpio0,
+ &am33xx_l4_wkup__adc_tsc,
+ &am33xx_l4_wkup__wd_timer1,
+ &am33xx_l4_hs__pruss,
+ &am33xx_l4_per__dcan0,
+ &am33xx_l4_per__dcan1,
+ &am33xx_l4_per__gpio1,
+ &am33xx_l4_per__gpio2,
+ &am33xx_l4_per__gpio3,
+ &am33xx_l4_per__i2c2,
+ &am33xx_l4_per__i2c3,
+ &am33xx_l4_per__mailbox,
+ &am33xx_l4_ls__mcasp0,
+ &am33xx_l3_s__mcasp0_data,
+ &am33xx_l4_ls__mcasp1,
+ &am33xx_l3_s__mcasp1_data,
+ &am33xx_l4_ls__mmc0,
+ &am33xx_l4_ls__mmc1,
+ &am33xx_l3_s__mmc2,
+ &am33xx_l4_ls__timer2,
+ &am33xx_l4_ls__timer3,
+ &am33xx_l4_ls__timer4,
+ &am33xx_l4_ls__timer5,
+ &am33xx_l4_ls__timer6,
+ &am33xx_l4_ls__timer7,
+ &am33xx_l3_main__tpcc,
+ &am33xx_l4_ls__uart2,
+ &am33xx_l4_ls__uart3,
+ &am33xx_l4_ls__uart4,
+ &am33xx_l4_ls__uart5,
+ &am33xx_l4_ls__uart6,
+ &am33xx_l4_ls__spinlock,
+ &am33xx_l4_ls__elm,
+ &am33xx_l4_ls__ehrpwm0,
+ &am33xx_l4_ls__ehrpwm1,
+ &am33xx_l4_ls__ehrpwm2,
+ &am33xx_l4_ls__ecap0,
+ &am33xx_l4_ls__ecap1,
+ &am33xx_l4_ls__ecap2,
+ &am33xx_l3_s__gpmc,
+ &am33xx_l3_main__lcdc,
+ &am33xx_l4_ls__mcspi0,
+ &am33xx_l4_ls__mcspi1,
+ &am33xx_l3_main__tptc0,
+ &am33xx_l3_main__tptc1,
+ &am33xx_l3_main__tptc2,
+ &am33xx_l3_s__usbss,
+ &am33xx_l4_hs__cpgmac0,
+ NULL,
+};
+
+int __init am33xx_hwmod_init(void)
+{
+ omap_hwmod_init();
+ return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 6132972..9b9646c 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -658,6 +658,7 @@ extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
+extern int am33xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-07-26 20:02 ` Paul Walmsley
0 siblings, 0 replies; 28+ messages in thread
From: Paul Walmsley @ 2012-07-26 20:02 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 25 Jul 2012, Paul Walmsley wrote:
> These IP blocks and the ECAP IP blocks have periods in their names.
> The rest of the IP block named in the file don't use periods -- which
> is also the style used by the rest of the OMAP SoCs. Is there
> some reason that these have periods in their names?
I've changed those to match the rest of the names, and queued the
following for 3.7.
Thanks again for all the hard work you all put into this. I realize that
with all the upstream changes, this was probably a little painful for you.
But from my perspective you've been a pleasure to work with through the
process.
- Paul
From: Vaibhav Hiremath <hvaibhav@ti.com>
Date: Wed, 25 Jul 2012 13:51:13 -0600
Subject: [PATCH] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
This patch adds HWMOD data for all the peripherals of
AM335X device and also hooks up to the existing OMAP framework.
hwmod data has been already been cleaned up for the recent
changes in clocktree, where all leaf nodes have been removed,
since with modulemode based control, both clock and hwmod
interface does same thing. This reduces the code size to large
extent and also avoids duplication of same control.
So instead of specifying module's leaf node as a main_clk,
now we are relying on parent clock of module's functional clock.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/io.c | 2 +
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3381 ++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
4 files changed, 3385 insertions(+)
create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f6a24b3..b360328 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -194,6 +194,7 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4d2d981..408b3f0 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -523,6 +523,8 @@ void __init am33xx_init_early(void)
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
+ am33xx_hwmod_init();
+ omap_hwmod_init_postsetup();
am33xx_clk_init();
}
#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
new file mode 100644
index 0000000..16d8543
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -0,0 +1,3381 @@
+/*
+ * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
+ *
+ * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+#include <plat/gpio.h>
+#include <plat/dma.h>
+#include <plat/mmc.h>
+#include <plat/mcspi.h>
+#include <plat/i2c.h>
+
+#include "omap_hwmod_common_data.h"
+
+#include "control.h"
+#include "cm33xx.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'emif_fw' class
+ * instance(s): emif_fw
+ */
+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
+ .name = "emif_fw",
+};
+
+/* emif_fw */
+static struct omap_hwmod am33xx_emif_fw_hwmod = {
+ .name = "emif_fw",
+ .class = &am33xx_emif_fw_hwmod_class,
+ .clkdm_name = "l4fw_clkdm",
+ .main_clk = "l4fw_gclk",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'emif' class
+ * instance(s): emif
+ */
+static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
+ .rev_offs = 0x0000,
+};
+
+static struct omap_hwmod_class am33xx_emif_hwmod_class = {
+ .name = "emif",
+ .sysc = &am33xx_emif_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
+ { .name = "ddrerr0", .irq = 101 },
+ { .irq = -1 }
+};
+
+/* emif */
+static struct omap_hwmod am33xx_emif_hwmod = {
+ .name = "emif",
+ .class = &am33xx_emif_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_emif_irqs,
+ .main_clk = "dpll_ddr_m2_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_main, l3_s, l3_instr
+ */
+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+ .name = "l3",
+};
+
+/* l3_main (l3_fast) */
+static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
+ { .name = "l3debug", .irq = 9 },
+ { .name = "l3appint", .irq = 10 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_l3_main_hwmod = {
+ .name = "l3_main",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_l3_main_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l3_s */
+static struct omap_hwmod am33xx_l3_s_hwmod = {
+ .name = "l3_s",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+};
+
+/* l3_instr */
+static struct omap_hwmod am33xx_l3_instr_hwmod = {
+ .name = "l3_instr",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
+ */
+static struct omap_hwmod_class am33xx_l4_hwmod_class = {
+ .name = "l4",
+};
+
+/* l4_ls */
+static struct omap_hwmod am33xx_l4_ls_hwmod = {
+ .name = "l4_ls",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_hs */
+static struct omap_hwmod am33xx_l4_hs_hwmod = {
+ .name = "l4_hs",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4hs_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l4hs_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/* l4_wkup */
+static struct omap_hwmod am33xx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_fw */
+static struct omap_hwmod am33xx_l4_fw_hwmod = {
+ .name = "l4_fw",
+ .class = &am33xx_l4_hwmod_class,
+ .clkdm_name = "l4fw_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mpu' class
+ */
+static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
+ .name = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
+ { .name = "emuint", .irq = 0 },
+ { .name = "commtx", .irq = 1 },
+ { .name = "commrx", .irq = 2 },
+ { .name = "bench", .irq = 3 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &am33xx_mpu_hwmod_class,
+ .clkdm_name = "mpu_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_mpu_irqs,
+ .main_clk = "dpll_mpu_m2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'wakeup m3' class
+ * Wakeup controller sub-system under wakeup domain
+ */
+static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+ .name = "wkup_m3",
+};
+
+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+ { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+};
+
+static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
+ { .name = "txev", .irq = 78 },
+ { .irq = -1 }
+};
+
+/* wkup_m3 */
+static struct omap_hwmod am33xx_wkup_m3_hwmod = {
+ .name = "wkup_m3",
+ .class = &am33xx_wkup_m3_hwmod_class,
+ .clkdm_name = "l4_wkup_aon_clkdm",
+ .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
+ .mpu_irqs = am33xx_wkup_m3_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_wkup_m3_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
+};
+
+/*
+ * 'pru-icss' class
+ * Programmable Real-Time Unit and Industrial Communication Subsystem
+ */
+static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
+ .name = "pruss",
+};
+
+static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
+ { .name = "pruss", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
+ { .name = "evtout0", .irq = 20 },
+ { .name = "evtout1", .irq = 21 },
+ { .name = "evtout2", .irq = 22 },
+ { .name = "evtout3", .irq = 23 },
+ { .name = "evtout4", .irq = 24 },
+ { .name = "evtout5", .irq = 25 },
+ { .name = "evtout6", .irq = 26 },
+ { .name = "evtout7", .irq = 27 },
+ { .irq = -1 }
+};
+
+/* pru-icss */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod am33xx_pruss_hwmod = {
+ .name = "pruss",
+ .class = &am33xx_pruss_hwmod_class,
+ .clkdm_name = "pruss_ocp_clkdm",
+ .mpu_irqs = am33xx_pruss_irqs,
+ .main_clk = "pruss_ocp_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_pruss_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
+};
+
+/* gfx */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
+ .name = "gfx",
+};
+
+static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
+ { .name = "gfx", .rst_shift = 0 },
+};
+
+static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
+ { .name = "gfxint", .irq = 37 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gfx_hwmod = {
+ .name = "gfx",
+ .class = &am33xx_gfx_hwmod_class,
+ .clkdm_name = "gfx_l3_clkdm",
+ .mpu_irqs = am33xx_gfx_irqs,
+ .main_clk = "gfx_fck_div_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .rst_lines = am33xx_gfx_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
+};
+
+/*
+ * 'prcm' class
+ * power and reset manager (whole prcm infrastructure)
+ */
+static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
+ .name = "prcm",
+};
+
+/* prcm */
+static struct omap_hwmod am33xx_prcm_hwmod = {
+ .name = "prcm",
+ .class = &am33xx_prcm_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+};
+
+/*
+ * 'adc/tsc' class
+ * TouchScreen Controller (Anolog-To-Digital Converter)
+ */
+static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x10,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
+ .name = "adc_tsc",
+ .sysc = &am33xx_adc_tsc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
+ { .irq = 16 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_adc_tsc_hwmod = {
+ .name = "adc_tsc",
+ .class = &am33xx_adc_tsc_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_adc_tsc_irqs,
+ .main_clk = "adc_tsc_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * Modules omap_hwmod structures
+ *
+ * The following IPs are excluded for the moment because:
+ * - They do not need an explicit SW control using omap_hwmod API.
+ * - They still need to be validated with the driver
+ * properly adapted to omap_hwmod / omap_device
+ *
+ * - cEFUSE (doesn't fall under any ocp_if)
+ * - clkdiv32k
+ * - debugss
+ * - ocmc ram
+ * - ocp watch point
+ * - aes0
+ * - sha0
+ */
+#if 0
+/*
+ * 'cefuse' class
+ */
+static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
+ .name = "cefuse",
+};
+
+static struct omap_hwmod am33xx_cefuse_hwmod = {
+ .name = "cefuse",
+ .class = &am33xx_cefuse_hwmod_class,
+ .clkdm_name = "l4_cefuse_clkdm",
+ .main_clk = "cefuse_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'clkdiv32k' class
+ */
+static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
+ .name = "clkdiv32k",
+};
+
+static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
+ .name = "clkdiv32k",
+ .class = &am33xx_clkdiv32k_hwmod_class,
+ .clkdm_name = "clk_24mhz_clkdm",
+ .main_clk = "clkdiv32k_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'debugss' class
+ * debug sub system
+ */
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+ .name = "debugss",
+};
+
+static struct omap_hwmod am33xx_debugss_hwmod = {
+ .name = "debugss",
+ .class = &am33xx_debugss_hwmod_class,
+ .clkdm_name = "l3_aon_clkdm",
+ .main_clk = "debugss_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+ .name = "ocmcram",
+};
+
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+ .name = "ocmcram",
+ .class = &am33xx_ocmcram_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ocpwp */
+static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
+ .name = "ocpwp",
+};
+
+static struct omap_hwmod am33xx_ocpwp_hwmod = {
+ .name = "ocpwp",
+ .class = &am33xx_ocpwp_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'aes' class
+ */
+static struct omap_hwmod_class am33xx_aes_hwmod_class = {
+ .name = "aes",
+};
+
+static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
+ { .irq = 102 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_aes0_hwmod = {
+ .name = "aes0",
+ .class = &am33xx_aes_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_aes0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* sha0 */
+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+ .name = "sha0",
+};
+
+static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
+ { .irq = 108 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_sha0_hwmod = {
+ .name = "sha0",
+ .class = &am33xx_sha0_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_sha0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+#endif
+
+/* 'smartreflex' class */
+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+ .name = "smartreflex",
+};
+
+/* smartreflex0 */
+static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
+ { .irq = 120 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_smartreflex0_hwmod = {
+ .name = "smartreflex0",
+ .class = &am33xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_smartreflex0_irqs,
+ .main_clk = "smartreflex0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* smartreflex1 */
+static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
+ { .irq = 121 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_smartreflex1_hwmod = {
+ .name = "smartreflex1",
+ .class = &am33xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_smartreflex1_irqs,
+ .main_clk = "smartreflex1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'control' module class
+ */
+static struct omap_hwmod_class am33xx_control_hwmod_class = {
+ .name = "control",
+};
+
+static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
+ { .irq = 8 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_control_hwmod = {
+ .name = "control",
+ .class = &am33xx_control_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_control_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'cpgmac' class
+ * cpsw/cpgmac sub system
+ */
+static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x8,
+ .syss_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+ MSTANDBY_NO),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+ .name = "cpgmac0",
+ .sysc = &am33xx_cpgmac_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
+ { .name = "c0_rx_thresh_pend", .irq = 40 },
+ { .name = "c0_rx_pend", .irq = 41 },
+ { .name = "c0_tx_pend", .irq = 42 },
+ { .name = "c0_misc_pend", .irq = 43 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_cpgmac0_hwmod = {
+ .name = "cpgmac0",
+ .class = &am33xx_cpgmac0_hwmod_class,
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .mpu_irqs = am33xx_cpgmac0_irqs,
+ .main_clk = "cpsw_125mhz_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * dcan class
+ */
+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+ .name = "d_can",
+};
+
+/* dcan0 */
+static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
+ { .name = "d_can_ms", .irq = 52 },
+ { .name = "d_can_mo", .irq = 53 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_dcan0_hwmod = {
+ .name = "d_can0",
+ .class = &am33xx_dcan_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_dcan0_irqs,
+ .main_clk = "dcan0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* dcan1 */
+static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
+ { .name = "d_can_ms", .irq = 55 },
+ { .name = "d_can_mo", .irq = 56 },
+ { .irq = -1 }
+};
+static struct omap_hwmod am33xx_dcan1_hwmod = {
+ .name = "d_can1",
+ .class = &am33xx_dcan_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_dcan1_irqs,
+ .main_clk = "dcan1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* elm */
+static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+ .name = "elm",
+ .sysc = &am33xx_elm_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
+ { .irq = 4 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_elm_hwmod = {
+ .name = "elm",
+ .class = &am33xx_elm_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_elm_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
+ */
+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+ .name = "epwmss",
+ .sysc = &am33xx_epwmss_sysc,
+};
+
+/* ehrpwm0 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
+ { .name = "int", .irq = 86 },
+ { .name = "tzint", .irq = 58 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+ .name = "ehrpwm0",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm0_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ehrpwm1 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+ { .name = "int", .irq = 87 },
+ { .name = "tzint", .irq = 59 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+ .name = "ehrpwm1",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ehrpwm2 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+ { .name = "int", .irq = 39 },
+ { .name = "tzint", .irq = 60 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+ .name = "ehrpwm2",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ehrpwm2_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap0 */
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+ { .irq = 31 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap0_hwmod = {
+ .name = "ecap0",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ecap0_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap1 */
+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
+ { .irq = 47 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap1_hwmod = {
+ .name = "ecap1",
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_ecap1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* ecap2 */
+static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
+ { .irq = 61 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_ecap2_hwmod = {
+ .name = "ecap2",
+ .mpu_irqs = am33xx_ecap2_irqs,
+ .class = &am33xx_epwmss_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'gpio' class: for gpio 0,1,2,3
+ */
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &am33xx_gpio_sysc,
+ .rev = 2,
+};
+
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio0 */
+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio0_dbclk" },
+};
+
+static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
+ { .irq = 96 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gpio0_hwmod = {
+ .name = "gpio1",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio0_irqs,
+ .main_clk = "dpll_core_m4_div2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio0_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
+ { .irq = 98 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio1_hwmod = {
+ .name = "gpio2",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio1_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
+ { .irq = 32 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio2_hwmod = {
+ .name = "gpio3",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio2_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
+ { .irq = 62 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio3_hwmod = {
+ .name = "gpio4",
+ .class = &am33xx_gpio_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio3_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpmc */
+static struct omap_hwmod_class_sysconfig gpmc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+ .name = "gpmc",
+ .sysc = &gpmc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
+ { .irq = 100 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_gpmc_hwmod = {
+ .name = "gpmc",
+ .class = &am33xx_gpmc_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = am33xx_gpmc_irqs,
+ .main_clk = "l3s_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'i2c' class */
+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0090,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &am33xx_i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_2,
+ .reset = &omap_i2c_reset,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = 70 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &i2c_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_wkupdm_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = 71 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &i2c_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+ { .irq = 30 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &i2c_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = i2c3_mpu_irqs,
+ .sdma_reqs = i2c3_edma_reqs,
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+
+/* lcdc */
+static struct omap_hwmod_class_sysconfig lcdc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x54,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
+ .name = "lcdc",
+ .sysc = &lcdc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
+ { .irq = 36 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_lcdc_hwmod = {
+ .name = "lcdc",
+ .class = &am33xx_lcdc_hwmod_class,
+ .clkdm_name = "lcdc_clkdm",
+ .mpu_irqs = am33xx_lcdc_irqs,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "lcd_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &am33xx_mailbox_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
+ { .irq = 77 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &am33xx_mailbox_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mailbox_irqs,
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mcasp' class
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+ .name = "mcasp",
+ .sysc = &am33xx_mcasp_sysc,
+};
+
+/* mcasp0 */
+static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
+ { .name = "ax", .irq = 80, },
+ { .name = "ar", .irq = 81, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
+ { .name = "tx", .dma_req = 8, },
+ { .name = "rx", .dma_req = 9, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp0_hwmod = {
+ .name = "mcasp0",
+ .class = &am33xx_mcasp_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mcasp0_irqs,
+ .sdma_reqs = am33xx_mcasp0_edma_reqs,
+ .main_clk = "mcasp0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp1 */
+static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
+ { .name = "ax", .irq = 82, },
+ { .name = "ar", .irq = 83, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 10, },
+ { .name = "rx", .dma_req = 11, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp1_hwmod = {
+ .name = "mcasp1",
+ .class = &am33xx_mcasp_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mcasp1_irqs,
+ .sdma_reqs = am33xx_mcasp1_edma_reqs,
+ .main_clk = "mcasp1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'mmc' class */
+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+ .rev_offs = 0x1fc,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+ .name = "mmc",
+ .sysc = &am33xx_mmc_sysc,
+};
+
+/* mmc0 */
+static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
+ { .irq = 64 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
+ { .name = "tx", .dma_req = 24, },
+ { .name = "rx", .dma_req = 25, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc0_hwmod = {
+ .name = "mmc1",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mmc0_irqs,
+ .sdma_reqs = am33xx_mmc0_edma_reqs,
+ .main_clk = "mmc_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc0_dev_attr,
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
+ { .irq = 28 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 2, },
+ { .name = "rx", .dma_req = 3, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc1_hwmod = {
+ .name = "mmc2",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mmc1_irqs,
+ .sdma_reqs = am33xx_mmc1_edma_reqs,
+ .main_clk = "mmc_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
+ { .irq = 29 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 64, },
+ { .name = "rx", .dma_req = 65, },
+ { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc2_hwmod = {
+ .name = "mmc3",
+ .class = &am33xx_mmc_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_mmc2_irqs,
+ .sdma_reqs = am33xx_mmc2_edma_reqs,
+ .main_clk = "mmc2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc2_dev_attr,
+};
+
+/*
+ * 'rtc' class
+ * rtc subsystem
+ */
+static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
+ .rev_offs = 0x0074,
+ .sysc_offs = 0x0078,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO |
+ SIDLE_SMART | SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+ .name = "rtc",
+ .sysc = &am33xx_rtc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
+ { .name = "rtcint", .irq = 75 },
+ { .name = "rtcalarmint", .irq = 76 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_rtc_hwmod = {
+ .name = "rtc",
+ .class = &am33xx_rtc_hwmod_class,
+ .clkdm_name = "l4_rtc_clkdm",
+ .mpu_irqs = am33xx_rtc_irqs,
+ .main_clk = "clk_32768_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'spi' class */
+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0110,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_spi_hwmod_class = {
+ .name = "mcspi",
+ .sysc = &am33xx_mcspi_sysc,
+ .rev = OMAP4_MCSPI_REV,
+};
+
+/* spi0 */
+static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
+ { .irq = 65 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
+ { .name = "rx0", .dma_req = 17 },
+ { .name = "tx0", .dma_req = 16 },
+ { .name = "rx1", .dma_req = 19 },
+ { .name = "tx1", .dma_req = 18 },
+ { .dma_req = -1 }
+};
+
+static struct omap2_mcspi_dev_attr mcspi_attrib = {
+ .num_chipselect = 2,
+};
+static struct omap_hwmod am33xx_spi0_hwmod = {
+ .name = "spi0",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_spi0_irqs,
+ .sdma_reqs = am33xx_mcspi0_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+/* spi1 */
+static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
+ { .irq = 125 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
+ { .name = "rx0", .dma_req = 43 },
+ { .name = "tx0", .dma_req = 42 },
+ { .name = "rx1", .dma_req = 45 },
+ { .name = "tx1", .dma_req = 44 },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_spi1_hwmod = {
+ .name = "spi1",
+ .class = &am33xx_spi_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_spi1_irqs,
+ .sdma_reqs = am33xx_mcspi1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+};
+
+/*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the
+ * processes running on multiple processors
+ */
+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+ .name = "spinlock",
+};
+
+static struct omap_hwmod am33xx_spinlock_hwmod = {
+ .name = "spinlock",
+ .class = &am33xx_spinlock_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .main_clk = "l4ls_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'timer 2-7' class */
+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &am33xx_timer_sysc,
+};
+
+/* timer1 1ms */
+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &am33xx_timer1ms_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
+ { .irq = 67 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &am33xx_timer1ms_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_timer1_irqs,
+ .main_clk = "timer1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
+ { .irq = 68 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer2_irqs,
+ .main_clk = "timer2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
+ { .irq = 69 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer3_irqs,
+ .main_clk = "timer3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
+ { .irq = 92 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer4_irqs,
+ .main_clk = "timer4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
+ { .irq = 93 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer5_irqs,
+ .main_clk = "timer5_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
+ { .irq = 94 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer6_irqs,
+ .main_clk = "timer6_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
+ { .irq = 95 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &am33xx_timer_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_timer7_irqs,
+ .main_clk = "timer7_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tpcc */
+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+ .name = "tpcc",
+};
+
+static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
+ { .name = "edma0", .irq = 12 },
+ { .name = "edma0_mperr", .irq = 13, },
+ { .name = "edma0_err", .irq = 14 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tpcc_hwmod = {
+ .name = "tpcc",
+ .class = &am33xx_tpcc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tpcc_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+/* 'tptc' class */
+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+ .name = "tptc",
+ .sysc = &am33xx_tptc_sysc,
+};
+
+/* tptc0 */
+static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
+ { .irq = 112 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc0_hwmod = {
+ .name = "tptc0",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc0_irqs,
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc1 */
+static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
+ { .irq = 113 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc1_hwmod = {
+ .name = "tptc1",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc1_irqs,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc2 */
+static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
+ { .irq = 114 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_tptc2_hwmod = {
+ .name = "tptc2",
+ .class = &am33xx_tptc_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .mpu_irqs = am33xx_tptc2_irqs,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'uart' class */
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+ .rev_offs = 0x50,
+ .sysc_offs = 0x54,
+ .syss_offs = 0x58,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+ .name = "uart",
+ .sysc = &uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 26, },
+ { .name = "rx", .dma_req = 27, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
+ { .irq = 72 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart1_hwmod = {
+ .name = "uart1",
+ .class = &uart_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = am33xx_uart1_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_wkupdm_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
+ { .irq = 73 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart2_hwmod = {
+ .name = "uart2",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart2_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart3 */
+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 30, },
+ { .name = "rx", .dma_req = 31, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
+ { .irq = 74 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart3_hwmod = {
+ .name = "uart3",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart3_irqs,
+ .sdma_reqs = uart3_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
+ { .irq = 44 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart4_hwmod = {
+ .name = "uart4",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart4_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
+ { .irq = 45 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart5_hwmod = {
+ .name = "uart5",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart5_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
+ { .irq = 46 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_uart6_hwmod = {
+ .name = "uart6",
+ .class = &uart_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_uart6_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "dpll_per_m2_div4_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'wd_timer' class */
+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+};
+
+/*
+ * XXX: device.c file uses hardcoded name for watchdog timer
+ * driver "wd_timer2, so we are also using same name as of now...
+ */
+static struct omap_hwmod am33xx_wd_timer1_hwmod = {
+ .name = "wd_timer2",
+ .class = &am33xx_wd_timer_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .main_clk = "wdt1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'usb_otg' class
+ * high-speed on-the-go universal serial bus (usb_otg) controller
+ */
+static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_usbotg_class = {
+ .name = "usbotg",
+ .sysc = &am33xx_usbhsotg_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
+ { .name = "usbss-irq", .irq = 17, },
+ { .name = "musb0-irq", .irq = 18, },
+ { .name = "musb1-irq", .irq = 19, },
+ { .irq = -1, },
+};
+
+static struct omap_hwmod am33xx_usbss_hwmod = {
+ .name = "usb_otg_hs",
+ .class = &am33xx_usbotg_class,
+ .clkdm_name = "l3s_clkdm",
+ .mpu_irqs = am33xx_usbss_mpu_irqs,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "usbotg_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l4 fw -> emif fw */
+static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
+ .master = &am33xx_l4_fw_hwmod,
+ .slave = &am33xx_emif_fw_hwmod,
+ .clk = "l4fw_gclk",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
+ {
+ .pa_start = 0x4c000000,
+ .pa_end = 0x4c000fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+/* l3 main -> emif */
+static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_emif_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_emif_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
+ .master = &am33xx_mpu_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "dpll_mpu_m2_ck",
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> l4 hs */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l4_hs_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 s */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l3_s_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 per/ls */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_ls_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_wkup_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 fw */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l4_fw_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 instr */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_l3_instr_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> prcm */
+static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
+ .master = &am33xx_mpu_hwmod,
+ .slave = &am33xx_prcm_hwmod,
+ .clk = "dpll_mpu_m2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l3 main*/
+static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "l3s_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* pru-icss -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
+ .master = &am33xx_pruss_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "l3_gclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* wkup m3 -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
+ .master = &am33xx_wkup_m3_hwmod,
+ .slave = &am33xx_l4_wkup_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gfx -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
+ .master = &am33xx_gfx_hwmod,
+ .slave = &am33xx_l3_main_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> wkup m3 */
+static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
+ {
+ .name = "umem",
+ .pa_start = 0x44d00000,
+ .pa_end = 0x44d00000 + SZ_16K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "dmem",
+ .pa_start = 0x44d80000,
+ .pa_end = 0x44d80000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_wkup_m3_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_wkup_m3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 hs -> pru-icss */
+static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
+ {
+ .pa_start = 0x4a300000,
+ .pa_end = 0x4a300000 + SZ_512K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
+ .master = &am33xx_l4_hs_hwmod,
+ .slave = &am33xx_pruss_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_pruss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> gfx */
+static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
+ {
+ .pa_start = 0x56000000,
+ .pa_end = 0x56000000 + SZ_16M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_gfx_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_gfx_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> smartreflex0 */
+static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
+ {
+ .pa_start = 0x44e37000,
+ .pa_end = 0x44e37000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_smartreflex0_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_smartreflex0_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> smartreflex1 */
+static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
+ {
+ .pa_start = 0x44e39000,
+ .pa_end = 0x44e39000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_smartreflex1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_smartreflex1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> control */
+static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
+ {
+ .pa_start = 0x44e10000,
+ .pa_end = 0x44e10000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_control_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_control_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> rtc */
+static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
+ {
+ .pa_start = 0x44e3e000,
+ .pa_end = 0x44e3e000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_rtc_hwmod,
+ .clk = "clkdiv32k_ick",
+ .addr = am33xx_rtc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per/ls -> DCAN0 */
+static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
+ {
+ .pa_start = 0x481CC000,
+ .pa_end = 0x481CC000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_dcan0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_dcan0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> DCAN1 */
+static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
+ {
+ .pa_start = 0x481D0000,
+ .pa_end = 0x481D0000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_dcan1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_dcan1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> GPIO2 */
+static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
+ {
+ .pa_start = 0x4804C000,
+ .pa_end = 0x4804C000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio3 */
+static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
+ {
+ .pa_start = 0x481AC000,
+ .pa_end = 0x481AC000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio4 */
+static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
+ {
+ .pa_start = 0x481AE000,
+ .pa_end = 0x481AE000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_gpio3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_gpio3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> I2C1 */
+static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
+ {
+ .pa_start = 0x44E0B000,
+ .pa_end = 0x44E0B000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_i2c1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_i2c1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* L4 WKUP -> GPIO1 */
+static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
+ {
+ .pa_start = 0x44E07000,
+ .pa_end = 0x44E07000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_gpio0_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_gpio0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> ADC_TSC */
+static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
+ {
+ .pa_start = 0x44E0D000,
+ .pa_end = 0x44E0D000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_adc_tsc_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_adc_tsc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+ /* cpsw ss */
+ {
+ .pa_start = 0x4a100000,
+ .pa_end = 0x4a100000 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ /* cpsw wr */
+ {
+ .pa_start = 0x4a101200,
+ .pa_end = 0x4a101200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
+ .master = &am33xx_l4_hs_hwmod,
+ .slave = &am33xx_cpgmac0_hwmod,
+ .clk = "cpsw_125mhz_gclk",
+ .addr = am33xx_cpgmac0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
+ {
+ .pa_start = 0x48080000,
+ .pa_end = 0x48080000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_elm_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_elm_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
+ {
+ .pa_start = 0x48300000,
+ .pa_end = 0x48300000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48300200,
+ .pa_end = 0x48300200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
+ {
+ .pa_start = 0x48302000,
+ .pa_end = 0x48302000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48302200,
+ .pa_end = 0x48302200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+ {
+ .pa_start = 0x48304000,
+ .pa_end = 0x48304000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48304200,
+ .pa_end = 0x48304200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ehrpwm2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ehrpwm2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
+ {
+ .pa_start = 0x48300000,
+ .pa_end = 0x48300000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48300100,
+ .pa_end = 0x48300100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
+ {
+ .pa_start = 0x48302000,
+ .pa_end = 0x48302000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48302100,
+ .pa_end = 0x48302100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+ {
+ .pa_start = 0x48304000,
+ .pa_end = 0x48304000 + SZ_16 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48304100,
+ .pa_end = 0x48304100 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_ecap2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_ecap2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3s cfg -> gpmc */
+static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
+ {
+ .pa_start = 0x50000000,
+ .pa_end = 0x50000000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_gpmc_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_gpmc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* i2c2 */
+static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
+ {
+ .pa_start = 0x4802A000,
+ .pa_end = 0x4802A000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_i2c2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_i2c2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
+ {
+ .pa_start = 0x4819C000,
+ .pa_end = 0x4819C000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_i2c3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_i2c3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
+ {
+ .pa_start = 0x4830E000,
+ .pa_end = 0x4830E000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_lcdc_hwmod,
+ .clk = "dpll_core_m4_ck",
+ .addr = am33xx_lcdc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x480C8000,
+ .pa_end = 0x480C8000 + (SZ_4K - 1),
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4 ls -> mailbox */
+static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mailbox_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mailbox_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> spinlock */
+static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
+ {
+ .pa_start = 0x480Ca000,
+ .pa_end = 0x480Ca000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spinlock_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_spinlock_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcasp0 */
+static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
+ {
+ .pa_start = 0x48038000,
+ .pa_end = 0x48038000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mcasp0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcasp0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp0 data */
+static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
+ {
+ .pa_start = 0x46000000,
+ .pa_end = 0x46000000 + SZ_4M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mcasp0_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mcasp0_data_addr_space,
+ .user = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mcasp1 */
+static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
+ {
+ .pa_start = 0x4803C000,
+ .pa_end = 0x4803C000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mcasp1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcasp1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp1 data */
+static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
+ {
+ .pa_start = 0x46400000,
+ .pa_end = 0x46400000 + SZ_4M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mcasp1_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mcasp1_data_addr_space,
+ .user = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mmc0 */
+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+ {
+ .pa_start = 0x48060100,
+ .pa_end = 0x48060100 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mmc0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mmc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mmc1 */
+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+ {
+ .pa_start = 0x481d8100,
+ .pa_end = 0x481d8100 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_mmc1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mmc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 s -> mmc2 */
+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+ {
+ .pa_start = 0x47810100,
+ .pa_end = 0x47810100 + SZ_64K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_mmc2_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_mmc2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi0 */
+static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
+ {
+ .pa_start = 0x48030000,
+ .pa_end = 0x48030000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spi0_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcspi0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi1 */
+static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
+ {
+ .pa_start = 0x481A0000,
+ .pa_end = 0x481A0000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_spi1_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_mcspi1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> timer1 */
+static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
+ {
+ .pa_start = 0x44E31000,
+ .pa_end = 0x44E31000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_timer1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_timer1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer2 */
+static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
+ {
+ .pa_start = 0x48040000,
+ .pa_end = 0x48040000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer3 */
+static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
+ {
+ .pa_start = 0x48042000,
+ .pa_end = 0x48042000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer4 */
+static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
+ {
+ .pa_start = 0x48044000,
+ .pa_end = 0x48044000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer4_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer4_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer5 */
+static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
+ {
+ .pa_start = 0x48046000,
+ .pa_end = 0x48046000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer5_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer5_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer6 */
+static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
+ {
+ .pa_start = 0x48048000,
+ .pa_end = 0x48048000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer6_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer6_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 per -> timer7 */
+static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
+ {
+ .pa_start = 0x4804A000,
+ .pa_end = 0x4804A000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_timer7_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_timer7_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc */
+static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
+ {
+ .pa_start = 0x49000000,
+ .pa_end = 0x49000000 + SZ_32K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tpcc_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tpcc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc0 */
+static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
+ {
+ .pa_start = 0x49800000,
+ .pa_end = 0x49800000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc0_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc1 */
+static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
+ {
+ .pa_start = 0x49900000,
+ .pa_end = 0x49900000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc1_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc2 */
+static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
+ {
+ .pa_start = 0x49a00000,
+ .pa_end = 0x49a00000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc2_hwmod,
+ .clk = "l3_gclk",
+ .addr = am33xx_tptc2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> uart1 */
+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
+ {
+ .pa_start = 0x44E09000,
+ .pa_end = 0x44E09000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_uart1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_uart1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart2 */
+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
+ {
+ .pa_start = 0x48022000,
+ .pa_end = 0x48022000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart2_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart3 */
+static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
+ {
+ .pa_start = 0x48024000,
+ .pa_end = 0x48024000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart3_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart4 */
+static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
+ {
+ .pa_start = 0x481A6000,
+ .pa_end = 0x481A6000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart4_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart4_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart5 */
+static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
+ {
+ .pa_start = 0x481A8000,
+ .pa_end = 0x481A8000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart5_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart5_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart6 */
+static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
+ {
+ .pa_start = 0x481aa000,
+ .pa_end = 0x481aa000 + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+ .master = &am33xx_l4_ls_hwmod,
+ .slave = &am33xx_uart6_hwmod,
+ .clk = "l4ls_gclk",
+ .addr = am33xx_uart6_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4 wkup -> wd_timer1 */
+static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
+ {
+ .pa_start = 0x44e35000,
+ .pa_end = 0x44e35000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
+ .master = &am33xx_l4_wkup_hwmod,
+ .slave = &am33xx_wd_timer1_hwmod,
+ .clk = "dpll_core_m4_div2_ck",
+ .addr = am33xx_wd_timer1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* usbss */
+/* l3 s -> USBSS interface */
+static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
+ {
+ .name = "usbss",
+ .pa_start = 0x47400000,
+ .pa_end = 0x47400000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb0",
+ .pa_start = 0x47401000,
+ .pa_end = 0x47401000 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb1",
+ .pa_start = 0x47401800,
+ .pa_end = 0x47401800 + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
+ .master = &am33xx_l3_s_hwmod,
+ .slave = &am33xx_usbss_hwmod,
+ .clk = "l3s_gclk",
+ .addr = am33xx_usbss_addr_space,
+ .user = OCP_USER_MPU,
+ .flags = OCPIF_SWSUP_IDLE,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
+ &am33xx_l4_fw__emif_fw,
+ &am33xx_l3_main__emif,
+ &am33xx_mpu__l3_main,
+ &am33xx_mpu__prcm,
+ &am33xx_l3_s__l4_ls,
+ &am33xx_l3_s__l4_wkup,
+ &am33xx_l3_s__l4_fw,
+ &am33xx_l3_main__l4_hs,
+ &am33xx_l3_main__l3_s,
+ &am33xx_l3_main__l3_instr,
+ &am33xx_l3_main__gfx,
+ &am33xx_l3_s__l3_main,
+ &am33xx_pruss__l3_main,
+ &am33xx_wkup_m3__l4_wkup,
+ &am33xx_gfx__l3_main,
+ &am33xx_l4_wkup__wkup_m3,
+ &am33xx_l4_wkup__control,
+ &am33xx_l4_wkup__smartreflex0,
+ &am33xx_l4_wkup__smartreflex1,
+ &am33xx_l4_wkup__uart1,
+ &am33xx_l4_wkup__timer1,
+ &am33xx_l4_wkup__rtc,
+ &am33xx_l4_wkup__i2c1,
+ &am33xx_l4_wkup__gpio0,
+ &am33xx_l4_wkup__adc_tsc,
+ &am33xx_l4_wkup__wd_timer1,
+ &am33xx_l4_hs__pruss,
+ &am33xx_l4_per__dcan0,
+ &am33xx_l4_per__dcan1,
+ &am33xx_l4_per__gpio1,
+ &am33xx_l4_per__gpio2,
+ &am33xx_l4_per__gpio3,
+ &am33xx_l4_per__i2c2,
+ &am33xx_l4_per__i2c3,
+ &am33xx_l4_per__mailbox,
+ &am33xx_l4_ls__mcasp0,
+ &am33xx_l3_s__mcasp0_data,
+ &am33xx_l4_ls__mcasp1,
+ &am33xx_l3_s__mcasp1_data,
+ &am33xx_l4_ls__mmc0,
+ &am33xx_l4_ls__mmc1,
+ &am33xx_l3_s__mmc2,
+ &am33xx_l4_ls__timer2,
+ &am33xx_l4_ls__timer3,
+ &am33xx_l4_ls__timer4,
+ &am33xx_l4_ls__timer5,
+ &am33xx_l4_ls__timer6,
+ &am33xx_l4_ls__timer7,
+ &am33xx_l3_main__tpcc,
+ &am33xx_l4_ls__uart2,
+ &am33xx_l4_ls__uart3,
+ &am33xx_l4_ls__uart4,
+ &am33xx_l4_ls__uart5,
+ &am33xx_l4_ls__uart6,
+ &am33xx_l4_ls__spinlock,
+ &am33xx_l4_ls__elm,
+ &am33xx_l4_ls__ehrpwm0,
+ &am33xx_l4_ls__ehrpwm1,
+ &am33xx_l4_ls__ehrpwm2,
+ &am33xx_l4_ls__ecap0,
+ &am33xx_l4_ls__ecap1,
+ &am33xx_l4_ls__ecap2,
+ &am33xx_l3_s__gpmc,
+ &am33xx_l3_main__lcdc,
+ &am33xx_l4_ls__mcspi0,
+ &am33xx_l4_ls__mcspi1,
+ &am33xx_l3_main__tptc0,
+ &am33xx_l3_main__tptc1,
+ &am33xx_l3_main__tptc2,
+ &am33xx_l3_s__usbss,
+ &am33xx_l4_hs__cpgmac0,
+ NULL,
+};
+
+int __init am33xx_hwmod_init(void)
+{
+ omap_hwmod_init();
+ return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 6132972..9b9646c 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -658,6 +658,7 @@ extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
+extern int am33xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* RE: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-07-26 20:02 ` Paul Walmsley
@ 2012-07-27 8:36 ` Hiremath, Vaibhav
-1 siblings, 0 replies; 28+ messages in thread
From: Hiremath, Vaibhav @ 2012-07-27 8:36 UTC (permalink / raw)
To: Paul Walmsley
Cc: linux-omap, linux-arm-kernel, Mohammed, Afzal, Bedia, Vaibhav,
Cousson, Benoit, Tony Lindgren, Hilman, Kevin, Nayak, Rajendra
On Fri, Jul 27, 2012 at 01:32:33, Paul Walmsley wrote:
> On Wed, 25 Jul 2012, Paul Walmsley wrote:
>
> > These IP blocks and the ECAP IP blocks have periods in their names.
> > The rest of the IP block named in the file don't use periods -- which
> > is also the style used by the rest of the OMAP SoCs. Is there
> > some reason that these have periods in their names?
>
> I've changed those to match the rest of the names, and queued the
> following for 3.7.
>
> Thanks again for all the hard work you all put into this. I realize that
> with all the upstream changes, this was probably a little painful for you.
> But from my perspective you've been a pleasure to work with through the
> process.
>
Thanks Paul for the appreciation, yes, it was pleasure to work with through
the process. And it would not have been possible without your support and
patience.
Still very long way ahead of me...now I can concentrate on other TODO
list which are dependent on basic baseport stuff and
cleanup/feature-addition to existing OMAP code.
Thanks,
Vaibhav
>
> - Paul
>
>
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> Date: Wed, 25 Jul 2012 13:51:13 -0600
> Subject: [PATCH] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
>
> This patch adds HWMOD data for all the peripherals of
> AM335X device and also hooks up to the existing OMAP framework.
>
> hwmod data has been already been cleaned up for the recent
> changes in clocktree, where all leaf nodes have been removed,
> since with modulemode based control, both clock and hwmod
> interface does same thing. This reduces the code size to large
> extent and also avoids duplication of same control.
> So instead of specifying module's leaf node as a main_clk,
> now we are relying on parent clock of module's functional clock.
>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> Cc: Paul Walmsley <paul@pwsan.com>
> Cc: Benoit Cousson <b-cousson@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Kevin Hilman <khilman@ti.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> ---
> arch/arm/mach-omap2/Makefile | 1 +
> arch/arm/mach-omap2/io.c | 2 +
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3381 ++++++++++++++++++++++++++
> arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
> 4 files changed, 3385 insertions(+)
> create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index f6a24b3..b360328 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -194,6 +194,7 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
> obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
> obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
> obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
> +obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
>
> # EMU peripherals
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index 4d2d981..408b3f0 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -523,6 +523,8 @@ void __init am33xx_init_early(void)
> am33xx_voltagedomains_init();
> am33xx_powerdomains_init();
> am33xx_clockdomains_init();
> + am33xx_hwmod_init();
> + omap_hwmod_init_postsetup();
> am33xx_clk_init();
> }
> #endif
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> new file mode 100644
> index 0000000..16d8543
> --- /dev/null
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -0,0 +1,3381 @@
> +/*
> + * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
> + *
> + * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This file is automatically generated from the AM33XX hardware databases.
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <plat/omap_hwmod.h>
> +#include <plat/cpu.h>
> +#include <plat/gpio.h>
> +#include <plat/dma.h>
> +#include <plat/mmc.h>
> +#include <plat/mcspi.h>
> +#include <plat/i2c.h>
> +
> +#include "omap_hwmod_common_data.h"
> +
> +#include "control.h"
> +#include "cm33xx.h"
> +#include "prm33xx.h"
> +#include "prm-regbits-33xx.h"
> +
> +/*
> + * IP blocks
> + */
> +
> +/*
> + * 'emif_fw' class
> + * instance(s): emif_fw
> + */
> +static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
> + .name = "emif_fw",
> +};
> +
> +/* emif_fw */
> +static struct omap_hwmod am33xx_emif_fw_hwmod = {
> + .name = "emif_fw",
> + .class = &am33xx_emif_fw_hwmod_class,
> + .clkdm_name = "l4fw_clkdm",
> + .main_clk = "l4fw_gclk",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'emif' class
> + * instance(s): emif
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
> + .rev_offs = 0x0000,
> +};
> +
> +static struct omap_hwmod_class am33xx_emif_hwmod_class = {
> + .name = "emif",
> + .sysc = &am33xx_emif_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
> + { .name = "ddrerr0", .irq = 101 },
> + { .irq = -1 }
> +};
> +
> +/* emif */
> +static struct omap_hwmod am33xx_emif_hwmod = {
> + .name = "emif",
> + .class = &am33xx_emif_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .mpu_irqs = am33xx_emif_irqs,
> + .main_clk = "dpll_ddr_m2_div2_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'l3' class
> + * instance(s): l3_main, l3_s, l3_instr
> + */
> +static struct omap_hwmod_class am33xx_l3_hwmod_class = {
> + .name = "l3",
> +};
> +
> +/* l3_main (l3_fast) */
> +static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
> + { .name = "l3debug", .irq = 9 },
> + { .name = "l3appint", .irq = 10 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_l3_main_hwmod = {
> + .name = "l3_main",
> + .class = &am33xx_l3_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .mpu_irqs = am33xx_l3_main_irqs,
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* l3_s */
> +static struct omap_hwmod am33xx_l3_s_hwmod = {
> + .name = "l3_s",
> + .class = &am33xx_l3_hwmod_class,
> + .clkdm_name = "l3s_clkdm",
> +};
> +
> +/* l3_instr */
> +static struct omap_hwmod am33xx_l3_instr_hwmod = {
> + .name = "l3_instr",
> + .class = &am33xx_l3_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'l4' class
> + * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
> + */
> +static struct omap_hwmod_class am33xx_l4_hwmod_class = {
> + .name = "l4",
> +};
> +
> +/* l4_ls */
> +static struct omap_hwmod am33xx_l4_ls_hwmod = {
> + .name = "l4_ls",
> + .class = &am33xx_l4_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* l4_hs */
> +static struct omap_hwmod am33xx_l4_hs_hwmod = {
> + .name = "l4_hs",
> + .class = &am33xx_l4_hwmod_class,
> + .clkdm_name = "l4hs_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .main_clk = "l4hs_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +
> +/* l4_wkup */
> +static struct omap_hwmod am33xx_l4_wkup_hwmod = {
> + .name = "l4_wkup",
> + .class = &am33xx_l4_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* l4_fw */
> +static struct omap_hwmod am33xx_l4_fw_hwmod = {
> + .name = "l4_fw",
> + .class = &am33xx_l4_hwmod_class,
> + .clkdm_name = "l4fw_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'mpu' class
> + */
> +static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
> + .name = "mpu",
> +};
> +
> +/* mpu */
> +static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
> + { .name = "emuint", .irq = 0 },
> + { .name = "commtx", .irq = 1 },
> + { .name = "commrx", .irq = 2 },
> + { .name = "bench", .irq = 3 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_mpu_hwmod = {
> + .name = "mpu",
> + .class = &am33xx_mpu_hwmod_class,
> + .clkdm_name = "mpu_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .mpu_irqs = am33xx_mpu_irqs,
> + .main_clk = "dpll_mpu_m2_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'wakeup m3' class
> + * Wakeup controller sub-system under wakeup domain
> + */
> +static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
> + .name = "wkup_m3",
> +};
> +
> +static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
> + { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
> + { .name = "txev", .irq = 78 },
> + { .irq = -1 }
> +};
> +
> +/* wkup_m3 */
> +static struct omap_hwmod am33xx_wkup_m3_hwmod = {
> + .name = "wkup_m3",
> + .class = &am33xx_wkup_m3_hwmod_class,
> + .clkdm_name = "l4_wkup_aon_clkdm",
> + .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
> + .mpu_irqs = am33xx_wkup_m3_irqs,
> + .main_clk = "dpll_core_m4_div2_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
> + .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .rst_lines = am33xx_wkup_m3_resets,
> + .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
> +};
> +
> +/*
> + * 'pru-icss' class
> + * Programmable Real-Time Unit and Industrial Communication Subsystem
> + */
> +static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
> + .name = "pruss",
> +};
> +
> +static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
> + { .name = "pruss", .rst_shift = 1 },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
> + { .name = "evtout0", .irq = 20 },
> + { .name = "evtout1", .irq = 21 },
> + { .name = "evtout2", .irq = 22 },
> + { .name = "evtout3", .irq = 23 },
> + { .name = "evtout4", .irq = 24 },
> + { .name = "evtout5", .irq = 25 },
> + { .name = "evtout6", .irq = 26 },
> + { .name = "evtout7", .irq = 27 },
> + { .irq = -1 }
> +};
> +
> +/* pru-icss */
> +/* Pseudo hwmod for reset control purpose only */
> +static struct omap_hwmod am33xx_pruss_hwmod = {
> + .name = "pruss",
> + .class = &am33xx_pruss_hwmod_class,
> + .clkdm_name = "pruss_ocp_clkdm",
> + .mpu_irqs = am33xx_pruss_irqs,
> + .main_clk = "pruss_ocp_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
> + .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .rst_lines = am33xx_pruss_resets,
> + .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
> +};
> +
> +/* gfx */
> +/* Pseudo hwmod for reset control purpose only */
> +static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
> + .name = "gfx",
> +};
> +
> +static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
> + { .name = "gfx", .rst_shift = 0 },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
> + { .name = "gfxint", .irq = 37 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_gfx_hwmod = {
> + .name = "gfx",
> + .class = &am33xx_gfx_hwmod_class,
> + .clkdm_name = "gfx_l3_clkdm",
> + .mpu_irqs = am33xx_gfx_irqs,
> + .main_clk = "gfx_fck_div_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
> + .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .rst_lines = am33xx_gfx_resets,
> + .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
> +};
> +
> +/*
> + * 'prcm' class
> + * power and reset manager (whole prcm infrastructure)
> + */
> +static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
> + .name = "prcm",
> +};
> +
> +/* prcm */
> +static struct omap_hwmod am33xx_prcm_hwmod = {
> + .name = "prcm",
> + .class = &am33xx_prcm_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> +};
> +
> +/*
> + * 'adc/tsc' class
> + * TouchScreen Controller (Anolog-To-Digital Converter)
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
> + .rev_offs = 0x00,
> + .sysc_offs = 0x10,
> + .sysc_flags = SYSC_HAS_SIDLEMODE,
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
> + .name = "adc_tsc",
> + .sysc = &am33xx_adc_tsc_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
> + { .irq = 16 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_adc_tsc_hwmod = {
> + .name = "adc_tsc",
> + .class = &am33xx_adc_tsc_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = am33xx_adc_tsc_irqs,
> + .main_clk = "adc_tsc_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * Modules omap_hwmod structures
> + *
> + * The following IPs are excluded for the moment because:
> + * - They do not need an explicit SW control using omap_hwmod API.
> + * - They still need to be validated with the driver
> + * properly adapted to omap_hwmod / omap_device
> + *
> + * - cEFUSE (doesn't fall under any ocp_if)
> + * - clkdiv32k
> + * - debugss
> + * - ocmc ram
> + * - ocp watch point
> + * - aes0
> + * - sha0
> + */
> +#if 0
> +/*
> + * 'cefuse' class
> + */
> +static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
> + .name = "cefuse",
> +};
> +
> +static struct omap_hwmod am33xx_cefuse_hwmod = {
> + .name = "cefuse",
> + .class = &am33xx_cefuse_hwmod_class,
> + .clkdm_name = "l4_cefuse_clkdm",
> + .main_clk = "cefuse_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'clkdiv32k' class
> + */
> +static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
> + .name = "clkdiv32k",
> +};
> +
> +static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
> + .name = "clkdiv32k",
> + .class = &am33xx_clkdiv32k_hwmod_class,
> + .clkdm_name = "clk_24mhz_clkdm",
> + .main_clk = "clkdiv32k_ick",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'debugss' class
> + * debug sub system
> + */
> +static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
> + .name = "debugss",
> +};
> +
> +static struct omap_hwmod am33xx_debugss_hwmod = {
> + .name = "debugss",
> + .class = &am33xx_debugss_hwmod_class,
> + .clkdm_name = "l3_aon_clkdm",
> + .main_clk = "debugss_ick",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ocmcram */
> +static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
> + .name = "ocmcram",
> +};
> +
> +static struct omap_hwmod am33xx_ocmcram_hwmod = {
> + .name = "ocmcram",
> + .class = &am33xx_ocmcram_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ocpwp */
> +static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
> + .name = "ocpwp",
> +};
> +
> +static struct omap_hwmod am33xx_ocpwp_hwmod = {
> + .name = "ocpwp",
> + .class = &am33xx_ocpwp_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'aes' class
> + */
> +static struct omap_hwmod_class am33xx_aes_hwmod_class = {
> + .name = "aes",
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
> + { .irq = 102 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_aes0_hwmod = {
> + .name = "aes0",
> + .class = &am33xx_aes_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_aes0_irqs,
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* sha0 */
> +static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
> + .name = "sha0",
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
> + { .irq = 108 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_sha0_hwmod = {
> + .name = "sha0",
> + .class = &am33xx_sha0_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_sha0_irqs,
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +#endif
> +
> +/* 'smartreflex' class */
> +static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
> + .name = "smartreflex",
> +};
> +
> +/* smartreflex0 */
> +static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
> + { .irq = 120 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_smartreflex0_hwmod = {
> + .name = "smartreflex0",
> + .class = &am33xx_smartreflex_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = am33xx_smartreflex0_irqs,
> + .main_clk = "smartreflex0_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* smartreflex1 */
> +static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
> + { .irq = 121 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_smartreflex1_hwmod = {
> + .name = "smartreflex1",
> + .class = &am33xx_smartreflex_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = am33xx_smartreflex1_irqs,
> + .main_clk = "smartreflex1_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'control' module class
> + */
> +static struct omap_hwmod_class am33xx_control_hwmod_class = {
> + .name = "control",
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
> + { .irq = 8 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_control_hwmod = {
> + .name = "control",
> + .class = &am33xx_control_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .mpu_irqs = am33xx_control_irqs,
> + .main_clk = "dpll_core_m4_div2_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'cpgmac' class
> + * cpsw/cpgmac sub system
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x8,
> + .syss_offs = 0x4,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
> + SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
> + MSTANDBY_NO),
> + .sysc_fields = &omap_hwmod_sysc_type3,
> +};
> +
> +static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
> + .name = "cpgmac0",
> + .sysc = &am33xx_cpgmac_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
> + { .name = "c0_rx_thresh_pend", .irq = 40 },
> + { .name = "c0_rx_pend", .irq = 41 },
> + { .name = "c0_tx_pend", .irq = 42 },
> + { .name = "c0_misc_pend", .irq = 43 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_cpgmac0_hwmod = {
> + .name = "cpgmac0",
> + .class = &am33xx_cpgmac0_hwmod_class,
> + .clkdm_name = "cpsw_125mhz_clkdm",
> + .mpu_irqs = am33xx_cpgmac0_irqs,
> + .main_clk = "cpsw_125mhz_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * dcan class
> + */
> +static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
> + .name = "d_can",
> +};
> +
> +/* dcan0 */
> +static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
> + { .name = "d_can_ms", .irq = 52 },
> + { .name = "d_can_mo", .irq = 53 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_dcan0_hwmod = {
> + .name = "d_can0",
> + .class = &am33xx_dcan_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_dcan0_irqs,
> + .main_clk = "dcan0_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* dcan1 */
> +static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
> + { .name = "d_can_ms", .irq = 55 },
> + { .name = "d_can_mo", .irq = 56 },
> + { .irq = -1 }
> +};
> +static struct omap_hwmod am33xx_dcan1_hwmod = {
> + .name = "d_can1",
> + .class = &am33xx_dcan_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_dcan1_irqs,
> + .main_clk = "dcan1_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* elm */
> +static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0010,
> + .syss_offs = 0x0014,
> + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> + SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_elm_hwmod_class = {
> + .name = "elm",
> + .sysc = &am33xx_elm_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
> + { .irq = 4 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_elm_hwmod = {
> + .name = "elm",
> + .class = &am33xx_elm_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_elm_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x4,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
> + MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
> + .name = "epwmss",
> + .sysc = &am33xx_epwmss_sysc,
> +};
> +
> +/* ehrpwm0 */
> +static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
> + { .name = "int", .irq = 86 },
> + { .name = "tzint", .irq = 58 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
> + .name = "ehrpwm0",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_ehrpwm0_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ehrpwm1 */
> +static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
> + { .name = "int", .irq = 87 },
> + { .name = "tzint", .irq = 59 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
> + .name = "ehrpwm1",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_ehrpwm1_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ehrpwm2 */
> +static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
> + { .name = "int", .irq = 39 },
> + { .name = "tzint", .irq = 60 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
> + .name = "ehrpwm2",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_ehrpwm2_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ecap0 */
> +static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
> + { .irq = 31 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ecap0_hwmod = {
> + .name = "ecap0",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_ecap0_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ecap1 */
> +static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
> + { .irq = 47 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ecap1_hwmod = {
> + .name = "ecap1",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_ecap1_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ecap2 */
> +static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
> + { .irq = 61 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ecap2_hwmod = {
> + .name = "ecap2",
> + .mpu_irqs = am33xx_ecap2_irqs,
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'gpio' class: for gpio 0,1,2,3
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0010,
> + .syss_offs = 0x0114,
> + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
> + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
> + SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
> + .name = "gpio",
> + .sysc = &am33xx_gpio_sysc,
> + .rev = 2,
> +};
> +
> +static struct omap_gpio_dev_attr gpio_dev_attr = {
> + .bank_width = 32,
> + .dbck_flag = true,
> +};
> +
> +/* gpio0 */
> +static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
> + { .role = "dbclk", .clk = "gpio0_dbclk" },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
> + { .irq = 96 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_gpio0_hwmod = {
> + .name = "gpio1",
> + .class = &am33xx_gpio_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> + .mpu_irqs = am33xx_gpio0_irqs,
> + .main_clk = "dpll_core_m4_div2_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .opt_clks = gpio0_opt_clks,
> + .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
> + .dev_attr = &gpio_dev_attr,
> +};
> +
> +/* gpio1 */
> +static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
> + { .irq = 98 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
> + { .role = "dbclk", .clk = "gpio1_dbclk" },
> +};
> +
> +static struct omap_hwmod am33xx_gpio1_hwmod = {
> + .name = "gpio2",
> + .class = &am33xx_gpio_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> + .mpu_irqs = am33xx_gpio1_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .opt_clks = gpio1_opt_clks,
> + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
> + .dev_attr = &gpio_dev_attr,
> +};
> +
> +/* gpio2 */
> +static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
> + { .irq = 32 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
> + { .role = "dbclk", .clk = "gpio2_dbclk" },
> +};
> +
> +static struct omap_hwmod am33xx_gpio2_hwmod = {
> + .name = "gpio3",
> + .class = &am33xx_gpio_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> + .mpu_irqs = am33xx_gpio2_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .opt_clks = gpio2_opt_clks,
> + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
> + .dev_attr = &gpio_dev_attr,
> +};
> +
> +/* gpio3 */
> +static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
> + { .irq = 62 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
> + { .role = "dbclk", .clk = "gpio3_dbclk" },
> +};
> +
> +static struct omap_hwmod am33xx_gpio3_hwmod = {
> + .name = "gpio4",
> + .class = &am33xx_gpio_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> + .mpu_irqs = am33xx_gpio3_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .opt_clks = gpio3_opt_clks,
> + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
> + .dev_attr = &gpio_dev_attr,
> +};
> +
> +/* gpmc */
> +static struct omap_hwmod_class_sysconfig gpmc_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x10,
> + .syss_offs = 0x14,
> + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
> + .name = "gpmc",
> + .sysc = &gpmc_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
> + { .irq = 100 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_gpmc_hwmod = {
> + .name = "gpmc",
> + .class = &am33xx_gpmc_hwmod_class,
> + .clkdm_name = "l3s_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .mpu_irqs = am33xx_gpmc_irqs,
> + .main_clk = "l3s_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'i2c' class */
> +static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
> + .sysc_offs = 0x0010,
> + .syss_offs = 0x0090,
> + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
> + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class i2c_class = {
> + .name = "i2c",
> + .sysc = &am33xx_i2c_sysc,
> + .rev = OMAP_I2C_IP_VERSION_2,
> + .reset = &omap_i2c_reset,
> +};
> +
> +static struct omap_i2c_dev_attr i2c_dev_attr = {
> + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
> + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
> +};
> +
> +/* i2c1 */
> +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
> + { .irq = 70 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
> + { .name = "tx", .dma_req = 0, },
> + { .name = "rx", .dma_req = 0, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_i2c1_hwmod = {
> + .name = "i2c1",
> + .class = &i2c_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = i2c1_mpu_irqs,
> + .sdma_reqs = i2c1_edma_reqs,
> + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
> + .main_clk = "dpll_per_m2_div4_wkupdm_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &i2c_dev_attr,
> +};
> +
> +/* i2c1 */
> +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
> + { .irq = 71 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
> + { .name = "tx", .dma_req = 0, },
> + { .name = "rx", .dma_req = 0, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_i2c2_hwmod = {
> + .name = "i2c2",
> + .class = &i2c_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = i2c2_mpu_irqs,
> + .sdma_reqs = i2c2_edma_reqs,
> + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &i2c_dev_attr,
> +};
> +
> +/* i2c3 */
> +static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
> + { .name = "tx", .dma_req = 0, },
> + { .name = "rx", .dma_req = 0, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
> + { .irq = 30 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_i2c3_hwmod = {
> + .name = "i2c3",
> + .class = &i2c_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = i2c3_mpu_irqs,
> + .sdma_reqs = i2c3_edma_reqs,
> + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &i2c_dev_attr,
> +};
> +
> +
> +/* lcdc */
> +static struct omap_hwmod_class_sysconfig lcdc_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x54,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
> + .name = "lcdc",
> + .sysc = &lcdc_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
> + { .irq = 36 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_lcdc_hwmod = {
> + .name = "lcdc",
> + .class = &am33xx_lcdc_hwmod_class,
> + .clkdm_name = "lcdc_clkdm",
> + .mpu_irqs = am33xx_lcdc_irqs,
> + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
> + .main_clk = "lcd_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'mailbox' class
> + * mailbox module allowing communication between the on-chip processors using a
> + * queued mailbox-interrupt mechanism.
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0010,
> + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
> + .name = "mailbox",
> + .sysc = &am33xx_mailbox_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
> + { .irq = 77 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_mailbox_hwmod = {
> + .name = "mailbox",
> + .class = &am33xx_mailbox_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_mailbox_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'mcasp' class
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x4,
> + .sysc_flags = SYSC_HAS_SIDLEMODE,
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type3,
> +};
> +
> +static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
> + .name = "mcasp",
> + .sysc = &am33xx_mcasp_sysc,
> +};
> +
> +/* mcasp0 */
> +static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
> + { .name = "ax", .irq = 80, },
> + { .name = "ar", .irq = 81, },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
> + { .name = "tx", .dma_req = 8, },
> + { .name = "rx", .dma_req = 9, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_mcasp0_hwmod = {
> + .name = "mcasp0",
> + .class = &am33xx_mcasp_hwmod_class,
> + .clkdm_name = "l3s_clkdm",
> + .mpu_irqs = am33xx_mcasp0_irqs,
> + .sdma_reqs = am33xx_mcasp0_edma_reqs,
> + .main_clk = "mcasp0_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* mcasp1 */
> +static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
> + { .name = "ax", .irq = 82, },
> + { .name = "ar", .irq = 83, },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
> + { .name = "tx", .dma_req = 10, },
> + { .name = "rx", .dma_req = 11, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_mcasp1_hwmod = {
> + .name = "mcasp1",
> + .class = &am33xx_mcasp_hwmod_class,
> + .clkdm_name = "l3s_clkdm",
> + .mpu_irqs = am33xx_mcasp1_irqs,
> + .sdma_reqs = am33xx_mcasp1_edma_reqs,
> + .main_clk = "mcasp1_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'mmc' class */
> +static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
> + .rev_offs = 0x1fc,
> + .sysc_offs = 0x10,
> + .syss_offs = 0x14,
> + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
> + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
> + .name = "mmc",
> + .sysc = &am33xx_mmc_sysc,
> +};
> +
> +/* mmc0 */
> +static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
> + { .irq = 64 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
> + { .name = "tx", .dma_req = 24, },
> + { .name = "rx", .dma_req = 25, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
> + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
> +};
> +
> +static struct omap_hwmod am33xx_mmc0_hwmod = {
> + .name = "mmc1",
> + .class = &am33xx_mmc_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_mmc0_irqs,
> + .sdma_reqs = am33xx_mmc0_edma_reqs,
> + .main_clk = "mmc_clk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &am33xx_mmc0_dev_attr,
> +};
> +
> +/* mmc1 */
> +static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
> + { .irq = 28 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
> + { .name = "tx", .dma_req = 2, },
> + { .name = "rx", .dma_req = 3, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
> + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
> +};
> +
> +static struct omap_hwmod am33xx_mmc1_hwmod = {
> + .name = "mmc2",
> + .class = &am33xx_mmc_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_mmc1_irqs,
> + .sdma_reqs = am33xx_mmc1_edma_reqs,
> + .main_clk = "mmc_clk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &am33xx_mmc1_dev_attr,
> +};
> +
> +/* mmc2 */
> +static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
> + { .irq = 29 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
> + { .name = "tx", .dma_req = 64, },
> + { .name = "rx", .dma_req = 65, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
> + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
> +};
> +static struct omap_hwmod am33xx_mmc2_hwmod = {
> + .name = "mmc3",
> + .class = &am33xx_mmc_hwmod_class,
> + .clkdm_name = "l3s_clkdm",
> + .mpu_irqs = am33xx_mmc2_irqs,
> + .sdma_reqs = am33xx_mmc2_edma_reqs,
> + .main_clk = "mmc2_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &am33xx_mmc2_dev_attr,
> +};
> +
> +/*
> + * 'rtc' class
> + * rtc subsystem
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
> + .rev_offs = 0x0074,
> + .sysc_offs = 0x0078,
> + .sysc_flags = SYSC_HAS_SIDLEMODE,
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO |
> + SIDLE_SMART | SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type3,
> +};
> +
> +static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
> + .name = "rtc",
> + .sysc = &am33xx_rtc_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
> + { .name = "rtcint", .irq = 75 },
> + { .name = "rtcalarmint", .irq = 76 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_rtc_hwmod = {
> + .name = "rtc",
> + .class = &am33xx_rtc_hwmod_class,
> + .clkdm_name = "l4_rtc_clkdm",
> + .mpu_irqs = am33xx_rtc_irqs,
> + .main_clk = "clk_32768_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'spi' class */
> +static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0110,
> + .syss_offs = 0x0114,
> + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> + SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_spi_hwmod_class = {
> + .name = "mcspi",
> + .sysc = &am33xx_mcspi_sysc,
> + .rev = OMAP4_MCSPI_REV,
> +};
> +
> +/* spi0 */
> +static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
> + { .irq = 65 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
> + { .name = "rx0", .dma_req = 17 },
> + { .name = "tx0", .dma_req = 16 },
> + { .name = "rx1", .dma_req = 19 },
> + { .name = "tx1", .dma_req = 18 },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap2_mcspi_dev_attr mcspi_attrib = {
> + .num_chipselect = 2,
> +};
> +static struct omap_hwmod am33xx_spi0_hwmod = {
> + .name = "spi0",
> + .class = &am33xx_spi_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_spi0_irqs,
> + .sdma_reqs = am33xx_mcspi0_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &mcspi_attrib,
> +};
> +
> +/* spi1 */
> +static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
> + { .irq = 125 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
> + { .name = "rx0", .dma_req = 43 },
> + { .name = "tx0", .dma_req = 42 },
> + { .name = "rx1", .dma_req = 45 },
> + { .name = "tx1", .dma_req = 44 },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_spi1_hwmod = {
> + .name = "spi1",
> + .class = &am33xx_spi_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_spi1_irqs,
> + .sdma_reqs = am33xx_mcspi1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &mcspi_attrib,
> +};
> +
> +/*
> + * 'spinlock' class
> + * spinlock provides hardware assistance for synchronizing the
> + * processes running on multiple processors
> + */
> +static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
> + .name = "spinlock",
> +};
> +
> +static struct omap_hwmod am33xx_spinlock_hwmod = {
> + .name = "spinlock",
> + .class = &am33xx_spinlock_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'timer 2-7' class */
> +static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0010,
> + .syss_offs = 0x0014,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_timer_hwmod_class = {
> + .name = "timer",
> + .sysc = &am33xx_timer_sysc,
> +};
> +
> +/* timer1 1ms */
> +static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0010,
> + .syss_offs = 0x0014,
> + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> + SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
> + .name = "timer",
> + .sysc = &am33xx_timer1ms_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
> + { .irq = 67 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer1_hwmod = {
> + .name = "timer1",
> + .class = &am33xx_timer1ms_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = am33xx_timer1_irqs,
> + .main_clk = "timer1_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
> + { .irq = 68 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer2_hwmod = {
> + .name = "timer2",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer2_irqs,
> + .main_clk = "timer2_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
> + { .irq = 69 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer3_hwmod = {
> + .name = "timer3",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer3_irqs,
> + .main_clk = "timer3_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
> + { .irq = 92 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer4_hwmod = {
> + .name = "timer4",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer4_irqs,
> + .main_clk = "timer4_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
> + { .irq = 93 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer5_hwmod = {
> + .name = "timer5",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer5_irqs,
> + .main_clk = "timer5_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
> + { .irq = 94 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer6_hwmod = {
> + .name = "timer6",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer6_irqs,
> + .main_clk = "timer6_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
> + { .irq = 95 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer7_hwmod = {
> + .name = "timer7",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer7_irqs,
> + .main_clk = "timer7_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* tpcc */
> +static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
> + .name = "tpcc",
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
> + { .name = "edma0", .irq = 12 },
> + { .name = "edma0_mperr", .irq = 13, },
> + { .name = "edma0_err", .irq = 14 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_tpcc_hwmod = {
> + .name = "tpcc",
> + .class = &am33xx_tpcc_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_tpcc_irqs,
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x10,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
> + SYSC_HAS_MIDLEMODE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +/* 'tptc' class */
> +static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
> + .name = "tptc",
> + .sysc = &am33xx_tptc_sysc,
> +};
> +
> +/* tptc0 */
> +static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
> + { .irq = 112 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_tptc0_hwmod = {
> + .name = "tptc0",
> + .class = &am33xx_tptc_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_tptc0_irqs,
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* tptc1 */
> +static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
> + { .irq = 113 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_tptc1_hwmod = {
> + .name = "tptc1",
> + .class = &am33xx_tptc_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_tptc1_irqs,
> + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* tptc2 */
> +static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
> + { .irq = 114 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_tptc2_hwmod = {
> + .name = "tptc2",
> + .class = &am33xx_tptc_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_tptc2_irqs,
> + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'uart' class */
> +static struct omap_hwmod_class_sysconfig uart_sysc = {
> + .rev_offs = 0x50,
> + .sysc_offs = 0x54,
> + .syss_offs = 0x58,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
> + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class uart_class = {
> + .name = "uart",
> + .sysc = &uart_sysc,
> +};
> +
> +/* uart1 */
> +static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
> + { .name = "tx", .dma_req = 26, },
> + { .name = "rx", .dma_req = 27, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
> + { .irq = 72 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart1_hwmod = {
> + .name = "uart1",
> + .class = &uart_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = am33xx_uart1_irqs,
> + .sdma_reqs = uart1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_wkupdm_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
> + { .irq = 73 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart2_hwmod = {
> + .name = "uart2",
> + .class = &uart_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_uart2_irqs,
> + .sdma_reqs = uart1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* uart3 */
> +static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
> + { .name = "tx", .dma_req = 30, },
> + { .name = "rx", .dma_req = 31, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
> + { .irq = 74 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart3_hwmod = {
> + .name = "uart3",
> + .class = &uart_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_uart3_irqs,
> + .sdma_reqs = uart3_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
> + { .irq = 44 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart4_hwmod = {
> + .name = "uart4",
> + .class = &uart_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_uart4_irqs,
> + .sdma_reqs = uart1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
> + { .irq = 45 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart5_hwmod = {
> + .name = "uart5",
> + .class = &uart_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_uart5_irqs,
> + .sdma_reqs = uart1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
> + { .irq = 46 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart6_hwmod = {
> + .name = "uart6",
> + .class = &uart_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_uart6_irqs,
> + .sdma_reqs = uart1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'wd_timer' class */
> +static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
> + .name = "wd_timer",
> +};
> +
> +/*
> + * XXX: device.c file uses hardcoded name for watchdog timer
> + * driver "wd_timer2, so we are also using same name as of now...
> + */
> +static struct omap_hwmod am33xx_wd_timer1_hwmod = {
> + .name = "wd_timer2",
> + .class = &am33xx_wd_timer_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .main_clk = "wdt1_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'usb_otg' class
> + * high-speed on-the-go universal serial bus (usb_otg) controller
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x10,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_usbotg_class = {
> + .name = "usbotg",
> + .sysc = &am33xx_usbhsotg_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
> + { .name = "usbss-irq", .irq = 17, },
> + { .name = "musb0-irq", .irq = 18, },
> + { .name = "musb1-irq", .irq = 19, },
> + { .irq = -1, },
> +};
> +
> +static struct omap_hwmod am33xx_usbss_hwmod = {
> + .name = "usb_otg_hs",
> + .class = &am33xx_usbotg_class,
> + .clkdm_name = "l3s_clkdm",
> + .mpu_irqs = am33xx_usbss_mpu_irqs,
> + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
> + .main_clk = "usbotg_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +
> +/*
> + * Interfaces
> + */
> +
> +/* l4 fw -> emif fw */
> +static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
> + .master = &am33xx_l4_fw_hwmod,
> + .slave = &am33xx_emif_fw_hwmod,
> + .clk = "l4fw_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
> + {
> + .pa_start = 0x4c000000,
> + .pa_end = 0x4c000fff,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +/* l3 main -> emif */
> +static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_emif_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .addr = am33xx_emif_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* mpu -> l3 main */
> +static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
> + .master = &am33xx_mpu_hwmod,
> + .slave = &am33xx_l3_main_hwmod,
> + .clk = "dpll_mpu_m2_ck",
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 main -> l4 hs */
> +static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_l4_hs_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 main -> l3 s */
> +static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_l3_s_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 s -> l4 per/ls */
> +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_l4_ls_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 s -> l4 wkup */
> +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_l4_wkup_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 s -> l4 fw */
> +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_l4_fw_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 main -> l3 instr */
> +static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_l3_instr_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* mpu -> prcm */
> +static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
> + .master = &am33xx_mpu_hwmod,
> + .slave = &am33xx_prcm_hwmod,
> + .clk = "dpll_mpu_m2_ck",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 s -> l3 main*/
> +static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_l3_main_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* pru-icss -> l3 main */
> +static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
> + .master = &am33xx_pruss_hwmod,
> + .slave = &am33xx_l3_main_hwmod,
> + .clk = "l3_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* wkup m3 -> l4 wkup */
> +static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
> + .master = &am33xx_wkup_m3_hwmod,
> + .slave = &am33xx_l4_wkup_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* gfx -> l3 main */
> +static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
> + .master = &am33xx_gfx_hwmod,
> + .slave = &am33xx_l3_main_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 wkup -> wkup m3 */
> +static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
> + {
> + .name = "umem",
> + .pa_start = 0x44d00000,
> + .pa_end = 0x44d00000 + SZ_16K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .name = "dmem",
> + .pa_start = 0x44d80000,
> + .pa_end = 0x44d80000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_wkup_m3_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_wkup_m3_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 hs -> pru-icss */
> +static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
> + {
> + .pa_start = 0x4a300000,
> + .pa_end = 0x4a300000 + SZ_512K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
> + .master = &am33xx_l4_hs_hwmod,
> + .slave = &am33xx_pruss_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .addr = am33xx_pruss_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 main -> gfx */
> +static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
> + {
> + .pa_start = 0x56000000,
> + .pa_end = 0x56000000 + SZ_16M - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_gfx_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .addr = am33xx_gfx_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 wkup -> smartreflex0 */
> +static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
> + {
> + .pa_start = 0x44e37000,
> + .pa_end = 0x44e37000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_smartreflex0_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_smartreflex0_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> smartreflex1 */
> +static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
> + {
> + .pa_start = 0x44e39000,
> + .pa_end = 0x44e39000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_smartreflex1_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_smartreflex1_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> control */
> +static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
> + {
> + .pa_start = 0x44e10000,
> + .pa_end = 0x44e10000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_control_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_control_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> rtc */
> +static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
> + {
> + .pa_start = 0x44e3e000,
> + .pa_end = 0x44e3e000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_rtc_hwmod,
> + .clk = "clkdiv32k_ick",
> + .addr = am33xx_rtc_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per/ls -> DCAN0 */
> +static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
> + {
> + .pa_start = 0x481CC000,
> + .pa_end = 0x481CC000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_dcan0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_dcan0_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 per/ls -> DCAN1 */
> +static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
> + {
> + .pa_start = 0x481D0000,
> + .pa_end = 0x481D0000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_dcan1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_dcan1_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 per/ls -> GPIO2 */
> +static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
> + {
> + .pa_start = 0x4804C000,
> + .pa_end = 0x4804C000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_gpio1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_gpio1_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 per/ls -> gpio3 */
> +static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
> + {
> + .pa_start = 0x481AC000,
> + .pa_end = 0x481AC000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_gpio2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_gpio2_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 per/ls -> gpio4 */
> +static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
> + {
> + .pa_start = 0x481AE000,
> + .pa_end = 0x481AE000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_gpio3_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_gpio3_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* L4 WKUP -> I2C1 */
> +static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
> + {
> + .pa_start = 0x44E0B000,
> + .pa_end = 0x44E0B000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_i2c1_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_i2c1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* L4 WKUP -> GPIO1 */
> +static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
> + {
> + .pa_start = 0x44E07000,
> + .pa_end = 0x44E07000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_gpio0_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_gpio0_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* L4 WKUP -> ADC_TSC */
> +static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
> + {
> + .pa_start = 0x44E0D000,
> + .pa_end = 0x44E0D000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_adc_tsc_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_adc_tsc_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
> + /* cpsw ss */
> + {
> + .pa_start = 0x4a100000,
> + .pa_end = 0x4a100000 + SZ_2K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + /* cpsw wr */
> + {
> + .pa_start = 0x4a101200,
> + .pa_end = 0x4a101200 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
> + .master = &am33xx_l4_hs_hwmod,
> + .slave = &am33xx_cpgmac0_hwmod,
> + .clk = "cpsw_125mhz_gclk",
> + .addr = am33xx_cpgmac0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
> + {
> + .pa_start = 0x48080000,
> + .pa_end = 0x48080000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_elm_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_elm_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
> + {
> + .pa_start = 0x48300000,
> + .pa_end = 0x48300000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48300200,
> + .pa_end = 0x48300200 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ehrpwm0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ehrpwm0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
> + {
> + .pa_start = 0x48302000,
> + .pa_end = 0x48302000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48302200,
> + .pa_end = 0x48302200 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ehrpwm1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ehrpwm1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
> + {
> + .pa_start = 0x48304000,
> + .pa_end = 0x48304000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48304200,
> + .pa_end = 0x48304200 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ehrpwm2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ehrpwm2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
> + {
> + .pa_start = 0x48300000,
> + .pa_end = 0x48300000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48300100,
> + .pa_end = 0x48300100 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ecap0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ecap0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
> + {
> + .pa_start = 0x48302000,
> + .pa_end = 0x48302000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48302100,
> + .pa_end = 0x48302100 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ecap1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ecap1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
> + {
> + .pa_start = 0x48304000,
> + .pa_end = 0x48304000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48304100,
> + .pa_end = 0x48304100 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ecap2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ecap2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3s cfg -> gpmc */
> +static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
> + {
> + .pa_start = 0x50000000,
> + .pa_end = 0x50000000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_gpmc_hwmod,
> + .clk = "l3s_gclk",
> + .addr = am33xx_gpmc_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* i2c2 */
> +static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
> + {
> + .pa_start = 0x4802A000,
> + .pa_end = 0x4802A000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_i2c2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_i2c2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
> + {
> + .pa_start = 0x4819C000,
> + .pa_end = 0x4819C000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_i2c3_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_i2c3_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
> + {
> + .pa_start = 0x4830E000,
> + .pa_end = 0x4830E000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_lcdc_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .addr = am33xx_lcdc_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
> + {
> + .pa_start = 0x480C8000,
> + .pa_end = 0x480C8000 + (SZ_4K - 1),
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +/* l4 ls -> mailbox */
> +static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_mailbox_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mailbox_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> spinlock */
> +static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
> + {
> + .pa_start = 0x480Ca000,
> + .pa_end = 0x480Ca000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_spinlock_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_spinlock_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> mcasp0 */
> +static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
> + {
> + .pa_start = 0x48038000,
> + .pa_end = 0x48038000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_mcasp0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mcasp0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 s -> mcasp0 data */
> +static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
> + {
> + .pa_start = 0x46000000,
> + .pa_end = 0x46000000 + SZ_4M - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_mcasp0_hwmod,
> + .clk = "l3s_gclk",
> + .addr = am33xx_mcasp0_data_addr_space,
> + .user = OCP_USER_SDMA,
> +};
> +
> +/* l4 ls -> mcasp1 */
> +static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
> + {
> + .pa_start = 0x4803C000,
> + .pa_end = 0x4803C000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_mcasp1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mcasp1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 s -> mcasp1 data */
> +static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
> + {
> + .pa_start = 0x46400000,
> + .pa_end = 0x46400000 + SZ_4M - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_mcasp1_hwmod,
> + .clk = "l3s_gclk",
> + .addr = am33xx_mcasp1_data_addr_space,
> + .user = OCP_USER_SDMA,
> +};
> +
> +/* l4 ls -> mmc0 */
> +static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
> + {
> + .pa_start = 0x48060100,
> + .pa_end = 0x48060100 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_mmc0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mmc0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> mmc1 */
> +static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
> + {
> + .pa_start = 0x481d8100,
> + .pa_end = 0x481d8100 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_mmc1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mmc1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 s -> mmc2 */
> +static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
> + {
> + .pa_start = 0x47810100,
> + .pa_end = 0x47810100 + SZ_64K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_mmc2_hwmod,
> + .clk = "l3s_gclk",
> + .addr = am33xx_mmc2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> mcspi0 */
> +static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
> + {
> + .pa_start = 0x48030000,
> + .pa_end = 0x48030000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_spi0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mcspi0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> mcspi1 */
> +static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
> + {
> + .pa_start = 0x481A0000,
> + .pa_end = 0x481A0000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_spi1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mcspi1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> timer1 */
> +static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
> + {
> + .pa_start = 0x44E31000,
> + .pa_end = 0x44E31000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_timer1_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_timer1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer2 */
> +static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
> + {
> + .pa_start = 0x48040000,
> + .pa_end = 0x48040000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer3 */
> +static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
> + {
> + .pa_start = 0x48042000,
> + .pa_end = 0x48042000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer3_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer3_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer4 */
> +static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
> + {
> + .pa_start = 0x48044000,
> + .pa_end = 0x48044000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer4_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer4_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer5 */
> +static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
> + {
> + .pa_start = 0x48046000,
> + .pa_end = 0x48046000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer5_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer5_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer6 */
> +static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
> + {
> + .pa_start = 0x48048000,
> + .pa_end = 0x48048000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer6_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer6_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer7 */
> +static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
> + {
> + .pa_start = 0x4804A000,
> + .pa_end = 0x4804A000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer7_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer7_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 main -> tpcc */
> +static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
> + {
> + .pa_start = 0x49000000,
> + .pa_end = 0x49000000 + SZ_32K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_tpcc_hwmod,
> + .clk = "l3_gclk",
> + .addr = am33xx_tpcc_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 main -> tpcc0 */
> +static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
> + {
> + .pa_start = 0x49800000,
> + .pa_end = 0x49800000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_tptc0_hwmod,
> + .clk = "l3_gclk",
> + .addr = am33xx_tptc0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 main -> tpcc1 */
> +static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
> + {
> + .pa_start = 0x49900000,
> + .pa_end = 0x49900000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_tptc1_hwmod,
> + .clk = "l3_gclk",
> + .addr = am33xx_tptc1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 main -> tpcc2 */
> +static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
> + {
> + .pa_start = 0x49a00000,
> + .pa_end = 0x49a00000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_tptc2_hwmod,
> + .clk = "l3_gclk",
> + .addr = am33xx_tptc2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> uart1 */
> +static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
> + {
> + .pa_start = 0x44E09000,
> + .pa_end = 0x44E09000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_uart1_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_uart1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> uart2 */
> +static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
> + {
> + .pa_start = 0x48022000,
> + .pa_end = 0x48022000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_uart2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_uart2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> uart3 */
> +static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
> + {
> + .pa_start = 0x48024000,
> + .pa_end = 0x48024000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_uart3_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_uart3_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> uart4 */
> +static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
> + {
> + .pa_start = 0x481A6000,
> + .pa_end = 0x481A6000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_uart4_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_uart4_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> uart5 */
> +static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
> + {
> + .pa_start = 0x481A8000,
> + .pa_end = 0x481A8000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_uart5_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_uart5_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> uart6 */
> +static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
> + {
> + .pa_start = 0x481aa000,
> + .pa_end = 0x481aa000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_uart6_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_uart6_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> wd_timer1 */
> +static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
> + {
> + .pa_start = 0x44e35000,
> + .pa_end = 0x44e35000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_wd_timer1_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_wd_timer1_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* usbss */
> +/* l3 s -> USBSS interface */
> +static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
> + {
> + .name = "usbss",
> + .pa_start = 0x47400000,
> + .pa_end = 0x47400000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .name = "musb0",
> + .pa_start = 0x47401000,
> + .pa_end = 0x47401000 + SZ_2K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .name = "musb1",
> + .pa_start = 0x47401800,
> + .pa_end = 0x47401800 + SZ_2K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_usbss_hwmod,
> + .clk = "l3s_gclk",
> + .addr = am33xx_usbss_addr_space,
> + .user = OCP_USER_MPU,
> + .flags = OCPIF_SWSUP_IDLE,
> +};
> +
> +static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
> + &am33xx_l4_fw__emif_fw,
> + &am33xx_l3_main__emif,
> + &am33xx_mpu__l3_main,
> + &am33xx_mpu__prcm,
> + &am33xx_l3_s__l4_ls,
> + &am33xx_l3_s__l4_wkup,
> + &am33xx_l3_s__l4_fw,
> + &am33xx_l3_main__l4_hs,
> + &am33xx_l3_main__l3_s,
> + &am33xx_l3_main__l3_instr,
> + &am33xx_l3_main__gfx,
> + &am33xx_l3_s__l3_main,
> + &am33xx_pruss__l3_main,
> + &am33xx_wkup_m3__l4_wkup,
> + &am33xx_gfx__l3_main,
> + &am33xx_l4_wkup__wkup_m3,
> + &am33xx_l4_wkup__control,
> + &am33xx_l4_wkup__smartreflex0,
> + &am33xx_l4_wkup__smartreflex1,
> + &am33xx_l4_wkup__uart1,
> + &am33xx_l4_wkup__timer1,
> + &am33xx_l4_wkup__rtc,
> + &am33xx_l4_wkup__i2c1,
> + &am33xx_l4_wkup__gpio0,
> + &am33xx_l4_wkup__adc_tsc,
> + &am33xx_l4_wkup__wd_timer1,
> + &am33xx_l4_hs__pruss,
> + &am33xx_l4_per__dcan0,
> + &am33xx_l4_per__dcan1,
> + &am33xx_l4_per__gpio1,
> + &am33xx_l4_per__gpio2,
> + &am33xx_l4_per__gpio3,
> + &am33xx_l4_per__i2c2,
> + &am33xx_l4_per__i2c3,
> + &am33xx_l4_per__mailbox,
> + &am33xx_l4_ls__mcasp0,
> + &am33xx_l3_s__mcasp0_data,
> + &am33xx_l4_ls__mcasp1,
> + &am33xx_l3_s__mcasp1_data,
> + &am33xx_l4_ls__mmc0,
> + &am33xx_l4_ls__mmc1,
> + &am33xx_l3_s__mmc2,
> + &am33xx_l4_ls__timer2,
> + &am33xx_l4_ls__timer3,
> + &am33xx_l4_ls__timer4,
> + &am33xx_l4_ls__timer5,
> + &am33xx_l4_ls__timer6,
> + &am33xx_l4_ls__timer7,
> + &am33xx_l3_main__tpcc,
> + &am33xx_l4_ls__uart2,
> + &am33xx_l4_ls__uart3,
> + &am33xx_l4_ls__uart4,
> + &am33xx_l4_ls__uart5,
> + &am33xx_l4_ls__uart6,
> + &am33xx_l4_ls__spinlock,
> + &am33xx_l4_ls__elm,
> + &am33xx_l4_ls__ehrpwm0,
> + &am33xx_l4_ls__ehrpwm1,
> + &am33xx_l4_ls__ehrpwm2,
> + &am33xx_l4_ls__ecap0,
> + &am33xx_l4_ls__ecap1,
> + &am33xx_l4_ls__ecap2,
> + &am33xx_l3_s__gpmc,
> + &am33xx_l3_main__lcdc,
> + &am33xx_l4_ls__mcspi0,
> + &am33xx_l4_ls__mcspi1,
> + &am33xx_l3_main__tptc0,
> + &am33xx_l3_main__tptc1,
> + &am33xx_l3_main__tptc2,
> + &am33xx_l3_s__usbss,
> + &am33xx_l4_hs__cpgmac0,
> + NULL,
> +};
> +
> +int __init am33xx_hwmod_init(void)
> +{
> + omap_hwmod_init();
> + return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
> +}
> diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
> index 6132972..9b9646c 100644
> --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
> +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
> @@ -658,6 +658,7 @@ extern int omap2420_hwmod_init(void);
> extern int omap2430_hwmod_init(void);
> extern int omap3xxx_hwmod_init(void);
> extern int omap44xx_hwmod_init(void);
> +extern int am33xx_hwmod_init(void);
>
> extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
>
> --
> 1.7.10.4
>
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-07-27 8:36 ` Hiremath, Vaibhav
0 siblings, 0 replies; 28+ messages in thread
From: Hiremath, Vaibhav @ 2012-07-27 8:36 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 27, 2012 at 01:32:33, Paul Walmsley wrote:
> On Wed, 25 Jul 2012, Paul Walmsley wrote:
>
> > These IP blocks and the ECAP IP blocks have periods in their names.
> > The rest of the IP block named in the file don't use periods -- which
> > is also the style used by the rest of the OMAP SoCs. Is there
> > some reason that these have periods in their names?
>
> I've changed those to match the rest of the names, and queued the
> following for 3.7.
>
> Thanks again for all the hard work you all put into this. I realize that
> with all the upstream changes, this was probably a little painful for you.
> But from my perspective you've been a pleasure to work with through the
> process.
>
Thanks Paul for the appreciation, yes, it was pleasure to work with through
the process. And it would not have been possible without your support and
patience.
Still very long way ahead of me...now I can concentrate on other TODO
list which are dependent on basic baseport stuff and
cleanup/feature-addition to existing OMAP code.
Thanks,
Vaibhav
>
> - Paul
>
>
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> Date: Wed, 25 Jul 2012 13:51:13 -0600
> Subject: [PATCH] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
>
> This patch adds HWMOD data for all the peripherals of
> AM335X device and also hooks up to the existing OMAP framework.
>
> hwmod data has been already been cleaned up for the recent
> changes in clocktree, where all leaf nodes have been removed,
> since with modulemode based control, both clock and hwmod
> interface does same thing. This reduces the code size to large
> extent and also avoids duplication of same control.
> So instead of specifying module's leaf node as a main_clk,
> now we are relying on parent clock of module's functional clock.
>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> Cc: Paul Walmsley <paul@pwsan.com>
> Cc: Benoit Cousson <b-cousson@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Kevin Hilman <khilman@ti.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> ---
> arch/arm/mach-omap2/Makefile | 1 +
> arch/arm/mach-omap2/io.c | 2 +
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3381 ++++++++++++++++++++++++++
> arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
> 4 files changed, 3385 insertions(+)
> create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index f6a24b3..b360328 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -194,6 +194,7 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
> obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
> obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
> obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
> +obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
>
> # EMU peripherals
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index 4d2d981..408b3f0 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -523,6 +523,8 @@ void __init am33xx_init_early(void)
> am33xx_voltagedomains_init();
> am33xx_powerdomains_init();
> am33xx_clockdomains_init();
> + am33xx_hwmod_init();
> + omap_hwmod_init_postsetup();
> am33xx_clk_init();
> }
> #endif
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> new file mode 100644
> index 0000000..16d8543
> --- /dev/null
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -0,0 +1,3381 @@
> +/*
> + * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
> + *
> + * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This file is automatically generated from the AM33XX hardware databases.
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <plat/omap_hwmod.h>
> +#include <plat/cpu.h>
> +#include <plat/gpio.h>
> +#include <plat/dma.h>
> +#include <plat/mmc.h>
> +#include <plat/mcspi.h>
> +#include <plat/i2c.h>
> +
> +#include "omap_hwmod_common_data.h"
> +
> +#include "control.h"
> +#include "cm33xx.h"
> +#include "prm33xx.h"
> +#include "prm-regbits-33xx.h"
> +
> +/*
> + * IP blocks
> + */
> +
> +/*
> + * 'emif_fw' class
> + * instance(s): emif_fw
> + */
> +static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
> + .name = "emif_fw",
> +};
> +
> +/* emif_fw */
> +static struct omap_hwmod am33xx_emif_fw_hwmod = {
> + .name = "emif_fw",
> + .class = &am33xx_emif_fw_hwmod_class,
> + .clkdm_name = "l4fw_clkdm",
> + .main_clk = "l4fw_gclk",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'emif' class
> + * instance(s): emif
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
> + .rev_offs = 0x0000,
> +};
> +
> +static struct omap_hwmod_class am33xx_emif_hwmod_class = {
> + .name = "emif",
> + .sysc = &am33xx_emif_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
> + { .name = "ddrerr0", .irq = 101 },
> + { .irq = -1 }
> +};
> +
> +/* emif */
> +static struct omap_hwmod am33xx_emif_hwmod = {
> + .name = "emif",
> + .class = &am33xx_emif_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .mpu_irqs = am33xx_emif_irqs,
> + .main_clk = "dpll_ddr_m2_div2_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'l3' class
> + * instance(s): l3_main, l3_s, l3_instr
> + */
> +static struct omap_hwmod_class am33xx_l3_hwmod_class = {
> + .name = "l3",
> +};
> +
> +/* l3_main (l3_fast) */
> +static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
> + { .name = "l3debug", .irq = 9 },
> + { .name = "l3appint", .irq = 10 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_l3_main_hwmod = {
> + .name = "l3_main",
> + .class = &am33xx_l3_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .mpu_irqs = am33xx_l3_main_irqs,
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* l3_s */
> +static struct omap_hwmod am33xx_l3_s_hwmod = {
> + .name = "l3_s",
> + .class = &am33xx_l3_hwmod_class,
> + .clkdm_name = "l3s_clkdm",
> +};
> +
> +/* l3_instr */
> +static struct omap_hwmod am33xx_l3_instr_hwmod = {
> + .name = "l3_instr",
> + .class = &am33xx_l3_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'l4' class
> + * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
> + */
> +static struct omap_hwmod_class am33xx_l4_hwmod_class = {
> + .name = "l4",
> +};
> +
> +/* l4_ls */
> +static struct omap_hwmod am33xx_l4_ls_hwmod = {
> + .name = "l4_ls",
> + .class = &am33xx_l4_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* l4_hs */
> +static struct omap_hwmod am33xx_l4_hs_hwmod = {
> + .name = "l4_hs",
> + .class = &am33xx_l4_hwmod_class,
> + .clkdm_name = "l4hs_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .main_clk = "l4hs_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +
> +/* l4_wkup */
> +static struct omap_hwmod am33xx_l4_wkup_hwmod = {
> + .name = "l4_wkup",
> + .class = &am33xx_l4_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* l4_fw */
> +static struct omap_hwmod am33xx_l4_fw_hwmod = {
> + .name = "l4_fw",
> + .class = &am33xx_l4_hwmod_class,
> + .clkdm_name = "l4fw_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'mpu' class
> + */
> +static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
> + .name = "mpu",
> +};
> +
> +/* mpu */
> +static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
> + { .name = "emuint", .irq = 0 },
> + { .name = "commtx", .irq = 1 },
> + { .name = "commrx", .irq = 2 },
> + { .name = "bench", .irq = 3 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_mpu_hwmod = {
> + .name = "mpu",
> + .class = &am33xx_mpu_hwmod_class,
> + .clkdm_name = "mpu_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .mpu_irqs = am33xx_mpu_irqs,
> + .main_clk = "dpll_mpu_m2_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'wakeup m3' class
> + * Wakeup controller sub-system under wakeup domain
> + */
> +static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
> + .name = "wkup_m3",
> +};
> +
> +static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
> + { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
> + { .name = "txev", .irq = 78 },
> + { .irq = -1 }
> +};
> +
> +/* wkup_m3 */
> +static struct omap_hwmod am33xx_wkup_m3_hwmod = {
> + .name = "wkup_m3",
> + .class = &am33xx_wkup_m3_hwmod_class,
> + .clkdm_name = "l4_wkup_aon_clkdm",
> + .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
> + .mpu_irqs = am33xx_wkup_m3_irqs,
> + .main_clk = "dpll_core_m4_div2_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
> + .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .rst_lines = am33xx_wkup_m3_resets,
> + .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
> +};
> +
> +/*
> + * 'pru-icss' class
> + * Programmable Real-Time Unit and Industrial Communication Subsystem
> + */
> +static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
> + .name = "pruss",
> +};
> +
> +static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
> + { .name = "pruss", .rst_shift = 1 },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
> + { .name = "evtout0", .irq = 20 },
> + { .name = "evtout1", .irq = 21 },
> + { .name = "evtout2", .irq = 22 },
> + { .name = "evtout3", .irq = 23 },
> + { .name = "evtout4", .irq = 24 },
> + { .name = "evtout5", .irq = 25 },
> + { .name = "evtout6", .irq = 26 },
> + { .name = "evtout7", .irq = 27 },
> + { .irq = -1 }
> +};
> +
> +/* pru-icss */
> +/* Pseudo hwmod for reset control purpose only */
> +static struct omap_hwmod am33xx_pruss_hwmod = {
> + .name = "pruss",
> + .class = &am33xx_pruss_hwmod_class,
> + .clkdm_name = "pruss_ocp_clkdm",
> + .mpu_irqs = am33xx_pruss_irqs,
> + .main_clk = "pruss_ocp_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
> + .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .rst_lines = am33xx_pruss_resets,
> + .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
> +};
> +
> +/* gfx */
> +/* Pseudo hwmod for reset control purpose only */
> +static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
> + .name = "gfx",
> +};
> +
> +static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
> + { .name = "gfx", .rst_shift = 0 },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
> + { .name = "gfxint", .irq = 37 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_gfx_hwmod = {
> + .name = "gfx",
> + .class = &am33xx_gfx_hwmod_class,
> + .clkdm_name = "gfx_l3_clkdm",
> + .mpu_irqs = am33xx_gfx_irqs,
> + .main_clk = "gfx_fck_div_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
> + .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .rst_lines = am33xx_gfx_resets,
> + .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
> +};
> +
> +/*
> + * 'prcm' class
> + * power and reset manager (whole prcm infrastructure)
> + */
> +static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
> + .name = "prcm",
> +};
> +
> +/* prcm */
> +static struct omap_hwmod am33xx_prcm_hwmod = {
> + .name = "prcm",
> + .class = &am33xx_prcm_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> +};
> +
> +/*
> + * 'adc/tsc' class
> + * TouchScreen Controller (Anolog-To-Digital Converter)
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
> + .rev_offs = 0x00,
> + .sysc_offs = 0x10,
> + .sysc_flags = SYSC_HAS_SIDLEMODE,
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
> + .name = "adc_tsc",
> + .sysc = &am33xx_adc_tsc_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
> + { .irq = 16 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_adc_tsc_hwmod = {
> + .name = "adc_tsc",
> + .class = &am33xx_adc_tsc_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = am33xx_adc_tsc_irqs,
> + .main_clk = "adc_tsc_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * Modules omap_hwmod structures
> + *
> + * The following IPs are excluded for the moment because:
> + * - They do not need an explicit SW control using omap_hwmod API.
> + * - They still need to be validated with the driver
> + * properly adapted to omap_hwmod / omap_device
> + *
> + * - cEFUSE (doesn't fall under any ocp_if)
> + * - clkdiv32k
> + * - debugss
> + * - ocmc ram
> + * - ocp watch point
> + * - aes0
> + * - sha0
> + */
> +#if 0
> +/*
> + * 'cefuse' class
> + */
> +static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
> + .name = "cefuse",
> +};
> +
> +static struct omap_hwmod am33xx_cefuse_hwmod = {
> + .name = "cefuse",
> + .class = &am33xx_cefuse_hwmod_class,
> + .clkdm_name = "l4_cefuse_clkdm",
> + .main_clk = "cefuse_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'clkdiv32k' class
> + */
> +static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
> + .name = "clkdiv32k",
> +};
> +
> +static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
> + .name = "clkdiv32k",
> + .class = &am33xx_clkdiv32k_hwmod_class,
> + .clkdm_name = "clk_24mhz_clkdm",
> + .main_clk = "clkdiv32k_ick",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'debugss' class
> + * debug sub system
> + */
> +static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
> + .name = "debugss",
> +};
> +
> +static struct omap_hwmod am33xx_debugss_hwmod = {
> + .name = "debugss",
> + .class = &am33xx_debugss_hwmod_class,
> + .clkdm_name = "l3_aon_clkdm",
> + .main_clk = "debugss_ick",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ocmcram */
> +static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
> + .name = "ocmcram",
> +};
> +
> +static struct omap_hwmod am33xx_ocmcram_hwmod = {
> + .name = "ocmcram",
> + .class = &am33xx_ocmcram_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ocpwp */
> +static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
> + .name = "ocpwp",
> +};
> +
> +static struct omap_hwmod am33xx_ocpwp_hwmod = {
> + .name = "ocpwp",
> + .class = &am33xx_ocpwp_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'aes' class
> + */
> +static struct omap_hwmod_class am33xx_aes_hwmod_class = {
> + .name = "aes",
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
> + { .irq = 102 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_aes0_hwmod = {
> + .name = "aes0",
> + .class = &am33xx_aes_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_aes0_irqs,
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* sha0 */
> +static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
> + .name = "sha0",
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
> + { .irq = 108 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_sha0_hwmod = {
> + .name = "sha0",
> + .class = &am33xx_sha0_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_sha0_irqs,
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +#endif
> +
> +/* 'smartreflex' class */
> +static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
> + .name = "smartreflex",
> +};
> +
> +/* smartreflex0 */
> +static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
> + { .irq = 120 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_smartreflex0_hwmod = {
> + .name = "smartreflex0",
> + .class = &am33xx_smartreflex_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = am33xx_smartreflex0_irqs,
> + .main_clk = "smartreflex0_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* smartreflex1 */
> +static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
> + { .irq = 121 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_smartreflex1_hwmod = {
> + .name = "smartreflex1",
> + .class = &am33xx_smartreflex_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = am33xx_smartreflex1_irqs,
> + .main_clk = "smartreflex1_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'control' module class
> + */
> +static struct omap_hwmod_class am33xx_control_hwmod_class = {
> + .name = "control",
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
> + { .irq = 8 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_control_hwmod = {
> + .name = "control",
> + .class = &am33xx_control_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .mpu_irqs = am33xx_control_irqs,
> + .main_clk = "dpll_core_m4_div2_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'cpgmac' class
> + * cpsw/cpgmac sub system
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x8,
> + .syss_offs = 0x4,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
> + SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
> + MSTANDBY_NO),
> + .sysc_fields = &omap_hwmod_sysc_type3,
> +};
> +
> +static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
> + .name = "cpgmac0",
> + .sysc = &am33xx_cpgmac_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
> + { .name = "c0_rx_thresh_pend", .irq = 40 },
> + { .name = "c0_rx_pend", .irq = 41 },
> + { .name = "c0_tx_pend", .irq = 42 },
> + { .name = "c0_misc_pend", .irq = 43 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_cpgmac0_hwmod = {
> + .name = "cpgmac0",
> + .class = &am33xx_cpgmac0_hwmod_class,
> + .clkdm_name = "cpsw_125mhz_clkdm",
> + .mpu_irqs = am33xx_cpgmac0_irqs,
> + .main_clk = "cpsw_125mhz_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * dcan class
> + */
> +static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
> + .name = "d_can",
> +};
> +
> +/* dcan0 */
> +static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
> + { .name = "d_can_ms", .irq = 52 },
> + { .name = "d_can_mo", .irq = 53 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_dcan0_hwmod = {
> + .name = "d_can0",
> + .class = &am33xx_dcan_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_dcan0_irqs,
> + .main_clk = "dcan0_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* dcan1 */
> +static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
> + { .name = "d_can_ms", .irq = 55 },
> + { .name = "d_can_mo", .irq = 56 },
> + { .irq = -1 }
> +};
> +static struct omap_hwmod am33xx_dcan1_hwmod = {
> + .name = "d_can1",
> + .class = &am33xx_dcan_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_dcan1_irqs,
> + .main_clk = "dcan1_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* elm */
> +static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0010,
> + .syss_offs = 0x0014,
> + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> + SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_elm_hwmod_class = {
> + .name = "elm",
> + .sysc = &am33xx_elm_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
> + { .irq = 4 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_elm_hwmod = {
> + .name = "elm",
> + .class = &am33xx_elm_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_elm_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x4,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
> + MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
> + .name = "epwmss",
> + .sysc = &am33xx_epwmss_sysc,
> +};
> +
> +/* ehrpwm0 */
> +static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
> + { .name = "int", .irq = 86 },
> + { .name = "tzint", .irq = 58 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
> + .name = "ehrpwm0",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_ehrpwm0_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ehrpwm1 */
> +static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
> + { .name = "int", .irq = 87 },
> + { .name = "tzint", .irq = 59 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
> + .name = "ehrpwm1",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_ehrpwm1_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ehrpwm2 */
> +static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
> + { .name = "int", .irq = 39 },
> + { .name = "tzint", .irq = 60 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
> + .name = "ehrpwm2",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_ehrpwm2_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ecap0 */
> +static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
> + { .irq = 31 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ecap0_hwmod = {
> + .name = "ecap0",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_ecap0_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ecap1 */
> +static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
> + { .irq = 47 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ecap1_hwmod = {
> + .name = "ecap1",
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_ecap1_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* ecap2 */
> +static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
> + { .irq = 61 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_ecap2_hwmod = {
> + .name = "ecap2",
> + .mpu_irqs = am33xx_ecap2_irqs,
> + .class = &am33xx_epwmss_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'gpio' class: for gpio 0,1,2,3
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0010,
> + .syss_offs = 0x0114,
> + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
> + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
> + SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
> + .name = "gpio",
> + .sysc = &am33xx_gpio_sysc,
> + .rev = 2,
> +};
> +
> +static struct omap_gpio_dev_attr gpio_dev_attr = {
> + .bank_width = 32,
> + .dbck_flag = true,
> +};
> +
> +/* gpio0 */
> +static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
> + { .role = "dbclk", .clk = "gpio0_dbclk" },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
> + { .irq = 96 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_gpio0_hwmod = {
> + .name = "gpio1",
> + .class = &am33xx_gpio_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> + .mpu_irqs = am33xx_gpio0_irqs,
> + .main_clk = "dpll_core_m4_div2_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .opt_clks = gpio0_opt_clks,
> + .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
> + .dev_attr = &gpio_dev_attr,
> +};
> +
> +/* gpio1 */
> +static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
> + { .irq = 98 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
> + { .role = "dbclk", .clk = "gpio1_dbclk" },
> +};
> +
> +static struct omap_hwmod am33xx_gpio1_hwmod = {
> + .name = "gpio2",
> + .class = &am33xx_gpio_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> + .mpu_irqs = am33xx_gpio1_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .opt_clks = gpio1_opt_clks,
> + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
> + .dev_attr = &gpio_dev_attr,
> +};
> +
> +/* gpio2 */
> +static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
> + { .irq = 32 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
> + { .role = "dbclk", .clk = "gpio2_dbclk" },
> +};
> +
> +static struct omap_hwmod am33xx_gpio2_hwmod = {
> + .name = "gpio3",
> + .class = &am33xx_gpio_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> + .mpu_irqs = am33xx_gpio2_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .opt_clks = gpio2_opt_clks,
> + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
> + .dev_attr = &gpio_dev_attr,
> +};
> +
> +/* gpio3 */
> +static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
> + { .irq = 62 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
> + { .role = "dbclk", .clk = "gpio3_dbclk" },
> +};
> +
> +static struct omap_hwmod am33xx_gpio3_hwmod = {
> + .name = "gpio4",
> + .class = &am33xx_gpio_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
> + .mpu_irqs = am33xx_gpio3_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .opt_clks = gpio3_opt_clks,
> + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
> + .dev_attr = &gpio_dev_attr,
> +};
> +
> +/* gpmc */
> +static struct omap_hwmod_class_sysconfig gpmc_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x10,
> + .syss_offs = 0x14,
> + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
> + .name = "gpmc",
> + .sysc = &gpmc_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
> + { .irq = 100 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_gpmc_hwmod = {
> + .name = "gpmc",
> + .class = &am33xx_gpmc_hwmod_class,
> + .clkdm_name = "l3s_clkdm",
> + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
> + .mpu_irqs = am33xx_gpmc_irqs,
> + .main_clk = "l3s_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'i2c' class */
> +static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
> + .sysc_offs = 0x0010,
> + .syss_offs = 0x0090,
> + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
> + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class i2c_class = {
> + .name = "i2c",
> + .sysc = &am33xx_i2c_sysc,
> + .rev = OMAP_I2C_IP_VERSION_2,
> + .reset = &omap_i2c_reset,
> +};
> +
> +static struct omap_i2c_dev_attr i2c_dev_attr = {
> + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
> + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
> +};
> +
> +/* i2c1 */
> +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
> + { .irq = 70 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
> + { .name = "tx", .dma_req = 0, },
> + { .name = "rx", .dma_req = 0, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_i2c1_hwmod = {
> + .name = "i2c1",
> + .class = &i2c_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = i2c1_mpu_irqs,
> + .sdma_reqs = i2c1_edma_reqs,
> + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
> + .main_clk = "dpll_per_m2_div4_wkupdm_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &i2c_dev_attr,
> +};
> +
> +/* i2c1 */
> +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
> + { .irq = 71 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
> + { .name = "tx", .dma_req = 0, },
> + { .name = "rx", .dma_req = 0, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_i2c2_hwmod = {
> + .name = "i2c2",
> + .class = &i2c_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = i2c2_mpu_irqs,
> + .sdma_reqs = i2c2_edma_reqs,
> + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &i2c_dev_attr,
> +};
> +
> +/* i2c3 */
> +static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
> + { .name = "tx", .dma_req = 0, },
> + { .name = "rx", .dma_req = 0, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
> + { .irq = 30 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_i2c3_hwmod = {
> + .name = "i2c3",
> + .class = &i2c_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = i2c3_mpu_irqs,
> + .sdma_reqs = i2c3_edma_reqs,
> + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &i2c_dev_attr,
> +};
> +
> +
> +/* lcdc */
> +static struct omap_hwmod_class_sysconfig lcdc_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x54,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
> + .name = "lcdc",
> + .sysc = &lcdc_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
> + { .irq = 36 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_lcdc_hwmod = {
> + .name = "lcdc",
> + .class = &am33xx_lcdc_hwmod_class,
> + .clkdm_name = "lcdc_clkdm",
> + .mpu_irqs = am33xx_lcdc_irqs,
> + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
> + .main_clk = "lcd_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'mailbox' class
> + * mailbox module allowing communication between the on-chip processors using a
> + * queued mailbox-interrupt mechanism.
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0010,
> + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
> + .name = "mailbox",
> + .sysc = &am33xx_mailbox_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
> + { .irq = 77 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_mailbox_hwmod = {
> + .name = "mailbox",
> + .class = &am33xx_mailbox_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_mailbox_irqs,
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'mcasp' class
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x4,
> + .sysc_flags = SYSC_HAS_SIDLEMODE,
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type3,
> +};
> +
> +static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
> + .name = "mcasp",
> + .sysc = &am33xx_mcasp_sysc,
> +};
> +
> +/* mcasp0 */
> +static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
> + { .name = "ax", .irq = 80, },
> + { .name = "ar", .irq = 81, },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
> + { .name = "tx", .dma_req = 8, },
> + { .name = "rx", .dma_req = 9, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_mcasp0_hwmod = {
> + .name = "mcasp0",
> + .class = &am33xx_mcasp_hwmod_class,
> + .clkdm_name = "l3s_clkdm",
> + .mpu_irqs = am33xx_mcasp0_irqs,
> + .sdma_reqs = am33xx_mcasp0_edma_reqs,
> + .main_clk = "mcasp0_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* mcasp1 */
> +static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
> + { .name = "ax", .irq = 82, },
> + { .name = "ar", .irq = 83, },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
> + { .name = "tx", .dma_req = 10, },
> + { .name = "rx", .dma_req = 11, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_mcasp1_hwmod = {
> + .name = "mcasp1",
> + .class = &am33xx_mcasp_hwmod_class,
> + .clkdm_name = "l3s_clkdm",
> + .mpu_irqs = am33xx_mcasp1_irqs,
> + .sdma_reqs = am33xx_mcasp1_edma_reqs,
> + .main_clk = "mcasp1_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'mmc' class */
> +static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
> + .rev_offs = 0x1fc,
> + .sysc_offs = 0x10,
> + .syss_offs = 0x14,
> + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
> + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
> + .name = "mmc",
> + .sysc = &am33xx_mmc_sysc,
> +};
> +
> +/* mmc0 */
> +static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
> + { .irq = 64 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
> + { .name = "tx", .dma_req = 24, },
> + { .name = "rx", .dma_req = 25, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
> + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
> +};
> +
> +static struct omap_hwmod am33xx_mmc0_hwmod = {
> + .name = "mmc1",
> + .class = &am33xx_mmc_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_mmc0_irqs,
> + .sdma_reqs = am33xx_mmc0_edma_reqs,
> + .main_clk = "mmc_clk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &am33xx_mmc0_dev_attr,
> +};
> +
> +/* mmc1 */
> +static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
> + { .irq = 28 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
> + { .name = "tx", .dma_req = 2, },
> + { .name = "rx", .dma_req = 3, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
> + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
> +};
> +
> +static struct omap_hwmod am33xx_mmc1_hwmod = {
> + .name = "mmc2",
> + .class = &am33xx_mmc_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_mmc1_irqs,
> + .sdma_reqs = am33xx_mmc1_edma_reqs,
> + .main_clk = "mmc_clk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &am33xx_mmc1_dev_attr,
> +};
> +
> +/* mmc2 */
> +static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
> + { .irq = 29 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
> + { .name = "tx", .dma_req = 64, },
> + { .name = "rx", .dma_req = 65, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
> + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
> +};
> +static struct omap_hwmod am33xx_mmc2_hwmod = {
> + .name = "mmc3",
> + .class = &am33xx_mmc_hwmod_class,
> + .clkdm_name = "l3s_clkdm",
> + .mpu_irqs = am33xx_mmc2_irqs,
> + .sdma_reqs = am33xx_mmc2_edma_reqs,
> + .main_clk = "mmc2_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &am33xx_mmc2_dev_attr,
> +};
> +
> +/*
> + * 'rtc' class
> + * rtc subsystem
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
> + .rev_offs = 0x0074,
> + .sysc_offs = 0x0078,
> + .sysc_flags = SYSC_HAS_SIDLEMODE,
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO |
> + SIDLE_SMART | SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type3,
> +};
> +
> +static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
> + .name = "rtc",
> + .sysc = &am33xx_rtc_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
> + { .name = "rtcint", .irq = 75 },
> + { .name = "rtcalarmint", .irq = 76 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_rtc_hwmod = {
> + .name = "rtc",
> + .class = &am33xx_rtc_hwmod_class,
> + .clkdm_name = "l4_rtc_clkdm",
> + .mpu_irqs = am33xx_rtc_irqs,
> + .main_clk = "clk_32768_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'spi' class */
> +static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0110,
> + .syss_offs = 0x0114,
> + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> + SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_spi_hwmod_class = {
> + .name = "mcspi",
> + .sysc = &am33xx_mcspi_sysc,
> + .rev = OMAP4_MCSPI_REV,
> +};
> +
> +/* spi0 */
> +static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
> + { .irq = 65 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
> + { .name = "rx0", .dma_req = 17 },
> + { .name = "tx0", .dma_req = 16 },
> + { .name = "rx1", .dma_req = 19 },
> + { .name = "tx1", .dma_req = 18 },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap2_mcspi_dev_attr mcspi_attrib = {
> + .num_chipselect = 2,
> +};
> +static struct omap_hwmod am33xx_spi0_hwmod = {
> + .name = "spi0",
> + .class = &am33xx_spi_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_spi0_irqs,
> + .sdma_reqs = am33xx_mcspi0_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &mcspi_attrib,
> +};
> +
> +/* spi1 */
> +static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
> + { .irq = 125 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
> + { .name = "rx0", .dma_req = 43 },
> + { .name = "tx0", .dma_req = 42 },
> + { .name = "rx1", .dma_req = 45 },
> + { .name = "tx1", .dma_req = 44 },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_spi1_hwmod = {
> + .name = "spi1",
> + .class = &am33xx_spi_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_spi1_irqs,
> + .sdma_reqs = am33xx_mcspi1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> + .dev_attr = &mcspi_attrib,
> +};
> +
> +/*
> + * 'spinlock' class
> + * spinlock provides hardware assistance for synchronizing the
> + * processes running on multiple processors
> + */
> +static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
> + .name = "spinlock",
> +};
> +
> +static struct omap_hwmod am33xx_spinlock_hwmod = {
> + .name = "spinlock",
> + .class = &am33xx_spinlock_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .main_clk = "l4ls_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'timer 2-7' class */
> +static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0010,
> + .syss_offs = 0x0014,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_timer_hwmod_class = {
> + .name = "timer",
> + .sysc = &am33xx_timer_sysc,
> +};
> +
> +/* timer1 1ms */
> +static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
> + .rev_offs = 0x0000,
> + .sysc_offs = 0x0010,
> + .syss_offs = 0x0014,
> + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
> + SYSS_HAS_RESET_STATUS),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
> + .name = "timer",
> + .sysc = &am33xx_timer1ms_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
> + { .irq = 67 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer1_hwmod = {
> + .name = "timer1",
> + .class = &am33xx_timer1ms_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = am33xx_timer1_irqs,
> + .main_clk = "timer1_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
> + { .irq = 68 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer2_hwmod = {
> + .name = "timer2",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer2_irqs,
> + .main_clk = "timer2_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
> + { .irq = 69 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer3_hwmod = {
> + .name = "timer3",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer3_irqs,
> + .main_clk = "timer3_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
> + { .irq = 92 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer4_hwmod = {
> + .name = "timer4",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer4_irqs,
> + .main_clk = "timer4_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
> + { .irq = 93 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer5_hwmod = {
> + .name = "timer5",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer5_irqs,
> + .main_clk = "timer5_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
> + { .irq = 94 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer6_hwmod = {
> + .name = "timer6",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer6_irqs,
> + .main_clk = "timer6_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
> + { .irq = 95 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_timer7_hwmod = {
> + .name = "timer7",
> + .class = &am33xx_timer_hwmod_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_timer7_irqs,
> + .main_clk = "timer7_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* tpcc */
> +static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
> + .name = "tpcc",
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
> + { .name = "edma0", .irq = 12 },
> + { .name = "edma0_mperr", .irq = 13, },
> + { .name = "edma0_err", .irq = 14 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_tpcc_hwmod = {
> + .name = "tpcc",
> + .class = &am33xx_tpcc_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_tpcc_irqs,
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x10,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
> + SYSC_HAS_MIDLEMODE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +/* 'tptc' class */
> +static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
> + .name = "tptc",
> + .sysc = &am33xx_tptc_sysc,
> +};
> +
> +/* tptc0 */
> +static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
> + { .irq = 112 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_tptc0_hwmod = {
> + .name = "tptc0",
> + .class = &am33xx_tptc_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_tptc0_irqs,
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* tptc1 */
> +static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
> + { .irq = 113 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_tptc1_hwmod = {
> + .name = "tptc1",
> + .class = &am33xx_tptc_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_tptc1_irqs,
> + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* tptc2 */
> +static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
> + { .irq = 114 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_tptc2_hwmod = {
> + .name = "tptc2",
> + .class = &am33xx_tptc_hwmod_class,
> + .clkdm_name = "l3_clkdm",
> + .mpu_irqs = am33xx_tptc2_irqs,
> + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
> + .main_clk = "l3_gclk",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'uart' class */
> +static struct omap_hwmod_class_sysconfig uart_sysc = {
> + .rev_offs = 0x50,
> + .sysc_offs = 0x54,
> + .syss_offs = 0x58,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
> + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + SIDLE_SMART_WKUP),
> + .sysc_fields = &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class uart_class = {
> + .name = "uart",
> + .sysc = &uart_sysc,
> +};
> +
> +/* uart1 */
> +static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
> + { .name = "tx", .dma_req = 26, },
> + { .name = "rx", .dma_req = 27, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
> + { .irq = 72 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart1_hwmod = {
> + .name = "uart1",
> + .class = &uart_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .mpu_irqs = am33xx_uart1_irqs,
> + .sdma_reqs = uart1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_wkupdm_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
> + { .irq = 73 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart2_hwmod = {
> + .name = "uart2",
> + .class = &uart_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_uart2_irqs,
> + .sdma_reqs = uart1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* uart3 */
> +static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
> + { .name = "tx", .dma_req = 30, },
> + { .name = "rx", .dma_req = 31, },
> + { .dma_req = -1 }
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
> + { .irq = 74 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart3_hwmod = {
> + .name = "uart3",
> + .class = &uart_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_uart3_irqs,
> + .sdma_reqs = uart3_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
> + { .irq = 44 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart4_hwmod = {
> + .name = "uart4",
> + .class = &uart_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_uart4_irqs,
> + .sdma_reqs = uart1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
> + { .irq = 45 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart5_hwmod = {
> + .name = "uart5",
> + .class = &uart_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_uart5_irqs,
> + .sdma_reqs = uart1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
> + { .irq = 46 },
> + { .irq = -1 }
> +};
> +
> +static struct omap_hwmod am33xx_uart6_hwmod = {
> + .name = "uart6",
> + .class = &uart_class,
> + .clkdm_name = "l4ls_clkdm",
> + .mpu_irqs = am33xx_uart6_irqs,
> + .sdma_reqs = uart1_edma_reqs,
> + .main_clk = "dpll_per_m2_div4_ck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* 'wd_timer' class */
> +static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
> + .name = "wd_timer",
> +};
> +
> +/*
> + * XXX: device.c file uses hardcoded name for watchdog timer
> + * driver "wd_timer2, so we are also using same name as of now...
> + */
> +static struct omap_hwmod am33xx_wd_timer1_hwmod = {
> + .name = "wd_timer2",
> + .class = &am33xx_wd_timer_hwmod_class,
> + .clkdm_name = "l4_wkup_clkdm",
> + .main_clk = "wdt1_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> + * 'usb_otg' class
> + * high-speed on-the-go universal serial bus (usb_otg) controller
> + */
> +static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
> + .rev_offs = 0x0,
> + .sysc_offs = 0x10,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
> + .sysc_fields = &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class am33xx_usbotg_class = {
> + .name = "usbotg",
> + .sysc = &am33xx_usbhsotg_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
> + { .name = "usbss-irq", .irq = 17, },
> + { .name = "musb0-irq", .irq = 18, },
> + { .name = "musb1-irq", .irq = 19, },
> + { .irq = -1, },
> +};
> +
> +static struct omap_hwmod am33xx_usbss_hwmod = {
> + .name = "usb_otg_hs",
> + .class = &am33xx_usbotg_class,
> + .clkdm_name = "l3s_clkdm",
> + .mpu_irqs = am33xx_usbss_mpu_irqs,
> + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
> + .main_clk = "usbotg_fck",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +
> +/*
> + * Interfaces
> + */
> +
> +/* l4 fw -> emif fw */
> +static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
> + .master = &am33xx_l4_fw_hwmod,
> + .slave = &am33xx_emif_fw_hwmod,
> + .clk = "l4fw_gclk",
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
> + {
> + .pa_start = 0x4c000000,
> + .pa_end = 0x4c000fff,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +/* l3 main -> emif */
> +static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_emif_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .addr = am33xx_emif_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* mpu -> l3 main */
> +static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
> + .master = &am33xx_mpu_hwmod,
> + .slave = &am33xx_l3_main_hwmod,
> + .clk = "dpll_mpu_m2_ck",
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 main -> l4 hs */
> +static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_l4_hs_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 main -> l3 s */
> +static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_l3_s_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 s -> l4 per/ls */
> +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_l4_ls_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 s -> l4 wkup */
> +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_l4_wkup_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 s -> l4 fw */
> +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_l4_fw_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 main -> l3 instr */
> +static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_l3_instr_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* mpu -> prcm */
> +static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
> + .master = &am33xx_mpu_hwmod,
> + .slave = &am33xx_prcm_hwmod,
> + .clk = "dpll_mpu_m2_ck",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 s -> l3 main*/
> +static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_l3_main_hwmod,
> + .clk = "l3s_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* pru-icss -> l3 main */
> +static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
> + .master = &am33xx_pruss_hwmod,
> + .slave = &am33xx_l3_main_hwmod,
> + .clk = "l3_gclk",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* wkup m3 -> l4 wkup */
> +static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
> + .master = &am33xx_wkup_m3_hwmod,
> + .slave = &am33xx_l4_wkup_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* gfx -> l3 main */
> +static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
> + .master = &am33xx_gfx_hwmod,
> + .slave = &am33xx_l3_main_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 wkup -> wkup m3 */
> +static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
> + {
> + .name = "umem",
> + .pa_start = 0x44d00000,
> + .pa_end = 0x44d00000 + SZ_16K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .name = "dmem",
> + .pa_start = 0x44d80000,
> + .pa_end = 0x44d80000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_wkup_m3_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_wkup_m3_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 hs -> pru-icss */
> +static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
> + {
> + .pa_start = 0x4a300000,
> + .pa_end = 0x4a300000 + SZ_512K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
> + .master = &am33xx_l4_hs_hwmod,
> + .slave = &am33xx_pruss_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .addr = am33xx_pruss_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3 main -> gfx */
> +static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
> + {
> + .pa_start = 0x56000000,
> + .pa_end = 0x56000000 + SZ_16M - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_gfx_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .addr = am33xx_gfx_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 wkup -> smartreflex0 */
> +static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
> + {
> + .pa_start = 0x44e37000,
> + .pa_end = 0x44e37000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_smartreflex0_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_smartreflex0_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> smartreflex1 */
> +static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
> + {
> + .pa_start = 0x44e39000,
> + .pa_end = 0x44e39000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_smartreflex1_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_smartreflex1_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> control */
> +static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
> + {
> + .pa_start = 0x44e10000,
> + .pa_end = 0x44e10000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_control_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_control_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> rtc */
> +static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
> + {
> + .pa_start = 0x44e3e000,
> + .pa_end = 0x44e3e000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_rtc_hwmod,
> + .clk = "clkdiv32k_ick",
> + .addr = am33xx_rtc_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per/ls -> DCAN0 */
> +static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
> + {
> + .pa_start = 0x481CC000,
> + .pa_end = 0x481CC000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_dcan0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_dcan0_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 per/ls -> DCAN1 */
> +static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
> + {
> + .pa_start = 0x481D0000,
> + .pa_end = 0x481D0000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_dcan1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_dcan1_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 per/ls -> GPIO2 */
> +static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
> + {
> + .pa_start = 0x4804C000,
> + .pa_end = 0x4804C000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_gpio1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_gpio1_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 per/ls -> gpio3 */
> +static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
> + {
> + .pa_start = 0x481AC000,
> + .pa_end = 0x481AC000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_gpio2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_gpio2_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4 per/ls -> gpio4 */
> +static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
> + {
> + .pa_start = 0x481AE000,
> + .pa_end = 0x481AE000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_gpio3_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_gpio3_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* L4 WKUP -> I2C1 */
> +static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
> + {
> + .pa_start = 0x44E0B000,
> + .pa_end = 0x44E0B000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_i2c1_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_i2c1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* L4 WKUP -> GPIO1 */
> +static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
> + {
> + .pa_start = 0x44E07000,
> + .pa_end = 0x44E07000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_gpio0_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_gpio0_addrs,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* L4 WKUP -> ADC_TSC */
> +static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
> + {
> + .pa_start = 0x44E0D000,
> + .pa_end = 0x44E0D000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_adc_tsc_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_adc_tsc_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
> + /* cpsw ss */
> + {
> + .pa_start = 0x4a100000,
> + .pa_end = 0x4a100000 + SZ_2K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + /* cpsw wr */
> + {
> + .pa_start = 0x4a101200,
> + .pa_end = 0x4a101200 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
> + .master = &am33xx_l4_hs_hwmod,
> + .slave = &am33xx_cpgmac0_hwmod,
> + .clk = "cpsw_125mhz_gclk",
> + .addr = am33xx_cpgmac0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
> + {
> + .pa_start = 0x48080000,
> + .pa_end = 0x48080000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_elm_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_elm_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
> + {
> + .pa_start = 0x48300000,
> + .pa_end = 0x48300000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48300200,
> + .pa_end = 0x48300200 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ehrpwm0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ehrpwm0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
> + {
> + .pa_start = 0x48302000,
> + .pa_end = 0x48302000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48302200,
> + .pa_end = 0x48302200 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ehrpwm1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ehrpwm1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
> + {
> + .pa_start = 0x48304000,
> + .pa_end = 0x48304000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48304200,
> + .pa_end = 0x48304200 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ehrpwm2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ehrpwm2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
> + {
> + .pa_start = 0x48300000,
> + .pa_end = 0x48300000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48300100,
> + .pa_end = 0x48300100 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ecap0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ecap0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
> + {
> + .pa_start = 0x48302000,
> + .pa_end = 0x48302000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48302100,
> + .pa_end = 0x48302100 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ecap1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ecap1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
> + {
> + .pa_start = 0x48304000,
> + .pa_end = 0x48304000 + SZ_16 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .pa_start = 0x48304100,
> + .pa_end = 0x48304100 + SZ_256 - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_ecap2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_ecap2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3s cfg -> gpmc */
> +static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
> + {
> + .pa_start = 0x50000000,
> + .pa_end = 0x50000000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_gpmc_hwmod,
> + .clk = "l3s_gclk",
> + .addr = am33xx_gpmc_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* i2c2 */
> +static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
> + {
> + .pa_start = 0x4802A000,
> + .pa_end = 0x4802A000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_i2c2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_i2c2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
> + {
> + .pa_start = 0x4819C000,
> + .pa_end = 0x4819C000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_i2c3_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_i2c3_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
> + {
> + .pa_start = 0x4830E000,
> + .pa_end = 0x4830E000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_lcdc_hwmod,
> + .clk = "dpll_core_m4_ck",
> + .addr = am33xx_lcdc_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
> + {
> + .pa_start = 0x480C8000,
> + .pa_end = 0x480C8000 + (SZ_4K - 1),
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +/* l4 ls -> mailbox */
> +static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_mailbox_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mailbox_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> spinlock */
> +static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
> + {
> + .pa_start = 0x480Ca000,
> + .pa_end = 0x480Ca000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_spinlock_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_spinlock_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> mcasp0 */
> +static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
> + {
> + .pa_start = 0x48038000,
> + .pa_end = 0x48038000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_mcasp0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mcasp0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 s -> mcasp0 data */
> +static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
> + {
> + .pa_start = 0x46000000,
> + .pa_end = 0x46000000 + SZ_4M - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_mcasp0_hwmod,
> + .clk = "l3s_gclk",
> + .addr = am33xx_mcasp0_data_addr_space,
> + .user = OCP_USER_SDMA,
> +};
> +
> +/* l4 ls -> mcasp1 */
> +static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
> + {
> + .pa_start = 0x4803C000,
> + .pa_end = 0x4803C000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_mcasp1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mcasp1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 s -> mcasp1 data */
> +static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
> + {
> + .pa_start = 0x46400000,
> + .pa_end = 0x46400000 + SZ_4M - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_mcasp1_hwmod,
> + .clk = "l3s_gclk",
> + .addr = am33xx_mcasp1_data_addr_space,
> + .user = OCP_USER_SDMA,
> +};
> +
> +/* l4 ls -> mmc0 */
> +static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
> + {
> + .pa_start = 0x48060100,
> + .pa_end = 0x48060100 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_mmc0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mmc0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> mmc1 */
> +static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
> + {
> + .pa_start = 0x481d8100,
> + .pa_end = 0x481d8100 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_mmc1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mmc1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 s -> mmc2 */
> +static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
> + {
> + .pa_start = 0x47810100,
> + .pa_end = 0x47810100 + SZ_64K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_mmc2_hwmod,
> + .clk = "l3s_gclk",
> + .addr = am33xx_mmc2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> mcspi0 */
> +static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
> + {
> + .pa_start = 0x48030000,
> + .pa_end = 0x48030000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_spi0_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mcspi0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> mcspi1 */
> +static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
> + {
> + .pa_start = 0x481A0000,
> + .pa_end = 0x481A0000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_spi1_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_mcspi1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> timer1 */
> +static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
> + {
> + .pa_start = 0x44E31000,
> + .pa_end = 0x44E31000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_timer1_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_timer1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer2 */
> +static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
> + {
> + .pa_start = 0x48040000,
> + .pa_end = 0x48040000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer3 */
> +static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
> + {
> + .pa_start = 0x48042000,
> + .pa_end = 0x48042000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer3_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer3_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer4 */
> +static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
> + {
> + .pa_start = 0x48044000,
> + .pa_end = 0x48044000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer4_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer4_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer5 */
> +static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
> + {
> + .pa_start = 0x48046000,
> + .pa_end = 0x48046000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer5_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer5_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer6 */
> +static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
> + {
> + .pa_start = 0x48048000,
> + .pa_end = 0x48048000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer6_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer6_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 per -> timer7 */
> +static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
> + {
> + .pa_start = 0x4804A000,
> + .pa_end = 0x4804A000 + SZ_1K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_timer7_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_timer7_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 main -> tpcc */
> +static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
> + {
> + .pa_start = 0x49000000,
> + .pa_end = 0x49000000 + SZ_32K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_tpcc_hwmod,
> + .clk = "l3_gclk",
> + .addr = am33xx_tpcc_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 main -> tpcc0 */
> +static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
> + {
> + .pa_start = 0x49800000,
> + .pa_end = 0x49800000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_tptc0_hwmod,
> + .clk = "l3_gclk",
> + .addr = am33xx_tptc0_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 main -> tpcc1 */
> +static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
> + {
> + .pa_start = 0x49900000,
> + .pa_end = 0x49900000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_tptc1_hwmod,
> + .clk = "l3_gclk",
> + .addr = am33xx_tptc1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l3 main -> tpcc2 */
> +static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
> + {
> + .pa_start = 0x49a00000,
> + .pa_end = 0x49a00000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_tptc2_hwmod,
> + .clk = "l3_gclk",
> + .addr = am33xx_tptc2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> uart1 */
> +static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
> + {
> + .pa_start = 0x44E09000,
> + .pa_end = 0x44E09000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_uart1_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_uart1_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> uart2 */
> +static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
> + {
> + .pa_start = 0x48022000,
> + .pa_end = 0x48022000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_uart2_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_uart2_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> uart3 */
> +static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
> + {
> + .pa_start = 0x48024000,
> + .pa_end = 0x48024000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_uart3_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_uart3_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> uart4 */
> +static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
> + {
> + .pa_start = 0x481A6000,
> + .pa_end = 0x481A6000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_uart4_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_uart4_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> uart5 */
> +static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
> + {
> + .pa_start = 0x481A8000,
> + .pa_end = 0x481A8000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_uart5_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_uart5_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 ls -> uart6 */
> +static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
> + {
> + .pa_start = 0x481aa000,
> + .pa_end = 0x481aa000 + SZ_8K - 1,
> + .flags = ADDR_TYPE_RT,
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
> + .master = &am33xx_l4_ls_hwmod,
> + .slave = &am33xx_uart6_hwmod,
> + .clk = "l4ls_gclk",
> + .addr = am33xx_uart6_addr_space,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* l4 wkup -> wd_timer1 */
> +static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
> + {
> + .pa_start = 0x44e35000,
> + .pa_end = 0x44e35000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
> + .master = &am33xx_l4_wkup_hwmod,
> + .slave = &am33xx_wd_timer1_hwmod,
> + .clk = "dpll_core_m4_div2_ck",
> + .addr = am33xx_wd_timer1_addrs,
> + .user = OCP_USER_MPU,
> +};
> +
> +/* usbss */
> +/* l3 s -> USBSS interface */
> +static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
> + {
> + .name = "usbss",
> + .pa_start = 0x47400000,
> + .pa_end = 0x47400000 + SZ_4K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .name = "musb0",
> + .pa_start = 0x47401000,
> + .pa_end = 0x47401000 + SZ_2K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + {
> + .name = "musb1",
> + .pa_start = 0x47401800,
> + .pa_end = 0x47401800 + SZ_2K - 1,
> + .flags = ADDR_TYPE_RT
> + },
> + { }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
> + .master = &am33xx_l3_s_hwmod,
> + .slave = &am33xx_usbss_hwmod,
> + .clk = "l3s_gclk",
> + .addr = am33xx_usbss_addr_space,
> + .user = OCP_USER_MPU,
> + .flags = OCPIF_SWSUP_IDLE,
> +};
> +
> +static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
> + &am33xx_l4_fw__emif_fw,
> + &am33xx_l3_main__emif,
> + &am33xx_mpu__l3_main,
> + &am33xx_mpu__prcm,
> + &am33xx_l3_s__l4_ls,
> + &am33xx_l3_s__l4_wkup,
> + &am33xx_l3_s__l4_fw,
> + &am33xx_l3_main__l4_hs,
> + &am33xx_l3_main__l3_s,
> + &am33xx_l3_main__l3_instr,
> + &am33xx_l3_main__gfx,
> + &am33xx_l3_s__l3_main,
> + &am33xx_pruss__l3_main,
> + &am33xx_wkup_m3__l4_wkup,
> + &am33xx_gfx__l3_main,
> + &am33xx_l4_wkup__wkup_m3,
> + &am33xx_l4_wkup__control,
> + &am33xx_l4_wkup__smartreflex0,
> + &am33xx_l4_wkup__smartreflex1,
> + &am33xx_l4_wkup__uart1,
> + &am33xx_l4_wkup__timer1,
> + &am33xx_l4_wkup__rtc,
> + &am33xx_l4_wkup__i2c1,
> + &am33xx_l4_wkup__gpio0,
> + &am33xx_l4_wkup__adc_tsc,
> + &am33xx_l4_wkup__wd_timer1,
> + &am33xx_l4_hs__pruss,
> + &am33xx_l4_per__dcan0,
> + &am33xx_l4_per__dcan1,
> + &am33xx_l4_per__gpio1,
> + &am33xx_l4_per__gpio2,
> + &am33xx_l4_per__gpio3,
> + &am33xx_l4_per__i2c2,
> + &am33xx_l4_per__i2c3,
> + &am33xx_l4_per__mailbox,
> + &am33xx_l4_ls__mcasp0,
> + &am33xx_l3_s__mcasp0_data,
> + &am33xx_l4_ls__mcasp1,
> + &am33xx_l3_s__mcasp1_data,
> + &am33xx_l4_ls__mmc0,
> + &am33xx_l4_ls__mmc1,
> + &am33xx_l3_s__mmc2,
> + &am33xx_l4_ls__timer2,
> + &am33xx_l4_ls__timer3,
> + &am33xx_l4_ls__timer4,
> + &am33xx_l4_ls__timer5,
> + &am33xx_l4_ls__timer6,
> + &am33xx_l4_ls__timer7,
> + &am33xx_l3_main__tpcc,
> + &am33xx_l4_ls__uart2,
> + &am33xx_l4_ls__uart3,
> + &am33xx_l4_ls__uart4,
> + &am33xx_l4_ls__uart5,
> + &am33xx_l4_ls__uart6,
> + &am33xx_l4_ls__spinlock,
> + &am33xx_l4_ls__elm,
> + &am33xx_l4_ls__ehrpwm0,
> + &am33xx_l4_ls__ehrpwm1,
> + &am33xx_l4_ls__ehrpwm2,
> + &am33xx_l4_ls__ecap0,
> + &am33xx_l4_ls__ecap1,
> + &am33xx_l4_ls__ecap2,
> + &am33xx_l3_s__gpmc,
> + &am33xx_l3_main__lcdc,
> + &am33xx_l4_ls__mcspi0,
> + &am33xx_l4_ls__mcspi1,
> + &am33xx_l3_main__tptc0,
> + &am33xx_l3_main__tptc1,
> + &am33xx_l3_main__tptc2,
> + &am33xx_l3_s__usbss,
> + &am33xx_l4_hs__cpgmac0,
> + NULL,
> +};
> +
> +int __init am33xx_hwmod_init(void)
> +{
> + omap_hwmod_init();
> + return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
> +}
> diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
> index 6132972..9b9646c 100644
> --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
> +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
> @@ -658,6 +658,7 @@ extern int omap2420_hwmod_init(void);
> extern int omap2430_hwmod_init(void);
> extern int omap3xxx_hwmod_init(void);
> extern int omap44xx_hwmod_init(void);
> +extern int am33xx_hwmod_init(void);
>
> extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
>
> --
> 1.7.10.4
>
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-07-26 20:02 ` Paul Walmsley
@ 2012-08-14 8:29 ` Tony Lindgren
-1 siblings, 0 replies; 28+ messages in thread
From: Tony Lindgren @ 2012-08-14 8:29 UTC (permalink / raw)
To: Paul Walmsley
Cc: Vaibhav Hiremath, linux-omap, linux-arm-kernel, Afzal Mohammed,
Vaibhav Bedia, Benoit Cousson, Kevin Hilman, Rajendra Nayak
Hi,
* Paul Walmsley <paul@pwsan.com> [120726 13:07]:
> On Wed, 25 Jul 2012, Paul Walmsley wrote:
>
> > These IP blocks and the ECAP IP blocks have periods in their names.
> > The rest of the IP block named in the file don't use periods -- which
> > is also the style used by the rest of the OMAP SoCs. Is there
> > some reason that these have periods in their names?
>
> I've changed those to match the rest of the names, and queued the
> following for 3.7.
>
> Thanks again for all the hard work you all put into this. I realize that
> with all the upstream changes, this was probably a little painful for you.
> But from my perspective you've been a pleasure to work with through the
> process.
As am33xx and omap5 are DT only, we should start moving towards getting
rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
data from .dtsi files instead.
Alternatively we could get rid of the names and match the module based on
pa_start and pa_end.
Regards,
Tony
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-08-14 8:29 ` Tony Lindgren
0 siblings, 0 replies; 28+ messages in thread
From: Tony Lindgren @ 2012-08-14 8:29 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
* Paul Walmsley <paul@pwsan.com> [120726 13:07]:
> On Wed, 25 Jul 2012, Paul Walmsley wrote:
>
> > These IP blocks and the ECAP IP blocks have periods in their names.
> > The rest of the IP block named in the file don't use periods -- which
> > is also the style used by the rest of the OMAP SoCs. Is there
> > some reason that these have periods in their names?
>
> I've changed those to match the rest of the names, and queued the
> following for 3.7.
>
> Thanks again for all the hard work you all put into this. I realize that
> with all the upstream changes, this was probably a little painful for you.
> But from my perspective you've been a pleasure to work with through the
> process.
As am33xx and omap5 are DT only, we should start moving towards getting
rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
data from .dtsi files instead.
Alternatively we could get rid of the names and match the module based on
pa_start and pa_end.
Regards,
Tony
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-08-14 8:29 ` Tony Lindgren
@ 2012-08-15 9:10 ` Hiremath, Vaibhav
-1 siblings, 0 replies; 28+ messages in thread
From: Hiremath, Vaibhav @ 2012-08-15 9:10 UTC (permalink / raw)
To: Tony Lindgren, Paul Walmsley
Cc: linux-omap, linux-arm-kernel, Mohammed, Afzal, Bedia, Vaibhav,
Cousson, Benoit, Hilman, Kevin, Nayak, Rajendra
On Tue, Aug 14, 2012 at 13:59:12, Tony Lindgren wrote:
> Hi,
>
> * Paul Walmsley <paul@pwsan.com> [120726 13:07]:
> > On Wed, 25 Jul 2012, Paul Walmsley wrote:
> >
> > > These IP blocks and the ECAP IP blocks have periods in their names.
> > > The rest of the IP block named in the file don't use periods -- which
> > > is also the style used by the rest of the OMAP SoCs. Is there
> > > some reason that these have periods in their names?
> >
> > I've changed those to match the rest of the names, and queued the
> > following for 3.7.
> >
> > Thanks again for all the hard work you all put into this. I realize that
> > with all the upstream changes, this was probably a little painful for you.
> > But from my perspective you've been a pleasure to work with through the
> > process.
>
> As am33xx and omap5 are DT only, we should start moving towards getting
> rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
> data from .dtsi files instead.
>
It may not be so straight, given the fact that hwmod layer
requires these resources, as hwmod is responsible to configure SYSCONF
register of the device (happens very early at core_init level).
Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
core_init call, which will take DT resources and initialize accordingly.
Another dependency we will have is on system timers, Jon has already done
some initial work on this, but I believe we did not concluded on the it.
I will re-start the thread again, since in any case DT support in timer is
required.
> Alternatively we could get rid of the names and match the module based on
> pa_start and pa_end.
>
Just FYI, from resource perspective, I have changed omap_device layer for DT
resources only (still need hwmod resources as explained above) and patch
looks something like (and it works) -
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..cb481fe 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -528,10 +528,15 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
* HACK: Ideally the resources from DT should match, and hwmod
* should just add the missing ones. Since the name is not
* properly populated by DT, stick to hwmod resources only.
+ *
+ * But in case of all new devices, like AM33XX and OMAP5, where
+ * only DT boot is supported, stick to DT resources only.
*/
- if (pdev->num_resources && pdev->resource)
+ if (pdev->num_resources && pdev->resource) {
dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
__func__, pdev->num_resources);
+ goto skip_res_override;
+ }
res_count = omap_device_count_resources(od);
if (res_count > 0) {
@@ -550,6 +555,7 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
goto oda_exit3;
}
+skip_res_override:
if (!pm_lats) {
pm_lats = omap_default_latency;
pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
Thanks,
Vaibhav
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-08-15 9:10 ` Hiremath, Vaibhav
0 siblings, 0 replies; 28+ messages in thread
From: Hiremath, Vaibhav @ 2012-08-15 9:10 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Aug 14, 2012 at 13:59:12, Tony Lindgren wrote:
> Hi,
>
> * Paul Walmsley <paul@pwsan.com> [120726 13:07]:
> > On Wed, 25 Jul 2012, Paul Walmsley wrote:
> >
> > > These IP blocks and the ECAP IP blocks have periods in their names.
> > > The rest of the IP block named in the file don't use periods -- which
> > > is also the style used by the rest of the OMAP SoCs. Is there
> > > some reason that these have periods in their names?
> >
> > I've changed those to match the rest of the names, and queued the
> > following for 3.7.
> >
> > Thanks again for all the hard work you all put into this. I realize that
> > with all the upstream changes, this was probably a little painful for you.
> > But from my perspective you've been a pleasure to work with through the
> > process.
>
> As am33xx and omap5 are DT only, we should start moving towards getting
> rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
> data from .dtsi files instead.
>
It may not be so straight, given the fact that hwmod layer
requires these resources, as hwmod is responsible to configure SYSCONF
register of the device (happens very early at core_init level).
Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
core_init call, which will take DT resources and initialize accordingly.
Another dependency we will have is on system timers, Jon has already done
some initial work on this, but I believe we did not concluded on the it.
I will re-start the thread again, since in any case DT support in timer is
required.
> Alternatively we could get rid of the names and match the module based on
> pa_start and pa_end.
>
Just FYI, from resource perspective, I have changed omap_device layer for DT
resources only (still need hwmod resources as explained above) and patch
looks something like (and it works) -
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..cb481fe 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -528,10 +528,15 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
* HACK: Ideally the resources from DT should match, and hwmod
* should just add the missing ones. Since the name is not
* properly populated by DT, stick to hwmod resources only.
+ *
+ * But in case of all new devices, like AM33XX and OMAP5, where
+ * only DT boot is supported, stick to DT resources only.
*/
- if (pdev->num_resources && pdev->resource)
+ if (pdev->num_resources && pdev->resource) {
dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
__func__, pdev->num_resources);
+ goto skip_res_override;
+ }
res_count = omap_device_count_resources(od);
if (res_count > 0) {
@@ -550,6 +555,7 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
goto oda_exit3;
}
+skip_res_override:
if (!pm_lats) {
pm_lats = omap_default_latency;
pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
Thanks,
Vaibhav
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-08-15 9:10 ` Hiremath, Vaibhav
@ 2012-08-17 7:49 ` Tony Lindgren
-1 siblings, 0 replies; 28+ messages in thread
From: Tony Lindgren @ 2012-08-17 7:49 UTC (permalink / raw)
To: Hiremath, Vaibhav
Cc: Paul Walmsley, linux-omap, linux-arm-kernel, Mohammed, Afzal,
Bedia, Vaibhav, Cousson, Benoit, Hilman, Kevin, Nayak, Rajendra
* Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> On Tue, Aug 14, 2012 at 13:59:12, Tony Lindgren wrote:
> > Hi,
> >
> > * Paul Walmsley <paul@pwsan.com> [120726 13:07]:
> > > On Wed, 25 Jul 2012, Paul Walmsley wrote:
> > >
> > > > These IP blocks and the ECAP IP blocks have periods in their names.
> > > > The rest of the IP block named in the file don't use periods -- which
> > > > is also the style used by the rest of the OMAP SoCs. Is there
> > > > some reason that these have periods in their names?
> > >
> > > I've changed those to match the rest of the names, and queued the
> > > following for 3.7.
> > >
> > > Thanks again for all the hard work you all put into this. I realize that
> > > with all the upstream changes, this was probably a little painful for you.
> > > But from my perspective you've been a pleasure to work with through the
> > > process.
> >
> > As am33xx and omap5 are DT only, we should start moving towards getting
> > rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
> > data from .dtsi files instead.
> >
>
> It may not be so straight, given the fact that hwmod layer
> requires these resources, as hwmod is responsible to configure SYSCONF
> register of the device (happens very early at core_init level).
>
> Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> core_init call, which will take DT resources and initialize accordingly.
That's for the device reset/idle? We should not do that in hwmod code
except in late_initcall for unclaimed devices as discussed earlier. We
discussed setting up the reset function in the device specific headers
so both device and hwmod code can call them as needed.
> Another dependency we will have is on system timers, Jon has already done
> some initial work on this, but I believe we did not concluded on the it.
> I will re-start the thread again, since in any case DT support in timer is
> required.
Right.. The timers are a pain right now as they need to be initialized
early. Everything else can and should be initialized at the device probe
time, or from a late_initcall for the unclaimed devices.
> > Alternatively we could get rid of the names and match the module based on
> > pa_start and pa_end.
> >
>
> Just FYI, from resource perspective, I have changed omap_device layer for DT
> resources only (still need hwmod resources as explained above) and patch
> looks something like (and it works) -
Cool yeah few more dependencies remain still.
Regards,
Tony
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-08-17 7:49 ` Tony Lindgren
0 siblings, 0 replies; 28+ messages in thread
From: Tony Lindgren @ 2012-08-17 7:49 UTC (permalink / raw)
To: linux-arm-kernel
* Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> On Tue, Aug 14, 2012 at 13:59:12, Tony Lindgren wrote:
> > Hi,
> >
> > * Paul Walmsley <paul@pwsan.com> [120726 13:07]:
> > > On Wed, 25 Jul 2012, Paul Walmsley wrote:
> > >
> > > > These IP blocks and the ECAP IP blocks have periods in their names.
> > > > The rest of the IP block named in the file don't use periods -- which
> > > > is also the style used by the rest of the OMAP SoCs. Is there
> > > > some reason that these have periods in their names?
> > >
> > > I've changed those to match the rest of the names, and queued the
> > > following for 3.7.
> > >
> > > Thanks again for all the hard work you all put into this. I realize that
> > > with all the upstream changes, this was probably a little painful for you.
> > > But from my perspective you've been a pleasure to work with through the
> > > process.
> >
> > As am33xx and omap5 are DT only, we should start moving towards getting
> > rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
> > data from .dtsi files instead.
> >
>
> It may not be so straight, given the fact that hwmod layer
> requires these resources, as hwmod is responsible to configure SYSCONF
> register of the device (happens very early at core_init level).
>
> Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> core_init call, which will take DT resources and initialize accordingly.
That's for the device reset/idle? We should not do that in hwmod code
except in late_initcall for unclaimed devices as discussed earlier. We
discussed setting up the reset function in the device specific headers
so both device and hwmod code can call them as needed.
> Another dependency we will have is on system timers, Jon has already done
> some initial work on this, but I believe we did not concluded on the it.
> I will re-start the thread again, since in any case DT support in timer is
> required.
Right.. The timers are a pain right now as they need to be initialized
early. Everything else can and should be initialized at the device probe
time, or from a late_initcall for the unclaimed devices.
> > Alternatively we could get rid of the names and match the module based on
> > pa_start and pa_end.
> >
>
> Just FYI, from resource perspective, I have changed omap_device layer for DT
> resources only (still need hwmod resources as explained above) and patch
> looks something like (and it works) -
Cool yeah few more dependencies remain still.
Regards,
Tony
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-08-17 7:49 ` Tony Lindgren
@ 2012-08-17 8:22 ` Hiremath, Vaibhav
-1 siblings, 0 replies; 28+ messages in thread
From: Hiremath, Vaibhav @ 2012-08-17 8:22 UTC (permalink / raw)
To: Tony Lindgren
Cc: Paul Walmsley, linux-omap, linux-arm-kernel, Mohammed, Afzal,
Bedia, Vaibhav, Cousson, Benoit, Hilman, Kevin, Nayak, Rajendra
On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> > On Tue, Aug 14, 2012 at 13:59:12, Tony Lindgren wrote:
> > > Hi,
> > >
> > > * Paul Walmsley <paul@pwsan.com> [120726 13:07]:
> > > > On Wed, 25 Jul 2012, Paul Walmsley wrote:
> > > >
> > > > > These IP blocks and the ECAP IP blocks have periods in their names.
> > > > > The rest of the IP block named in the file don't use periods -- which
> > > > > is also the style used by the rest of the OMAP SoCs. Is there
> > > > > some reason that these have periods in their names?
> > > >
> > > > I've changed those to match the rest of the names, and queued the
> > > > following for 3.7.
> > > >
> > > > Thanks again for all the hard work you all put into this. I realize that
> > > > with all the upstream changes, this was probably a little painful for you.
> > > > But from my perspective you've been a pleasure to work with through the
> > > > process.
> > >
> > > As am33xx and omap5 are DT only, we should start moving towards getting
> > > rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
> > > data from .dtsi files instead.
> > >
> >
> > It may not be so straight, given the fact that hwmod layer
> > requires these resources, as hwmod is responsible to configure SYSCONF
> > register of the device (happens very early at core_init level).
> >
> > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> > core_init call, which will take DT resources and initialize accordingly.
>
> That's for the device reset/idle? We should not do that in hwmod code
> except in late_initcall for unclaimed devices as discussed earlier. We
> discussed setting up the reset function in the device specific headers
> so both device and hwmod code can call them as needed.
>
Tony,
May be I didn't understand your above statement, can you please elaborate
more on "device specific header file"?
Just to highlight, its not only during late_initcall, the _enable and _idle
functions are getting executed as part of every runtime_pm_get\put_sync from
the driver.
Are you saying as part of late_initcall, we should initialize " _mpu_rt_va"
of "struct omap_hwmod"???
Also, as far unclaimed resources is concerned, somewhere you should have
base addr of the device maintained, right? Currently, hwmod is maintaining
this data and the execution goes something like,
Core_initcall()
-> _setup()
-> _setup_reset()
-> _idle()
Another biggest worry is, if I play here, it may break existing omap3/4
Functionality, especially may impact from PM perspective. So I believe, we
need to have something which adds/cleans-up things in stages.
May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
now??
Any thoughts??
Thanks,
Vaibhav
> > Another dependency we will have is on system timers, Jon has already done
> > some initial work on this, but I believe we did not concluded on the it.
> > I will re-start the thread again, since in any case DT support in timer is
> > required.
>
> Right.. The timers are a pain right now as they need to be initialized
> early. Everything else can and should be initialized at the device probe
> time, or from a late_initcall for the unclaimed devices.
>
> > > Alternatively we could get rid of the names and match the module based on
> > > pa_start and pa_end.
> > >
> >
> > Just FYI, from resource perspective, I have changed omap_device layer for DT
> > resources only (still need hwmod resources as explained above) and patch
> > looks something like (and it works) -
>
> Cool yeah few more dependencies remain still.
>
> Regards,
>
> Tony
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-08-17 8:22 ` Hiremath, Vaibhav
0 siblings, 0 replies; 28+ messages in thread
From: Hiremath, Vaibhav @ 2012-08-17 8:22 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> > On Tue, Aug 14, 2012 at 13:59:12, Tony Lindgren wrote:
> > > Hi,
> > >
> > > * Paul Walmsley <paul@pwsan.com> [120726 13:07]:
> > > > On Wed, 25 Jul 2012, Paul Walmsley wrote:
> > > >
> > > > > These IP blocks and the ECAP IP blocks have periods in their names.
> > > > > The rest of the IP block named in the file don't use periods -- which
> > > > > is also the style used by the rest of the OMAP SoCs. Is there
> > > > > some reason that these have periods in their names?
> > > >
> > > > I've changed those to match the rest of the names, and queued the
> > > > following for 3.7.
> > > >
> > > > Thanks again for all the hard work you all put into this. I realize that
> > > > with all the upstream changes, this was probably a little painful for you.
> > > > But from my perspective you've been a pleasure to work with through the
> > > > process.
> > >
> > > As am33xx and omap5 are DT only, we should start moving towards getting
> > > rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
> > > data from .dtsi files instead.
> > >
> >
> > It may not be so straight, given the fact that hwmod layer
> > requires these resources, as hwmod is responsible to configure SYSCONF
> > register of the device (happens very early at core_init level).
> >
> > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> > core_init call, which will take DT resources and initialize accordingly.
>
> That's for the device reset/idle? We should not do that in hwmod code
> except in late_initcall for unclaimed devices as discussed earlier. We
> discussed setting up the reset function in the device specific headers
> so both device and hwmod code can call them as needed.
>
Tony,
May be I didn't understand your above statement, can you please elaborate
more on "device specific header file"?
Just to highlight, its not only during late_initcall, the _enable and _idle
functions are getting executed as part of every runtime_pm_get\put_sync from
the driver.
Are you saying as part of late_initcall, we should initialize " _mpu_rt_va"
of "struct omap_hwmod"???
Also, as far unclaimed resources is concerned, somewhere you should have
base addr of the device maintained, right? Currently, hwmod is maintaining
this data and the execution goes something like,
Core_initcall()
-> _setup()
-> _setup_reset()
-> _idle()
Another biggest worry is, if I play here, it may break existing omap3/4
Functionality, especially may impact from PM perspective. So I believe, we
need to have something which adds/cleans-up things in stages.
May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
now??
Any thoughts??
Thanks,
Vaibhav
> > Another dependency we will have is on system timers, Jon has already done
> > some initial work on this, but I believe we did not concluded on the it.
> > I will re-start the thread again, since in any case DT support in timer is
> > required.
>
> Right.. The timers are a pain right now as they need to be initialized
> early. Everything else can and should be initialized at the device probe
> time, or from a late_initcall for the unclaimed devices.
>
> > > Alternatively we could get rid of the names and match the module based on
> > > pa_start and pa_end.
> > >
> >
> > Just FYI, from resource perspective, I have changed omap_device layer for DT
> > resources only (still need hwmod resources as explained above) and patch
> > looks something like (and it works) -
>
> Cool yeah few more dependencies remain still.
>
> Regards,
>
> Tony
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-08-17 8:22 ` Hiremath, Vaibhav
@ 2012-08-17 8:40 ` Tony Lindgren
-1 siblings, 0 replies; 28+ messages in thread
From: Tony Lindgren @ 2012-08-17 8:40 UTC (permalink / raw)
To: Hiremath, Vaibhav
Cc: Paul Walmsley, linux-omap, linux-arm-kernel, Mohammed, Afzal,
Bedia, Vaibhav, Cousson, Benoit, Hilman, Kevin, Nayak, Rajendra
* Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
> On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> > >
> > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> > > core_init call, which will take DT resources and initialize accordingly.
> >
> > That's for the device reset/idle? We should not do that in hwmod code
> > except in late_initcall for unclaimed devices as discussed earlier. We
> > discussed setting up the reset function in the device specific headers
> > so both device and hwmod code can call them as needed.
>
> May be I didn't understand your above statement, can you please elaborate
> more on "device specific header file"?
We should have the device drivers idle and reset the devices. But also
hwmod may need to do that for the unclaimed devices for PM to work.
As the driver may not be even compiled in, the driver specific reset and
idle functions should be static inline functions in the device specific
header file so hwmod code can still call those.
> Just to highlight, its not only during late_initcall, the _enable and _idle
> functions are getting executed as part of every runtime_pm_get\put_sync from
> the driver.
Right, so no need to initialize those until at driver probe time.
> Are you saying as part of late_initcall, we should initialize " _mpu_rt_va"
> of "struct omap_hwmod"???
I guess either at driver probe for the claimed devices, or at late_initcall
for the unclaimeded devices.
> Also, as far unclaimed resources is concerned, somewhere you should have
> base addr of the device maintained, right? Currently, hwmod is maintaining
> this data and the execution goes something like,
>
> Core_initcall()
> -> _setup()
> -> _setup_reset()
> -> _idle()
For the DT only case also the unclaimed devices can from DT with
status = "disabled".
> Another biggest worry is, if I play here, it may break existing omap3/4
> Functionality, especially may impact from PM perspective. So I believe, we
> need to have something which adds/cleans-up things in stages.
It seems that we need three stages: Something early for the timers only,
initialize most things during driver probe, then late_initcall for the
unclaimed devices.
> May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
> now??
Sorry I don't follow this part, care to explain a little more?
Regards,
Tony
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-08-17 8:40 ` Tony Lindgren
0 siblings, 0 replies; 28+ messages in thread
From: Tony Lindgren @ 2012-08-17 8:40 UTC (permalink / raw)
To: linux-arm-kernel
* Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
> On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> > >
> > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> > > core_init call, which will take DT resources and initialize accordingly.
> >
> > That's for the device reset/idle? We should not do that in hwmod code
> > except in late_initcall for unclaimed devices as discussed earlier. We
> > discussed setting up the reset function in the device specific headers
> > so both device and hwmod code can call them as needed.
>
> May be I didn't understand your above statement, can you please elaborate
> more on "device specific header file"?
We should have the device drivers idle and reset the devices. But also
hwmod may need to do that for the unclaimed devices for PM to work.
As the driver may not be even compiled in, the driver specific reset and
idle functions should be static inline functions in the device specific
header file so hwmod code can still call those.
> Just to highlight, its not only during late_initcall, the _enable and _idle
> functions are getting executed as part of every runtime_pm_get\put_sync from
> the driver.
Right, so no need to initialize those until at driver probe time.
> Are you saying as part of late_initcall, we should initialize " _mpu_rt_va"
> of "struct omap_hwmod"???
I guess either at driver probe for the claimed devices, or at late_initcall
for the unclaimeded devices.
> Also, as far unclaimed resources is concerned, somewhere you should have
> base addr of the device maintained, right? Currently, hwmod is maintaining
> this data and the execution goes something like,
>
> Core_initcall()
> -> _setup()
> -> _setup_reset()
> -> _idle()
For the DT only case also the unclaimed devices can from DT with
status = "disabled".
> Another biggest worry is, if I play here, it may break existing omap3/4
> Functionality, especially may impact from PM perspective. So I believe, we
> need to have something which adds/cleans-up things in stages.
It seems that we need three stages: Something early for the timers only,
initialize most things during driver probe, then late_initcall for the
unclaimed devices.
> May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
> now??
Sorry I don't follow this part, care to explain a little more?
Regards,
Tony
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-08-17 8:40 ` Tony Lindgren
@ 2012-08-17 9:51 ` Hiremath, Vaibhav
-1 siblings, 0 replies; 28+ messages in thread
From: Hiremath, Vaibhav @ 2012-08-17 9:51 UTC (permalink / raw)
To: Tony Lindgren
Cc: Paul Walmsley, linux-omap, linux-arm-kernel, Mohammed, Afzal,
Bedia, Vaibhav, Cousson, Benoit, Hilman, Kevin, Nayak, Rajendra
On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
> > On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > > * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> > > >
> > > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> > > > core_init call, which will take DT resources and initialize accordingly.
> > >
> > > That's for the device reset/idle? We should not do that in hwmod code
> > > except in late_initcall for unclaimed devices as discussed earlier. We
> > > discussed setting up the reset function in the device specific headers
> > > so both device and hwmod code can call them as needed.
> >
> > May be I didn't understand your above statement, can you please elaborate
> > more on "device specific header file"?
>
> We should have the device drivers idle and reset the devices. But also
> hwmod may need to do that for the unclaimed devices for PM to work.
> As the driver may not be even compiled in, the driver specific reset and
> idle functions should be static inline functions in the device specific
> header file so hwmod code can still call those.
>
How about mapping the address of the devices?
Some more thoughts on the similar line on unclaimed devices -
As par of late_initcall(), traverse all the DTB nodes and for each node with
"state = disabled", we can do something like,
Late_initcall()
-> Traverse DTB nodes and check for "state = disabled"
-> Read the "ti,hwmod" entry and get offsets like, sys_config
and reset.
-> Map the base address
-> Enable the module/clock
-> Reset the device
-> Write to sysc register offset
-> Disable the module/clock
> > Just to highlight, its not only during late_initcall, the _enable and _idle
> > functions are getting executed as part of every runtime_pm_get\put_sync from
> > the driver.
>
> Right, so no need to initialize those until at driver probe time.
>
Agreed.
> > Are you saying as part of late_initcall, we should initialize " _mpu_rt_va"
> > of "struct omap_hwmod"???
>
> I guess either at driver probe for the claimed devices, or at late_initcall
> for the unclaimeded devices.
>
> > Also, as far unclaimed resources is concerned, somewhere you should have
> > base addr of the device maintained, right? Currently, hwmod is maintaining
> > this data and the execution goes something like,
> >
> > Core_initcall()
> > -> _setup()
> > -> _setup_reset()
> > -> _idle()
>
> For the DT only case also the unclaimed devices can from DT with
> status = "disabled".
>
> > Another biggest worry is, if I play here, it may break existing omap3/4
> > Functionality, especially may impact from PM perspective. So I believe, we
> > need to have something which adds/cleans-up things in stages.
>
> It seems that we need three stages: Something early for the timers only,
> initialize most things during driver probe, then late_initcall for the
> unclaimed devices.
>
Most likely yes, or it may even get into more stages.
At the current stage, I really think it would be really nice and beneficial
for driver developers from the community if they get Linux Boot from
linux-next/master branch. I have seen lot of community folks are struggling
with it and they are blocked because we do not have booting kernel on
BeagleBone.
They always end up patching kernel with HWMOD patch and submit the driver
patches. So request to consider this cleanup as sequential patch on top of
original HWMOD patch?
> > May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
> > now??
>
> Sorry I don't follow this part, care to explain a little more?
>
As per current implementation, we are using HWMOD information to fill the
platform_device->resources. Even if you pass "reg" and "interrupt" property
from DT, omap_device layer overwrites it with HWMOD data information.
So what I am trying to propose here is, avoid this overwrite and resources
(address and interrupt) should strictly gets used from DT blob. Since AM33xx
and OMAP5 devices are the new devices and supports DT boot only, we can
implement it easily for them.
Only issue her is, DMA resources, I was going through some of the old email
archives today, submitted by Benoit and later Jon, but I am still not sure
how to pass dma_channel to driver as a resource.
Below logic works for me, I have tested it on both BeagleBone and AM37xEVM -
omap_device_alloc ()
{
...
res_count = omap_device_count_resources(od);
if (res_count > pdev->num_resources) {
res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
if (!res)
goto oda_exit3;
if (pdev->num_resources && pdev->resource) {
omap_device_fill_dma_resources(od, res);
memcpy(&res[pdev->num_resources], pdev->resource,
sizeof(struct resource) * pdev->num_resources);
} else {
omap_device_fill_resources(od, res);
}
ret = platform_device_add_resources(pdev, res, res_count);
kfree(res);
}
...
}
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-08-17 9:51 ` Hiremath, Vaibhav
0 siblings, 0 replies; 28+ messages in thread
From: Hiremath, Vaibhav @ 2012-08-17 9:51 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
> > On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > > * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> > > >
> > > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> > > > core_init call, which will take DT resources and initialize accordingly.
> > >
> > > That's for the device reset/idle? We should not do that in hwmod code
> > > except in late_initcall for unclaimed devices as discussed earlier. We
> > > discussed setting up the reset function in the device specific headers
> > > so both device and hwmod code can call them as needed.
> >
> > May be I didn't understand your above statement, can you please elaborate
> > more on "device specific header file"?
>
> We should have the device drivers idle and reset the devices. But also
> hwmod may need to do that for the unclaimed devices for PM to work.
> As the driver may not be even compiled in, the driver specific reset and
> idle functions should be static inline functions in the device specific
> header file so hwmod code can still call those.
>
How about mapping the address of the devices?
Some more thoughts on the similar line on unclaimed devices -
As par of late_initcall(), traverse all the DTB nodes and for each node with
"state = disabled", we can do something like,
Late_initcall()
-> Traverse DTB nodes and check for "state = disabled"
-> Read the "ti,hwmod" entry and get offsets like, sys_config
and reset.
-> Map the base address
-> Enable the module/clock
-> Reset the device
-> Write to sysc register offset
-> Disable the module/clock
> > Just to highlight, its not only during late_initcall, the _enable and _idle
> > functions are getting executed as part of every runtime_pm_get\put_sync from
> > the driver.
>
> Right, so no need to initialize those until at driver probe time.
>
Agreed.
> > Are you saying as part of late_initcall, we should initialize " _mpu_rt_va"
> > of "struct omap_hwmod"???
>
> I guess either at driver probe for the claimed devices, or at late_initcall
> for the unclaimeded devices.
>
> > Also, as far unclaimed resources is concerned, somewhere you should have
> > base addr of the device maintained, right? Currently, hwmod is maintaining
> > this data and the execution goes something like,
> >
> > Core_initcall()
> > -> _setup()
> > -> _setup_reset()
> > -> _idle()
>
> For the DT only case also the unclaimed devices can from DT with
> status = "disabled".
>
> > Another biggest worry is, if I play here, it may break existing omap3/4
> > Functionality, especially may impact from PM perspective. So I believe, we
> > need to have something which adds/cleans-up things in stages.
>
> It seems that we need three stages: Something early for the timers only,
> initialize most things during driver probe, then late_initcall for the
> unclaimed devices.
>
Most likely yes, or it may even get into more stages.
At the current stage, I really think it would be really nice and beneficial
for driver developers from the community if they get Linux Boot from
linux-next/master branch. I have seen lot of community folks are struggling
with it and they are blocked because we do not have booting kernel on
BeagleBone.
They always end up patching kernel with HWMOD patch and submit the driver
patches. So request to consider this cleanup as sequential patch on top of
original HWMOD patch?
> > May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
> > now??
>
> Sorry I don't follow this part, care to explain a little more?
>
As per current implementation, we are using HWMOD information to fill the
platform_device->resources. Even if you pass "reg" and "interrupt" property
from DT, omap_device layer overwrites it with HWMOD data information.
So what I am trying to propose here is, avoid this overwrite and resources
(address and interrupt) should strictly gets used from DT blob. Since AM33xx
and OMAP5 devices are the new devices and supports DT boot only, we can
implement it easily for them.
Only issue her is, DMA resources, I was going through some of the old email
archives today, submitted by Benoit and later Jon, but I am still not sure
how to pass dma_channel to driver as a resource.
Below logic works for me, I have tested it on both BeagleBone and AM37xEVM -
omap_device_alloc ()
{
...
res_count = omap_device_count_resources(od);
if (res_count > pdev->num_resources) {
res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
if (!res)
goto oda_exit3;
if (pdev->num_resources && pdev->resource) {
omap_device_fill_dma_resources(od, res);
memcpy(&res[pdev->num_resources], pdev->resource,
sizeof(struct resource) * pdev->num_resources);
} else {
omap_device_fill_resources(od, res);
}
ret = platform_device_add_resources(pdev, res, res_count);
kfree(res);
}
...
}
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-08-17 9:51 ` Hiremath, Vaibhav
@ 2012-08-17 9:58 ` Tony Lindgren
-1 siblings, 0 replies; 28+ messages in thread
From: Tony Lindgren @ 2012-08-17 9:58 UTC (permalink / raw)
To: Hiremath, Vaibhav
Cc: Paul Walmsley, linux-omap, linux-arm-kernel, Mohammed, Afzal,
Bedia, Vaibhav, Cousson, Benoit, Hilman, Kevin, Nayak, Rajendra
* Hiremath, Vaibhav <hvaibhav@ti.com> [120817 02:51]:
> On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
> > * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
> > > On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > > > * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> > > > >
> > > > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> > > > > core_init call, which will take DT resources and initialize accordingly.
> > > >
> > > > That's for the device reset/idle? We should not do that in hwmod code
> > > > except in late_initcall for unclaimed devices as discussed earlier. We
> > > > discussed setting up the reset function in the device specific headers
> > > > so both device and hwmod code can call them as needed.
> > >
> > > May be I didn't understand your above statement, can you please elaborate
> > > more on "device specific header file"?
> >
> > We should have the device drivers idle and reset the devices. But also
> > hwmod may need to do that for the unclaimed devices for PM to work.
> > As the driver may not be even compiled in, the driver specific reset and
> > idle functions should be static inline functions in the device specific
> > header file so hwmod code can still call those.
> >
>
> How about mapping the address of the devices?
That should be done based on the iorange coming from DT during the driver
probe. The range in hwmod can be populated at that point too if needed.
> Some more thoughts on the similar line on unclaimed devices -
> As par of late_initcall(), traverse all the DTB nodes and for each node with
> "state = disabled", we can do something like,
>
> Late_initcall()
> -> Traverse DTB nodes and check for "state = disabled"
> -> Read the "ti,hwmod" entry and get offsets like, sys_config
> and reset.
> -> Map the base address
> -> Enable the module/clock
> -> Reset the device
> -> Write to sysc register offset
> -> Disable the module/clock
>
>
>
> > > Just to highlight, its not only during late_initcall, the _enable and _idle
> > > functions are getting executed as part of every runtime_pm_get\put_sync from
> > > the driver.
Heh, but the unclaimed devices do not have a driver :) So there's no runtime_pm
calls for the unclaimed devicdes.
> At the current stage, I really think it would be really nice and beneficial
> for driver developers from the community if they get Linux Boot from
> linux-next/master branch. I have seen lot of community folks are struggling
> with it and they are blocked because we do not have booting kernel on
> BeagleBone.
> They always end up patching kernel with HWMOD patch and submit the driver
> patches. So request to consider this cleanup as sequential patch on top of
> original HWMOD patch?
Yes I'm fine merging the data as is, just trying to figure out how to sort
out the issues for future.
> > > May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
> > > now??
> >
> > Sorry I don't follow this part, care to explain a little more?
> >
>
> As per current implementation, we are using HWMOD information to fill the
> platform_device->resources. Even if you pass "reg" and "interrupt" property
> from DT, omap_device layer overwrites it with HWMOD data information.
>
> So what I am trying to propose here is, avoid this overwrite and resources
> (address and interrupt) should strictly gets used from DT blob. Since AM33xx
> and OMAP5 devices are the new devices and supports DT boot only, we can
> implement it easily for them.
Yes I agree. And then we should also drop the data from hwmod when it's no
longer needed.
> Only issue her is, DMA resources, I was going through some of the old email
> archives today, submitted by Benoit and later Jon, but I am still not sure
> how to pass dma_channel to driver as a resource.
Hmm I thought that got merged already? Anyways, the iorange and interrupts
are standard resources that should exist in every device entry in .dts files.
Regards,
Tony
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-08-17 9:58 ` Tony Lindgren
0 siblings, 0 replies; 28+ messages in thread
From: Tony Lindgren @ 2012-08-17 9:58 UTC (permalink / raw)
To: linux-arm-kernel
* Hiremath, Vaibhav <hvaibhav@ti.com> [120817 02:51]:
> On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
> > * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
> > > On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > > > * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> > > > >
> > > > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> > > > > core_init call, which will take DT resources and initialize accordingly.
> > > >
> > > > That's for the device reset/idle? We should not do that in hwmod code
> > > > except in late_initcall for unclaimed devices as discussed earlier. We
> > > > discussed setting up the reset function in the device specific headers
> > > > so both device and hwmod code can call them as needed.
> > >
> > > May be I didn't understand your above statement, can you please elaborate
> > > more on "device specific header file"?
> >
> > We should have the device drivers idle and reset the devices. But also
> > hwmod may need to do that for the unclaimed devices for PM to work.
> > As the driver may not be even compiled in, the driver specific reset and
> > idle functions should be static inline functions in the device specific
> > header file so hwmod code can still call those.
> >
>
> How about mapping the address of the devices?
That should be done based on the iorange coming from DT during the driver
probe. The range in hwmod can be populated at that point too if needed.
> Some more thoughts on the similar line on unclaimed devices -
> As par of late_initcall(), traverse all the DTB nodes and for each node with
> "state = disabled", we can do something like,
>
> Late_initcall()
> -> Traverse DTB nodes and check for "state = disabled"
> -> Read the "ti,hwmod" entry and get offsets like, sys_config
> and reset.
> -> Map the base address
> -> Enable the module/clock
> -> Reset the device
> -> Write to sysc register offset
> -> Disable the module/clock
>
>
>
> > > Just to highlight, its not only during late_initcall, the _enable and _idle
> > > functions are getting executed as part of every runtime_pm_get\put_sync from
> > > the driver.
Heh, but the unclaimed devices do not have a driver :) So there's no runtime_pm
calls for the unclaimed devicdes.
> At the current stage, I really think it would be really nice and beneficial
> for driver developers from the community if they get Linux Boot from
> linux-next/master branch. I have seen lot of community folks are struggling
> with it and they are blocked because we do not have booting kernel on
> BeagleBone.
> They always end up patching kernel with HWMOD patch and submit the driver
> patches. So request to consider this cleanup as sequential patch on top of
> original HWMOD patch?
Yes I'm fine merging the data as is, just trying to figure out how to sort
out the issues for future.
> > > May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
> > > now??
> >
> > Sorry I don't follow this part, care to explain a little more?
> >
>
> As per current implementation, we are using HWMOD information to fill the
> platform_device->resources. Even if you pass "reg" and "interrupt" property
> from DT, omap_device layer overwrites it with HWMOD data information.
>
> So what I am trying to propose here is, avoid this overwrite and resources
> (address and interrupt) should strictly gets used from DT blob. Since AM33xx
> and OMAP5 devices are the new devices and supports DT boot only, we can
> implement it easily for them.
Yes I agree. And then we should also drop the data from hwmod when it's no
longer needed.
> Only issue her is, DMA resources, I was going through some of the old email
> archives today, submitted by Benoit and later Jon, but I am still not sure
> how to pass dma_channel to driver as a resource.
Hmm I thought that got merged already? Anyways, the iorange and interrupts
are standard resources that should exist in every device entry in .dts files.
Regards,
Tony
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-08-17 9:58 ` Tony Lindgren
@ 2012-08-17 10:09 ` Hiremath, Vaibhav
-1 siblings, 0 replies; 28+ messages in thread
From: Hiremath, Vaibhav @ 2012-08-17 10:09 UTC (permalink / raw)
To: Tony Lindgren
Cc: Paul Walmsley, linux-omap, linux-arm-kernel, Mohammed, Afzal,
Bedia, Vaibhav, Cousson, Benoit, Hilman, Kevin, Nayak, Rajendra
On Fri, Aug 17, 2012 at 15:28:51, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 02:51]:
> > On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
> > > * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
> > > > On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > > > > * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> > > > > >
> > > > > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> > > > > > core_init call, which will take DT resources and initialize accordingly.
> > > > >
> > > > > That's for the device reset/idle? We should not do that in hwmod code
> > > > > except in late_initcall for unclaimed devices as discussed earlier. We
> > > > > discussed setting up the reset function in the device specific headers
> > > > > so both device and hwmod code can call them as needed.
> > > >
> > > > May be I didn't understand your above statement, can you please elaborate
> > > > more on "device specific header file"?
> > >
> > > We should have the device drivers idle and reset the devices. But also
> > > hwmod may need to do that for the unclaimed devices for PM to work.
> > > As the driver may not be even compiled in, the driver specific reset and
> > > idle functions should be static inline functions in the device specific
> > > header file so hwmod code can still call those.
> > >
> >
> > How about mapping the address of the devices?
>
> That should be done based on the iorange coming from DT during the driver
> probe. The range in hwmod can be populated at that point too if needed.
>
There will not be any driver probe for unclaimed devices, right?
> > Some more thoughts on the similar line on unclaimed devices -
> > As par of late_initcall(), traverse all the DTB nodes and for each node with
> > "state = disabled", we can do something like,
> >
> > Late_initcall()
> > -> Traverse DTB nodes and check for "state = disabled"
> > -> Read the "ti,hwmod" entry and get offsets like, sys_config
> > and reset.
> > -> Map the base address
> > -> Enable the module/clock
> > -> Reset the device
> > -> Write to sysc register offset
> > -> Disable the module/clock
> >
> >
> >
> > > > Just to highlight, its not only during late_initcall, the _enable and _idle
> > > > functions are getting executed as part of every runtime_pm_get\put_sync from
> > > > the driver.
>
> Heh, but the unclaimed devices do not have a driver :) So there's no runtime_pm
> calls for the unclaimed devicdes.
>
I think you mixed two responses here, this was not part of my last response.
Just only read above code execution steps, I think they still make sense and
we may end up doing something similar.
> > At the current stage, I really think it would be really nice and beneficial
> > for driver developers from the community if they get Linux Boot from
> > linux-next/master branch. I have seen lot of community folks are struggling
> > with it and they are blocked because we do not have booting kernel on
> > BeagleBone.
> > They always end up patching kernel with HWMOD patch and submit the driver
> > patches. So request to consider this cleanup as sequential patch on top of
> > original HWMOD patch?
>
> Yes I'm fine merging the data as is, just trying to figure out how to sort
> out the issues for future.
>
Thanks a lot Tony.
Paul, Care to add it in your next pull request.
> > > > May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
> > > > now??
> > >
> > > Sorry I don't follow this part, care to explain a little more?
> > >
> >
> > As per current implementation, we are using HWMOD information to fill the
> > platform_device->resources. Even if you pass "reg" and "interrupt" property
> > from DT, omap_device layer overwrites it with HWMOD data information.
> >
> > So what I am trying to propose here is, avoid this overwrite and resources
> > (address and interrupt) should strictly gets used from DT blob. Since AM33xx
> > and OMAP5 devices are the new devices and supports DT boot only, we can
> > implement it easily for them.
>
> Yes I agree. And then we should also drop the data from hwmod when it's no
> longer needed.
>
Exactly, I will submit RFC for this.
> > Only issue her is, DMA resources, I was going through some of the old email
> > archives today, submitted by Benoit and later Jon, but I am still not sure
> > how to pass dma_channel to driver as a resource.
>
> Hmm I thought that got merged already?
No, atleast didn't find in 3.6-rc1.
> Anyways, the iorange and interrupts
> are standard resources that should exist in every device entry in .dts files.
>
Agreed, I am submitting patch for this as well.
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-08-17 10:09 ` Hiremath, Vaibhav
0 siblings, 0 replies; 28+ messages in thread
From: Hiremath, Vaibhav @ 2012-08-17 10:09 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Aug 17, 2012 at 15:28:51, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 02:51]:
> > On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
> > > * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
> > > > On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > > > > * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
> > > > > >
> > > > > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
> > > > > > core_init call, which will take DT resources and initialize accordingly.
> > > > >
> > > > > That's for the device reset/idle? We should not do that in hwmod code
> > > > > except in late_initcall for unclaimed devices as discussed earlier. We
> > > > > discussed setting up the reset function in the device specific headers
> > > > > so both device and hwmod code can call them as needed.
> > > >
> > > > May be I didn't understand your above statement, can you please elaborate
> > > > more on "device specific header file"?
> > >
> > > We should have the device drivers idle and reset the devices. But also
> > > hwmod may need to do that for the unclaimed devices for PM to work.
> > > As the driver may not be even compiled in, the driver specific reset and
> > > idle functions should be static inline functions in the device specific
> > > header file so hwmod code can still call those.
> > >
> >
> > How about mapping the address of the devices?
>
> That should be done based on the iorange coming from DT during the driver
> probe. The range in hwmod can be populated at that point too if needed.
>
There will not be any driver probe for unclaimed devices, right?
> > Some more thoughts on the similar line on unclaimed devices -
> > As par of late_initcall(), traverse all the DTB nodes and for each node with
> > "state = disabled", we can do something like,
> >
> > Late_initcall()
> > -> Traverse DTB nodes and check for "state = disabled"
> > -> Read the "ti,hwmod" entry and get offsets like, sys_config
> > and reset.
> > -> Map the base address
> > -> Enable the module/clock
> > -> Reset the device
> > -> Write to sysc register offset
> > -> Disable the module/clock
> >
> >
> >
> > > > Just to highlight, its not only during late_initcall, the _enable and _idle
> > > > functions are getting executed as part of every runtime_pm_get\put_sync from
> > > > the driver.
>
> Heh, but the unclaimed devices do not have a driver :) So there's no runtime_pm
> calls for the unclaimed devicdes.
>
I think you mixed two responses here, this was not part of my last response.
Just only read above code execution steps, I think they still make sense and
we may end up doing something similar.
> > At the current stage, I really think it would be really nice and beneficial
> > for driver developers from the community if they get Linux Boot from
> > linux-next/master branch. I have seen lot of community folks are struggling
> > with it and they are blocked because we do not have booting kernel on
> > BeagleBone.
> > They always end up patching kernel with HWMOD patch and submit the driver
> > patches. So request to consider this cleanup as sequential patch on top of
> > original HWMOD patch?
>
> Yes I'm fine merging the data as is, just trying to figure out how to sort
> out the issues for future.
>
Thanks a lot Tony.
Paul, Care to add it in your next pull request.
> > > > May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
> > > > now??
> > >
> > > Sorry I don't follow this part, care to explain a little more?
> > >
> >
> > As per current implementation, we are using HWMOD information to fill the
> > platform_device->resources. Even if you pass "reg" and "interrupt" property
> > from DT, omap_device layer overwrites it with HWMOD data information.
> >
> > So what I am trying to propose here is, avoid this overwrite and resources
> > (address and interrupt) should strictly gets used from DT blob. Since AM33xx
> > and OMAP5 devices are the new devices and supports DT boot only, we can
> > implement it easily for them.
>
> Yes I agree. And then we should also drop the data from hwmod when it's no
> longer needed.
>
Exactly, I will submit RFC for this.
> > Only issue her is, DMA resources, I was going through some of the old email
> > archives today, submitted by Benoit and later Jon, but I am still not sure
> > how to pass dma_channel to driver as a resource.
>
> Hmm I thought that got merged already?
No, atleast didn't find in 3.6-rc1.
> Anyways, the iorange and interrupts
> are standard resources that should exist in every device entry in .dts files.
>
Agreed, I am submitting patch for this as well.
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-08-17 9:58 ` Tony Lindgren
@ 2012-08-17 11:33 ` Benoit Cousson
-1 siblings, 0 replies; 28+ messages in thread
From: Benoit Cousson @ 2012-08-17 11:33 UTC (permalink / raw)
To: Tony Lindgren
Cc: Hiremath, Vaibhav, Paul Walmsley, linux-omap, linux-arm-kernel,
Mohammed, Afzal, Bedia, Vaibhav, Hilman, Kevin, Nayak, Rajendra
Hi Guys,
On 08/17/2012 11:58 AM, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 02:51]:
>> On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
>>> * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
>>>> On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
>>>>> * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
>>>>>>
>>>>>> Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
>>>>>> core_init call, which will take DT resources and initialize accordingly.
>>>>>
>>>>> That's for the device reset/idle? We should not do that in hwmod code
>>>>> except in late_initcall for unclaimed devices as discussed earlier. We
>>>>> discussed setting up the reset function in the device specific headers
>>>>> so both device and hwmod code can call them as needed.
>>>>
>>>> May be I didn't understand your above statement, can you please elaborate
>>>> more on "device specific header file"?
>>>
>>> We should have the device drivers idle and reset the devices. But also
>>> hwmod may need to do that for the unclaimed devices for PM to work.
>>> As the driver may not be even compiled in, the driver specific reset and
>>> idle functions should be static inline functions in the device specific
>>> header file so hwmod code can still call those.
>>>
>>
>> How about mapping the address of the devices?
>
> That should be done based on the iorange coming from DT during the driver
> probe. The range in hwmod can be populated at that point too if needed.
>
>> Some more thoughts on the similar line on unclaimed devices -
>> As par of late_initcall(), traverse all the DTB nodes and for each node with
>> "state = disabled", we can do something like,
>>
>> Late_initcall()
>> -> Traverse DTB nodes and check for "state = disabled"
>> -> Read the "ti,hwmod" entry and get offsets like, sys_config
>> and reset.
>> -> Map the base address
>> -> Enable the module/clock
>> -> Reset the device
>> -> Write to sysc register offset
>> -> Disable the module/clock
>>
>>
>>
>>>> Just to highlight, its not only during late_initcall, the _enable and _idle
>>>> functions are getting executed as part of every runtime_pm_get\put_sync from
>>>> the driver.
>
> Heh, but the unclaimed devices do not have a driver :) So there's no runtime_pm
> calls for the unclaimed devicdes.
>
>> At the current stage, I really think it would be really nice and beneficial
>> for driver developers from the community if they get Linux Boot from
>> linux-next/master branch. I have seen lot of community folks are struggling
>> with it and they are blocked because we do not have booting kernel on
>> BeagleBone.
>> They always end up patching kernel with HWMOD patch and submit the driver
>> patches. So request to consider this cleanup as sequential patch on top of
>> original HWMOD patch?
>
> Yes I'm fine merging the data as is, just trying to figure out how to sort
> out the issues for future.
>
>>>> May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
>>>> now??
>>>
>>> Sorry I don't follow this part, care to explain a little more?
>>>
>>
>> As per current implementation, we are using HWMOD information to fill the
>> platform_device->resources. Even if you pass "reg" and "interrupt" property
>> from DT, omap_device layer overwrites it with HWMOD data information.
>>
>> So what I am trying to propose here is, avoid this overwrite and resources
>> (address and interrupt) should strictly gets used from DT blob. Since AM33xx
>> and OMAP5 devices are the new devices and supports DT boot only, we can
>> implement it easily for them.
>
> Yes I agree. And then we should also drop the data from hwmod when it's no
> longer needed.
>
>> Only issue her is, DMA resources, I was going through some of the old email
>> archives today, submitted by Benoit and later Jon, but I am still not sure
>> how to pass dma_channel to driver as a resource.
>
> Hmm I thought that got merged already?
No, it is still under discussion. I don't even know why they are still
arguing, but there are still a lot of discussion on that thread.
> Anyways, the iorange and interrupts
> are standard resources that should exist in every device entry in .dts files.
Yeah, I wanted to avoid that to make things simpler. As soon as we have
the DMA we can switch easily to DT resource.
My other concern is that so far we still have to duplicate the io space
address with the way the hwmod is initializing the syscofig today.
So it will require some change in that part to make an effective use of
DT. So point is that if we start using that mechanism for DT boot, we
will still have to keep the legacy one for non DT boot.
Nothing is impossible, but that's still a lot of work before having
something useful.
The idea was to stop iterating the hwmods early and init the hwmod only
during device probe or late_initcall for the one that will not probe.
Again, easy with DT, less straighforward for non-DT boot.
Regards,
Benoit
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-08-17 11:33 ` Benoit Cousson
0 siblings, 0 replies; 28+ messages in thread
From: Benoit Cousson @ 2012-08-17 11:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi Guys,
On 08/17/2012 11:58 AM, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 02:51]:
>> On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
>>> * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
>>>> On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
>>>>> * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
>>>>>>
>>>>>> Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
>>>>>> core_init call, which will take DT resources and initialize accordingly.
>>>>>
>>>>> That's for the device reset/idle? We should not do that in hwmod code
>>>>> except in late_initcall for unclaimed devices as discussed earlier. We
>>>>> discussed setting up the reset function in the device specific headers
>>>>> so both device and hwmod code can call them as needed.
>>>>
>>>> May be I didn't understand your above statement, can you please elaborate
>>>> more on "device specific header file"?
>>>
>>> We should have the device drivers idle and reset the devices. But also
>>> hwmod may need to do that for the unclaimed devices for PM to work.
>>> As the driver may not be even compiled in, the driver specific reset and
>>> idle functions should be static inline functions in the device specific
>>> header file so hwmod code can still call those.
>>>
>>
>> How about mapping the address of the devices?
>
> That should be done based on the iorange coming from DT during the driver
> probe. The range in hwmod can be populated at that point too if needed.
>
>> Some more thoughts on the similar line on unclaimed devices -
>> As par of late_initcall(), traverse all the DTB nodes and for each node with
>> "state = disabled", we can do something like,
>>
>> Late_initcall()
>> -> Traverse DTB nodes and check for "state = disabled"
>> -> Read the "ti,hwmod" entry and get offsets like, sys_config
>> and reset.
>> -> Map the base address
>> -> Enable the module/clock
>> -> Reset the device
>> -> Write to sysc register offset
>> -> Disable the module/clock
>>
>>
>>
>>>> Just to highlight, its not only during late_initcall, the _enable and _idle
>>>> functions are getting executed as part of every runtime_pm_get\put_sync from
>>>> the driver.
>
> Heh, but the unclaimed devices do not have a driver :) So there's no runtime_pm
> calls for the unclaimed devicdes.
>
>> At the current stage, I really think it would be really nice and beneficial
>> for driver developers from the community if they get Linux Boot from
>> linux-next/master branch. I have seen lot of community folks are struggling
>> with it and they are blocked because we do not have booting kernel on
>> BeagleBone.
>> They always end up patching kernel with HWMOD patch and submit the driver
>> patches. So request to consider this cleanup as sequential patch on top of
>> original HWMOD patch?
>
> Yes I'm fine merging the data as is, just trying to figure out how to sort
> out the issues for future.
>
>>>> May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
>>>> now??
>>>
>>> Sorry I don't follow this part, care to explain a little more?
>>>
>>
>> As per current implementation, we are using HWMOD information to fill the
>> platform_device->resources. Even if you pass "reg" and "interrupt" property
>> from DT, omap_device layer overwrites it with HWMOD data information.
>>
>> So what I am trying to propose here is, avoid this overwrite and resources
>> (address and interrupt) should strictly gets used from DT blob. Since AM33xx
>> and OMAP5 devices are the new devices and supports DT boot only, we can
>> implement it easily for them.
>
> Yes I agree. And then we should also drop the data from hwmod when it's no
> longer needed.
>
>> Only issue her is, DMA resources, I was going through some of the old email
>> archives today, submitted by Benoit and later Jon, but I am still not sure
>> how to pass dma_channel to driver as a resource.
>
> Hmm I thought that got merged already?
No, it is still under discussion. I don't even know why they are still
arguing, but there are still a lot of discussion on that thread.
> Anyways, the iorange and interrupts
> are standard resources that should exist in every device entry in .dts files.
Yeah, I wanted to avoid that to make things simpler. As soon as we have
the DMA we can switch easily to DT resource.
My other concern is that so far we still have to duplicate the io space
address with the way the hwmod is initializing the syscofig today.
So it will require some change in that part to make an effective use of
DT. So point is that if we start using that mechanism for DT boot, we
will still have to keep the legacy one for non DT boot.
Nothing is impossible, but that's still a lot of work before having
something useful.
The idea was to stop iterating the hwmods early and init the hwmod only
during device probe or late_initcall for the one that will not probe.
Again, easy with DT, less straighforward for non-DT boot.
Regards,
Benoit
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
2012-08-17 9:51 ` Hiremath, Vaibhav
@ 2012-08-17 11:43 ` Benoit Cousson
-1 siblings, 0 replies; 28+ messages in thread
From: Benoit Cousson @ 2012-08-17 11:43 UTC (permalink / raw)
To: Hiremath, Vaibhav
Cc: Tony Lindgren, Paul Walmsley, linux-omap, linux-arm-kernel,
Mohammed, Afzal, Bedia, Vaibhav, Hilman, Kevin, Nayak, Rajendra
Hi Vaibhav,
On 08/17/2012 11:51 AM, Hiremath, Vaibhav wrote:
> On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
>> * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
>>> On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
>>>> * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
>>>>>
>>>>> Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
>>>>> core_init call, which will take DT resources and initialize accordingly.
>>>>
>>>> That's for the device reset/idle? We should not do that in hwmod code
>>>> except in late_initcall for unclaimed devices as discussed earlier. We
>>>> discussed setting up the reset function in the device specific headers
>>>> so both device and hwmod code can call them as needed.
>>>
>>> May be I didn't understand your above statement, can you please elaborate
>>> more on "device specific header file"?
>>
>> We should have the device drivers idle and reset the devices. But also
>> hwmod may need to do that for the unclaimed devices for PM to work.
>> As the driver may not be even compiled in, the driver specific reset and
>> idle functions should be static inline functions in the device specific
>> header file so hwmod code can still call those.
>>
>
> How about mapping the address of the devices?
>
> Some more thoughts on the similar line on unclaimed devices -
> As par of late_initcall(), traverse all the DTB nodes and for each node with
> "state = disabled", we can do something like,
Yes, in fact we should duplicate the same mechanism that will be used to
init a regular device during probe.
> Late_initcall()
> -> Traverse DTB nodes and check for "state = disabled"
> -> Read the "ti,hwmod" entry and get offsets like, sys_config
> and reset.
> -> Map the base address
> -> Enable the module/clock
> -> Reset the device
> -> Write to sysc register offset
> -> Disable the module/clock
>
>
>
>>> Just to highlight, its not only during late_initcall, the _enable and _idle
>>> functions are getting executed as part of every runtime_pm_get\put_sync from
>>> the driver.
>>
>> Right, so no need to initialize those until at driver probe time.
>>
>
> Agreed.
>
>>> Are you saying as part of late_initcall, we should initialize " _mpu_rt_va"
>>> of "struct omap_hwmod"???
>>
>> I guess either at driver probe for the claimed devices, or at late_initcall
>> for the unclaimeded devices.
>>
>>> Also, as far unclaimed resources is concerned, somewhere you should have
>>> base addr of the device maintained, right? Currently, hwmod is maintaining
>>> this data and the execution goes something like,
>>>
>>> Core_initcall()
>>> -> _setup()
>>> -> _setup_reset()
>>> -> _idle()
>>
>> For the DT only case also the unclaimed devices can from DT with
>> status = "disabled".
>>
>>> Another biggest worry is, if I play here, it may break existing omap3/4
>>> Functionality, especially may impact from PM perspective. So I believe, we
>>> need to have something which adds/cleans-up things in stages.
>>
>> It seems that we need three stages: Something early for the timers only,
>> initialize most things during driver probe, then late_initcall for the
>> unclaimed devices.
>>
>
> Most likely yes, or it may even get into more stages.
>
> At the current stage, I really think it would be really nice and beneficial
> for driver developers from the community if they get Linux Boot from
> linux-next/master branch. I have seen lot of community folks are struggling
> with it and they are blocked because we do not have booting kernel on
> BeagleBone.
> They always end up patching kernel with HWMOD patch and submit the driver
> patches. So request to consider this cleanup as sequential patch on top of
> original HWMOD patch?
>
>
>>> May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
>>> now??
>>
>> Sorry I don't follow this part, care to explain a little more?
>>
>
> As per current implementation, we are using HWMOD information to fill the
> platform_device->resources. Even if you pass "reg" and "interrupt" property
> from DT, omap_device layer overwrites it with HWMOD data information.
>
> So what I am trying to propose here is, avoid this overwrite and resources
> (address and interrupt) should strictly gets used from DT blob. Since AM33xx
> and OMAP5 devices are the new devices and supports DT boot only, we can
> implement it easily for them.
Well, the point is that that mechanism is still common to OMAP2+
devices, so the tricky part is that a legacy mode will still be needed.
> Only issue her is, DMA resources, I was going through some of the old email
> archives today, submitted by Benoit and later Jon, but I am still not sure
> how to pass dma_channel to driver as a resource.
There is no way currently :-(.
> Below logic works for me, I have tested it on both BeagleBone and AM37xEVM -
>
> omap_device_alloc ()
> {
> ...
>
> res_count = omap_device_count_resources(od);
> if (res_count > pdev->num_resources) {
> res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
> if (!res)
> goto oda_exit3;
>
> if (pdev->num_resources && pdev->resource) {
> omap_device_fill_dma_resources(od, res);
> memcpy(&res[pdev->num_resources], pdev->resource,
> sizeof(struct resource) * pdev->num_resources);
> } else {
> omap_device_fill_resources(od, res);
> }
>
> ret = platform_device_add_resources(pdev, res, res_count);
> kfree(res);
> }
>
> ...
> }
Yeah, or we can potentially define a custom ti DMA binding for the time
being. In fact Tegra and Exynios are currently using some custom DMA
binding. I wanted to avoid that with a generic binding RFC, but as
already said, that series is not progressing really fast whereas our
need for SDMA/EDMA is pretty simple. Well at least for SDMA.
Anyway, your approach is the proper one to me and something we've been
discussing for a while with Tony. I've just never had the time to
progress on that. I'll be more than happy to support you on OMAP4+
devices to validate that code if you can work on it.
Thanks,
Benoit
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
@ 2012-08-17 11:43 ` Benoit Cousson
0 siblings, 0 replies; 28+ messages in thread
From: Benoit Cousson @ 2012-08-17 11:43 UTC (permalink / raw)
To: linux-arm-kernel
Hi Vaibhav,
On 08/17/2012 11:51 AM, Hiremath, Vaibhav wrote:
> On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
>> * Hiremath, Vaibhav <hvaibhav@ti.com> [120817 01:22]:
>>> On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
>>>> * Hiremath, Vaibhav <hvaibhav@ti.com> [120815 02:11]:
>>>>>
>>>>> Somehow we have to have some mechanism to initialize " _mpu_rt_va" before
>>>>> core_init call, which will take DT resources and initialize accordingly.
>>>>
>>>> That's for the device reset/idle? We should not do that in hwmod code
>>>> except in late_initcall for unclaimed devices as discussed earlier. We
>>>> discussed setting up the reset function in the device specific headers
>>>> so both device and hwmod code can call them as needed.
>>>
>>> May be I didn't understand your above statement, can you please elaborate
>>> more on "device specific header file"?
>>
>> We should have the device drivers idle and reset the devices. But also
>> hwmod may need to do that for the unclaimed devices for PM to work.
>> As the driver may not be even compiled in, the driver specific reset and
>> idle functions should be static inline functions in the device specific
>> header file so hwmod code can still call those.
>>
>
> How about mapping the address of the devices?
>
> Some more thoughts on the similar line on unclaimed devices -
> As par of late_initcall(), traverse all the DTB nodes and for each node with
> "state = disabled", we can do something like,
Yes, in fact we should duplicate the same mechanism that will be used to
init a regular device during probe.
> Late_initcall()
> -> Traverse DTB nodes and check for "state = disabled"
> -> Read the "ti,hwmod" entry and get offsets like, sys_config
> and reset.
> -> Map the base address
> -> Enable the module/clock
> -> Reset the device
> -> Write to sysc register offset
> -> Disable the module/clock
>
>
>
>>> Just to highlight, its not only during late_initcall, the _enable and _idle
>>> functions are getting executed as part of every runtime_pm_get\put_sync from
>>> the driver.
>>
>> Right, so no need to initialize those until at driver probe time.
>>
>
> Agreed.
>
>>> Are you saying as part of late_initcall, we should initialize " _mpu_rt_va"
>>> of "struct omap_hwmod"???
>>
>> I guess either at driver probe for the claimed devices, or at late_initcall
>> for the unclaimeded devices.
>>
>>> Also, as far unclaimed resources is concerned, somewhere you should have
>>> base addr of the device maintained, right? Currently, hwmod is maintaining
>>> this data and the execution goes something like,
>>>
>>> Core_initcall()
>>> -> _setup()
>>> -> _setup_reset()
>>> -> _idle()
>>
>> For the DT only case also the unclaimed devices can from DT with
>> status = "disabled".
>>
>>> Another biggest worry is, if I play here, it may break existing omap3/4
>>> Functionality, especially may impact from PM perspective. So I believe, we
>>> need to have something which adds/cleans-up things in stages.
>>
>> It seems that we need three stages: Something early for the timers only,
>> initialize most things during driver probe, then late_initcall for the
>> unclaimed devices.
>>
>
> Most likely yes, or it may even get into more stages.
>
> At the current stage, I really think it would be really nice and beneficial
> for driver developers from the community if they get Linux Boot from
> linux-next/master branch. I have seen lot of community folks are struggling
> with it and they are blocked because we do not have booting kernel on
> BeagleBone.
> They always end up patching kernel with HWMOD patch and submit the driver
> patches. So request to consider this cleanup as sequential patch on top of
> original HWMOD patch?
>
>
>>> May be get rid of resource overwriting for AM33xx and OMAP5 alone as of
>>> now??
>>
>> Sorry I don't follow this part, care to explain a little more?
>>
>
> As per current implementation, we are using HWMOD information to fill the
> platform_device->resources. Even if you pass "reg" and "interrupt" property
> from DT, omap_device layer overwrites it with HWMOD data information.
>
> So what I am trying to propose here is, avoid this overwrite and resources
> (address and interrupt) should strictly gets used from DT blob. Since AM33xx
> and OMAP5 devices are the new devices and supports DT boot only, we can
> implement it easily for them.
Well, the point is that that mechanism is still common to OMAP2+
devices, so the tricky part is that a legacy mode will still be needed.
> Only issue her is, DMA resources, I was going through some of the old email
> archives today, submitted by Benoit and later Jon, but I am still not sure
> how to pass dma_channel to driver as a resource.
There is no way currently :-(.
> Below logic works for me, I have tested it on both BeagleBone and AM37xEVM -
>
> omap_device_alloc ()
> {
> ...
>
> res_count = omap_device_count_resources(od);
> if (res_count > pdev->num_resources) {
> res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
> if (!res)
> goto oda_exit3;
>
> if (pdev->num_resources && pdev->resource) {
> omap_device_fill_dma_resources(od, res);
> memcpy(&res[pdev->num_resources], pdev->resource,
> sizeof(struct resource) * pdev->num_resources);
> } else {
> omap_device_fill_resources(od, res);
> }
>
> ret = platform_device_add_resources(pdev, res, res_count);
> kfree(res);
> }
>
> ...
> }
Yeah, or we can potentially define a custom ti DMA binding for the time
being. In fact Tegra and Exynios are currently using some custom DMA
binding. I wanted to avoid that with a generic binding RFC, but as
already said, that series is not progressing really fast whereas our
need for SDMA/EDMA is pretty simple. Well at least for SDMA.
Anyway, your approach is the proper one to me and something we've been
discussing for a while with Tony. I've just never had the time to
progress on that. I'll be more than happy to support you on OMAP4+
devices to validate that code if you can work on it.
Thanks,
Benoit
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2012-08-17 11:43 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-07-25 11:07 [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data Vaibhav Hiremath
2012-07-25 11:07 ` Vaibhav Hiremath
2012-07-25 20:41 ` Paul Walmsley
2012-07-25 20:41 ` Paul Walmsley
2012-07-26 20:02 ` Paul Walmsley
2012-07-26 20:02 ` Paul Walmsley
2012-07-27 8:36 ` Hiremath, Vaibhav
2012-07-27 8:36 ` Hiremath, Vaibhav
2012-08-14 8:29 ` Tony Lindgren
2012-08-14 8:29 ` Tony Lindgren
2012-08-15 9:10 ` Hiremath, Vaibhav
2012-08-15 9:10 ` Hiremath, Vaibhav
2012-08-17 7:49 ` Tony Lindgren
2012-08-17 7:49 ` Tony Lindgren
2012-08-17 8:22 ` Hiremath, Vaibhav
2012-08-17 8:22 ` Hiremath, Vaibhav
2012-08-17 8:40 ` Tony Lindgren
2012-08-17 8:40 ` Tony Lindgren
2012-08-17 9:51 ` Hiremath, Vaibhav
2012-08-17 9:51 ` Hiremath, Vaibhav
2012-08-17 9:58 ` Tony Lindgren
2012-08-17 9:58 ` Tony Lindgren
2012-08-17 10:09 ` Hiremath, Vaibhav
2012-08-17 10:09 ` Hiremath, Vaibhav
2012-08-17 11:33 ` Benoit Cousson
2012-08-17 11:33 ` Benoit Cousson
2012-08-17 11:43 ` Benoit Cousson
2012-08-17 11:43 ` Benoit Cousson
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.