* [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2
@ 2012-09-05 20:41 Eduardo Habkost
2012-09-05 20:41 ` [Qemu-devel] [PATCH 1/7] target-i386: Fold -cpu ?cpuid, ?model output into -cpu help, drop ?dump Eduardo Habkost
` (8 more replies)
0 siblings, 9 replies; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-05 20:41 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andreas Färber, Anthony Liguori, Igor Mammedov
Hi,
This is a small queue of patches that I consider "ready to go", that didn't
enter QEMU 1.2.
Eduardo Habkost (5):
i386: add missing CPUID_* constants
move CPU models from cpus-x86_64.conf to C
eliminate cpus-x86_64.conf file
x86_cpudef_setup: coding style change
i386: kill cpudef config section support
Peter Maydell (2):
target-i386: Fold -cpu ?cpuid, ?model output into -cpu help, drop
?dump
Drop cpu_list_id macro
Makefile | 1 -
arch_init.c | 1 -
cpus.c | 6 +-
linux-user/main.c | 6 +-
sysconfigs/target/cpus-x86_64.conf | 128 ------------
target-i386/cpu.c | 399 ++++++++++++++++++++++---------------
target-i386/cpu.h | 26 ++-
7 files changed, 269 insertions(+), 298 deletions(-)
delete mode 100644 sysconfigs/target/cpus-x86_64.conf
--
1.7.11.4
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 1/7] target-i386: Fold -cpu ?cpuid, ?model output into -cpu help, drop ?dump
2012-09-05 20:41 [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Eduardo Habkost
@ 2012-09-05 20:41 ` Eduardo Habkost
2012-09-10 9:40 ` Igor Mammedov
2012-09-05 20:41 ` [Qemu-devel] [PATCH 2/7] Drop cpu_list_id macro Eduardo Habkost
` (7 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-05 20:41 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andreas Färber, Anthony Liguori, Igor Mammedov
From: Peter Maydell <peter.maydell@linaro.org>
Commit c8057f95 (accidentally) disabled the ability to pass
option strings starting with '?' to the target-specific
cpu_list function, so the target-i386 specific "-cpu ?dump",
"-cpu ?cpuid" and "-cpu ?model" stopped working.
Since these options are undocumented and not used by libvirt,
simply drop them completely rather than reinstating them
with new style syntax. Instead, we fold the ?model and ?cpuid
output into the output of the plain "-cpu help" output. The
detailed output produced by ?dump is dropped.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/cpu.c | 64 ++++++++++---------------------------------------------
1 file changed, 11 insertions(+), 53 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 423e009..5c98064 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1073,70 +1073,28 @@ static void listflags(char *buf, int bufsize, uint32_t fbits,
}
}
-/* generate CPU information:
- * -? list model names
- * -?model list model names/IDs
- * -?dump output all model (x86_def_t) data
- * -?cpuid list all recognized cpuid flag names
- */
+/* generate CPU information */
void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
{
- unsigned char model = !strcmp("?model", optarg);
- unsigned char dump = !strcmp("?dump", optarg);
- unsigned char cpuid = !strcmp("?cpuid", optarg);
x86_def_t *def;
char buf[256];
- if (cpuid) {
- (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
- listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
- (*cpu_fprintf)(f, " f_edx: %s\n", buf);
- listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
- (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
- listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
- (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
- listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
- (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
- return;
- }
for (def = x86_defs; def; def = def->next) {
snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
- if (model || dump) {
- (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
- } else {
- (*cpu_fprintf)(f, "x86 %16s\n", buf);
- }
- if (dump) {
- memcpy(buf, &def->vendor1, sizeof (def->vendor1));
- memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
- memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
- buf[12] = '\0';
- (*cpu_fprintf)(f,
- " family %d model %d stepping %d level %d xlevel 0x%x"
- " vendor \"%s\"\n",
- def->family, def->model, def->stepping, def->level,
- def->xlevel, buf);
- listflags(buf, sizeof (buf), def->features, feature_name, 0);
- (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
- buf);
- listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
- 0);
- (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
- buf);
- listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
- 0);
- (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
- def->ext2_features, buf);
- listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
- 0);
- (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
- def->ext3_features, buf);
- (*cpu_fprintf)(f, "\n");
- }
+ (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
}
if (kvm_enabled()) {
(*cpu_fprintf)(f, "x86 %16s\n", "[host]");
}
+ (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
+ listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
+ (*cpu_fprintf)(f, " f_edx: %s\n", buf);
+ listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
+ (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
+ listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
+ (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
+ listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
+ (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
}
CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 2/7] Drop cpu_list_id macro
2012-09-05 20:41 [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Eduardo Habkost
2012-09-05 20:41 ` [Qemu-devel] [PATCH 1/7] target-i386: Fold -cpu ?cpuid, ?model output into -cpu help, drop ?dump Eduardo Habkost
@ 2012-09-05 20:41 ` Eduardo Habkost
2012-09-10 9:46 ` Igor Mammedov
2012-09-05 20:41 ` [Qemu-devel] [PATCH 3/7] i386: add missing CPUID_* constants Eduardo Habkost
` (6 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-05 20:41 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andreas Färber, Anthony Liguori, Igor Mammedov
From: Peter Maydell <peter.maydell@linaro.org>
Since the only user of the extended cpu_list_id() format
was the x86 ?model/?dump/?cpuid output, we can drop it
completely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
---
cpus.c | 6 ++----
linux-user/main.c | 6 ++----
target-i386/cpu.c | 4 ++--
target-i386/cpu.h | 4 ++--
4 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/cpus.c b/cpus.c
index e476a3c..4b726ef 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1192,10 +1192,8 @@ void set_cpu_log_filename(const char *optarg)
void list_cpus(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
{
/* XXX: implement xxx_cpu_list for targets that still miss it */
-#if defined(cpu_list_id)
- cpu_list_id(f, cpu_fprintf, optarg);
-#elif defined(cpu_list)
- cpu_list(f, cpu_fprintf); /* deprecated */
+#if defined(cpu_list)
+ cpu_list(f, cpu_fprintf);
#endif
}
diff --git a/linux-user/main.c b/linux-user/main.c
index 1a1c661..6e66e5d 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3143,10 +3143,8 @@ static void handle_arg_cpu(const char *arg)
cpu_model = strdup(arg);
if (cpu_model == NULL || is_help_option(cpu_model)) {
/* XXX: implement xxx_cpu_list for targets that still miss it */
-#if defined(cpu_list_id)
- cpu_list_id(stdout, &fprintf, "");
-#elif defined(cpu_list)
- cpu_list(stdout, &fprintf); /* deprecated */
+#if defined(cpu_list)
+ cpu_list(stdout, &fprintf);
#endif
exit(1);
}
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 5c98064..d2af0ff 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1073,8 +1073,8 @@ static void listflags(char *buf, int bufsize, uint32_t fbits,
}
}
-/* generate CPU information */
-void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
+/* generate CPU information. */
+void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
x86_def_t *def;
char buf[256];
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 0677502..49e0259 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -792,7 +792,7 @@ typedef struct CPUX86State {
X86CPU *cpu_x86_init(const char *cpu_model);
int cpu_x86_exec(CPUX86State *s);
-void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char *optarg);
+void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void x86_cpudef_setup(void);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
@@ -976,7 +976,7 @@ static inline CPUX86State *cpu_init(const char *cpu_model)
#define cpu_exec cpu_x86_exec
#define cpu_gen_code cpu_x86_gen_code
#define cpu_signal_handler cpu_x86_signal_handler
-#define cpu_list_id x86_cpu_list
+#define cpu_list x86_cpu_list
#define cpudef_setup x86_cpudef_setup
#define CPU_SAVE_VERSION 12
--
1.7.11.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 3/7] i386: add missing CPUID_* constants
2012-09-05 20:41 [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Eduardo Habkost
2012-09-05 20:41 ` [Qemu-devel] [PATCH 1/7] target-i386: Fold -cpu ?cpuid, ?model output into -cpu help, drop ?dump Eduardo Habkost
2012-09-05 20:41 ` [Qemu-devel] [PATCH 2/7] Drop cpu_list_id macro Eduardo Habkost
@ 2012-09-05 20:41 ` Eduardo Habkost
2012-09-10 9:57 ` Igor Mammedov
2012-09-05 20:41 ` [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C Eduardo Habkost
` (5 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-05 20:41 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andreas Färber, Anthony Liguori, Igor Mammedov
Those constants will be used by new CPU model definitions.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/cpu.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 49e0259..d7ea2f9 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -382,6 +382,7 @@
#define CPUID_PBE (1 << 31)
#define CPUID_EXT_SSE3 (1 << 0)
+#define CPUID_EXT_PCLMULQDQ (1 << 1)
#define CPUID_EXT_DTES64 (1 << 2)
#define CPUID_EXT_MONITOR (1 << 3)
#define CPUID_EXT_DSCPL (1 << 4)
@@ -401,14 +402,33 @@
#define CPUID_EXT_MOVBE (1 << 22)
#define CPUID_EXT_POPCNT (1 << 23)
#define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24)
+#define CPUID_EXT_AES (1 << 25)
#define CPUID_EXT_XSAVE (1 << 26)
#define CPUID_EXT_OSXSAVE (1 << 27)
+#define CPUID_EXT_AVX (1 << 28)
#define CPUID_EXT_HYPERVISOR (1 << 31)
+#define CPUID_EXT2_FPU (1 << 0)
+#define CPUID_EXT2_DE (1 << 2)
+#define CPUID_EXT2_PSE (1 << 3)
+#define CPUID_EXT2_TSC (1 << 4)
+#define CPUID_EXT2_MSR (1 << 5)
+#define CPUID_EXT2_PAE (1 << 6)
+#define CPUID_EXT2_MCE (1 << 7)
+#define CPUID_EXT2_CX8 (1 << 8)
+#define CPUID_EXT2_APIC (1 << 9)
#define CPUID_EXT2_SYSCALL (1 << 11)
+#define CPUID_EXT2_MTRR (1 << 12)
+#define CPUID_EXT2_PGE (1 << 13)
+#define CPUID_EXT2_MCA (1 << 14)
+#define CPUID_EXT2_CMOV (1 << 15)
+#define CPUID_EXT2_PAT (1 << 16)
+#define CPUID_EXT2_PSE36 (1 << 17)
#define CPUID_EXT2_MP (1 << 19)
#define CPUID_EXT2_NX (1 << 20)
#define CPUID_EXT2_MMXEXT (1 << 22)
+#define CPUID_EXT2_MMX (1 << 23)
+#define CPUID_EXT2_FXSR (1 << 24)
#define CPUID_EXT2_FFXSR (1 << 25)
#define CPUID_EXT2_PDPE1GB (1 << 26)
#define CPUID_EXT2_RDTSCP (1 << 27)
@@ -427,7 +447,9 @@
#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
#define CPUID_EXT3_OSVW (1 << 9)
#define CPUID_EXT3_IBS (1 << 10)
+#define CPUID_EXT3_XOP (1 << 11)
#define CPUID_EXT3_SKINIT (1 << 12)
+#define CPUID_EXT3_FMA4 (1 << 16)
#define CPUID_SVM_NPT (1 << 0)
#define CPUID_SVM_LBRV (1 << 1)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-05 20:41 [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Eduardo Habkost
` (2 preceding siblings ...)
2012-09-05 20:41 ` [Qemu-devel] [PATCH 3/7] i386: add missing CPUID_* constants Eduardo Habkost
@ 2012-09-05 20:41 ` Eduardo Habkost
2012-09-10 12:18 ` Igor Mammedov
2012-09-10 13:40 ` Igor Mammedov
2012-09-05 20:41 ` [Qemu-devel] [PATCH 5/7] eliminate cpus-x86_64.conf file Eduardo Habkost
` (4 subsequent siblings)
8 siblings, 2 replies; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-05 20:41 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andreas Färber, Anthony Liguori, Igor Mammedov
Those models are maintained by QEMU and may require compatibility code
to be added when making some changes. Keeping the data in the C source
code should make it simpler to handle those details.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
sysconfigs/target/cpus-x86_64.conf | 129 +---------------------
target-i386/cpu.c | 219 +++++++++++++++++++++++++++++++++++++
2 files changed, 220 insertions(+), 128 deletions(-)
diff --git a/sysconfigs/target/cpus-x86_64.conf b/sysconfigs/target/cpus-x86_64.conf
index cee0ea9..3902189 100644
--- a/sysconfigs/target/cpus-x86_64.conf
+++ b/sysconfigs/target/cpus-x86_64.conf
@@ -1,128 +1 @@
-# x86 CPU MODELS
-
-[cpudef]
- name = "Conroe"
- level = "2"
- vendor = "GenuineIntel"
- family = "6"
- model = "2"
- stepping = "3"
- feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
- feature_ecx = "ssse3 sse3"
- extfeature_edx = "i64 xd syscall"
- extfeature_ecx = "lahf_lm"
- xlevel = "0x8000000A"
- model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
-
-[cpudef]
- name = "Penryn"
- level = "2"
- vendor = "GenuineIntel"
- family = "6"
- model = "2"
- stepping = "3"
- feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
- feature_ecx = "sse4.1 cx16 ssse3 sse3"
- extfeature_edx = "i64 xd syscall"
- extfeature_ecx = "lahf_lm"
- xlevel = "0x8000000A"
- model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
-
-[cpudef]
- name = "Nehalem"
- level = "2"
- vendor = "GenuineIntel"
- family = "6"
- model = "2"
- stepping = "3"
- feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
- feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
- extfeature_edx = "i64 syscall xd"
- extfeature_ecx = "lahf_lm"
- xlevel = "0x8000000A"
- model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
-
-[cpudef]
- name = "Westmere"
- level = "11"
- vendor = "GenuineIntel"
- family = "6"
- model = "44"
- stepping = "1"
- feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
- feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
- extfeature_edx = "i64 syscall xd"
- extfeature_ecx = "lahf_lm"
- xlevel = "0x8000000A"
- model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
-
-[cpudef]
- name = "SandyBridge"
- level = "0xd"
- vendor = "GenuineIntel"
- family = "6"
- model = "42"
- stepping = "1"
- feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
- feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3"
- extfeature_edx = "i64 rdtscp nx syscall "
- extfeature_ecx = "lahf_lm"
- xlevel = "0x8000000A"
- model_id = "Intel Xeon E312xx (Sandy Bridge)"
-
-[cpudef]
- name = "Opteron_G1"
- level = "5"
- vendor = "AuthenticAMD"
- family = "15"
- model = "6"
- stepping = "1"
- feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
- feature_ecx = "sse3"
- extfeature_edx = "lm fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
- extfeature_ecx = " "
- xlevel = "0x80000008"
- model_id = "AMD Opteron 240 (Gen 1 Class Opteron)"
-
-[cpudef]
- name = "Opteron_G2"
- level = "5"
- vendor = "AuthenticAMD"
- family = "15"
- model = "6"
- stepping = "1"
- feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
- feature_ecx = "cx16 sse3"
- extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
- extfeature_ecx = "svm lahf_lm"
- xlevel = "0x80000008"
- model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)"
-
-[cpudef]
- name = "Opteron_G3"
- level = "5"
- vendor = "AuthenticAMD"
- family = "15"
- model = "6"
- stepping = "1"
- feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
- feature_ecx = "popcnt cx16 monitor sse3"
- extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
- extfeature_ecx = "misalignsse sse4a abm svm lahf_lm"
- xlevel = "0x80000008"
- model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)"
-
-[cpudef]
- name = "Opteron_G4"
- level = "0xd"
- vendor = "AuthenticAMD"
- family = "21"
- model = "1"
- stepping = "2"
- feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
- feature_ecx = "avx xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3"
- extfeature_edx = "lm rdtscp pdpe1gb fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
- extfeature_ecx = " fma4 xop 3dnowprefetch misalignsse sse4a abm svm lahf_lm"
- xlevel = "0x8000001A"
- model_id = "AMD Opteron 62xx class CPU"
-
+# The CPU models from this file are now built-in in the QEMU source code
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index d2af0ff..73302d8 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -490,6 +490,225 @@ static x86_def_t builtin_x86_defs[] = {
.xlevel = 0x8000000A,
.model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
},
+ {
+ .name = "Conroe",
+ .level = 2,
+ .vendor1 = CPUID_VENDOR_INTEL_1,
+ .vendor2 = CPUID_VENDOR_INTEL_2,
+ .vendor3 = CPUID_VENDOR_INTEL_3,
+ .family = 6,
+ .model = 2,
+ .stepping = 3,
+ .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+ .ext3_features = CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
+ },
+ {
+ .name = "Penryn",
+ .level = 2,
+ .vendor1 = CPUID_VENDOR_INTEL_1,
+ .vendor2 = CPUID_VENDOR_INTEL_2,
+ .vendor3 = CPUID_VENDOR_INTEL_3,
+ .family = 6,
+ .model = 2,
+ .stepping = 3,
+ .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+ CPUID_EXT_SSE3,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+ .ext3_features = CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
+ },
+ {
+ .name = "Nehalem",
+ .level = 2,
+ .vendor1 = CPUID_VENDOR_INTEL_1,
+ .vendor2 = CPUID_VENDOR_INTEL_2,
+ .vendor3 = CPUID_VENDOR_INTEL_3,
+ .family = 6,
+ .model = 2,
+ .stepping = 3,
+ .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+ CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+ .ext3_features = CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
+ },
+ {
+ .name = "Westmere",
+ .level = 11,
+ .vendor1 = CPUID_VENDOR_INTEL_1,
+ .vendor2 = CPUID_VENDOR_INTEL_2,
+ .vendor3 = CPUID_VENDOR_INTEL_3,
+ .family = 6,
+ .model = 44,
+ .stepping = 1,
+ .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+ CPUID_EXT_SSE3,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+ .ext3_features = CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x8000000A,
+ .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
+ },
+ {
+ .name = "SandyBridge",
+ .level = 0xd,
+ .vendor1 = CPUID_VENDOR_INTEL_1,
+ .vendor2 = CPUID_VENDOR_INTEL_2,
+ .vendor3 = CPUID_VENDOR_INTEL_3,
+ .family = 6,
+ .model = 42,
+ .stepping = 1,
+ .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
+ CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+ CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
+ CPUID_EXT_SSE3,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
+ CPUID_EXT2_SYSCALL,
+ .ext3_features = CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel Xeon E312xx (Sandy Bridge)",
+ },
+ {
+ .name = "Opteron_G1",
+ .level = 5,
+ .vendor1 = CPUID_VENDOR_AMD_1,
+ .vendor2 = CPUID_VENDOR_AMD_2,
+ .vendor3 = CPUID_VENDOR_AMD_3,
+ .family = 15,
+ .model = 6,
+ .stepping = 1,
+ .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .ext_features = CPUID_EXT_SSE3,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
+ CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
+ CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
+ CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
+ CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
+ CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
+ .xlevel = 0x80000008,
+ .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
+ },
+ {
+ .name = "Opteron_G2",
+ .level = 5,
+ .vendor1 = CPUID_VENDOR_AMD_1,
+ .vendor2 = CPUID_VENDOR_AMD_2,
+ .vendor3 = CPUID_VENDOR_AMD_3,
+ .family = 15,
+ .model = 6,
+ .stepping = 1,
+ .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
+ CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
+ CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
+ CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
+ CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
+ CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
+ CPUID_EXT2_DE | CPUID_EXT2_FPU,
+ .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x80000008,
+ .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
+ },
+ {
+ .name = "Opteron_G3",
+ .level = 5,
+ .vendor1 = CPUID_VENDOR_AMD_1,
+ .vendor2 = CPUID_VENDOR_AMD_2,
+ .vendor3 = CPUID_VENDOR_AMD_3,
+ .family = 15,
+ .model = 6,
+ .stepping = 1,
+ .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
+ CPUID_EXT_SSE3,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
+ CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
+ CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
+ CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
+ CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
+ CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
+ CPUID_EXT2_DE | CPUID_EXT2_FPU,
+ .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
+ CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x80000008,
+ .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
+ },
+ {
+ .name = "Opteron_G4",
+ .level = 0xd,
+ .vendor1 = CPUID_VENDOR_AMD_1,
+ .vendor2 = CPUID_VENDOR_AMD_2,
+ .vendor3 = CPUID_VENDOR_AMD_3,
+ .family = 21,
+ .model = 1,
+ .stepping = 2,
+ .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+ CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+ CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
+ CPUID_EXT_SSE3,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
+ CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
+ CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
+ CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
+ CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
+ CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
+ CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
+ .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
+ CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
+ CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
+ CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x8000001A,
+ .model_id = "AMD Opteron 62xx class CPU",
+ },
};
static int cpu_x86_fill_model_id(char *str)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 5/7] eliminate cpus-x86_64.conf file
2012-09-05 20:41 [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Eduardo Habkost
` (3 preceding siblings ...)
2012-09-05 20:41 ` [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C Eduardo Habkost
@ 2012-09-05 20:41 ` Eduardo Habkost
2012-09-10 13:46 ` Igor Mammedov
2012-09-05 20:41 ` [Qemu-devel] [PATCH 6/7] x86_cpudef_setup: coding style change Eduardo Habkost
` (3 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-05 20:41 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andreas Färber, Anthony Liguori, Igor Mammedov
This file is not needed anymore, as QEMU won't ship any config-based
cpudefs out of the box, relying only on the builtin CPU models.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Makefile | 1 -
arch_init.c | 1 -
sysconfigs/target/cpus-x86_64.conf | 1 -
3 files changed, 3 deletions(-)
delete mode 100644 sysconfigs/target/cpus-x86_64.conf
diff --git a/Makefile b/Makefile
index 1cd5bc8..a8d9236 100644
--- a/Makefile
+++ b/Makefile
@@ -297,7 +297,6 @@ install-confdir:
install-sysconfig: install-datadir install-confdir
$(INSTALL_DATA) $(SRC_PATH)/sysconfigs/target/target-x86_64.conf "$(DESTDIR)$(qemu_confdir)"
- $(INSTALL_DATA) $(SRC_PATH)/sysconfigs/target/cpus-x86_64.conf "$(DESTDIR)$(qemu_datadir)"
install: all $(if $(BUILD_DOCS),install-doc) install-sysconfig install-datadir
$(INSTALL_DIR) "$(DESTDIR)$(bindir)"
diff --git a/arch_init.c b/arch_init.c
index 5a1173e..510d3ef 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -136,7 +136,6 @@ static struct defconfig_file {
/* Indicates it is an user config file (disabled by -no-user-config) */
bool userconfig;
} default_config_files[] = {
- { CONFIG_QEMU_DATADIR "/cpus-" TARGET_ARCH ".conf", false },
{ CONFIG_QEMU_CONFDIR "/qemu.conf", true },
{ CONFIG_QEMU_CONFDIR "/target-" TARGET_ARCH ".conf", true },
{ NULL }, /* end of list */
diff --git a/sysconfigs/target/cpus-x86_64.conf b/sysconfigs/target/cpus-x86_64.conf
deleted file mode 100644
index 3902189..0000000
--- a/sysconfigs/target/cpus-x86_64.conf
+++ /dev/null
@@ -1 +0,0 @@
-# The CPU models from this file are now built-in in the QEMU source code
--
1.7.11.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 6/7] x86_cpudef_setup: coding style change
2012-09-05 20:41 [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Eduardo Habkost
` (4 preceding siblings ...)
2012-09-05 20:41 ` [Qemu-devel] [PATCH 5/7] eliminate cpus-x86_64.conf file Eduardo Habkost
@ 2012-09-05 20:41 ` Eduardo Habkost
2012-09-11 19:45 ` Don Slutz
2012-09-05 20:41 ` [Qemu-devel] [PATCH 7/7] i386: kill cpudef config section support Eduardo Habkost
` (2 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-05 20:41 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andreas Färber, Anthony Liguori, Igor Mammedov
Make source code lines shorter.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/cpu.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 73302d8..e13e6d5 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1513,20 +1513,23 @@ void x86_cpudef_setup(void)
static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
- builtin_x86_defs[i].next = x86_defs;
- builtin_x86_defs[i].flags = 1;
+ x86_def_t *def = &builtin_x86_defs[i];
+ def->next = x86_defs;
+ def->flags = 1;
/* Look for specific "cpudef" models that */
/* have the QEMU version in .model_id */
for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
- if (strcmp(model_with_versions[j], builtin_x86_defs[i].name) == 0) {
- pstrcpy(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), "QEMU Virtual CPU version ");
- pstrcat(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), qemu_get_version());
+ if (strcmp(model_with_versions[j], def->name) == 0) {
+ pstrcpy(def->model_id, sizeof(def->model_id),
+ "QEMU Virtual CPU version ");
+ pstrcat(def->model_id, sizeof(def->model_id),
+ qemu_get_version());
break;
}
}
- x86_defs = &builtin_x86_defs[i];
+ x86_defs = def;
}
#if !defined(CONFIG_USER_ONLY)
qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 7/7] i386: kill cpudef config section support
2012-09-05 20:41 [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Eduardo Habkost
` (5 preceding siblings ...)
2012-09-05 20:41 ` [Qemu-devel] [PATCH 6/7] x86_cpudef_setup: coding style change Eduardo Habkost
@ 2012-09-05 20:41 ` Eduardo Habkost
2012-09-10 14:20 ` Igor Mammedov
2012-09-10 15:17 ` [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Andreas Färber
2012-09-17 17:29 ` [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Andreas Färber
8 siblings, 1 reply; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-05 20:41 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andreas Färber, Anthony Liguori, Igor Mammedov
It's nice to have a flexible system to maintain CPU models as data, but
this is holding us from making improvements in the CPU code because it's
not using the common infra-structure, and because the machine-type data
is still inside C code.
Users who want to configure CPU features directly may simply use the
"-cpu" command-line option (and maybe an equivalent -device option in
the future) to set CPU features.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/cpu.c | 101 ++----------------------------------------------------
1 file changed, 2 insertions(+), 99 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index e13e6d5..7c0953f 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -240,7 +240,6 @@ typedef struct x86_def_t {
uint32_t xlevel;
char model_id[48];
int vendor_override;
- uint32_t flags;
/* Store the results of Centaur's CPUID instructions */
uint32_t ext4_features;
uint32_t xlevel2;
@@ -1299,7 +1298,7 @@ void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
char buf[256];
for (def = x86_defs; def; def = def->next) {
- snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
+ snprintf(buf, sizeof(buf), "%s", def->name);
(*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
}
if (kvm_enabled()) {
@@ -1393,16 +1392,6 @@ int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
}
#if !defined(CONFIG_USER_ONLY)
-/* copy vendor id string to 32 bit register, nul pad as needed
- */
-static void cpyid(const char *s, uint32_t *id)
-{
- char *d = (char *)id;
- char i;
-
- for (i = sizeof (*id); i--; )
- *d++ = *s ? *s++ : '\0';
-}
/* interpret radix and convert from string to arbitrary scalar,
* otherwise flag failure
@@ -1416,87 +1405,6 @@ static void cpyid(const char *s, uint32_t *id)
*str && !*pend ? (*pval = ul) : (*perr = 1); \
}
-/* map cpuid options to feature bits, otherwise return failure
- * (option tags in *str are delimited by whitespace)
- */
-static void setfeatures(uint32_t *pval, const char *str,
- const char **featureset, int *perr)
-{
- const char *p, *q;
-
- for (q = p = str; *p || *q; q = p) {
- while (iswhite(*p))
- q = ++p;
- while (*p && !iswhite(*p))
- ++p;
- if (!*q && !*p)
- return;
- if (!lookup_feature(pval, q, p, featureset)) {
- fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
- (int)(p - q), q);
- *perr = 1;
- return;
- }
- }
-}
-
-/* map config file options to x86_def_t form
- */
-static int cpudef_setfield(const char *name, const char *str, void *opaque)
-{
- x86_def_t *def = opaque;
- int err = 0;
-
- if (!strcmp(name, "name")) {
- g_free((void *)def->name);
- def->name = g_strdup(str);
- } else if (!strcmp(name, "model_id")) {
- strncpy(def->model_id, str, sizeof (def->model_id));
- } else if (!strcmp(name, "level")) {
- setscalar(&def->level, str, &err)
- } else if (!strcmp(name, "vendor")) {
- cpyid(&str[0], &def->vendor1);
- cpyid(&str[4], &def->vendor2);
- cpyid(&str[8], &def->vendor3);
- } else if (!strcmp(name, "family")) {
- setscalar(&def->family, str, &err)
- } else if (!strcmp(name, "model")) {
- setscalar(&def->model, str, &err)
- } else if (!strcmp(name, "stepping")) {
- setscalar(&def->stepping, str, &err)
- } else if (!strcmp(name, "feature_edx")) {
- setfeatures(&def->features, str, feature_name, &err);
- } else if (!strcmp(name, "feature_ecx")) {
- setfeatures(&def->ext_features, str, ext_feature_name, &err);
- } else if (!strcmp(name, "extfeature_edx")) {
- setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
- } else if (!strcmp(name, "extfeature_ecx")) {
- setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
- } else if (!strcmp(name, "xlevel")) {
- setscalar(&def->xlevel, str, &err)
- } else {
- fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
- return (1);
- }
- if (err) {
- fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
- return (1);
- }
- return (0);
-}
-
-/* register config file entry as x86_def_t
- */
-static int cpudef_register(QemuOpts *opts, void *opaque)
-{
- x86_def_t *def = g_malloc0(sizeof (x86_def_t));
-
- qemu_opt_foreach(opts, cpudef_setfield, def, 1);
- def->next = x86_defs;
- x86_defs = def;
- return (0);
-}
-
void cpu_clear_apic_feature(CPUX86State *env)
{
env->cpuid_features &= ~CPUID_APIC;
@@ -1504,8 +1412,7 @@ void cpu_clear_apic_feature(CPUX86State *env)
#endif /* !CONFIG_USER_ONLY */
-/* register "cpudef" models defined in configuration file. Here we first
- * preload any built-in definitions
+/* Initialize list of CPU models, filling some non-static fields if necessary
*/
void x86_cpudef_setup(void)
{
@@ -1515,7 +1422,6 @@ void x86_cpudef_setup(void)
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
x86_def_t *def = &builtin_x86_defs[i];
def->next = x86_defs;
- def->flags = 1;
/* Look for specific "cpudef" models that */
/* have the QEMU version in .model_id */
@@ -1531,9 +1437,6 @@ void x86_cpudef_setup(void)
x86_defs = def;
}
-#if !defined(CONFIG_USER_ONLY)
- qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
-#endif
}
static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
--
1.7.11.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 1/7] target-i386: Fold -cpu ?cpuid, ?model output into -cpu help, drop ?dump
2012-09-05 20:41 ` [Qemu-devel] [PATCH 1/7] target-i386: Fold -cpu ?cpuid, ?model output into -cpu help, drop ?dump Eduardo Habkost
@ 2012-09-10 9:40 ` Igor Mammedov
0 siblings, 0 replies; 29+ messages in thread
From: Igor Mammedov @ 2012-09-10 9:40 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, qemu-devel, Anthony Liguori, Andreas Färber
On Wed, 5 Sep 2012 17:41:07 -0300
Eduardo Habkost <ehabkost@redhat.com> wrote:
> From: Peter Maydell <peter.maydell@linaro.org>
>
> Commit c8057f95 (accidentally) disabled the ability to pass
> option strings starting with '?' to the target-specific
> cpu_list function, so the target-i386 specific "-cpu ?dump",
> "-cpu ?cpuid" and "-cpu ?model" stopped working.
>
> Since these options are undocumented and not used by libvirt,
> simply drop them completely rather than reinstating them
> with new style syntax. Instead, we fold the ?model and ?cpuid
> output into the output of the plain "-cpu help" output. The
> detailed output produced by ?dump is dropped.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> target-i386/cpu.c | 64
> ++++++++++--------------------------------------------- 1 file changed, 11
> insertions(+), 53 deletions(-)
>
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 423e009..5c98064 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -1073,70 +1073,28 @@ static void listflags(char *buf, int bufsize,
> uint32_t fbits, }
> }
>
> -/* generate CPU information:
> - * -? list model names
> - * -?model list model names/IDs
> - * -?dump output all model (x86_def_t) data
> - * -?cpuid list all recognized cpuid flag names
> - */
> +/* generate CPU information */
> void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char
> *optarg) {
> - unsigned char model = !strcmp("?model", optarg);
> - unsigned char dump = !strcmp("?dump", optarg);
> - unsigned char cpuid = !strcmp("?cpuid", optarg);
> x86_def_t *def;
> char buf[256];
>
> - if (cpuid) {
> - (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
> - listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
> - (*cpu_fprintf)(f, " f_edx: %s\n", buf);
> - listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
> - (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
> - listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
> - (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
> - listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
> - (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
> - return;
> - }
> for (def = x86_defs; def; def = def->next) {
> snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
> - if (model || dump) {
> - (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
> - } else {
> - (*cpu_fprintf)(f, "x86 %16s\n", buf);
> - }
> - if (dump) {
> - memcpy(buf, &def->vendor1, sizeof (def->vendor1));
> - memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
> - memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
> - buf[12] = '\0';
> - (*cpu_fprintf)(f,
> - " family %d model %d stepping %d level %d xlevel 0x%x"
> - " vendor \"%s\"\n",
> - def->family, def->model, def->stepping, def->level,
> - def->xlevel, buf);
> - listflags(buf, sizeof (buf), def->features, feature_name, 0);
> - (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
> - buf);
> - listflags(buf, sizeof (buf), def->ext_features,
> ext_feature_name,
> - 0);
> - (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n",
> def->ext_features,
> - buf);
> - listflags(buf, sizeof (buf), def->ext2_features,
> ext2_feature_name,
> - 0);
> - (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
> - def->ext2_features, buf);
> - listflags(buf, sizeof (buf), def->ext3_features,
> ext3_feature_name,
> - 0);
> - (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
> - def->ext3_features, buf);
> - (*cpu_fprintf)(f, "\n");
> - }
> + (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
> }
> if (kvm_enabled()) {
> (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
> }
> + (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
> + listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
> + (*cpu_fprintf)(f, " f_edx: %s\n", buf);
> + listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
> + (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
> + listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
> + (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
> + listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
> + (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
> }
>
> CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 2/7] Drop cpu_list_id macro
2012-09-05 20:41 ` [Qemu-devel] [PATCH 2/7] Drop cpu_list_id macro Eduardo Habkost
@ 2012-09-10 9:46 ` Igor Mammedov
0 siblings, 0 replies; 29+ messages in thread
From: Igor Mammedov @ 2012-09-10 9:46 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, qemu-devel, Anthony Liguori, Andreas Färber
On Wed, 5 Sep 2012 17:41:08 -0300
Eduardo Habkost <ehabkost@redhat.com> wrote:
> From: Peter Maydell <peter.maydell@linaro.org>
>
> Since the only user of the extended cpu_list_id() format
> was the x86 ?model/?dump/?cpuid output, we can drop it
> completely.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> cpus.c | 6 ++----
> linux-user/main.c | 6 ++----
> target-i386/cpu.c | 4 ++--
> target-i386/cpu.h | 4 ++--
> 4 files changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/cpus.c b/cpus.c
> index e476a3c..4b726ef 100644
> --- a/cpus.c
> +++ b/cpus.c
> @@ -1192,10 +1192,8 @@ void set_cpu_log_filename(const char *optarg)
> void list_cpus(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
> {
> /* XXX: implement xxx_cpu_list for targets that still miss it */
> -#if defined(cpu_list_id)
> - cpu_list_id(f, cpu_fprintf, optarg);
> -#elif defined(cpu_list)
> - cpu_list(f, cpu_fprintf); /* deprecated */
> +#if defined(cpu_list)
> + cpu_list(f, cpu_fprintf);
> #endif
> }
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 1a1c661..6e66e5d 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -3143,10 +3143,8 @@ static void handle_arg_cpu(const char *arg)
> cpu_model = strdup(arg);
> if (cpu_model == NULL || is_help_option(cpu_model)) {
> /* XXX: implement xxx_cpu_list for targets that still miss it */
> -#if defined(cpu_list_id)
> - cpu_list_id(stdout, &fprintf, "");
> -#elif defined(cpu_list)
> - cpu_list(stdout, &fprintf); /* deprecated */
> +#if defined(cpu_list)
> + cpu_list(stdout, &fprintf);
> #endif
> exit(1);
> }
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 5c98064..d2af0ff 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -1073,8 +1073,8 @@ static void listflags(char *buf, int bufsize,
> uint32_t fbits, }
> }
>
> -/* generate CPU information */
> -void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char
> *optarg) +/* generate CPU information. */
> +void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
> {
> x86_def_t *def;
> char buf[256];
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 0677502..49e0259 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -792,7 +792,7 @@ typedef struct CPUX86State {
>
> X86CPU *cpu_x86_init(const char *cpu_model);
> int cpu_x86_exec(CPUX86State *s);
> -void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char
> *optarg); +void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> void x86_cpudef_setup(void);
> int cpu_x86_support_mca_broadcast(CPUX86State *env);
>
> @@ -976,7 +976,7 @@ static inline CPUX86State *cpu_init(const char
> *cpu_model) #define cpu_exec cpu_x86_exec
> #define cpu_gen_code cpu_x86_gen_code
> #define cpu_signal_handler cpu_x86_signal_handler
> -#define cpu_list_id x86_cpu_list
> +#define cpu_list x86_cpu_list
> #define cpudef_setup x86_cpudef_setup
>
> #define CPU_SAVE_VERSION 12
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 3/7] i386: add missing CPUID_* constants
2012-09-05 20:41 ` [Qemu-devel] [PATCH 3/7] i386: add missing CPUID_* constants Eduardo Habkost
@ 2012-09-10 9:57 ` Igor Mammedov
0 siblings, 0 replies; 29+ messages in thread
From: Igor Mammedov @ 2012-09-10 9:57 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, qemu-devel, Anthony Liguori, Andreas Färber
On Wed, 5 Sep 2012 17:41:09 -0300
Eduardo Habkost <ehabkost@redhat.com> wrote:
> Those constants will be used by new CPU model definitions.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> target-i386/cpu.h | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 49e0259..d7ea2f9 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -382,6 +382,7 @@
> #define CPUID_PBE (1 << 31)
>
> #define CPUID_EXT_SSE3 (1 << 0)
> +#define CPUID_EXT_PCLMULQDQ (1 << 1)
> #define CPUID_EXT_DTES64 (1 << 2)
> #define CPUID_EXT_MONITOR (1 << 3)
> #define CPUID_EXT_DSCPL (1 << 4)
> @@ -401,14 +402,33 @@
> #define CPUID_EXT_MOVBE (1 << 22)
> #define CPUID_EXT_POPCNT (1 << 23)
> #define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24)
> +#define CPUID_EXT_AES (1 << 25)
> #define CPUID_EXT_XSAVE (1 << 26)
> #define CPUID_EXT_OSXSAVE (1 << 27)
> +#define CPUID_EXT_AVX (1 << 28)
> #define CPUID_EXT_HYPERVISOR (1 << 31)
>
> +#define CPUID_EXT2_FPU (1 << 0)
> +#define CPUID_EXT2_DE (1 << 2)
> +#define CPUID_EXT2_PSE (1 << 3)
> +#define CPUID_EXT2_TSC (1 << 4)
> +#define CPUID_EXT2_MSR (1 << 5)
> +#define CPUID_EXT2_PAE (1 << 6)
> +#define CPUID_EXT2_MCE (1 << 7)
> +#define CPUID_EXT2_CX8 (1 << 8)
> +#define CPUID_EXT2_APIC (1 << 9)
> #define CPUID_EXT2_SYSCALL (1 << 11)
> +#define CPUID_EXT2_MTRR (1 << 12)
> +#define CPUID_EXT2_PGE (1 << 13)
> +#define CPUID_EXT2_MCA (1 << 14)
> +#define CPUID_EXT2_CMOV (1 << 15)
> +#define CPUID_EXT2_PAT (1 << 16)
> +#define CPUID_EXT2_PSE36 (1 << 17)
> #define CPUID_EXT2_MP (1 << 19)
> #define CPUID_EXT2_NX (1 << 20)
> #define CPUID_EXT2_MMXEXT (1 << 22)
> +#define CPUID_EXT2_MMX (1 << 23)
> +#define CPUID_EXT2_FXSR (1 << 24)
> #define CPUID_EXT2_FFXSR (1 << 25)
> #define CPUID_EXT2_PDPE1GB (1 << 26)
> #define CPUID_EXT2_RDTSCP (1 << 27)
> @@ -427,7 +447,9 @@
> #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
> #define CPUID_EXT3_OSVW (1 << 9)
> #define CPUID_EXT3_IBS (1 << 10)
> +#define CPUID_EXT3_XOP (1 << 11)
> #define CPUID_EXT3_SKINIT (1 << 12)
> +#define CPUID_EXT3_FMA4 (1 << 16)
>
> #define CPUID_SVM_NPT (1 << 0)
> #define CPUID_SVM_LBRV (1 << 1)
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-05 20:41 ` [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C Eduardo Habkost
@ 2012-09-10 12:18 ` Igor Mammedov
2012-09-10 12:31 ` Igor Mammedov
2012-09-10 13:40 ` Igor Mammedov
1 sibling, 1 reply; 29+ messages in thread
From: Igor Mammedov @ 2012-09-10 12:18 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, qemu-devel, Anthony Liguori, Andreas Färber
On Wed, 5 Sep 2012 17:41:10 -0300
Eduardo Habkost <ehabkost@redhat.com> wrote:
> Those models are maintained by QEMU and may require compatibility code
> to be added when making some changes. Keeping the data in the C source
> code should make it simpler to handle those details.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> sysconfigs/target/cpus-x86_64.conf | 129 +---------------------
> target-i386/cpu.c | 219
> +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+),
> 128 deletions(-)
>
> diff --git a/sysconfigs/target/cpus-x86_64.conf
> b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644
> --- a/sysconfigs/target/cpus-x86_64.conf
> +++ b/sysconfigs/target/cpus-x86_64.conf
> @@ -1,128 +1 @@
> -# x86 CPU MODELS
> -
> -[cpudef]
> - name = "Conroe"
> - level = "2"
> - vendor = "GenuineIntel"
> - family = "6"
> - model = "2"
> - stepping = "3"
> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> - feature_ecx = "ssse3 sse3"
> - extfeature_edx = "i64 xd syscall"
...
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
> CPUID_EXT2_SYSCALL,
Silent fix, replacing i64 with CPUID_EXT2_LM
looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides
01.EDX[30] is reserved and what was probably meant/intended here is to use
80000001h.EDX[29] /* CPUID_EXT2_LM */
Perhaps patch that fixes it ought to go before this one.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-10 12:18 ` Igor Mammedov
@ 2012-09-10 12:31 ` Igor Mammedov
2012-09-10 13:04 ` Igor Mammedov
0 siblings, 1 reply; 29+ messages in thread
From: Igor Mammedov @ 2012-09-10 12:31 UTC (permalink / raw)
To: Igor Mammedov
Cc: Peter Maydell, Andreas Färber, Eduardo Habkost,
Anthony Liguori, qemu-devel
On Mon, 10 Sep 2012 14:18:38 +0200
Igor Mammedov <imammedo@redhat.com> wrote:
> On Wed, 5 Sep 2012 17:41:10 -0300
> Eduardo Habkost <ehabkost@redhat.com> wrote:
>
> > Those models are maintained by QEMU and may require compatibility code
> > to be added when making some changes. Keeping the data in the C source
> > code should make it simpler to handle those details.
> >
> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> > ---
> > sysconfigs/target/cpus-x86_64.conf | 129 +---------------------
> > target-i386/cpu.c | 219
> > +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+),
> > 128 deletions(-)
> >
> > diff --git a/sysconfigs/target/cpus-x86_64.conf
> > b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644
> > --- a/sysconfigs/target/cpus-x86_64.conf
> > +++ b/sysconfigs/target/cpus-x86_64.conf
> > @@ -1,128 +1 @@
> > -# x86 CPU MODELS
> > -
> > -[cpudef]
> > - name = "Conroe"
> > - level = "2"
> > - vendor = "GenuineIntel"
> > - family = "6"
> > - model = "2"
> > - stepping = "3"
> > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> > sep apic cx8 mce pae msr tsc pse de fpu"
> > - feature_ecx = "ssse3 sse3"
> > - extfeature_edx = "i64 xd syscall"
> ...
> > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
> > CPUID_EXT2_SYSCALL,
> Silent fix, replacing i64 with CPUID_EXT2_LM
> looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides
Actually it works when setting feature fields because it uses
setfeatures(), however setting i64 will set wrong bit if it's set using
add_flagname_to_bitmaps()
> 01.EDX[30] is reserved and what was probably meant/intended here is to use
> 80000001h.EDX[29] /* CPUID_EXT2_LM */
> Perhaps patch that fixes it ought to go before this one.
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-10 12:31 ` Igor Mammedov
@ 2012-09-10 13:04 ` Igor Mammedov
2012-09-10 14:50 ` Don Slutz
2012-09-10 15:04 ` Eduardo Habkost
0 siblings, 2 replies; 29+ messages in thread
From: Igor Mammedov @ 2012-09-10 13:04 UTC (permalink / raw)
To: Igor Mammedov
Cc: Peter Maydell, Andreas Färber, Eduardo Habkost,
Anthony Liguori, qemu-devel
On Mon, 10 Sep 2012 14:31:49 +0200
Igor Mammedov <imammedo@redhat.com> wrote:
> On Mon, 10 Sep 2012 14:18:38 +0200
> Igor Mammedov <imammedo@redhat.com> wrote:
>
> > On Wed, 5 Sep 2012 17:41:10 -0300
> > Eduardo Habkost <ehabkost@redhat.com> wrote:
> >
> > > Those models are maintained by QEMU and may require compatibility code
> > > to be added when making some changes. Keeping the data in the C source
> > > code should make it simpler to handle those details.
> > >
> > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> > > ---
> > > sysconfigs/target/cpus-x86_64.conf | 129 +---------------------
> > > target-i386/cpu.c | 219
> > > +++++++++++++++++++++++++++++++++++++ 2 files changed, 220
> > > insertions(+), 128 deletions(-)
> > >
> > > diff --git a/sysconfigs/target/cpus-x86_64.conf
> > > b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644
> > > --- a/sysconfigs/target/cpus-x86_64.conf
> > > +++ b/sysconfigs/target/cpus-x86_64.conf
> > > @@ -1,128 +1 @@
> > > -# x86 CPU MODELS
> > > -
> > > -[cpudef]
> > > - name = "Conroe"
> > > - level = "2"
> > > - vendor = "GenuineIntel"
> > > - family = "6"
> > > - model = "2"
> > > - stepping = "3"
> > > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> > > sep apic cx8 mce pae msr tsc pse de fpu"
> > > - feature_ecx = "ssse3 sse3"
> > > - extfeature_edx = "i64 xd syscall"
> > ...
> > > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
> > > CPUID_EXT2_SYSCALL,
> > Silent fix, replacing i64 with CPUID_EXT2_LM
> > looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides
> Actually it works when setting feature fields because it uses
> setfeatures(), however setting i64 will set wrong bit if it's set using
> add_flagname_to_bitmaps()
I'm wrong, and sorry for noise. I mixed up ia64 from feature_name with i64
from ext2_feature_name.
But question unrelated to this patch is still stand if ia64 is valid bit for
01.EDX[30]?
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-05 20:41 ` [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C Eduardo Habkost
2012-09-10 12:18 ` Igor Mammedov
@ 2012-09-10 13:40 ` Igor Mammedov
2012-09-11 19:45 ` Don Slutz
1 sibling, 1 reply; 29+ messages in thread
From: Igor Mammedov @ 2012-09-10 13:40 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, qemu-devel, Anthony Liguori, Andreas Färber
On Wed, 5 Sep 2012 17:41:10 -0300
Eduardo Habkost <ehabkost@redhat.com> wrote:
> Those models are maintained by QEMU and may require compatibility code
> to be added when making some changes. Keeping the data in the C source
> code should make it simpler to handle those details.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> sysconfigs/target/cpus-x86_64.conf | 129 +---------------------
> target-i386/cpu.c | 219
> +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+),
> 128 deletions(-)
>
> diff --git a/sysconfigs/target/cpus-x86_64.conf
> b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644
> --- a/sysconfigs/target/cpus-x86_64.conf
> +++ b/sysconfigs/target/cpus-x86_64.conf
> @@ -1,128 +1 @@
> -# x86 CPU MODELS
> -
> -[cpudef]
> - name = "Conroe"
> - level = "2"
> - vendor = "GenuineIntel"
> - family = "6"
> - model = "2"
> - stepping = "3"
> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> - feature_ecx = "ssse3 sse3"
> - extfeature_edx = "i64 xd syscall"
> - extfeature_ecx = "lahf_lm"
> - xlevel = "0x8000000A"
> - model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
> -
> -[cpudef]
> - name = "Penryn"
> - level = "2"
> - vendor = "GenuineIntel"
> - family = "6"
> - model = "2"
> - stepping = "3"
> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> - feature_ecx = "sse4.1 cx16 ssse3 sse3"
> - extfeature_edx = "i64 xd syscall"
> - extfeature_ecx = "lahf_lm"
> - xlevel = "0x8000000A"
> - model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
> -
> -[cpudef]
> - name = "Nehalem"
> - level = "2"
> - vendor = "GenuineIntel"
> - family = "6"
> - model = "2"
> - stepping = "3"
> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> - feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
> - extfeature_edx = "i64 syscall xd"
> - extfeature_ecx = "lahf_lm"
> - xlevel = "0x8000000A"
> - model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
> -
> -[cpudef]
> - name = "Westmere"
> - level = "11"
> - vendor = "GenuineIntel"
> - family = "6"
> - model = "44"
> - stepping = "1"
> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> - feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
> - extfeature_edx = "i64 syscall xd"
> - extfeature_ecx = "lahf_lm"
> - xlevel = "0x8000000A"
> - model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
> -
> -[cpudef]
> - name = "SandyBridge"
> - level = "0xd"
> - vendor = "GenuineIntel"
> - family = "6"
> - model = "42"
> - stepping = "1"
> - feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> - feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1
> cx16 ssse3 pclmulqdq sse3"
> - extfeature_edx = "i64 rdtscp nx syscall "
> - extfeature_ecx = "lahf_lm"
> - xlevel = "0x8000000A"
> - model_id = "Intel Xeon E312xx (Sandy Bridge)"
> -
> -[cpudef]
> - name = "Opteron_G1"
> - level = "5"
> - vendor = "AuthenticAMD"
> - family = "15"
> - model = "6"
> - stepping = "1"
> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> - feature_ecx = "sse3"
> - extfeature_edx = "lm fxsr mmx nx pse36 pat cmov mca pge mtrr syscall
> apic cx8 mce pae msr tsc pse de fpu"
> - extfeature_ecx = " "
> - xlevel = "0x80000008"
> - model_id = "AMD Opteron 240 (Gen 1 Class Opteron)"
> -
> -[cpudef]
> - name = "Opteron_G2"
> - level = "5"
> - vendor = "AuthenticAMD"
> - family = "15"
> - model = "6"
> - stepping = "1"
> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> - feature_ecx = "cx16 sse3"
> - extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr
> syscall apic cx8 mce pae msr tsc pse de fpu"
> - extfeature_ecx = "svm lahf_lm"
> - xlevel = "0x80000008"
> - model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)"
> -
> -[cpudef]
> - name = "Opteron_G3"
> - level = "5"
> - vendor = "AuthenticAMD"
> - family = "15"
> - model = "6"
> - stepping = "1"
> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> - feature_ecx = "popcnt cx16 monitor sse3"
> - extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr
> syscall apic cx8 mce pae msr tsc pse de fpu"
> - extfeature_ecx = "misalignsse sse4a abm svm lahf_lm"
> - xlevel = "0x80000008"
> - model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)"
> -
> -[cpudef]
> - name = "Opteron_G4"
> - level = "0xd"
> - vendor = "AuthenticAMD"
> - family = "21"
> - model = "1"
> - stepping = "2"
> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> - feature_ecx = "avx xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 pclmulqdq
> sse3"
> - extfeature_edx = "lm rdtscp pdpe1gb fxsr mmx nx pse36 pat cmov mca pge
> mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
> - extfeature_ecx = " fma4 xop 3dnowprefetch misalignsse sse4a abm svm
> lahf_lm"
> - xlevel = "0x8000001A"
> - model_id = "AMD Opteron 62xx class CPU"
> -
> +# The CPU models from this file are now built-in in the QEMU source code
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index d2af0ff..73302d8 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -490,6 +490,225 @@ static x86_def_t builtin_x86_defs[] = {
> .xlevel = 0x8000000A,
> .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
> },
> + {
> + .name = "Conroe",
> + .level = 2,
> + .vendor1 = CPUID_VENDOR_INTEL_1,
> + .vendor2 = CPUID_VENDOR_INTEL_2,
> + .vendor3 = CPUID_VENDOR_INTEL_3,
> + .family = 6,
> + .model = 2,
> + .stepping = 3,
> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
> CPUID_MCA |
> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> + CPUID_DE | CPUID_FP87,
> + .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
> CPUID_EXT2_SYSCALL,
> + .ext3_features = CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x8000000A,
> + .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
> + },
> + {
> + .name = "Penryn",
> + .level = 2,
> + .vendor1 = CPUID_VENDOR_INTEL_1,
> + .vendor2 = CPUID_VENDOR_INTEL_2,
> + .vendor3 = CPUID_VENDOR_INTEL_3,
> + .family = 6,
> + .model = 2,
> + .stepping = 3,
> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
> CPUID_MCA |
> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> + CPUID_DE | CPUID_FP87,
> + .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3
> |
> + CPUID_EXT_SSE3,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
> CPUID_EXT2_SYSCALL,
> + .ext3_features = CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x8000000A,
> + .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
> + },
> + {
> + .name = "Nehalem",
> + .level = 2,
> + .vendor1 = CPUID_VENDOR_INTEL_1,
> + .vendor2 = CPUID_VENDOR_INTEL_2,
> + .vendor3 = CPUID_VENDOR_INTEL_3,
> + .family = 6,
> + .model = 2,
> + .stepping = 3,
> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
> CPUID_MCA |
> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> + CPUID_DE | CPUID_FP87,
> + .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
> CPUID_EXT_SSE41 |
> + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
> CPUID_EXT2_NX,
> + .ext3_features = CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x8000000A,
> + .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
> + },
> + {
> + .name = "Westmere",
> + .level = 11,
> + .vendor1 = CPUID_VENDOR_INTEL_1,
> + .vendor2 = CPUID_VENDOR_INTEL_2,
> + .vendor3 = CPUID_VENDOR_INTEL_3,
> + .family = 6,
> + .model = 44,
> + .stepping = 1,
> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
> CPUID_MCA |
> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> + CPUID_DE | CPUID_FP87,
> + .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42
> |
> + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> + CPUID_EXT_SSE3,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
> CPUID_EXT2_NX,
> + .ext3_features = CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x8000000A,
> + .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
> + },
> + {
> + .name = "SandyBridge",
> + .level = 0xd,
> + .vendor1 = CPUID_VENDOR_INTEL_1,
> + .vendor2 = CPUID_VENDOR_INTEL_2,
> + .vendor3 = CPUID_VENDOR_INTEL_3,
> + .family = 6,
> + .model = 42,
> + .stepping = 1,
> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
> CPUID_MCA |
> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> + CPUID_DE | CPUID_FP87,
> + .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
> + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
> + CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
> + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
> + CPUID_EXT_SSE3,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX
> |
> + CPUID_EXT2_SYSCALL,
> + .ext3_features = CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x8000000A,
> + .model_id = "Intel Xeon E312xx (Sandy Bridge)",
> + },
> + {
> + .name = "Opteron_G1",
> + .level = 5,
> + .vendor1 = CPUID_VENDOR_AMD_1,
> + .vendor2 = CPUID_VENDOR_AMD_2,
> + .vendor3 = CPUID_VENDOR_AMD_3,
> + .family = 15,
> + .model = 6,
> + .stepping = 1,
> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
> CPUID_MCA |
> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> + CPUID_DE | CPUID_FP87,
> + .ext_features = CPUID_EXT_SSE3,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
> + CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
> + CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
> + CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
> + CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE |
> CPUID_EXT2_MSR |
> + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE |
> CPUID_EXT2_FPU,
> + .xlevel = 0x80000008,
> + .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
> + },
> + {
> + .name = "Opteron_G2",
> + .level = 5,
> + .vendor1 = CPUID_VENDOR_AMD_1,
> + .vendor2 = CPUID_VENDOR_AMD_2,
> + .vendor3 = CPUID_VENDOR_AMD_3,
> + .family = 15,
> + .model = 6,
> + .stepping = 1,
> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
> CPUID_MCA |
> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> + CPUID_DE | CPUID_FP87,
> + .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
> CPUID_EXT2_FXSR |
> + CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
> + CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
> + CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
> + CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
> + CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC |
> CPUID_EXT2_PSE |
> + CPUID_EXT2_DE | CPUID_EXT2_FPU,
> + .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x80000008,
> + .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
> + },
> + {
> + .name = "Opteron_G3",
> + .level = 5,
> + .vendor1 = CPUID_VENDOR_AMD_1,
> + .vendor2 = CPUID_VENDOR_AMD_2,
> + .vendor3 = CPUID_VENDOR_AMD_3,
> + .family = 15,
> + .model = 6,
> + .stepping = 1,
> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
> CPUID_MCA |
> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> + CPUID_DE | CPUID_FP87,
> + .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 |
> CPUID_EXT_MONITOR |
> + CPUID_EXT_SSE3,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
> CPUID_EXT2_FXSR |
> + CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
> + CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
> + CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
> + CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
> + CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC |
> CPUID_EXT2_PSE |
> + CPUID_EXT2_DE | CPUID_EXT2_FPU,
> + .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
> + CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x80000008,
> + .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
> + },
> + {
> + .name = "Opteron_G4",
> + .level = 0xd,
> + .vendor1 = CPUID_VENDOR_AMD_1,
> + .vendor2 = CPUID_VENDOR_AMD_2,
> + .vendor3 = CPUID_VENDOR_AMD_3,
> + .family = 21,
> + .model = 1,
> + .stepping = 2,
> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
> CPUID_MCA |
> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> + CPUID_DE | CPUID_FP87,
> + .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
> + CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
> + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
> + CPUID_EXT_SSE3,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
> + CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
> + CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
> + CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
> + CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
> + CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE |
> CPUID_EXT2_MSR |
> + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE |
> CPUID_EXT2_FPU,
> + .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
> + CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
> + CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
> + CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x8000001A,
> + .model_id = "AMD Opteron 62xx class CPU",
> + },
> };
>
> static int cpu_x86_fill_model_id(char *str)
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 5/7] eliminate cpus-x86_64.conf file
2012-09-05 20:41 ` [Qemu-devel] [PATCH 5/7] eliminate cpus-x86_64.conf file Eduardo Habkost
@ 2012-09-10 13:46 ` Igor Mammedov
0 siblings, 0 replies; 29+ messages in thread
From: Igor Mammedov @ 2012-09-10 13:46 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, qemu-devel, Anthony Liguori, Andreas Färber
On Wed, 5 Sep 2012 17:41:11 -0300
Eduardo Habkost <ehabkost@redhat.com> wrote:
> This file is not needed anymore, as QEMU won't ship any config-based
> cpudefs out of the box, relying only on the builtin CPU models.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Makefile | 1 -
> arch_init.c | 1 -
> sysconfigs/target/cpus-x86_64.conf | 1 -
> 3 files changed, 3 deletions(-)
> delete mode 100644 sysconfigs/target/cpus-x86_64.conf
>
> diff --git a/Makefile b/Makefile
> index 1cd5bc8..a8d9236 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -297,7 +297,6 @@ install-confdir:
>
> install-sysconfig: install-datadir install-confdir
> $(INSTALL_DATA) $(SRC_PATH)/sysconfigs/target/target-x86_64.conf
> "$(DESTDIR)$(qemu_confdir)"
> - $(INSTALL_DATA) $(SRC_PATH)/sysconfigs/target/cpus-x86_64.conf
> "$(DESTDIR)$(qemu_datadir)"
> install: all $(if $(BUILD_DOCS),install-doc) install-sysconfig
> install-datadir $(INSTALL_DIR) "$(DESTDIR)$(bindir)"
> diff --git a/arch_init.c b/arch_init.c
> index 5a1173e..510d3ef 100644
> --- a/arch_init.c
> +++ b/arch_init.c
> @@ -136,7 +136,6 @@ static struct defconfig_file {
> /* Indicates it is an user config file (disabled by -no-user-config) */
> bool userconfig;
> } default_config_files[] = {
> - { CONFIG_QEMU_DATADIR "/cpus-" TARGET_ARCH ".conf", false },
> { CONFIG_QEMU_CONFDIR "/qemu.conf", true },
> { CONFIG_QEMU_CONFDIR "/target-" TARGET_ARCH ".conf", true },
> { NULL }, /* end of list */
> diff --git a/sysconfigs/target/cpus-x86_64.conf
> b/sysconfigs/target/cpus-x86_64.conf deleted file mode 100644
> index 3902189..0000000
> --- a/sysconfigs/target/cpus-x86_64.conf
> +++ /dev/null
> @@ -1 +0,0 @@
> -# The CPU models from this file are now built-in in the QEMU source code
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 7/7] i386: kill cpudef config section support
2012-09-05 20:41 ` [Qemu-devel] [PATCH 7/7] i386: kill cpudef config section support Eduardo Habkost
@ 2012-09-10 14:20 ` Igor Mammedov
0 siblings, 0 replies; 29+ messages in thread
From: Igor Mammedov @ 2012-09-10 14:20 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, qemu-devel, Anthony Liguori, Andreas Färber
On Wed, 5 Sep 2012 17:41:13 -0300
Eduardo Habkost <ehabkost@redhat.com> wrote:
> It's nice to have a flexible system to maintain CPU models as data, but
> this is holding us from making improvements in the CPU code because it's
> not using the common infra-structure, and because the machine-type data
> is still inside C code.
>
> Users who want to configure CPU features directly may simply use the
> "-cpu" command-line option (and maybe an equivalent -device option in
> the future) to set CPU features.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> target-i386/cpu.c | 101
> ++---------------------------------------------------- 1 file changed, 2
> insertions(+), 99 deletions(-)
>
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index e13e6d5..7c0953f 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -240,7 +240,6 @@ typedef struct x86_def_t {
> uint32_t xlevel;
> char model_id[48];
> int vendor_override;
> - uint32_t flags;
> /* Store the results of Centaur's CPUID instructions */
> uint32_t ext4_features;
> uint32_t xlevel2;
> @@ -1299,7 +1298,7 @@ void x86_cpu_list(FILE *f, fprintf_function
> cpu_fprintf) char buf[256];
>
> for (def = x86_defs; def; def = def->next) {
> - snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
> + snprintf(buf, sizeof(buf), "%s", def->name);
> (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
> }
> if (kvm_enabled()) {
> @@ -1393,16 +1392,6 @@ int cpu_x86_register(X86CPU *cpu, const char
> *cpu_model) }
>
> #if !defined(CONFIG_USER_ONLY)
> -/* copy vendor id string to 32 bit register, nul pad as needed
> - */
> -static void cpyid(const char *s, uint32_t *id)
> -{
> - char *d = (char *)id;
> - char i;
> -
> - for (i = sizeof (*id); i--; )
> - *d++ = *s ? *s++ : '\0';
> -}
>
> /* interpret radix and convert from string to arbitrary scalar,
> * otherwise flag failure
*/
#define setscalar(pval, str, perr) \
is used only from to be removed setfeatures(), could you remove it as well.
> @@ -1416,87 +1405,6 @@ static void cpyid(const char *s, uint32_t *id)
> *str && !*pend ? (*pval = ul) : (*perr = 1); \
> }
>
> -/* map cpuid options to feature bits, otherwise return failure
> - * (option tags in *str are delimited by whitespace)
> - */
> -static void setfeatures(uint32_t *pval, const char *str,
> - const char **featureset, int *perr)
> -{
> - const char *p, *q;
> -
> - for (q = p = str; *p || *q; q = p) {
> - while (iswhite(*p))
> - q = ++p;
> - while (*p && !iswhite(*p))
> - ++p;
> - if (!*q && !*p)
> - return;
> - if (!lookup_feature(pval, q, p, featureset)) {
> - fprintf(stderr, "error: feature \"%.*s\" not available in
> set\n",
> - (int)(p - q), q);
> - *perr = 1;
> - return;
> - }
> - }
> -}
> -
> -/* map config file options to x86_def_t form
> - */
> -static int cpudef_setfield(const char *name, const char *str, void *opaque)
> -{
> - x86_def_t *def = opaque;
> - int err = 0;
> -
> - if (!strcmp(name, "name")) {
> - g_free((void *)def->name);
> - def->name = g_strdup(str);
> - } else if (!strcmp(name, "model_id")) {
> - strncpy(def->model_id, str, sizeof (def->model_id));
> - } else if (!strcmp(name, "level")) {
> - setscalar(&def->level, str, &err)
> - } else if (!strcmp(name, "vendor")) {
> - cpyid(&str[0], &def->vendor1);
> - cpyid(&str[4], &def->vendor2);
> - cpyid(&str[8], &def->vendor3);
> - } else if (!strcmp(name, "family")) {
> - setscalar(&def->family, str, &err)
> - } else if (!strcmp(name, "model")) {
> - setscalar(&def->model, str, &err)
> - } else if (!strcmp(name, "stepping")) {
> - setscalar(&def->stepping, str, &err)
> - } else if (!strcmp(name, "feature_edx")) {
> - setfeatures(&def->features, str, feature_name, &err);
> - } else if (!strcmp(name, "feature_ecx")) {
> - setfeatures(&def->ext_features, str, ext_feature_name, &err);
> - } else if (!strcmp(name, "extfeature_edx")) {
> - setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
> - } else if (!strcmp(name, "extfeature_ecx")) {
> - setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
> - } else if (!strcmp(name, "xlevel")) {
> - setscalar(&def->xlevel, str, &err)
> - } else {
> - fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
> - return (1);
> - }
> - if (err) {
> - fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
> - return (1);
> - }
> - return (0);
> -}
> -
> -/* register config file entry as x86_def_t
> - */
> -static int cpudef_register(QemuOpts *opts, void *opaque)
> -{
> - x86_def_t *def = g_malloc0(sizeof (x86_def_t));
> -
> - qemu_opt_foreach(opts, cpudef_setfield, def, 1);
> - def->next = x86_defs;
> - x86_defs = def;
> - return (0);
> -}
> -
> void cpu_clear_apic_feature(CPUX86State *env)
> {
> env->cpuid_features &= ~CPUID_APIC;
> @@ -1504,8 +1412,7 @@ void cpu_clear_apic_feature(CPUX86State *env)
>
> #endif /* !CONFIG_USER_ONLY */
>
> -/* register "cpudef" models defined in configuration file. Here we first
> - * preload any built-in definitions
> +/* Initialize list of CPU models, filling some non-static fields if
> necessary */
> void x86_cpudef_setup(void)
> {
> @@ -1515,7 +1422,6 @@ void x86_cpudef_setup(void)
> for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
> x86_def_t *def = &builtin_x86_defs[i];
> def->next = x86_defs;
> - def->flags = 1;
>
> /* Look for specific "cpudef" models that */
> /* have the QEMU version in .model_id */
> @@ -1531,9 +1437,6 @@ void x86_cpudef_setup(void)
>
> x86_defs = def;
> }
> -#if !defined(CONFIG_USER_ONLY)
> - qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
> -#endif
> }
>
> static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-10 13:04 ` Igor Mammedov
@ 2012-09-10 14:50 ` Don Slutz
2012-09-10 14:58 ` Andreas Färber
2012-09-10 15:04 ` Eduardo Habkost
1 sibling, 1 reply; 29+ messages in thread
From: Don Slutz @ 2012-09-10 14:50 UTC (permalink / raw)
To: Igor Mammedov
Cc: qemu-devel, Peter Maydell, Andreas Färber, Anthony Liguori,
Eduardo Habkost
On 09/10/12 09:04, Igor Mammedov wrote:
> On Mon, 10 Sep 2012 14:31:49 +0200
> Igor Mammedov <imammedo@redhat.com> wrote:
>
>> On Mon, 10 Sep 2012 14:18:38 +0200
>> Igor Mammedov <imammedo@redhat.com> wrote:
>>
>>> On Wed, 5 Sep 2012 17:41:10 -0300
>>> Eduardo Habkost <ehabkost@redhat.com> wrote:
>>>
>>>> Those models are maintained by QEMU and may require compatibility code
>>>> to be added when making some changes. Keeping the data in the C source
>>>> code should make it simpler to handle those details.
>>>>
>>>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
>>>> ---
>>>> sysconfigs/target/cpus-x86_64.conf | 129 +---------------------
>>>> target-i386/cpu.c | 219
>>>> +++++++++++++++++++++++++++++++++++++ 2 files changed, 220
>>>> insertions(+), 128 deletions(-)
>>>>
>>>> diff --git a/sysconfigs/target/cpus-x86_64.conf
>>>> b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644
>>>> --- a/sysconfigs/target/cpus-x86_64.conf
>>>> +++ b/sysconfigs/target/cpus-x86_64.conf
>>>> @@ -1,128 +1 @@
>>>> -# x86 CPU MODELS
>>>> -
>>>> -[cpudef]
>>>> - name = "Conroe"
>>>> - level = "2"
>>>> - vendor = "GenuineIntel"
>>>> - family = "6"
>>>> - model = "2"
>>>> - stepping = "3"
>>>> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>>>> sep apic cx8 mce pae msr tsc pse de fpu"
>>>> - feature_ecx = "ssse3 sse3"
>>>> - extfeature_edx = "i64 xd syscall"
>>> ...
>>>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
>>>> CPUID_EXT2_SYSCALL,
>>> Silent fix, replacing i64 with CPUID_EXT2_LM
>>> looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides
>> Actually it works when setting feature fields because it uses
>> setfeatures(), however setting i64 will set wrong bit if it's set using
>> add_flagname_to_bitmaps()
> I'm wrong, and sorry for noise. I mixed up ia64 from feature_name with i64
> from ext2_feature_name.
>
> But question unrelated to this patch is still stand if ia64 is valid bit for
> 01.EDX[30]?
>
>
Intel® Processor Identification
and the CPUID Instruction
Application Note 485
January 2006
Order Number: 241618-030
...
Updated Table 3-5 to include the feature flag definition (EDX[30]) for
IA64 capabilities.
...
30 IA64 IA64 Capabilities The processor is a member of the Intel®
Itanium® processor family
and currently operating in IA32 emulation mode.
---------------
Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and
http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64)
But the newest version I found (241618-037, January 2011) is back to
Reserved.
-Don Slutz
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-10 14:50 ` Don Slutz
@ 2012-09-10 14:58 ` Andreas Färber
2012-09-10 15:07 ` Eduardo Habkost
0 siblings, 1 reply; 29+ messages in thread
From: Andreas Färber @ 2012-09-10 14:58 UTC (permalink / raw)
To: Don Slutz, Igor Mammedov
Cc: Peter Maydell, Eduardo Habkost, Anthony Liguori, qemu-devel
Am 10.09.2012 16:50, schrieb Don Slutz:
> On 09/10/12 09:04, Igor Mammedov wrote:
>> But question unrelated to this patch is still stand if ia64 is valid
>> bit for
>> 01.EDX[30]?
>>
>>
> Intel® Processor Identification
> and the CPUID Instruction
> Application Note 485
> January 2006
>
> Order Number: 241618-030
>
> ...
>
> Updated Table 3-5 to include the feature flag definition (EDX[30]) for
> IA64 capabilities.
> ...
> 30 IA64 IA64 Capabilities The processor is a member of the Intel®
> Itanium® processor family
> and currently operating in IA32 emulation mode.
>
> ---------------
>
> Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and
> http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64)
Don't those semantics contradict the use in qemu-system-x86_64 or
qemu-system-i386 rather than qemu-system-ia64 then? We don't model ia64
CPUs here (just like we don't model ppc64 CPUs in ppc) so the flag could
never become 1 IIUC.
Andreas
> But the newest version I found (241618-037, January 2011) is back to
> Reserved.
>
>
> -Don Slutz
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-10 13:04 ` Igor Mammedov
2012-09-10 14:50 ` Don Slutz
@ 2012-09-10 15:04 ` Eduardo Habkost
1 sibling, 0 replies; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-10 15:04 UTC (permalink / raw)
To: Igor Mammedov
Cc: Peter Maydell, qemu-devel, Anthony Liguori, Andreas Färber
On Mon, Sep 10, 2012 at 03:04:30PM +0200, Igor Mammedov wrote:
> On Mon, 10 Sep 2012 14:31:49 +0200
> Igor Mammedov <imammedo@redhat.com> wrote:
>
> > On Mon, 10 Sep 2012 14:18:38 +0200
> > Igor Mammedov <imammedo@redhat.com> wrote:
> >
> > > On Wed, 5 Sep 2012 17:41:10 -0300
> > > Eduardo Habkost <ehabkost@redhat.com> wrote:
> > >
> > > > Those models are maintained by QEMU and may require compatibility code
> > > > to be added when making some changes. Keeping the data in the C source
> > > > code should make it simpler to handle those details.
> > > >
> > > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> > > > ---
> > > > sysconfigs/target/cpus-x86_64.conf | 129 +---------------------
> > > > target-i386/cpu.c | 219
> > > > +++++++++++++++++++++++++++++++++++++ 2 files changed, 220
> > > > insertions(+), 128 deletions(-)
> > > >
> > > > diff --git a/sysconfigs/target/cpus-x86_64.conf
> > > > b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644
> > > > --- a/sysconfigs/target/cpus-x86_64.conf
> > > > +++ b/sysconfigs/target/cpus-x86_64.conf
> > > > @@ -1,128 +1 @@
> > > > -# x86 CPU MODELS
> > > > -
> > > > -[cpudef]
> > > > - name = "Conroe"
> > > > - level = "2"
> > > > - vendor = "GenuineIntel"
> > > > - family = "6"
> > > > - model = "2"
> > > > - stepping = "3"
> > > > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> > > > sep apic cx8 mce pae msr tsc pse de fpu"
> > > > - feature_ecx = "ssse3 sse3"
> > > > - extfeature_edx = "i64 xd syscall"
> > > ...
> > > > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
> > > > CPUID_EXT2_SYSCALL,
> > > Silent fix, replacing i64 with CPUID_EXT2_LM
> > > looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides
> > Actually it works when setting feature fields because it uses
> > setfeatures(), however setting i64 will set wrong bit if it's set using
> > add_flagname_to_bitmaps()
> I'm wrong, and sorry for noise. I mixed up ia64 from feature_name with i64
> from ext2_feature_name.
>
> But question unrelated to this patch is still stand if ia64 is valid bit for
> 01.EDX[30]?
It is reserved on IA-32 and Intel-64/AMD64, but it has a name/meaning,
already[1]. The name of that bit is in the table, but it's harmless (and
useless) because both KVM and TCG modes disable it automatically (and
-cpu check/enforce should warn about it not being supported by the
host).
[1] Linux recognizes it as X86_FEATURE_IA64/"ia64".
Itanium SDM documents it as:
"30 Processor based on the Intel Itanium architecture
"The processor is based on the Intel Itanium architecture and is capable
of executing the Intel Itanium instruction set. IA-32 application level
software MUST also check with the running operating system to see if the
system can also support Itanium architecture-based code before switching
to the Intel Itanium instruction set."
--
Eduardo
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-10 14:58 ` Andreas Färber
@ 2012-09-10 15:07 ` Eduardo Habkost
2012-09-10 15:13 ` Andreas Färber
0 siblings, 1 reply; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-10 15:07 UTC (permalink / raw)
To: Andreas Färber
Cc: Igor Mammedov, Don Slutz, qemu-devel, Anthony Liguori, Peter Maydell
On Mon, Sep 10, 2012 at 04:58:39PM +0200, Andreas Färber wrote:
> Am 10.09.2012 16:50, schrieb Don Slutz:
> > On 09/10/12 09:04, Igor Mammedov wrote:
> >> But question unrelated to this patch is still stand if ia64 is valid
> >> bit for
> >> 01.EDX[30]?
> >>
> >>
> > Intel® Processor Identification
> > and the CPUID Instruction
> > Application Note 485
> > January 2006
> >
> > Order Number: 241618-030
> >
> > ...
> >
> > Updated Table 3-5 to include the feature flag definition (EDX[30]) for
> > IA64 capabilities.
> > ...
> > 30 IA64 IA64 Capabilities The processor is a member of the Intel®
> > Itanium® processor family
> > and currently operating in IA32 emulation mode.
> >
> > ---------------
> >
> > Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and
> > http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64)
>
> Don't those semantics contradict the use in qemu-system-x86_64 or
> qemu-system-i386 rather than qemu-system-ia64 then? We don't model ia64
> CPUs here (just like we don't model ppc64 CPUs in ppc) so the flag could
> never become 1 IIUC.
Correct, and the bit is always filtered out on both TCG and KVM modes.
The name is in the table because we know the name/meaning of that
feature bit, but it's impossible to enable it.
That said, I don't mind removing it from the table just to avoid
confusion, but I also wouldn't mind keeping it (as it's harmless).
--
Eduardo
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-10 15:07 ` Eduardo Habkost
@ 2012-09-10 15:13 ` Andreas Färber
0 siblings, 0 replies; 29+ messages in thread
From: Andreas Färber @ 2012-09-10 15:13 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Igor Mammedov, Don Slutz, qemu-devel, Anthony Liguori, Peter Maydell
Am 10.09.2012 17:07, schrieb Eduardo Habkost:
> On Mon, Sep 10, 2012 at 04:58:39PM +0200, Andreas Färber wrote:
>> Am 10.09.2012 16:50, schrieb Don Slutz:
>>> On 09/10/12 09:04, Igor Mammedov wrote:
>>>> But question unrelated to this patch is still stand if ia64 is valid
>>>> bit for
>>>> 01.EDX[30]?
>>>>
>>>>
>>> Intel® Processor Identification
>>> and the CPUID Instruction
>>> Application Note 485
>>> January 2006
>>>
>>> Order Number: 241618-030
>>>
>>> ...
>>>
>>> Updated Table 3-5 to include the feature flag definition (EDX[30]) for
>>> IA64 capabilities.
>>> ...
>>> 30 IA64 IA64 Capabilities The processor is a member of the Intel®
>>> Itanium® processor family
>>> and currently operating in IA32 emulation mode.
>>>
>>> ---------------
>>>
>>> Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and
>>> http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64)
>>
>> Don't those semantics contradict the use in qemu-system-x86_64 or
>> qemu-system-i386 rather than qemu-system-ia64 then? We don't model ia64
>> CPUs here (just like we don't model ppc64 CPUs in ppc) so the flag could
>> never become 1 IIUC.
>
> Correct, and the bit is always filtered out on both TCG and KVM modes.
> The name is in the table because we know the name/meaning of that
> feature bit, but it's impossible to enable it.
>
> That said, I don't mind removing it from the table just to avoid
> confusion, but I also wouldn't mind keeping it (as it's harmless).
No objections from my side against having it for informational purpose.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2
2012-09-05 20:41 [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Eduardo Habkost
` (6 preceding siblings ...)
2012-09-05 20:41 ` [Qemu-devel] [PATCH 7/7] i386: kill cpudef config section support Eduardo Habkost
@ 2012-09-10 15:17 ` Andreas Färber
2012-09-10 15:30 ` Igor Mammedov
2012-09-10 15:46 ` [Qemu-devel] CPU code roadmap (was Re: [PATCH 0/7] x86 CPU patches that didn't get into 1.2) Eduardo Habkost
2012-09-17 17:29 ` [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Andreas Färber
8 siblings, 2 replies; 29+ messages in thread
From: Andreas Färber @ 2012-09-10 15:17 UTC (permalink / raw)
To: Eduardo Habkost; +Cc: Peter Maydell, qemu-devel, Anthony Liguori, Igor Mammedov
Hi Eduardo,
Am 05.09.2012 22:41, schrieb Eduardo Habkost:
> This is a small queue of patches that I consider "ready to go", that didn't
> enter QEMU 1.2.
There's so many x86 CPU series on the list again... Am I understanding
correctly that this is the start, applying directly to master? Or does
it have further prerequisites?
Would be great to get one batch reviewed and applied, so that we can all
test and review from the same base. ;)
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2
2012-09-10 15:17 ` [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Andreas Färber
@ 2012-09-10 15:30 ` Igor Mammedov
2012-09-10 15:46 ` [Qemu-devel] CPU code roadmap (was Re: [PATCH 0/7] x86 CPU patches that didn't get into 1.2) Eduardo Habkost
1 sibling, 0 replies; 29+ messages in thread
From: Igor Mammedov @ 2012-09-10 15:30 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Eduardo Habkost, Anthony Liguori, qemu-devel
On Mon, 10 Sep 2012 17:17:03 +0200
Andreas Färber <afaerber@suse.de> wrote:
> Hi Eduardo,
>
> Am 05.09.2012 22:41, schrieb Eduardo Habkost:
> > This is a small queue of patches that I consider "ready to go", that
> > didn't enter QEMU 1.2.
>
> There's so many x86 CPU series on the list again... Am I understanding
> correctly that this is the start, applying directly to master? Or does
> it have further prerequisites?
Yes, it's the start without prerequisites.
then goes "[PATCH 0/5] i386: cpu: remove duplicate feature names"
and then "[PATCH 00/22 v2] target-i386: convert CPU features into properties"
> Would be great to get one batch reviewed and applied, so that we can all
> test and review from the same base. ;)
>
> Regards,
> Andreas
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] CPU code roadmap (was Re: [PATCH 0/7] x86 CPU patches that didn't get into 1.2)
2012-09-10 15:17 ` [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Andreas Färber
2012-09-10 15:30 ` Igor Mammedov
@ 2012-09-10 15:46 ` Eduardo Habkost
2012-09-11 14:59 ` Eduardo Habkost
1 sibling, 1 reply; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-10 15:46 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Don Slutz, qemu-devel, Anthony Liguori, Igor Mammedov
On Mon, Sep 10, 2012 at 05:17:03PM +0200, Andreas Färber wrote:
> Hi Eduardo,
>
> Am 05.09.2012 22:41, schrieb Eduardo Habkost:
> > This is a small queue of patches that I consider "ready to go", that didn't
> > enter QEMU 1.2.
>
> There's so many x86 CPU series on the list again... Am I understanding
> correctly that this is the start, applying directly to master? Or does
> it have further prerequisites?
Correct. This one does not have any prerequisites and used 'master' as
base. But it is a prerequisite for many other series.
>
> Would be great to get one batch reviewed and applied, so that we can all
> test and review from the same base. ;)
True. At the same time, I wouldn't like to hold from submitting patches
for review because others are still pending.
Let's try to be very clear about dependencies on each series, though, to
avoid confusion (I could have been more explicit and mentioned that this
can be applied directly to master).
I am aware of three "properly ordered" series on the list, by now:
1) This one ("x86 CPU patches that didn't get into 1.2")
2) "unduplicate feature names" series, from myself, explicitly depending
on (1)
3) "CPU properties" series, from Igor, explicitly depending on (1) and (2)
And I am aware of the following series, that still need to be
rebased/resubmitted:
- "Allow changing of Hypervisor CPUIDs" from Don Slutz
- CPU model classes, from myself
- APIC ID / topology fixes, from myself (previously sent as RFC)
- Make X86CPU child of DeviceState (there are 3 proposals today, and I
don't know which one will be adopted
Also, I have plans to submit series for the following:
- Call GET_SUPPORTED_CPUID only once and store the results
- General kvm_arch_get_supported_cpuid() refactor/cleanup
- General refactoring of feature flag handling, to use a generic
"feature words" structure
- Fix -cpu check/enforce to properly use GET_SUPPORTED_CPUID
- Fix -cpu host to properly use GET_SUPPORTED_CPUID
- Addition of feature flag names for CPUID leaf 7
Anything else I am missing?
--
Eduardo
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] CPU code roadmap (was Re: [PATCH 0/7] x86 CPU patches that didn't get into 1.2)
2012-09-10 15:46 ` [Qemu-devel] CPU code roadmap (was Re: [PATCH 0/7] x86 CPU patches that didn't get into 1.2) Eduardo Habkost
@ 2012-09-11 14:59 ` Eduardo Habkost
0 siblings, 0 replies; 29+ messages in thread
From: Eduardo Habkost @ 2012-09-11 14:59 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Don Slutz, qemu-devel, Anthony Liguori, Igor Mammedov
On Mon, Sep 10, 2012 at 12:46:18PM -0300, Eduardo Habkost wrote:
> On Mon, Sep 10, 2012 at 05:17:03PM +0200, Andreas Färber wrote:
> > Hi Eduardo,
> >
> > Am 05.09.2012 22:41, schrieb Eduardo Habkost:
> > > This is a small queue of patches that I consider "ready to go", that didn't
> > > enter QEMU 1.2.
> >
> > There's so many x86 CPU series on the list again... Am I understanding
> > correctly that this is the start, applying directly to master? Or does
> > it have further prerequisites?
>
> Correct. This one does not have any prerequisites and used 'master' as
> base. But it is a prerequisite for many other series.
>
>
> >
> > Would be great to get one batch reviewed and applied, so that we can all
> > test and review from the same base. ;)
>
> True. At the same time, I wouldn't like to hold from submitting patches
> for review because others are still pending.
>
> Let's try to be very clear about dependencies on each series, though, to
> avoid confusion (I could have been more explicit and mentioned that this
> can be applied directly to master).
>
> I am aware of three "properly ordered" series on the list, by now:
>
> 1) This one ("x86 CPU patches that didn't get into 1.2")
> 2) "unduplicate feature names" series, from myself, explicitly depending
> on (1)
> 3) "CPU properties" series, from Igor, explicitly depending on (1) and (2)
New item:
4) [PATCH v2 0/4] Allow changing of Hypervisor CPUIDs
http://article.gmane.org/gmane.comp.emulators.kvm.devel/97991
I am keeping the current queue at:
https://github.com/ehabkost/qemu/commits/cpu-queue
Note that "cpu-queue" is going to be a rebased-often branch (with
frequent non-fast-forward updates), as it is just a place where I am
storing the work in progress while it's being reviewed in the list.
>
> And I am aware of the following series, that still need to be
> rebased/resubmitted:
>
> - "Allow changing of Hypervisor CPUIDs" from Don Slutz
> - CPU model classes, from myself
> - APIC ID / topology fixes, from myself (previously sent as RFC)
> - Make X86CPU child of DeviceState (there are 3 proposals today, and I
> don't know which one will be adopted
>
> Also, I have plans to submit series for the following:
>
> - Call GET_SUPPORTED_CPUID only once and store the results
> - General kvm_arch_get_supported_cpuid() refactor/cleanup
> - General refactoring of feature flag handling, to use a generic
> "feature words" structure
> - Fix -cpu check/enforce to properly use GET_SUPPORTED_CPUID
> - Fix -cpu host to properly use GET_SUPPORTED_CPUID
> - Addition of feature flag names for CPUID leaf 7
>
> Anything else I am missing?
>
> --
> Eduardo
>
--
Eduardo
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C
2012-09-10 13:40 ` Igor Mammedov
@ 2012-09-11 19:45 ` Don Slutz
0 siblings, 0 replies; 29+ messages in thread
From: Don Slutz @ 2012-09-11 19:45 UTC (permalink / raw)
To: Igor Mammedov
Cc: Peter Maydell, Andreas Färber, Eduardo Habkost,
Anthony Liguori, qemu-devel
On 09/10/12 09:40, Igor Mammedov wrote:
> On Wed, 5 Sep 2012 17:41:10 -0300
> Eduardo Habkost <ehabkost@redhat.com> wrote:
>
>> Those models are maintained by QEMU and may require compatibility code
>> to be added when making some changes. Keeping the data in the C source
>> code should make it simpler to handle those details.
>>
>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
>> ---
>> sysconfigs/target/cpus-x86_64.conf | 129 +---------------------
>> target-i386/cpu.c | 219
>> +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+),
>> 128 deletions(-)
>>
>> diff --git a/sysconfigs/target/cpus-x86_64.conf
>> b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644
>> --- a/sysconfigs/target/cpus-x86_64.conf
>> +++ b/sysconfigs/target/cpus-x86_64.conf
>> @@ -1,128 +1 @@
>> -# x86 CPU MODELS
>> -
>> -[cpudef]
>> - name = "Conroe"
>> - level = "2"
>> - vendor = "GenuineIntel"
>> - family = "6"
>> - model = "2"
>> - stepping = "3"
>> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>> sep apic cx8 mce pae msr tsc pse de fpu"
>> - feature_ecx = "ssse3 sse3"
>> - extfeature_edx = "i64 xd syscall"
>> - extfeature_ecx = "lahf_lm"
>> - xlevel = "0x8000000A"
>> - model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
>> -
>> -[cpudef]
>> - name = "Penryn"
>> - level = "2"
>> - vendor = "GenuineIntel"
>> - family = "6"
>> - model = "2"
>> - stepping = "3"
>> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>> sep apic cx8 mce pae msr tsc pse de fpu"
>> - feature_ecx = "sse4.1 cx16 ssse3 sse3"
>> - extfeature_edx = "i64 xd syscall"
>> - extfeature_ecx = "lahf_lm"
>> - xlevel = "0x8000000A"
>> - model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
>> -
>> -[cpudef]
>> - name = "Nehalem"
>> - level = "2"
>> - vendor = "GenuineIntel"
>> - family = "6"
>> - model = "2"
>> - stepping = "3"
>> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>> sep apic cx8 mce pae msr tsc pse de fpu"
>> - feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
>> - extfeature_edx = "i64 syscall xd"
>> - extfeature_ecx = "lahf_lm"
>> - xlevel = "0x8000000A"
>> - model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
>> -
>> -[cpudef]
>> - name = "Westmere"
>> - level = "11"
>> - vendor = "GenuineIntel"
>> - family = "6"
>> - model = "44"
>> - stepping = "1"
>> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>> sep apic cx8 mce pae msr tsc pse de fpu"
>> - feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
>> - extfeature_edx = "i64 syscall xd"
>> - extfeature_ecx = "lahf_lm"
>> - xlevel = "0x8000000A"
>> - model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
>> -
>> -[cpudef]
>> - name = "SandyBridge"
>> - level = "0xd"
>> - vendor = "GenuineIntel"
>> - family = "6"
>> - model = "42"
>> - stepping = "1"
>> - feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>> sep apic cx8 mce pae msr tsc pse de fpu"
>> - feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1
>> cx16 ssse3 pclmulqdq sse3"
>> - extfeature_edx = "i64 rdtscp nx syscall "
>> - extfeature_ecx = "lahf_lm"
>> - xlevel = "0x8000000A"
>> - model_id = "Intel Xeon E312xx (Sandy Bridge)"
>> -
>> -[cpudef]
>> - name = "Opteron_G1"
>> - level = "5"
>> - vendor = "AuthenticAMD"
>> - family = "15"
>> - model = "6"
>> - stepping = "1"
>> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>> sep apic cx8 mce pae msr tsc pse de fpu"
>> - feature_ecx = "sse3"
>> - extfeature_edx = "lm fxsr mmx nx pse36 pat cmov mca pge mtrr syscall
>> apic cx8 mce pae msr tsc pse de fpu"
>> - extfeature_ecx = " "
>> - xlevel = "0x80000008"
>> - model_id = "AMD Opteron 240 (Gen 1 Class Opteron)"
>> -
>> -[cpudef]
>> - name = "Opteron_G2"
>> - level = "5"
>> - vendor = "AuthenticAMD"
>> - family = "15"
>> - model = "6"
>> - stepping = "1"
>> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>> sep apic cx8 mce pae msr tsc pse de fpu"
>> - feature_ecx = "cx16 sse3"
>> - extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr
>> syscall apic cx8 mce pae msr tsc pse de fpu"
>> - extfeature_ecx = "svm lahf_lm"
>> - xlevel = "0x80000008"
>> - model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)"
>> -
>> -[cpudef]
>> - name = "Opteron_G3"
>> - level = "5"
>> - vendor = "AuthenticAMD"
>> - family = "15"
>> - model = "6"
>> - stepping = "1"
>> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>> sep apic cx8 mce pae msr tsc pse de fpu"
>> - feature_ecx = "popcnt cx16 monitor sse3"
>> - extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr
>> syscall apic cx8 mce pae msr tsc pse de fpu"
>> - extfeature_ecx = "misalignsse sse4a abm svm lahf_lm"
>> - xlevel = "0x80000008"
>> - model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)"
>> -
>> -[cpudef]
>> - name = "Opteron_G4"
>> - level = "0xd"
>> - vendor = "AuthenticAMD"
>> - family = "21"
>> - model = "1"
>> - stepping = "2"
>> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>> sep apic cx8 mce pae msr tsc pse de fpu"
>> - feature_ecx = "avx xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 pclmulqdq
>> sse3"
>> - extfeature_edx = "lm rdtscp pdpe1gb fxsr mmx nx pse36 pat cmov mca pge
>> mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
>> - extfeature_ecx = " fma4 xop 3dnowprefetch misalignsse sse4a abm svm
>> lahf_lm"
>> - xlevel = "0x8000001A"
>> - model_id = "AMD Opteron 62xx class CPU"
>> -
>> +# The CPU models from this file are now built-in in the QEMU source code
>> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
>> index d2af0ff..73302d8 100644
>> --- a/target-i386/cpu.c
>> +++ b/target-i386/cpu.c
>> @@ -490,6 +490,225 @@ static x86_def_t builtin_x86_defs[] = {
>> .xlevel = 0x8000000A,
>> .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
>> },
>> + {
>> + .name = "Conroe",
>> + .level = 2,
>> + .vendor1 = CPUID_VENDOR_INTEL_1,
>> + .vendor2 = CPUID_VENDOR_INTEL_2,
>> + .vendor3 = CPUID_VENDOR_INTEL_3,
>> + .family = 6,
>> + .model = 2,
>> + .stepping = 3,
>> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
>> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
>> CPUID_MCA |
>> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
>> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>> + CPUID_DE | CPUID_FP87,
>> + .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
>> CPUID_EXT2_SYSCALL,
>> + .ext3_features = CPUID_EXT3_LAHF_LM,
>> + .xlevel = 0x8000000A,
>> + .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
>> + },
>> + {
>> + .name = "Penryn",
>> + .level = 2,
>> + .vendor1 = CPUID_VENDOR_INTEL_1,
>> + .vendor2 = CPUID_VENDOR_INTEL_2,
>> + .vendor3 = CPUID_VENDOR_INTEL_3,
>> + .family = 6,
>> + .model = 2,
>> + .stepping = 3,
>> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
>> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
>> CPUID_MCA |
>> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
>> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>> + CPUID_DE | CPUID_FP87,
>> + .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3
>> |
>> + CPUID_EXT_SSE3,
>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
>> CPUID_EXT2_SYSCALL,
>> + .ext3_features = CPUID_EXT3_LAHF_LM,
>> + .xlevel = 0x8000000A,
>> + .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
>> + },
>> + {
>> + .name = "Nehalem",
>> + .level = 2,
>> + .vendor1 = CPUID_VENDOR_INTEL_1,
>> + .vendor2 = CPUID_VENDOR_INTEL_2,
>> + .vendor3 = CPUID_VENDOR_INTEL_3,
>> + .family = 6,
>> + .model = 2,
>> + .stepping = 3,
>> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
>> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
>> CPUID_MCA |
>> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
>> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>> + CPUID_DE | CPUID_FP87,
>> + .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
>> CPUID_EXT_SSE41 |
>> + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
>> CPUID_EXT2_NX,
>> + .ext3_features = CPUID_EXT3_LAHF_LM,
>> + .xlevel = 0x8000000A,
>> + .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
>> + },
>> + {
>> + .name = "Westmere",
>> + .level = 11,
>> + .vendor1 = CPUID_VENDOR_INTEL_1,
>> + .vendor2 = CPUID_VENDOR_INTEL_2,
>> + .vendor3 = CPUID_VENDOR_INTEL_3,
>> + .family = 6,
>> + .model = 44,
>> + .stepping = 1,
>> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
>> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
>> CPUID_MCA |
>> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
>> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>> + CPUID_DE | CPUID_FP87,
>> + .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42
>> |
>> + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
>> + CPUID_EXT_SSE3,
>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
>> CPUID_EXT2_NX,
>> + .ext3_features = CPUID_EXT3_LAHF_LM,
>> + .xlevel = 0x8000000A,
>> + .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
>> + },
>> + {
>> + .name = "SandyBridge",
>> + .level = 0xd,
>> + .vendor1 = CPUID_VENDOR_INTEL_1,
>> + .vendor2 = CPUID_VENDOR_INTEL_2,
>> + .vendor3 = CPUID_VENDOR_INTEL_3,
>> + .family = 6,
>> + .model = 42,
>> + .stepping = 1,
>> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
>> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
>> CPUID_MCA |
>> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
>> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>> + CPUID_DE | CPUID_FP87,
>> + .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
>> + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
>> + CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
>> + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
>> + CPUID_EXT_SSE3,
>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX
>> |
>> + CPUID_EXT2_SYSCALL,
>> + .ext3_features = CPUID_EXT3_LAHF_LM,
>> + .xlevel = 0x8000000A,
>> + .model_id = "Intel Xeon E312xx (Sandy Bridge)",
>> + },
>> + {
>> + .name = "Opteron_G1",
>> + .level = 5,
>> + .vendor1 = CPUID_VENDOR_AMD_1,
>> + .vendor2 = CPUID_VENDOR_AMD_2,
>> + .vendor3 = CPUID_VENDOR_AMD_3,
>> + .family = 15,
>> + .model = 6,
>> + .stepping = 1,
>> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
>> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
>> CPUID_MCA |
>> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
>> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>> + CPUID_DE | CPUID_FP87,
>> + .ext_features = CPUID_EXT_SSE3,
>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
>> + CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
>> + CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
>> + CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
>> + CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE |
>> CPUID_EXT2_MSR |
>> + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE |
>> CPUID_EXT2_FPU,
>> + .xlevel = 0x80000008,
>> + .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
>> + },
>> + {
>> + .name = "Opteron_G2",
>> + .level = 5,
>> + .vendor1 = CPUID_VENDOR_AMD_1,
>> + .vendor2 = CPUID_VENDOR_AMD_2,
>> + .vendor3 = CPUID_VENDOR_AMD_3,
>> + .family = 15,
>> + .model = 6,
>> + .stepping = 1,
>> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
>> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
>> CPUID_MCA |
>> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
>> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>> + CPUID_DE | CPUID_FP87,
>> + .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
>> CPUID_EXT2_FXSR |
>> + CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
>> + CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
>> + CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
>> + CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
>> + CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC |
>> CPUID_EXT2_PSE |
>> + CPUID_EXT2_DE | CPUID_EXT2_FPU,
>> + .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
>> + .xlevel = 0x80000008,
>> + .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
>> + },
>> + {
>> + .name = "Opteron_G3",
>> + .level = 5,
>> + .vendor1 = CPUID_VENDOR_AMD_1,
>> + .vendor2 = CPUID_VENDOR_AMD_2,
>> + .vendor3 = CPUID_VENDOR_AMD_3,
>> + .family = 15,
>> + .model = 6,
>> + .stepping = 1,
>> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
>> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
>> CPUID_MCA |
>> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
>> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>> + CPUID_DE | CPUID_FP87,
>> + .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 |
>> CPUID_EXT_MONITOR |
>> + CPUID_EXT_SSE3,
>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
>> CPUID_EXT2_FXSR |
>> + CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
>> + CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
>> + CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
>> + CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
>> + CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC |
>> CPUID_EXT2_PSE |
>> + CPUID_EXT2_DE | CPUID_EXT2_FPU,
>> + .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
>> + CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
>> + .xlevel = 0x80000008,
>> + .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
>> + },
>> + {
>> + .name = "Opteron_G4",
>> + .level = 0xd,
>> + .vendor1 = CPUID_VENDOR_AMD_1,
>> + .vendor2 = CPUID_VENDOR_AMD_2,
>> + .vendor3 = CPUID_VENDOR_AMD_3,
>> + .family = 21,
>> + .model = 1,
>> + .stepping = 2,
>> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
>> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
>> CPUID_MCA |
>> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
>> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>> + CPUID_DE | CPUID_FP87,
>> + .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
>> + CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
>> + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
>> + CPUID_EXT_SSE3,
>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
>> + CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
>> + CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
>> + CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
>> + CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
>> + CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE |
>> CPUID_EXT2_MSR |
>> + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE |
>> CPUID_EXT2_FPU,
>> + .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
>> + CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
>> + CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
>> + CPUID_EXT3_LAHF_LM,
>> + .xlevel = 0x8000001A,
>> + .model_id = "AMD Opteron 62xx class CPU",
>> + },
>> };
>>
>> static int cpu_x86_fill_model_id(char *str)
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
>
Reviewed-by: Don Slutz <Don@CloudSwitch.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 6/7] x86_cpudef_setup: coding style change
2012-09-05 20:41 ` [Qemu-devel] [PATCH 6/7] x86_cpudef_setup: coding style change Eduardo Habkost
@ 2012-09-11 19:45 ` Don Slutz
0 siblings, 0 replies; 29+ messages in thread
From: Don Slutz @ 2012-09-11 19:45 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, Igor Mammedov, qemu-devel, Anthony Liguori,
Andreas Färber
On 09/05/12 16:41, Eduardo Habkost wrote:
> Make source code lines shorter.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> target-i386/cpu.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 73302d8..e13e6d5 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -1513,20 +1513,23 @@ void x86_cpudef_setup(void)
> static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
>
> for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
> - builtin_x86_defs[i].next = x86_defs;
> - builtin_x86_defs[i].flags = 1;
> + x86_def_t *def = &builtin_x86_defs[i];
> + def->next = x86_defs;
> + def->flags = 1;
>
> /* Look for specific "cpudef" models that */
> /* have the QEMU version in .model_id */
> for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
> - if (strcmp(model_with_versions[j], builtin_x86_defs[i].name) == 0) {
> - pstrcpy(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), "QEMU Virtual CPU version ");
> - pstrcat(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), qemu_get_version());
> + if (strcmp(model_with_versions[j], def->name) == 0) {
> + pstrcpy(def->model_id, sizeof(def->model_id),
> + "QEMU Virtual CPU version ");
> + pstrcat(def->model_id, sizeof(def->model_id),
> + qemu_get_version());
> break;
> }
> }
>
> - x86_defs = &builtin_x86_defs[i];
> + x86_defs = def;
> }
> #if !defined(CONFIG_USER_ONLY)
> qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
Reviewed-by: Don Slutz <Don@CloudSwitch.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2
2012-09-05 20:41 [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Eduardo Habkost
` (7 preceding siblings ...)
2012-09-10 15:17 ` [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Andreas Färber
@ 2012-09-17 17:29 ` Andreas Färber
8 siblings, 0 replies; 29+ messages in thread
From: Andreas Färber @ 2012-09-17 17:29 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, Don Slutz, qemu-devel, Anthony Liguori, Igor Mammedov
Hi Eduardo,
Am 05.09.2012 22:41, schrieb Eduardo Habkost:
> This is a small queue of patches that I consider "ready to go", that didn't
> enter QEMU 1.2.
>
> Eduardo Habkost (5):
> i386: add missing CPUID_* constants
> move CPU models from cpus-x86_64.conf to C
> eliminate cpus-x86_64.conf file
> x86_cpudef_setup: coding style change
> i386: kill cpudef config section support
>
> Peter Maydell (2):
> target-i386: Fold -cpu ?cpuid, ?model output into -cpu help, drop
> ?dump
> Drop cpu_list_id macro
Finished walking through these now and concur that they are ready to go!
I've queued them on my qom-cpu branch (enforcing a consistent
"target-i386" subject where applicable; dropping my pending field
movements for now) and intend to send a pull shortly.
https://github.com/afaerber/qemu-cpu/commits/qom-cpu
To address Igor's setscalar() review comment, I appended this follow-up:
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 7c0953f..c2e65ea 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1393,18 +1393,6 @@ int cpu_x86_register(X86CPU *cpu, const char
*cpu_model)
#if !defined(CONFIG_USER_ONLY)
-/* interpret radix and convert from string to arbitrary scalar,
- * otherwise flag failure
- */
-#define setscalar(pval, str, perr) \
-{ \
- char *pend; \
- unsigned long ul; \
- \
- ul = strtoul(str, &pend, 0); \
- *str && !*pend ? (*pval = ul) : (*perr = 1); \
-}
-
void cpu_clear_apic_feature(CPUX86State *env)
{
env->cpuid_features &= ~CPUID_APIC;
Thanks for helping sort these things out,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply related [flat|nested] 29+ messages in thread
end of thread, other threads:[~2012-09-17 17:29 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-09-05 20:41 [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Eduardo Habkost
2012-09-05 20:41 ` [Qemu-devel] [PATCH 1/7] target-i386: Fold -cpu ?cpuid, ?model output into -cpu help, drop ?dump Eduardo Habkost
2012-09-10 9:40 ` Igor Mammedov
2012-09-05 20:41 ` [Qemu-devel] [PATCH 2/7] Drop cpu_list_id macro Eduardo Habkost
2012-09-10 9:46 ` Igor Mammedov
2012-09-05 20:41 ` [Qemu-devel] [PATCH 3/7] i386: add missing CPUID_* constants Eduardo Habkost
2012-09-10 9:57 ` Igor Mammedov
2012-09-05 20:41 ` [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C Eduardo Habkost
2012-09-10 12:18 ` Igor Mammedov
2012-09-10 12:31 ` Igor Mammedov
2012-09-10 13:04 ` Igor Mammedov
2012-09-10 14:50 ` Don Slutz
2012-09-10 14:58 ` Andreas Färber
2012-09-10 15:07 ` Eduardo Habkost
2012-09-10 15:13 ` Andreas Färber
2012-09-10 15:04 ` Eduardo Habkost
2012-09-10 13:40 ` Igor Mammedov
2012-09-11 19:45 ` Don Slutz
2012-09-05 20:41 ` [Qemu-devel] [PATCH 5/7] eliminate cpus-x86_64.conf file Eduardo Habkost
2012-09-10 13:46 ` Igor Mammedov
2012-09-05 20:41 ` [Qemu-devel] [PATCH 6/7] x86_cpudef_setup: coding style change Eduardo Habkost
2012-09-11 19:45 ` Don Slutz
2012-09-05 20:41 ` [Qemu-devel] [PATCH 7/7] i386: kill cpudef config section support Eduardo Habkost
2012-09-10 14:20 ` Igor Mammedov
2012-09-10 15:17 ` [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Andreas Färber
2012-09-10 15:30 ` Igor Mammedov
2012-09-10 15:46 ` [Qemu-devel] CPU code roadmap (was Re: [PATCH 0/7] x86 CPU patches that didn't get into 1.2) Eduardo Habkost
2012-09-11 14:59 ` Eduardo Habkost
2012-09-17 17:29 ` [Qemu-devel] [PATCH 0/7] x86 CPU patches that didn't get into 1.2 Andreas Färber
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