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From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>,
	Jordan Crouse <jcrouse@codeaurora.org>,
	Rob Clark <robdclark@gmail.com>
Cc: iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, Sean Paul <sean@poorly.run>,
	Sharat Masetty <smasetty@codeaurora.org>,
	Akhil P Oommen <akhilpo@codeaurora.org>,
	freedreno@lists.freedesktop.org, Daniel Vetter <daniel@ffwll.ch>,
	David Airlie <airlied@linux.ie>,
	Emil Velikov <emil.velikov@collabora.com>,
	dri-devel@lists.freedesktop.org,
	linux-arm-kernel@lists.infradead.org,
	"Kristian H . Kristensen" <hoegsberg@google.com>,
	Stephen Boyd <swboyd@chromium.org>,
	Matthias Kaehlcke <mka@chromium.org>,
	Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Subject: [PATCHv3 3/7] iommu/arm-smmu: Add domain attribute for system cache
Date: Mon, 29 Jun 2020 21:22:46 +0530	[thread overview]
Message-ID: <134a67a32813dba111e9b888244d8ca44ab15f84.1593344119.git.saiprakash.ranjan@codeaurora.org> (raw)
In-Reply-To: <cover.1593344119.git.saiprakash.ranjan@codeaurora.org>

Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/iommu/arm-smmu.c | 17 +++++++++++++++++
 drivers/iommu/arm-smmu.h |  1 +
 include/linux/iommu.h    |  1 +
 3 files changed, 19 insertions(+)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index b2564f93d685..71b6f7038423 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -897,6 +897,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 			goto out_unlock;
 	}
 
+	if (smmu_domain->sys_cache)
+		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_SYS_CACHE;
+
 	if (smmu_domain->non_strict)
 		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
 
@@ -1732,6 +1735,9 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
 		case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
 			*(int *)data = smmu_domain->non_strict;
 			return 0;
+		case DOMAIN_ATTR_SYS_CACHE:
+			*((int *)data) = smmu_domain->sys_cache;
+			return 0;
 		default:
 			return -ENODEV;
 		}
@@ -1763,6 +1769,17 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
 			else
 				smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
 			break;
+		case DOMAIN_ATTR_SYS_CACHE:
+			if (smmu_domain->smmu) {
+				ret = -EPERM;
+				goto out_unlock;
+			}
+
+			if (*((int *)data))
+				smmu_domain->sys_cache = true;
+			else
+				smmu_domain->sys_cache = false;
+			break;
 		default:
 			ret = -ENODEV;
 		}
diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index 4a335ef3d97a..bbae48bdc022 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -348,6 +348,7 @@ struct arm_smmu_domain {
 	struct iommu_domain		domain;
 	struct device			*dev;	/* Device attached to this domain */
 	bool				aux;
+	bool				sys_cache;
 };
 
 struct arm_smmu_cb {
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 2388117641f1..a48edbebe3cb 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -125,6 +125,7 @@ enum iommu_attr {
 	DOMAIN_ATTR_NESTING,	/* two stages of translation */
 	DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE,
 	DOMAIN_ATTR_PGTABLE_CFG,
+	DOMAIN_ATTR_SYS_CACHE,
 	DOMAIN_ATTR_MAX,
 };
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


WARNING: multiple messages have this Message-ID (diff)
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>,
	Jordan Crouse <jcrouse@codeaurora.org>,
	Rob Clark <robdclark@gmail.com>
Cc: freedreno@lists.freedesktop.org, David Airlie <airlied@linux.ie>,
	linux-arm-msm@vger.kernel.org,
	Sharat Masetty <smasetty@codeaurora.org>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Akhil P Oommen <akhilpo@codeaurora.org>,
	iommu@lists.linux-foundation.org,
	Matthias Kaehlcke <mka@chromium.org>,
	"Kristian H . Kristensen" <hoegsberg@google.com>,
	Daniel Vetter <daniel@ffwll.ch>,
	Stephen Boyd <swboyd@chromium.org>, Sean Paul <sean@poorly.run>,
	linux-arm-kernel@lists.infradead.org,
	Emil Velikov <emil.velikov@collabora.com>
Subject: [PATCHv3 3/7] iommu/arm-smmu: Add domain attribute for system cache
Date: Mon, 29 Jun 2020 21:22:46 +0530	[thread overview]
Message-ID: <134a67a32813dba111e9b888244d8ca44ab15f84.1593344119.git.saiprakash.ranjan@codeaurora.org> (raw)
In-Reply-To: <cover.1593344119.git.saiprakash.ranjan@codeaurora.org>

Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/iommu/arm-smmu.c | 17 +++++++++++++++++
 drivers/iommu/arm-smmu.h |  1 +
 include/linux/iommu.h    |  1 +
 3 files changed, 19 insertions(+)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index b2564f93d685..71b6f7038423 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -897,6 +897,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 			goto out_unlock;
 	}
 
+	if (smmu_domain->sys_cache)
+		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_SYS_CACHE;
+
 	if (smmu_domain->non_strict)
 		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
 
@@ -1732,6 +1735,9 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
 		case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
 			*(int *)data = smmu_domain->non_strict;
 			return 0;
+		case DOMAIN_ATTR_SYS_CACHE:
+			*((int *)data) = smmu_domain->sys_cache;
+			return 0;
 		default:
 			return -ENODEV;
 		}
@@ -1763,6 +1769,17 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
 			else
 				smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
 			break;
+		case DOMAIN_ATTR_SYS_CACHE:
+			if (smmu_domain->smmu) {
+				ret = -EPERM;
+				goto out_unlock;
+			}
+
+			if (*((int *)data))
+				smmu_domain->sys_cache = true;
+			else
+				smmu_domain->sys_cache = false;
+			break;
 		default:
 			ret = -ENODEV;
 		}
diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index 4a335ef3d97a..bbae48bdc022 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -348,6 +348,7 @@ struct arm_smmu_domain {
 	struct iommu_domain		domain;
 	struct device			*dev;	/* Device attached to this domain */
 	bool				aux;
+	bool				sys_cache;
 };
 
 struct arm_smmu_cb {
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 2388117641f1..a48edbebe3cb 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -125,6 +125,7 @@ enum iommu_attr {
 	DOMAIN_ATTR_NESTING,	/* two stages of translation */
 	DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE,
 	DOMAIN_ATTR_PGTABLE_CFG,
+	DOMAIN_ATTR_SYS_CACHE,
 	DOMAIN_ATTR_MAX,
 };
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>,
	Jordan Crouse <jcrouse@codeaurora.org>,
	Rob Clark <robdclark@gmail.com>
Cc: freedreno@lists.freedesktop.org,
	Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
	David Airlie <airlied@linux.ie>,
	linux-arm-msm@vger.kernel.org,
	Sharat Masetty <smasetty@codeaurora.org>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Akhil P Oommen <akhilpo@codeaurora.org>,
	iommu@lists.linux-foundation.org,
	Matthias Kaehlcke <mka@chromium.org>,
	"Kristian H . Kristensen" <hoegsberg@google.com>,
	Daniel Vetter <daniel@ffwll.ch>,
	Stephen Boyd <swboyd@chromium.org>, Sean Paul <sean@poorly.run>,
	linux-arm-kernel@lists.infradead.org,
	Emil Velikov <emil.velikov@collabora.com>
Subject: [PATCHv3 3/7] iommu/arm-smmu: Add domain attribute for system cache
Date: Mon, 29 Jun 2020 21:22:46 +0530	[thread overview]
Message-ID: <134a67a32813dba111e9b888244d8ca44ab15f84.1593344119.git.saiprakash.ranjan@codeaurora.org> (raw)
In-Reply-To: <cover.1593344119.git.saiprakash.ranjan@codeaurora.org>

Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/iommu/arm-smmu.c | 17 +++++++++++++++++
 drivers/iommu/arm-smmu.h |  1 +
 include/linux/iommu.h    |  1 +
 3 files changed, 19 insertions(+)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index b2564f93d685..71b6f7038423 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -897,6 +897,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 			goto out_unlock;
 	}
 
+	if (smmu_domain->sys_cache)
+		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_SYS_CACHE;
+
 	if (smmu_domain->non_strict)
 		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
 
@@ -1732,6 +1735,9 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
 		case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
 			*(int *)data = smmu_domain->non_strict;
 			return 0;
+		case DOMAIN_ATTR_SYS_CACHE:
+			*((int *)data) = smmu_domain->sys_cache;
+			return 0;
 		default:
 			return -ENODEV;
 		}
@@ -1763,6 +1769,17 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
 			else
 				smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
 			break;
+		case DOMAIN_ATTR_SYS_CACHE:
+			if (smmu_domain->smmu) {
+				ret = -EPERM;
+				goto out_unlock;
+			}
+
+			if (*((int *)data))
+				smmu_domain->sys_cache = true;
+			else
+				smmu_domain->sys_cache = false;
+			break;
 		default:
 			ret = -ENODEV;
 		}
diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index 4a335ef3d97a..bbae48bdc022 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -348,6 +348,7 @@ struct arm_smmu_domain {
 	struct iommu_domain		domain;
 	struct device			*dev;	/* Device attached to this domain */
 	bool				aux;
+	bool				sys_cache;
 };
 
 struct arm_smmu_cb {
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 2388117641f1..a48edbebe3cb 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -125,6 +125,7 @@ enum iommu_attr {
 	DOMAIN_ATTR_NESTING,	/* two stages of translation */
 	DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE,
 	DOMAIN_ATTR_PGTABLE_CFG,
+	DOMAIN_ATTR_SYS_CACHE,
 	DOMAIN_ATTR_MAX,
 };
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>,
	Jordan Crouse <jcrouse@codeaurora.org>,
	Rob Clark <robdclark@gmail.com>
Cc: freedreno@lists.freedesktop.org,
	Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
	David Airlie <airlied@linux.ie>,
	linux-arm-msm@vger.kernel.org,
	Sharat Masetty <smasetty@codeaurora.org>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Akhil P Oommen <akhilpo@codeaurora.org>,
	iommu@lists.linux-foundation.org,
	Matthias Kaehlcke <mka@chromium.org>,
	"Kristian H . Kristensen" <hoegsberg@google.com>,
	Stephen Boyd <swboyd@chromium.org>, Sean Paul <sean@poorly.run>,
	linux-arm-kernel@lists.infradead.org,
	Emil Velikov <emil.velikov@collabora.com>
Subject: [PATCHv3 3/7] iommu/arm-smmu: Add domain attribute for system cache
Date: Mon, 29 Jun 2020 21:22:46 +0530	[thread overview]
Message-ID: <134a67a32813dba111e9b888244d8ca44ab15f84.1593344119.git.saiprakash.ranjan@codeaurora.org> (raw)
In-Reply-To: <cover.1593344119.git.saiprakash.ranjan@codeaurora.org>

Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/iommu/arm-smmu.c | 17 +++++++++++++++++
 drivers/iommu/arm-smmu.h |  1 +
 include/linux/iommu.h    |  1 +
 3 files changed, 19 insertions(+)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index b2564f93d685..71b6f7038423 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -897,6 +897,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 			goto out_unlock;
 	}
 
+	if (smmu_domain->sys_cache)
+		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_SYS_CACHE;
+
 	if (smmu_domain->non_strict)
 		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
 
@@ -1732,6 +1735,9 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
 		case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
 			*(int *)data = smmu_domain->non_strict;
 			return 0;
+		case DOMAIN_ATTR_SYS_CACHE:
+			*((int *)data) = smmu_domain->sys_cache;
+			return 0;
 		default:
 			return -ENODEV;
 		}
@@ -1763,6 +1769,17 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
 			else
 				smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
 			break;
+		case DOMAIN_ATTR_SYS_CACHE:
+			if (smmu_domain->smmu) {
+				ret = -EPERM;
+				goto out_unlock;
+			}
+
+			if (*((int *)data))
+				smmu_domain->sys_cache = true;
+			else
+				smmu_domain->sys_cache = false;
+			break;
 		default:
 			ret = -ENODEV;
 		}
diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index 4a335ef3d97a..bbae48bdc022 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -348,6 +348,7 @@ struct arm_smmu_domain {
 	struct iommu_domain		domain;
 	struct device			*dev;	/* Device attached to this domain */
 	bool				aux;
+	bool				sys_cache;
 };
 
 struct arm_smmu_cb {
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 2388117641f1..a48edbebe3cb 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -125,6 +125,7 @@ enum iommu_attr {
 	DOMAIN_ATTR_NESTING,	/* two stages of translation */
 	DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE,
 	DOMAIN_ATTR_PGTABLE_CFG,
+	DOMAIN_ATTR_SYS_CACHE,
 	DOMAIN_ATTR_MAX,
 };
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

  parent reply	other threads:[~2020-06-29 18:40 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-29 15:52 [PATCHv3 0/7] System Cache support for GPU and required SMMU support Sai Prakash Ranjan
2020-06-29 15:52 ` Sai Prakash Ranjan
2020-06-29 15:52 ` Sai Prakash Ranjan
2020-06-29 15:52 ` Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 1/7] iommu/arm-smmu: Add a init_context_bank implementation hook Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 2/7] iommu/io-pgtable-arm: Add support to use system cache Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52 ` Sai Prakash Ranjan [this message]
2020-06-29 15:52   ` [PATCHv3 3/7] iommu/arm-smmu: Add domain attribute for " Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 4/7] iommu: arm-smmu-impl: Remove unwanted extra blank lines Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 5/7] iommu: arm-smmu-impl: Convert to use of_match_node() for qcom impl Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 6/7] drm/msm: rearrange the gpu_rmw() function Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 7/7] drm/msm/a6xx: Add support for using system cache(LLC) Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-06-29 15:52   ` Sai Prakash Ranjan
2020-07-03 13:37   ` Will Deacon
2020-07-03 13:37     ` Will Deacon
2020-07-03 13:37     ` Will Deacon
2020-07-03 13:37     ` Will Deacon
2020-07-03 14:53     ` Sai Prakash Ranjan
2020-07-03 14:53       ` Sai Prakash Ranjan
2020-07-03 14:53       ` Sai Prakash Ranjan
2020-07-03 14:53       ` Sai Prakash Ranjan
2020-07-03 15:40       ` Will Deacon
2020-07-03 15:40         ` Will Deacon
2020-07-03 15:40         ` Will Deacon
2020-07-03 15:40         ` Will Deacon
2020-07-03 16:04       ` Rob Clark
2020-07-03 16:04         ` Rob Clark
2020-07-03 16:04         ` Rob Clark
2020-07-03 16:04         ` Rob Clark
2020-07-03 16:59         ` Sai Prakash Ranjan
2020-07-03 16:59           ` Sai Prakash Ranjan
2020-07-03 16:59           ` Sai Prakash Ranjan
2020-07-03 16:59           ` Sai Prakash Ranjan
2020-07-09 16:13         ` Jordan Crouse
2020-07-09 16:13           ` Jordan Crouse
2020-07-09 16:13           ` Jordan Crouse
2020-07-09 16:13           ` Jordan Crouse

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