* [PATCH 0/3] add a reset helper for resetting cores
@ 2012-10-28 13:17 Jonas Gorski
2012-10-28 13:17 ` [PATCH 1/3] MIPS: BCM63XX: add softreset register description for BCM6358 Jonas Gorski
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Jonas Gorski @ 2012-10-28 13:17 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, John Crispin, Maxime Bizon, Florian Fainelli,
Kevin Cernekee
This patchset adds a reset helper to abstract out resetting the
different cores found on BCM63XX SoCs and adds proper locking to prevent
concurrent access to the softreset register.
This patchset technically depends on the pcie clock patch, but git am -3
manages to merge it automatically and correctly if it isn't applied.
There is no real dependency on the other patch.
Jonas Gorski (3):
MIPS: BCM63XX: add softreset register description for BCM6358
MIPS: BCM63XX: add core reset helper
MIPS: BCM63XX: use the new reset helper
arch/mips/bcm63xx/Makefile | 6 +-
arch/mips/bcm63xx/clk.c | 19 +--
arch/mips/bcm63xx/reset.c | 223 ++++++++++++++++++++
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 10 +
arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 21 ++
arch/mips/pci/pci-bcm63xx.c | 19 +--
6 files changed, 268 insertions(+), 30 deletions(-)
create mode 100644 arch/mips/bcm63xx/reset.c
create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
--
1.7.2.5
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] MIPS: BCM63XX: add softreset register description for BCM6358
2012-10-28 13:17 [PATCH 0/3] add a reset helper for resetting cores Jonas Gorski
@ 2012-10-28 13:17 ` Jonas Gorski
2012-10-29 10:56 ` Sergei Shtylyov
2012-10-28 13:17 ` [PATCH 2/3] MIPS: BCM63XX: add core reset helper Jonas Gorski
2012-10-28 13:17 ` [PATCH 3/3] MIPS: BCM63XX: use the new " Jonas Gorski
2 siblings, 1 reply; 6+ messages in thread
From: Jonas Gorski @ 2012-10-28 13:17 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, John Crispin, Maxime Bizon, Florian Fainelli,
Kevin Cernekee
The softreset register description for BCM6358 was missing, so add it.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 12963d0..e84e602 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -191,6 +191,7 @@
/* Soft Reset register */
#define PERF_SOFTRESET_REG 0x28
#define PERF_SOFTRESET_6328_REG 0x10
+#define PERF_SOFTRESET_6358_REG 0x34
#define PERF_SOFTRESET_6368_REG 0x10
#define SOFTRESET_6328_SPI_MASK (1 << 0)
@@ -244,6 +245,15 @@
SOFTRESET_6348_ACLC_MASK | \
SOFTRESET_6348_ADSLMIPSPLL_MASK)
+#define SOFTRESET_6358_SPI_MASK (1 << 0)
+#define SOFTRESET_6358_ENET_MASK (1 << 2)
+#define SOFTRESET_6358_MPI_MASK (1 << 3)
+#define SOFTRESET_6358_EPHY_MASK (1 << 6)
+#define SOFTRESET_6358_SAR_MASK (1 << 7)
+#define SOFTRESET_6358_USBH_MASK (1 << 12)
+#define SOFTRESET_6358_PCM_MASK (1 << 13)
+#define SOFTRESET_6358_ADSL_MASK (1 << 14)
+
#define SOFTRESET_6368_SPI_MASK (1 << 0)
#define SOFTRESET_6368_MPI_MASK (1 << 3)
#define SOFTRESET_6368_EPHY_MASK (1 << 6)
--
1.7.2.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] MIPS: BCM63XX: add core reset helper
2012-10-28 13:17 [PATCH 0/3] add a reset helper for resetting cores Jonas Gorski
2012-10-28 13:17 ` [PATCH 1/3] MIPS: BCM63XX: add softreset register description for BCM6358 Jonas Gorski
@ 2012-10-28 13:17 ` Jonas Gorski
2012-10-28 13:17 ` [PATCH 3/3] MIPS: BCM63XX: use the new " Jonas Gorski
2 siblings, 0 replies; 6+ messages in thread
From: Jonas Gorski @ 2012-10-28 13:17 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, John Crispin, Maxime Bizon, Florian Fainelli,
Kevin Cernekee
Add a reset helper for resetting the different cores.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
arch/mips/bcm63xx/Makefile | 6 +-
arch/mips/bcm63xx/reset.c | 223 ++++++++++++++++++++
arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 21 ++
3 files changed, 247 insertions(+), 3 deletions(-)
create mode 100644 arch/mips/bcm63xx/reset.c
create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index 9bbb30a..bfc9b84 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -1,6 +1,6 @@
-obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
- dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
- dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o
+obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o reset.o setup.o \
+ timer.o dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o \
+ dev-rng.o dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-y += boards/
diff --git a/arch/mips/bcm63xx/reset.c b/arch/mips/bcm63xx/reset.c
new file mode 100644
index 0000000..68a31bb
--- /dev/null
+++ b/arch/mips/bcm63xx/reset.c
@@ -0,0 +1,223 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <bcm63xx_cpu.h>
+#include <bcm63xx_io.h>
+#include <bcm63xx_regs.h>
+#include <bcm63xx_reset.h>
+
+#define __GEN_RESET_BITS_TABLE(__cpu) \
+ [BCM63XX_RESET_SPI] = BCM## __cpu ##_RESET_SPI, \
+ [BCM63XX_RESET_ENET] = BCM## __cpu ##_RESET_ENET, \
+ [BCM63XX_RESET_USBH] = BCM## __cpu ##_RESET_USBH, \
+ [BCM63XX_RESET_USBD] = BCM## __cpu ##_RESET_USBD, \
+ [BCM63XX_RESET_DSL] = BCM## __cpu ##_RESET_DSL, \
+ [BCM63XX_RESET_SAR] = BCM## __cpu ##_RESET_SAR, \
+ [BCM63XX_RESET_EPHY] = BCM## __cpu ##_RESET_EPHY, \
+ [BCM63XX_RESET_ENETSW] = BCM## __cpu ##_RESET_ENETSW, \
+ [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \
+ [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \
+ [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
+ [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
+
+#define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
+#define BCM6328_RESET_ENET 0
+#define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
+#define BCM6328_RESET_USBD SOFTRESET_6328_USBS_MASK
+#define BCM6328_RESET_DSL 0
+#define BCM6328_RESET_SAR SOFTRESET_6328_SAR_MASK
+#define BCM6328_RESET_EPHY SOFTRESET_6328_EPHY_MASK
+#define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK
+#define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK
+#define BCM6328_RESET_MPI 0
+#define BCM6328_RESET_PCIE \
+ (SOFTRESET_6328_PCIE_MASK | \
+ SOFTRESET_6328_PCIE_CORE_MASK | \
+ SOFTRESET_6328_PCIE_HARD_MASK)
+#define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK
+
+#define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK
+#define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK
+#define BCM6338_RESET_USBH SOFTRESET_6338_USBH_MASK
+#define BCM6338_RESET_USBD SOFTRESET_6338_USBS_MASK
+#define BCM6338_RESET_DSL SOFTRESET_6338_ADSL_MASK
+#define BCM6338_RESET_SAR SOFTRESET_6338_SAR_MASK
+#define BCM6338_RESET_EPHY 0
+#define BCM6338_RESET_ENETSW 0
+#define BCM6338_RESET_PCM 0
+#define BCM6338_RESET_MPI 0
+#define BCM6338_RESET_PCIE 0
+#define BCM6338_RESET_PCIE_EXT 0
+
+#define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK
+#define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK
+#define BCM6348_RESET_USBH SOFTRESET_6348_USBH_MASK
+#define BCM6348_RESET_USBD SOFTRESET_6348_USBS_MASK
+#define BCM6348_RESET_DSL SOFTRESET_6348_ADSL_MASK
+#define BCM6348_RESET_SAR SOFTRESET_6348_SAR_MASK
+#define BCM6348_RESET_EPHY 0
+#define BCM6348_RESET_ENETSW 0
+#define BCM6348_RESET_PCM 0
+#define BCM6348_RESET_MPI 0
+#define BCM6348_RESET_PCIE 0
+#define BCM6348_RESET_PCIE_EXT 0
+
+#define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK
+#define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK
+#define BCM6358_RESET_USBH SOFTRESET_6358_USBH_MASK
+#define BCM6358_RESET_USBD 0
+#define BCM6358_RESET_DSL SOFTRESET_6358_ADSL_MASK
+#define BCM6358_RESET_SAR SOFTRESET_6358_SAR_MASK
+#define BCM6358_RESET_EPHY SOFTRESET_6358_EPHY_MASK
+#define BCM6358_RESET_ENETSW 0
+#define BCM6358_RESET_PCM SOFTRESET_6358_PCM_MASK
+#define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK
+#define BCM6358_RESET_PCIE 0
+#define BCM6358_RESET_PCIE_EXT 0
+
+#define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
+#define BCM6368_RESET_ENET 0
+#define BCM6368_RESET_USBH SOFTRESET_6368_USBH_MASK
+#define BCM6368_RESET_USBD SOFTRESET_6368_USBS_MASK
+#define BCM6368_RESET_DSL 0
+#define BCM6368_RESET_SAR SOFTRESET_6368_SAR_MASK
+#define BCM6368_RESET_EPHY SOFTRESET_6368_EPHY_MASK
+#define BCM6368_RESET_ENETSW 0
+#define BCM6368_RESET_PCM SOFTRESET_6368_PCM_MASK
+#define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK
+#define BCM6368_RESET_PCIE 0
+#define BCM6368_RESET_PCIE_EXT 0
+
+#ifdef BCMCPU_RUNTIME_DETECT
+
+/*
+ * core reset bits
+ */
+static const u32 bcm6328_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6328)
+};
+
+static const u32 bcm6338_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6338)
+};
+
+static const u32 bcm6348_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6348)
+};
+
+static const u32 bcm6358_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6358)
+};
+
+static const u32 bcm6368_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6368)
+};
+
+const u32 *bcm63xx_reset_bits;
+static int reset_reg;
+
+static int __init bcm63xx_reset_bits_init(void)
+{
+ if (BCMCPU_IS_6328()) {
+ reset_reg = PERF_SOFTRESET_6328_REG;
+ bcm63xx_reset_bits = bcm6328_reset_bits;
+ } else if (BCMCPU_IS_6338()) {
+ reset_reg = PERF_SOFTRESET_REG;
+ bcm63xx_reset_bits = bcm6338_reset_bits;
+ } else if (BCMCPU_IS_6348()) {
+ reset_reg = PERF_SOFTRESET_REG;
+ bcm63xx_reset_bits = bcm6348_reset_bits;
+ } else if (BCMCPU_IS_6358()) {
+ reset_reg = PERF_SOFTRESET_6358_REG;
+ bcm63xx_reset_bits = bcm6358_reset_bits;
+ } else if (BCMCPU_IS_6368()) {
+ reset_reg = PERF_SOFTRESET_6368_REG;
+ bcm63xx_reset_bits = bcm6368_reset_bits;
+ }
+
+ return 0;
+}
+#else
+
+#ifdef CONFIG_BCM63XX_CPU_6328
+static const u32 bcm63xx_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6328)
+};
+#define reset_reg PERF_SOFTRESET_6328_REG
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6338
+static const u32 bcm63xx_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6338)
+};
+#define reset_reg PERF_SOFTRESET_REG
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6345
+static const u32 bcm63xx_reset_bits[] = { };
+#define reset_reg 0
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6348
+static const u32 bcm63xx_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6348)
+};
+#define reset_reg PERF_SOFTRESET_REG
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6358
+static const u32 bcm63xx_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6358)
+};
+#define reset_reg PERF_SOFTRESET_6358_REG
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6368
+static const u32 bcm63xx_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6368)
+};
+#define reset_reg PERF_SOFTRESET_6368_REG
+#endif
+
+static int __init bcm63xx_reset_bits_init(void) { return 0; }
+#endif
+
+static DEFINE_SPINLOCK(reset_mutex);
+
+static void __bcm63xx_core_set_reset(u32 mask, int enable)
+{
+ unsigned long flags;
+ u32 val;
+
+ if (!mask)
+ return;
+
+ spin_lock_irqsave(&reset_mutex, flags);
+ val = bcm_perf_readl(reset_reg);
+
+ if (enable)
+ val &= ~mask;
+ else
+ val |= mask;
+
+ bcm_perf_writel(val, reset_reg);
+ spin_unlock_irqrestore(&reset_mutex, flags);
+}
+
+void bcm63xx_core_set_reset(enum bcm63xx_core_reset core, int reset)
+{
+ __bcm63xx_core_set_reset(bcm63xx_reset_bits[core], reset);
+}
+EXPORT_SYMBOL(bcm63xx_core_set_reset);
+
+postcore_initcall(bcm63xx_reset_bits_init);
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
new file mode 100644
index 0000000..3a6eb9c
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
@@ -0,0 +1,21 @@
+#ifndef __BCM63XX_RESET_H
+#define __BCM63XX_RESET_H
+
+enum bcm63xx_core_reset {
+ BCM63XX_RESET_SPI,
+ BCM63XX_RESET_ENET,
+ BCM63XX_RESET_USBH,
+ BCM63XX_RESET_USBD,
+ BCM63XX_RESET_SAR,
+ BCM63XX_RESET_DSL,
+ BCM63XX_RESET_EPHY,
+ BCM63XX_RESET_ENETSW,
+ BCM63XX_RESET_PCM,
+ BCM63XX_RESET_MPI,
+ BCM63XX_RESET_PCIE,
+ BCM63XX_RESET_PCIE_EXT,
+};
+
+void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
+
+#endif
--
1.7.2.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] MIPS: BCM63XX: use the new reset helper
2012-10-28 13:17 [PATCH 0/3] add a reset helper for resetting cores Jonas Gorski
2012-10-28 13:17 ` [PATCH 1/3] MIPS: BCM63XX: add softreset register description for BCM6358 Jonas Gorski
2012-10-28 13:17 ` [PATCH 2/3] MIPS: BCM63XX: add core reset helper Jonas Gorski
@ 2012-10-28 13:17 ` Jonas Gorski
2 siblings, 0 replies; 6+ messages in thread
From: Jonas Gorski @ 2012-10-28 13:17 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, John Crispin, Maxime Bizon, Florian Fainelli,
Kevin Cernekee
Use the new reset helper where appropriate.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
arch/mips/bcm63xx/clk.c | 19 +++++--------------
arch/mips/pci/pci-bcm63xx.c | 19 ++++++-------------
2 files changed, 11 insertions(+), 27 deletions(-)
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 89a5fb0..b9e948d 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -14,6 +14,7 @@
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
+#include <bcm63xx_reset.h>
#include <bcm63xx_clk.h>
static DEFINE_MUTEX(clocks_mutex);
@@ -124,15 +125,10 @@ static void enetsw_set(struct clk *clk, int enable)
CKCTL_6368_SWPKT_USB_EN |
CKCTL_6368_SWPKT_SAR_EN, enable);
if (enable) {
- u32 val;
-
/* reset switch core afer clock change */
- val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
- val &= ~SOFTRESET_6368_ENETSW_MASK;
- bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+ bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
msleep(10);
- val |= SOFTRESET_6368_ENETSW_MASK;
- bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+ bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
msleep(10);
}
}
@@ -222,15 +218,10 @@ static void xtm_set(struct clk *clk, int enable)
CKCTL_6368_SWPKT_SAR_EN, enable);
if (enable) {
- u32 val;
-
/* reset sar core afer clock change */
- val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
- val &= ~SOFTRESET_6368_SAR_MASK;
- bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+ bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
mdelay(1);
- val |= SOFTRESET_6368_SAR_MASK;
- bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+ bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
mdelay(1);
}
}
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index fa8c320..ca179b6 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -14,6 +14,8 @@
#include <linux/clk.h>
#include <asm/bootinfo.h>
+#include <bcm63xx_reset.h>
+
#include "pci-bcm63xx.h"
/*
@@ -126,23 +128,14 @@ static void __init bcm63xx_reset_pcie(void)
bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
/* reset the PCIe core */
- val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
-
- val &= ~SOFTRESET_6328_PCIE_MASK;
- val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
- val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
- val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
mdelay(10);
- val |= SOFTRESET_6328_PCIE_MASK;
- val |= SOFTRESET_6328_PCIE_CORE_MASK;
- val |= SOFTRESET_6328_PCIE_HARD_MASK;
- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
mdelay(10);
- val |= SOFTRESET_6328_PCIE_EXT_MASK;
- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
mdelay(200);
}
--
1.7.2.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] MIPS: BCM63XX: add softreset register description for BCM6358
2012-10-28 13:17 ` [PATCH 1/3] MIPS: BCM63XX: add softreset register description for BCM6358 Jonas Gorski
@ 2012-10-29 10:56 ` Sergei Shtylyov
2012-10-29 11:10 ` Florian Fainelli
0 siblings, 1 reply; 6+ messages in thread
From: Sergei Shtylyov @ 2012-10-29 10:56 UTC (permalink / raw)
To: Jonas Gorski
Cc: linux-mips, Ralf Baechle, John Crispin, Maxime Bizon,
Florian Fainelli, Kevin Cernekee
Hello.
On 28-10-2012 17:17, Jonas Gorski wrote:
> The softreset register description for BCM6358 was missing, so add it.
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
> ---
> arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 10 ++++++++++
> 1 files changed, 10 insertions(+), 0 deletions(-)
> diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> index 12963d0..e84e602 100644
> --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
[...]
> @@ -244,6 +245,15 @@
> SOFTRESET_6348_ACLC_MASK | \
> SOFTRESET_6348_ADSLMIPSPLL_MASK)
>
> +#define SOFTRESET_6358_SPI_MASK (1 << 0)
> +#define SOFTRESET_6358_ENET_MASK (1 << 2)
> +#define SOFTRESET_6358_MPI_MASK (1 << 3)
> +#define SOFTRESET_6358_EPHY_MASK (1 << 6)
> +#define SOFTRESET_6358_SAR_MASK (1 << 7)
> +#define SOFTRESET_6358_USBH_MASK (1 << 12)
> +#define SOFTRESET_6358_PCM_MASK (1 << 13)
> +#define SOFTRESET_6358_ADSL_MASK (1 << 14)
> +
Why not use BIT(n) instead of (1 << n)?
WBR, Sergei
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] MIPS: BCM63XX: add softreset register description for BCM6358
2012-10-29 10:56 ` Sergei Shtylyov
@ 2012-10-29 11:10 ` Florian Fainelli
0 siblings, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2012-10-29 11:10 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Jonas Gorski, linux-mips, Ralf Baechle, John Crispin,
Maxime Bizon, Kevin Cernekee
On Monday 29 October 2012 14:56:27 Sergei Shtylyov wrote:
> Hello.
>
> On 28-10-2012 17:17, Jonas Gorski wrote:
>
> > The softreset register description for BCM6358 was missing, so add it.
>
> > Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
> > ---
> > arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 10 ++++++++++
> > 1 files changed, 10 insertions(+), 0 deletions(-)
>
> > diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> > index 12963d0..e84e602 100644
> > --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> > +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> [...]
> > @@ -244,6 +245,15 @@
> > SOFTRESET_6348_ACLC_MASK | \
> > SOFTRESET_6348_ADSLMIPSPLL_MASK)
> >
> > +#define SOFTRESET_6358_SPI_MASK (1 << 0)
> > +#define SOFTRESET_6358_ENET_MASK (1 << 2)
> > +#define SOFTRESET_6358_MPI_MASK (1 << 3)
> > +#define SOFTRESET_6358_EPHY_MASK (1 << 6)
> > +#define SOFTRESET_6358_SAR_MASK (1 << 7)
> > +#define SOFTRESET_6358_USBH_MASK (1 << 12)
> > +#define SOFTRESET_6358_PCM_MASK (1 << 13)
> > +#define SOFTRESET_6358_ADSL_MASK (1 << 14)
> > +
>
> Why not use BIT(n) instead of (1 << n)?
All other bcm63xx headers consistently use (1 << n), I would rather we keep
this convention.
--
Florian
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-10-29 11:12 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-10-28 13:17 [PATCH 0/3] add a reset helper for resetting cores Jonas Gorski
2012-10-28 13:17 ` [PATCH 1/3] MIPS: BCM63XX: add softreset register description for BCM6358 Jonas Gorski
2012-10-29 10:56 ` Sergei Shtylyov
2012-10-29 11:10 ` Florian Fainelli
2012-10-28 13:17 ` [PATCH 2/3] MIPS: BCM63XX: add core reset helper Jonas Gorski
2012-10-28 13:17 ` [PATCH 3/3] MIPS: BCM63XX: use the new " Jonas Gorski
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