[PATCH 00/36] Haswell VGA fixes

[PATCH 00/36] Haswell VGA fixes

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Hi

As you may have noticed this is not "Haswell VGA enablement", but "Haswell VGA
fixes" since VGA is already enabled on Haswell. Even though it's enabled,
whenever I try to "xrandr --output VGA1 --auto" my machine hard hangs.

So what does this series fixes?
  - It makes our code follow the "mode set sequence for CRT" described in our
    documentation.
  - It makes my old VGA monitor work :)

What kind of problems remain?

  - I really don't know exactly what problems remain, but this series just does
    not touch the code that sets the PCH clocks and I'm sure that code is
    incomplete. We are probably still relying on the fact that the BIOS enables
    things for us. But since I didn't even touch that code and VGA works for me,
    I think we can address those problems in a later patch series.

How does the series fix the problems?

  - It forks some of the Ironlake PCH functions.
  - It makes all those forked functions aware of the fact that there's only one
    CPU transcoder and that CPU transcoder may be different from CPU pipe.
  - It changes a lot of things to make sure we follow the mode set sequence.

The number of patches may be scary, but each patch tries to be really small and
easy to review, so if you grab our "mode set sequence" document you'll be able
to review a lot of patches in just a few minutes :)

Cheers,
Paulo

Paulo Zanoni (36):
  drm/i915: don't set ADPA pipe select on LPT
  drm/i915: use intel_ddi_get_hw_state on CRT encoder too
  drm/i915: add lpt_pch_enable
  drm/i915: remove Haswell/LPT bits from ironlake_pch_enable
  drm/i915: remove ironlake bits from lpt_pch_enable
  drm/i915: train Haswell FDI at the right time
  drm/i915: use the right FDI_RX_CTL register on Haswell
  drm/i915: set the correct number of FDI lanes on Haswell
  drm/i915: don't rely on DDI_BUF_CTL previous values
  drm/i915: program the FDI RX TUSIZE register on hsw_fdi_link_train
  drm/i915: properly program FDI_RX_MISC pwrdn lane values on HSW
  drm/i915: wait only 35us for the FDI link training
  drm/i915: remove an useless indentation level on hsw_fdi_link_train
  drm/i915: disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
  drm/i915: change Haswell FDI link training error messages
  drm/i915: try each voltage twice at hsw_fdi_link_train
  drm/i915: fix Haswell FDI link disable path
  drm/i915: don't write FDI_RX_TUSIZE on lpt_pch_enable
  drm/i915: rename intel_enable_pch_pll to ironlake_enable_pch_pll
  drm/i915: don't call ironlake_enable_pch_pll on lpt_pch_enable
  drm/i915: don't assert_panel_unlocked on LPT
  drm/i915: use the CPU and PCH transcoders on lpt_pch_enable
  drm/i915: rename intel_{en,dis}able_transcoder
  drm/i915: fork lpt version of ironlake_{en,dis}able_pch_transcoder
  drm/i915: remove Haswell code from ironlake_enable_pch_transcoder
  drm/i915: remove IBX code from lpt_enable_pch_transcoder
  drm/i915: don't assert_pch_pll_enabled on lpt_enable_pch_transcoder
  drm/i915: use CPU and PCH transcoders on lpt_enable_pch_transcoder
  drm/i915: use PIPECONF_INTERLACE_MASK_HSW on
    lpt_enable_pch_transcoder
  drm/i915: don't rely on previous values when setting LPT TRANSCONF
  drm/i915: don't assert_pch_ports_disabled on LPT
  drm/i915: use CPU and PCH transcoders on lpt_disable_pch_transcoder
  drm/i915: implement timing override workarounds on LPT
  drm/i915: don't intel_disable_pch_pll on Haswell/LPT
  drm/i915: don't limit Haswell CRT encoder to pipe A
  drm/i915: don't assert disabled FDI before disabling the FDI

 drivers/gpu/drm/i915/i915_reg.h      |  17 +++--
 drivers/gpu/drm/i915/intel_crt.c     |  14 ++--
 drivers/gpu/drm/i915/intel_ddi.c     | 134 +++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_display.c | 127 +++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_drv.h     |   4 +-
 5 files changed, 202 insertions(+), 94 deletions(-)

-- 
1.7.11.4

[PATCH 01/36] drm/i915: don't set ADPA pipe select on LPT

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Those bits just don't exist on LPT. The CRT DAC, PCH transcoder and
FDI RX are always connected to DDI E.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 5f7c414..e4fd102 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -245,7 +245,9 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
 		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 
 	/* For CPT allow 3 pipe config, for others just use A or B */
-	if (HAS_PCH_CPT(dev))
+	if (HAS_PCH_LPT(dev))
+		; /* Those bits don't exist here */
+	else if (HAS_PCH_CPT(dev))
 		adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 	else if (intel_crtc->pipe == 0)
 		adpa |= ADPA_PIPE_A_SELECT;
-- 
1.7.11.4

[PATCH 02/36] drm/i915: use intel_ddi_get_hw_state on CRT encoder too

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Because things changed on Haswell/LPT and the bits checked by
intel_crt_get_hw_state have moved to other registers.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index e4fd102..1c97c27 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -784,7 +784,10 @@ void intel_crt_init(struct drm_device *dev)
 
 	crt->base.disable = intel_disable_crt;
 	crt->base.enable = intel_enable_crt;
-	crt->base.get_hw_state = intel_crt_get_hw_state;
+	if (IS_HASWELL(dev))
+		crt->base.get_hw_state = intel_ddi_get_hw_state;
+	else
+		crt->base.get_hw_state = intel_crt_get_hw_state;
 	intel_connector->get_hw_state = intel_connector_get_hw_state;
 
 	drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
-- 
1.7.11.4

[PATCH 03/36] drm/i915: add lpt_pch_enable

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

For now it's just a fork of ironlake_pch_enable. The next commits will
change this.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 111 ++++++++++++++++++++++++++++++++++-
 1 file changed, 110 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4eb84ad..73d6516 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3137,6 +3137,115 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	intel_enable_transcoder(dev_priv, pipe);
 }
 
+static void lpt_pch_enable(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 reg, temp;
+
+	assert_transcoder_disabled(dev_priv, pipe);
+
+	/* Write the TU size bits before fdi link training, so that error
+	 * detection works. */
+	I915_WRITE(FDI_RX_TUSIZE1(pipe),
+		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+
+	/* For PCH output, training FDI link */
+	dev_priv->display.fdi_link_train(crtc);
+
+	/* XXX: pch pll's can be enabled any time before we enable the PCH
+	 * transcoder, and we actually should do this to not upset any PCH
+	 * transcoder that already use the clock when we share it.
+	 *
+	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
+	 * unconditionally resets the pll - we need that to have the right LVDS
+	 * enable sequence. */
+	intel_enable_pch_pll(intel_crtc);
+
+	if (HAS_PCH_LPT(dev)) {
+		DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
+		lpt_program_iclkip(crtc);
+	} else if (HAS_PCH_CPT(dev)) {
+		u32 sel;
+
+		temp = I915_READ(PCH_DPLL_SEL);
+		switch (pipe) {
+		default:
+		case 0:
+			temp |= TRANSA_DPLL_ENABLE;
+			sel = TRANSA_DPLLB_SEL;
+			break;
+		case 1:
+			temp |= TRANSB_DPLL_ENABLE;
+			sel = TRANSB_DPLLB_SEL;
+			break;
+		case 2:
+			temp |= TRANSC_DPLL_ENABLE;
+			sel = TRANSC_DPLLB_SEL;
+			break;
+		}
+		if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
+			temp |= sel;
+		else
+			temp &= ~sel;
+		I915_WRITE(PCH_DPLL_SEL, temp);
+	}
+
+	/* set transcoder timing, panel must allow it */
+	assert_panel_unlocked(dev_priv, pipe);
+	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
+	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
+	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
+
+	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
+	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
+	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
+	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
+
+	if (!IS_HASWELL(dev))
+		intel_fdi_normal_train(crtc);
+
+	/* For PCH DP, enable TRANS_DP_CTL */
+	if (HAS_PCH_CPT(dev) &&
+	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
+		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
+		reg = TRANS_DP_CTL(pipe);
+		temp = I915_READ(reg);
+		temp &= ~(TRANS_DP_PORT_SEL_MASK |
+			  TRANS_DP_SYNC_MASK |
+			  TRANS_DP_BPC_MASK);
+		temp |= (TRANS_DP_OUTPUT_ENABLE |
+			 TRANS_DP_ENH_FRAMING);
+		temp |= bpc << 9; /* same format but at 11:9 */
+
+		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
+			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
+		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
+			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
+
+		switch (intel_trans_dp_port_sel(crtc)) {
+		case PCH_DP_B:
+			temp |= TRANS_DP_PORT_SEL_B;
+			break;
+		case PCH_DP_C:
+			temp |= TRANS_DP_PORT_SEL_C;
+			break;
+		case PCH_DP_D:
+			temp |= TRANS_DP_PORT_SEL_D;
+			break;
+		default:
+			BUG();
+		}
+
+		I915_WRITE(reg, temp);
+	}
+
+	intel_enable_transcoder(dev_priv, pipe);
+}
+
 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
 {
 	struct intel_pch_pll *pll = intel_crtc->pch_pll;
@@ -3383,7 +3492,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	intel_enable_plane(dev_priv, plane, pipe);
 
 	if (is_pch_port)
-		ironlake_pch_enable(crtc);
+		lpt_pch_enable(crtc);
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
-- 
1.7.11.4

[PATCH 04/36] drm/i915: remove Haswell/LPT bits from ironlake_pch_enable

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Since now we have lpt_pch_enable for them.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 73d6516..6b72788 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3055,10 +3055,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	 * enable sequence. */
 	intel_enable_pch_pll(intel_crtc);
 
-	if (HAS_PCH_LPT(dev)) {
-		DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
-		lpt_program_iclkip(crtc);
-	} else if (HAS_PCH_CPT(dev)) {
+	if (HAS_PCH_CPT(dev)) {
 		u32 sel;
 
 		temp = I915_READ(PCH_DPLL_SEL);
@@ -3095,8 +3092,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
 	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
 
-	if (!IS_HASWELL(dev))
-		intel_fdi_normal_train(crtc);
+	intel_fdi_normal_train(crtc);
 
 	/* For PCH DP, enable TRANS_DP_CTL */
 	if (HAS_PCH_CPT(dev) &&
-- 
1.7.11.4

[PATCH 05/36] drm/i915: remove ironlake bits from lpt_pch_enable

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Since this function will only run on Haswell/LPT and newer.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 69 +-----------------------------------
 1 file changed, 1 insertion(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6b72788..2dff7b2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3139,7 +3139,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp;
 
 	assert_transcoder_disabled(dev_priv, pipe);
 
@@ -3160,34 +3159,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	 * enable sequence. */
 	intel_enable_pch_pll(intel_crtc);
 
-	if (HAS_PCH_LPT(dev)) {
-		DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
-		lpt_program_iclkip(crtc);
-	} else if (HAS_PCH_CPT(dev)) {
-		u32 sel;
-
-		temp = I915_READ(PCH_DPLL_SEL);
-		switch (pipe) {
-		default:
-		case 0:
-			temp |= TRANSA_DPLL_ENABLE;
-			sel = TRANSA_DPLLB_SEL;
-			break;
-		case 1:
-			temp |= TRANSB_DPLL_ENABLE;
-			sel = TRANSB_DPLLB_SEL;
-			break;
-		case 2:
-			temp |= TRANSC_DPLL_ENABLE;
-			sel = TRANSC_DPLLB_SEL;
-			break;
-		}
-		if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
-			temp |= sel;
-		else
-			temp &= ~sel;
-		I915_WRITE(PCH_DPLL_SEL, temp);
-	}
+	lpt_program_iclkip(crtc);
 
 	/* set transcoder timing, panel must allow it */
 	assert_panel_unlocked(dev_priv, pipe);
@@ -3200,45 +3172,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
 	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
 
-	if (!IS_HASWELL(dev))
-		intel_fdi_normal_train(crtc);
-
-	/* For PCH DP, enable TRANS_DP_CTL */
-	if (HAS_PCH_CPT(dev) &&
-	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
-	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
-		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
-		reg = TRANS_DP_CTL(pipe);
-		temp = I915_READ(reg);
-		temp &= ~(TRANS_DP_PORT_SEL_MASK |
-			  TRANS_DP_SYNC_MASK |
-			  TRANS_DP_BPC_MASK);
-		temp |= (TRANS_DP_OUTPUT_ENABLE |
-			 TRANS_DP_ENH_FRAMING);
-		temp |= bpc << 9; /* same format but at 11:9 */
-
-		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
-			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
-		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
-			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
-
-		switch (intel_trans_dp_port_sel(crtc)) {
-		case PCH_DP_B:
-			temp |= TRANS_DP_PORT_SEL_B;
-			break;
-		case PCH_DP_C:
-			temp |= TRANS_DP_PORT_SEL_C;
-			break;
-		case PCH_DP_D:
-			temp |= TRANS_DP_PORT_SEL_D;
-			break;
-		default:
-			BUG();
-		}
-
-		I915_WRITE(reg, temp);
-	}
-
 	intel_enable_transcoder(dev_priv, pipe);
 }
 
-- 
1.7.11.4

[PATCH 06/36] drm/i915: train Haswell FDI at the right time

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Haswell FDI link training is very different from the previous
generations.

After this commit, hsw_fdi_link_train is responsible for implementing
all the steps described as "Enable and train FDI" from the Haswell
CRT mode set sequence documentation.

We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.

We are also removing ironlake_fdi_pll_enable since the PLL enablement
on Haswell is completely different and is also done during the link
training steps.

There are still quite a few things we need to fix on
hsw_fdi_link_train, so stay tuned for the next patches :)

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 17 +++++++++++------
 drivers/gpu/drm/i915/intel_ddi.c     | 34 ++++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_display.c |  5 +----
 3 files changed, 36 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0514823..abdc002 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3917,16 +3917,21 @@
 #define  FDI_PORT_WIDTH_2X_LPT			(1<<19)
 #define  FDI_PORT_WIDTH_1X_LPT			(0<<19)
 
-#define _FDI_RXA_MISC            0xf0010
-#define _FDI_RXB_MISC            0xf1010
+#define _FDI_RXA_MISC			0xf0010
+#define _FDI_RXB_MISC			0xf1010
+#define  FDI_RX_PWRDN_LANE1_MASK	(3<<26)
+#define  FDI_RX_PWRDN_LANE1_VAL(x)	((x)<<26)
+#define  FDI_RX_PWRDN_LANE0_MASK	(3<<24)
+#define  FDI_RX_PWRDN_LANE0_VAL(x)	((x)<<24)
+#define  FDI_RX_TP1_TO_TP2_48		(2<<20)
+#define  FDI_RX_TP1_TO_TP2_64		(3<<20)
+#define  FDI_RX_FDI_DELAY_90		(0x90<<0)
+#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
+
 #define _FDI_RXA_TUSIZE1         0xf0030
 #define _FDI_RXA_TUSIZE2         0xf0038
 #define _FDI_RXB_TUSIZE1         0xf1030
 #define _FDI_RXB_TUSIZE2         0xf1038
-#define  FDI_RX_TP1_TO_TP2_48	(2<<20)
-#define  FDI_RX_TP1_TO_TP2_64	(3<<20)
-#define  FDI_RX_FDI_DELAY_90	(0x90<<0)
-#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 67bd6ba..39a53b4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -154,7 +154,30 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp, i;
+	u32 reg, temp, i, rx_ctl_val;
+
+	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
+	 * mode set "sequence for CRT port" document:
+	 * - TP1 to TP2 time with the default value
+	 * - FDI delay to 90h
+	 */
+	I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
+				  FDI_RX_PWRDN_LANE0_VAL(2) |
+				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
+
+	/* Enable the PCH Receiver FDI PLL */
+	rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE |
+		     ((intel_crtc->fdi_lanes - 1) << 19);
+	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+	POSTING_READ(_FDI_RXA_CTL);
+	udelay(220);
+
+	/* Switch from Rawclk to PCDclk */
+	rx_ctl_val |= FDI_PCDCLK;
+	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+
+	/* Configure Port Clock Select */
+	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
 
 	/* Start the training iterating through available voltages and emphasis */
 	for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
@@ -176,15 +199,6 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 
 		udelay(600);
 
-		/* We need to program FDI_RX_MISC with the default TP1 to TP2
-		 * values before enabling the receiver, and configure the delay
-		 * for the FDI timing generator to 90h. Luckily, all the other
-		 * bits are supposed to be zeroed, so we can write those values
-		 * directly.
-		 */
-		I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 |
-				FDI_RX_FDI_DELAY_90);
-
 		/* Enable CPU FDI Receiver with auto-training */
 		reg = FDI_RX_CTL(pipe);
 		I915_WRITE(reg,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2dff7b2..e0b1f8c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3147,9 +3147,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(FDI_RX_TUSIZE1(pipe),
 		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
 
-	/* For PCH output, training FDI link */
-	dev_priv->display.fdi_link_train(crtc);
-
 	/* XXX: pch pll's can be enabled any time before we enable the PCH
 	 * transcoder, and we actually should do this to not upset any PCH
 	 * transcoder that already use the clock when we share it.
@@ -3389,7 +3386,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	is_pch_port = haswell_crtc_driving_pch(crtc);
 
 	if (is_pch_port)
-		ironlake_fdi_pll_enable(intel_crtc);
+		dev_priv->display.fdi_link_train(crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
-- 
1.7.11.4

[PATCH 07/36] drm/i915: use the right FDI_RX_CTL register on Haswell

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

There is only one PCH transcoder, so it's always _FDI_RXA_CTL. Using
"pipe" here is wrong.

While at it, also reuse the rx_ctl_val variable created in the
previous commit.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 24 ++++++++----------------
 1 file changed, 8 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 39a53b4..c397da3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -153,8 +153,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int pipe = intel_crtc->pipe;
-	u32 reg, temp, i, rx_ctl_val;
+	u32 temp, i, rx_ctl_val;
 
 	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 	 * mode set "sequence for CRT port" document:
@@ -199,17 +198,10 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 
 		udelay(600);
 
-		/* Enable CPU FDI Receiver with auto-training */
-		reg = FDI_RX_CTL(pipe);
-		I915_WRITE(reg,
-				I915_READ(reg) |
-					FDI_LINK_TRAIN_AUTO |
-					FDI_RX_ENABLE |
-					FDI_LINK_TRAIN_PATTERN_1_CPT |
-					FDI_RX_ENHANCE_FRAME_ENABLE |
-					FDI_PORT_WIDTH_2X_LPT |
-					FDI_RX_PLL_ENABLE);
-		POSTING_READ(reg);
+		/* Enable PCH FDI Receiver with auto-training */
+		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
+		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+		POSTING_READ(_FDI_RXA_CTL);
 		udelay(100);
 
 		temp = I915_READ(DP_TP_STATUS(PORT_E));
@@ -231,9 +223,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 			I915_WRITE(DP_TP_CTL(PORT_E),
 					I915_READ(DP_TP_CTL(PORT_E)) &
 						~DP_TP_CTL_ENABLE);
-			I915_WRITE(FDI_RX_CTL(pipe),
-					I915_READ(FDI_RX_CTL(pipe)) &
-						~FDI_RX_PLL_ENABLE);
+
+			rx_ctl_val &= ~FDI_RX_PLL_ENABLE;
+			I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 			continue;
 		}
 	}
-- 
1.7.11.4

[PATCH 08/36] drm/i915: set the correct number of FDI lanes on Haswell

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c397da3..e903502 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -193,7 +193,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(DDI_BUF_CTL(PORT_E),
 				temp |
 				DDI_BUF_CTL_ENABLE |
-				DDI_PORT_WIDTH_X2 |
+				((intel_crtc->fdi_lanes - 1) << 1) |
 				hsw_ddi_buf_ctl_values[i]);
 
 		udelay(600);
@@ -958,6 +958,7 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
 
 	} else if (type == INTEL_OUTPUT_ANALOG) {
 		temp |= TRANS_DDI_MODE_SELECT_FDI;
+		temp |= (intel_crtc->fdi_lanes - 1) << 1;
 
 	} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 		   type == INTEL_OUTPUT_EDP) {
-- 
1.7.11.4

[PATCH 09/36] drm/i915: don't rely on DDI_BUF_CTL previous values

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

... inside hsw_fdi_link_train. Just set the bits we want, everything
else is zero.

While at it, also POSTING_READ the register before waiting.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e903502..0cb6441 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -188,13 +188,11 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 					DP_TP_CTL_ENABLE);
 
 		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
-		temp = I915_READ(DDI_BUF_CTL(PORT_E));
-		temp = (temp & ~DDI_BUF_EMP_MASK);
 		I915_WRITE(DDI_BUF_CTL(PORT_E),
-				temp |
-				DDI_BUF_CTL_ENABLE |
-				((intel_crtc->fdi_lanes - 1) << 1) |
-				hsw_ddi_buf_ctl_values[i]);
+			   DDI_BUF_CTL_ENABLE |
+			   ((intel_crtc->fdi_lanes - 1) << 1) |
+			   hsw_ddi_buf_ctl_values[i]);
+		POSTING_READ(DDI_BUF_CTL(PORT_E));
 
 		udelay(600);
 
-- 
1.7.11.4

[PATCH 10/36] drm/i915: program the FDI RX TUSIZE register on hsw_fdi_link_train

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

According to the mode set sequence documentation, this is the right
place. According to the FDI_RX_TUSIZE register description, this is
the value we should set.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0cb6441..5d33f62 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -196,6 +196,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 
 		udelay(600);
 
+		/* Program PCH FDI Receiver TU */
+		I915_WRITE(_FDI_RXA_TUSIZE1, 0x7E000000);
+
 		/* Enable PCH FDI Receiver with auto-training */
 		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-- 
1.7.11.4

[PATCH 11/36] drm/i915: properly program FDI_RX_MISC pwrdn lane values on HSW

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

That's what our mode set sequence documentation says we need to do.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5d33f62..0239888 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -205,6 +205,12 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		POSTING_READ(_FDI_RXA_CTL);
 		udelay(100);
 
+		/* Program FDI_RX_MISC pwrdn lanes */
+		temp = I915_READ(_FDI_RXA_MISC);
+		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
+		I915_WRITE(_FDI_RXA_MISC, temp);
+		POSTING_READ(_FDI_RXA_MISC);
+
 		temp = I915_READ(DP_TP_STATUS(PORT_E));
 		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 			DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i);
@@ -227,6 +233,14 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 
 			rx_ctl_val &= ~FDI_RX_PLL_ENABLE;
 			I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+
+			temp = I915_READ(_FDI_RXA_MISC);
+			temp &= ~(FDI_RX_PWRDN_LANE1_MASK |
+				  FDI_RX_PWRDN_LANE0_MASK);
+			temp |= FDI_RX_PWRDN_LANE1_VAL(2) |
+				FDI_RX_PWRDN_LANE0_VAL(2);
+			I915_WRITE(_FDI_RXA_MISC, temp);
+
 			continue;
 		}
 	}
-- 
1.7.11.4

[PATCH 12/36] drm/i915: wait only 35us for the FDI link training

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

First we wait 30us for the FDI receiver lane calibration, then we wait
5us for the FDI auto training time.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0239888..11b5809 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -203,7 +203,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 		POSTING_READ(_FDI_RXA_CTL);
-		udelay(100);
+
+		/* Wait for FDI receiver lane calibration */
+		udelay(30);
 
 		/* Program FDI_RX_MISC pwrdn lanes */
 		temp = I915_READ(_FDI_RXA_MISC);
@@ -211,6 +213,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(_FDI_RXA_MISC, temp);
 		POSTING_READ(_FDI_RXA_MISC);
 
+		/* Wait for FDI auto training time */
+		udelay(5);
+
 		temp = I915_READ(DP_TP_STATUS(PORT_E));
 		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 			DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i);
-- 
1.7.11.4

[PATCH 13/36] drm/i915: remove an useless indentation level on hsw_fdi_link_train

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We already "break" when the link training succeeds.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 27 +++++++++++----------------
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 11b5809..3e43e42 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -228,26 +228,21 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 						DP_TP_CTL_ENABLE);
 
 			break;
-		} else {
-			DRM_ERROR("Error training BUF_CTL %d\n", i);
+		}
 
-			/* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
-			I915_WRITE(DP_TP_CTL(PORT_E),
-					I915_READ(DP_TP_CTL(PORT_E)) &
-						~DP_TP_CTL_ENABLE);
+		DRM_ERROR("Error training BUF_CTL %d\n", i);
 
-			rx_ctl_val &= ~FDI_RX_PLL_ENABLE;
-			I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+		/* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
+		I915_WRITE(DP_TP_CTL(PORT_E),
+			   I915_READ(DP_TP_CTL(PORT_E)) & ~DP_TP_CTL_ENABLE);
 
-			temp = I915_READ(_FDI_RXA_MISC);
-			temp &= ~(FDI_RX_PWRDN_LANE1_MASK |
-				  FDI_RX_PWRDN_LANE0_MASK);
-			temp |= FDI_RX_PWRDN_LANE1_VAL(2) |
-				FDI_RX_PWRDN_LANE0_VAL(2);
-			I915_WRITE(_FDI_RXA_MISC, temp);
+		rx_ctl_val &= ~FDI_RX_PLL_ENABLE;
+		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 
-			continue;
-		}
+		temp = I915_READ(_FDI_RXA_MISC);
+		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
+		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
+		I915_WRITE(_FDI_RXA_MISC, temp);
 	}
 
 	DRM_DEBUG_KMS("FDI train done.\n");
-- 
1.7.11.4

[PATCH 14/36] drm/i915: disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

... on hsw_fdi_link_train. Check the mode set sequence documentation.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3e43e42..c21e71c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -236,7 +236,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(DP_TP_CTL(PORT_E),
 			   I915_READ(DP_TP_CTL(PORT_E)) & ~DP_TP_CTL_ENABLE);
 
-		rx_ctl_val &= ~FDI_RX_PLL_ENABLE;
+		rx_ctl_val &= ~FDI_RX_ENABLE;
 		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 
 		temp = I915_READ(_FDI_RXA_MISC);
-- 
1.7.11.4

[PATCH 15/36] drm/i915: change Haswell FDI link training error messages

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We shouldn't call DRM_ERROR when still looping through voltage levels
since this is expected and not really a failure. So in this commit we
adjust the error path to only DRM_ERROR when we really fail after
trying everything.

While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since it's
what we use everywhere.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c21e71c..f8ca3c4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -218,7 +218,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 
 		temp = I915_READ(DP_TP_STATUS(PORT_E));
 		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
-			DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i);
+			DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 
 			/* Enable normal pixel sending for FDI */
 			I915_WRITE(DP_TP_CTL(PORT_E),
@@ -227,11 +227,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 						DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 						DP_TP_CTL_ENABLE);
 
-			break;
+			return;
 		}
 
-		DRM_ERROR("Error training BUF_CTL %d\n", i);
-
 		/* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
 		I915_WRITE(DP_TP_CTL(PORT_E),
 			   I915_READ(DP_TP_CTL(PORT_E)) & ~DP_TP_CTL_ENABLE);
@@ -245,7 +243,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(_FDI_RXA_MISC, temp);
 	}
 
-	DRM_DEBUG_KMS("FDI train done.\n");
+	DRM_ERROR("FDI link training failed!\n");
 }
 
 /* WRPLL clock dividers */
-- 
1.7.11.4

[PATCH 16/36] drm/i915: try each voltage twice at hsw_fdi_link_train

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

>From the mode set sequence document: "Each setting should be tried at
least twice before failing mode set".

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f8ca3c4..94c6b76 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -179,7 +179,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
 
 	/* Start the training iterating through available voltages and emphasis */
-	for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
+	for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
 		/* Configure DP_TP_CTL with auto-training */
 		I915_WRITE(DP_TP_CTL(PORT_E),
 					DP_TP_CTL_FDI_AUTOTRAIN |
@@ -191,7 +191,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(DDI_BUF_CTL(PORT_E),
 			   DDI_BUF_CTL_ENABLE |
 			   ((intel_crtc->fdi_lanes - 1) << 1) |
-			   hsw_ddi_buf_ctl_values[i]);
+			   hsw_ddi_buf_ctl_values[i >> 1]);
 		POSTING_READ(DDI_BUF_CTL(PORT_E));
 
 		udelay(600);
-- 
1.7.11.4

[PATCH 17/36] drm/i915: fix Haswell FDI link disable path

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

This covers the "Disable FDI" section from the CRT mode set sequence.
This disables the FDI receiver and also the FDI pll.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c     | 26 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  3 +--
 drivers/gpu/drm/i915/intel_drv.h     |  4 +++-
 3 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 94c6b76..21dfc8a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1363,6 +1363,32 @@ void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
 	udelay(600);
 }
 
+void intel_ddi_fdi_disable(struct drm_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
+	uint32_t val;
+
+	intel_ddi_post_disable(intel_encoder);
+
+	val = I915_READ(_FDI_RXA_CTL);
+	val &= ~FDI_RX_ENABLE;
+	I915_WRITE(_FDI_RXA_CTL, val);
+
+	val = I915_READ(_FDI_RXA_MISC);
+	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
+	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
+	I915_WRITE(_FDI_RXA_MISC, val);
+
+	val = I915_READ(_FDI_RXA_CTL);
+	val &= ~FDI_PCDCLK;
+	I915_WRITE(_FDI_RXA_CTL, val);
+
+	val = I915_READ(_FDI_RXA_CTL);
+	val &= ~FDI_RX_PLL_ENABLE;
+	I915_WRITE(_FDI_RXA_CTL, val);
+}
+
 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e0b1f8c..ee81932 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3563,10 +3563,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 			encoder->post_disable(encoder);
 
 	if (is_pch_port) {
-		ironlake_fdi_disable(crtc);
 		intel_disable_transcoder(dev_priv, pipe);
 		intel_disable_pch_pll(intel_crtc);
-		ironlake_fdi_pll_disable(intel_crtc);
+		intel_ddi_fdi_disable(crtc);
 	}
 
 	intel_crtc->active = false;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 08238ef..bcc5241 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -662,6 +662,8 @@ extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
-bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
+extern bool
+intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
+extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 
 #endif /* __INTEL_DRV_H__ */
-- 
1.7.11.4

[PATCH 18/36] drm/i915: don't write FDI_RX_TUSIZE on lpt_pch_enable

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

This is done way earlier on HSW/LPT and is just wrong here.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ee81932..f9441d1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3142,11 +3142,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 
 	assert_transcoder_disabled(dev_priv, pipe);
 
-	/* Write the TU size bits before fdi link training, so that error
-	 * detection works. */
-	I915_WRITE(FDI_RX_TUSIZE1(pipe),
-		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
-
 	/* XXX: pch pll's can be enabled any time before we enable the PCH
 	 * transcoder, and we actually should do this to not upset any PCH
 	 * transcoder that already use the clock when we share it.
-- 
1.7.11.4

[PATCH 19/36] drm/i915: rename intel_enable_pch_pll to ironlake_enable_pch_pll

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Because this function is only for the older PCHs, not the newer ones.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f9441d1..39f5bd1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1579,14 +1579,14 @@ out_unlock:
 }
 
 /**
- * intel_enable_pch_pll - enable PCH PLL
+ * ironlake_enable_pch_pll - enable PCH PLL
  * @dev_priv: i915 private structure
  * @pipe: pipe PLL to enable
  *
  * The PCH PLL needs to be enabled before the PCH transcoder, since it
  * drives the transcoder clock.
  */
-static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
+static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
 {
 	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
 	struct intel_pch_pll *pll;
@@ -3053,7 +3053,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
 	 * unconditionally resets the pll - we need that to have the right LVDS
 	 * enable sequence. */
-	intel_enable_pch_pll(intel_crtc);
+	ironlake_enable_pch_pll(intel_crtc);
 
 	if (HAS_PCH_CPT(dev)) {
 		u32 sel;
@@ -3149,7 +3149,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
 	 * unconditionally resets the pll - we need that to have the right LVDS
 	 * enable sequence. */
-	intel_enable_pch_pll(intel_crtc);
+	ironlake_enable_pch_pll(intel_crtc);
 
 	lpt_program_iclkip(crtc);
 
-- 
1.7.11.4

[PATCH 20/36] drm/i915: don't call ironlake_enable_pch_pll on lpt_pch_enable

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

This is just wrong. The lpt_program_iclkip should disable the PCH
pixel clocks (and yes, we plan to rename it later).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 39f5bd1..8761023 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3142,15 +3142,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 
 	assert_transcoder_disabled(dev_priv, pipe);
 
-	/* XXX: pch pll's can be enabled any time before we enable the PCH
-	 * transcoder, and we actually should do this to not upset any PCH
-	 * transcoder that already use the clock when we share it.
-	 *
-	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
-	 * unconditionally resets the pll - we need that to have the right LVDS
-	 * enable sequence. */
-	ironlake_enable_pch_pll(intel_crtc);
-
 	lpt_program_iclkip(crtc);
 
 	/* set transcoder timing, panel must allow it */
-- 
1.7.11.4

[PATCH 21/36] drm/i915: don't assert_panel_unlocked on LPT

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

There is no LVDS, so don't poke the LVDS registers.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8761023..da1ba26 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3144,8 +3144,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 
 	lpt_program_iclkip(crtc);
 
-	/* set transcoder timing, panel must allow it */
-	assert_panel_unlocked(dev_priv, pipe);
+	/* Set transcoder timing. */
 	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
 	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
 	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
-- 
1.7.11.4

[PATCH 22/36] drm/i915: use the CPU and PCH transcoders on lpt_pch_enable

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

On Haswell/LPT, pipe, cpu_transcoder and pch_transcoder are different
things with different values, unlinke the previous gens. So here we
use the right thing at the right place.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index da1ba26..53a88e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3138,23 +3138,23 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 
-	assert_transcoder_disabled(dev_priv, pipe);
+	assert_transcoder_disabled(dev_priv, TRANSCODER_A);
 
 	lpt_program_iclkip(crtc);
 
 	/* Set transcoder timing. */
-	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
-	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
-	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
+	I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
+	I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
+	I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
 
-	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
-	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
-	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
-	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
+	I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
+	I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
+	I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
+	I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
 
-	intel_enable_transcoder(dev_priv, pipe);
+	intel_enable_transcoder(dev_priv, intel_crtc->pipe);
 }
 
 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
-- 
1.7.11.4

[PATCH 23/36] drm/i915: rename intel_{en, dis}able_transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

To ironlake_{en,dis}able_pch_transcoder since these functions will be
different on Haswell/LPT and since the "transcoder" they {en,dis}able
is on the PCH.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 53a88e7..50c8848 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1670,8 +1670,8 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
 	pll->on = false;
 }
 
-static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
-				    enum pipe pipe)
+static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
+					   enum pipe pipe)
 {
 	int reg;
 	u32 val, pipeconf_val;
@@ -1721,8 +1721,8 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 		DRM_ERROR("failed to enable transcoder %d\n", pipe);
 }
 
-static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
-				     enum pipe pipe)
+static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
+					    enum pipe pipe)
 {
 	int reg;
 	u32 val;
@@ -3130,7 +3130,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 		I915_WRITE(reg, temp);
 	}
 
-	intel_enable_transcoder(dev_priv, pipe);
+	ironlake_enable_pch_transcoder(dev_priv, pipe);
 }
 
 static void lpt_pch_enable(struct drm_crtc *crtc)
@@ -3154,7 +3154,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
 	I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
 
-	intel_enable_transcoder(dev_priv, intel_crtc->pipe);
+	ironlake_enable_pch_transcoder(dev_priv, intel_crtc->pipe);
 }
 
 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
@@ -3463,7 +3463,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
 	ironlake_fdi_disable(crtc);
 
-	intel_disable_transcoder(dev_priv, pipe);
+	ironlake_disable_pch_transcoder(dev_priv, pipe);
 
 	if (HAS_PCH_CPT(dev)) {
 		/* disable TRANS_DP_CTL */
@@ -3548,7 +3548,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 			encoder->post_disable(encoder);
 
 	if (is_pch_port) {
-		intel_disable_transcoder(dev_priv, pipe);
+		ironlake_disable_pch_transcoder(dev_priv, pipe);
 		intel_disable_pch_pll(intel_crtc);
 		intel_ddi_fdi_disable(crtc);
 	}
-- 
1.7.11.4

[PATCH 24/36] drm/i915: fork lpt version of ironlake_{en, dis}able_pch_transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

For now the new functions are just copies. Differences will be added
later.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 77 +++++++++++++++++++++++++++++++++++-
 1 file changed, 75 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 50c8848..066eb27 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1721,6 +1721,57 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 		DRM_ERROR("failed to enable transcoder %d\n", pipe);
 }
 
+static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
+				      enum pipe pipe)
+{
+	int reg;
+	u32 val, pipeconf_val;
+	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+
+	/* PCH only available on ILK+ */
+	BUG_ON(dev_priv->info->gen < 5);
+
+	/* Make sure PCH DPLL is enabled */
+	assert_pch_pll_enabled(dev_priv,
+			       to_intel_crtc(crtc)->pch_pll,
+			       to_intel_crtc(crtc));
+
+	/* FDI must be feeding us bits for PCH ports */
+	assert_fdi_tx_enabled(dev_priv, pipe);
+	assert_fdi_rx_enabled(dev_priv, pipe);
+
+	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+		DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
+		return;
+	}
+	reg = TRANSCONF(pipe);
+	val = I915_READ(reg);
+	pipeconf_val = I915_READ(PIPECONF(pipe));
+
+	if (HAS_PCH_IBX(dev_priv->dev)) {
+		/*
+		 * make the BPC in transcoder be consistent with
+		 * that in pipeconf reg.
+		 */
+		val &= ~PIPE_BPC_MASK;
+		val |= pipeconf_val & PIPE_BPC_MASK;
+	}
+
+	val &= ~TRANS_INTERLACE_MASK;
+	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
+		if (HAS_PCH_IBX(dev_priv->dev) &&
+		    intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
+			val |= TRANS_LEGACY_INTERLACED_ILK;
+		else
+			val |= TRANS_INTERLACED;
+	else
+		val |= TRANS_PROGRESSIVE;
+
+	I915_WRITE(reg, val | TRANS_ENABLE);
+	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
+		DRM_ERROR("failed to enable transcoder %d\n", pipe);
+}
+
 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 					    enum pipe pipe)
 {
@@ -1743,6 +1794,28 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 		DRM_ERROR("failed to disable transcoder %d\n", pipe);
 }
 
+static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
+				       enum pipe pipe)
+{
+	int reg;
+	u32 val;
+
+	/* FDI relies on the transcoder */
+	assert_fdi_tx_disabled(dev_priv, pipe);
+	assert_fdi_rx_disabled(dev_priv, pipe);
+
+	/* Ports must be off as well */
+	assert_pch_ports_disabled(dev_priv, pipe);
+
+	reg = TRANSCONF(pipe);
+	val = I915_READ(reg);
+	val &= ~TRANS_ENABLE;
+	I915_WRITE(reg, val);
+	/* wait for PCH transcoder off, transcoder state */
+	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
+		DRM_ERROR("failed to disable transcoder %d\n", pipe);
+}
+
 /**
  * intel_enable_pipe - enable a pipe, asserting requirements
  * @dev_priv: i915 private structure
@@ -3154,7 +3227,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
 	I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
 
-	ironlake_enable_pch_transcoder(dev_priv, intel_crtc->pipe);
+	lpt_enable_pch_transcoder(dev_priv, intel_crtc->pipe);
 }
 
 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
@@ -3548,7 +3621,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 			encoder->post_disable(encoder);
 
 	if (is_pch_port) {
-		ironlake_disable_pch_transcoder(dev_priv, pipe);
+		lpt_disable_pch_transcoder(dev_priv, pipe);
 		intel_disable_pch_pll(intel_crtc);
 		intel_ddi_fdi_disable(crtc);
 	}
-- 
1.7.11.4

[PATCH 25/36] drm/i915: remove Haswell code from ironlake_enable_pch_transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Since now we have lpt_enable_pch_transcoder.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 066eb27..763e909 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1689,10 +1689,6 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	assert_fdi_tx_enabled(dev_priv, pipe);
 	assert_fdi_rx_enabled(dev_priv, pipe);
 
-	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
-		DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
-		return;
-	}
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
 	pipeconf_val = I915_READ(PIPECONF(pipe));
-- 
1.7.11.4

[PATCH 26/36] drm/i915: remove IBX code from lpt_enable_pch_transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 763e909..7e8f4ed 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1744,22 +1744,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	val = I915_READ(reg);
 	pipeconf_val = I915_READ(PIPECONF(pipe));
 
-	if (HAS_PCH_IBX(dev_priv->dev)) {
-		/*
-		 * make the BPC in transcoder be consistent with
-		 * that in pipeconf reg.
-		 */
-		val &= ~PIPE_BPC_MASK;
-		val |= pipeconf_val & PIPE_BPC_MASK;
-	}
-
 	val &= ~TRANS_INTERLACE_MASK;
 	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
-		if (HAS_PCH_IBX(dev_priv->dev) &&
-		    intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
-			val |= TRANS_LEGACY_INTERLACED_ILK;
-		else
-			val |= TRANS_INTERLACED;
+		val |= TRANS_INTERLACED;
 	else
 		val |= TRANS_PROGRESSIVE;
 
-- 
1.7.11.4

[PATCH 27/36] drm/i915: don't assert_pch_pll_enabled on lpt_enable_pch_transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

These asserts are specific to IBX/CPT/PPT. Inside the assert_pch_pll
function we even "return" in case we detect LPT, but I prefer to just
not call it. In the future we might rename to something like
ibx_assert_pch_pll.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7e8f4ed..0884137 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1722,16 +1722,10 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 {
 	int reg;
 	u32 val, pipeconf_val;
-	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 
 	/* PCH only available on ILK+ */
 	BUG_ON(dev_priv->info->gen < 5);
 
-	/* Make sure PCH DPLL is enabled */
-	assert_pch_pll_enabled(dev_priv,
-			       to_intel_crtc(crtc)->pch_pll,
-			       to_intel_crtc(crtc));
-
 	/* FDI must be feeding us bits for PCH ports */
 	assert_fdi_tx_enabled(dev_priv, pipe);
 	assert_fdi_rx_enabled(dev_priv, pipe);
-- 
1.7.11.4

[PATCH 28/36] drm/i915: use CPU and PCH transcoders on lpt_enable_pch_transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

... instead of using "pipe". As already explained in previous commits,
since Haswell/LPT cpu_transcoder, pch_transcoder and pipe are not the
same thing.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 24 +++++++++---------------
 1 file changed, 9 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0884137..066994f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1718,25 +1718,19 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 }
 
 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
-				      enum pipe pipe)
+				      enum transcoder cpu_transcoder)
 {
-	int reg;
 	u32 val, pipeconf_val;
 
 	/* PCH only available on ILK+ */
 	BUG_ON(dev_priv->info->gen < 5);
 
 	/* FDI must be feeding us bits for PCH ports */
-	assert_fdi_tx_enabled(dev_priv, pipe);
-	assert_fdi_rx_enabled(dev_priv, pipe);
+	assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
+	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
 
-	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
-		DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
-		return;
-	}
-	reg = TRANSCONF(pipe);
-	val = I915_READ(reg);
-	pipeconf_val = I915_READ(PIPECONF(pipe));
+	val = I915_READ(_TRANSACONF);
+	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
 
 	val &= ~TRANS_INTERLACE_MASK;
 	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
@@ -1744,9 +1738,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	else
 		val |= TRANS_PROGRESSIVE;
 
-	I915_WRITE(reg, val | TRANS_ENABLE);
-	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
-		DRM_ERROR("failed to enable transcoder %d\n", pipe);
+	I915_WRITE(_TRANSACONF, val | TRANS_ENABLE);
+	if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
+		DRM_ERROR("Failed to enable PCH transcoder\n");
 }
 
 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
@@ -3204,7 +3198,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
 	I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
 
-	lpt_enable_pch_transcoder(dev_priv, intel_crtc->pipe);
+	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
 }
 
 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
-- 
1.7.11.4

[PATCH 29/36] drm/i915: use PIPECONF_INTERLACE_MASK_HSW on lpt_enable_pch_transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

... instead of PIPECONF_INTERLACE_MASK.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 066994f..4fbb296 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1733,7 +1733,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
 
 	val &= ~TRANS_INTERLACE_MASK;
-	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
+	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
+	    PIPECONF_INTERLACED_ILK)
 		val |= TRANS_INTERLACED;
 	else
 		val |= TRANS_PROGRESSIVE;
-- 
1.7.11.4

[PATCH 30/36] drm/i915: don't rely on previous values when setting LPT TRANSCONF

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Because we already set all the bits we can set.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4fbb296..10ea4f5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1729,17 +1729,16 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
 	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
 
-	val = I915_READ(_TRANSACONF);
+	val = TRANS_ENABLE;
 	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
 
-	val &= ~TRANS_INTERLACE_MASK;
 	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
 	    PIPECONF_INTERLACED_ILK)
 		val |= TRANS_INTERLACED;
 	else
 		val |= TRANS_PROGRESSIVE;
 
-	I915_WRITE(_TRANSACONF, val | TRANS_ENABLE);
+	I915_WRITE(_TRANSACONF, val);
 	if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
 		DRM_ERROR("Failed to enable PCH transcoder\n");
 }
-- 
1.7.11.4

[PATCH 31/36] drm/i915: don't assert_pch_ports_disabled on LPT

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

That function is made for IBX. Running it on LPT will trigger tons of
"unclaimed register" errors. The only port remaining on LPT is
PCH_ADPA.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 10ea4f5..7d858f8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1775,9 +1775,6 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 	assert_fdi_tx_disabled(dev_priv, pipe);
 	assert_fdi_rx_disabled(dev_priv, pipe);
 
-	/* Ports must be off as well */
-	assert_pch_ports_disabled(dev_priv, pipe);
-
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
 	val &= ~TRANS_ENABLE;
-- 
1.7.11.4

[PATCH 32/36] drm/i915: use CPU and PCH transcoders on lpt_disable_pch_transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

... instead of "pipe", which is wrong.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7d858f8..ae22d4d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1766,22 +1766,20 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 }
 
 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
-				       enum pipe pipe)
+				       enum transcoder cpu_transcoder)
 {
-	int reg;
 	u32 val;
 
 	/* FDI relies on the transcoder */
-	assert_fdi_tx_disabled(dev_priv, pipe);
-	assert_fdi_rx_disabled(dev_priv, pipe);
+	assert_fdi_tx_disabled(dev_priv, cpu_transcoder);
+	assert_fdi_rx_disabled(dev_priv, TRANSCODER_A);
 
-	reg = TRANSCONF(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(_TRANSACONF);
 	val &= ~TRANS_ENABLE;
-	I915_WRITE(reg, val);
+	I915_WRITE(_TRANSACONF, val);
 	/* wait for PCH transcoder off, transcoder state */
-	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
-		DRM_ERROR("failed to disable transcoder %d\n", pipe);
+	if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
+		DRM_ERROR("Failed to disable PCH transcoder\n");
 }
 
 /**
@@ -3589,7 +3587,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 			encoder->post_disable(encoder);
 
 	if (is_pch_port) {
-		lpt_disable_pch_transcoder(dev_priv, pipe);
+		lpt_disable_pch_transcoder(dev_priv, cpu_transcoder);
 		intel_disable_pch_pll(intel_crtc);
 		intel_ddi_fdi_disable(crtc);
 	}
-- 
1.7.11.4

[PATCH 33/36] drm/i915: implement timing override workarounds on LPT

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

These workarounds are documented on the CRT mode set sequence.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ae22d4d..a01901a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1729,6 +1729,11 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
 	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
 
+	/* Workaround: set timing override bit. */
+	val = I915_READ(_TRANSA_CHICKEN2);
+	val |= TRANS_AUTOTRAIN_GEN_STALL_DIS;
+	I915_WRITE(_TRANSA_CHICKEN2, val);
+
 	val = TRANS_ENABLE;
 	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
 
@@ -1780,6 +1785,11 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 	/* wait for PCH transcoder off, transcoder state */
 	if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
 		DRM_ERROR("Failed to disable PCH transcoder\n");
+
+	/* Workaround: clear timing override bit. */
+	val = I915_READ(_TRANSA_CHICKEN2);
+	val &= ~TRANS_AUTOTRAIN_GEN_STALL_DIS;
+	I915_WRITE(_TRANSA_CHICKEN2, val);
 }
 
 /**
-- 
1.7.11.4

[PATCH 34/36] drm/i915: don't intel_disable_pch_pll on Haswell/LPT

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

This function is only for the previous gens.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a01901a..0119b3b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3598,7 +3598,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	if (is_pch_port) {
 		lpt_disable_pch_transcoder(dev_priv, cpu_transcoder);
-		intel_disable_pch_pll(intel_crtc);
 		intel_ddi_fdi_disable(crtc);
 	}
 
-- 
1.7.11.4

[PATCH 35/36] drm/i915: don't limit Haswell CRT encoder to pipe A

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

This is a full revert of 59c859d6f2e78344945e8a8406a194156176bc4e:
    drm/i915: account for only one PCH receiver on Haswell

Now that the PCH code is fixed to be able use the only PCH transcoder
independently of the pipe and CPU transcoder, we can revert this.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c     |  5 +----
 drivers/gpu/drm/i915/intel_display.c | 15 +++------------
 2 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 1c97c27..124fd78 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -764,10 +764,7 @@ void intel_crt_init(struct drm_device *dev)
 
 	crt->base.type = INTEL_OUTPUT_ANALOG;
 	crt->base.cloneable = true;
-	if (IS_HASWELL(dev))
-		crt->base.crtc_mask = (1 << 0);
-	else
-		crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 
 	if (IS_GEN2(dev))
 		connector->interlace_allowed = 0;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0119b3b..c495bfa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1151,14 +1151,9 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 	u32 val;
 	bool cur_state;
 
-	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
-			DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
-			return;
-	} else {
-		reg = FDI_RX_CTL(pipe);
-		val = I915_READ(reg);
-		cur_state = !!(val & FDI_RX_ENABLE);
-	}
+	reg = FDI_RX_CTL(pipe);
+	val = I915_READ(reg);
+	cur_state = !!(val & FDI_RX_ENABLE);
 	WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
@@ -1191,10 +1186,6 @@ static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 	int reg;
 	u32 val;
 
-	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
-		DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
-		return;
-	}
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
-- 
1.7.11.4

[PATCH 36/36] drm/i915: don't assert disabled FDI before disabling the FDI

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

On Haswell/LPT we must disable the PCH transcoder before we disable
the FDI, so don't check for disabled FDI there.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c495bfa..310f2f2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1761,15 +1761,10 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 		DRM_ERROR("failed to disable transcoder %d\n", pipe);
 }
 
-static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
-				       enum transcoder cpu_transcoder)
+static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
 {
 	u32 val;
 
-	/* FDI relies on the transcoder */
-	assert_fdi_tx_disabled(dev_priv, cpu_transcoder);
-	assert_fdi_rx_disabled(dev_priv, TRANSCODER_A);
-
 	val = I915_READ(_TRANSACONF);
 	val &= ~TRANS_ENABLE;
 	I915_WRITE(_TRANSACONF, val);
@@ -3588,7 +3583,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 			encoder->post_disable(encoder);
 
 	if (is_pch_port) {
-		lpt_disable_pch_transcoder(dev_priv, cpu_transcoder);
+		lpt_disable_pch_transcoder(dev_priv);
 		intel_ddi_fdi_disable(crtc);
 	}
 
-- 
1.7.11.4

Re: [PATCH 06/36] drm/i915: train Haswell FDI at the right time

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:25PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Haswell FDI link training is very different from the previous
> generations.
> 
> After this commit, hsw_fdi_link_train is responsible for implementing
> all the steps described as "Enable and train FDI" from the Haswell
> CRT mode set sequence documentation.
> 
> We need to train the FDI before enabling the pipes and planes, so
> we're moving the call from lpt_pch_enable to haswell_crtc_enable
> directly.
> 
> We are also removing ironlake_fdi_pll_enable since the PLL enablement
> on Haswell is completely different and is also done during the link
> training steps.
> 
> There are still quite a few things we need to fix on
> hsw_fdi_link_train, so stay tuned for the next patches :)
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 17 +++++++++++------
>  drivers/gpu/drm/i915/intel_ddi.c     | 34 ++++++++++++++++++++++++----------
>  drivers/gpu/drm/i915/intel_display.c |  5 +----
>  3 files changed, 36 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0514823..abdc002 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3917,16 +3917,21 @@
>  #define  FDI_PORT_WIDTH_2X_LPT			(1<<19)
>  #define  FDI_PORT_WIDTH_1X_LPT			(0<<19)
>  
> -#define _FDI_RXA_MISC            0xf0010
> -#define _FDI_RXB_MISC            0xf1010
> +#define _FDI_RXA_MISC			0xf0010
> +#define _FDI_RXB_MISC			0xf1010
> +#define  FDI_RX_PWRDN_LANE1_MASK	(3<<26)
> +#define  FDI_RX_PWRDN_LANE1_VAL(x)	((x)<<26)
> +#define  FDI_RX_PWRDN_LANE0_MASK	(3<<24)
> +#define  FDI_RX_PWRDN_LANE0_VAL(x)	((x)<<24)
> +#define  FDI_RX_TP1_TO_TP2_48		(2<<20)
> +#define  FDI_RX_TP1_TO_TP2_64		(3<<20)
> +#define  FDI_RX_FDI_DELAY_90		(0x90<<0)
> +#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
> +
>  #define _FDI_RXA_TUSIZE1         0xf0030
>  #define _FDI_RXA_TUSIZE2         0xf0038
>  #define _FDI_RXB_TUSIZE1         0xf1030
>  #define _FDI_RXB_TUSIZE2         0xf1038
> -#define  FDI_RX_TP1_TO_TP2_48	(2<<20)
> -#define  FDI_RX_TP1_TO_TP2_64	(3<<20)
> -#define  FDI_RX_FDI_DELAY_90	(0x90<<0)
> -#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
>  #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
>  #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
>  
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 67bd6ba..39a53b4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -154,7 +154,30 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	int pipe = intel_crtc->pipe;
> -	u32 reg, temp, i;
> +	u32 reg, temp, i, rx_ctl_val;
> +
> +	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
> +	 * mode set "sequence for CRT port" document:
> +	 * - TP1 to TP2 time with the default value
> +	 * - FDI delay to 90h
> +	 */
> +	I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
> +				  FDI_RX_PWRDN_LANE0_VAL(2) |
> +				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
> +
> +	/* Enable the PCH Receiver FDI PLL */
> +	rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE |
> +		     ((intel_crtc->fdi_lanes - 1) << 19);

You switch here to a variable selection of the port width/number of fdi
lanes you're using on the RX side. But the TX side below is still fixed to
2X. I guess this part here belongs in another patch?
-Daniel

> +	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> +	POSTING_READ(_FDI_RXA_CTL);
> +	udelay(220);
> +
> +	/* Switch from Rawclk to PCDclk */
> +	rx_ctl_val |= FDI_PCDCLK;
> +	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> +
> +	/* Configure Port Clock Select */
> +	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
>  
>  	/* Start the training iterating through available voltages and emphasis */
>  	for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
> @@ -176,15 +199,6 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  
>  		udelay(600);
>  
> -		/* We need to program FDI_RX_MISC with the default TP1 to TP2
> -		 * values before enabling the receiver, and configure the delay
> -		 * for the FDI timing generator to 90h. Luckily, all the other
> -		 * bits are supposed to be zeroed, so we can write those values
> -		 * directly.
> -		 */
> -		I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 |
> -				FDI_RX_FDI_DELAY_90);
> -
>  		/* Enable CPU FDI Receiver with auto-training */
>  		reg = FDI_RX_CTL(pipe);
>  		I915_WRITE(reg,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2dff7b2..e0b1f8c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3147,9 +3147,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
>  	I915_WRITE(FDI_RX_TUSIZE1(pipe),
>  		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
>  
> -	/* For PCH output, training FDI link */
> -	dev_priv->display.fdi_link_train(crtc);
> -
>  	/* XXX: pch pll's can be enabled any time before we enable the PCH
>  	 * transcoder, and we actually should do this to not upset any PCH
>  	 * transcoder that already use the clock when we share it.
> @@ -3389,7 +3386,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	is_pch_port = haswell_crtc_driving_pch(crtc);
>  
>  	if (is_pch_port)
> -		ironlake_fdi_pll_enable(intel_crtc);
> +		dev_priv->display.fdi_link_train(crtc);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 07/36] drm/i915: use the right FDI_RX_CTL register on Haswell

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:26PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> There is only one PCH transcoder, so it's always _FDI_RXA_CTL. Using
> "pipe" here is wrong.
> 
> While at it, also reuse the rx_ctl_val variable created in the
> previous commit.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 24 ++++++++----------------
>  1 file changed, 8 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 39a53b4..c397da3 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -153,8 +153,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	int pipe = intel_crtc->pipe;
> -	u32 reg, temp, i, rx_ctl_val;
> +	u32 temp, i, rx_ctl_val;
>  
>  	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
>  	 * mode set "sequence for CRT port" document:
> @@ -199,17 +198,10 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  
>  		udelay(600);
>  
> -		/* Enable CPU FDI Receiver with auto-training */
> -		reg = FDI_RX_CTL(pipe);
> -		I915_WRITE(reg,
> -				I915_READ(reg) |
> -					FDI_LINK_TRAIN_AUTO |
> -					FDI_RX_ENABLE |
> -					FDI_LINK_TRAIN_PATTERN_1_CPT |

The LINK_TRAIN_PAT1 here seems to disappear. Is that simply because when
using auto training, we may not set this? If so, please mention that in
the commit message. All the other flags are set, safe for ...
> -					FDI_RX_ENHANCE_FRAME_ENABLE |
> -					FDI_PORT_WIDTH_2X_LPT |

... dropping the 2X_LPT mode here will blow up on low-res, see my comment
in the previous patch.
-Daniel

> -					FDI_RX_PLL_ENABLE);
> -		POSTING_READ(reg);
> +		/* Enable PCH FDI Receiver with auto-training */
> +		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
> +		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> +		POSTING_READ(_FDI_RXA_CTL);
>  		udelay(100);
>  
>  		temp = I915_READ(DP_TP_STATUS(PORT_E));
> @@ -231,9 +223,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  			I915_WRITE(DP_TP_CTL(PORT_E),
>  					I915_READ(DP_TP_CTL(PORT_E)) &
>  						~DP_TP_CTL_ENABLE);
> -			I915_WRITE(FDI_RX_CTL(pipe),
> -					I915_READ(FDI_RX_CTL(pipe)) &
> -						~FDI_RX_PLL_ENABLE);
> +
> +			rx_ctl_val &= ~FDI_RX_PLL_ENABLE;
> +			I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
>  			continue;
>  		}
>  	}
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 10/36] drm/i915: program the FDI RX TUSIZE register on hsw_fdi_link_train

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:29PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> According to the mode set sequence documentation, this is the right
> place. According to the FDI_RX_TUSIZE register description, this is
> the value we should set.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 0cb6441..5d33f62 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -196,6 +196,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  
>  		udelay(600);
>  
> +		/* Program PCH FDI Receiver TU */
> +		I915_WRITE(_FDI_RXA_TUSIZE1, 0x7E000000);
> +

I think you also want to remove the setting of RX_TU_SIZE in
lpt_pch_enable. And we have nice symbolic constants to encode that 0-based
64 shifter by 25 bits ...
-Daniel

>  		/* Enable PCH FDI Receiver with auto-training */
>  		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
>  		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 11/36] drm/i915: properly program FDI_RX_MISC pwrdn lane values on HSW

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:30PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> That's what our mode set sequence documentation says we need to do.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

As already bikeshedded on irc, I think the comment is a bit useless.
Instead of "program foo" I think "set foo in bla" and "unset foo in bla"
explains more ...
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 5d33f62..0239888 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -205,6 +205,12 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  		POSTING_READ(_FDI_RXA_CTL);
>  		udelay(100);
>  
> +		/* Program FDI_RX_MISC pwrdn lanes */
> +		temp = I915_READ(_FDI_RXA_MISC);
> +		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> +		I915_WRITE(_FDI_RXA_MISC, temp);
> +		POSTING_READ(_FDI_RXA_MISC);
> +
>  		temp = I915_READ(DP_TP_STATUS(PORT_E));
>  		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
>  			DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i);
> @@ -227,6 +233,14 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  
>  			rx_ctl_val &= ~FDI_RX_PLL_ENABLE;
>  			I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> +
> +			temp = I915_READ(_FDI_RXA_MISC);
> +			temp &= ~(FDI_RX_PWRDN_LANE1_MASK |
> +				  FDI_RX_PWRDN_LANE0_MASK);
> +			temp |= FDI_RX_PWRDN_LANE1_VAL(2) |
> +				FDI_RX_PWRDN_LANE0_VAL(2);
> +			I915_WRITE(_FDI_RXA_MISC, temp);
> +
>  			continue;
>  		}
>  	}
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 16/36] drm/i915: try each voltage twice at hsw_fdi_link_train

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:35PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> From the mode set sequence document: "Each setting should be tried at
> least twice before failing mode set".
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f8ca3c4..94c6b76 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -179,7 +179,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
>  
>  	/* Start the training iterating through available voltages and emphasis */
> -	for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
> +	for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
>  		/* Configure DP_TP_CTL with auto-training */
>  		I915_WRITE(DP_TP_CTL(PORT_E),
>  					DP_TP_CTL_FDI_AUTOTRAIN |
> @@ -191,7 +191,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  		I915_WRITE(DDI_BUF_CTL(PORT_E),
>  			   DDI_BUF_CTL_ENABLE |
>  			   ((intel_crtc->fdi_lanes - 1) << 1) |
> -			   hsw_ddi_buf_ctl_values[i]);
> +			   hsw_ddi_buf_ctl_values[i >> 1]);

I think a simple / 2 is clearer here and symmetric with the * 2 above. The
compiler will apply clever tricks for you anyway ;-)
-Daniel

>  		POSTING_READ(DDI_BUF_CTL(PORT_E));
>  
>  		udelay(600);
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 18/36] drm/i915: don't write FDI_RX_TUSIZE on lpt_pch_enable

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:37PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> This is done way earlier on HSW/LPT and is just wrong here.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Ok, I'll probably regret it right away, but I think splitting the fdi link
training code up into that many patches was a bit too much - imo it makes
reviewing more painful, since you can essentially only check things once
you have all patches applied and can look at the end result.

So in hindsight I think the following 2 patches would have been good
enough:
- move RX_TU_SIZE programming to the right spot (since that also touches
  code outside of the fdi link train code)
- fixup the fdi link train. It is essentially a complete rewrite, it's not
  a lot of code (I think just 100 lines in the end), and you pretty much
  can only check the end result with bspec. Ofc, this commit needs a nice
  big commit message that explains all the little fixes that have been
  required.

In a way this is a special case, since all the changes are concentrated
in just one fucntion and don't have any implications towards other code
outside of that function.

For other fixes that are not so well contained, I still prefer small
patches over big patches ;-)

Cheers, Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ee81932..f9441d1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3142,11 +3142,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
>  
>  	assert_transcoder_disabled(dev_priv, pipe);
>  
> -	/* Write the TU size bits before fdi link training, so that error
> -	 * detection works. */
> -	I915_WRITE(FDI_RX_TUSIZE1(pipe),
> -		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
> -
>  	/* XXX: pch pll's can be enabled any time before we enable the PCH
>  	 * transcoder, and we actually should do this to not upset any PCH
>  	 * transcoder that already use the clock when we share it.
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 19/36] drm/i915: rename intel_enable_pch_pll to ironlake_enable_pch_pll

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:38PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Because this function is only for the older PCHs, not the newer ones.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Ok, I've merged patches 1-6 plus this one here for now. gtg, will resume
reviewing afterwards.

Thanks a lot for digging through this mess.

Cheers, Daniel
> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f9441d1..39f5bd1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1579,14 +1579,14 @@ out_unlock:
>  }
>  
>  /**
> - * intel_enable_pch_pll - enable PCH PLL
> + * ironlake_enable_pch_pll - enable PCH PLL
>   * @dev_priv: i915 private structure
>   * @pipe: pipe PLL to enable
>   *
>   * The PCH PLL needs to be enabled before the PCH transcoder, since it
>   * drives the transcoder clock.
>   */
> -static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
> +static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
>  {
>  	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
>  	struct intel_pch_pll *pll;
> @@ -3053,7 +3053,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
>  	 * unconditionally resets the pll - we need that to have the right LVDS
>  	 * enable sequence. */
> -	intel_enable_pch_pll(intel_crtc);
> +	ironlake_enable_pch_pll(intel_crtc);
>  
>  	if (HAS_PCH_CPT(dev)) {
>  		u32 sel;
> @@ -3149,7 +3149,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
>  	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
>  	 * unconditionally resets the pll - we need that to have the right LVDS
>  	 * enable sequence. */
> -	intel_enable_pch_pll(intel_crtc);
> +	ironlake_enable_pch_pll(intel_crtc);
>  
>  	lpt_program_iclkip(crtc);
>  
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 27/36] drm/i915: don't assert_pch_pll_enabled on lpt_enable_pch_transcoder

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:46PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> These asserts are specific to IBX/CPT/PPT. Inside the assert_pch_pll
> function we even "return" in case we detect LPT, but I prefer to just
> not call it. In the future we might rename to something like
> ibx_assert_pch_pll.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Can't we now remove the HAS_LPT check from assert_pch_pll? Afaics we only
call it from ilk_pch_transcoder_enable and from the pch_pll handling
functions, both of which should no longer be called from haswell code.

For renaming them, I think that particular problem will solve itself once
we move all the ilk-ivb crtc/pch code into it's own file. With all these
splits you've done here for vga, I don't see much common code between
older pch and new-style ddi pch any more ...
-Daniel
> ---
>  drivers/gpu/drm/i915/intel_display.c | 6 ------
>  1 file changed, 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7e8f4ed..0884137 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1722,16 +1722,10 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  {
>  	int reg;
>  	u32 val, pipeconf_val;
> -	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
>  
>  	/* PCH only available on ILK+ */
>  	BUG_ON(dev_priv->info->gen < 5);
>  
> -	/* Make sure PCH DPLL is enabled */
> -	assert_pch_pll_enabled(dev_priv,
> -			       to_intel_crtc(crtc)->pch_pll,
> -			       to_intel_crtc(crtc));
> -
>  	/* FDI must be feeding us bits for PCH ports */
>  	assert_fdi_tx_enabled(dev_priv, pipe);
>  	assert_fdi_rx_enabled(dev_priv, pipe);
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 29/36] drm/i915: use PIPECONF_INTERLACE_MASK_HSW on lpt_enable_pch_transcoder

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:48PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> ... instead of PIPECONF_INTERLACE_MASK.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

My Bspec here still has bits 23:21 for the interlaced bits on the lpt pch,
but everything with bit 23 set is a reserved value. Sinc we set the
correct stuff anyway, I don't think we need to change the mask here - the
same would apply to cpt. So I'll drop this one here.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 066994f..4fbb296 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1733,7 +1733,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
>  
>  	val &= ~TRANS_INTERLACE_MASK;
> -	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
> +	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
> +	    PIPECONF_INTERLACED_ILK)
>  		val |= TRANS_INTERLACED;
>  	else
>  		val |= TRANS_PROGRESSIVE;
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 31/36] drm/i915: don't assert_pch_ports_disabled on LPT

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:50PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> That function is made for IBX. Running it on LPT will trigger tons of
> "unclaimed register" errors. The only port remaining on LPT is
> PCH_ADPA.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Actually I've had to stay around for a while longer before heading off, so
reviewed and applied a few more patches, up to this one here (minus the
one I've dropped).

Thanks, Daniel
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 10ea4f5..7d858f8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1775,9 +1775,6 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
>  	assert_fdi_tx_disabled(dev_priv, pipe);
>  	assert_fdi_rx_disabled(dev_priv, pipe);
>  
> -	/* Ports must be off as well */
> -	assert_pch_ports_disabled(dev_priv, pipe);
> -
>  	reg = TRANSCONF(pipe);
>  	val = I915_READ(reg);
>  	val &= ~TRANS_ENABLE;
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 07/36] drm/i915: use the right FDI_RX_CTL register on Haswell

[Paulo Zanoni]

Hi

2012/11/1 Daniel Vetter <daniel@ffwll.ch>:
> On Wed, Oct 31, 2012 at 06:12:26PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> There is only one PCH transcoder, so it's always _FDI_RXA_CTL. Using
>> "pipe" here is wrong.
>>
>> While at it, also reuse the rx_ctl_val variable created in the
>> previous commit.
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_ddi.c | 24 ++++++++----------------
>>  1 file changed, 8 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 39a53b4..c397da3 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -153,8 +153,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>>       struct drm_device *dev = crtc->dev;
>>       struct drm_i915_private *dev_priv = dev->dev_private;
>>       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> -     int pipe = intel_crtc->pipe;
>> -     u32 reg, temp, i, rx_ctl_val;
>> +     u32 temp, i, rx_ctl_val;
>>
>>       /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
>>        * mode set "sequence for CRT port" document:
>> @@ -199,17 +198,10 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>>
>>               udelay(600);
>>
>> -             /* Enable CPU FDI Receiver with auto-training */
>> -             reg = FDI_RX_CTL(pipe);
>> -             I915_WRITE(reg,
>> -                             I915_READ(reg) |
>> -                                     FDI_LINK_TRAIN_AUTO |
>> -                                     FDI_RX_ENABLE |
>> -                                     FDI_LINK_TRAIN_PATTERN_1_CPT |
>
> The LINK_TRAIN_PAT1 here seems to disappear. Is that simply because when
> using auto training, we may not set this? If so, please mention that in
> the commit message. All the other flags are set, safe for ...
>> -                                     FDI_RX_ENHANCE_FRAME_ENABLE |
>> -                                     FDI_PORT_WIDTH_2X_LPT |
>
> ... dropping the 2X_LPT mode here will blow up on low-res, see my comment
> in the previous patch.

It would blow up if everything else was actually working...

If you take a look at intel_ddi_enable_pipe_func, you will see that
before my series it sets the width to 1x where the other pieces of our
code set to 2x, which is just wrong. On my series, as I change the
functions I change them to use the "correct width", and after patch 8
we do have the "correct width" being set, but VGA really doesn't work
yet because of the other thousand problems it has: you can't notice
the difference in patch 8 because you need all the other future fixes.

So I really think we should just assume VGA is a total failure until
before the very last patch :)

> -Daniel
>
>> -                                     FDI_RX_PLL_ENABLE);
>> -             POSTING_READ(reg);
>> +             /* Enable PCH FDI Receiver with auto-training */
>> +             rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
>> +             I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
>> +             POSTING_READ(_FDI_RXA_CTL);
>>               udelay(100);
>>
>>               temp = I915_READ(DP_TP_STATUS(PORT_E));
>> @@ -231,9 +223,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>>                       I915_WRITE(DP_TP_CTL(PORT_E),
>>                                       I915_READ(DP_TP_CTL(PORT_E)) &
>>                                               ~DP_TP_CTL_ENABLE);
>> -                     I915_WRITE(FDI_RX_CTL(pipe),
>> -                                     I915_READ(FDI_RX_CTL(pipe)) &
>> -                                             ~FDI_RX_PLL_ENABLE);
>> +
>> +                     rx_ctl_val &= ~FDI_RX_PLL_ENABLE;
>> +                     I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
>>                       continue;
>>               }
>>       }
>> --
>> 1.7.11.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



-- 
Paulo Zanoni

Re: [PATCH 29/36] drm/i915: use PIPECONF_INTERLACE_MASK_HSW on lpt_enable_pch_transcoder

[Paulo Zanoni]

Hi

2012/11/1 Daniel Vetter <daniel@ffwll.ch>:
> On Wed, Oct 31, 2012 at 06:12:48PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> ... instead of PIPECONF_INTERLACE_MASK.
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> My Bspec here still has bits 23:21 for the interlaced bits on the lpt pch,
> but everything with bit 23 set is a reserved value. Sinc we set the
> correct stuff anyway, I don't think we need to change the mask here - the
> same would apply to cpt. So I'll drop this one here.

But here we're dealing with "pipeconf_val" which the value we read in
PIPECONF, which is on the CPU, not on the PCH.

TRANS_CONF has bits 23:21 for the interlaced mode, but PIPECONF has
bits 22:21 for the interlaced mode. We're reading from PIPECONF to
write to TRANSCONF, but the mask is being applied to pipeconf, so the
mask should be 22:21.

I still think my patch is correct.

> -Daniel
>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 066994f..4fbb296 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -1733,7 +1733,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>>       pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
>>
>>       val &= ~TRANS_INTERLACE_MASK;
>> -     if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
>> +     if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
>> +         PIPECONF_INTERLACED_ILK)
>>               val |= TRANS_INTERLACED;
>>       else
>>               val |= TRANS_PROGRESSIVE;
>> --
>> 1.7.11.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



-- 
Paulo Zanoni

Re: [PATCH 29/36] drm/i915: use PIPECONF_INTERLACE_MASK_HSW on lpt_enable_pch_transcoder

[Daniel Vetter]

On Thu, Nov 01, 2012 at 02:53:40PM -0200, Paulo Zanoni wrote:
> Hi
> 
> 2012/11/1 Daniel Vetter <daniel@ffwll.ch>:
> > On Wed, Oct 31, 2012 at 06:12:48PM -0200, Paulo Zanoni wrote:
> >> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >>
> >> ... instead of PIPECONF_INTERLACE_MASK.
> >>
> >> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > My Bspec here still has bits 23:21 for the interlaced bits on the lpt pch,
> > but everything with bit 23 set is a reserved value. Sinc we set the
> > correct stuff anyway, I don't think we need to change the mask here - the
> > same would apply to cpt. So I'll drop this one here.
> 
> But here we're dealing with "pipeconf_val" which the value we read in
> PIPECONF, which is on the CPU, not on the PCH.
> 
> TRANS_CONF has bits 23:21 for the interlaced mode, but PIPECONF has
> bits 22:21 for the interlaced mode. We're reading from PIPECONF to
> write to TRANSCONF, but the mask is being applied to pipeconf, so the
> mask should be 22:21.
> 
> I still think my patch is correct.

Ah, now I see, thanks for the correction, patch applied.

Btw, while reading Bspec I've noticed some restrictions on the interlaced
mode we're using (i.e. progressive->interlaced conversion): We seem to
need a 7x5 panel fitter (which doesn't exist on all pipes) and have a
limit of 2048 on the source width ...
-Daniel
> 
> > -Daniel
> >
> >> ---
> >>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
> >>  1 file changed, 2 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> index 066994f..4fbb296 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -1733,7 +1733,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> >>       pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
> >>
> >>       val &= ~TRANS_INTERLACE_MASK;
> >> -     if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
> >> +     if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
> >> +         PIPECONF_INTERLACED_ILK)
> >>               val |= TRANS_INTERLACED;
> >>       else
> >>               val |= TRANS_PROGRESSIVE;
> >> --
> >> 1.7.11.4
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 36/36] drm/i915: don't assert disabled FDI before disabling the FDI

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:55PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> On Haswell/LPT we must disable the PCH transcoder before we disable
> the FDI, so don't check for disabled FDI there.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Ok, I've slurped in the last few patches here, safe for patch 35, I'll do
that last. Next up: fdi link train madness ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch