* [PATCH 1/2] tests: storedw on VEBOX
2012-11-14 4:55 [PATCH 0/2] test cases for the new ring on Haswell Xiang, Haihao
@ 2012-11-14 4:55 ` Xiang, Haihao
2012-11-14 4:55 ` [PATCH 2/2] Update gem_ring_sync_loop to support VEBOX ring (the 4th ring) on Haswell Xiang, Haihao
2012-11-14 8:23 ` [PATCH 0/2] test cases for the new ring " Chris Wilson
2 siblings, 0 replies; 5+ messages in thread
From: Xiang, Haihao @ 2012-11-14 4:55 UTC (permalink / raw)
To: intel-gfx
From: "Xiang, Haihao" <haihao.xiang@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
---
lib/intel_chipset.h | 2 +
tests/Makefile.am | 1 +
tests/gem_storedw_loop_vebox.c | 153 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 156 insertions(+)
create mode 100644 tests/gem_storedw_loop_vebox.c
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 9dd4c94..0433a75 100755
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -268,3 +268,5 @@
#define IS_CRESTLINE(devid) (devid == PCI_CHIP_I965_GM || \
devid == PCI_CHIP_I965_GME)
+
+#define HAS_VEBOX_RING(devid) (IS_HASWELL(devid))
diff --git a/tests/Makefile.am b/tests/Makefile.am
index d4c7c46..9a0e509 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -58,6 +58,7 @@ TESTS_progs = \
gem_storedw_loop_render \
gem_storedw_loop_blt \
gem_storedw_loop_bsd \
+ gem_storedw_loop_vebox \
gem_storedw_batches_loop \
gem_dummy_reloc_loop \
gem_double_irq_loop \
diff --git a/tests/gem_storedw_loop_vebox.c b/tests/gem_storedw_loop_vebox.c
new file mode 100644
index 0000000..3f06102
--- /dev/null
+++ b/tests/gem_storedw_loop_vebox.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang, Haihao <haihao.xiang@intel.com>
+ * Eric Anholt <eric@anholt.net>
+ * Jesse Barnes <jbarnes@virtuousgeek.org> (based on gem_bad_blit.c)
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "i915_drm.h"
+#include "drmtest.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "intel_gpu_tools.h"
+
+static drm_intel_bufmgr *bufmgr;
+struct intel_batchbuffer *batch;
+static drm_intel_bo *target_buffer;
+static int has_ppgtt = 0;
+
+/*
+ * Testcase: Basic vebox MI check using MI_STORE_DATA_IMM
+ */
+
+static void
+store_dword_loop(void)
+{
+ int cmd, i, val = 0;
+ uint32_t *buf;
+
+ cmd = MI_STORE_DWORD_IMM;
+ if (!has_ppgtt)
+ cmd |= MI_MEM_VIRTUAL;
+
+ for (i = 0; i < 0x100000; i++) {
+ BEGIN_BATCH(4);
+ OUT_BATCH(cmd);
+ OUT_BATCH(0); /* reserved */
+ OUT_RELOC(target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
+ OUT_BATCH(val);
+ ADVANCE_BATCH();
+
+ intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
+
+ drm_intel_bo_map(target_buffer, 0);
+
+ buf = target_buffer->virtual;
+ if (buf[0] != val) {
+ fprintf(stderr,
+ "value mismatch: cur 0x%08x, stored 0x%08x\n",
+ buf[0], val);
+ exit(-1);
+ }
+
+ drm_intel_bo_unmap(target_buffer);
+
+ val++;
+ }
+
+ drm_intel_bo_map(target_buffer, 0);
+ buf = target_buffer->virtual;
+
+ printf("completed %d writes successfully, current value: 0x%08x\n", i,
+ buf[0]);
+ drm_intel_bo_unmap(target_buffer);
+}
+
+int main(int argc, char **argv)
+{
+ int fd;
+ int devid;
+
+ if (argc != 1) {
+ fprintf(stderr, "usage: %s\n", argv[0]);
+ exit(-1);
+ }
+
+ fd = drm_open_any();
+ devid = intel_get_drm_devid(fd);
+
+ if (!HAS_VEBOX_RING(devid)) {
+ fprintf(stderr, "Doesn't have vebox ring\n");
+ return 77;
+ }
+
+ has_ppgtt = gem_uses_aliasing_ppgtt(fd);
+
+ /* This only works with ppgtt */
+ if (!has_ppgtt) {
+ fprintf(stderr, "no ppgtt detected, which is required\n");
+ return 77;
+ }
+
+ bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+ if (!bufmgr) {
+ fprintf(stderr, "failed to init libdrm\n");
+ exit(-1);
+ }
+ drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+ if (!batch) {
+ fprintf(stderr, "failed to create batch buffer\n");
+ exit(-1);
+ }
+
+ target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
+ if (!target_buffer) {
+ fprintf(stderr, "failed to alloc target buffer\n");
+ exit(-1);
+ }
+
+ store_dword_loop();
+
+ drm_intel_bo_unreference(target_buffer);
+ intel_batchbuffer_free(batch);
+ drm_intel_bufmgr_destroy(bufmgr);
+
+ close(fd);
+
+ return 0;
+}
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] Update gem_ring_sync_loop to support VEBOX ring (the 4th ring) on Haswell
2012-11-14 4:55 [PATCH 0/2] test cases for the new ring on Haswell Xiang, Haihao
2012-11-14 4:55 ` [PATCH 1/2] tests: storedw on VEBOX Xiang, Haihao
@ 2012-11-14 4:55 ` Xiang, Haihao
2012-11-14 8:23 ` [PATCH 0/2] test cases for the new ring " Chris Wilson
2 siblings, 0 replies; 5+ messages in thread
From: Xiang, Haihao @ 2012-11-14 4:55 UTC (permalink / raw)
To: intel-gfx
From: "Xiang, Haihao" <haihao.xiang@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
---
tests/gem_ring_sync_loop.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/tests/gem_ring_sync_loop.c b/tests/gem_ring_sync_loop.c
index b689bcd..199dcfd 100644
--- a/tests/gem_ring_sync_loop.c
+++ b/tests/gem_ring_sync_loop.c
@@ -56,14 +56,26 @@ static drm_intel_bo *target_buffer;
#define MI_DO_COMPARE (1<<21)
static void
-store_dword_loop(void)
+store_dword_loop(int devid)
{
int i;
+ int num_rings = 3;
srandom(0xdeadbeef);
+ if (IS_HASWELL(devid))
+ num_rings = 4;
+ else if (IS_IVYBRIDGE(devid) || IS_GEN6(devid))
+ num_rings = 3;
+ else if (IS_GEN5(devid) || IS_G4X(devid))
+ num_rings = 2;
+ else
+ num_rings = 1;
+
+ fprintf(stderr, "The number of rings: %d\n", num_rings);
+
for (i = 0; i < 0x100000; i++) {
- int ring = random() % 3 + 1;
+ int ring = random() % num_rings + 1;
if (ring == I915_EXEC_RENDER) {
BEGIN_BATCH(4);
@@ -127,7 +139,7 @@ int main(int argc, char **argv)
exit(-1);
}
- store_dword_loop();
+ store_dword_loop(devid);
drm_intel_bo_unreference(target_buffer);
intel_batchbuffer_free(batch);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread