[U-Boot] [PATCH 00/10] Add Marvell Dove and SolidRun CuBox

[U-Boot] [PATCH 00/10] Add Marvell Dove and SolidRun CuBox

[Sebastian Hesselbarth]

This patch set add support for the Marvell Dove 88AP510 SoC and
the SolidRun CuBox board based on that SoC. The patch set is divided
into the four following sections:

(1) Patches 1-5:
Add support for the Dove SoC and related drivers. Where possible
drivers from Marvell Kirkwood are reused (mvsata, mvgbe), or
forked to allow more generic usage (SPI, GPIO). The SDHCI driver
is different and a new driver is added for it. The forked drivers
can also be reused on Kirkwood but that would have required patching
existing boards.

(2) Patches 6-8:
Allow mvgbe to use the phylib API, add support for 88E1310 PHY and
allow Dove to use the driver.

(3) Patch 9
Add the SolidRun CuBox as the first board based on Marvell Dove SoC.

(4) Patch 10
Add support for different UART boot mode found on Dove.

Sebastian Hesselbarth (10):
  ARM: dove: add support for Marvell Dove SoC
  GPIO: add gpio driver for Orion SoCs
  MMC: sdhci: Add support for dove sdhci
  SPI: Add Orion SPI driver
  block: mvsata: add dove include
  NET: phy: add 88E1310 PHY initialization
  NET: mvgbe: add phylib support
  NET: mvgbe: add support for Dove
  Boards: Add support for SolidRun CuBox
  tools: Add support for Dove to kwboot

 arch/arm/cpu/armv7/dove/Makefile        |   49 +++++
 arch/arm/cpu/armv7/dove/cpu.c           |  266 ++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/dram.c          |  116 +++++++++++
 arch/arm/cpu/armv7/dove/lowlevel_init.S |   83 ++++++++
 arch/arm/cpu/armv7/dove/mpp.c           |  319 +++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/timer.c         |  176 +++++++++++++++++
 arch/arm/cpu/armv7/dove/usb.c           |  101 ++++++++++
 arch/arm/include/asm/arch-dove/config.h |  153 +++++++++++++++
 arch/arm/include/asm/arch-dove/cpu.h    |  204 ++++++++++++++++++++
 arch/arm/include/asm/arch-dove/dove.h   |   93 +++++++++
 arch/arm/include/asm/arch-dove/gpio.h   |   35 ++++
 arch/arm/include/asm/arch-dove/mpp.h    |  283 +++++++++++++++++++++++++++
 board/solidrun/cubox/Makefile           |   45 +++++
 board/solidrun/cubox/cubox.c            |  141 ++++++++++++++
 board/solidrun/cubox/kwbimage.cfg       |   76 ++++++++
 boards.cfg                              |    1 +
 drivers/block/mvsata_ide.c              |    2 +
 drivers/gpio/Makefile                   |    1 +
 drivers/gpio/orion_gpio.c               |  167 ++++++++++++++++
 drivers/mmc/Makefile                    |    1 +
 drivers/mmc/dove_sdhci.c                |  101 ++++++++++
 drivers/net/mvgbe.c                     |   70 ++++++-
 drivers/net/mvgbe.h                     |    7 +
 drivers/net/phy/marvell.c               |   48 +++++
 drivers/spi/Makefile                    |    1 +
 drivers/spi/orion_spi.c                 |  217 +++++++++++++++++++++
 include/configs/cubox.h                 |  175 +++++++++++++++++
 include/orion_gpio.h                    |   64 +++++++
 tools/Makefile                          |    2 +
 tools/kwboot.c                          |   44 ++++-
 30 files changed, 3033 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/dove/Makefile
 create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
 create mode 100644 arch/arm/cpu/armv7/dove/dram.c
 create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
 create mode 100644 arch/arm/cpu/armv7/dove/timer.c
 create mode 100644 arch/arm/cpu/armv7/dove/usb.c
 create mode 100644 arch/arm/include/asm/arch-dove/config.h
 create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
 create mode 100644 arch/arm/include/asm/arch-dove/dove.h
 create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
 create mode 100644 arch/arm/include/asm/arch-dove/mpp.h
 create mode 100644 board/solidrun/cubox/Makefile
 create mode 100644 board/solidrun/cubox/cubox.c
 create mode 100644 board/solidrun/cubox/kwbimage.cfg
 create mode 100644 drivers/gpio/orion_gpio.c
 create mode 100644 drivers/mmc/dove_sdhci.c
 create mode 100644 drivers/spi/orion_spi.c
 create mode 100644 include/configs/cubox.h
 create mode 100644 include/orion_gpio.h

---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
-- 
1.7.10.4

[U-Boot] [PATCH 01/10] ARM: dove: add support for Marvell Dove SoC

[Sebastian Hesselbarth]

This patch adds initial support for the armv7-based Marvell Dove SoC
(88AP510).

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
---
 arch/arm/cpu/armv7/dove/Makefile        |   49 +++++
 arch/arm/cpu/armv7/dove/cpu.c           |  266 ++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/dram.c          |  116 +++++++++++
 arch/arm/cpu/armv7/dove/lowlevel_init.S |   83 ++++++++
 arch/arm/cpu/armv7/dove/mpp.c           |  319 +++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/timer.c         |  176 +++++++++++++++++
 arch/arm/cpu/armv7/dove/usb.c           |  101 ++++++++++
 arch/arm/include/asm/arch-dove/config.h |  153 +++++++++++++++
 arch/arm/include/asm/arch-dove/cpu.h    |  204 ++++++++++++++++++++
 arch/arm/include/asm/arch-dove/dove.h   |   93 +++++++++
 arch/arm/include/asm/arch-dove/gpio.h   |   35 ++++
 arch/arm/include/asm/arch-dove/mpp.h    |  283 +++++++++++++++++++++++++++
 12 files changed, 1878 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/dove/Makefile
 create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
 create mode 100644 arch/arm/cpu/armv7/dove/dram.c
 create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
 create mode 100644 arch/arm/cpu/armv7/dove/timer.c
 create mode 100644 arch/arm/cpu/armv7/dove/usb.c
 create mode 100644 arch/arm/include/asm/arch-dove/config.h
 create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
 create mode 100644 arch/arm/include/asm/arch-dove/dove.h
 create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
 create mode 100644 arch/arm/include/asm/arch-dove/mpp.h

diff --git a/arch/arm/cpu/armv7/dove/Makefile b/arch/arm/cpu/armv7/dove/Makefile
new file mode 100644
index 0000000..127d67e
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/Makefile
@@ -0,0 +1,49 @@
+#
+# Marvell Dove SoC Makefile
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	+= lowlevel_init.o
+COBJS-y := cpu.o dram.o timer.o mpp.o
+COBJS-$(CONFIG_USB_EHCI_MARVELL) += usb.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/dove/cpu.c b/arch/arm/cpu/armv7/dove/cpu.c
new file mode 100644
index 0000000..b9e708c
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/cpu.c
@@ -0,0 +1,266 @@
+/*
+ * Marvell Dove SoC cpu related functions
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <u-boot/md5.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <hush.h>
+
+void reset_cpu(unsigned long ignored)
+{
+	struct dovecpu_registers *cpureg =
+	    (struct dovecpu_registers *)DOVE_CPU_REG_BASE;
+
+	/* Enable soft reset to assert RSTOUTn */
+	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+	       &cpureg->rstoutn_mask);
+	/* Assert soft reset */
+	writel(readl(&cpureg->sys_soft_rst) | 1,
+	       &cpureg->sys_soft_rst);
+	do {} while (1);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int dove_print_cpu(void)
+{
+	char *cpu;
+	u32 idreg;
+	u16 part, rev;
+
+	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(idreg));
+
+	part = (idreg >> ARM_ID_PARTNUM_OFFSET) & ARM_ID_PARTNUM_MASK;
+	rev = (idreg >> ARM_ID_REVISION_OFFSET) & ARM_ID_REVISION_MASK;
+
+	switch (part) {
+	case DOVECPU_PART_SHEEVA:
+		cpu = "Marvell Sheeva";
+		break;
+	default:
+		cpu = "Unknown CPU";
+	}
+
+	printf("CPU:   %s (rev %d)\n", cpu, rev);
+	return 0;
+}
+
+int dove_print_soc(void)
+{
+	char *soc, *rev;
+	u16 devid = (readl(DOVE_REG_PCIE_DEVID) >> 16) & 0xffff;
+	u8 revid = readl(DOVE_REG_PCIE_REVID) & 0xff;
+
+	switch (devid) {
+	case DOVESOC_DEVID_AP510:
+		soc = "AP510";
+		break;
+	case DOVESOC_DEVID_F6781:
+		soc = "F6781";
+		break;
+	default:
+		printf("ERROR.. %s: Unsupported SoC %04x\n", __func__, devid);
+		return -1;
+	}
+
+	switch (revid) {
+	case DOVESOC_REVID_Z0:
+		rev = "Z0";
+		break;
+	case DOVESOC_REVID_Z1:
+		rev = "Z1";
+		break;
+	case DOVESOC_REVID_Y0:
+		rev = "Y0";
+		break;
+	case DOVESOC_REVID_Y1:
+		rev = "Y1";
+		break;
+	case DOVESOC_REVID_X0:
+		rev = "X0";
+		break;
+	case DOVESOC_REVID_A0:
+		rev = "A0";
+		break;
+	case DOVESOC_REVID_A1:
+		rev = "A1";
+		break;
+	default:
+		rev = "Unknown revision";
+	};
+
+	printf("SoC:   Dove 88%s (%s)\n", soc, rev);
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	if (dove_print_soc())
+		return -1;
+	if (dove_print_cpu())
+		return -1;
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*
+ * dove_init_gpio - initial GPIO configuration
+ */
+void dove_init_gpio(struct dove_gpio_init *gpp)
+{
+	struct dovegpio_registers *gpio0reg =
+		(struct dovegpio_registers *)DOVE_GPIO0_BASE;
+	struct dovegpio_registers *gpio1reg =
+		(struct dovegpio_registers *)DOVE_GPIO1_BASE;
+	struct dovegpio_registers *gpio2reg =
+		(struct dovegpio_registers *)DOVE_GPIO2_BASE;
+
+	/* Init GPIOS to default values as per board requirement */
+	writel(gpp->val0, &gpio0reg->dout);
+	writel(gpp->val1, &gpio1reg->dout);
+	writel(gpp->val2, &gpio2reg->dout);
+	writel(gpp->oe0_n, &gpio0reg->oe);
+	writel(gpp->oe1_n, &gpio1reg->oe);
+	writel(gpp->oe2_n, &gpio2reg->oe);
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int dove_winctrl_calcsize(unsigned int sizeval)
+{
+	int i;
+	unsigned int j = 0;
+	u32 val = sizeval >> 1;
+
+	for (i = 0; val >= 0x10000; i++) {
+		j |= (1 << i);
+		val = val >> 1;
+	}
+	return 0x0000ffff & j;
+}
+
+/*
+ * dove_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Dove Soc to addess different
+ * devices. Windows 0-3 can be configured for size, BAR and remap addr.
+ * Windows 4-7 can be configured for size and BAR.
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ */
+int dove_config_adr_windows(void)
+{
+	struct dovewin_registers *winregs =
+		(struct dovewin_registers *)DOVE_CPU_WIN_BASE;
+
+	/* Window 0: 1M PCIE0 IO address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE0,
+	     DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE), &winregs[0].ctrl);
+
+	writel(DOVE_DEFADR_PCIE0_IO, &winregs[0].base);
+	writel(DOVE_DEFADR_PCIE0_IO_REMAP, &winregs[0].remap_lo);
+	writel(0x0, &winregs[0].remap_hi);
+
+	/* Window 1: 1M PCIE1 IO address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE1,
+	     DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE), &winregs[1].ctrl);
+
+	writel(DOVE_DEFADR_PCIE1_IO, &winregs[1].base);
+	writel(DOVE_DEFADR_PCIE1_IO_REMAP, &winregs[1].remap_lo);
+	writel(0x0, &winregs[1].remap_hi);
+
+	/* Window 2: 128M PCIE0 MEM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE0,
+	     DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE), &winregs[2].ctrl);
+
+	writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].base);
+	writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].remap_lo);
+	writel(0x0, &winregs[2].remap_hi);
+
+	/* Window 3: 128M PCIE1 MEM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE1,
+	     DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE), &winregs[3].ctrl);
+
+	writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].base);
+	writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].remap_lo);
+	writel(0x0, &winregs[3].remap_hi);
+
+	/* Window 4: 1M Cryptographic SRAM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_SASRAM,
+	     DOVECPU_ATTR_SASRAM, DOVECPU_WIN_ENABLE), &winregs[4].ctrl);
+	writel(DOVE_DEFADR_SASRAM, &winregs[4].base);
+
+	/* Window 5: 128M Bootrom address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_BOOTROM,
+	     DOVECPU_ATTR_BOOTROM, DOVECPU_WIN_ENABLE), &winregs[5].ctrl);
+	writel(DOVE_DEFADR_BOOTROM, &winregs[5].base);
+
+	/* Window 6: 1M PMU Scratchpad address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PMURAM,
+	     DOVECPU_ATTR_PMURAM, DOVECPU_WIN_ENABLE), &winregs[6].ctrl);
+	writel(DOVE_DEFADR_PMURAM, &winregs[6].base);
+
+	/* Window 7: Disabled */
+	writel(DOVECPU_WIN_DISABLE, &winregs[7].ctrl);
+
+	return 0;
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	dove_config_adr_windows();
+#ifdef CONFIG_USB_EHCI_MARVELL
+	dove_ehci_phy_init(0);
+	dove_ehci_phy_init(1);
+#endif /* CONFIG_USB_EHCI_MARVELL */
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Enable D-cache. I-cache is already enabled in lowlevel_init.S */
+	dcache_enable();
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+#ifdef CONFIG_MVGBE
+int cpu_eth_init(bd_t *bis)
+{
+	mvgbe_initialize(bis);
+	return 0;
+}
+#endif /* CONFIG_MVGBE */
diff --git a/arch/arm/cpu/armv7/dove/dram.c b/arch/arm/cpu/armv7/dove/dram.c
new file mode 100644
index 0000000..f5e8246
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/dram.c
@@ -0,0 +1,116 @@
+/*
+ * Marvell Dove SoC DRAM initialization
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DOVE_REG_DRAM_MAP(x)	(DOVE_REGISTER(0x800100) + (x * 0x10))
+#define DRAM_START_MASK		0xff800000
+#define DRAM_SIZE_MASK		0xf
+#define DRAM_SIZE_SHIFT		16
+
+/*
+ * dove_sdram_start - reads start from Memory Address Map Register n
+ */
+u32 dove_dram_start(enum memory_bank bank)
+{
+	u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
+	u32 enable = 0x01 & reg;
+
+	if ((!enable) || (bank > BANK1))
+		return 0;
+
+	return reg & DRAM_START_MASK;
+}
+
+/*
+ * dove_sdram_size - reads size from Memory Address Map Register n
+ */
+u32 dove_dram_size(enum memory_bank bank)
+{
+	u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
+	u32 enable = 0x01 & reg;
+	u32 size;
+
+	if ((!enable) || (bank > BANK1))
+		return 0;
+
+	/*
+	 * area_length: 7 = 8M, 8 = 16M, ..., 15 = 2048M
+	 * size = 1 << (area_length + 16)
+	 */
+	size = (reg >> DRAM_SIZE_SHIFT) & DRAM_SIZE_MASK;
+	size = 1 << (size + 16);
+	return size;
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = dove_dram_start(i);
+		gd->bd->bi_dram[i].size = dove_dram_size(i);
+
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/armv7/dove/lowlevel_init.S b/arch/arm/cpu/armv7/dove/lowlevel_init.S
new file mode 100644
index 0000000..105d12d
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/lowlevel_init.S
@@ -0,0 +1,83 @@
+/*
+ * Marvell Dove SoC icache and reg base low level init
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/dove.h>
+#include <generated/asm-offsets.h>
+#include <linux/linkage.h>
+
+/*
+ * Enable Tauros2 L2 ICache
+ */
+.macro init_l2cc
+	mrc	15, 0, r0, c1, c0, 1
+	orr	r0, r0, #0x2
+	mcr	15, 0, r0, c1, c0, 1
+.endm /* init_l2cc */
+
+/*
+ * Init internal register base addresses
+ */
+.macro init_reg_base
+	/* set SB reg base to 0xf1000000 */
+	ldr	r1, =(DOVE_PREMAP_INT_REGS_BASE_ADDR)
+	ldr	r6, =DOVE_SB_REGS_PHYS_BASE
+	str	r6, [r1]
+
+	/* set NB reg base to 0xf1800000 */
+	ldr	r1, =(DOVE_CPU_CTRL_REG)
+	ldr	r4, =0xffff0000
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	lsr	r4, r6, #16
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+	/* Set AXI bridge address mapping to 0xf1800000 */
+	ldr	r1, =(DOVE_AXI_CTRL_REG)
+	ldr	r4, =0x007fffff
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+	/* set MC configuration register decode address to 0xf1800000 */
+	ldr	r1, =(DOVE_PREMAP_MC_DECODE_REG)
+	ldr	r4, =0x0000ffff
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+.endm /* init_reg_base */
+
+.section ".text.init", "x"
+
+ENTRY(lowlevel_init)
+	init_l2cc
+	init_reg_base
+
+	/* r12 saved upper lr*/
+	mov pc,lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/dove/mpp.c b/arch/arm/cpu/armv7/dove/mpp.c
new file mode 100644
index 0000000..6722858
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/mpp.c
@@ -0,0 +1,319 @@
+/*
+ * Marvell Dove SoC MPP pinmux
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define MPP_BITS	4
+#define MPP_MASK	0xf
+#define MPPS_PER_REG	8
+
+#define MPP_NUM(_x)	((_x) & 0xff)
+#define MPP_SEL(_x)	(((_x) >> 8) & 0x1f)
+#define MPP_GPIO(_x)	((_x) & (1 << 15))
+
+#define MPP_CTRL(i)			(DOVE_MPP_BASE + (i * MPP_BITS))
+#define MPP_PMU_GENERAL_CTRL		(DOVE_MPP_BASE + 0x010)
+#define  PMUG_AUDIO0_AC97_SEL		(1 << 16)
+#define MPP4_CTRL			(DOVE_MPP_BASE + 0x240)
+#define  MPP4_SDIO0_GPIO_SEL		(1 << 0)
+#define  MPP4_SDIO1_GPIO_SEL		(1 << 1)
+#define  MPP4_CAMERA_GPIO_SEL		(1 << 2)
+#define  MPP4_AUDIO1_GPIO_SEL		(1 << 3)
+#define  MPP4_UART1_GPIO_SEL		(1 << 4)
+#define  MPP4_SPI_GPIO_SEL		(1 << 5)
+#define MPP_GENERAL_CTRL		(DOVE_PDMA_BASE + 0x403c)
+#define  MPPG_NAND_GPIO_SEL		(1 << 0)
+#define  MPPG_AUDIO1_SPDIFO_GPIO_SEL	(1 << 1)
+#define GENERAL_CONFIG_1		(DOVE_PDMA_BASE + 0x002c)
+#define  GENERAL_TWSI_MUXEN_OPTION1	(1 << 7)
+#define GENERAL_CONFIG_2		(DOVE_PDMA_BASE + 0x0030)
+#define  GENERAL_TWSI_OPTION3_SEL	(1 << 22)
+#define  GENERAL_TWSI_MUXEN_OPTION3	(1 << 21)
+#define  GENERAL_TWSI_MUXEN_OPTION2	(1 << 20)
+#define SSP_CONFIG_STATUS_1		(DOVE_PDMA_BASE + 0x0034)
+#define  SSP_SSP_ON_AUDIO1		(1 << 0)
+
+/*
+ * MPP0-23 have standard MPP register layout
+ */
+static void dove_mpp_std_set(u16 config)
+{
+	u8 num = MPP_NUM(config);
+	u32 off = (num / MPPS_PER_REG) * MPP_BITS;
+	u32 shift = (num % MPPS_PER_REG) * MPP_BITS;
+	u32 reg;
+
+	/* configure standard MPP pin */
+	reg  = readl(MPP_CTRL(off));
+	reg &= ~(MPP_MASK << shift);
+	reg |= MPP_SEL(config) << shift;
+	writel(reg, MPP_CTRL(off));
+
+	/* configure gpio capabilities */
+	if (MPP_GPIO(config))
+		orion_gpio_set_valid(num, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+	else
+		orion_gpio_set_valid(num, 0);
+}
+
+/*
+ * MPP0-15 also allow to mux PMU functions
+ */
+static void dove_mpp_pmu_set(u16 config)
+{
+	u8 num = MPP_NUM(config);
+
+	if (MPP_SEL(config) == PMU) {
+		/* enable PMU on MPP */
+		writel(readl(MPP_PMU_GENERAL_CTRL) | (1 << num),
+		       MPP_PMU_GENERAL_CTRL);
+		/* disable gpio capabilities */
+		orion_gpio_set_valid(num, 0);
+	} else {
+		/* disable PMU on MPP */
+		writel(readl(MPP_PMU_GENERAL_CTRL) & ~(1 << num),
+		       MPP_PMU_GENERAL_CTRL);
+		/* configure MPP */
+		dove_mpp_std_set(config);
+	}
+}
+
+/*
+ * MPP groups on MPP4_CTRL have different register layout
+ * and allow GPIO or special function only
+ */
+static void dove_mpp4_set(u16 config)
+{
+	u32 reg = readl(MPP4_CTRL);
+	u32 mask;
+	u8  n, nmin, nmax;
+	int gpio;
+
+	switch (MPP_NUM(config)) {
+	case MPP_CAMERA:
+		mask = MPP4_CAMERA_GPIO_SEL;
+		nmin = MPP_CAMERA;
+		nmax = MPP_CAMERA_MAX;
+		break;
+	case MPP_SDIO0:
+		mask = MPP4_SDIO0_GPIO_SEL;
+		nmin = MPP_SDIO0;
+		nmax = MPP_SDIO0_MAX;
+		break;
+	case MPP_SDIO1:
+		mask = MPP4_SDIO1_GPIO_SEL;
+		nmin = MPP_SDIO1;
+		nmax = MPP_SDIO1_MAX;
+		break;
+	case MPP_SPI:
+		mask = MPP4_SPI_GPIO_SEL;
+		nmin = MPP_SPI;
+		nmax = MPP_SPI_MAX;
+		break;
+	case MPP_UART1:
+		mask = MPP4_UART1_GPIO_SEL;
+		nmin = MPP_UART1;
+		nmax = MPP_UART1_MAX;
+		break;
+	default:
+		return;
+	}
+
+	reg &= ~mask;
+	if (MPP_SEL(config))
+		reg |= mask;
+	writel(reg, MPP4_CTRL);
+
+	/* configure gpio capabilities */
+	gpio = 0;
+	if (MPP_GPIO(config))
+		gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+	for (n = nmin; n <= nmax; n++)
+		orion_gpio_set_valid(n, gpio);
+}
+
+/*
+ * MPP_GENERAL_CTRL allows GPIO on NAND pins
+ */
+static void dove_mpp_nand_set(u16 config)
+{
+	u32 reg = readl(MPP_GENERAL_CTRL);
+	u8 n;
+	int gpio;
+
+	reg &= ~MPPG_NAND_GPIO_SEL;
+	if (config == MPP_NAND_GPO)
+		reg |= MPPG_NAND_GPIO_SEL;
+	writel(reg, MPP_GENERAL_CTRL);
+
+	/* configure gpio capabilities */
+	gpio = (config == MPP_NAND_GPO) ? GPIO_OUTPUT_OK : 0;
+	for (n = MPP_NAND; n <= MPP_NAND_MAX; n++)
+		orion_gpio_set_valid(n, gpio);
+}
+
+/*
+ * Dedicated audio1 pins can carry i2s, spdif, ssp or twsi
+ * and gpio in various combinations
+ */
+#define AUDIO1_TWSI	(1 << 0)
+#define AUDIO1_SPDIFO	(1 << 1)
+#define AUDIO1_SSP	(1 << 2)
+#define AUDIO1_GPIO	(1 << 3)
+
+static void dove_mpp_audio1_set(u16 config)
+{
+	u32 mpp4  = readl(MPP4_CTRL);
+	u32 sspc1 = readl(SSP_CONFIG_STATUS_1);
+	u32 gmpp  = readl(MPP_GENERAL_CTRL);
+	u32 gcfg2 = readl(GENERAL_CONFIG_2);
+	u8 n, sel = MPP_SEL(config);
+	int gpio;
+
+	gcfg2 &= ~GENERAL_TWSI_OPTION3_SEL;
+	gmpp &= ~MPPG_AUDIO1_SPDIFO_GPIO_SEL;
+	sspc1 &= ~SSP_SSP_ON_AUDIO1;
+	mpp4 &= ~MPP4_AUDIO1_GPIO_SEL;
+	if (sel & AUDIO1_TWSI)
+		gcfg2 |= GENERAL_TWSI_OPTION3_SEL;
+	if (sel & AUDIO1_SPDIFO)
+		gmpp |= MPPG_AUDIO1_SPDIFO_GPIO_SEL;
+	if (sel & AUDIO1_SSP)
+		sspc1 |= SSP_SSP_ON_AUDIO1;
+	if (sel & AUDIO1_GPIO)
+		mpp4 |= MPP4_AUDIO1_GPIO_SEL;
+
+	writel(mpp4, MPP4_CTRL);
+	writel(sspc1, SSP_CONFIG_STATUS_1);
+	writel(gmpp, MPP_GENERAL_CTRL);
+	writel(gcfg2, GENERAL_CONFIG_2);
+
+	/* configure gpio capabilities */
+	/* gpio allows gpio on all audio1 mpp pins */
+	gpio = 0;
+	if (config == MPP_AUDIO1_GPIO)
+		gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+
+	for (n = MPP_AUDIO1; n <= MPP_AUDIO1_MAX; n++)
+		orion_gpio_set_valid(n, gpio);
+
+	switch (config) {
+	/* spdifo and twsi allow gpio on mpp[52:55] */
+	case MPP_AUDIO1_SPDIFO:
+	case MPP_AUDIO1_TWSI:
+		orion_gpio_set_valid(52, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(53, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(54, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(55, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		break;
+	/* i2s and ssp allow gpio on mpp[56:57] */
+	case MPP_AUDIO1_I2S:
+	case MPP_AUDIO1_SSP:
+		orion_gpio_set_valid(56, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(57, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		break;
+	}
+}
+
+/*
+ * MPP PMU switches audio0 pins to ac97 or i2s0
+ */
+static void dove_mpp_audio0_set(u16 config)
+{
+	/* switch i2s or ac97 to audio0 */
+	u32 reg = readl(MPP_PMU_GENERAL_CTRL);
+
+	reg &= ~PMUG_AUDIO0_AC97_SEL;
+	if (config == MPP_AUDIO0_AC97)
+		reg |= PMUG_AUDIO0_AC97_SEL;
+	writel(reg, MPP_PMU_GENERAL_CTRL);
+}
+
+/*
+ * TWSI has 3 optional pin sets that can be switched during runtime
+ */
+static void dove_mpp_twsi_set(u16 config)
+{
+	u32 gcfg1 = readl(GENERAL_CONFIG_1);
+	u32 gcfg2 = readl(GENERAL_CONFIG_2);
+
+	gcfg1 &= ~GENERAL_TWSI_MUXEN_OPTION1;
+	gcfg2 &= ~(GENERAL_TWSI_MUXEN_OPTION2 | GENERAL_TWSI_MUXEN_OPTION3);
+
+	switch (config) {
+	case MPP_TWSI_OPTION1:
+		gcfg1 |= GENERAL_TWSI_MUXEN_OPTION1;
+		break;
+	case MPP_TWSI_OPTION2:
+		gcfg2 |= GENERAL_TWSI_MUXEN_OPTION2;
+		break;
+	case MPP_TWSI_OPTION3:
+		gcfg2 |= GENERAL_TWSI_MUXEN_OPTION3;
+		break;
+	}
+
+	writel(gcfg1, GENERAL_CONFIG_1);
+	writel(gcfg2, GENERAL_CONFIG_2);
+}
+
+void dove_mpp_conf(u16 *mpp_list)
+{
+	while (*mpp_list) {
+		u8 num = MPP_NUM(*mpp_list);
+
+		if (num <= MPP_PMU_MAX)
+			dove_mpp_pmu_set(*mpp_list);
+		else if (num <= MPP_STD_MAX)
+			dove_mpp_std_set(*mpp_list);
+		else {
+			switch (num) {
+			case MPP_CAMERA:
+			case MPP_SDIO0:
+			case MPP_SDIO1:
+			case MPP_SPI:
+			case MPP_UART1:
+				dove_mpp4_set(*mpp_list);
+				break;
+			case MPP_NAND:
+				dove_mpp_nand_set(*mpp_list);
+				break;
+			case MPP_AUDIO0:
+				dove_mpp_audio0_set(*mpp_list);
+				break;
+			case MPP_AUDIO1:
+				dove_mpp_audio1_set(*mpp_list);
+				break;
+			case MPP_TWSI:
+				dove_mpp_twsi_set(*mpp_list);
+				break;
+			}
+		}
+		mpp_list++;
+	}
+}
diff --git a/arch/arm/cpu/armv7/dove/timer.c b/arch/arm/cpu/armv7/dove/timer.c
new file mode 100644
index 0000000..3be9b78
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/timer.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Dove SoC timer
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dove.h>
+
+#define UBOOT_CNTR	0	/* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct dovetmr_val {
+	u32 reload;	/* Timer reload reg */
+	u32 val;	/* Timer value reg */
+};
+
+/* Timer registers */
+struct dovetmr_registers {
+	u32 ctrl;	/* Timer control reg */
+	u32 pad[3];
+	struct dovetmr_val tmr[2];
+	u32 wdt_reload;
+	u32 wdt_val;
+};
+
+struct dovetmr_registers *dovetmr_regs =
+	(struct dovetmr_registers *)DOVE_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG			&dovetmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum)	&dovetmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum)		&dovetmr_regs->tmr[tmrnum].val
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS		0
+#define TRG_ARM_TIMER_REL_MASK		0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS		0
+#define TVR_ARM_TIMER_MASK		0xffffffff
+#define TVR_ARM_TIMER_MAX		0xffffffff
+#define TIMER_LOAD_VAL			0xffffffff
+
+#define READ_TIMER			(readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
+					 (CONFIG_SYS_TCLK / 1000))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER;
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec +
+			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	uint current;
+	ulong delayticks;
+
+	current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
+	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+	if (current < delayticks) {
+		delayticks -= current;
+		do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current);
+		do {} while ((TIMER_LOAD_VAL - delayticks) <
+			     readl(CNTMR_VAL_REG(UBOOT_CNTR)));
+	} else {
+		do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
+			     (current - delayticks));
+	}
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+	unsigned int cntmrctrl;
+
+	/* load value into timer */
+	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+	/* enable timer in auto reload mode */
+	cntmrctrl = readl(CNTMR_CTRL_REG);
+	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+	writel(cntmrctrl, CNTMR_CTRL_REG);
+
+	/* init the timestamp and lastdec value */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/armv7/dove/usb.c b/arch/arm/cpu/armv7/dove/usb.c
new file mode 100644
index 0000000..1b932db
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/usb.c
@@ -0,0 +1,101 @@
+/*
+ * Marvell Dove SoC USB PHY init
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+
+/* Dove USB2.0 PHY registers */
+#define USB20_POWER_CTRL		((base) + 0x400)
+#define USB20_PHY_PLL_CTRL		((base) + 0x410)
+#define  PHY_PLL_VCO_RECALIBRATE	(1 << 21)
+#define USB20_PHY_TX_CTRL		((base) + 0x420)
+#define  PHY_TX_HS_STRESS_CTRL		(1 << 31)
+#define  PHY_TX_BLOCK_EN		(1 << 21)
+#define  PHY_TX_IMP_CAL_VTH(x)		(x << 14)
+#define  PHY_TX_IMP_CAL_VTH_MASK	PHY_TX_IMP_CAL_VTH(0x7)
+#define  PHY_TX_RCAL_START		(1 << 12)
+#define  PHY_TX_LOWVDD_EN		(1 << 11)
+#define USB20_PHY_RX_CTRL		((base) + 0x430)
+#define  PHY_RX_EDGE_DET(x)		(x << 26)
+#define  PHY_RX_EDGE_DET_MASK		PHY_RX_EDGE_DET(0x3)
+#define  PHY_RX_CDR_FASTLOCK_EN		(1 << 21)
+#define  PHY_RX_SQ_LENGTH(x)		(x << 15)
+#define  PHY_RX_SQ_LENGTH_MASK		PHY_RX_SQ_LENGTH(0x3)
+#define  PHY_RX_SQ_THRESH(x)		(x << 4)
+#define  PHY_RX_SQ_THRESH_MASK		PHY_RX_SQ_THRESH(0xf)
+#define  PHY_RX_LPF_COEFF(x)		(x << 2)
+#define  PHY_RX_LPF_COEFF_MASK		PHY_RX_LPF_COEFF(0x3)
+#define USB20_PHY_IVREF_CTRL		((base) + 0x440)
+#define  PHY_IVREF_TXVDD12(x)		(x << 8)
+#define  PHY_IVREF_TXVDD12_MASK		PHY_IVREF_TXVDD12(0x3)
+#define USB20_PHY_TESTGRP_CTRL		((base) + 0x450)
+#define  PHY_TESTGRP_SQ_RST		(1 << 15)
+
+void dove_ehci_phy_init(int port)
+{
+	u32 base = (port == 0) ? DOVE_USB20_0_BASE : DOVE_USB20_1_BASE;
+	u32 reg;
+
+	/* USB PHY PLL control */
+	reg = readl(USB20_PHY_PLL_CTRL);
+	writel(reg | PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
+	udelay(100);
+	writel(reg & ~PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
+
+	/* USB PHY Tx control */
+	reg = readl(USB20_PHY_TX_CTRL);
+	reg &= ~PHY_TX_IMP_CAL_VTH_MASK;
+	reg |= PHY_TX_IMP_CAL_VTH(0x5);
+	reg |= PHY_TX_LOWVDD_EN;
+	reg |= PHY_TX_RCAL_START;
+	reg |= PHY_TX_BLOCK_EN;
+	reg |= PHY_TX_HS_STRESS_CTRL;
+	writel(reg, USB20_PHY_TX_CTRL);
+	udelay(100);
+	writel(reg & ~PHY_TX_RCAL_START, USB20_PHY_TX_CTRL);
+
+	/* USB PHY RX control */
+	reg = readl(USB20_PHY_RX_CTRL);
+	reg &= ~(PHY_RX_LPF_COEFF_MASK | PHY_RX_SQ_THRESH_MASK |
+		 PHY_RX_SQ_LENGTH_MASK | PHY_RX_EDGE_DET_MASK);
+	reg |= PHY_RX_LPF_COEFF(0x1);
+	reg |= PHY_RX_SQ_THRESH(0xc);
+	reg |= PHY_RX_SQ_LENGTH(0x1);
+	reg |= PHY_RX_EDGE_DET(0x0);
+	reg &= ~PHY_RX_CDR_FASTLOCK_EN;
+	writel(reg, USB20_PHY_RX_CTRL);
+
+	/* USB PHY IVREF control */
+	reg = readl(USB20_PHY_IVREF_CTRL);
+	reg &= ~PHY_IVREF_TXVDD12_MASK;
+	reg |= PHY_IVREF_TXVDD12(0x3);
+	writel(reg, USB20_PHY_IVREF_CTRL);
+
+	/* USB PHY TEST GROUP control */
+	reg = readl(USB20_PHY_TESTGRP_CTRL);
+	reg &= ~PHY_TESTGRP_SQ_RST;
+	writel(reg, USB20_PHY_TESTGRP_CTRL);
+}
diff --git a/arch/arm/include/asm/arch-dove/config.h b/arch/arm/include/asm/arch-dove/config.h
new file mode 100644
index 0000000..2d94a48
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/config.h
@@ -0,0 +1,153 @@
+/*
+ * Marvell SoC config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_CONFIG_H
+#define _DOVE_CONFIG_H
+
+#include <asm/arch/dove.h>
+
+#define CONFIG_ARMV7			/* Basic Architecture */
+#define CONFIG_DOVE			/* SOC Family Name */
+#define CONFIG_SHEEVA_88SV581		/* CPU Core subversion */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+				/* default Dcache Line length for Dove */
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#define CONFIG_SYS_DCACHE_OFF		/* Disable DCache by default */
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Dove has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#define CONFIG_I2C_MVTWSI_BASE	DOVE_TWSI_BASE
+#define MV_UART_CONSOLE_BASE	DOVE_UART0_BASE
+#define MV_SATA_BASE		DOVE_SATA_BASE
+#define MV_SATA_PORT0_OFFSET	DOVE_SATA_PORT0_OFFSET
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD		1
+#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL		1
+#endif
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI			1
+#define CONFIG_ORION_SPI		1
+#define ORION_SPI_BASE			DOVE_SPI_BASE
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS		0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS		0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ		25000000
+#endif
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_PHYLIB
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SDHCI
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_SDHCI
+#define CONFIG_DOVE_SDHCI	/* Enable Dove SDHCI controller driver */
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS
+#define CONFIG_SYS_MMC_MAX_DEVICE	2
+#endif
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * IDE Support on SATA ports
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#ifndef CONFIG_SOFT_I2C
+#define CONFIG_I2C_MVTWSI
+#endif
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#endif /* _DOVE_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-dove/cpu.h b/arch/arm/include/asm/arch-dove/cpu.h
new file mode 100644
index 0000000..718dd59
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/cpu.h
@@ -0,0 +1,204 @@
+/*
+ * Marvell Dove SoC CPU
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVECPU_H
+#define _DOVECPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define DOVECPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+			| (attr << 8) | (dove_winctrl_calcsize(size) << 16))
+
+#define DOVEGBE_PORT_SERIAL_CONTROL1_REG	(DOVE_EGIGA_BASE + 0x44c)
+#define DOVE_REG_PCIE_DEVID			(DOVE_REG_PCIE0_BASE + 0x00)
+#define DOVE_REG_PCIE_REVID			(DOVE_REG_PCIE0_BASE + 0x08)
+#define DOVE_REG_SYSRST_CNT			(DOVE_MPP_BASE + 0x50)
+#define SYSRST_CNT_1SEC_VAL			(25*1000000)
+#define DOVE_REG_MPP_OUT_DRV_REG		(DOVE_MPP_BASE + 0xE0)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+};
+
+enum dovecpu_winen {
+	DOVECPU_WIN_DISABLE,
+	DOVECPU_WIN_ENABLE
+};
+
+enum dovecpu_target {
+	DOVECPU_TARGET_DRAM = 0x0,
+	DOVECPU_TARGET_SASRAM = 0x3,
+	DOVECPU_TARGET_NAND = 0xc,
+	DOVECPU_TARGET_PMURAM = 0xd,
+	DOVECPU_TARGET_PCIE0 = 0x4,
+	DOVECPU_TARGET_PCIE1 = 0x8,
+	DOVECPU_TARGET_SPI = 0x1,
+	DOVECPU_TARGET_BOOTROM = 0x1,
+};
+
+enum dovecpu_attrib {
+	DOVECPU_ATTR_DRAM = 0x00,
+	DOVECPU_ATTR_SASRAM = 0x00,
+	DOVECPU_ATTR_NAND = 0x00,
+	DOVECPU_ATTR_PMURAM = 0x00,
+	DOVECPU_ATTR_PCIE_IO = 0xe0,
+	DOVECPU_ATTR_PCIE_MEM = 0xe8,
+	DOVECPU_ATTR_SPI0 = 0xfe,
+	DOVECPU_ATTR_SPI1 = 0xfb,
+	DOVECPU_ATTR_BOOTROM = 0xfd,
+};
+
+enum dovecpu_part {
+	DOVECPU_PART_SHEEVA = 0x581,
+};
+
+enum dovesoc_devid {
+	DOVESOC_DEVID_F6781 = 0x6781,
+	DOVESOC_DEVID_AP510 = 0x0510,
+};
+
+enum dovesoc_revid {
+	DOVESOC_REVID_Z0 = 0,
+	DOVESOC_REVID_Z1 = 1,
+	DOVESOC_REVID_Y0 = 2,
+	DOVESOC_REVID_Y1 = 3,
+	DOVESOC_REVID_X0 = 4,
+	DOVESOC_REVID_A0 = 6,
+	DOVESOC_REVID_A1 = 7,
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define DOVE_DEFADR_PCIE0_MEM		0xe0000000
+#define DOVE_DEFADR_PCIE0_IO		0xf2000000
+#define DOVE_DEFADR_PCIE0_IO_REMAP	0x00000000
+#define DOVE_DEFADR_PCIE1_MEM		0xe8000000
+#define DOVE_DEFADR_PCIE1_IO		0xf2100000
+#define DOVE_DEFADR_PCIE1_IO_REMAP	0x00100000
+#define DOVE_DEFADR_SASRAM		0xc8000000
+#define DOVE_DEFADR_BOOTROM		0xf8000000
+#define DOVE_DEFADR_PMURAM		0xf0000000
+
+/*
+ * ARM CPUID register
+ */
+#define ARM_ID_REVISION_OFFSET	0
+#define ARM_ID_REVISION_MASK	0xf
+#define ARM_ID_PARTNUM_OFFSET	4
+#define ARM_ID_PARTNUM_MASK	0xfff
+#define ARM_ID_ARCH_OFFSET	16
+#define ARM_ID_ARCH_MASK	0xf
+#define ARM_ID_VAR_OFFSET	20
+#define ARM_ID_VAR_MASK		0xf
+#define ARM_ID_ASCII_OFFSET	24
+#define ARM_ID_ASCII_MASK	0xff
+
+/*
+ * read feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+	unsigned int val;
+	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
+			(val) : : "cc");
+	return val;
+}
+
+/*
+ * write feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
+			(val) : "cc");
+	isb();
+}
+
+/*
+ * Downstream Bridge Registers
+ */
+struct dovewin_registers {
+	u32 ctrl;
+	u32 base;
+	u32 remap_lo;
+	u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ */
+struct dovecpu_registers {
+	u32 config;		/* 0x20100 */
+	u32 ctrl_stat;		/* 0x20104 */
+	u32 rstoutn_mask;	/* 0x20108 */
+	u32 sys_soft_rst;	/* 0x2010C */
+	u32 bridge_cause_irq;	/* 0x20110 */
+	u32 bridge_mask_irq;	/* 0x20114 */
+	u32 pad1;
+	u32 pmu_ctrl;		/* 0x2011c */
+};
+
+/*
+ * GPIO 0/1 Registers
+ * GPIO 2 Registers (no datain/irq)
+ */
+struct dovegpio_registers {
+	u32 dout;
+	u32 oe;
+	u32 blink_en;
+	u32 din_pol;
+	u32 din;
+	u32 irq_cause;
+	u32 irq_mask;
+	u32 irq_level;
+};
+
+struct dove_gpio_init {
+	u32 val0;
+	u32 val1;
+	u32 val2;
+	u32 oe0_n;
+	u32 oe1_n;
+	u32 oe2_n;
+};
+
+/*
+ * functions
+ */
+void reset_cpu(unsigned long ignored);
+unsigned char get_random_hex(void);
+u32 dove_dram_start(enum memory_bank bank);
+u32 dove_dram_size(enum memory_bank bank);
+int dove_config_adr_windows(void);
+void dove_init_gpio(struct dove_gpio_init *);
+unsigned int dove_winctrl_calcsize(unsigned int sizeval);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _DOVECPU_H */
diff --git a/arch/arm/include/asm/arch-dove/dove.h b/arch/arm/include/asm/arch-dove/dove.h
new file mode 100644
index 0000000..da5011b
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/dove.h
@@ -0,0 +1,93 @@
+/*
+ * Marvell Dove SoC register offsets and config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_H
+#define _DOVE_H
+
+/* Dove TCLK is fixed to 166MHz */
+#define CONFIG_SYS_TCLK			166666667
+
+/* SOC specific definitions */
+#define DOVE_PREMAP_REGS_PHYS_BASE	0xd0000000
+#define DOVE_PREMAP_INT_REGS_BASE_ADDR  (DOVE_PREMAP_REGS_PHYS_BASE + 0x20080)
+#define DOVE_PREMAP_MC_DECODE_REG       (DOVE_PREMAP_REGS_PHYS_BASE + 0x800010)
+
+#define DOVE_SB_REGS_PHYS_BASE		0xf1000000
+#define DOVE_NB_REGS_PHYS_BASE		0xf1800000
+#define DOVE_REGISTER(x)		(DOVE_SB_REGS_PHYS_BASE + x)
+
+#define DOVE_AXI_CTRL_REG		(DOVE_REGISTER(0xd0224))
+#define DOVE_CPU_CTRL_REG		(DOVE_REGISTER(0xd025c))
+#define DOVE_MC_CTRL_REG		(DOVE_REGISTER(0xd0260))
+#define DOVE_MC_DECODE_REG		(DOVE_REGISTER(0x800010))
+
+#define DOVE_SPI_BASE			(DOVE_REGISTER(0x10600))
+#define DOVE_TWSI_BASE			(DOVE_REGISTER(0x11000))
+#define DOVE_UART0_BASE			(DOVE_REGISTER(0x12000))
+#define DOVE_UART1_BASE			(DOVE_REGISTER(0x12100))
+#define DOVE_UART2_BASE			(DOVE_REGISTER(0x12200))
+#define DOVE_UART3_BASE			(DOVE_REGISTER(0x12300))
+#define DOVE_CPU_WIN_BASE		(DOVE_REGISTER(0x20000))
+#define DOVE_CPU_REG_BASE		(DOVE_REGISTER(0x20100))
+#define DOVE_TIMER_BASE			(DOVE_REGISTER(0x20300))
+#define DOVE_REG_PCIE0_BASE		(DOVE_REGISTER(0x40000))
+#define DOVE_REG_PCIE1_BASE		(DOVE_REGISTER(0x80000))
+#define DOVE_USB20_0_BASE		(DOVE_REGISTER(0x50000))
+#define DOVE_USB20_1_BASE		(DOVE_REGISTER(0x51000))
+#define DOVE_EGIGA_BASE			(DOVE_REGISTER(0x72000))
+#define DOVE_SDIO1_BASE			(DOVE_REGISTER(0x90000))
+#define DOVE_SDIO0_BASE			(DOVE_REGISTER(0x92000))
+#define DOVE_CAMERA_BASE		(DOVE_REGISTER(0x94000))
+#define DOVE_SATA_BASE			(DOVE_REGISTER(0xa0000))
+#define DOVE_NANDF_BASE			(DOVE_REGISTER(0xc0000))
+#define DOVE_PMU_BASE			(DOVE_REGISTER(0xd0000))
+#define DOVE_MPP_BASE			(DOVE_REGISTER(0xd0200))
+#define DOVE_GPIO0_BASE			(DOVE_REGISTER(0xd0400))
+#define DOVE_GPIO1_BASE			(DOVE_REGISTER(0xd0420))
+#define DOVE_RTC_BASE			(DOVE_REGISTER(0xd8500))
+#define DOVE_AC97_BASE			(DOVE_REGISTER(0xe0000))
+#define DOVE_PDMA_BASE			(DOVE_REGISTER(0xe4000))
+#define DOVE_GPIO2_BASE			(DOVE_REGISTER(0xe8400))
+#define DOVE_SSP_BASE			(DOVE_REGISTER(0xec000))
+
+/* Dove Sata controller has one port */
+#define DOVE_SATA_PORT0_OFFSET		0x2000
+
+/* Dove GbE controller has one port */
+#define MAX_MVGBE_DEVS			1
+#define MVGBE0_BASE			DOVE_EGIGA_BASE
+
+/* Dove USB Host controller */
+#define MVUSB0_BASE			DOVE_USB20_0_BASE
+#define MVUSB0_CPU_ATTR_DRAM_CS0	DOVECPU_ATTR_DRAM
+#define MVUSB0_CPU_ATTR_DRAM_CS1	DOVECPU_ATTR_DRAM
+#define MVUSB0_CPU_ATTR_DRAM_CS2	DOVECPU_WIN_DISABLE
+#define MVUSB0_CPU_ATTR_DRAM_CS3	DOVECPU_WIN_DISABLE
+
+/* Dove CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA		DOVECPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE		DOVECPU_WIN_ENABLE
+#define MVCPU_WIN_DISABLE		DOVECPU_WIN_DISABLE
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/gpio.h b/arch/arm/include/asm/arch-dove/gpio.h
new file mode 100644
index 0000000..71bef8e
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Marvell Dove SoC gpio
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __DOVE_GPIO_H
+#define __DOVE_GPIO_H
+
+#include <orion_gpio.h>
+
+#define GPIO_MAX		70
+#define GPIO_BASE(pin)		(((pin) >= 64) ? DOVE_GPIO2_BASE : \
+				 ((pin) >= 32) ? DOVE_GPIO1_BASE : \
+				 DOVE_GPIO0_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/mpp.h b/arch/arm/include/asm/arch-dove/mpp.h
new file mode 100644
index 0000000..1279ac2
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/mpp.h
@@ -0,0 +1,283 @@
+/*
+ * Marvell Dove SoC pinmux
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_MPP_H
+#define _DOVE_MPP_H
+
+#define DOVE_GPI	(1 << 0)
+#define DOVE_GPO	(1 << 1)
+#define DOVE_GPIO	(DOVE_GPO | DOVE_GPI)
+
+#define MPP(_num, _sel, _gpio) (			 \
+	/* MPP number */	((_num) & 0xff) |	 \
+	/* MPP select value */	(((_sel) & 0x1f) << 8) | \
+	/* is gpio config */	((!!(_gpio)) << 15))
+
+/* MPP0-15 allow PMU function */
+#define MPP_PMU_MAX		15
+#define PMU			(0x10)
+/* MPP0-23 have standard mpp register layout */
+#define MPP_STD_MAX		23
+
+#define MPP0			0
+#define MPP0_GPIO		MPP(0, 0x0, 1)
+#define MPP0_UART2_RTS		MPP(0, 0x2, 0)
+#define MPP0_SDIO0_CD		MPP(0, 0x3, 0)
+#define MPP0_LCD0_PWM		MPP(0, 0xf, 0)
+#define MPP0_PMU		MPP(0, PMU, 0)
+
+#define MPP1			1
+#define MPP1_GPIO		MPP(1, 0x0, 1)
+#define MPP1_UART2_CTS		MPP(1, 0x2, 0)
+#define MPP1_SDIO0_WP		MPP(1, 0x3, 0)
+#define MPP1_LCD1_PWM		MPP(1, 0xf, 0)
+#define MPP1_PMU		MPP(1, PMU, 0)
+
+#define MPP2			2
+#define MPP2_GPIO		MPP(2, 0x0, 1)
+#define MPP2_SATA_PRSNT		MPP(2, 0x1, 0)
+#define MPP2_UART2_TXD		MPP(2, 0x2, 0)
+#define MPP2_SDIO0_BUSPWR	MPP(2, 0x3, 0)
+#define MPP2_UART1_RTS		MPP(2, 0x4, 0)
+#define MPP2_PMU		MPP(2, PMU, 0)
+
+#define MPP3			3
+#define MPP3_GPIO		MPP(3, 0x0, 1)
+#define MPP3_SATA_ACT		MPP(3, 0x1, 0)
+#define MPP3_UART2_RXD		MPP(3, 0x2, 0)
+#define MPP3_SDIO0_LEDCTRL	MPP(3, 0x3, 0)
+#define MPP3_UART1_CTS		MPP(3, 0x4, 0)
+#define MPP3_LCD_SPI_CS1	MPP(3, 0xf, 0)
+#define MPP3_PMU		MPP(3, PMU, 0)
+
+#define MPP4			4
+#define MPP4_GPIO		MPP(4, 0x0, 1)
+#define MPP4_UART3_RTS		MPP(4, 0x2, 0)
+#define MPP4_SDIO1_CD		MPP(4, 0x3, 0)
+#define MPP4_SPI1_MISO		MPP(4, 0x4, 0)
+#define MPP4_PMU		MPP(4, PMU, 0)
+
+#define MPP5			5
+#define MPP5_GPIO		MPP(5, 0x0, 1)
+#define MPP5_UART3_CTS		MPP(5, 0x2, 0)
+#define MPP5_SDIO1_WP		MPP(5, 0x3, 0)
+#define MPP5_SPI1_CS		MPP(5, 0x4, 0)
+#define MPP5_PMU		MPP(5, PMU, 0)
+
+#define MPP6			6
+#define MPP6_GPIO		MPP(6, 0x0, 1)
+#define MPP6_UART3_TXD		MPP(6, 0x2, 0)
+#define MPP6_SDIO1_BUSPWR	MPP(6, 0x3, 0)
+#define MPP6_SPI1_MOSI		MPP(6, 0x4, 0)
+#define MPP6_PMU		MPP(6, PMU, 0)
+
+#define MPP7			7
+#define MPP7_GPIO		MPP(7, 0x0, 1)
+#define MPP7_UART3_RXD		MPP(7, 0x2, 0)
+#define MPP7_SDIO1_LEDCTRL	MPP(7, 0x3, 0)
+#define MPP7_SPI1_SCK		MPP(7, 0x4, 0)
+#define MPP7_PMU		MPP(7, PMU, 0)
+
+#define MPP8			8
+#define MPP8_GPIO		MPP(8, 0x0, 1)
+#define MPP8_WATCHDOG_RSTOUT	MPP(8, 0x1, 0)
+#define MPP8_PMU		MPP(8, PMU, 0)
+
+#define MPP9			9
+#define MPP9_GPIO		MPP(9, 0x0, 1)
+#define MPP9_PEX1_CLKREQ	MPP(9, 0x5, 0)
+#define MPP9_PMU		MPP(9, PMU, 0)
+
+#define MPP10			10
+#define MPP10_GPIO		MPP(10, 0x0, 1)
+#define MPP10_SSP_SCLK		MPP(10, 0x5, 0)
+#define MPP10_PMU		MPP(10, PMU, 0)
+
+#define MPP11			11
+#define MPP11_GPIO		MPP(11, 0x0, 1)
+#define MPP11_SATA_PRSNT	MPP(11, 0x1, 0)
+#define MPP11_SATA_ACT		MPP(11, 0x2, 0)
+#define MPP11_SDIO0_LEDCTRL	MPP(11, 0x3, 0)
+#define MPP11_SDIO1_LEDCTRL	MPP(11, 0x4, 0)
+#define MPP11_PEX0_CLKREQ	MPP(11, 0x5, 0)
+#define MPP11_PMU		MPP(11, PMU, 0)
+
+#define MPP12			12
+#define MPP12_GPIO		MPP(12, 0x0, 1)
+#define MPP12_SATA_ACT		MPP(12, 0x1, 0)
+#define MPP12_UART2_RTS		MPP(12, 0x2, 0)
+#define MPP12_AUDIO0_EXTCLK	MPP(12, 0x3, 0)
+#define MPP12_SDIO1_CD		MPP(12, 0x4, 0)
+#define MPP12_PMU		MPP(12, PMU, 0)
+
+#define MPP13			13
+#define MPP13_GPIO		MPP(13, 0x0, 1)
+#define MPP13_UART2_CTS		MPP(13, 0x2, 0)
+#define MPP13_AUDIO1_EXTCLK	MPP(13, 0x3, 0)
+#define MPP13_SDIO1_WP		MPP(13, 0x4, 0)
+#define MPP13_SSP_EXTCLK	MPP(13, 0x5, 0)
+#define MPP13_PMU		MPP(13, PMU, 0)
+
+#define MPP14			14
+#define MPP14_GPIO		MPP(14, 0x0, 1)
+#define MPP14_UART2_TXD		MPP(14, 0x2, 0)
+#define MPP14_SDIO1_BUSPWR	MPP(14, 0x4, 0)
+#define MPP14_SSP_TXD		MPP(14, 0x5, 0)
+#define MPP14_PMU		MPP(14, PMU, 0)
+
+#define MPP15			15
+#define MPP15_GPIO		MPP(15, 0x0, 1)
+#define MPP15_UART2_RXD		MPP(15, 0x2, 0)
+#define MPP15_SDIO1_LEDCTRL	MPP(15, 0x4, 0)
+#define MPP15_SSP_SFRM		MPP(15, 0x5, 0)
+#define MPP15_PMU		MPP(15, PMU, 0)
+
+#define MPP16			16
+#define MPP16_GPIO		MPP(16, 0x0, 1)
+#define MPP16_UART3_RTS		MPP(16, 0x2, 0)
+#define MPP16_SDIO0_CD		MPP(16, 0x3, 0)
+#define MPP16_LCD_SPI_CS1	MPP(16, 0x4, 0)
+#define MPP16_AC97_SDI1		MPP(16, 0x5, 0)
+
+#define MPP17			17
+#define MPP17_GPIO		MPP(17, 0x0, 1)
+#define MPP17_AC97_SYSCLKO	MPP(17, 0x1, 0)
+#define MPP17_UART3_CTS		MPP(17, 0x2, 0)
+#define MPP17_SDIO0_WP		MPP(17, 0x3, 0)
+#define MPP17_TWSI_SDA		MPP(17, 0x4, 0)
+#define MPP17_AC97_SDI2		MPP(17, 0x5, 0)
+
+#define MPP18			18
+#define MPP18_GPIO		MPP(18, 0x0, 1)
+#define MPP18_UART3_TXD		MPP(18, 0x2, 0)
+#define MPP18_SDIO0_BUSPWR	MPP(18, 0x3, 0)
+#define MPP18_LCD0_PWM		MPP(18, 0x4, 0)
+#define MPP18_AC97_SDI3		MPP(18, 0x5, 0)
+
+#define MPP19			19
+#define MPP19_GPIO		MPP(19, 0x0, 1)
+#define MPP19_UART3_RXD		MPP(19, 0x2, 0)
+#define MPP19_SDIO0_LEDCTRL	MPP(19, 0x3, 0)
+#define MPP19_TWSI_SCK		MPP(19, 0x4, 0)
+
+#define MPP20			20
+#define MPP20_GPIO		MPP(20, 0x0, 1)
+#define MPP20_AC97_SYSCLKO	MPP(20, 0x1, 0)
+#define MPP20_LCD_SPI_MISO	MPP(20, 0x2, 0)
+#define MPP20_SDIO1_CD		MPP(20, 0x3, 0)
+#define MPP20_SDIO0_CD		MPP(20, 0x5, 0)
+#define MPP20_SPI1_MISO		MPP(20, 0x6, 0)
+
+#define MPP21			21
+#define MPP21_GPIO		MPP(21, 0x0, 1)
+#define MPP21_UART1_RTS		MPP(21, 0x1, 0)
+#define MPP21_LCD_SPI_CS0	MPP(21, 0x2, 0)
+#define MPP21_SDIO1_WP		MPP(21, 0x3, 0)
+#define MPP21_SSP_SFRM		MPP(21, 0x4, 0)
+#define MPP21_SDIO0_WP		MPP(21, 0x5, 0)
+#define MPP21_SPI1_CS		MPP(21, 0x6, 0)
+
+#define MPP22			22
+#define MPP22_GPIO		MPP(22, 0x0, 1)
+#define MPP22_UART1_CTS		MPP(22, 0x1, 0)
+#define MPP22_LCD_SPI_MOSI	MPP(22, 0x2, 0)
+#define MPP22_SDIO1_BUSPWR	MPP(22, 0x3, 0)
+#define MPP22_SSP_TXD		MPP(22, 0x4, 0)
+#define MPP22_SDIO0_BUSPWR	MPP(22, 0x5, 0)
+#define MPP22_SPI1_MOSI		MPP(22, 0x6, 0)
+
+#define MPP23			23
+#define MPP23_GPIO		MPP(23, 0x0, 1)
+#define MPP23_LCD_SPI_SCK	MPP(23, 0x2, 0)
+#define MPP23_SDIO1_LEDCTRL	MPP(23, 0x3, 0)
+#define MPP23_SSP_SCLK		MPP(23, 0x4, 0)
+#define MPP23_SDIO0_LEDCTRL	MPP(23, 0x5, 0)
+#define MPP23_SPI1_SCK		MPP(23, 0x6, 0)
+
+/* MPP_CAMERA = MPP[24:39] */
+#define MPP_CAMERA		24
+#define MPP_CAMERA_CAMERA	MPP(24, 0x0, 0)
+#define MPP_CAMERA_GPIO		MPP(24, 0x1, 1)
+#define MPP_CAMERA_MAX		39
+
+/* MPP_SDIO0 = MPP[40:45] */
+#define MPP_SDIO0		40
+#define MPP_SDIO0_SDIO		MPP(40, 0x0, 0)
+#define MPP_SDIO0_GPIO		MPP(40, 0x1, 1)
+#define MPP_SDIO0_MAX		45
+
+/* MPP_SDIO1 = MPP[46:51] */
+#define MPP_SDIO1		46
+#define MPP_SDIO1_SDIO		MPP(46, 0x0, 0)
+#define MPP_SDIO1_GPIO		MPP(46, 0x1, 1)
+#define MPP_SDIO1_MAX		51
+
+/* MPP_AUDIO1 = MPP[52:57] */
+#define MPP_AUDIO1		52
+#define MPP_AUDIO1_I2S_SPDIFO	MPP(52, 0x0, 0)
+#define MPP_AUDIO1_I2S		MPP(52, 0x2, 0)
+#define MPP_AUDIO1_SPDIFO	MPP(52, 0x8, 0)
+#define MPP_AUDIO1_GPIO		MPP(52, 0xa, 1)
+#define MPP_AUDIO1_TWSI		MPP(52, 0xb, 0)
+#define MPP_AUDIO1_SSP_SPDIFO	MPP(52, 0xc, 0)
+#define MPP_AUDIO1_SSP		MPP(52, 0xe, 0)
+#define MPP_AUDIO1_SSP_TWSI	MPP(52, 0xf, 0)
+#define MPP_AUDIO1_MAX		57
+
+/* MPP_SPI = MPP[58:61] */
+#define MPP_SPI			58
+#define MPP_SPI_SPI		MPP(58, 0x0, 0)
+#define MPP_SPI_GPIO		MPP(58, 0x1, 1)
+#define MPP_SPI_MAX		61
+
+/* MPP_UART1 = MPP[62:63] */
+#define MPP_UART1		62
+#define MPP_UART1_UART1		MPP(62, 0x0, 0)
+#define MPP_UART1_GPIO		MPP(62, 0x1, 1)
+#define MPP_UART1_MAX		63
+
+/* MPP_NAND = MPP[64:71] */
+#define MPP_NAND		64
+#define MPP_NAND_NAND		MPP(64, 0x0, 0)
+#define MPP_NAND_GPO		MPP(64, 0x1, 1)
+#define MPP_NAND_MAX		71
+
+/* MPP_AUDIO0 = Internal AC97/I2S mux for audio0 pins */
+#define MPP_AUDIO0		72
+#define MPP_AUDIO0_I2S		MPP(72, 0x0, 0)
+#define MPP_AUDIO0_AC97		MPP(72, 0x1, 0)
+
+/* MPP_TWSI = Internal TWSI option mux */
+#define MPP_TWSI		73
+#define MPP_TWSI_NONE		MPP(73, 0x0, 0)
+#define MPP_TWSI_OPTION1	MPP(73, 0x1, 0)
+#define MPP_TWSI_OPTION2	MPP(73, 0x2, 0)
+#define MPP_TWSI_OPTION3	MPP(73, 0x3, 0)
+
+#define MPP_MAX			MPP_TWSI
+
+u8 dove_mpp_get_gpio_caps(u8 num);
+void dove_mpp_conf(u16 *mpp_list);
+
+#endif
-- 
1.7.10.4

[U-Boot] [PATCH 02/10] GPIO: add gpio driver for Orion SoCs

[Sebastian Hesselbarth]

This adds a gpio driver for Marvell Orion SoCs, i.e. orion5x, kirkwood,
dove. This is based on kw_gpio but as gpio capabilities depend heavily
on the mpp configuration for dove, it allows to set gpi/gpo capabilities
from mpp. This should be compatible with the current kw_gpio and porting
mpp of kirkwood and orion5x is appreciated.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
---
 drivers/gpio/Makefile     |    1 +
 drivers/gpio/orion_gpio.c |  167 +++++++++++++++++++++++++++++++++++++++++++++
 include/orion_gpio.h      |   64 +++++++++++++++++
 3 files changed, 232 insertions(+)
 create mode 100644 drivers/gpio/orion_gpio.c
 create mode 100644 include/orion_gpio.h

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index d50ac3b..6fc163b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 LIB 	:= $(obj)libgpio.o
 
 COBJS-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
+COBJS-$(CONFIG_ORION_GPIO)	+= orion_gpio.o
 COBJS-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
 COBJS-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
 COBJS-$(CONFIG_MARVELL_MFP)	+= mvmfp.o
diff --git a/drivers/gpio/orion_gpio.c b/drivers/gpio/orion_gpio.c
new file mode 100644
index 0000000..209354d
--- /dev/null
+++ b/drivers/gpio/orion_gpio.c
@@ -0,0 +1,167 @@
+/*
+ * Marvell Orion SoC GPIO handling.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed orion_gpiochip struct and kernel level irq handling.
+ * Dieter Kiermaier dk-arm-linux at gmx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <orion_gpio.h>
+
+static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
+static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
+
+void __set_direction(unsigned pin, int input)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_IO_CONF(base));
+	if (input)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_IO_CONF(base));
+
+	u = readl(GPIO_IO_CONF(base));
+}
+
+void __set_level(unsigned pin, int high)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_OUT(base));
+	if (high)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_OUT(base));
+}
+
+void __set_blinking(unsigned pin, int blink)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_BLINK_EN(base));
+	if (blink)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_BLINK_EN(base));
+}
+
+int orion_gpio_is_valid(unsigned pin, int mode)
+{
+	if (pin < GPIO_MAX) {
+		if ((mode & GPIO_INPUT_OK) &&
+		    !test_bit(pin, gpio_valid_input))
+			goto err_out;
+
+		if ((mode & GPIO_OUTPUT_OK) &&
+		    !test_bit(pin, gpio_valid_output))
+			goto err_out;
+		return 0;
+	}
+
+err_out:
+	printf("%s: invalid GPIO %d/%d\n", __func__, pin, GPIO_MAX);
+	return 1;
+}
+
+void orion_gpio_set_valid(unsigned pin, int mode)
+{
+	if (mode & GPIO_INPUT_OK)
+		__set_bit(pin, gpio_valid_input);
+	else
+		__clear_bit(pin, gpio_valid_input);
+	if (mode & GPIO_OUTPUT_OK)
+		__set_bit(pin, gpio_valid_output);
+	else
+		__clear_bit(pin, gpio_valid_output);
+}
+
+/*
+ * GENERIC_GPIO primitives.
+ */
+int orion_gpio_direction_input(unsigned pin)
+{
+	if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) != 0)
+		return 1;
+
+	/* Configure GPIO direction. */
+	__set_direction(pin, 1);
+
+	return 0;
+}
+
+int orion_gpio_direction_output(unsigned pin, int value)
+{
+	if (orion_gpio_is_valid(pin, GPIO_OUTPUT_OK) != 0) {
+		printf("%s: invalid GPIO %d\n", __func__, pin);
+		return 1;
+	}
+
+	__set_blinking(pin, 0);
+
+	/* Configure GPIO output value. */
+	__set_level(pin, value);
+
+	/* Configure GPIO direction. */
+	__set_direction(pin, 0);
+
+	return 0;
+}
+
+int orion_gpio_get_value(unsigned pin)
+{
+	u32 base = GPIO_BASE(pin);
+	int val;
+
+	if (readl(GPIO_IO_CONF(base)) & (1 << (pin & 31)))
+		val = readl(GPIO_DATA_IN(base)) ^ readl(GPIO_IN_POL(base));
+	else
+		val = readl(GPIO_OUT(base));
+
+	return (val >> (pin & 31)) & 1;
+}
+
+void orion_gpio_set_value(unsigned pin, int value)
+{
+	/* Configure GPIO output value. */
+	__set_level(pin, value);
+}
+
+void orion_gpio_set_blink(unsigned pin, int blink)
+{
+	/* Set output value to zero. */
+	__set_level(pin, 0);
+
+	/* Set blinking. */
+	__set_blinking(pin, blink);
+}
diff --git a/include/orion_gpio.h b/include/orion_gpio.h
new file mode 100644
index 0000000..ba67068
--- /dev/null
+++ b/include/orion_gpio.h
@@ -0,0 +1,64 @@
+/*
+ * Marvell Orion SoCs common gpio
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ORION_GPIO_H
+#define __ORION_GPIO_H
+
+/*
+ * SoC-specific gpio.h defines
+ * GPIO_MAX and GPIO_BASE(pin) macro
+ */
+
+#define GPIO_INPUT_OK		(1 << 0)
+#define GPIO_OUTPUT_OK		(1 << 1)
+#define GPIO_LOW		0
+#define GPIO_HIGH		1
+
+/* got from kernel include/linux/bitops.h */
+#define BITS_PER_BYTE 8
+#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+
+#define GPIO_OUT(base)		((base) + 0x00)
+#define GPIO_IO_CONF(base)	((base) + 0x04)
+#define GPIO_BLINK_EN(base)	((base) + 0x08)
+#define GPIO_IN_POL(base)	((base) + 0x0c)
+#define GPIO_DATA_IN(base)	((base) + 0x10)
+#define GPIO_EDGE_CAUSE(base)	((base) + 0x14)
+#define GPIO_EDGE_MASK(base)	((base) + 0x18)
+#define GPIO_LEVEL_MASK(base)	((base) + 0x1c)
+
+/*
+ * Orion-specific GPIO API
+ */
+
+void orion_gpio_set_valid(unsigned pin, int mode);
+int orion_gpio_is_valid(unsigned pin, int mode);
+int orion_gpio_direction_input(unsigned pin);
+int orion_gpio_direction_output(unsigned pin, int value);
+int orion_gpio_get_value(unsigned pin);
+void orion_gpio_set_value(unsigned pin, int value);
+void orion_gpio_set_blink(unsigned pin, int blink);
+void orion_gpio_set_unused(unsigned pin);
+
+#endif
-- 
1.7.10.4

[U-Boot] [PATCH 03/10] MMC: sdhci: Add support for dove sdhci

[Sebastian Hesselbarth]

This adds a driver for the sdhci controller found on Dove SoCs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
---
 drivers/mmc/Makefile     |    1 +
 drivers/mmc/dove_sdhci.c |  101 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 102 insertions(+)
 create mode 100644 drivers/mmc/dove_sdhci.c

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 65791aa..f7c731f 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -31,6 +31,7 @@ endif
 
 COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+COBJS-$(CONFIG_DOVE_SDHCI) += dove_sdhci.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
 COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
diff --git a/drivers/mmc/dove_sdhci.c b/drivers/mmc/dove_sdhci.c
new file mode 100644
index 0000000..ac15fd7
--- /dev/null
+++ b/drivers/mmc/dove_sdhci.c
@@ -0,0 +1,101 @@
+/*
+ *
+ * Marvell Dove SDHCI driver
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on linux drivers/mmc/host/sdhci-dove.c
+ * by: Saeed Bishara <saeed@marvell.com>
+ *     Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/arch/dove.h>
+
+static u16 dove_sdhci_readw(struct sdhci_host *host, int reg)
+{
+	u16 ret;
+
+	switch (reg) {
+	case SDHCI_HOST_VERSION:
+	case SDHCI_SLOT_INT_STATUS:
+		/* those registers don't exist */
+		return 0;
+	default:
+		ret = readw(host->ioaddr + reg);
+	}
+
+	return ret;
+}
+
+static u32 dove_sdhci_readl(struct sdhci_host *host, int reg)
+{
+	u32 ret;
+
+	switch (reg) {
+	case SDHCI_CAPABILITIES:
+		ret = readl(host->ioaddr + reg);
+		/* Mask the support for 3.0V */
+		ret &= ~SDHCI_CAN_VDD_300;
+		break;
+	default:
+		ret = readl(host->ioaddr + reg);
+	}
+
+	return ret;
+}
+
+static struct sdhci_ops dove_sdhci_ops = {
+	.read_w	= dove_sdhci_readw,
+	.read_l	= dove_sdhci_readl,
+};
+
+static struct sdhci_host hosts[2] = {
+	{
+		.name = "Dove SDHCI0",
+		.ioaddr = (void *)DOVE_SDIO0_BASE,
+	},
+	{
+		.name = "Dove SDHCI1",
+		.ioaddr = (void *)DOVE_SDIO1_BASE,
+	},
+};
+
+int dove_sdhci_init(int num)
+{
+	struct sdhci_host *host;
+
+	if (num < 0 || num > 1)
+		return 1;
+
+	host = &hosts[num];
+
+	if (host->version)
+		return 1;
+
+	host->quirks =
+		SDHCI_QUIRK_NO_HISPD_BIT |
+		SDHCI_QUIRK_BROKEN_R1B |
+		SDHCI_QUIRK_32BIT_DMA_ADDR;
+	host->version = SDHCI_SPEC_200;
+	host->ops = &dove_sdhci_ops;
+
+	add_sdhci(host, 50000000, 4000000);
+	return 0;
+}
-- 
1.7.10.4

[U-Boot] [PATCH 04/10] SPI: Add Orion SPI driver

[Sebastian Hesselbarth]

This adds an SPI driver found on Marvell Orion SoCs. This driver is
taken from kirkwood_spi but removes mpp configuration as dove has
dedicated spi pins. To have a common driver for orion5x, kirkwood,
and dove, mpp configuration should be handled in some cpu/board-specific
setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
---
 drivers/spi/Makefile    |    1 +
 drivers/spi/orion_spi.c |  217 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 218 insertions(+)
 create mode 100644 drivers/spi/orion_spi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index f0b82c6..679ba61 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
 COBJS-$(CONFIG_CF_SPI) += cf_spi.o
 COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
 COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_ORION_SPI) += orion_spi.o
 COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
 COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
diff --git a/drivers/spi/orion_spi.c b/drivers/spi/orion_spi.c
new file mode 100644
index 0000000..8a50531
--- /dev/null
+++ b/drivers/spi/orion_spi.c
@@ -0,0 +1,217 @@
+/*
+ * Marvell Orion SoCs common spi driver
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * based on kirkwood_spi.c written by
+ *  Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/arch/config.h>
+
+/* SPI Registers on orion SOC */
+struct orionspi_registers {
+	u32 ctrl;	/* 0x00 */
+	u32 cfg;	/* 0x04 */
+	u32 dout;	/* 0x08 */
+	u32 din;	/* 0x0c */
+	u32 irq_cause;	/* 0x10 */
+	u32 irq_mask;	/* 0x14 */
+};
+
+#define ORIONSPI_CLKPRESCL_MASK	0x1f
+#define ORIONSPI_CLKPRESCL_MIN	0x12
+#define ORIONSPI_CSN_ACT	1 /* Activates serial memory interface */
+#define ORIONSPI_SMEMRDY	(1 << 1) /* SerMem Data xfer ready */
+#define ORIONSPI_IRQUNMASK	1 /* unmask SPI interrupt */
+#define ORIONSPI_IRQMASK	0 /* mask SPI interrupt */
+#define ORIONSPI_SMEMRDIRQ	1 /* SerMem data xfer ready irq */
+#define ORIONSPI_XFERLEN_1BYTE	0
+#define ORIONSPI_XFERLEN_2BYTE	(1 << 5)
+#define ORIONSPI_XFERLEN_MASK	(1 << 5)
+#define ORIONSPI_ADRLEN_1BYTE	0
+#define ORIONSPI_ADRLEN_2BYTE	(1 << 8)
+#define ORIONSPI_ADRLEN_3BYTE	(2 << 8)
+#define ORIONSPI_ADRLEN_4BYTE	(3 << 8)
+#define ORIONSPI_ADRLEN_MASK	(3 << 8)
+#define ORIONSPI_TIMEOUT	10000
+
+static struct orionspi_registers *spireg =
+	(struct orionspi_registers *)ORION_SPI_BASE;
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				unsigned int max_hz, unsigned int mode)
+{
+	struct spi_slave *slave;
+	u32 data;
+	u32 kwspi_mpp_config[] = { 0, 0 };
+
+	if (!spi_cs_is_valid(bus, cs))
+		return NULL;
+
+	slave = malloc(sizeof(struct spi_slave));
+	if (!slave)
+		return NULL;
+
+	slave->bus = bus;
+	slave->cs = cs;
+
+	writel(~ORIONSPI_CSN_ACT | ORIONSPI_SMEMRDY, &spireg->ctrl);
+
+	/* calculate spi clock prescaller using max_hz */
+	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
+	data = data < ORIONSPI_CLKPRESCL_MIN ? ORIONSPI_CLKPRESCL_MIN : data;
+	data = data > ORIONSPI_CLKPRESCL_MASK ? ORIONSPI_CLKPRESCL_MASK : data;
+
+	/* program spi clock prescaller using max_hz */
+	writel(ORIONSPI_ADRLEN_3BYTE | data, &spireg->cfg);
+	debug("data = 0x%08x\n", data);
+
+	writel(ORIONSPI_SMEMRDIRQ, &spireg->irq_cause);
+	writel(ORIONSPI_IRQMASK, &spireg->irq_mask);
+
+	return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	free(slave);
+}
+
+#if defined(CONFIG_SYS_KW_SPI_MPP)
+u32 spi_mpp_backup[4];
+#endif
+
+__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return board_spi_claim_bus(slave);
+}
+
+__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
+{
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	board_spi_release_bus(slave);
+}
+
+#ifndef CONFIG_SPI_CS_IS_VALID
+/*
+ * you can define this function board specific
+ * define above CONFIG in board specific config file and
+ * provide the function in board specific src file
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return (bus == 0 && (cs == 0 || cs == 1));
+}
+#endif
+
+void spi_init(void)
+{
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	writel(readl(&spireg->ctrl) | ORIONSPI_IRQUNMASK, &spireg->ctrl);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	writel(readl(&spireg->ctrl) & ORIONSPI_IRQMASK, &spireg->ctrl);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	unsigned int tmpdout, tmpdin;
+	int tm, isread = 0;
+
+	debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
+	      slave->bus, slave->cs, dout, din, bitlen);
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	/*
+	 * handle data in 8-bit chunks
+	 * TBD: 2byte xfer mode to be enabled
+	 */
+	writel(((readl(&spireg->cfg) & ~ORIONSPI_XFERLEN_MASK) |
+		ORIONSPI_XFERLEN_1BYTE), &spireg->cfg);
+
+	while (bitlen > 4) {
+		debug("loopstart bitlen %d\n", bitlen);
+		tmpdout = 0;
+
+		/* Shift data so it's msb-justified */
+		if (dout)
+			tmpdout = *(u32 *) dout & 0x0ff;
+
+		writel(~ORIONSPI_SMEMRDIRQ, &spireg->irq_cause);
+		writel(tmpdout, &spireg->dout);	/* Write the data out */
+		debug("*** spi_xfer: ... %08x written, bitlen %d\n",
+		      tmpdout, bitlen);
+
+		/*
+		 * Wait for SPI transmit to get out
+		 * or time out (1 second = 1000 ms)
+		 * The NE event must be read and cleared first
+		 */
+		for (tm = 0, isread = 0; tm < ORIONSPI_TIMEOUT; ++tm) {
+			if (readl(&spireg->irq_cause) & ORIONSPI_SMEMRDIRQ) {
+				isread = 1;
+				tmpdin = readl(&spireg->din);
+				debug
+					("spi_xfer: din %p..%08x read\n",
+					din, tmpdin);
+
+				if (din) {
+					*((u8 *) din) = (u8) tmpdin;
+					din += 1;
+				}
+				if (dout)
+					dout += 1;
+				bitlen -= 8;
+			}
+			if (isread)
+				break;
+		}
+		if (tm >= ORIONSPI_TIMEOUT)
+			printf("*** spi_xfer: Time out during SPI transfer\n");
+
+		debug("loopend bitlen %d\n", bitlen);
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	return 0;
+}
-- 
1.7.10.4

[U-Boot] [PATCH 05/10] block: mvsata: add dove include

[Sebastian Hesselbarth]

Dove SoC also uses mvsata, therefore add a SoC specific include to
allow to reuse the mvsata ide driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
---
 drivers/block/mvsata_ide.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index a88d0f7..9918f80 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -29,6 +29,8 @@
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 /* SATA port registers */
-- 
1.7.10.4

[U-Boot] [PATCH 06/10] NET: phy: add 88E1310 PHY initialization

[Sebastian Hesselbarth]

This adds PHY initialization for Marvell Alaska 88E1310 PHY.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
---
 drivers/net/phy/marvell.c |   48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index e51e799..e920212 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -89,6 +89,12 @@
 
 #define MIIM_88E1149_PHY_PAGE	29
 
+/* 88E1310 PHY defines */
+#define MIIM_88E1310_PHY_LED_CTRL	16
+#define MIIM_88E1310_PHY_IRQ_EN		18
+#define MIIM_88E1310_PHY_RGMII_CTRL	21
+#define MIIM_88E1310_PHY_PAGE		22
+
 /* Marvell 88E1011S */
 static int m88e1011s_config(struct phy_device *phydev)
 {
@@ -394,6 +400,37 @@ static int m88e1149_config(struct phy_device *phydev)
 	return 0;
 }
 
+/* Marvell 88E1310 */
+static int m88e1310_config(struct phy_device *phydev)
+{
+	u16 reg;
+
+	/* LED link and activity */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
+	reg = (reg & ~0xf) | 0x1;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
+
+	/* Set LED2/INT to INT mode, low active */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
+	reg = (reg & 0x77ff) | 0x0880;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
+
+	/* Set RGMII delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
+	reg |= 0x0030;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
+
+	/* Ensure to return to page 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
+
+	genphy_config_aneg(phydev);
+	phy_reset(phydev);
+
+	return 0;
+}
 
 static struct phy_driver M88E1011S_driver = {
 	.name = "Marvell 88E1011S",
@@ -455,8 +492,19 @@ static struct phy_driver M88E1149S_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver M88E1310_driver = {
+	.name = "Marvell 88E1310",
+	.uid = 0x01410e90,
+	.mask = 0xffffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &m88e1310_config,
+	.startup = &m88e1011s_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 int phy_marvell_init(void)
 {
+	phy_register(&M88E1310_driver);
 	phy_register(&M88E1149S_driver);
 	phy_register(&M88E1145_driver);
 	phy_register(&M88E1121R_driver);
-- 
1.7.10.4

[U-Boot] [PATCH 07/10] NET: mvgbe: add phylib support

[Sebastian Hesselbarth]

This add phylib support to the Marvell GBE driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
---
 drivers/net/mvgbe.c |   68 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 64 insertions(+), 4 deletions(-)

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 47bf27c..192c989 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MV_PHY_ADR_REQUEST 0xee
 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 /*
  * smi_reg_read - miiphy_read callback function.
  *
@@ -184,6 +184,24 @@ static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
 }
 #endif
 
+#if defined(CONFIG_PHYLIB)
+int mvgbe_phy_read(struct mii_dev *bus, int phyAddr, int devAddr, int regAddr)
+{
+	u16 data;
+	int ret;
+	ret = smi_reg_read(bus->name, phyAddr, regAddr, &data);
+	if (ret)
+		return ret;
+	return data;
+}
+
+int mvgbe_phy_write(struct mii_dev *bus, int phyAddr, int devAddr, int regAddr,
+	u16 data)
+{
+	return smi_reg_write(bus->name, phyAddr, regAddr, data);
+}
+#endif
+
 /* Stop and checks all queues */
 static void stop_queue(u32 * qreg)
 {
@@ -467,8 +485,9 @@ static int mvgbe_init(struct eth_device *dev)
 	/* Enable port Rx. */
 	MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
 
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
-	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))   \
+	&& !defined(CONFIG_PHYLIB)		       \
+	&& defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 	/* Wait up to 5s for the link status */
 	for (i = 0; i < 5; i++) {
 		u16 phyadr;
@@ -647,6 +666,45 @@ static int mvgbe_recv(struct eth_device *dev)
 	return 0;
 }
 
+#if defined(CONFIG_PHYLIB)
+int mvgbe_phylib_init(struct eth_device *dev, int phyid)
+{
+	struct mii_dev *bus;
+	struct phy_device *phydev;
+	int ret;
+
+	bus = mdio_alloc();
+	if (!bus) {
+		printf("mdio_alloc failed\n");
+		return -ENOMEM;
+	}
+	bus->read = mvgbe_phy_read;
+	bus->write = mvgbe_phy_write;
+	sprintf(bus->name, dev->name);
+
+	ret = mdio_register(bus);
+	if (ret) {
+		printf("mdio_register failed\n");
+		free(bus);
+		return -ENOMEM;
+	}
+
+	/* Set phy address of the port */
+	mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
+
+	phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		printf("phy_connect failed\n");
+		return -ENODEV;
+	}
+
+	phy_config(phydev);
+	phy_startup(phydev);
+
+	return 0;
+}
+#endif
+
 int mvgbe_initialize(bd_t *bis)
 {
 	struct mvgbe_device *dmvgbe;
@@ -729,7 +787,9 @@ error1:
 
 		eth_register(dev);
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_PHYLIB)
+		mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
+#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 		miiphy_register(dev->name, smi_reg_read, smi_reg_write);
 		/* Set phy address of the port */
 		miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
-- 
1.7.10.4

[U-Boot] [PATCH 08/10] NET: mvgbe: add support for Dove

[Sebastian Hesselbarth]

Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
---
 drivers/net/mvgbe.c |    2 ++
 drivers/net/mvgbe.h |    7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 192c989..590ea0b 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -43,6 +43,8 @@
 #include <asm/arch/kirkwood.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 #include "mvgbe.h"
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index d8a5429..7f5d98f 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -308,10 +308,17 @@
 #define EBAR_TARGET_GUNIT			0x00000007
 
 /* Window attrib */
+#if defined(CONFIG_DOVE)
+#define EBAR_DRAM_CS0				0x00000000
+#define EBAR_DRAM_CS1				0x00000000
+#define EBAR_DRAM_CS2				0x00000000
+#define EBAR_DRAM_CS3				0x00000000
+#else
 #define EBAR_DRAM_CS0				0x00000E00
 #define EBAR_DRAM_CS1				0x00000D00
 #define EBAR_DRAM_CS2				0x00000B00
 #define EBAR_DRAM_CS3				0x00000700
+#endif
 
 /* DRAM Target interface */
 #define EBAR_DRAM_NO_CACHE_COHERENCY		0x00000000
-- 
1.7.10.4

[U-Boot] [PATCH 09/10] Boards: Add support for SolidRun CuBox

[Sebastian Hesselbarth]

With latest support for Marvell Dove SoC, add the SolidRun CuBox as
the very first board with that SoC.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
---
 board/solidrun/cubox/Makefile     |   45 ++++++++++
 board/solidrun/cubox/cubox.c      |  141 ++++++++++++++++++++++++++++++
 board/solidrun/cubox/kwbimage.cfg |   76 ++++++++++++++++
 boards.cfg                        |    1 +
 include/configs/cubox.h           |  175 +++++++++++++++++++++++++++++++++++++
 5 files changed, 438 insertions(+)
 create mode 100644 board/solidrun/cubox/Makefile
 create mode 100644 board/solidrun/cubox/cubox.c
 create mode 100644 board/solidrun/cubox/kwbimage.cfg
 create mode 100644 include/configs/cubox.h

diff --git a/board/solidrun/cubox/Makefile b/board/solidrun/cubox/Makefile
new file mode 100644
index 0000000..c771d72
--- /dev/null
+++ b/board/solidrun/cubox/Makefile
@@ -0,0 +1,45 @@
+#
+# SolidRun CuBox Makefile
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cubox.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/solidrun/cubox/cubox.c b/board/solidrun/cubox/cubox.c
new file mode 100644
index 0000000..70c016f
--- /dev/null
+++ b/board/solidrun/cubox/cubox.c
@@ -0,0 +1,141 @@
+/*
+ * SolidRun CuBox board support
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/mpp.h>
+#include <orion_gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u16 mpp_config[] = {
+	MPP0_GPIO,
+	MPP1_GPIO, /* USB power enable */
+	MPP2_GPIO, /* USB over-current indication */
+	MPP3_GPIO, /* micro button beneath eSATA port */
+	MPP4_GPIO,
+	MPP5_GPIO,
+	MPP6_GPIO,
+	MPP7_GPIO,
+
+	MPP8_GPIO,
+	MPP9_GPIO,
+	MPP10_GPIO,
+	MPP11_GPIO,
+	MPP12_GPIO, /* SDIO0 card detect */
+	MPP13_AUDIO1_EXTCLK, /* Si5351a audio clock output */
+	MPP14_GPIO,
+	MPP15_GPIO,
+
+	MPP16_GPIO,
+	MPP17_GPIO,
+	MPP18_GPIO, /* Red front LED */
+	MPP19_UART3_RXD, /* IR sensor */
+	MPP20_GPIO,
+	MPP21_GPIO,
+	MPP22_GPIO,
+	MPP23_GPIO,
+
+	MPP_CAMERA_GPIO,
+	MPP_SDIO0_SDIO, /* SDIO0 */
+	MPP_SDIO1_GPIO,
+	MPP_AUDIO1_I2S_SPDIFO, /* SPDIF and HDMI audio */
+	MPP_SPI_SPI, /* SPI */
+	MPP_UART1_GPIO,
+	MPP_NAND_GPO,
+
+	MPP_AUDIO0_I2S,
+	MPP_TWSI_OPTION1, /* TWSI on dedicated pins */
+	0 };
+
+int board_early_init_f(void)
+{
+	struct dove_gpio_init gpp = {
+		.val0  = 0x00010186,
+		.oe0_n = 0xffffffff,
+		.val1  = 0x018000c0,
+		.oe1_n = 0xffffffff,
+		.val2  = 0x00000000,
+		.oe2_n = 0xffffffff,
+	};
+
+	dove_init_gpio(&gpp);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = dove_dram_start(0) + 0x100;
+
+	/* configure mpp */
+	dove_mpp_conf(mpp_config);
+
+	/* usb power enable */
+	orion_gpio_direction_output(MPP1, GPIO_HIGH);
+
+	/* blink led */
+	orion_gpio_direction_output(MPP18, GPIO_HIGH);
+	orion_gpio_set_blink(MPP18, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_MMC
+int board_mmc_init(bd_t *bis)
+{
+	dove_sdhci_init(0);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_RESET_PHY_R
+void dove_eth_phy_init(char *name)
+{
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__func__);
+		return;
+	}
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("%s PHY initialized\n", name);
+}
+
+void reset_phy(void)
+{
+	dove_eth_phy_init("egiga0");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/solidrun/cubox/kwbimage.cfg b/board/solidrun/cubox/kwbimage.cfg
new file mode 100644
index 0000000..c3f1ad9
--- /dev/null
+++ b/board/solidrun/cubox/kwbimage.cfg
@@ -0,0 +1,76 @@
+#
+# Marvell BootROM config for SolidRun CuBox
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# SDRAM initalization
+DATA 0xd0800020 0x00022430	# SDRAM Configuration register 0
+DATA 0xd0800030 0x00022430	# SDRAM Configuration register 1
+DATA 0xd0800050 0x911500c3	# SDRAM Timing register 1
+DATA 0xd0800060 0x646602c4	# SDRAM Timing register 2
+DATA 0xd0800190 0xc2003053	# SDRAM Timing register 3
+DATA 0xd08001c0 0x34f4a187	# SDRAM Timing register 4
+DATA 0xd0800650 0x000f0121	# SDRAM Timing register 5
+DATA 0xd0800660 0x04040200	# SDRAM Timing register 6
+DATA 0xd0800080 0x00000000	# SDRAM Control register 1
+DATA 0xd0800090 0x00080000	# SDRAM Control register 2
+DATA 0xd08000f0 0xc0000000	# SDRAM Control register 3
+DATA 0xd08001a0 0x20c0c009	# SDRAM Control register 4
+DATA 0xd0800280 0x010e0202	# SDRAM Control register 5
+DATA 0xd0800760 0x00000000	# SDRAM Control register 6
+DATA 0xd0800770 0x0000000a	# SDRAM Control register 7
+DATA 0xd0800140 0x20004044	# SDRAM PHY control register 3
+DATA 0xd08001d0 0x133c2339	# SDRAM PHY control register 7
+DATA 0xd08001e0 0x07700330	# SDRAM PHY control register 8
+DATA 0xd08001f0 0x00000033	# SDRAM PHY control register 9
+DATA 0xd0800200 0x0011311c	# SDRAM PHY control register 10
+DATA 0xd0800210 0x00300000	# SDRAM PHY control register 11
+DATA 0xd0800240 0x80000000	# SDRAM PHY control register 14
+DATA 0xd0800510 0x010e0101	# SDRAM MCB control register 1
+DATA 0xd0800230 0x2028006a	# SDRAM PHY control register 13
+DATA 0xd0800e10 0x00280062	# SDRAM PHY DLL control registers 2
+DATA 0xd0800e20 0x00280062	# SDRAM PHY DLL control registers 3
+DATA 0xd0800e30 0x00280062	# SDRAM PHY DLL control registers 4
+
+# SDRAM memory map (2x512MB)
+DATA 0xd0800100 0x000d0001	# SDRAM Memory Address Map register 1
+DATA 0xd0800110 0x200d0001	# SDRAM Memory Address Map register 1
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/boards.cfg b/boards.cfg
index ca9b12b..1bd734b 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -289,6 +289,7 @@ whistler                     arm         armv7:arm720t whistler          nvidia
 colibri_t20_iris             arm         armv7:arm720t colibri_t20_iris  toradex        tegra20
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
 snowball                     arm         armv7       snowball               st-ericsson    u8500
+cubox                        arm         armv7       cubox               solidrun       dove
 kzm9g                        arm         armv7       kzm9g               kmc            rmobile
 armadillo-800eva             arm         armv7       armadillo-800eva    atmark-techno  rmobile
 zynq                         arm         armv7       zynq                xilinx         zynq
diff --git a/include/configs/cubox.h b/include/configs/cubox.h
new file mode 100644
index 0000000..223b1d7
--- /dev/null
+++ b/include/configs/cubox.h
@@ -0,0 +1,175 @@
+/*
+ * SolidRun CuBox config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_CUBOX_H
+#define _CONFIG_CUBOX_H
+#include <asm/sizes.h>
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\SolidRun CuBox"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MACH_SOLIDRUN_CUBOX	/* Machine type */
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_ORION_GPIO               /* Orion GPIO driver */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable u-boot API for standalone programs.
+ */
+#define CONFIG_API
+
+/*
+ * Enable devicetree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Commands configuration
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFT_PARTITION
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * redefine mv-common.h macros for armv7/cubox
+ */
+#undef CONFIG_SYS_PROMPT	/* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT	"CuBox> "	/* Command Prompt */
+
+/* There is no arch_misc_init on armv7 */
+#undef CONFIG_ARCH_MISC_INIT
+
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN	(4 * 1024 * 1024) /* 4MiB for malloc() */
+
+/*
+ *  Environment variables configurations
+ */
+#if defined(CONFIG_CMD_SF)
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SECT_SIZE		0x1000	/* 4k */
+#define CONFIG_ENV_SIZE			0x20000 /* 128k */
+#define CONFIG_ENV_OFFSET		0xc0000 /* env starts here */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+
+/*
+ * Default CuBox bootscript environment
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootscript=boot.scr\0"						\
+	"loadaddr=0x02000000\0"						\
+	"mmc_started=0\0"						\
+	"ide_started=0\0"						\
+	"usb_started=0\0"						\
+	"mtdparts=mtdparts=spi0.0:768k(u-boot)ro,128k(uboot_env),128k(fdt),-(empty)\0"	\
+	"ethaddr=00:50:43:15:17:17\0"
+
+#define CONFIG_BOOTCOMMAND						\
+	"for devn in usb mmc ide ; do "					\
+	"  for part in 0 1; do "					\
+	"    for dir  in / /boot/;do "					\
+	"      for fs in ext2 fat; do "					\
+	"        echo ===> Executing ${fs}load ${devn} 0:${part} ${loadaddr} ${dir}${bootscript};" \
+	"        if itest.s $devn -eq mmc; then"			\
+	"          if itest.s $mmc_started -ne 1; then"			\
+	"            mmcinfo; setenv mmc_started '1';fi;fi;"		\
+	"        if itest.s $devn -eq usb; then"			\
+	"          if itest.s $usb_started -ne 1; then"			\
+	"            usb start; setenv usb_started '1';fi;fi;"		\
+	"        if itest.s $devn -eq ide; then"			\
+	"          if itest.s $ide_started -ne 1; then"			\
+	"            ide reset; setenv ide_started '1';fi;fi;"		\
+	"        if ${fs}load ${devn} 0:${part} ${loadaddr} ${dir}${bootscript}; then" \
+	"          source ${loadaddr}; fi;"				\
+	"        if itest.s $devn -eq usb; then"			\
+	"          echo ===> Executing ${fs}load ${devn} 1:${part} ${loadaddr} ${dir}${bootscript};" \
+	"          if ${fs}load ${devn} 1:${part} ${loadaddr} ${dir}${bootscript}; then" \
+	"            source ${loadaddr}; fi;"				\
+	"        fi;"							\
+	"      done;"							\
+	"    done;"							\
+	"  done;"							\
+	"done;"								\
+	"tftp ${loadaddr} ${bootscript};"				\
+	"source ${loadaddr};"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1}	/* enable port 0 */
+#define CONFIG_PHY_BASE_ADR	1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
+#endif /* CONFIG_CMD_NET */
+
+#ifdef CONFIG_CMD_IDE
+#undef CONFIG_IDE_LED
+#undef CONFIG_SYS_IDE_MAXBUS
+#define CONFIG_SYS_IDE_MAXBUS		1
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_CUBOX_H */
-- 
1.7.10.4

[U-Boot] [PATCH 10/10] tools: Add support for Dove to kwboot

[Sebastian Hesselbarth]

On Dove kwboot can also be used to boot an u-boot image into RAM.
In contrast to Kirkwood, Dove does not support the UART boot mode
sequence but requires the UART boot mode to be selected through
strap pins. The SolidRun CuBox has a push button to allow uart
boot mode but fails on the boot sequence sent by kwboot.

This patch adds another cmdline option to allow to send a boot
image without the boot sequence and adds support for Dove.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
---
 tools/Makefile |    2 ++
 tools/kwboot.c |   44 ++++++++++++++++++++++++++++++++++++++++----
 2 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/tools/Makefile b/tools/Makefile
index 686840a..845384f 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -73,6 +73,7 @@ BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
 BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
 BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
 BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
+BIN_FILES-$(CONFIG_DOVE) += kwboot$(SFX)
 
 # Source files which exist outside the tools directory
 EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
@@ -104,6 +105,7 @@ NOPED_OBJ_FILES-y += os_support.o
 OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
 NOPED_OBJ_FILES-y += ublimage.o
 OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
+OBJ_FILES-$(CONFIG_DOVE) += kwboot.o
 
 # Don't build by default
 #ifeq ($(ARCH),ppc)
diff --git a/tools/kwboot.c b/tools/kwboot.c
index e773f01..199678a 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -293,6 +293,30 @@ kwboot_bootmsg(int tty, void *msg)
 }
 
 static int
+kwboot_bootmsg_uartmode(int tty)
+{
+	int rc;
+	char c;
+
+	kwboot_printv("Please reboot the target into UART boot mode...");
+
+	do {
+		rc = tcflush(tty, TCIOFLUSH);
+		if (rc)
+			break;
+
+		rc = kwboot_tty_recv(tty, &c, 1, KWBOOT_MSG_RSP_TIMEO);
+
+		kwboot_spinner();
+
+	} while (rc || c != NAK);
+
+	kwboot_printv("\n");
+
+	return rc;
+}
+
+static int
 kwboot_xm_makeblock(struct kwboot_block *block, const void *data,
 		    size_t size, int pnum)
 {
@@ -601,10 +625,11 @@ static void
 kwboot_usage(FILE *stream, char *progname)
 {
 	fprintf(stream,
-		"Usage: %s -b <image> [ -p ] [ -t ] "
+		"Usage: %s -b <image> [ -p ] [ -t ] [ -u ] "
 		"[-B <baud> ] <TTY>\n", progname);
 	fprintf(stream, "\n");
 	fprintf(stream, "  -b <image>: boot <image>\n");
+	fprintf(stream, "  -u: target requires UART boot mode (e.g. Dove)\n");
 	fprintf(stream, "  -p: patch <image> to type 0x69 (uart boot)\n");
 	fprintf(stream, "\n");
 	fprintf(stream, "  -t: mini terminal\n");
@@ -617,7 +642,7 @@ int
 main(int argc, char **argv)
 {
 	const char *ttypath, *imgpath;
-	int rv, rc, tty, term, prot, patch;
+	int rv, rc, tty, uartmode, term, prot, patch;
 	void *bootmsg;
 	void *img;
 	size_t size;
@@ -628,6 +653,7 @@ main(int argc, char **argv)
 	bootmsg = NULL;
 	imgpath = NULL;
 	img = NULL;
+	uartmode = 0;
 	term = 0;
 	patch = 0;
 	size = 0;
@@ -636,7 +662,7 @@ main(int argc, char **argv)
 	kwboot_verbose = isatty(STDOUT_FILENO);
 
 	do {
-		int c = getopt(argc, argv, "hb:ptB:");
+		int c = getopt(argc, argv, "hb:ptuB:");
 		if (c < 0)
 			break;
 
@@ -654,6 +680,10 @@ main(int argc, char **argv)
 			term = 1;
 			break;
 
+		case 'u':
+			uartmode = 1;
+			break;
+
 		case 'B':
 			speed = kwboot_tty_speed(atoi(optarg));
 			if (speed == -1)
@@ -702,7 +732,13 @@ main(int argc, char **argv)
 		}
 	}
 
-	if (bootmsg) {
+	if (uartmode) {
+		rc = kwboot_bootmsg_uartmode(tty);
+		if (rc) {
+			perror("bootmsg");
+			goto out;
+		}
+	} else if (bootmsg) {
 		rc = kwboot_bootmsg(tty, bootmsg);
 		if (rc) {
 			perror("bootmsg");
-- 
1.7.10.4

[U-Boot] [PATCH 01/10] ARM: dove: add support for Marvell Dove SoC

[Luka Perkov]

Hi Sebastian,

On Sun, Dec 02, 2012 at 03:36:13PM +0100, Sebastian Hesselbarth wrote:
> This patch adds initial support for the armv7-based Marvell Dove SoC
> (88AP510).
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

...

> +	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
> +		/* If above loop terminated prematurely, we need to set
> +		 * remaining banks' start address & size as 0. Otherwise other
> +		 * u-boot functions and Linux kernel gets wrong values which
> +		 * could result in crash */

Please fix this comment style.

...

> +	/* configure gpio capabilities */
> +	/* gpio allows gpio on all audio1 mpp pins */

Here too.

Also, your patch to MAINTAINERS file is missing...

Luka

[U-Boot] [PATCH 09/10] Boards: Add support for SolidRun CuBox

[Luka Perkov]

Hi Sebastian,

On Sun, Dec 02, 2012 at 03:36:21PM +0100, Sebastian Hesselbarth wrote:
> With latest support for Marvell Dove SoC, add the SolidRun CuBox as
> the very first board with that SoC.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

...

> +/*
> + * Enable devicetree support
> + */

Shouldn't this be "device tree"?

Luka

[U-Boot] [PATCH 10/10] tools: Add support for Dove to kwboot

[Luka Perkov]

Hi Sebastian,

On Sun, Dec 02, 2012 at 03:36:22PM +0100, Sebastian Hesselbarth wrote:
> On Dove kwboot can also be used to boot an u-boot image into RAM.
> In contrast to Kirkwood, Dove does not support the UART boot mode
> sequence but requires the UART boot mode to be selected through
> strap pins. The SolidRun CuBox has a push button to allow uart
> boot mode but fails on the boot sequence sent by kwboot.
> 
> This patch adds another cmdline option to allow to send a boot
> image without the boot sequence and adds support for Dove.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: u-boot at lists.denx.de
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> Cc: Andy Fleming <afleming@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Daniel Stodden <daniel.stodden@gmail.com>
> Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
> ---
>  tools/Makefile |    2 ++
>  tools/kwboot.c |   44 ++++++++++++++++++++++++++++++++++++++++----
>  2 files changed, 42 insertions(+), 4 deletions(-)

Please update the documentation too (doc/kwboot.1).

Luka

[U-Boot] [PATCH v2 00/10] Add Marvell Dove and SolidRun CuBox

[Sebastian Hesselbarth]

This patch set add support for the Marvell Dove 88AP510 SoC and
the SolidRun CuBox board based on that SoC. The patch set is divided
into the four following sections:

(1) Patches 1-5:
Add support for the Dove SoC and related drivers. Where possible
drivers from Marvell Kirkwood are reused (mvsata, mvgbe), or
forked to allow more generic usage (SPI, GPIO). The SDHCI driver
is different and a new driver is added for it. The forked drivers
can also be reused on Kirkwood but that would have required patching
existing boards.

(2) Patches 6-8:
Allow mvgbe to use the phylib API, add support for 88E1310 PHY and
allow Dove to use the driver.

(3) Patch 9
Add the SolidRun CuBox as the first board based on Marvell Dove SoC.

(4) Patch 10
Add support for different UART boot mode found on Dove.

Changelog:
v1->v2: respect review comments by Luka Perkov
- fix commenting styles and typos
- add MAINTAINERS entry
- also update kwboot.1 manpage

Sebastian Hesselbarth (10):
  ARM: dove: add support for Marvell Dove SoC
  GPIO: add gpio driver for Orion SoCs
  MMC: sdhci: Add support for dove sdhci
  SPI: Add Orion SPI driver
  block: mvsata: add dove include
  NET: phy: add 88E1310 PHY initialization
  NET: mvgbe: add phylib support
  NET: mvgbe: add support for Dove
  Boards: Add support for SolidRun CuBox
  tools: Add support for Dove to kwboot

 MAINTAINERS                             |    4 +
 arch/arm/cpu/armv7/dove/Makefile        |   49 +++++
 arch/arm/cpu/armv7/dove/cpu.c           |  266 ++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/dram.c          |  118 ++++++++++++
 arch/arm/cpu/armv7/dove/lowlevel_init.S |   83 ++++++++
 arch/arm/cpu/armv7/dove/mpp.c           |  318 +++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/timer.c         |  176 +++++++++++++++++
 arch/arm/cpu/armv7/dove/usb.c           |  101 ++++++++++
 arch/arm/include/asm/arch-dove/config.h |  153 +++++++++++++++
 arch/arm/include/asm/arch-dove/cpu.h    |  204 ++++++++++++++++++++
 arch/arm/include/asm/arch-dove/dove.h   |   93 +++++++++
 arch/arm/include/asm/arch-dove/gpio.h   |   35 ++++
 arch/arm/include/asm/arch-dove/mpp.h    |  283 +++++++++++++++++++++++++++
 board/solidrun/cubox/Makefile           |   45 +++++
 board/solidrun/cubox/cubox.c            |  141 ++++++++++++++
 board/solidrun/cubox/kwbimage.cfg       |   76 ++++++++
 boards.cfg                              |    1 +
 doc/kwboot.1                            |   13 +-
 drivers/block/mvsata_ide.c              |    2 +
 drivers/gpio/Makefile                   |    1 +
 drivers/gpio/orion_gpio.c               |  167 ++++++++++++++++
 drivers/mmc/Makefile                    |    1 +
 drivers/mmc/dove_sdhci.c                |  101 ++++++++++
 drivers/net/mvgbe.c                     |   70 ++++++-
 drivers/net/mvgbe.h                     |    7 +
 drivers/net/phy/marvell.c               |   48 +++++
 drivers/spi/Makefile                    |    1 +
 drivers/spi/orion_spi.c                 |  217 +++++++++++++++++++++
 include/configs/cubox.h                 |  175 +++++++++++++++++
 include/orion_gpio.h                    |   64 +++++++
 tools/Makefile                          |    2 +
 tools/kwboot.c                          |   44 ++++-
 32 files changed, 3048 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/dove/Makefile
 create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
 create mode 100644 arch/arm/cpu/armv7/dove/dram.c
 create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
 create mode 100644 arch/arm/cpu/armv7/dove/timer.c
 create mode 100644 arch/arm/cpu/armv7/dove/usb.c
 create mode 100644 arch/arm/include/asm/arch-dove/config.h
 create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
 create mode 100644 arch/arm/include/asm/arch-dove/dove.h
 create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
 create mode 100644 arch/arm/include/asm/arch-dove/mpp.h
 create mode 100644 board/solidrun/cubox/Makefile
 create mode 100644 board/solidrun/cubox/cubox.c
 create mode 100644 board/solidrun/cubox/kwbimage.cfg
 create mode 100644 drivers/gpio/orion_gpio.c
 create mode 100644 drivers/mmc/dove_sdhci.c
 create mode 100644 drivers/spi/orion_spi.c
 create mode 100644 include/configs/cubox.h
 create mode 100644 include/orion_gpio.h

---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
-- 
1.7.10.4

[U-Boot] [PATCH v2 01/10] ARM: dove: add support for Marvell Dove SoC

[Sebastian Hesselbarth]

This patch adds initial support for the armv7-based Marvell Dove SoC
(88AP510).

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- fix some commenting styles

Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 arch/arm/cpu/armv7/dove/Makefile        |   49 +++++
 arch/arm/cpu/armv7/dove/cpu.c           |  266 ++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/dram.c          |  118 ++++++++++++
 arch/arm/cpu/armv7/dove/lowlevel_init.S |   83 ++++++++
 arch/arm/cpu/armv7/dove/mpp.c           |  318 +++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/timer.c         |  176 +++++++++++++++++
 arch/arm/cpu/armv7/dove/usb.c           |  101 ++++++++++
 arch/arm/include/asm/arch-dove/config.h |  153 +++++++++++++++
 arch/arm/include/asm/arch-dove/cpu.h    |  204 ++++++++++++++++++++
 arch/arm/include/asm/arch-dove/dove.h   |   93 +++++++++
 arch/arm/include/asm/arch-dove/gpio.h   |   35 ++++
 arch/arm/include/asm/arch-dove/mpp.h    |  283 +++++++++++++++++++++++++++
 12 files changed, 1879 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/dove/Makefile
 create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
 create mode 100644 arch/arm/cpu/armv7/dove/dram.c
 create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
 create mode 100644 arch/arm/cpu/armv7/dove/timer.c
 create mode 100644 arch/arm/cpu/armv7/dove/usb.c
 create mode 100644 arch/arm/include/asm/arch-dove/config.h
 create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
 create mode 100644 arch/arm/include/asm/arch-dove/dove.h
 create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
 create mode 100644 arch/arm/include/asm/arch-dove/mpp.h

diff --git a/arch/arm/cpu/armv7/dove/Makefile b/arch/arm/cpu/armv7/dove/Makefile
new file mode 100644
index 0000000..127d67e
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/Makefile
@@ -0,0 +1,49 @@
+#
+# Marvell Dove SoC Makefile
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	+= lowlevel_init.o
+COBJS-y := cpu.o dram.o timer.o mpp.o
+COBJS-$(CONFIG_USB_EHCI_MARVELL) += usb.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/dove/cpu.c b/arch/arm/cpu/armv7/dove/cpu.c
new file mode 100644
index 0000000..b9e708c
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/cpu.c
@@ -0,0 +1,266 @@
+/*
+ * Marvell Dove SoC cpu related functions
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <u-boot/md5.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <hush.h>
+
+void reset_cpu(unsigned long ignored)
+{
+	struct dovecpu_registers *cpureg =
+	    (struct dovecpu_registers *)DOVE_CPU_REG_BASE;
+
+	/* Enable soft reset to assert RSTOUTn */
+	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+	       &cpureg->rstoutn_mask);
+	/* Assert soft reset */
+	writel(readl(&cpureg->sys_soft_rst) | 1,
+	       &cpureg->sys_soft_rst);
+	do {} while (1);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int dove_print_cpu(void)
+{
+	char *cpu;
+	u32 idreg;
+	u16 part, rev;
+
+	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(idreg));
+
+	part = (idreg >> ARM_ID_PARTNUM_OFFSET) & ARM_ID_PARTNUM_MASK;
+	rev = (idreg >> ARM_ID_REVISION_OFFSET) & ARM_ID_REVISION_MASK;
+
+	switch (part) {
+	case DOVECPU_PART_SHEEVA:
+		cpu = "Marvell Sheeva";
+		break;
+	default:
+		cpu = "Unknown CPU";
+	}
+
+	printf("CPU:   %s (rev %d)\n", cpu, rev);
+	return 0;
+}
+
+int dove_print_soc(void)
+{
+	char *soc, *rev;
+	u16 devid = (readl(DOVE_REG_PCIE_DEVID) >> 16) & 0xffff;
+	u8 revid = readl(DOVE_REG_PCIE_REVID) & 0xff;
+
+	switch (devid) {
+	case DOVESOC_DEVID_AP510:
+		soc = "AP510";
+		break;
+	case DOVESOC_DEVID_F6781:
+		soc = "F6781";
+		break;
+	default:
+		printf("ERROR.. %s: Unsupported SoC %04x\n", __func__, devid);
+		return -1;
+	}
+
+	switch (revid) {
+	case DOVESOC_REVID_Z0:
+		rev = "Z0";
+		break;
+	case DOVESOC_REVID_Z1:
+		rev = "Z1";
+		break;
+	case DOVESOC_REVID_Y0:
+		rev = "Y0";
+		break;
+	case DOVESOC_REVID_Y1:
+		rev = "Y1";
+		break;
+	case DOVESOC_REVID_X0:
+		rev = "X0";
+		break;
+	case DOVESOC_REVID_A0:
+		rev = "A0";
+		break;
+	case DOVESOC_REVID_A1:
+		rev = "A1";
+		break;
+	default:
+		rev = "Unknown revision";
+	};
+
+	printf("SoC:   Dove 88%s (%s)\n", soc, rev);
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	if (dove_print_soc())
+		return -1;
+	if (dove_print_cpu())
+		return -1;
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*
+ * dove_init_gpio - initial GPIO configuration
+ */
+void dove_init_gpio(struct dove_gpio_init *gpp)
+{
+	struct dovegpio_registers *gpio0reg =
+		(struct dovegpio_registers *)DOVE_GPIO0_BASE;
+	struct dovegpio_registers *gpio1reg =
+		(struct dovegpio_registers *)DOVE_GPIO1_BASE;
+	struct dovegpio_registers *gpio2reg =
+		(struct dovegpio_registers *)DOVE_GPIO2_BASE;
+
+	/* Init GPIOS to default values as per board requirement */
+	writel(gpp->val0, &gpio0reg->dout);
+	writel(gpp->val1, &gpio1reg->dout);
+	writel(gpp->val2, &gpio2reg->dout);
+	writel(gpp->oe0_n, &gpio0reg->oe);
+	writel(gpp->oe1_n, &gpio1reg->oe);
+	writel(gpp->oe2_n, &gpio2reg->oe);
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int dove_winctrl_calcsize(unsigned int sizeval)
+{
+	int i;
+	unsigned int j = 0;
+	u32 val = sizeval >> 1;
+
+	for (i = 0; val >= 0x10000; i++) {
+		j |= (1 << i);
+		val = val >> 1;
+	}
+	return 0x0000ffff & j;
+}
+
+/*
+ * dove_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Dove Soc to addess different
+ * devices. Windows 0-3 can be configured for size, BAR and remap addr.
+ * Windows 4-7 can be configured for size and BAR.
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ */
+int dove_config_adr_windows(void)
+{
+	struct dovewin_registers *winregs =
+		(struct dovewin_registers *)DOVE_CPU_WIN_BASE;
+
+	/* Window 0: 1M PCIE0 IO address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE0,
+	     DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE), &winregs[0].ctrl);
+
+	writel(DOVE_DEFADR_PCIE0_IO, &winregs[0].base);
+	writel(DOVE_DEFADR_PCIE0_IO_REMAP, &winregs[0].remap_lo);
+	writel(0x0, &winregs[0].remap_hi);
+
+	/* Window 1: 1M PCIE1 IO address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE1,
+	     DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE), &winregs[1].ctrl);
+
+	writel(DOVE_DEFADR_PCIE1_IO, &winregs[1].base);
+	writel(DOVE_DEFADR_PCIE1_IO_REMAP, &winregs[1].remap_lo);
+	writel(0x0, &winregs[1].remap_hi);
+
+	/* Window 2: 128M PCIE0 MEM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE0,
+	     DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE), &winregs[2].ctrl);
+
+	writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].base);
+	writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].remap_lo);
+	writel(0x0, &winregs[2].remap_hi);
+
+	/* Window 3: 128M PCIE1 MEM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE1,
+	     DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE), &winregs[3].ctrl);
+
+	writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].base);
+	writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].remap_lo);
+	writel(0x0, &winregs[3].remap_hi);
+
+	/* Window 4: 1M Cryptographic SRAM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_SASRAM,
+	     DOVECPU_ATTR_SASRAM, DOVECPU_WIN_ENABLE), &winregs[4].ctrl);
+	writel(DOVE_DEFADR_SASRAM, &winregs[4].base);
+
+	/* Window 5: 128M Bootrom address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_BOOTROM,
+	     DOVECPU_ATTR_BOOTROM, DOVECPU_WIN_ENABLE), &winregs[5].ctrl);
+	writel(DOVE_DEFADR_BOOTROM, &winregs[5].base);
+
+	/* Window 6: 1M PMU Scratchpad address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PMURAM,
+	     DOVECPU_ATTR_PMURAM, DOVECPU_WIN_ENABLE), &winregs[6].ctrl);
+	writel(DOVE_DEFADR_PMURAM, &winregs[6].base);
+
+	/* Window 7: Disabled */
+	writel(DOVECPU_WIN_DISABLE, &winregs[7].ctrl);
+
+	return 0;
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	dove_config_adr_windows();
+#ifdef CONFIG_USB_EHCI_MARVELL
+	dove_ehci_phy_init(0);
+	dove_ehci_phy_init(1);
+#endif /* CONFIG_USB_EHCI_MARVELL */
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Enable D-cache. I-cache is already enabled in lowlevel_init.S */
+	dcache_enable();
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+#ifdef CONFIG_MVGBE
+int cpu_eth_init(bd_t *bis)
+{
+	mvgbe_initialize(bis);
+	return 0;
+}
+#endif /* CONFIG_MVGBE */
diff --git a/arch/arm/cpu/armv7/dove/dram.c b/arch/arm/cpu/armv7/dove/dram.c
new file mode 100644
index 0000000..437263c
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/dram.c
@@ -0,0 +1,118 @@
+/*
+ * Marvell Dove SoC DRAM initialization
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DOVE_REG_DRAM_MAP(x)	(DOVE_REGISTER(0x800100) + (x * 0x10))
+#define DRAM_START_MASK		0xff800000
+#define DRAM_SIZE_MASK		0xf
+#define DRAM_SIZE_SHIFT		16
+
+/*
+ * dove_sdram_start - reads start from Memory Address Map Register n
+ */
+u32 dove_dram_start(enum memory_bank bank)
+{
+	u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
+	u32 enable = 0x01 & reg;
+
+	if ((!enable) || (bank > BANK1))
+		return 0;
+
+	return reg & DRAM_START_MASK;
+}
+
+/*
+ * dove_sdram_size - reads size from Memory Address Map Register n
+ */
+u32 dove_dram_size(enum memory_bank bank)
+{
+	u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
+	u32 enable = 0x01 & reg;
+	u32 size;
+
+	if ((!enable) || (bank > BANK1))
+		return 0;
+
+	/*
+	 * area_length: 7 = 8M, 8 = 16M, ..., 15 = 2048M
+	 * size = 1 << (area_length + 16)
+	 */
+	size = (reg >> DRAM_SIZE_SHIFT) & DRAM_SIZE_MASK;
+	size = 1 << (size + 16);
+	return size;
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = dove_dram_start(i);
+		gd->bd->bi_dram[i].size = dove_dram_size(i);
+
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/*
+		 * If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash
+		 */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/armv7/dove/lowlevel_init.S b/arch/arm/cpu/armv7/dove/lowlevel_init.S
new file mode 100644
index 0000000..105d12d
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/lowlevel_init.S
@@ -0,0 +1,83 @@
+/*
+ * Marvell Dove SoC icache and reg base low level init
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/dove.h>
+#include <generated/asm-offsets.h>
+#include <linux/linkage.h>
+
+/*
+ * Enable Tauros2 L2 ICache
+ */
+.macro init_l2cc
+	mrc	15, 0, r0, c1, c0, 1
+	orr	r0, r0, #0x2
+	mcr	15, 0, r0, c1, c0, 1
+.endm /* init_l2cc */
+
+/*
+ * Init internal register base addresses
+ */
+.macro init_reg_base
+	/* set SB reg base to 0xf1000000 */
+	ldr	r1, =(DOVE_PREMAP_INT_REGS_BASE_ADDR)
+	ldr	r6, =DOVE_SB_REGS_PHYS_BASE
+	str	r6, [r1]
+
+	/* set NB reg base to 0xf1800000 */
+	ldr	r1, =(DOVE_CPU_CTRL_REG)
+	ldr	r4, =0xffff0000
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	lsr	r4, r6, #16
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+	/* Set AXI bridge address mapping to 0xf1800000 */
+	ldr	r1, =(DOVE_AXI_CTRL_REG)
+	ldr	r4, =0x007fffff
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+	/* set MC configuration register decode address to 0xf1800000 */
+	ldr	r1, =(DOVE_PREMAP_MC_DECODE_REG)
+	ldr	r4, =0x0000ffff
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+.endm /* init_reg_base */
+
+.section ".text.init", "x"
+
+ENTRY(lowlevel_init)
+	init_l2cc
+	init_reg_base
+
+	/* r12 saved upper lr*/
+	mov pc,lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/dove/mpp.c b/arch/arm/cpu/armv7/dove/mpp.c
new file mode 100644
index 0000000..ed24b38
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/mpp.c
@@ -0,0 +1,318 @@
+/*
+ * Marvell Dove SoC MPP pinmux
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define MPP_BITS	4
+#define MPP_MASK	0xf
+#define MPPS_PER_REG	8
+
+#define MPP_NUM(_x)	((_x) & 0xff)
+#define MPP_SEL(_x)	(((_x) >> 8) & 0x1f)
+#define MPP_GPIO(_x)	((_x) & (1 << 15))
+
+#define MPP_CTRL(i)			(DOVE_MPP_BASE + (i * MPP_BITS))
+#define MPP_PMU_GENERAL_CTRL		(DOVE_MPP_BASE + 0x010)
+#define  PMUG_AUDIO0_AC97_SEL		(1 << 16)
+#define MPP4_CTRL			(DOVE_MPP_BASE + 0x240)
+#define  MPP4_SDIO0_GPIO_SEL		(1 << 0)
+#define  MPP4_SDIO1_GPIO_SEL		(1 << 1)
+#define  MPP4_CAMERA_GPIO_SEL		(1 << 2)
+#define  MPP4_AUDIO1_GPIO_SEL		(1 << 3)
+#define  MPP4_UART1_GPIO_SEL		(1 << 4)
+#define  MPP4_SPI_GPIO_SEL		(1 << 5)
+#define MPP_GENERAL_CTRL		(DOVE_PDMA_BASE + 0x403c)
+#define  MPPG_NAND_GPIO_SEL		(1 << 0)
+#define  MPPG_AUDIO1_SPDIFO_GPIO_SEL	(1 << 1)
+#define GENERAL_CONFIG_1		(DOVE_PDMA_BASE + 0x002c)
+#define  GENERAL_TWSI_MUXEN_OPTION1	(1 << 7)
+#define GENERAL_CONFIG_2		(DOVE_PDMA_BASE + 0x0030)
+#define  GENERAL_TWSI_OPTION3_SEL	(1 << 22)
+#define  GENERAL_TWSI_MUXEN_OPTION3	(1 << 21)
+#define  GENERAL_TWSI_MUXEN_OPTION2	(1 << 20)
+#define SSP_CONFIG_STATUS_1		(DOVE_PDMA_BASE + 0x0034)
+#define  SSP_SSP_ON_AUDIO1		(1 << 0)
+
+/*
+ * MPP0-23 have standard MPP register layout
+ */
+static void dove_mpp_std_set(u16 config)
+{
+	u8 num = MPP_NUM(config);
+	u32 off = (num / MPPS_PER_REG) * MPP_BITS;
+	u32 shift = (num % MPPS_PER_REG) * MPP_BITS;
+	u32 reg;
+
+	/* configure standard MPP pin */
+	reg  = readl(MPP_CTRL(off));
+	reg &= ~(MPP_MASK << shift);
+	reg |= MPP_SEL(config) << shift;
+	writel(reg, MPP_CTRL(off));
+
+	/* configure gpio capabilities */
+	if (MPP_GPIO(config))
+		orion_gpio_set_valid(num, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+	else
+		orion_gpio_set_valid(num, 0);
+}
+
+/*
+ * MPP0-15 also allow to mux PMU functions
+ */
+static void dove_mpp_pmu_set(u16 config)
+{
+	u8 num = MPP_NUM(config);
+
+	if (MPP_SEL(config) == PMU) {
+		/* enable PMU on MPP */
+		writel(readl(MPP_PMU_GENERAL_CTRL) | (1 << num),
+		       MPP_PMU_GENERAL_CTRL);
+		/* disable gpio capabilities */
+		orion_gpio_set_valid(num, 0);
+	} else {
+		/* disable PMU on MPP */
+		writel(readl(MPP_PMU_GENERAL_CTRL) & ~(1 << num),
+		       MPP_PMU_GENERAL_CTRL);
+		/* configure MPP */
+		dove_mpp_std_set(config);
+	}
+}
+
+/*
+ * MPP groups on MPP4_CTRL have different register layout
+ * and allow GPIO or special function only
+ */
+static void dove_mpp4_set(u16 config)
+{
+	u32 reg = readl(MPP4_CTRL);
+	u32 mask;
+	u8  n, nmin, nmax;
+	int gpio;
+
+	switch (MPP_NUM(config)) {
+	case MPP_CAMERA:
+		mask = MPP4_CAMERA_GPIO_SEL;
+		nmin = MPP_CAMERA;
+		nmax = MPP_CAMERA_MAX;
+		break;
+	case MPP_SDIO0:
+		mask = MPP4_SDIO0_GPIO_SEL;
+		nmin = MPP_SDIO0;
+		nmax = MPP_SDIO0_MAX;
+		break;
+	case MPP_SDIO1:
+		mask = MPP4_SDIO1_GPIO_SEL;
+		nmin = MPP_SDIO1;
+		nmax = MPP_SDIO1_MAX;
+		break;
+	case MPP_SPI:
+		mask = MPP4_SPI_GPIO_SEL;
+		nmin = MPP_SPI;
+		nmax = MPP_SPI_MAX;
+		break;
+	case MPP_UART1:
+		mask = MPP4_UART1_GPIO_SEL;
+		nmin = MPP_UART1;
+		nmax = MPP_UART1_MAX;
+		break;
+	default:
+		return;
+	}
+
+	reg &= ~mask;
+	if (MPP_SEL(config))
+		reg |= mask;
+	writel(reg, MPP4_CTRL);
+
+	/* configure gpio capabilities */
+	gpio = 0;
+	if (MPP_GPIO(config))
+		gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+	for (n = nmin; n <= nmax; n++)
+		orion_gpio_set_valid(n, gpio);
+}
+
+/*
+ * MPP_GENERAL_CTRL allows GPIO on NAND pins
+ */
+static void dove_mpp_nand_set(u16 config)
+{
+	u32 reg = readl(MPP_GENERAL_CTRL);
+	u8 n;
+	int gpio;
+
+	reg &= ~MPPG_NAND_GPIO_SEL;
+	if (config == MPP_NAND_GPO)
+		reg |= MPPG_NAND_GPIO_SEL;
+	writel(reg, MPP_GENERAL_CTRL);
+
+	/* configure gpio capabilities */
+	gpio = (config == MPP_NAND_GPO) ? GPIO_OUTPUT_OK : 0;
+	for (n = MPP_NAND; n <= MPP_NAND_MAX; n++)
+		orion_gpio_set_valid(n, gpio);
+}
+
+/*
+ * Dedicated audio1 pins can carry i2s, spdif, ssp or twsi
+ * and gpio in various combinations
+ */
+#define AUDIO1_TWSI	(1 << 0)
+#define AUDIO1_SPDIFO	(1 << 1)
+#define AUDIO1_SSP	(1 << 2)
+#define AUDIO1_GPIO	(1 << 3)
+
+static void dove_mpp_audio1_set(u16 config)
+{
+	u32 mpp4  = readl(MPP4_CTRL);
+	u32 sspc1 = readl(SSP_CONFIG_STATUS_1);
+	u32 gmpp  = readl(MPP_GENERAL_CTRL);
+	u32 gcfg2 = readl(GENERAL_CONFIG_2);
+	u8 n, sel = MPP_SEL(config);
+	int gpio;
+
+	gcfg2 &= ~GENERAL_TWSI_OPTION3_SEL;
+	gmpp &= ~MPPG_AUDIO1_SPDIFO_GPIO_SEL;
+	sspc1 &= ~SSP_SSP_ON_AUDIO1;
+	mpp4 &= ~MPP4_AUDIO1_GPIO_SEL;
+	if (sel & AUDIO1_TWSI)
+		gcfg2 |= GENERAL_TWSI_OPTION3_SEL;
+	if (sel & AUDIO1_SPDIFO)
+		gmpp |= MPPG_AUDIO1_SPDIFO_GPIO_SEL;
+	if (sel & AUDIO1_SSP)
+		sspc1 |= SSP_SSP_ON_AUDIO1;
+	if (sel & AUDIO1_GPIO)
+		mpp4 |= MPP4_AUDIO1_GPIO_SEL;
+
+	writel(mpp4, MPP4_CTRL);
+	writel(sspc1, SSP_CONFIG_STATUS_1);
+	writel(gmpp, MPP_GENERAL_CTRL);
+	writel(gcfg2, GENERAL_CONFIG_2);
+
+	/* gpio allows gpio on all audio1 mpp pins */
+	gpio = 0;
+	if (config == MPP_AUDIO1_GPIO)
+		gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+
+	for (n = MPP_AUDIO1; n <= MPP_AUDIO1_MAX; n++)
+		orion_gpio_set_valid(n, gpio);
+
+	switch (config) {
+	/* spdifo and twsi allow gpio on mpp[52:55] */
+	case MPP_AUDIO1_SPDIFO:
+	case MPP_AUDIO1_TWSI:
+		orion_gpio_set_valid(52, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(53, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(54, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(55, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		break;
+	/* i2s and ssp allow gpio on mpp[56:57] */
+	case MPP_AUDIO1_I2S:
+	case MPP_AUDIO1_SSP:
+		orion_gpio_set_valid(56, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(57, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		break;
+	}
+}
+
+/*
+ * MPP PMU switches audio0 pins to ac97 or i2s0
+ */
+static void dove_mpp_audio0_set(u16 config)
+{
+	/* switch i2s or ac97 to audio0 */
+	u32 reg = readl(MPP_PMU_GENERAL_CTRL);
+
+	reg &= ~PMUG_AUDIO0_AC97_SEL;
+	if (config == MPP_AUDIO0_AC97)
+		reg |= PMUG_AUDIO0_AC97_SEL;
+	writel(reg, MPP_PMU_GENERAL_CTRL);
+}
+
+/*
+ * TWSI has 3 optional pin sets that can be switched during runtime
+ */
+static void dove_mpp_twsi_set(u16 config)
+{
+	u32 gcfg1 = readl(GENERAL_CONFIG_1);
+	u32 gcfg2 = readl(GENERAL_CONFIG_2);
+
+	gcfg1 &= ~GENERAL_TWSI_MUXEN_OPTION1;
+	gcfg2 &= ~(GENERAL_TWSI_MUXEN_OPTION2 | GENERAL_TWSI_MUXEN_OPTION3);
+
+	switch (config) {
+	case MPP_TWSI_OPTION1:
+		gcfg1 |= GENERAL_TWSI_MUXEN_OPTION1;
+		break;
+	case MPP_TWSI_OPTION2:
+		gcfg2 |= GENERAL_TWSI_MUXEN_OPTION2;
+		break;
+	case MPP_TWSI_OPTION3:
+		gcfg2 |= GENERAL_TWSI_MUXEN_OPTION3;
+		break;
+	}
+
+	writel(gcfg1, GENERAL_CONFIG_1);
+	writel(gcfg2, GENERAL_CONFIG_2);
+}
+
+void dove_mpp_conf(u16 *mpp_list)
+{
+	while (*mpp_list) {
+		u8 num = MPP_NUM(*mpp_list);
+
+		if (num <= MPP_PMU_MAX)
+			dove_mpp_pmu_set(*mpp_list);
+		else if (num <= MPP_STD_MAX)
+			dove_mpp_std_set(*mpp_list);
+		else {
+			switch (num) {
+			case MPP_CAMERA:
+			case MPP_SDIO0:
+			case MPP_SDIO1:
+			case MPP_SPI:
+			case MPP_UART1:
+				dove_mpp4_set(*mpp_list);
+				break;
+			case MPP_NAND:
+				dove_mpp_nand_set(*mpp_list);
+				break;
+			case MPP_AUDIO0:
+				dove_mpp_audio0_set(*mpp_list);
+				break;
+			case MPP_AUDIO1:
+				dove_mpp_audio1_set(*mpp_list);
+				break;
+			case MPP_TWSI:
+				dove_mpp_twsi_set(*mpp_list);
+				break;
+			}
+		}
+		mpp_list++;
+	}
+}
diff --git a/arch/arm/cpu/armv7/dove/timer.c b/arch/arm/cpu/armv7/dove/timer.c
new file mode 100644
index 0000000..3be9b78
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/timer.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Dove SoC timer
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dove.h>
+
+#define UBOOT_CNTR	0	/* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct dovetmr_val {
+	u32 reload;	/* Timer reload reg */
+	u32 val;	/* Timer value reg */
+};
+
+/* Timer registers */
+struct dovetmr_registers {
+	u32 ctrl;	/* Timer control reg */
+	u32 pad[3];
+	struct dovetmr_val tmr[2];
+	u32 wdt_reload;
+	u32 wdt_val;
+};
+
+struct dovetmr_registers *dovetmr_regs =
+	(struct dovetmr_registers *)DOVE_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG			&dovetmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum)	&dovetmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum)		&dovetmr_regs->tmr[tmrnum].val
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS		0
+#define TRG_ARM_TIMER_REL_MASK		0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS		0
+#define TVR_ARM_TIMER_MASK		0xffffffff
+#define TVR_ARM_TIMER_MAX		0xffffffff
+#define TIMER_LOAD_VAL			0xffffffff
+
+#define READ_TIMER			(readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
+					 (CONFIG_SYS_TCLK / 1000))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER;
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec +
+			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	uint current;
+	ulong delayticks;
+
+	current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
+	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+	if (current < delayticks) {
+		delayticks -= current;
+		do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current);
+		do {} while ((TIMER_LOAD_VAL - delayticks) <
+			     readl(CNTMR_VAL_REG(UBOOT_CNTR)));
+	} else {
+		do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
+			     (current - delayticks));
+	}
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+	unsigned int cntmrctrl;
+
+	/* load value into timer */
+	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+	/* enable timer in auto reload mode */
+	cntmrctrl = readl(CNTMR_CTRL_REG);
+	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+	writel(cntmrctrl, CNTMR_CTRL_REG);
+
+	/* init the timestamp and lastdec value */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/armv7/dove/usb.c b/arch/arm/cpu/armv7/dove/usb.c
new file mode 100644
index 0000000..1b932db
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/usb.c
@@ -0,0 +1,101 @@
+/*
+ * Marvell Dove SoC USB PHY init
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+
+/* Dove USB2.0 PHY registers */
+#define USB20_POWER_CTRL		((base) + 0x400)
+#define USB20_PHY_PLL_CTRL		((base) + 0x410)
+#define  PHY_PLL_VCO_RECALIBRATE	(1 << 21)
+#define USB20_PHY_TX_CTRL		((base) + 0x420)
+#define  PHY_TX_HS_STRESS_CTRL		(1 << 31)
+#define  PHY_TX_BLOCK_EN		(1 << 21)
+#define  PHY_TX_IMP_CAL_VTH(x)		(x << 14)
+#define  PHY_TX_IMP_CAL_VTH_MASK	PHY_TX_IMP_CAL_VTH(0x7)
+#define  PHY_TX_RCAL_START		(1 << 12)
+#define  PHY_TX_LOWVDD_EN		(1 << 11)
+#define USB20_PHY_RX_CTRL		((base) + 0x430)
+#define  PHY_RX_EDGE_DET(x)		(x << 26)
+#define  PHY_RX_EDGE_DET_MASK		PHY_RX_EDGE_DET(0x3)
+#define  PHY_RX_CDR_FASTLOCK_EN		(1 << 21)
+#define  PHY_RX_SQ_LENGTH(x)		(x << 15)
+#define  PHY_RX_SQ_LENGTH_MASK		PHY_RX_SQ_LENGTH(0x3)
+#define  PHY_RX_SQ_THRESH(x)		(x << 4)
+#define  PHY_RX_SQ_THRESH_MASK		PHY_RX_SQ_THRESH(0xf)
+#define  PHY_RX_LPF_COEFF(x)		(x << 2)
+#define  PHY_RX_LPF_COEFF_MASK		PHY_RX_LPF_COEFF(0x3)
+#define USB20_PHY_IVREF_CTRL		((base) + 0x440)
+#define  PHY_IVREF_TXVDD12(x)		(x << 8)
+#define  PHY_IVREF_TXVDD12_MASK		PHY_IVREF_TXVDD12(0x3)
+#define USB20_PHY_TESTGRP_CTRL		((base) + 0x450)
+#define  PHY_TESTGRP_SQ_RST		(1 << 15)
+
+void dove_ehci_phy_init(int port)
+{
+	u32 base = (port == 0) ? DOVE_USB20_0_BASE : DOVE_USB20_1_BASE;
+	u32 reg;
+
+	/* USB PHY PLL control */
+	reg = readl(USB20_PHY_PLL_CTRL);
+	writel(reg | PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
+	udelay(100);
+	writel(reg & ~PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
+
+	/* USB PHY Tx control */
+	reg = readl(USB20_PHY_TX_CTRL);
+	reg &= ~PHY_TX_IMP_CAL_VTH_MASK;
+	reg |= PHY_TX_IMP_CAL_VTH(0x5);
+	reg |= PHY_TX_LOWVDD_EN;
+	reg |= PHY_TX_RCAL_START;
+	reg |= PHY_TX_BLOCK_EN;
+	reg |= PHY_TX_HS_STRESS_CTRL;
+	writel(reg, USB20_PHY_TX_CTRL);
+	udelay(100);
+	writel(reg & ~PHY_TX_RCAL_START, USB20_PHY_TX_CTRL);
+
+	/* USB PHY RX control */
+	reg = readl(USB20_PHY_RX_CTRL);
+	reg &= ~(PHY_RX_LPF_COEFF_MASK | PHY_RX_SQ_THRESH_MASK |
+		 PHY_RX_SQ_LENGTH_MASK | PHY_RX_EDGE_DET_MASK);
+	reg |= PHY_RX_LPF_COEFF(0x1);
+	reg |= PHY_RX_SQ_THRESH(0xc);
+	reg |= PHY_RX_SQ_LENGTH(0x1);
+	reg |= PHY_RX_EDGE_DET(0x0);
+	reg &= ~PHY_RX_CDR_FASTLOCK_EN;
+	writel(reg, USB20_PHY_RX_CTRL);
+
+	/* USB PHY IVREF control */
+	reg = readl(USB20_PHY_IVREF_CTRL);
+	reg &= ~PHY_IVREF_TXVDD12_MASK;
+	reg |= PHY_IVREF_TXVDD12(0x3);
+	writel(reg, USB20_PHY_IVREF_CTRL);
+
+	/* USB PHY TEST GROUP control */
+	reg = readl(USB20_PHY_TESTGRP_CTRL);
+	reg &= ~PHY_TESTGRP_SQ_RST;
+	writel(reg, USB20_PHY_TESTGRP_CTRL);
+}
diff --git a/arch/arm/include/asm/arch-dove/config.h b/arch/arm/include/asm/arch-dove/config.h
new file mode 100644
index 0000000..2d94a48
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/config.h
@@ -0,0 +1,153 @@
+/*
+ * Marvell SoC config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_CONFIG_H
+#define _DOVE_CONFIG_H
+
+#include <asm/arch/dove.h>
+
+#define CONFIG_ARMV7			/* Basic Architecture */
+#define CONFIG_DOVE			/* SOC Family Name */
+#define CONFIG_SHEEVA_88SV581		/* CPU Core subversion */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+				/* default Dcache Line length for Dove */
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#define CONFIG_SYS_DCACHE_OFF		/* Disable DCache by default */
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Dove has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#define CONFIG_I2C_MVTWSI_BASE	DOVE_TWSI_BASE
+#define MV_UART_CONSOLE_BASE	DOVE_UART0_BASE
+#define MV_SATA_BASE		DOVE_SATA_BASE
+#define MV_SATA_PORT0_OFFSET	DOVE_SATA_PORT0_OFFSET
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD		1
+#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL		1
+#endif
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI			1
+#define CONFIG_ORION_SPI		1
+#define ORION_SPI_BASE			DOVE_SPI_BASE
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS		0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS		0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ		25000000
+#endif
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_PHYLIB
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SDHCI
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_SDHCI
+#define CONFIG_DOVE_SDHCI	/* Enable Dove SDHCI controller driver */
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS
+#define CONFIG_SYS_MMC_MAX_DEVICE	2
+#endif
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * IDE Support on SATA ports
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#ifndef CONFIG_SOFT_I2C
+#define CONFIG_I2C_MVTWSI
+#endif
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#endif /* _DOVE_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-dove/cpu.h b/arch/arm/include/asm/arch-dove/cpu.h
new file mode 100644
index 0000000..718dd59
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/cpu.h
@@ -0,0 +1,204 @@
+/*
+ * Marvell Dove SoC CPU
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVECPU_H
+#define _DOVECPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define DOVECPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+			| (attr << 8) | (dove_winctrl_calcsize(size) << 16))
+
+#define DOVEGBE_PORT_SERIAL_CONTROL1_REG	(DOVE_EGIGA_BASE + 0x44c)
+#define DOVE_REG_PCIE_DEVID			(DOVE_REG_PCIE0_BASE + 0x00)
+#define DOVE_REG_PCIE_REVID			(DOVE_REG_PCIE0_BASE + 0x08)
+#define DOVE_REG_SYSRST_CNT			(DOVE_MPP_BASE + 0x50)
+#define SYSRST_CNT_1SEC_VAL			(25*1000000)
+#define DOVE_REG_MPP_OUT_DRV_REG		(DOVE_MPP_BASE + 0xE0)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+};
+
+enum dovecpu_winen {
+	DOVECPU_WIN_DISABLE,
+	DOVECPU_WIN_ENABLE
+};
+
+enum dovecpu_target {
+	DOVECPU_TARGET_DRAM = 0x0,
+	DOVECPU_TARGET_SASRAM = 0x3,
+	DOVECPU_TARGET_NAND = 0xc,
+	DOVECPU_TARGET_PMURAM = 0xd,
+	DOVECPU_TARGET_PCIE0 = 0x4,
+	DOVECPU_TARGET_PCIE1 = 0x8,
+	DOVECPU_TARGET_SPI = 0x1,
+	DOVECPU_TARGET_BOOTROM = 0x1,
+};
+
+enum dovecpu_attrib {
+	DOVECPU_ATTR_DRAM = 0x00,
+	DOVECPU_ATTR_SASRAM = 0x00,
+	DOVECPU_ATTR_NAND = 0x00,
+	DOVECPU_ATTR_PMURAM = 0x00,
+	DOVECPU_ATTR_PCIE_IO = 0xe0,
+	DOVECPU_ATTR_PCIE_MEM = 0xe8,
+	DOVECPU_ATTR_SPI0 = 0xfe,
+	DOVECPU_ATTR_SPI1 = 0xfb,
+	DOVECPU_ATTR_BOOTROM = 0xfd,
+};
+
+enum dovecpu_part {
+	DOVECPU_PART_SHEEVA = 0x581,
+};
+
+enum dovesoc_devid {
+	DOVESOC_DEVID_F6781 = 0x6781,
+	DOVESOC_DEVID_AP510 = 0x0510,
+};
+
+enum dovesoc_revid {
+	DOVESOC_REVID_Z0 = 0,
+	DOVESOC_REVID_Z1 = 1,
+	DOVESOC_REVID_Y0 = 2,
+	DOVESOC_REVID_Y1 = 3,
+	DOVESOC_REVID_X0 = 4,
+	DOVESOC_REVID_A0 = 6,
+	DOVESOC_REVID_A1 = 7,
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define DOVE_DEFADR_PCIE0_MEM		0xe0000000
+#define DOVE_DEFADR_PCIE0_IO		0xf2000000
+#define DOVE_DEFADR_PCIE0_IO_REMAP	0x00000000
+#define DOVE_DEFADR_PCIE1_MEM		0xe8000000
+#define DOVE_DEFADR_PCIE1_IO		0xf2100000
+#define DOVE_DEFADR_PCIE1_IO_REMAP	0x00100000
+#define DOVE_DEFADR_SASRAM		0xc8000000
+#define DOVE_DEFADR_BOOTROM		0xf8000000
+#define DOVE_DEFADR_PMURAM		0xf0000000
+
+/*
+ * ARM CPUID register
+ */
+#define ARM_ID_REVISION_OFFSET	0
+#define ARM_ID_REVISION_MASK	0xf
+#define ARM_ID_PARTNUM_OFFSET	4
+#define ARM_ID_PARTNUM_MASK	0xfff
+#define ARM_ID_ARCH_OFFSET	16
+#define ARM_ID_ARCH_MASK	0xf
+#define ARM_ID_VAR_OFFSET	20
+#define ARM_ID_VAR_MASK		0xf
+#define ARM_ID_ASCII_OFFSET	24
+#define ARM_ID_ASCII_MASK	0xff
+
+/*
+ * read feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+	unsigned int val;
+	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
+			(val) : : "cc");
+	return val;
+}
+
+/*
+ * write feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
+			(val) : "cc");
+	isb();
+}
+
+/*
+ * Downstream Bridge Registers
+ */
+struct dovewin_registers {
+	u32 ctrl;
+	u32 base;
+	u32 remap_lo;
+	u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ */
+struct dovecpu_registers {
+	u32 config;		/* 0x20100 */
+	u32 ctrl_stat;		/* 0x20104 */
+	u32 rstoutn_mask;	/* 0x20108 */
+	u32 sys_soft_rst;	/* 0x2010C */
+	u32 bridge_cause_irq;	/* 0x20110 */
+	u32 bridge_mask_irq;	/* 0x20114 */
+	u32 pad1;
+	u32 pmu_ctrl;		/* 0x2011c */
+};
+
+/*
+ * GPIO 0/1 Registers
+ * GPIO 2 Registers (no datain/irq)
+ */
+struct dovegpio_registers {
+	u32 dout;
+	u32 oe;
+	u32 blink_en;
+	u32 din_pol;
+	u32 din;
+	u32 irq_cause;
+	u32 irq_mask;
+	u32 irq_level;
+};
+
+struct dove_gpio_init {
+	u32 val0;
+	u32 val1;
+	u32 val2;
+	u32 oe0_n;
+	u32 oe1_n;
+	u32 oe2_n;
+};
+
+/*
+ * functions
+ */
+void reset_cpu(unsigned long ignored);
+unsigned char get_random_hex(void);
+u32 dove_dram_start(enum memory_bank bank);
+u32 dove_dram_size(enum memory_bank bank);
+int dove_config_adr_windows(void);
+void dove_init_gpio(struct dove_gpio_init *);
+unsigned int dove_winctrl_calcsize(unsigned int sizeval);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _DOVECPU_H */
diff --git a/arch/arm/include/asm/arch-dove/dove.h b/arch/arm/include/asm/arch-dove/dove.h
new file mode 100644
index 0000000..da5011b
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/dove.h
@@ -0,0 +1,93 @@
+/*
+ * Marvell Dove SoC register offsets and config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_H
+#define _DOVE_H
+
+/* Dove TCLK is fixed to 166MHz */
+#define CONFIG_SYS_TCLK			166666667
+
+/* SOC specific definitions */
+#define DOVE_PREMAP_REGS_PHYS_BASE	0xd0000000
+#define DOVE_PREMAP_INT_REGS_BASE_ADDR  (DOVE_PREMAP_REGS_PHYS_BASE + 0x20080)
+#define DOVE_PREMAP_MC_DECODE_REG       (DOVE_PREMAP_REGS_PHYS_BASE + 0x800010)
+
+#define DOVE_SB_REGS_PHYS_BASE		0xf1000000
+#define DOVE_NB_REGS_PHYS_BASE		0xf1800000
+#define DOVE_REGISTER(x)		(DOVE_SB_REGS_PHYS_BASE + x)
+
+#define DOVE_AXI_CTRL_REG		(DOVE_REGISTER(0xd0224))
+#define DOVE_CPU_CTRL_REG		(DOVE_REGISTER(0xd025c))
+#define DOVE_MC_CTRL_REG		(DOVE_REGISTER(0xd0260))
+#define DOVE_MC_DECODE_REG		(DOVE_REGISTER(0x800010))
+
+#define DOVE_SPI_BASE			(DOVE_REGISTER(0x10600))
+#define DOVE_TWSI_BASE			(DOVE_REGISTER(0x11000))
+#define DOVE_UART0_BASE			(DOVE_REGISTER(0x12000))
+#define DOVE_UART1_BASE			(DOVE_REGISTER(0x12100))
+#define DOVE_UART2_BASE			(DOVE_REGISTER(0x12200))
+#define DOVE_UART3_BASE			(DOVE_REGISTER(0x12300))
+#define DOVE_CPU_WIN_BASE		(DOVE_REGISTER(0x20000))
+#define DOVE_CPU_REG_BASE		(DOVE_REGISTER(0x20100))
+#define DOVE_TIMER_BASE			(DOVE_REGISTER(0x20300))
+#define DOVE_REG_PCIE0_BASE		(DOVE_REGISTER(0x40000))
+#define DOVE_REG_PCIE1_BASE		(DOVE_REGISTER(0x80000))
+#define DOVE_USB20_0_BASE		(DOVE_REGISTER(0x50000))
+#define DOVE_USB20_1_BASE		(DOVE_REGISTER(0x51000))
+#define DOVE_EGIGA_BASE			(DOVE_REGISTER(0x72000))
+#define DOVE_SDIO1_BASE			(DOVE_REGISTER(0x90000))
+#define DOVE_SDIO0_BASE			(DOVE_REGISTER(0x92000))
+#define DOVE_CAMERA_BASE		(DOVE_REGISTER(0x94000))
+#define DOVE_SATA_BASE			(DOVE_REGISTER(0xa0000))
+#define DOVE_NANDF_BASE			(DOVE_REGISTER(0xc0000))
+#define DOVE_PMU_BASE			(DOVE_REGISTER(0xd0000))
+#define DOVE_MPP_BASE			(DOVE_REGISTER(0xd0200))
+#define DOVE_GPIO0_BASE			(DOVE_REGISTER(0xd0400))
+#define DOVE_GPIO1_BASE			(DOVE_REGISTER(0xd0420))
+#define DOVE_RTC_BASE			(DOVE_REGISTER(0xd8500))
+#define DOVE_AC97_BASE			(DOVE_REGISTER(0xe0000))
+#define DOVE_PDMA_BASE			(DOVE_REGISTER(0xe4000))
+#define DOVE_GPIO2_BASE			(DOVE_REGISTER(0xe8400))
+#define DOVE_SSP_BASE			(DOVE_REGISTER(0xec000))
+
+/* Dove Sata controller has one port */
+#define DOVE_SATA_PORT0_OFFSET		0x2000
+
+/* Dove GbE controller has one port */
+#define MAX_MVGBE_DEVS			1
+#define MVGBE0_BASE			DOVE_EGIGA_BASE
+
+/* Dove USB Host controller */
+#define MVUSB0_BASE			DOVE_USB20_0_BASE
+#define MVUSB0_CPU_ATTR_DRAM_CS0	DOVECPU_ATTR_DRAM
+#define MVUSB0_CPU_ATTR_DRAM_CS1	DOVECPU_ATTR_DRAM
+#define MVUSB0_CPU_ATTR_DRAM_CS2	DOVECPU_WIN_DISABLE
+#define MVUSB0_CPU_ATTR_DRAM_CS3	DOVECPU_WIN_DISABLE
+
+/* Dove CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA		DOVECPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE		DOVECPU_WIN_ENABLE
+#define MVCPU_WIN_DISABLE		DOVECPU_WIN_DISABLE
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/gpio.h b/arch/arm/include/asm/arch-dove/gpio.h
new file mode 100644
index 0000000..71bef8e
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Marvell Dove SoC gpio
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __DOVE_GPIO_H
+#define __DOVE_GPIO_H
+
+#include <orion_gpio.h>
+
+#define GPIO_MAX		70
+#define GPIO_BASE(pin)		(((pin) >= 64) ? DOVE_GPIO2_BASE : \
+				 ((pin) >= 32) ? DOVE_GPIO1_BASE : \
+				 DOVE_GPIO0_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/mpp.h b/arch/arm/include/asm/arch-dove/mpp.h
new file mode 100644
index 0000000..1279ac2
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/mpp.h
@@ -0,0 +1,283 @@
+/*
+ * Marvell Dove SoC pinmux
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_MPP_H
+#define _DOVE_MPP_H
+
+#define DOVE_GPI	(1 << 0)
+#define DOVE_GPO	(1 << 1)
+#define DOVE_GPIO	(DOVE_GPO | DOVE_GPI)
+
+#define MPP(_num, _sel, _gpio) (			 \
+	/* MPP number */	((_num) & 0xff) |	 \
+	/* MPP select value */	(((_sel) & 0x1f) << 8) | \
+	/* is gpio config */	((!!(_gpio)) << 15))
+
+/* MPP0-15 allow PMU function */
+#define MPP_PMU_MAX		15
+#define PMU			(0x10)
+/* MPP0-23 have standard mpp register layout */
+#define MPP_STD_MAX		23
+
+#define MPP0			0
+#define MPP0_GPIO		MPP(0, 0x0, 1)
+#define MPP0_UART2_RTS		MPP(0, 0x2, 0)
+#define MPP0_SDIO0_CD		MPP(0, 0x3, 0)
+#define MPP0_LCD0_PWM		MPP(0, 0xf, 0)
+#define MPP0_PMU		MPP(0, PMU, 0)
+
+#define MPP1			1
+#define MPP1_GPIO		MPP(1, 0x0, 1)
+#define MPP1_UART2_CTS		MPP(1, 0x2, 0)
+#define MPP1_SDIO0_WP		MPP(1, 0x3, 0)
+#define MPP1_LCD1_PWM		MPP(1, 0xf, 0)
+#define MPP1_PMU		MPP(1, PMU, 0)
+
+#define MPP2			2
+#define MPP2_GPIO		MPP(2, 0x0, 1)
+#define MPP2_SATA_PRSNT		MPP(2, 0x1, 0)
+#define MPP2_UART2_TXD		MPP(2, 0x2, 0)
+#define MPP2_SDIO0_BUSPWR	MPP(2, 0x3, 0)
+#define MPP2_UART1_RTS		MPP(2, 0x4, 0)
+#define MPP2_PMU		MPP(2, PMU, 0)
+
+#define MPP3			3
+#define MPP3_GPIO		MPP(3, 0x0, 1)
+#define MPP3_SATA_ACT		MPP(3, 0x1, 0)
+#define MPP3_UART2_RXD		MPP(3, 0x2, 0)
+#define MPP3_SDIO0_LEDCTRL	MPP(3, 0x3, 0)
+#define MPP3_UART1_CTS		MPP(3, 0x4, 0)
+#define MPP3_LCD_SPI_CS1	MPP(3, 0xf, 0)
+#define MPP3_PMU		MPP(3, PMU, 0)
+
+#define MPP4			4
+#define MPP4_GPIO		MPP(4, 0x0, 1)
+#define MPP4_UART3_RTS		MPP(4, 0x2, 0)
+#define MPP4_SDIO1_CD		MPP(4, 0x3, 0)
+#define MPP4_SPI1_MISO		MPP(4, 0x4, 0)
+#define MPP4_PMU		MPP(4, PMU, 0)
+
+#define MPP5			5
+#define MPP5_GPIO		MPP(5, 0x0, 1)
+#define MPP5_UART3_CTS		MPP(5, 0x2, 0)
+#define MPP5_SDIO1_WP		MPP(5, 0x3, 0)
+#define MPP5_SPI1_CS		MPP(5, 0x4, 0)
+#define MPP5_PMU		MPP(5, PMU, 0)
+
+#define MPP6			6
+#define MPP6_GPIO		MPP(6, 0x0, 1)
+#define MPP6_UART3_TXD		MPP(6, 0x2, 0)
+#define MPP6_SDIO1_BUSPWR	MPP(6, 0x3, 0)
+#define MPP6_SPI1_MOSI		MPP(6, 0x4, 0)
+#define MPP6_PMU		MPP(6, PMU, 0)
+
+#define MPP7			7
+#define MPP7_GPIO		MPP(7, 0x0, 1)
+#define MPP7_UART3_RXD		MPP(7, 0x2, 0)
+#define MPP7_SDIO1_LEDCTRL	MPP(7, 0x3, 0)
+#define MPP7_SPI1_SCK		MPP(7, 0x4, 0)
+#define MPP7_PMU		MPP(7, PMU, 0)
+
+#define MPP8			8
+#define MPP8_GPIO		MPP(8, 0x0, 1)
+#define MPP8_WATCHDOG_RSTOUT	MPP(8, 0x1, 0)
+#define MPP8_PMU		MPP(8, PMU, 0)
+
+#define MPP9			9
+#define MPP9_GPIO		MPP(9, 0x0, 1)
+#define MPP9_PEX1_CLKREQ	MPP(9, 0x5, 0)
+#define MPP9_PMU		MPP(9, PMU, 0)
+
+#define MPP10			10
+#define MPP10_GPIO		MPP(10, 0x0, 1)
+#define MPP10_SSP_SCLK		MPP(10, 0x5, 0)
+#define MPP10_PMU		MPP(10, PMU, 0)
+
+#define MPP11			11
+#define MPP11_GPIO		MPP(11, 0x0, 1)
+#define MPP11_SATA_PRSNT	MPP(11, 0x1, 0)
+#define MPP11_SATA_ACT		MPP(11, 0x2, 0)
+#define MPP11_SDIO0_LEDCTRL	MPP(11, 0x3, 0)
+#define MPP11_SDIO1_LEDCTRL	MPP(11, 0x4, 0)
+#define MPP11_PEX0_CLKREQ	MPP(11, 0x5, 0)
+#define MPP11_PMU		MPP(11, PMU, 0)
+
+#define MPP12			12
+#define MPP12_GPIO		MPP(12, 0x0, 1)
+#define MPP12_SATA_ACT		MPP(12, 0x1, 0)
+#define MPP12_UART2_RTS		MPP(12, 0x2, 0)
+#define MPP12_AUDIO0_EXTCLK	MPP(12, 0x3, 0)
+#define MPP12_SDIO1_CD		MPP(12, 0x4, 0)
+#define MPP12_PMU		MPP(12, PMU, 0)
+
+#define MPP13			13
+#define MPP13_GPIO		MPP(13, 0x0, 1)
+#define MPP13_UART2_CTS		MPP(13, 0x2, 0)
+#define MPP13_AUDIO1_EXTCLK	MPP(13, 0x3, 0)
+#define MPP13_SDIO1_WP		MPP(13, 0x4, 0)
+#define MPP13_SSP_EXTCLK	MPP(13, 0x5, 0)
+#define MPP13_PMU		MPP(13, PMU, 0)
+
+#define MPP14			14
+#define MPP14_GPIO		MPP(14, 0x0, 1)
+#define MPP14_UART2_TXD		MPP(14, 0x2, 0)
+#define MPP14_SDIO1_BUSPWR	MPP(14, 0x4, 0)
+#define MPP14_SSP_TXD		MPP(14, 0x5, 0)
+#define MPP14_PMU		MPP(14, PMU, 0)
+
+#define MPP15			15
+#define MPP15_GPIO		MPP(15, 0x0, 1)
+#define MPP15_UART2_RXD		MPP(15, 0x2, 0)
+#define MPP15_SDIO1_LEDCTRL	MPP(15, 0x4, 0)
+#define MPP15_SSP_SFRM		MPP(15, 0x5, 0)
+#define MPP15_PMU		MPP(15, PMU, 0)
+
+#define MPP16			16
+#define MPP16_GPIO		MPP(16, 0x0, 1)
+#define MPP16_UART3_RTS		MPP(16, 0x2, 0)
+#define MPP16_SDIO0_CD		MPP(16, 0x3, 0)
+#define MPP16_LCD_SPI_CS1	MPP(16, 0x4, 0)
+#define MPP16_AC97_SDI1		MPP(16, 0x5, 0)
+
+#define MPP17			17
+#define MPP17_GPIO		MPP(17, 0x0, 1)
+#define MPP17_AC97_SYSCLKO	MPP(17, 0x1, 0)
+#define MPP17_UART3_CTS		MPP(17, 0x2, 0)
+#define MPP17_SDIO0_WP		MPP(17, 0x3, 0)
+#define MPP17_TWSI_SDA		MPP(17, 0x4, 0)
+#define MPP17_AC97_SDI2		MPP(17, 0x5, 0)
+
+#define MPP18			18
+#define MPP18_GPIO		MPP(18, 0x0, 1)
+#define MPP18_UART3_TXD		MPP(18, 0x2, 0)
+#define MPP18_SDIO0_BUSPWR	MPP(18, 0x3, 0)
+#define MPP18_LCD0_PWM		MPP(18, 0x4, 0)
+#define MPP18_AC97_SDI3		MPP(18, 0x5, 0)
+
+#define MPP19			19
+#define MPP19_GPIO		MPP(19, 0x0, 1)
+#define MPP19_UART3_RXD		MPP(19, 0x2, 0)
+#define MPP19_SDIO0_LEDCTRL	MPP(19, 0x3, 0)
+#define MPP19_TWSI_SCK		MPP(19, 0x4, 0)
+
+#define MPP20			20
+#define MPP20_GPIO		MPP(20, 0x0, 1)
+#define MPP20_AC97_SYSCLKO	MPP(20, 0x1, 0)
+#define MPP20_LCD_SPI_MISO	MPP(20, 0x2, 0)
+#define MPP20_SDIO1_CD		MPP(20, 0x3, 0)
+#define MPP20_SDIO0_CD		MPP(20, 0x5, 0)
+#define MPP20_SPI1_MISO		MPP(20, 0x6, 0)
+
+#define MPP21			21
+#define MPP21_GPIO		MPP(21, 0x0, 1)
+#define MPP21_UART1_RTS		MPP(21, 0x1, 0)
+#define MPP21_LCD_SPI_CS0	MPP(21, 0x2, 0)
+#define MPP21_SDIO1_WP		MPP(21, 0x3, 0)
+#define MPP21_SSP_SFRM		MPP(21, 0x4, 0)
+#define MPP21_SDIO0_WP		MPP(21, 0x5, 0)
+#define MPP21_SPI1_CS		MPP(21, 0x6, 0)
+
+#define MPP22			22
+#define MPP22_GPIO		MPP(22, 0x0, 1)
+#define MPP22_UART1_CTS		MPP(22, 0x1, 0)
+#define MPP22_LCD_SPI_MOSI	MPP(22, 0x2, 0)
+#define MPP22_SDIO1_BUSPWR	MPP(22, 0x3, 0)
+#define MPP22_SSP_TXD		MPP(22, 0x4, 0)
+#define MPP22_SDIO0_BUSPWR	MPP(22, 0x5, 0)
+#define MPP22_SPI1_MOSI		MPP(22, 0x6, 0)
+
+#define MPP23			23
+#define MPP23_GPIO		MPP(23, 0x0, 1)
+#define MPP23_LCD_SPI_SCK	MPP(23, 0x2, 0)
+#define MPP23_SDIO1_LEDCTRL	MPP(23, 0x3, 0)
+#define MPP23_SSP_SCLK		MPP(23, 0x4, 0)
+#define MPP23_SDIO0_LEDCTRL	MPP(23, 0x5, 0)
+#define MPP23_SPI1_SCK		MPP(23, 0x6, 0)
+
+/* MPP_CAMERA = MPP[24:39] */
+#define MPP_CAMERA		24
+#define MPP_CAMERA_CAMERA	MPP(24, 0x0, 0)
+#define MPP_CAMERA_GPIO		MPP(24, 0x1, 1)
+#define MPP_CAMERA_MAX		39
+
+/* MPP_SDIO0 = MPP[40:45] */
+#define MPP_SDIO0		40
+#define MPP_SDIO0_SDIO		MPP(40, 0x0, 0)
+#define MPP_SDIO0_GPIO		MPP(40, 0x1, 1)
+#define MPP_SDIO0_MAX		45
+
+/* MPP_SDIO1 = MPP[46:51] */
+#define MPP_SDIO1		46
+#define MPP_SDIO1_SDIO		MPP(46, 0x0, 0)
+#define MPP_SDIO1_GPIO		MPP(46, 0x1, 1)
+#define MPP_SDIO1_MAX		51
+
+/* MPP_AUDIO1 = MPP[52:57] */
+#define MPP_AUDIO1		52
+#define MPP_AUDIO1_I2S_SPDIFO	MPP(52, 0x0, 0)
+#define MPP_AUDIO1_I2S		MPP(52, 0x2, 0)
+#define MPP_AUDIO1_SPDIFO	MPP(52, 0x8, 0)
+#define MPP_AUDIO1_GPIO		MPP(52, 0xa, 1)
+#define MPP_AUDIO1_TWSI		MPP(52, 0xb, 0)
+#define MPP_AUDIO1_SSP_SPDIFO	MPP(52, 0xc, 0)
+#define MPP_AUDIO1_SSP		MPP(52, 0xe, 0)
+#define MPP_AUDIO1_SSP_TWSI	MPP(52, 0xf, 0)
+#define MPP_AUDIO1_MAX		57
+
+/* MPP_SPI = MPP[58:61] */
+#define MPP_SPI			58
+#define MPP_SPI_SPI		MPP(58, 0x0, 0)
+#define MPP_SPI_GPIO		MPP(58, 0x1, 1)
+#define MPP_SPI_MAX		61
+
+/* MPP_UART1 = MPP[62:63] */
+#define MPP_UART1		62
+#define MPP_UART1_UART1		MPP(62, 0x0, 0)
+#define MPP_UART1_GPIO		MPP(62, 0x1, 1)
+#define MPP_UART1_MAX		63
+
+/* MPP_NAND = MPP[64:71] */
+#define MPP_NAND		64
+#define MPP_NAND_NAND		MPP(64, 0x0, 0)
+#define MPP_NAND_GPO		MPP(64, 0x1, 1)
+#define MPP_NAND_MAX		71
+
+/* MPP_AUDIO0 = Internal AC97/I2S mux for audio0 pins */
+#define MPP_AUDIO0		72
+#define MPP_AUDIO0_I2S		MPP(72, 0x0, 0)
+#define MPP_AUDIO0_AC97		MPP(72, 0x1, 0)
+
+/* MPP_TWSI = Internal TWSI option mux */
+#define MPP_TWSI		73
+#define MPP_TWSI_NONE		MPP(73, 0x0, 0)
+#define MPP_TWSI_OPTION1	MPP(73, 0x1, 0)
+#define MPP_TWSI_OPTION2	MPP(73, 0x2, 0)
+#define MPP_TWSI_OPTION3	MPP(73, 0x3, 0)
+
+#define MPP_MAX			MPP_TWSI
+
+u8 dove_mpp_get_gpio_caps(u8 num);
+void dove_mpp_conf(u16 *mpp_list);
+
+#endif
-- 
1.7.10.4

[U-Boot] [PATCH v2 02/10] GPIO: add gpio driver for Orion SoCs

[Sebastian Hesselbarth]

This adds a gpio driver for Marvell Orion SoCs, i.e. orion5x, kirkwood,
dove. This is based on kw_gpio but as gpio capabilities depend heavily
on the mpp configuration for dove, it allows to set gpi/gpo capabilities
from mpp. This should be compatible with the current kw_gpio and porting
mpp of kirkwood and orion5x is appreciated.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/gpio/Makefile     |    1 +
 drivers/gpio/orion_gpio.c |  167 +++++++++++++++++++++++++++++++++++++++++++++
 include/orion_gpio.h      |   64 +++++++++++++++++
 3 files changed, 232 insertions(+)
 create mode 100644 drivers/gpio/orion_gpio.c
 create mode 100644 include/orion_gpio.h

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index d50ac3b..6fc163b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 LIB 	:= $(obj)libgpio.o
 
 COBJS-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
+COBJS-$(CONFIG_ORION_GPIO)	+= orion_gpio.o
 COBJS-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
 COBJS-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
 COBJS-$(CONFIG_MARVELL_MFP)	+= mvmfp.o
diff --git a/drivers/gpio/orion_gpio.c b/drivers/gpio/orion_gpio.c
new file mode 100644
index 0000000..209354d
--- /dev/null
+++ b/drivers/gpio/orion_gpio.c
@@ -0,0 +1,167 @@
+/*
+ * Marvell Orion SoC GPIO handling.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed orion_gpiochip struct and kernel level irq handling.
+ * Dieter Kiermaier dk-arm-linux at gmx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <orion_gpio.h>
+
+static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
+static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
+
+void __set_direction(unsigned pin, int input)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_IO_CONF(base));
+	if (input)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_IO_CONF(base));
+
+	u = readl(GPIO_IO_CONF(base));
+}
+
+void __set_level(unsigned pin, int high)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_OUT(base));
+	if (high)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_OUT(base));
+}
+
+void __set_blinking(unsigned pin, int blink)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_BLINK_EN(base));
+	if (blink)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_BLINK_EN(base));
+}
+
+int orion_gpio_is_valid(unsigned pin, int mode)
+{
+	if (pin < GPIO_MAX) {
+		if ((mode & GPIO_INPUT_OK) &&
+		    !test_bit(pin, gpio_valid_input))
+			goto err_out;
+
+		if ((mode & GPIO_OUTPUT_OK) &&
+		    !test_bit(pin, gpio_valid_output))
+			goto err_out;
+		return 0;
+	}
+
+err_out:
+	printf("%s: invalid GPIO %d/%d\n", __func__, pin, GPIO_MAX);
+	return 1;
+}
+
+void orion_gpio_set_valid(unsigned pin, int mode)
+{
+	if (mode & GPIO_INPUT_OK)
+		__set_bit(pin, gpio_valid_input);
+	else
+		__clear_bit(pin, gpio_valid_input);
+	if (mode & GPIO_OUTPUT_OK)
+		__set_bit(pin, gpio_valid_output);
+	else
+		__clear_bit(pin, gpio_valid_output);
+}
+
+/*
+ * GENERIC_GPIO primitives.
+ */
+int orion_gpio_direction_input(unsigned pin)
+{
+	if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) != 0)
+		return 1;
+
+	/* Configure GPIO direction. */
+	__set_direction(pin, 1);
+
+	return 0;
+}
+
+int orion_gpio_direction_output(unsigned pin, int value)
+{
+	if (orion_gpio_is_valid(pin, GPIO_OUTPUT_OK) != 0) {
+		printf("%s: invalid GPIO %d\n", __func__, pin);
+		return 1;
+	}
+
+	__set_blinking(pin, 0);
+
+	/* Configure GPIO output value. */
+	__set_level(pin, value);
+
+	/* Configure GPIO direction. */
+	__set_direction(pin, 0);
+
+	return 0;
+}
+
+int orion_gpio_get_value(unsigned pin)
+{
+	u32 base = GPIO_BASE(pin);
+	int val;
+
+	if (readl(GPIO_IO_CONF(base)) & (1 << (pin & 31)))
+		val = readl(GPIO_DATA_IN(base)) ^ readl(GPIO_IN_POL(base));
+	else
+		val = readl(GPIO_OUT(base));
+
+	return (val >> (pin & 31)) & 1;
+}
+
+void orion_gpio_set_value(unsigned pin, int value)
+{
+	/* Configure GPIO output value. */
+	__set_level(pin, value);
+}
+
+void orion_gpio_set_blink(unsigned pin, int blink)
+{
+	/* Set output value to zero. */
+	__set_level(pin, 0);
+
+	/* Set blinking. */
+	__set_blinking(pin, blink);
+}
diff --git a/include/orion_gpio.h b/include/orion_gpio.h
new file mode 100644
index 0000000..ba67068
--- /dev/null
+++ b/include/orion_gpio.h
@@ -0,0 +1,64 @@
+/*
+ * Marvell Orion SoCs common gpio
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ORION_GPIO_H
+#define __ORION_GPIO_H
+
+/*
+ * SoC-specific gpio.h defines
+ * GPIO_MAX and GPIO_BASE(pin) macro
+ */
+
+#define GPIO_INPUT_OK		(1 << 0)
+#define GPIO_OUTPUT_OK		(1 << 1)
+#define GPIO_LOW		0
+#define GPIO_HIGH		1
+
+/* got from kernel include/linux/bitops.h */
+#define BITS_PER_BYTE 8
+#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+
+#define GPIO_OUT(base)		((base) + 0x00)
+#define GPIO_IO_CONF(base)	((base) + 0x04)
+#define GPIO_BLINK_EN(base)	((base) + 0x08)
+#define GPIO_IN_POL(base)	((base) + 0x0c)
+#define GPIO_DATA_IN(base)	((base) + 0x10)
+#define GPIO_EDGE_CAUSE(base)	((base) + 0x14)
+#define GPIO_EDGE_MASK(base)	((base) + 0x18)
+#define GPIO_LEVEL_MASK(base)	((base) + 0x1c)
+
+/*
+ * Orion-specific GPIO API
+ */
+
+void orion_gpio_set_valid(unsigned pin, int mode);
+int orion_gpio_is_valid(unsigned pin, int mode);
+int orion_gpio_direction_input(unsigned pin);
+int orion_gpio_direction_output(unsigned pin, int value);
+int orion_gpio_get_value(unsigned pin);
+void orion_gpio_set_value(unsigned pin, int value);
+void orion_gpio_set_blink(unsigned pin, int blink);
+void orion_gpio_set_unused(unsigned pin);
+
+#endif
-- 
1.7.10.4

[U-Boot] [PATCH v2 03/10] MMC: sdhci: Add support for dove sdhci

[Sebastian Hesselbarth]

This adds a driver for the sdhci controller found on Dove SoCs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/mmc/Makefile     |    1 +
 drivers/mmc/dove_sdhci.c |  101 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 102 insertions(+)
 create mode 100644 drivers/mmc/dove_sdhci.c

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 65791aa..f7c731f 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -31,6 +31,7 @@ endif
 
 COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+COBJS-$(CONFIG_DOVE_SDHCI) += dove_sdhci.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
 COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
diff --git a/drivers/mmc/dove_sdhci.c b/drivers/mmc/dove_sdhci.c
new file mode 100644
index 0000000..ac15fd7
--- /dev/null
+++ b/drivers/mmc/dove_sdhci.c
@@ -0,0 +1,101 @@
+/*
+ *
+ * Marvell Dove SDHCI driver
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on linux drivers/mmc/host/sdhci-dove.c
+ * by: Saeed Bishara <saeed@marvell.com>
+ *     Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/arch/dove.h>
+
+static u16 dove_sdhci_readw(struct sdhci_host *host, int reg)
+{
+	u16 ret;
+
+	switch (reg) {
+	case SDHCI_HOST_VERSION:
+	case SDHCI_SLOT_INT_STATUS:
+		/* those registers don't exist */
+		return 0;
+	default:
+		ret = readw(host->ioaddr + reg);
+	}
+
+	return ret;
+}
+
+static u32 dove_sdhci_readl(struct sdhci_host *host, int reg)
+{
+	u32 ret;
+
+	switch (reg) {
+	case SDHCI_CAPABILITIES:
+		ret = readl(host->ioaddr + reg);
+		/* Mask the support for 3.0V */
+		ret &= ~SDHCI_CAN_VDD_300;
+		break;
+	default:
+		ret = readl(host->ioaddr + reg);
+	}
+
+	return ret;
+}
+
+static struct sdhci_ops dove_sdhci_ops = {
+	.read_w	= dove_sdhci_readw,
+	.read_l	= dove_sdhci_readl,
+};
+
+static struct sdhci_host hosts[2] = {
+	{
+		.name = "Dove SDHCI0",
+		.ioaddr = (void *)DOVE_SDIO0_BASE,
+	},
+	{
+		.name = "Dove SDHCI1",
+		.ioaddr = (void *)DOVE_SDIO1_BASE,
+	},
+};
+
+int dove_sdhci_init(int num)
+{
+	struct sdhci_host *host;
+
+	if (num < 0 || num > 1)
+		return 1;
+
+	host = &hosts[num];
+
+	if (host->version)
+		return 1;
+
+	host->quirks =
+		SDHCI_QUIRK_NO_HISPD_BIT |
+		SDHCI_QUIRK_BROKEN_R1B |
+		SDHCI_QUIRK_32BIT_DMA_ADDR;
+	host->version = SDHCI_SPEC_200;
+	host->ops = &dove_sdhci_ops;
+
+	add_sdhci(host, 50000000, 4000000);
+	return 0;
+}
-- 
1.7.10.4

[U-Boot] [PATCH v2 04/10] SPI: Add Orion SPI driver

[Sebastian Hesselbarth]

This adds an SPI driver found on Marvell Orion SoCs. This driver is
taken from kirkwood_spi but removes mpp configuration as dove has
dedicated spi pins. To have a common driver for orion5x, kirkwood,
and dove, mpp configuration should be handled in some cpu/board-specific
setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/spi/Makefile    |    1 +
 drivers/spi/orion_spi.c |  217 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 218 insertions(+)
 create mode 100644 drivers/spi/orion_spi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index f0b82c6..679ba61 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
 COBJS-$(CONFIG_CF_SPI) += cf_spi.o
 COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
 COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_ORION_SPI) += orion_spi.o
 COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
 COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
diff --git a/drivers/spi/orion_spi.c b/drivers/spi/orion_spi.c
new file mode 100644
index 0000000..8a50531
--- /dev/null
+++ b/drivers/spi/orion_spi.c
@@ -0,0 +1,217 @@
+/*
+ * Marvell Orion SoCs common spi driver
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * based on kirkwood_spi.c written by
+ *  Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/arch/config.h>
+
+/* SPI Registers on orion SOC */
+struct orionspi_registers {
+	u32 ctrl;	/* 0x00 */
+	u32 cfg;	/* 0x04 */
+	u32 dout;	/* 0x08 */
+	u32 din;	/* 0x0c */
+	u32 irq_cause;	/* 0x10 */
+	u32 irq_mask;	/* 0x14 */
+};
+
+#define ORIONSPI_CLKPRESCL_MASK	0x1f
+#define ORIONSPI_CLKPRESCL_MIN	0x12
+#define ORIONSPI_CSN_ACT	1 /* Activates serial memory interface */
+#define ORIONSPI_SMEMRDY	(1 << 1) /* SerMem Data xfer ready */
+#define ORIONSPI_IRQUNMASK	1 /* unmask SPI interrupt */
+#define ORIONSPI_IRQMASK	0 /* mask SPI interrupt */
+#define ORIONSPI_SMEMRDIRQ	1 /* SerMem data xfer ready irq */
+#define ORIONSPI_XFERLEN_1BYTE	0
+#define ORIONSPI_XFERLEN_2BYTE	(1 << 5)
+#define ORIONSPI_XFERLEN_MASK	(1 << 5)
+#define ORIONSPI_ADRLEN_1BYTE	0
+#define ORIONSPI_ADRLEN_2BYTE	(1 << 8)
+#define ORIONSPI_ADRLEN_3BYTE	(2 << 8)
+#define ORIONSPI_ADRLEN_4BYTE	(3 << 8)
+#define ORIONSPI_ADRLEN_MASK	(3 << 8)
+#define ORIONSPI_TIMEOUT	10000
+
+static struct orionspi_registers *spireg =
+	(struct orionspi_registers *)ORION_SPI_BASE;
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				unsigned int max_hz, unsigned int mode)
+{
+	struct spi_slave *slave;
+	u32 data;
+	u32 kwspi_mpp_config[] = { 0, 0 };
+
+	if (!spi_cs_is_valid(bus, cs))
+		return NULL;
+
+	slave = malloc(sizeof(struct spi_slave));
+	if (!slave)
+		return NULL;
+
+	slave->bus = bus;
+	slave->cs = cs;
+
+	writel(~ORIONSPI_CSN_ACT | ORIONSPI_SMEMRDY, &spireg->ctrl);
+
+	/* calculate spi clock prescaller using max_hz */
+	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
+	data = data < ORIONSPI_CLKPRESCL_MIN ? ORIONSPI_CLKPRESCL_MIN : data;
+	data = data > ORIONSPI_CLKPRESCL_MASK ? ORIONSPI_CLKPRESCL_MASK : data;
+
+	/* program spi clock prescaller using max_hz */
+	writel(ORIONSPI_ADRLEN_3BYTE | data, &spireg->cfg);
+	debug("data = 0x%08x\n", data);
+
+	writel(ORIONSPI_SMEMRDIRQ, &spireg->irq_cause);
+	writel(ORIONSPI_IRQMASK, &spireg->irq_mask);
+
+	return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	free(slave);
+}
+
+#if defined(CONFIG_SYS_KW_SPI_MPP)
+u32 spi_mpp_backup[4];
+#endif
+
+__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return board_spi_claim_bus(slave);
+}
+
+__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
+{
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	board_spi_release_bus(slave);
+}
+
+#ifndef CONFIG_SPI_CS_IS_VALID
+/*
+ * you can define this function board specific
+ * define above CONFIG in board specific config file and
+ * provide the function in board specific src file
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return (bus == 0 && (cs == 0 || cs == 1));
+}
+#endif
+
+void spi_init(void)
+{
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	writel(readl(&spireg->ctrl) | ORIONSPI_IRQUNMASK, &spireg->ctrl);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	writel(readl(&spireg->ctrl) & ORIONSPI_IRQMASK, &spireg->ctrl);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	unsigned int tmpdout, tmpdin;
+	int tm, isread = 0;
+
+	debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
+	      slave->bus, slave->cs, dout, din, bitlen);
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	/*
+	 * handle data in 8-bit chunks
+	 * TBD: 2byte xfer mode to be enabled
+	 */
+	writel(((readl(&spireg->cfg) & ~ORIONSPI_XFERLEN_MASK) |
+		ORIONSPI_XFERLEN_1BYTE), &spireg->cfg);
+
+	while (bitlen > 4) {
+		debug("loopstart bitlen %d\n", bitlen);
+		tmpdout = 0;
+
+		/* Shift data so it's msb-justified */
+		if (dout)
+			tmpdout = *(u32 *) dout & 0x0ff;
+
+		writel(~ORIONSPI_SMEMRDIRQ, &spireg->irq_cause);
+		writel(tmpdout, &spireg->dout);	/* Write the data out */
+		debug("*** spi_xfer: ... %08x written, bitlen %d\n",
+		      tmpdout, bitlen);
+
+		/*
+		 * Wait for SPI transmit to get out
+		 * or time out (1 second = 1000 ms)
+		 * The NE event must be read and cleared first
+		 */
+		for (tm = 0, isread = 0; tm < ORIONSPI_TIMEOUT; ++tm) {
+			if (readl(&spireg->irq_cause) & ORIONSPI_SMEMRDIRQ) {
+				isread = 1;
+				tmpdin = readl(&spireg->din);
+				debug
+					("spi_xfer: din %p..%08x read\n",
+					din, tmpdin);
+
+				if (din) {
+					*((u8 *) din) = (u8) tmpdin;
+					din += 1;
+				}
+				if (dout)
+					dout += 1;
+				bitlen -= 8;
+			}
+			if (isread)
+				break;
+		}
+		if (tm >= ORIONSPI_TIMEOUT)
+			printf("*** spi_xfer: Time out during SPI transfer\n");
+
+		debug("loopend bitlen %d\n", bitlen);
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	return 0;
+}
-- 
1.7.10.4

[U-Boot] [PATCH v2 05/10] block: mvsata: add dove include

[Sebastian Hesselbarth]

Dove SoC also uses mvsata, therefore add a SoC specific include to
allow to reuse the mvsata ide driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/block/mvsata_ide.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index a88d0f7..9918f80 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -29,6 +29,8 @@
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 /* SATA port registers */
-- 
1.7.10.4

[U-Boot] [PATCH v2 06/10] NET: phy: add 88E1310 PHY initialization

[Sebastian Hesselbarth]

This adds PHY initialization for Marvell Alaska 88E1310 PHY.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/net/phy/marvell.c |   48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index e51e799..e920212 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -89,6 +89,12 @@
 
 #define MIIM_88E1149_PHY_PAGE	29
 
+/* 88E1310 PHY defines */
+#define MIIM_88E1310_PHY_LED_CTRL	16
+#define MIIM_88E1310_PHY_IRQ_EN		18
+#define MIIM_88E1310_PHY_RGMII_CTRL	21
+#define MIIM_88E1310_PHY_PAGE		22
+
 /* Marvell 88E1011S */
 static int m88e1011s_config(struct phy_device *phydev)
 {
@@ -394,6 +400,37 @@ static int m88e1149_config(struct phy_device *phydev)
 	return 0;
 }
 
+/* Marvell 88E1310 */
+static int m88e1310_config(struct phy_device *phydev)
+{
+	u16 reg;
+
+	/* LED link and activity */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
+	reg = (reg & ~0xf) | 0x1;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
+
+	/* Set LED2/INT to INT mode, low active */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
+	reg = (reg & 0x77ff) | 0x0880;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
+
+	/* Set RGMII delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
+	reg |= 0x0030;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
+
+	/* Ensure to return to page 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
+
+	genphy_config_aneg(phydev);
+	phy_reset(phydev);
+
+	return 0;
+}
 
 static struct phy_driver M88E1011S_driver = {
 	.name = "Marvell 88E1011S",
@@ -455,8 +492,19 @@ static struct phy_driver M88E1149S_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver M88E1310_driver = {
+	.name = "Marvell 88E1310",
+	.uid = 0x01410e90,
+	.mask = 0xffffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &m88e1310_config,
+	.startup = &m88e1011s_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 int phy_marvell_init(void)
 {
+	phy_register(&M88E1310_driver);
 	phy_register(&M88E1149S_driver);
 	phy_register(&M88E1145_driver);
 	phy_register(&M88E1121R_driver);
-- 
1.7.10.4

[U-Boot] [PATCH v2 07/10] NET: mvgbe: add phylib support

[Sebastian Hesselbarth]

This add phylib support to the Marvell GBE driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/net/mvgbe.c |   68 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 64 insertions(+), 4 deletions(-)

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 47bf27c..192c989 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MV_PHY_ADR_REQUEST 0xee
 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 /*
  * smi_reg_read - miiphy_read callback function.
  *
@@ -184,6 +184,24 @@ static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
 }
 #endif
 
+#if defined(CONFIG_PHYLIB)
+int mvgbe_phy_read(struct mii_dev *bus, int phyAddr, int devAddr, int regAddr)
+{
+	u16 data;
+	int ret;
+	ret = smi_reg_read(bus->name, phyAddr, regAddr, &data);
+	if (ret)
+		return ret;
+	return data;
+}
+
+int mvgbe_phy_write(struct mii_dev *bus, int phyAddr, int devAddr, int regAddr,
+	u16 data)
+{
+	return smi_reg_write(bus->name, phyAddr, regAddr, data);
+}
+#endif
+
 /* Stop and checks all queues */
 static void stop_queue(u32 * qreg)
 {
@@ -467,8 +485,9 @@ static int mvgbe_init(struct eth_device *dev)
 	/* Enable port Rx. */
 	MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
 
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
-	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))   \
+	&& !defined(CONFIG_PHYLIB)		       \
+	&& defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 	/* Wait up to 5s for the link status */
 	for (i = 0; i < 5; i++) {
 		u16 phyadr;
@@ -647,6 +666,45 @@ static int mvgbe_recv(struct eth_device *dev)
 	return 0;
 }
 
+#if defined(CONFIG_PHYLIB)
+int mvgbe_phylib_init(struct eth_device *dev, int phyid)
+{
+	struct mii_dev *bus;
+	struct phy_device *phydev;
+	int ret;
+
+	bus = mdio_alloc();
+	if (!bus) {
+		printf("mdio_alloc failed\n");
+		return -ENOMEM;
+	}
+	bus->read = mvgbe_phy_read;
+	bus->write = mvgbe_phy_write;
+	sprintf(bus->name, dev->name);
+
+	ret = mdio_register(bus);
+	if (ret) {
+		printf("mdio_register failed\n");
+		free(bus);
+		return -ENOMEM;
+	}
+
+	/* Set phy address of the port */
+	mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
+
+	phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		printf("phy_connect failed\n");
+		return -ENODEV;
+	}
+
+	phy_config(phydev);
+	phy_startup(phydev);
+
+	return 0;
+}
+#endif
+
 int mvgbe_initialize(bd_t *bis)
 {
 	struct mvgbe_device *dmvgbe;
@@ -729,7 +787,9 @@ error1:
 
 		eth_register(dev);
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_PHYLIB)
+		mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
+#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 		miiphy_register(dev->name, smi_reg_read, smi_reg_write);
 		/* Set phy address of the port */
 		miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
-- 
1.7.10.4

[U-Boot] [PATCH v2 08/10] NET: mvgbe: add support for Dove

[Sebastian Hesselbarth]

Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/net/mvgbe.c |    2 ++
 drivers/net/mvgbe.h |    7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 192c989..590ea0b 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -43,6 +43,8 @@
 #include <asm/arch/kirkwood.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 #include "mvgbe.h"
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index d8a5429..7f5d98f 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -308,10 +308,17 @@
 #define EBAR_TARGET_GUNIT			0x00000007
 
 /* Window attrib */
+#if defined(CONFIG_DOVE)
+#define EBAR_DRAM_CS0				0x00000000
+#define EBAR_DRAM_CS1				0x00000000
+#define EBAR_DRAM_CS2				0x00000000
+#define EBAR_DRAM_CS3				0x00000000
+#else
 #define EBAR_DRAM_CS0				0x00000E00
 #define EBAR_DRAM_CS1				0x00000D00
 #define EBAR_DRAM_CS2				0x00000B00
 #define EBAR_DRAM_CS3				0x00000700
+#endif
 
 /* DRAM Target interface */
 #define EBAR_DRAM_NO_CACHE_COHERENCY		0x00000000
-- 
1.7.10.4

[U-Boot] [PATCH v2 09/10] Boards: Add support for SolidRun CuBox

[Sebastian Hesselbarth]

With latest support for Marvell Dove SoC, add the SolidRun CuBox as
the very first board with that SoC.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- add MAINTAINERS entry and fix a typo

Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 MAINTAINERS                       |    4 +
 board/solidrun/cubox/Makefile     |   45 ++++++++++
 board/solidrun/cubox/cubox.c      |  141 ++++++++++++++++++++++++++++++
 board/solidrun/cubox/kwbimage.cfg |   76 ++++++++++++++++
 boards.cfg                        |    1 +
 include/configs/cubox.h           |  175 +++++++++++++++++++++++++++++++++++++
 6 files changed, 442 insertions(+)
 create mode 100644 board/solidrun/cubox/Makefile
 create mode 100644 board/solidrun/cubox/cubox.c
 create mode 100644 board/solidrun/cubox/kwbimage.cfg
 create mode 100644 include/configs/cubox.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c430574..d315cb6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -677,6 +677,10 @@ Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
 
 	dns325		ARM926EJS (Kirkwood SoC)
 
+Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+
+	cubox		ARM ARMV7 (Dove SoC)
+
 Vaibhav Hiremath <hvaibhav@ti.com>
 
 	am3517_evm	ARM ARMV7 (AM35x SoC)
diff --git a/board/solidrun/cubox/Makefile b/board/solidrun/cubox/Makefile
new file mode 100644
index 0000000..c771d72
--- /dev/null
+++ b/board/solidrun/cubox/Makefile
@@ -0,0 +1,45 @@
+#
+# SolidRun CuBox Makefile
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cubox.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/solidrun/cubox/cubox.c b/board/solidrun/cubox/cubox.c
new file mode 100644
index 0000000..70c016f
--- /dev/null
+++ b/board/solidrun/cubox/cubox.c
@@ -0,0 +1,141 @@
+/*
+ * SolidRun CuBox board support
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/mpp.h>
+#include <orion_gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u16 mpp_config[] = {
+	MPP0_GPIO,
+	MPP1_GPIO, /* USB power enable */
+	MPP2_GPIO, /* USB over-current indication */
+	MPP3_GPIO, /* micro button beneath eSATA port */
+	MPP4_GPIO,
+	MPP5_GPIO,
+	MPP6_GPIO,
+	MPP7_GPIO,
+
+	MPP8_GPIO,
+	MPP9_GPIO,
+	MPP10_GPIO,
+	MPP11_GPIO,
+	MPP12_GPIO, /* SDIO0 card detect */
+	MPP13_AUDIO1_EXTCLK, /* Si5351a audio clock output */
+	MPP14_GPIO,
+	MPP15_GPIO,
+
+	MPP16_GPIO,
+	MPP17_GPIO,
+	MPP18_GPIO, /* Red front LED */
+	MPP19_UART3_RXD, /* IR sensor */
+	MPP20_GPIO,
+	MPP21_GPIO,
+	MPP22_GPIO,
+	MPP23_GPIO,
+
+	MPP_CAMERA_GPIO,
+	MPP_SDIO0_SDIO, /* SDIO0 */
+	MPP_SDIO1_GPIO,
+	MPP_AUDIO1_I2S_SPDIFO, /* SPDIF and HDMI audio */
+	MPP_SPI_SPI, /* SPI */
+	MPP_UART1_GPIO,
+	MPP_NAND_GPO,
+
+	MPP_AUDIO0_I2S,
+	MPP_TWSI_OPTION1, /* TWSI on dedicated pins */
+	0 };
+
+int board_early_init_f(void)
+{
+	struct dove_gpio_init gpp = {
+		.val0  = 0x00010186,
+		.oe0_n = 0xffffffff,
+		.val1  = 0x018000c0,
+		.oe1_n = 0xffffffff,
+		.val2  = 0x00000000,
+		.oe2_n = 0xffffffff,
+	};
+
+	dove_init_gpio(&gpp);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = dove_dram_start(0) + 0x100;
+
+	/* configure mpp */
+	dove_mpp_conf(mpp_config);
+
+	/* usb power enable */
+	orion_gpio_direction_output(MPP1, GPIO_HIGH);
+
+	/* blink led */
+	orion_gpio_direction_output(MPP18, GPIO_HIGH);
+	orion_gpio_set_blink(MPP18, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_MMC
+int board_mmc_init(bd_t *bis)
+{
+	dove_sdhci_init(0);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_RESET_PHY_R
+void dove_eth_phy_init(char *name)
+{
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__func__);
+		return;
+	}
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("%s PHY initialized\n", name);
+}
+
+void reset_phy(void)
+{
+	dove_eth_phy_init("egiga0");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/solidrun/cubox/kwbimage.cfg b/board/solidrun/cubox/kwbimage.cfg
new file mode 100644
index 0000000..c3f1ad9
--- /dev/null
+++ b/board/solidrun/cubox/kwbimage.cfg
@@ -0,0 +1,76 @@
+#
+# Marvell BootROM config for SolidRun CuBox
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# SDRAM initalization
+DATA 0xd0800020 0x00022430	# SDRAM Configuration register 0
+DATA 0xd0800030 0x00022430	# SDRAM Configuration register 1
+DATA 0xd0800050 0x911500c3	# SDRAM Timing register 1
+DATA 0xd0800060 0x646602c4	# SDRAM Timing register 2
+DATA 0xd0800190 0xc2003053	# SDRAM Timing register 3
+DATA 0xd08001c0 0x34f4a187	# SDRAM Timing register 4
+DATA 0xd0800650 0x000f0121	# SDRAM Timing register 5
+DATA 0xd0800660 0x04040200	# SDRAM Timing register 6
+DATA 0xd0800080 0x00000000	# SDRAM Control register 1
+DATA 0xd0800090 0x00080000	# SDRAM Control register 2
+DATA 0xd08000f0 0xc0000000	# SDRAM Control register 3
+DATA 0xd08001a0 0x20c0c009	# SDRAM Control register 4
+DATA 0xd0800280 0x010e0202	# SDRAM Control register 5
+DATA 0xd0800760 0x00000000	# SDRAM Control register 6
+DATA 0xd0800770 0x0000000a	# SDRAM Control register 7
+DATA 0xd0800140 0x20004044	# SDRAM PHY control register 3
+DATA 0xd08001d0 0x133c2339	# SDRAM PHY control register 7
+DATA 0xd08001e0 0x07700330	# SDRAM PHY control register 8
+DATA 0xd08001f0 0x00000033	# SDRAM PHY control register 9
+DATA 0xd0800200 0x0011311c	# SDRAM PHY control register 10
+DATA 0xd0800210 0x00300000	# SDRAM PHY control register 11
+DATA 0xd0800240 0x80000000	# SDRAM PHY control register 14
+DATA 0xd0800510 0x010e0101	# SDRAM MCB control register 1
+DATA 0xd0800230 0x2028006a	# SDRAM PHY control register 13
+DATA 0xd0800e10 0x00280062	# SDRAM PHY DLL control registers 2
+DATA 0xd0800e20 0x00280062	# SDRAM PHY DLL control registers 3
+DATA 0xd0800e30 0x00280062	# SDRAM PHY DLL control registers 4
+
+# SDRAM memory map (2x512MB)
+DATA 0xd0800100 0x000d0001	# SDRAM Memory Address Map register 1
+DATA 0xd0800110 0x200d0001	# SDRAM Memory Address Map register 1
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/boards.cfg b/boards.cfg
index ca9b12b..1bd734b 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -289,6 +289,7 @@ whistler                     arm         armv7:arm720t whistler          nvidia
 colibri_t20_iris             arm         armv7:arm720t colibri_t20_iris  toradex        tegra20
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
 snowball                     arm         armv7       snowball               st-ericsson    u8500
+cubox                        arm         armv7       cubox               solidrun       dove
 kzm9g                        arm         armv7       kzm9g               kmc            rmobile
 armadillo-800eva             arm         armv7       armadillo-800eva    atmark-techno  rmobile
 zynq                         arm         armv7       zynq                xilinx         zynq
diff --git a/include/configs/cubox.h b/include/configs/cubox.h
new file mode 100644
index 0000000..88a2fda
--- /dev/null
+++ b/include/configs/cubox.h
@@ -0,0 +1,175 @@
+/*
+ * SolidRun CuBox config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_CUBOX_H
+#define _CONFIG_CUBOX_H
+#include <asm/sizes.h>
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\SolidRun CuBox"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MACH_SOLIDRUN_CUBOX	/* Machine type */
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_ORION_GPIO               /* Orion GPIO driver */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable u-boot API for standalone programs.
+ */
+#define CONFIG_API
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Commands configuration
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFT_PARTITION
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * redefine mv-common.h macros for armv7/cubox
+ */
+#undef CONFIG_SYS_PROMPT	/* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT	"CuBox> "	/* Command Prompt */
+
+/* There is no arch_misc_init on armv7 */
+#undef CONFIG_ARCH_MISC_INIT
+
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN	(4 * 1024 * 1024) /* 4MiB for malloc() */
+
+/*
+ *  Environment variables configurations
+ */
+#if defined(CONFIG_CMD_SF)
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SECT_SIZE		0x1000	/* 4k */
+#define CONFIG_ENV_SIZE			0x20000 /* 128k */
+#define CONFIG_ENV_OFFSET		0xc0000 /* env starts here */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+
+/*
+ * Default CuBox bootscript environment
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootscript=boot.scr\0"						\
+	"loadaddr=0x02000000\0"						\
+	"mmc_started=0\0"						\
+	"ide_started=0\0"						\
+	"usb_started=0\0"						\
+	"mtdparts=mtdparts=spi0.0:768k(u-boot)ro,128k(uboot_env),128k(fdt),-(empty)\0"	\
+	"ethaddr=00:50:43:15:17:17\0"
+
+#define CONFIG_BOOTCOMMAND						\
+	"for devn in usb mmc ide ; do "					\
+	"  for part in 0 1; do "					\
+	"    for dir  in / /boot/;do "					\
+	"      for fs in ext2 fat; do "					\
+	"        echo ===> Executing ${fs}load ${devn} 0:${part} ${loadaddr} ${dir}${bootscript};" \
+	"        if itest.s $devn -eq mmc; then"			\
+	"          if itest.s $mmc_started -ne 1; then"			\
+	"            mmcinfo; setenv mmc_started '1';fi;fi;"		\
+	"        if itest.s $devn -eq usb; then"			\
+	"          if itest.s $usb_started -ne 1; then"			\
+	"            usb start; setenv usb_started '1';fi;fi;"		\
+	"        if itest.s $devn -eq ide; then"			\
+	"          if itest.s $ide_started -ne 1; then"			\
+	"            ide reset; setenv ide_started '1';fi;fi;"		\
+	"        if ${fs}load ${devn} 0:${part} ${loadaddr} ${dir}${bootscript}; then" \
+	"          source ${loadaddr}; fi;"				\
+	"        if itest.s $devn -eq usb; then"			\
+	"          echo ===> Executing ${fs}load ${devn} 1:${part} ${loadaddr} ${dir}${bootscript};" \
+	"          if ${fs}load ${devn} 1:${part} ${loadaddr} ${dir}${bootscript}; then" \
+	"            source ${loadaddr}; fi;"				\
+	"        fi;"							\
+	"      done;"							\
+	"    done;"							\
+	"  done;"							\
+	"done;"								\
+	"tftp ${loadaddr} ${bootscript};"				\
+	"source ${loadaddr};"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1}	/* enable port 0 */
+#define CONFIG_PHY_BASE_ADR	1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
+#endif /* CONFIG_CMD_NET */
+
+#ifdef CONFIG_CMD_IDE
+#undef CONFIG_IDE_LED
+#undef CONFIG_SYS_IDE_MAXBUS
+#define CONFIG_SYS_IDE_MAXBUS		1
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_CUBOX_H */
-- 
1.7.10.4

[U-Boot] [PATCH v2 10/10] tools: Add support for Dove to kwboot

[Sebastian Hesselbarth]

On Dove kwboot can also be used to boot an u-boot image into RAM.
In contrast to Kirkwood, Dove does not support the UART boot mode
sequence but requires the UART boot mode to be selected through
strap pins. The SolidRun CuBox has a push button to allow uart
boot mode but fails on the boot sequence sent by kwboot.

This patch adds another cmdline option to allow to send a boot
image without the boot sequence and adds support for Dove.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- also update kwboot.1 manpage

Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 doc/kwboot.1   |   13 ++++++++++---
 tools/Makefile |    2 ++
 tools/kwboot.c |   44 ++++++++++++++++++++++++++++++++++++++++----
 3 files changed, 52 insertions(+), 7 deletions(-)

diff --git a/doc/kwboot.1 b/doc/kwboot.1
index ed08398..3e26acc 100644
--- a/doc/kwboot.1
+++ b/doc/kwboot.1
@@ -1,17 +1,18 @@
-.TH KWBOOT 1 "2012-05-19"
+.TH KWBOOT 1 "2012-12-02"
 
 .SH NAME
-kwboot \- Boot Marvell Kirkwood SoCs over a serial link.
+kwboot \- Boot Marvell Kirkwood/Dove SoCs over a serial link.
 .SH SYNOPSIS
 .B kwboot
 .RB [ "-b \fIimage\fP" ]
 .RB [ "-p" ]
 .RB [ "-t" ]
+.RB [ "-u" ]
 .RB [ "-B \fIbaudrate\fP" ]
 .RB \fITTY\fP
 .SH "DESCRIPTION"
 
-The \fBmkimage\fP program boots boards based on Marvell's Kirkwood
+The \fBmkimage\fP program boots boards based on Marvell's Kirkwood/Dove
 platform over their integrated UART. Boot image files will typically
 contain a second stage boot loader, such as U-Boot. The image file
 must conform to Marvell's BootROM firmware image format
@@ -68,6 +69,12 @@ If standard I/O streams connect to a console, this mode will terminate
 after receiving 'ctrl-\\' followed by 'c' from console input.
 
 .TP
+.BI "\-u"
+Disables the UART boot mode sequence for platforms that do not support
+it (e.g. Dove). Usually, the UART boot mode can be selected by pressing
+a push button on power-up.
+
+.TP
 .BI "\-B \fIbaudrate\fP"
 Adjust the baud rate on \fITTY\fP. Default rate is 115200.
 
diff --git a/tools/Makefile b/tools/Makefile
index 686840a..845384f 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -73,6 +73,7 @@ BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
 BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
 BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
 BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
+BIN_FILES-$(CONFIG_DOVE) += kwboot$(SFX)
 
 # Source files which exist outside the tools directory
 EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
@@ -104,6 +105,7 @@ NOPED_OBJ_FILES-y += os_support.o
 OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
 NOPED_OBJ_FILES-y += ublimage.o
 OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
+OBJ_FILES-$(CONFIG_DOVE) += kwboot.o
 
 # Don't build by default
 #ifeq ($(ARCH),ppc)
diff --git a/tools/kwboot.c b/tools/kwboot.c
index e773f01..199678a 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -293,6 +293,30 @@ kwboot_bootmsg(int tty, void *msg)
 }
 
 static int
+kwboot_bootmsg_uartmode(int tty)
+{
+	int rc;
+	char c;
+
+	kwboot_printv("Please reboot the target into UART boot mode...");
+
+	do {
+		rc = tcflush(tty, TCIOFLUSH);
+		if (rc)
+			break;
+
+		rc = kwboot_tty_recv(tty, &c, 1, KWBOOT_MSG_RSP_TIMEO);
+
+		kwboot_spinner();
+
+	} while (rc || c != NAK);
+
+	kwboot_printv("\n");
+
+	return rc;
+}
+
+static int
 kwboot_xm_makeblock(struct kwboot_block *block, const void *data,
 		    size_t size, int pnum)
 {
@@ -601,10 +625,11 @@ static void
 kwboot_usage(FILE *stream, char *progname)
 {
 	fprintf(stream,
-		"Usage: %s -b <image> [ -p ] [ -t ] "
+		"Usage: %s -b <image> [ -p ] [ -t ] [ -u ] "
 		"[-B <baud> ] <TTY>\n", progname);
 	fprintf(stream, "\n");
 	fprintf(stream, "  -b <image>: boot <image>\n");
+	fprintf(stream, "  -u: target requires UART boot mode (e.g. Dove)\n");
 	fprintf(stream, "  -p: patch <image> to type 0x69 (uart boot)\n");
 	fprintf(stream, "\n");
 	fprintf(stream, "  -t: mini terminal\n");
@@ -617,7 +642,7 @@ int
 main(int argc, char **argv)
 {
 	const char *ttypath, *imgpath;
-	int rv, rc, tty, term, prot, patch;
+	int rv, rc, tty, uartmode, term, prot, patch;
 	void *bootmsg;
 	void *img;
 	size_t size;
@@ -628,6 +653,7 @@ main(int argc, char **argv)
 	bootmsg = NULL;
 	imgpath = NULL;
 	img = NULL;
+	uartmode = 0;
 	term = 0;
 	patch = 0;
 	size = 0;
@@ -636,7 +662,7 @@ main(int argc, char **argv)
 	kwboot_verbose = isatty(STDOUT_FILENO);
 
 	do {
-		int c = getopt(argc, argv, "hb:ptB:");
+		int c = getopt(argc, argv, "hb:ptuB:");
 		if (c < 0)
 			break;
 
@@ -654,6 +680,10 @@ main(int argc, char **argv)
 			term = 1;
 			break;
 
+		case 'u':
+			uartmode = 1;
+			break;
+
 		case 'B':
 			speed = kwboot_tty_speed(atoi(optarg));
 			if (speed == -1)
@@ -702,7 +732,13 @@ main(int argc, char **argv)
 		}
 	}
 
-	if (bootmsg) {
+	if (uartmode) {
+		rc = kwboot_bootmsg_uartmode(tty);
+		if (rc) {
+			perror("bootmsg");
+			goto out;
+		}
+	} else if (bootmsg) {
 		rc = kwboot_bootmsg(tty, bootmsg);
 		if (rc) {
 			perror("bootmsg");
-- 
1.7.10.4

[U-Boot] [PATCH 10/10] tools: Add support for Dove to kwboot

[Daniel Stodden]

On Sun, 2012-12-02 at 20:15 +0100, Luka Perkov wrote:
> Hi Sebastian,
> 
> On Sun, Dec 02, 2012 at 03:36:22PM +0100, Sebastian Hesselbarth wrote:
> > On Dove kwboot can also be used to boot an u-boot image into RAM.
> > In contrast to Kirkwood, Dove does not support the UART boot mode
> > sequence but requires the UART boot mode to be selected through
> > strap pins. The SolidRun CuBox has a push button to allow uart
> > boot mode but fails on the boot sequence sent by kwboot.
> > 
> > This patch adds another cmdline option to allow to send a boot
> > image without the boot sequence and adds support for Dove.
> > 
> > Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> > ---
> > Cc: u-boot at lists.denx.de
> > Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> > Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> > Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> > Cc: Prafulla Wadaskar <prafulla@marvell.com>
> > Cc: Andy Fleming <afleming@gmail.com>
> > Cc: Joe Hershberger <joe.hershberger@gmail.com>
> > Cc: Daniel Stodden <daniel.stodden@gmail.com>
> > Cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
> > ---
> >  tools/Makefile |    2 ++
> >  tools/kwboot.c |   44 ++++++++++++++++++++++++++++++++++++++++----
> >  2 files changed, 42 insertions(+), 4 deletions(-)
> 
> Please update the documentation too (doc/kwboot.1).

Second that.

Hey Sebastian,

since the protocol remains the same, and just doesn't take a boot
message while polling, better to keep the bootmsg_call() intact and just
make the option parsing flip the message type?

The original BootROM had a couple more message, the tool just no
immediate use for that. Eventual options to change message type wasn't
unanticipated. Ok, no message at all was.

Sketchy patch attached for your consideration. Beware, I can't test it
right now.

Also, while I've got nothing against adding a flag for that, I'm partly
wondering whether this took a patch at all -- what's the target behavior
if you keep shooting it with the original boot message?

I would assume it would keep responding with NAKs. But doesn't?

Cheers,
Daniel 

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[U-Boot] [PATCH 10/10] tools: Add support for Dove to kwboot

[Sebastian Hesselbarth]

On 12/05/2012 11:15 PM, Daniel Stodden wrote:
> On Sun, 2012-12-02 at 20:15 +0100, Luka Perkov wrote:
>> On Sun, Dec 02, 2012 at 03:36:22PM +0100, Sebastian Hesselbarth wrote:
>>> On Dove kwboot can also be used to boot an u-boot image into RAM.
>>> In contrast to Kirkwood, Dove does not support the UART boot mode
>>> sequence but requires the UART boot mode to be selected through
>>> strap pins. The SolidRun CuBox has a push button to allow uart
>>> boot mode but fails on the boot sequence sent by kwboot.
> ...
> since the protocol remains the same, and just doesn't take a boot
> message while polling, better to keep the bootmsg_call() intact and just
> make the option parsing flip the message type?
>
> The original BootROM had a couple more message, the tool just no
> immediate use for that. Eventual options to change message type wasn't
> unanticipated. Ok, no message at all was.
>
> Sketchy patch attached for your consideration. Beware, I can't test it
> right now.

Hi Daniel,

I tried your patch and except that you forgot to add 'n' to the getopt
call, it works as expected.

> Also, while I've got nothing against adding a flag for that, I'm partly
> wondering whether this took a patch at all -- what's the target behavior
> if you keep shooting it with the original boot message?
>
> I would assume it would keep responding with NAKs. But doesn't?

I tried original kwboot and it failed, then I checked the DS for the boot
sequence and finally found out, that Dove doesn't support the "force into
UART boot mode" sequence. But your are right, if I reboot Dove into UART
boot mode it makes no difference if you send the sequence or not. It works
on both kwboot modes.

It just doesn't work if you are doing a normal boot of Dove, as it ignores
the sequence sent.

So finally, we have three options:
- leave kwboot as is and hope the user will know about Dove's inability to
use the boot sequence
- add a note to usage() and kwboot that Dove doen't like the sequence
- add an option to kwboot as you are proposing

Sebastian

[U-Boot] [PATCH 10/10] tools: Add support for Dove to kwboot

[Daniel Stodden]

On Thu, 2012-12-06 at 11:59 +0100, Sebastian Hesselbarth wrote:
> On 12/05/2012 11:15 PM, Daniel Stodden wrote:
> > On Sun, 2012-12-02 at 20:15 +0100, Luka Perkov wrote:
> >> On Sun, Dec 02, 2012 at 03:36:22PM +0100, Sebastian Hesselbarth wrote:
> >>> On Dove kwboot can also be used to boot an u-boot image into RAM.
> >>> In contrast to Kirkwood, Dove does not support the UART boot mode
> >>> sequence but requires the UART boot mode to be selected through
> >>> strap pins. The SolidRun CuBox has a push button to allow uart
> >>> boot mode but fails on the boot sequence sent by kwboot.
> > ...
> > since the protocol remains the same, and just doesn't take a boot
> > message while polling, better to keep the bootmsg_call() intact and just
> > make the option parsing flip the message type?
> >
> > The original BootROM had a couple more message, the tool just no
> > immediate use for that. Eventual options to change message type wasn't
> > unanticipated. Ok, no message at all was.
> >
> > Sketchy patch attached for your consideration. Beware, I can't test it
> > right now.
> 
> Hi Daniel,
> 
> I tried your patch and except that you forgot to add 'n' to the getopt
> call, it works as expected.

Thanks, mission accomplished :)

> > Also, while I've got nothing against adding a flag for that, I'm partly
> > wondering whether this took a patch at all -- what's the target behavior
> > if you keep shooting it with the original boot message?
> >
> > I would assume it would keep responding with NAKs. But doesn't?
> 
> I tried original kwboot and it failed, then I checked the DS for the boot
> sequence and finally found out, that Dove doesn't support the "force into
> UART boot mode" sequence. But your are right, if I reboot Dove into UART
> boot mode it makes no difference if you send the sequence or not. It works
> on both kwboot modes.
> 
> It just doesn't work if you are doing a normal boot of Dove, as it ignores
> the sequence sent.
> 
> So finally, we have three options:
> - leave kwboot as is and hope the user will know about Dove's inability to
> use the boot sequence
> - add a note to usage() and kwboot that Dove doen't like the sequence
> - add an option to kwboot as you are proposing

Okay, here's a deal.

We've got a bit of a backward compatibility problem anyway. Dave Purdy
was so kind to write up a summary of popular devices known working and
not working. That's mainly a matter of firmware revisions. [1]

 - Let's add a message selector, -m <foo> or so.

   Kirkwood specs list two types, let's make those -mdebug and -muart.

   If we add -m debug, maybe that even results in someone on the web
   being ultimately able to explain wth debug mode does :)

   Default is -m uart, that's what's going on right now.

 - We add -mnone for pin-selected uart boot mode.

 - Maybe a slightly less specific printv message.

 - But most importantly, we add a COMPATIBILITY section to the manpage,
   and explain the difference between core revisions there.

We could drop the none case. But then again, if the target isn't reset
yet, then not scribbling into getties and stuff where it's avoidable
might be preferred by those who can. So why not.

Could you try to read us the boot firmware revision you're running? It's
described under the link below. Not sure if it works on your platform
though.

Daniel

[1] http://forum.doozan.com/read.php?3,7852

[U-Boot] [PATCH 10/10] tools: Add support for Dove to kwboot

[Sebastian Hesselbarth]

On 12/06/2012 07:18 PM, Daniel Stodden wrote:
> On Thu, 2012-12-06 at 11:59 +0100, Sebastian Hesselbarth wrote:
>> So finally, we have three options:
>> - leave kwboot as is and hope the user will know about Dove's inability to
>> use the boot sequence
>> - add a note to usage() and kwboot that Dove doen't like the sequence
>> - add an option to kwboot as you are proposing
>
> Okay, here's a deal.
>
> We've got a bit of a backward compatibility problem anyway. Dave Purdy
> was so kind to write up a summary of popular devices known working and
> not working. That's mainly a matter of firmware revisions. [1]
>
>   - Let's add a message selector, -m<foo>  or so.
>
>     Kirkwood specs list two types, let's make those -mdebug and -muart.
>
>     If we add -m debug, maybe that even results in someone on the web
>     being ultimately able to explain wth debug mode does :)
>
>     Default is -m uart, that's what's going on right now.
>
>   - We add -mnone for pin-selected uart boot mode.
>
>   - Maybe a slightly less specific printv message.
>
>   - But most importantly, we add a COMPATIBILITY section to the manpage,
>     and explain the difference between core revisions there.
>
> We could drop the none case. But then again, if the target isn't reset
> yet, then not scribbling into getties and stuff where it's avoidable
> might be preferred by those who can. So why not.
>
> Could you try to read us the boot firmware revision you're running? It's
> described under the link below. Not sure if it works on your platform
> though.

Daniel,

I did a little testing with kwboot and boot sequence.

First, BootROM version of my Dove is 2.33. The BootROM version address is a
little different what is given on the webpage (ffff003c instead of ff00003c).

CuBox>> md ffff003c 1
ffff003c: 00000233    3...

Dove does not support UART boot sequences. It has to be selected by reset
strapping, i.e. if there is no push button as on the cubox it will be
difficult for most of the users ;)

I also tested the above on the Mirabox (Armada 370) and except that the BootROM
there, prints out some message after reset it works if I first call kwboot with
-b and then with -n or delay xmodem call by a second.

BootROM version on Armada 370 is 1.08 and the version register address is very
different. It resets if I try to read ff00003c or ffff003c and I have neither
a DS nor the u-boot source available.

Finally, I tested kwboot on 88F6282 (aka Armada 300) and there BootROM version
is 1.21 (on ff00003c) and it does work as with Kirkwood (i.e. send boot sequence).

I think, for the patch set, that I will remove patch 10 from it and leave the
required modifications up to you?

Sebastian

[U-Boot] [PATCH v2 00/10] Add Marvell Dove and SolidRun CuBox

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 04 December 2012 14:02
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v2 00/10] Add Marvell Dove and SolidRun CuBox
> 
> This patch set add support for the Marvell Dove 88AP510 SoC and
> the SolidRun CuBox board based on that SoC. The patch set is divided
> into the four following sections:
> 
> (1) Patches 1-5:
> Add support for the Dove SoC and related drivers. Where possible
> drivers from Marvell Kirkwood are reused (mvsata, mvgbe), or
> forked to allow more generic usage (SPI, GPIO). The SDHCI driver
> is different and a new driver is added for it. The forked drivers
> can also be reused on Kirkwood but that would have required patching
> existing boards.
> 
> (2) Patches 6-8:
> Allow mvgbe to use the phylib API, add support for 88E1310 PHY and
> allow Dove to use the driver.
> 
> (3) Patch 9
> Add the SolidRun CuBox as the first board based on Marvell Dove SoC.
> 
> (4) Patch 10
> Add support for different UART boot mode found on Dove.
> 
> Changelog:
> v1->v2: respect review comments by Luka Perkov
> - fix commenting styles and typos
> - add MAINTAINERS entry
> - also update kwboot.1 manpage
> 
> Sebastian Hesselbarth (10):
>   ARM: dove: add support for Marvell Dove SoC
>   GPIO: add gpio driver for Orion SoCs
>   MMC: sdhci: Add support for dove sdhci
>   SPI: Add Orion SPI driver
>   block: mvsata: add dove include
>   NET: phy: add 88E1310 PHY initialization
>   NET: mvgbe: add phylib support
>   NET: mvgbe: add support for Dove
>   Boards: Add support for SolidRun CuBox
>   tools: Add support for Dove to kwboot
> 
>  MAINTAINERS                             |    4 +
>  arch/arm/cpu/armv7/dove/Makefile        |   49 +++++
>  arch/arm/cpu/armv7/dove/cpu.c           |  266
> ++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/dove/dram.c          |  118 ++++++++++++
>  arch/arm/cpu/armv7/dove/lowlevel_init.S |   83 ++++++++
>  arch/arm/cpu/armv7/dove/mpp.c           |  318
> +++++++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/dove/timer.c         |  176 +++++++++++++++++
>  arch/arm/cpu/armv7/dove/usb.c           |  101 ++++++++++
>  arch/arm/include/asm/arch-dove/config.h |  153 +++++++++++++++
>  arch/arm/include/asm/arch-dove/cpu.h    |  204 ++++++++++++++++++++
>  arch/arm/include/asm/arch-dove/dove.h   |   93 +++++++++
>  arch/arm/include/asm/arch-dove/gpio.h   |   35 ++++
>  arch/arm/include/asm/arch-dove/mpp.h    |  283
> +++++++++++++++++++++++++++
>  board/solidrun/cubox/Makefile           |   45 +++++
>  board/solidrun/cubox/cubox.c            |  141 ++++++++++++++
>  board/solidrun/cubox/kwbimage.cfg       |   76 ++++++++
>  boards.cfg                              |    1 +
>  doc/kwboot.1                            |   13 +-
>  drivers/block/mvsata_ide.c              |    2 +
>  drivers/gpio/Makefile                   |    1 +
>  drivers/gpio/orion_gpio.c               |  167 ++++++++++++++++
>  drivers/mmc/Makefile                    |    1 +
>  drivers/mmc/dove_sdhci.c                |  101 ++++++++++
>  drivers/net/mvgbe.c                     |   70 ++++++-
>  drivers/net/mvgbe.h                     |    7 +
>  drivers/net/phy/marvell.c               |   48 +++++
>  drivers/spi/Makefile                    |    1 +
>  drivers/spi/orion_spi.c                 |  217 +++++++++++++++++++++
>  include/configs/cubox.h                 |  175 +++++++++++++++++
>  include/orion_gpio.h                    |   64 +++++++
>  tools/Makefile                          |    2 +
>  tools/kwboot.c                          |   44 ++++-
>  32 files changed, 3048 insertions(+), 11 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/dove/Makefile
>  create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
>  create mode 100644 arch/arm/cpu/armv7/dove/dram.c
>  create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
>  create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
>  create mode 100644 arch/arm/cpu/armv7/dove/timer.c
>  create mode 100644 arch/arm/cpu/armv7/dove/usb.c
>  create mode 100644 arch/arm/include/asm/arch-dove/config.h
>  create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
>  create mode 100644 arch/arm/include/asm/arch-dove/dove.h
>  create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
>  create mode 100644 arch/arm/include/asm/arch-dove/mpp.h
>  create mode 100644 board/solidrun/cubox/Makefile
>  create mode 100644 board/solidrun/cubox/cubox.c
>  create mode 100644 board/solidrun/cubox/kwbimage.cfg
>  create mode 100644 drivers/gpio/orion_gpio.c
>  create mode 100644 drivers/mmc/dove_sdhci.c
>  create mode 100644 drivers/spi/orion_spi.c
>  create mode 100644 include/configs/cubox.h
>  create mode 100644 include/orion_gpio.h

Hi Sebastian
First of all thanks for this patch series.
FYI: I'll review and provide the comments towards the end of this week.

Regards...
Prafulla . . .

[U-Boot] [PATCH 00/10] Add Marvell Dove and SolidRun CuBox

[Albert ARIBAUD]

Hi Sebastian,

On Sun,  2 Dec 2012 15:36:12 +0100, Sebastian Hesselbarth
<sebastian.hesselbarth@gmail.com> wrote:
> This patch set add support for the Marvell Dove 88AP510 SoC and
> the SolidRun CuBox board based on that SoC. The patch set is divided
> into the four following sections:
> 
> (1) Patches 1-5:
> Add support for the Dove SoC and related drivers. Where possible
> drivers from Marvell Kirkwood are reused (mvsata, mvgbe), or
> forked to allow more generic usage (SPI, GPIO). The SDHCI driver
> is different and a new driver is added for it. The forked drivers
> can also be reused on Kirkwood but that would have required patching
> existing boards.
> 
> (2) Patches 6-8:
> Allow mvgbe to use the phylib API, add support for 88E1310 PHY and
> allow Dove to use the driver.
> 
> (3) Patch 9
> Add the SolidRun CuBox as the first board based on Marvell Dove SoC.
> 
> (4) Patch 10
> Add support for different UART boot mode found on Dove.
> 
> Sebastian Hesselbarth (10):
>   ARM: dove: add support for Marvell Dove SoC
>   GPIO: add gpio driver for Orion SoCs
>   MMC: sdhci: Add support for dove sdhci
>   SPI: Add Orion SPI driver
>   block: mvsata: add dove include
>   NET: phy: add 88E1310 PHY initialization
>   NET: mvgbe: add phylib support
>   NET: mvgbe: add support for Dove
>   Boards: Add support for SolidRun CuBox
>   tools: Add support for Dove to kwboot

Just a general remark: as this is a new support patch, it will only go
in during next merge window; so when kirkwood or ARM pull requests are
sent, make sure your patch set still applies to the new tree tip and if
not, fix and submit a new version that does apply.

(mentioning this because you're touching files that I'm pretty sure are
being modified by changes that *will* go in 2013.01)

Amicalement,
-- 
Albert.

[U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox

[Sebastian Hesselbarth]

This patch set add support for the Marvell Dove 88AP510 SoC and
the SolidRun CuBox board based on that SoC. The patch set is divided
into the four following sections:

(1) Patches 1-5:
Add support for the Dove SoC and related drivers. Where possible
drivers from Marvell Kirkwood are reused (mvsata, mvgbe), or
forked to allow more generic usage (SPI, GPIO). The SDHCI driver
is different and a new driver is added for it. The forked drivers
can also be reused on Kirkwood but that would have required patching
existing boards.

(2) Patches 6-8:
Allow mvgbe to use the phylib API, add support for 88E1310 PHY and
allow Dove to use the driver.

(3) Patch 9
Add the SolidRun CuBox as the first board based on Marvell Dove SoC.

(4) Patch 10
Add support for different UART boot mode found on Dove.

Changelog:
v1->v2:
- respect review comments by Luka Perkov
- fix commenting styles and typos
- add MAINTAINERS entry
- also update kwboot.1 manpage

v2->v3:
- integrate kwboot patch from Daniel Stodden
- rebase on release v2013.01

Sebastian Hesselbarth (10):
  ARM: dove: add support for Marvell Dove SoC
  GPIO: add gpio driver for Orion SoCs
  MMC: sdhci: Add support for dove sdhci
  SPI: Add Orion SPI driver
  block: mvsata: add dove include
  NET: phy: add 88E1310 PHY initialization
  NET: mvgbe: add phylib support
  NET: mvgbe: add support for Dove
  Boards: Add support for SolidRun CuBox
  tools: Add support for Dove to kwboot

 MAINTAINERS                             |    4 +
 arch/arm/cpu/armv7/dove/Makefile        |   49 +++++
 arch/arm/cpu/armv7/dove/cpu.c           |  266 ++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/dram.c          |  118 ++++++++++++
 arch/arm/cpu/armv7/dove/lowlevel_init.S |   83 ++++++++
 arch/arm/cpu/armv7/dove/mpp.c           |  318 +++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/timer.c         |  176 +++++++++++++++++
 arch/arm/cpu/armv7/dove/usb.c           |  101 ++++++++++
 arch/arm/include/asm/arch-dove/config.h |  153 +++++++++++++++
 arch/arm/include/asm/arch-dove/cpu.h    |  204 ++++++++++++++++++++
 arch/arm/include/asm/arch-dove/dove.h   |   93 +++++++++
 arch/arm/include/asm/arch-dove/gpio.h   |   35 ++++
 arch/arm/include/asm/arch-dove/mpp.h    |  283 +++++++++++++++++++++++++++
 board/solidrun/cubox/Makefile           |   45 +++++
 board/solidrun/cubox/cubox.c            |  141 ++++++++++++++
 board/solidrun/cubox/kwbimage.cfg       |   76 ++++++++
 boards.cfg                              |    1 +
 doc/kwboot.1                            |   13 +-
 drivers/block/mvsata_ide.c              |    2 +
 drivers/gpio/Makefile                   |    1 +
 drivers/gpio/orion_gpio.c               |  167 ++++++++++++++++
 drivers/mmc/Makefile                    |    1 +
 drivers/mmc/dove_sdhci.c                |  101 ++++++++++
 drivers/net/mvgbe.c                     |   70 ++++++-
 drivers/net/mvgbe.h                     |    7 +
 drivers/net/phy/marvell.c               |   48 +++++
 drivers/spi/Makefile                    |    1 +
 drivers/spi/orion_spi.c                 |  217 +++++++++++++++++++++
 include/configs/cubox.h                 |  175 +++++++++++++++++
 include/orion_gpio.h                    |   64 +++++++
 tools/Makefile                          |    2 +
 tools/kwboot.c                          |   25 ++-
 32 files changed, 3027 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/dove/Makefile
 create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
 create mode 100644 arch/arm/cpu/armv7/dove/dram.c
 create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
 create mode 100644 arch/arm/cpu/armv7/dove/timer.c
 create mode 100644 arch/arm/cpu/armv7/dove/usb.c
 create mode 100644 arch/arm/include/asm/arch-dove/config.h
 create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
 create mode 100644 arch/arm/include/asm/arch-dove/dove.h
 create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
 create mode 100644 arch/arm/include/asm/arch-dove/mpp.h
 create mode 100644 board/solidrun/cubox/Makefile
 create mode 100644 board/solidrun/cubox/cubox.c
 create mode 100644 board/solidrun/cubox/kwbimage.cfg
 create mode 100644 drivers/gpio/orion_gpio.c
 create mode 100644 drivers/mmc/dove_sdhci.c
 create mode 100644 drivers/spi/orion_spi.c
 create mode 100644 include/configs/cubox.h
 create mode 100644 include/orion_gpio.h

---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
-- 
1.7.10.4

[U-Boot] [PATCH v3 01/10] ARM: dove: add support for Marvell Dove SoC

[Sebastian Hesselbarth]

This patch adds initial support for the armv7-based Marvell Dove SoC
(88AP510).

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 arch/arm/cpu/armv7/dove/Makefile        |   49 +++++
 arch/arm/cpu/armv7/dove/cpu.c           |  266 ++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/dram.c          |  118 ++++++++++++
 arch/arm/cpu/armv7/dove/lowlevel_init.S |   83 ++++++++
 arch/arm/cpu/armv7/dove/mpp.c           |  318 +++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/timer.c         |  176 +++++++++++++++++
 arch/arm/cpu/armv7/dove/usb.c           |  101 ++++++++++
 arch/arm/include/asm/arch-dove/config.h |  153 +++++++++++++++
 arch/arm/include/asm/arch-dove/cpu.h    |  204 ++++++++++++++++++++
 arch/arm/include/asm/arch-dove/dove.h   |   93 +++++++++
 arch/arm/include/asm/arch-dove/gpio.h   |   35 ++++
 arch/arm/include/asm/arch-dove/mpp.h    |  283 +++++++++++++++++++++++++++
 12 files changed, 1879 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/dove/Makefile
 create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
 create mode 100644 arch/arm/cpu/armv7/dove/dram.c
 create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
 create mode 100644 arch/arm/cpu/armv7/dove/timer.c
 create mode 100644 arch/arm/cpu/armv7/dove/usb.c
 create mode 100644 arch/arm/include/asm/arch-dove/config.h
 create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
 create mode 100644 arch/arm/include/asm/arch-dove/dove.h
 create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
 create mode 100644 arch/arm/include/asm/arch-dove/mpp.h

diff --git a/arch/arm/cpu/armv7/dove/Makefile b/arch/arm/cpu/armv7/dove/Makefile
new file mode 100644
index 0000000..127d67e
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/Makefile
@@ -0,0 +1,49 @@
+#
+# Marvell Dove SoC Makefile
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	+= lowlevel_init.o
+COBJS-y := cpu.o dram.o timer.o mpp.o
+COBJS-$(CONFIG_USB_EHCI_MARVELL) += usb.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/dove/cpu.c b/arch/arm/cpu/armv7/dove/cpu.c
new file mode 100644
index 0000000..b9e708c
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/cpu.c
@@ -0,0 +1,266 @@
+/*
+ * Marvell Dove SoC cpu related functions
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <u-boot/md5.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <hush.h>
+
+void reset_cpu(unsigned long ignored)
+{
+	struct dovecpu_registers *cpureg =
+	    (struct dovecpu_registers *)DOVE_CPU_REG_BASE;
+
+	/* Enable soft reset to assert RSTOUTn */
+	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+	       &cpureg->rstoutn_mask);
+	/* Assert soft reset */
+	writel(readl(&cpureg->sys_soft_rst) | 1,
+	       &cpureg->sys_soft_rst);
+	do {} while (1);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int dove_print_cpu(void)
+{
+	char *cpu;
+	u32 idreg;
+	u16 part, rev;
+
+	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(idreg));
+
+	part = (idreg >> ARM_ID_PARTNUM_OFFSET) & ARM_ID_PARTNUM_MASK;
+	rev = (idreg >> ARM_ID_REVISION_OFFSET) & ARM_ID_REVISION_MASK;
+
+	switch (part) {
+	case DOVECPU_PART_SHEEVA:
+		cpu = "Marvell Sheeva";
+		break;
+	default:
+		cpu = "Unknown CPU";
+	}
+
+	printf("CPU:   %s (rev %d)\n", cpu, rev);
+	return 0;
+}
+
+int dove_print_soc(void)
+{
+	char *soc, *rev;
+	u16 devid = (readl(DOVE_REG_PCIE_DEVID) >> 16) & 0xffff;
+	u8 revid = readl(DOVE_REG_PCIE_REVID) & 0xff;
+
+	switch (devid) {
+	case DOVESOC_DEVID_AP510:
+		soc = "AP510";
+		break;
+	case DOVESOC_DEVID_F6781:
+		soc = "F6781";
+		break;
+	default:
+		printf("ERROR.. %s: Unsupported SoC %04x\n", __func__, devid);
+		return -1;
+	}
+
+	switch (revid) {
+	case DOVESOC_REVID_Z0:
+		rev = "Z0";
+		break;
+	case DOVESOC_REVID_Z1:
+		rev = "Z1";
+		break;
+	case DOVESOC_REVID_Y0:
+		rev = "Y0";
+		break;
+	case DOVESOC_REVID_Y1:
+		rev = "Y1";
+		break;
+	case DOVESOC_REVID_X0:
+		rev = "X0";
+		break;
+	case DOVESOC_REVID_A0:
+		rev = "A0";
+		break;
+	case DOVESOC_REVID_A1:
+		rev = "A1";
+		break;
+	default:
+		rev = "Unknown revision";
+	};
+
+	printf("SoC:   Dove 88%s (%s)\n", soc, rev);
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	if (dove_print_soc())
+		return -1;
+	if (dove_print_cpu())
+		return -1;
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*
+ * dove_init_gpio - initial GPIO configuration
+ */
+void dove_init_gpio(struct dove_gpio_init *gpp)
+{
+	struct dovegpio_registers *gpio0reg =
+		(struct dovegpio_registers *)DOVE_GPIO0_BASE;
+	struct dovegpio_registers *gpio1reg =
+		(struct dovegpio_registers *)DOVE_GPIO1_BASE;
+	struct dovegpio_registers *gpio2reg =
+		(struct dovegpio_registers *)DOVE_GPIO2_BASE;
+
+	/* Init GPIOS to default values as per board requirement */
+	writel(gpp->val0, &gpio0reg->dout);
+	writel(gpp->val1, &gpio1reg->dout);
+	writel(gpp->val2, &gpio2reg->dout);
+	writel(gpp->oe0_n, &gpio0reg->oe);
+	writel(gpp->oe1_n, &gpio1reg->oe);
+	writel(gpp->oe2_n, &gpio2reg->oe);
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int dove_winctrl_calcsize(unsigned int sizeval)
+{
+	int i;
+	unsigned int j = 0;
+	u32 val = sizeval >> 1;
+
+	for (i = 0; val >= 0x10000; i++) {
+		j |= (1 << i);
+		val = val >> 1;
+	}
+	return 0x0000ffff & j;
+}
+
+/*
+ * dove_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Dove Soc to addess different
+ * devices. Windows 0-3 can be configured for size, BAR and remap addr.
+ * Windows 4-7 can be configured for size and BAR.
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ */
+int dove_config_adr_windows(void)
+{
+	struct dovewin_registers *winregs =
+		(struct dovewin_registers *)DOVE_CPU_WIN_BASE;
+
+	/* Window 0: 1M PCIE0 IO address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE0,
+	     DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE), &winregs[0].ctrl);
+
+	writel(DOVE_DEFADR_PCIE0_IO, &winregs[0].base);
+	writel(DOVE_DEFADR_PCIE0_IO_REMAP, &winregs[0].remap_lo);
+	writel(0x0, &winregs[0].remap_hi);
+
+	/* Window 1: 1M PCIE1 IO address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE1,
+	     DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE), &winregs[1].ctrl);
+
+	writel(DOVE_DEFADR_PCIE1_IO, &winregs[1].base);
+	writel(DOVE_DEFADR_PCIE1_IO_REMAP, &winregs[1].remap_lo);
+	writel(0x0, &winregs[1].remap_hi);
+
+	/* Window 2: 128M PCIE0 MEM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE0,
+	     DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE), &winregs[2].ctrl);
+
+	writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].base);
+	writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].remap_lo);
+	writel(0x0, &winregs[2].remap_hi);
+
+	/* Window 3: 128M PCIE1 MEM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE1,
+	     DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE), &winregs[3].ctrl);
+
+	writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].base);
+	writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].remap_lo);
+	writel(0x0, &winregs[3].remap_hi);
+
+	/* Window 4: 1M Cryptographic SRAM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_SASRAM,
+	     DOVECPU_ATTR_SASRAM, DOVECPU_WIN_ENABLE), &winregs[4].ctrl);
+	writel(DOVE_DEFADR_SASRAM, &winregs[4].base);
+
+	/* Window 5: 128M Bootrom address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_BOOTROM,
+	     DOVECPU_ATTR_BOOTROM, DOVECPU_WIN_ENABLE), &winregs[5].ctrl);
+	writel(DOVE_DEFADR_BOOTROM, &winregs[5].base);
+
+	/* Window 6: 1M PMU Scratchpad address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PMURAM,
+	     DOVECPU_ATTR_PMURAM, DOVECPU_WIN_ENABLE), &winregs[6].ctrl);
+	writel(DOVE_DEFADR_PMURAM, &winregs[6].base);
+
+	/* Window 7: Disabled */
+	writel(DOVECPU_WIN_DISABLE, &winregs[7].ctrl);
+
+	return 0;
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	dove_config_adr_windows();
+#ifdef CONFIG_USB_EHCI_MARVELL
+	dove_ehci_phy_init(0);
+	dove_ehci_phy_init(1);
+#endif /* CONFIG_USB_EHCI_MARVELL */
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Enable D-cache. I-cache is already enabled in lowlevel_init.S */
+	dcache_enable();
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+#ifdef CONFIG_MVGBE
+int cpu_eth_init(bd_t *bis)
+{
+	mvgbe_initialize(bis);
+	return 0;
+}
+#endif /* CONFIG_MVGBE */
diff --git a/arch/arm/cpu/armv7/dove/dram.c b/arch/arm/cpu/armv7/dove/dram.c
new file mode 100644
index 0000000..437263c
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/dram.c
@@ -0,0 +1,118 @@
+/*
+ * Marvell Dove SoC DRAM initialization
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DOVE_REG_DRAM_MAP(x)	(DOVE_REGISTER(0x800100) + (x * 0x10))
+#define DRAM_START_MASK		0xff800000
+#define DRAM_SIZE_MASK		0xf
+#define DRAM_SIZE_SHIFT		16
+
+/*
+ * dove_sdram_start - reads start from Memory Address Map Register n
+ */
+u32 dove_dram_start(enum memory_bank bank)
+{
+	u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
+	u32 enable = 0x01 & reg;
+
+	if ((!enable) || (bank > BANK1))
+		return 0;
+
+	return reg & DRAM_START_MASK;
+}
+
+/*
+ * dove_sdram_size - reads size from Memory Address Map Register n
+ */
+u32 dove_dram_size(enum memory_bank bank)
+{
+	u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
+	u32 enable = 0x01 & reg;
+	u32 size;
+
+	if ((!enable) || (bank > BANK1))
+		return 0;
+
+	/*
+	 * area_length: 7 = 8M, 8 = 16M, ..., 15 = 2048M
+	 * size = 1 << (area_length + 16)
+	 */
+	size = (reg >> DRAM_SIZE_SHIFT) & DRAM_SIZE_MASK;
+	size = 1 << (size + 16);
+	return size;
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = dove_dram_start(i);
+		gd->bd->bi_dram[i].size = dove_dram_size(i);
+
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/*
+		 * If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash
+		 */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/armv7/dove/lowlevel_init.S b/arch/arm/cpu/armv7/dove/lowlevel_init.S
new file mode 100644
index 0000000..105d12d
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/lowlevel_init.S
@@ -0,0 +1,83 @@
+/*
+ * Marvell Dove SoC icache and reg base low level init
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/dove.h>
+#include <generated/asm-offsets.h>
+#include <linux/linkage.h>
+
+/*
+ * Enable Tauros2 L2 ICache
+ */
+.macro init_l2cc
+	mrc	15, 0, r0, c1, c0, 1
+	orr	r0, r0, #0x2
+	mcr	15, 0, r0, c1, c0, 1
+.endm /* init_l2cc */
+
+/*
+ * Init internal register base addresses
+ */
+.macro init_reg_base
+	/* set SB reg base to 0xf1000000 */
+	ldr	r1, =(DOVE_PREMAP_INT_REGS_BASE_ADDR)
+	ldr	r6, =DOVE_SB_REGS_PHYS_BASE
+	str	r6, [r1]
+
+	/* set NB reg base to 0xf1800000 */
+	ldr	r1, =(DOVE_CPU_CTRL_REG)
+	ldr	r4, =0xffff0000
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	lsr	r4, r6, #16
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+	/* Set AXI bridge address mapping to 0xf1800000 */
+	ldr	r1, =(DOVE_AXI_CTRL_REG)
+	ldr	r4, =0x007fffff
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+	/* set MC configuration register decode address to 0xf1800000 */
+	ldr	r1, =(DOVE_PREMAP_MC_DECODE_REG)
+	ldr	r4, =0x0000ffff
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+.endm /* init_reg_base */
+
+.section ".text.init", "x"
+
+ENTRY(lowlevel_init)
+	init_l2cc
+	init_reg_base
+
+	/* r12 saved upper lr*/
+	mov pc,lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/dove/mpp.c b/arch/arm/cpu/armv7/dove/mpp.c
new file mode 100644
index 0000000..ed24b38
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/mpp.c
@@ -0,0 +1,318 @@
+/*
+ * Marvell Dove SoC MPP pinmux
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define MPP_BITS	4
+#define MPP_MASK	0xf
+#define MPPS_PER_REG	8
+
+#define MPP_NUM(_x)	((_x) & 0xff)
+#define MPP_SEL(_x)	(((_x) >> 8) & 0x1f)
+#define MPP_GPIO(_x)	((_x) & (1 << 15))
+
+#define MPP_CTRL(i)			(DOVE_MPP_BASE + (i * MPP_BITS))
+#define MPP_PMU_GENERAL_CTRL		(DOVE_MPP_BASE + 0x010)
+#define  PMUG_AUDIO0_AC97_SEL		(1 << 16)
+#define MPP4_CTRL			(DOVE_MPP_BASE + 0x240)
+#define  MPP4_SDIO0_GPIO_SEL		(1 << 0)
+#define  MPP4_SDIO1_GPIO_SEL		(1 << 1)
+#define  MPP4_CAMERA_GPIO_SEL		(1 << 2)
+#define  MPP4_AUDIO1_GPIO_SEL		(1 << 3)
+#define  MPP4_UART1_GPIO_SEL		(1 << 4)
+#define  MPP4_SPI_GPIO_SEL		(1 << 5)
+#define MPP_GENERAL_CTRL		(DOVE_PDMA_BASE + 0x403c)
+#define  MPPG_NAND_GPIO_SEL		(1 << 0)
+#define  MPPG_AUDIO1_SPDIFO_GPIO_SEL	(1 << 1)
+#define GENERAL_CONFIG_1		(DOVE_PDMA_BASE + 0x002c)
+#define  GENERAL_TWSI_MUXEN_OPTION1	(1 << 7)
+#define GENERAL_CONFIG_2		(DOVE_PDMA_BASE + 0x0030)
+#define  GENERAL_TWSI_OPTION3_SEL	(1 << 22)
+#define  GENERAL_TWSI_MUXEN_OPTION3	(1 << 21)
+#define  GENERAL_TWSI_MUXEN_OPTION2	(1 << 20)
+#define SSP_CONFIG_STATUS_1		(DOVE_PDMA_BASE + 0x0034)
+#define  SSP_SSP_ON_AUDIO1		(1 << 0)
+
+/*
+ * MPP0-23 have standard MPP register layout
+ */
+static void dove_mpp_std_set(u16 config)
+{
+	u8 num = MPP_NUM(config);
+	u32 off = (num / MPPS_PER_REG) * MPP_BITS;
+	u32 shift = (num % MPPS_PER_REG) * MPP_BITS;
+	u32 reg;
+
+	/* configure standard MPP pin */
+	reg  = readl(MPP_CTRL(off));
+	reg &= ~(MPP_MASK << shift);
+	reg |= MPP_SEL(config) << shift;
+	writel(reg, MPP_CTRL(off));
+
+	/* configure gpio capabilities */
+	if (MPP_GPIO(config))
+		orion_gpio_set_valid(num, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+	else
+		orion_gpio_set_valid(num, 0);
+}
+
+/*
+ * MPP0-15 also allow to mux PMU functions
+ */
+static void dove_mpp_pmu_set(u16 config)
+{
+	u8 num = MPP_NUM(config);
+
+	if (MPP_SEL(config) == PMU) {
+		/* enable PMU on MPP */
+		writel(readl(MPP_PMU_GENERAL_CTRL) | (1 << num),
+		       MPP_PMU_GENERAL_CTRL);
+		/* disable gpio capabilities */
+		orion_gpio_set_valid(num, 0);
+	} else {
+		/* disable PMU on MPP */
+		writel(readl(MPP_PMU_GENERAL_CTRL) & ~(1 << num),
+		       MPP_PMU_GENERAL_CTRL);
+		/* configure MPP */
+		dove_mpp_std_set(config);
+	}
+}
+
+/*
+ * MPP groups on MPP4_CTRL have different register layout
+ * and allow GPIO or special function only
+ */
+static void dove_mpp4_set(u16 config)
+{
+	u32 reg = readl(MPP4_CTRL);
+	u32 mask;
+	u8  n, nmin, nmax;
+	int gpio;
+
+	switch (MPP_NUM(config)) {
+	case MPP_CAMERA:
+		mask = MPP4_CAMERA_GPIO_SEL;
+		nmin = MPP_CAMERA;
+		nmax = MPP_CAMERA_MAX;
+		break;
+	case MPP_SDIO0:
+		mask = MPP4_SDIO0_GPIO_SEL;
+		nmin = MPP_SDIO0;
+		nmax = MPP_SDIO0_MAX;
+		break;
+	case MPP_SDIO1:
+		mask = MPP4_SDIO1_GPIO_SEL;
+		nmin = MPP_SDIO1;
+		nmax = MPP_SDIO1_MAX;
+		break;
+	case MPP_SPI:
+		mask = MPP4_SPI_GPIO_SEL;
+		nmin = MPP_SPI;
+		nmax = MPP_SPI_MAX;
+		break;
+	case MPP_UART1:
+		mask = MPP4_UART1_GPIO_SEL;
+		nmin = MPP_UART1;
+		nmax = MPP_UART1_MAX;
+		break;
+	default:
+		return;
+	}
+
+	reg &= ~mask;
+	if (MPP_SEL(config))
+		reg |= mask;
+	writel(reg, MPP4_CTRL);
+
+	/* configure gpio capabilities */
+	gpio = 0;
+	if (MPP_GPIO(config))
+		gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+	for (n = nmin; n <= nmax; n++)
+		orion_gpio_set_valid(n, gpio);
+}
+
+/*
+ * MPP_GENERAL_CTRL allows GPIO on NAND pins
+ */
+static void dove_mpp_nand_set(u16 config)
+{
+	u32 reg = readl(MPP_GENERAL_CTRL);
+	u8 n;
+	int gpio;
+
+	reg &= ~MPPG_NAND_GPIO_SEL;
+	if (config == MPP_NAND_GPO)
+		reg |= MPPG_NAND_GPIO_SEL;
+	writel(reg, MPP_GENERAL_CTRL);
+
+	/* configure gpio capabilities */
+	gpio = (config == MPP_NAND_GPO) ? GPIO_OUTPUT_OK : 0;
+	for (n = MPP_NAND; n <= MPP_NAND_MAX; n++)
+		orion_gpio_set_valid(n, gpio);
+}
+
+/*
+ * Dedicated audio1 pins can carry i2s, spdif, ssp or twsi
+ * and gpio in various combinations
+ */
+#define AUDIO1_TWSI	(1 << 0)
+#define AUDIO1_SPDIFO	(1 << 1)
+#define AUDIO1_SSP	(1 << 2)
+#define AUDIO1_GPIO	(1 << 3)
+
+static void dove_mpp_audio1_set(u16 config)
+{
+	u32 mpp4  = readl(MPP4_CTRL);
+	u32 sspc1 = readl(SSP_CONFIG_STATUS_1);
+	u32 gmpp  = readl(MPP_GENERAL_CTRL);
+	u32 gcfg2 = readl(GENERAL_CONFIG_2);
+	u8 n, sel = MPP_SEL(config);
+	int gpio;
+
+	gcfg2 &= ~GENERAL_TWSI_OPTION3_SEL;
+	gmpp &= ~MPPG_AUDIO1_SPDIFO_GPIO_SEL;
+	sspc1 &= ~SSP_SSP_ON_AUDIO1;
+	mpp4 &= ~MPP4_AUDIO1_GPIO_SEL;
+	if (sel & AUDIO1_TWSI)
+		gcfg2 |= GENERAL_TWSI_OPTION3_SEL;
+	if (sel & AUDIO1_SPDIFO)
+		gmpp |= MPPG_AUDIO1_SPDIFO_GPIO_SEL;
+	if (sel & AUDIO1_SSP)
+		sspc1 |= SSP_SSP_ON_AUDIO1;
+	if (sel & AUDIO1_GPIO)
+		mpp4 |= MPP4_AUDIO1_GPIO_SEL;
+
+	writel(mpp4, MPP4_CTRL);
+	writel(sspc1, SSP_CONFIG_STATUS_1);
+	writel(gmpp, MPP_GENERAL_CTRL);
+	writel(gcfg2, GENERAL_CONFIG_2);
+
+	/* gpio allows gpio on all audio1 mpp pins */
+	gpio = 0;
+	if (config == MPP_AUDIO1_GPIO)
+		gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+
+	for (n = MPP_AUDIO1; n <= MPP_AUDIO1_MAX; n++)
+		orion_gpio_set_valid(n, gpio);
+
+	switch (config) {
+	/* spdifo and twsi allow gpio on mpp[52:55] */
+	case MPP_AUDIO1_SPDIFO:
+	case MPP_AUDIO1_TWSI:
+		orion_gpio_set_valid(52, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(53, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(54, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(55, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		break;
+	/* i2s and ssp allow gpio on mpp[56:57] */
+	case MPP_AUDIO1_I2S:
+	case MPP_AUDIO1_SSP:
+		orion_gpio_set_valid(56, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		orion_gpio_set_valid(57, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		break;
+	}
+}
+
+/*
+ * MPP PMU switches audio0 pins to ac97 or i2s0
+ */
+static void dove_mpp_audio0_set(u16 config)
+{
+	/* switch i2s or ac97 to audio0 */
+	u32 reg = readl(MPP_PMU_GENERAL_CTRL);
+
+	reg &= ~PMUG_AUDIO0_AC97_SEL;
+	if (config == MPP_AUDIO0_AC97)
+		reg |= PMUG_AUDIO0_AC97_SEL;
+	writel(reg, MPP_PMU_GENERAL_CTRL);
+}
+
+/*
+ * TWSI has 3 optional pin sets that can be switched during runtime
+ */
+static void dove_mpp_twsi_set(u16 config)
+{
+	u32 gcfg1 = readl(GENERAL_CONFIG_1);
+	u32 gcfg2 = readl(GENERAL_CONFIG_2);
+
+	gcfg1 &= ~GENERAL_TWSI_MUXEN_OPTION1;
+	gcfg2 &= ~(GENERAL_TWSI_MUXEN_OPTION2 | GENERAL_TWSI_MUXEN_OPTION3);
+
+	switch (config) {
+	case MPP_TWSI_OPTION1:
+		gcfg1 |= GENERAL_TWSI_MUXEN_OPTION1;
+		break;
+	case MPP_TWSI_OPTION2:
+		gcfg2 |= GENERAL_TWSI_MUXEN_OPTION2;
+		break;
+	case MPP_TWSI_OPTION3:
+		gcfg2 |= GENERAL_TWSI_MUXEN_OPTION3;
+		break;
+	}
+
+	writel(gcfg1, GENERAL_CONFIG_1);
+	writel(gcfg2, GENERAL_CONFIG_2);
+}
+
+void dove_mpp_conf(u16 *mpp_list)
+{
+	while (*mpp_list) {
+		u8 num = MPP_NUM(*mpp_list);
+
+		if (num <= MPP_PMU_MAX)
+			dove_mpp_pmu_set(*mpp_list);
+		else if (num <= MPP_STD_MAX)
+			dove_mpp_std_set(*mpp_list);
+		else {
+			switch (num) {
+			case MPP_CAMERA:
+			case MPP_SDIO0:
+			case MPP_SDIO1:
+			case MPP_SPI:
+			case MPP_UART1:
+				dove_mpp4_set(*mpp_list);
+				break;
+			case MPP_NAND:
+				dove_mpp_nand_set(*mpp_list);
+				break;
+			case MPP_AUDIO0:
+				dove_mpp_audio0_set(*mpp_list);
+				break;
+			case MPP_AUDIO1:
+				dove_mpp_audio1_set(*mpp_list);
+				break;
+			case MPP_TWSI:
+				dove_mpp_twsi_set(*mpp_list);
+				break;
+			}
+		}
+		mpp_list++;
+	}
+}
diff --git a/arch/arm/cpu/armv7/dove/timer.c b/arch/arm/cpu/armv7/dove/timer.c
new file mode 100644
index 0000000..3be9b78
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/timer.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Dove SoC timer
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dove.h>
+
+#define UBOOT_CNTR	0	/* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct dovetmr_val {
+	u32 reload;	/* Timer reload reg */
+	u32 val;	/* Timer value reg */
+};
+
+/* Timer registers */
+struct dovetmr_registers {
+	u32 ctrl;	/* Timer control reg */
+	u32 pad[3];
+	struct dovetmr_val tmr[2];
+	u32 wdt_reload;
+	u32 wdt_val;
+};
+
+struct dovetmr_registers *dovetmr_regs =
+	(struct dovetmr_registers *)DOVE_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG			&dovetmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum)	&dovetmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum)		&dovetmr_regs->tmr[tmrnum].val
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS		0
+#define TRG_ARM_TIMER_REL_MASK		0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS		0
+#define TVR_ARM_TIMER_MASK		0xffffffff
+#define TVR_ARM_TIMER_MAX		0xffffffff
+#define TIMER_LOAD_VAL			0xffffffff
+
+#define READ_TIMER			(readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
+					 (CONFIG_SYS_TCLK / 1000))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER;
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec +
+			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	uint current;
+	ulong delayticks;
+
+	current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
+	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+	if (current < delayticks) {
+		delayticks -= current;
+		do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current);
+		do {} while ((TIMER_LOAD_VAL - delayticks) <
+			     readl(CNTMR_VAL_REG(UBOOT_CNTR)));
+	} else {
+		do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
+			     (current - delayticks));
+	}
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+	unsigned int cntmrctrl;
+
+	/* load value into timer */
+	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+	/* enable timer in auto reload mode */
+	cntmrctrl = readl(CNTMR_CTRL_REG);
+	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+	writel(cntmrctrl, CNTMR_CTRL_REG);
+
+	/* init the timestamp and lastdec value */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/armv7/dove/usb.c b/arch/arm/cpu/armv7/dove/usb.c
new file mode 100644
index 0000000..1b932db
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/usb.c
@@ -0,0 +1,101 @@
+/*
+ * Marvell Dove SoC USB PHY init
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+
+/* Dove USB2.0 PHY registers */
+#define USB20_POWER_CTRL		((base) + 0x400)
+#define USB20_PHY_PLL_CTRL		((base) + 0x410)
+#define  PHY_PLL_VCO_RECALIBRATE	(1 << 21)
+#define USB20_PHY_TX_CTRL		((base) + 0x420)
+#define  PHY_TX_HS_STRESS_CTRL		(1 << 31)
+#define  PHY_TX_BLOCK_EN		(1 << 21)
+#define  PHY_TX_IMP_CAL_VTH(x)		(x << 14)
+#define  PHY_TX_IMP_CAL_VTH_MASK	PHY_TX_IMP_CAL_VTH(0x7)
+#define  PHY_TX_RCAL_START		(1 << 12)
+#define  PHY_TX_LOWVDD_EN		(1 << 11)
+#define USB20_PHY_RX_CTRL		((base) + 0x430)
+#define  PHY_RX_EDGE_DET(x)		(x << 26)
+#define  PHY_RX_EDGE_DET_MASK		PHY_RX_EDGE_DET(0x3)
+#define  PHY_RX_CDR_FASTLOCK_EN		(1 << 21)
+#define  PHY_RX_SQ_LENGTH(x)		(x << 15)
+#define  PHY_RX_SQ_LENGTH_MASK		PHY_RX_SQ_LENGTH(0x3)
+#define  PHY_RX_SQ_THRESH(x)		(x << 4)
+#define  PHY_RX_SQ_THRESH_MASK		PHY_RX_SQ_THRESH(0xf)
+#define  PHY_RX_LPF_COEFF(x)		(x << 2)
+#define  PHY_RX_LPF_COEFF_MASK		PHY_RX_LPF_COEFF(0x3)
+#define USB20_PHY_IVREF_CTRL		((base) + 0x440)
+#define  PHY_IVREF_TXVDD12(x)		(x << 8)
+#define  PHY_IVREF_TXVDD12_MASK		PHY_IVREF_TXVDD12(0x3)
+#define USB20_PHY_TESTGRP_CTRL		((base) + 0x450)
+#define  PHY_TESTGRP_SQ_RST		(1 << 15)
+
+void dove_ehci_phy_init(int port)
+{
+	u32 base = (port == 0) ? DOVE_USB20_0_BASE : DOVE_USB20_1_BASE;
+	u32 reg;
+
+	/* USB PHY PLL control */
+	reg = readl(USB20_PHY_PLL_CTRL);
+	writel(reg | PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
+	udelay(100);
+	writel(reg & ~PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
+
+	/* USB PHY Tx control */
+	reg = readl(USB20_PHY_TX_CTRL);
+	reg &= ~PHY_TX_IMP_CAL_VTH_MASK;
+	reg |= PHY_TX_IMP_CAL_VTH(0x5);
+	reg |= PHY_TX_LOWVDD_EN;
+	reg |= PHY_TX_RCAL_START;
+	reg |= PHY_TX_BLOCK_EN;
+	reg |= PHY_TX_HS_STRESS_CTRL;
+	writel(reg, USB20_PHY_TX_CTRL);
+	udelay(100);
+	writel(reg & ~PHY_TX_RCAL_START, USB20_PHY_TX_CTRL);
+
+	/* USB PHY RX control */
+	reg = readl(USB20_PHY_RX_CTRL);
+	reg &= ~(PHY_RX_LPF_COEFF_MASK | PHY_RX_SQ_THRESH_MASK |
+		 PHY_RX_SQ_LENGTH_MASK | PHY_RX_EDGE_DET_MASK);
+	reg |= PHY_RX_LPF_COEFF(0x1);
+	reg |= PHY_RX_SQ_THRESH(0xc);
+	reg |= PHY_RX_SQ_LENGTH(0x1);
+	reg |= PHY_RX_EDGE_DET(0x0);
+	reg &= ~PHY_RX_CDR_FASTLOCK_EN;
+	writel(reg, USB20_PHY_RX_CTRL);
+
+	/* USB PHY IVREF control */
+	reg = readl(USB20_PHY_IVREF_CTRL);
+	reg &= ~PHY_IVREF_TXVDD12_MASK;
+	reg |= PHY_IVREF_TXVDD12(0x3);
+	writel(reg, USB20_PHY_IVREF_CTRL);
+
+	/* USB PHY TEST GROUP control */
+	reg = readl(USB20_PHY_TESTGRP_CTRL);
+	reg &= ~PHY_TESTGRP_SQ_RST;
+	writel(reg, USB20_PHY_TESTGRP_CTRL);
+}
diff --git a/arch/arm/include/asm/arch-dove/config.h b/arch/arm/include/asm/arch-dove/config.h
new file mode 100644
index 0000000..2d94a48
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/config.h
@@ -0,0 +1,153 @@
+/*
+ * Marvell SoC config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_CONFIG_H
+#define _DOVE_CONFIG_H
+
+#include <asm/arch/dove.h>
+
+#define CONFIG_ARMV7			/* Basic Architecture */
+#define CONFIG_DOVE			/* SOC Family Name */
+#define CONFIG_SHEEVA_88SV581		/* CPU Core subversion */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+				/* default Dcache Line length for Dove */
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#define CONFIG_SYS_DCACHE_OFF		/* Disable DCache by default */
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Dove has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#define CONFIG_I2C_MVTWSI_BASE	DOVE_TWSI_BASE
+#define MV_UART_CONSOLE_BASE	DOVE_UART0_BASE
+#define MV_SATA_BASE		DOVE_SATA_BASE
+#define MV_SATA_PORT0_OFFSET	DOVE_SATA_PORT0_OFFSET
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD		1
+#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL		1
+#endif
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI			1
+#define CONFIG_ORION_SPI		1
+#define ORION_SPI_BASE			DOVE_SPI_BASE
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS		0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS		0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ		25000000
+#endif
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_PHYLIB
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SDHCI
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_SDHCI
+#define CONFIG_DOVE_SDHCI	/* Enable Dove SDHCI controller driver */
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS
+#define CONFIG_SYS_MMC_MAX_DEVICE	2
+#endif
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * IDE Support on SATA ports
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#ifndef CONFIG_SOFT_I2C
+#define CONFIG_I2C_MVTWSI
+#endif
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#endif /* _DOVE_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-dove/cpu.h b/arch/arm/include/asm/arch-dove/cpu.h
new file mode 100644
index 0000000..718dd59
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/cpu.h
@@ -0,0 +1,204 @@
+/*
+ * Marvell Dove SoC CPU
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVECPU_H
+#define _DOVECPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define DOVECPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+			| (attr << 8) | (dove_winctrl_calcsize(size) << 16))
+
+#define DOVEGBE_PORT_SERIAL_CONTROL1_REG	(DOVE_EGIGA_BASE + 0x44c)
+#define DOVE_REG_PCIE_DEVID			(DOVE_REG_PCIE0_BASE + 0x00)
+#define DOVE_REG_PCIE_REVID			(DOVE_REG_PCIE0_BASE + 0x08)
+#define DOVE_REG_SYSRST_CNT			(DOVE_MPP_BASE + 0x50)
+#define SYSRST_CNT_1SEC_VAL			(25*1000000)
+#define DOVE_REG_MPP_OUT_DRV_REG		(DOVE_MPP_BASE + 0xE0)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+};
+
+enum dovecpu_winen {
+	DOVECPU_WIN_DISABLE,
+	DOVECPU_WIN_ENABLE
+};
+
+enum dovecpu_target {
+	DOVECPU_TARGET_DRAM = 0x0,
+	DOVECPU_TARGET_SASRAM = 0x3,
+	DOVECPU_TARGET_NAND = 0xc,
+	DOVECPU_TARGET_PMURAM = 0xd,
+	DOVECPU_TARGET_PCIE0 = 0x4,
+	DOVECPU_TARGET_PCIE1 = 0x8,
+	DOVECPU_TARGET_SPI = 0x1,
+	DOVECPU_TARGET_BOOTROM = 0x1,
+};
+
+enum dovecpu_attrib {
+	DOVECPU_ATTR_DRAM = 0x00,
+	DOVECPU_ATTR_SASRAM = 0x00,
+	DOVECPU_ATTR_NAND = 0x00,
+	DOVECPU_ATTR_PMURAM = 0x00,
+	DOVECPU_ATTR_PCIE_IO = 0xe0,
+	DOVECPU_ATTR_PCIE_MEM = 0xe8,
+	DOVECPU_ATTR_SPI0 = 0xfe,
+	DOVECPU_ATTR_SPI1 = 0xfb,
+	DOVECPU_ATTR_BOOTROM = 0xfd,
+};
+
+enum dovecpu_part {
+	DOVECPU_PART_SHEEVA = 0x581,
+};
+
+enum dovesoc_devid {
+	DOVESOC_DEVID_F6781 = 0x6781,
+	DOVESOC_DEVID_AP510 = 0x0510,
+};
+
+enum dovesoc_revid {
+	DOVESOC_REVID_Z0 = 0,
+	DOVESOC_REVID_Z1 = 1,
+	DOVESOC_REVID_Y0 = 2,
+	DOVESOC_REVID_Y1 = 3,
+	DOVESOC_REVID_X0 = 4,
+	DOVESOC_REVID_A0 = 6,
+	DOVESOC_REVID_A1 = 7,
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define DOVE_DEFADR_PCIE0_MEM		0xe0000000
+#define DOVE_DEFADR_PCIE0_IO		0xf2000000
+#define DOVE_DEFADR_PCIE0_IO_REMAP	0x00000000
+#define DOVE_DEFADR_PCIE1_MEM		0xe8000000
+#define DOVE_DEFADR_PCIE1_IO		0xf2100000
+#define DOVE_DEFADR_PCIE1_IO_REMAP	0x00100000
+#define DOVE_DEFADR_SASRAM		0xc8000000
+#define DOVE_DEFADR_BOOTROM		0xf8000000
+#define DOVE_DEFADR_PMURAM		0xf0000000
+
+/*
+ * ARM CPUID register
+ */
+#define ARM_ID_REVISION_OFFSET	0
+#define ARM_ID_REVISION_MASK	0xf
+#define ARM_ID_PARTNUM_OFFSET	4
+#define ARM_ID_PARTNUM_MASK	0xfff
+#define ARM_ID_ARCH_OFFSET	16
+#define ARM_ID_ARCH_MASK	0xf
+#define ARM_ID_VAR_OFFSET	20
+#define ARM_ID_VAR_MASK		0xf
+#define ARM_ID_ASCII_OFFSET	24
+#define ARM_ID_ASCII_MASK	0xff
+
+/*
+ * read feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+	unsigned int val;
+	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
+			(val) : : "cc");
+	return val;
+}
+
+/*
+ * write feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
+			(val) : "cc");
+	isb();
+}
+
+/*
+ * Downstream Bridge Registers
+ */
+struct dovewin_registers {
+	u32 ctrl;
+	u32 base;
+	u32 remap_lo;
+	u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ */
+struct dovecpu_registers {
+	u32 config;		/* 0x20100 */
+	u32 ctrl_stat;		/* 0x20104 */
+	u32 rstoutn_mask;	/* 0x20108 */
+	u32 sys_soft_rst;	/* 0x2010C */
+	u32 bridge_cause_irq;	/* 0x20110 */
+	u32 bridge_mask_irq;	/* 0x20114 */
+	u32 pad1;
+	u32 pmu_ctrl;		/* 0x2011c */
+};
+
+/*
+ * GPIO 0/1 Registers
+ * GPIO 2 Registers (no datain/irq)
+ */
+struct dovegpio_registers {
+	u32 dout;
+	u32 oe;
+	u32 blink_en;
+	u32 din_pol;
+	u32 din;
+	u32 irq_cause;
+	u32 irq_mask;
+	u32 irq_level;
+};
+
+struct dove_gpio_init {
+	u32 val0;
+	u32 val1;
+	u32 val2;
+	u32 oe0_n;
+	u32 oe1_n;
+	u32 oe2_n;
+};
+
+/*
+ * functions
+ */
+void reset_cpu(unsigned long ignored);
+unsigned char get_random_hex(void);
+u32 dove_dram_start(enum memory_bank bank);
+u32 dove_dram_size(enum memory_bank bank);
+int dove_config_adr_windows(void);
+void dove_init_gpio(struct dove_gpio_init *);
+unsigned int dove_winctrl_calcsize(unsigned int sizeval);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _DOVECPU_H */
diff --git a/arch/arm/include/asm/arch-dove/dove.h b/arch/arm/include/asm/arch-dove/dove.h
new file mode 100644
index 0000000..da5011b
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/dove.h
@@ -0,0 +1,93 @@
+/*
+ * Marvell Dove SoC register offsets and config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_H
+#define _DOVE_H
+
+/* Dove TCLK is fixed to 166MHz */
+#define CONFIG_SYS_TCLK			166666667
+
+/* SOC specific definitions */
+#define DOVE_PREMAP_REGS_PHYS_BASE	0xd0000000
+#define DOVE_PREMAP_INT_REGS_BASE_ADDR  (DOVE_PREMAP_REGS_PHYS_BASE + 0x20080)
+#define DOVE_PREMAP_MC_DECODE_REG       (DOVE_PREMAP_REGS_PHYS_BASE + 0x800010)
+
+#define DOVE_SB_REGS_PHYS_BASE		0xf1000000
+#define DOVE_NB_REGS_PHYS_BASE		0xf1800000
+#define DOVE_REGISTER(x)		(DOVE_SB_REGS_PHYS_BASE + x)
+
+#define DOVE_AXI_CTRL_REG		(DOVE_REGISTER(0xd0224))
+#define DOVE_CPU_CTRL_REG		(DOVE_REGISTER(0xd025c))
+#define DOVE_MC_CTRL_REG		(DOVE_REGISTER(0xd0260))
+#define DOVE_MC_DECODE_REG		(DOVE_REGISTER(0x800010))
+
+#define DOVE_SPI_BASE			(DOVE_REGISTER(0x10600))
+#define DOVE_TWSI_BASE			(DOVE_REGISTER(0x11000))
+#define DOVE_UART0_BASE			(DOVE_REGISTER(0x12000))
+#define DOVE_UART1_BASE			(DOVE_REGISTER(0x12100))
+#define DOVE_UART2_BASE			(DOVE_REGISTER(0x12200))
+#define DOVE_UART3_BASE			(DOVE_REGISTER(0x12300))
+#define DOVE_CPU_WIN_BASE		(DOVE_REGISTER(0x20000))
+#define DOVE_CPU_REG_BASE		(DOVE_REGISTER(0x20100))
+#define DOVE_TIMER_BASE			(DOVE_REGISTER(0x20300))
+#define DOVE_REG_PCIE0_BASE		(DOVE_REGISTER(0x40000))
+#define DOVE_REG_PCIE1_BASE		(DOVE_REGISTER(0x80000))
+#define DOVE_USB20_0_BASE		(DOVE_REGISTER(0x50000))
+#define DOVE_USB20_1_BASE		(DOVE_REGISTER(0x51000))
+#define DOVE_EGIGA_BASE			(DOVE_REGISTER(0x72000))
+#define DOVE_SDIO1_BASE			(DOVE_REGISTER(0x90000))
+#define DOVE_SDIO0_BASE			(DOVE_REGISTER(0x92000))
+#define DOVE_CAMERA_BASE		(DOVE_REGISTER(0x94000))
+#define DOVE_SATA_BASE			(DOVE_REGISTER(0xa0000))
+#define DOVE_NANDF_BASE			(DOVE_REGISTER(0xc0000))
+#define DOVE_PMU_BASE			(DOVE_REGISTER(0xd0000))
+#define DOVE_MPP_BASE			(DOVE_REGISTER(0xd0200))
+#define DOVE_GPIO0_BASE			(DOVE_REGISTER(0xd0400))
+#define DOVE_GPIO1_BASE			(DOVE_REGISTER(0xd0420))
+#define DOVE_RTC_BASE			(DOVE_REGISTER(0xd8500))
+#define DOVE_AC97_BASE			(DOVE_REGISTER(0xe0000))
+#define DOVE_PDMA_BASE			(DOVE_REGISTER(0xe4000))
+#define DOVE_GPIO2_BASE			(DOVE_REGISTER(0xe8400))
+#define DOVE_SSP_BASE			(DOVE_REGISTER(0xec000))
+
+/* Dove Sata controller has one port */
+#define DOVE_SATA_PORT0_OFFSET		0x2000
+
+/* Dove GbE controller has one port */
+#define MAX_MVGBE_DEVS			1
+#define MVGBE0_BASE			DOVE_EGIGA_BASE
+
+/* Dove USB Host controller */
+#define MVUSB0_BASE			DOVE_USB20_0_BASE
+#define MVUSB0_CPU_ATTR_DRAM_CS0	DOVECPU_ATTR_DRAM
+#define MVUSB0_CPU_ATTR_DRAM_CS1	DOVECPU_ATTR_DRAM
+#define MVUSB0_CPU_ATTR_DRAM_CS2	DOVECPU_WIN_DISABLE
+#define MVUSB0_CPU_ATTR_DRAM_CS3	DOVECPU_WIN_DISABLE
+
+/* Dove CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA		DOVECPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE		DOVECPU_WIN_ENABLE
+#define MVCPU_WIN_DISABLE		DOVECPU_WIN_DISABLE
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/gpio.h b/arch/arm/include/asm/arch-dove/gpio.h
new file mode 100644
index 0000000..71bef8e
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Marvell Dove SoC gpio
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __DOVE_GPIO_H
+#define __DOVE_GPIO_H
+
+#include <orion_gpio.h>
+
+#define GPIO_MAX		70
+#define GPIO_BASE(pin)		(((pin) >= 64) ? DOVE_GPIO2_BASE : \
+				 ((pin) >= 32) ? DOVE_GPIO1_BASE : \
+				 DOVE_GPIO0_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/mpp.h b/arch/arm/include/asm/arch-dove/mpp.h
new file mode 100644
index 0000000..1279ac2
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/mpp.h
@@ -0,0 +1,283 @@
+/*
+ * Marvell Dove SoC pinmux
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_MPP_H
+#define _DOVE_MPP_H
+
+#define DOVE_GPI	(1 << 0)
+#define DOVE_GPO	(1 << 1)
+#define DOVE_GPIO	(DOVE_GPO | DOVE_GPI)
+
+#define MPP(_num, _sel, _gpio) (			 \
+	/* MPP number */	((_num) & 0xff) |	 \
+	/* MPP select value */	(((_sel) & 0x1f) << 8) | \
+	/* is gpio config */	((!!(_gpio)) << 15))
+
+/* MPP0-15 allow PMU function */
+#define MPP_PMU_MAX		15
+#define PMU			(0x10)
+/* MPP0-23 have standard mpp register layout */
+#define MPP_STD_MAX		23
+
+#define MPP0			0
+#define MPP0_GPIO		MPP(0, 0x0, 1)
+#define MPP0_UART2_RTS		MPP(0, 0x2, 0)
+#define MPP0_SDIO0_CD		MPP(0, 0x3, 0)
+#define MPP0_LCD0_PWM		MPP(0, 0xf, 0)
+#define MPP0_PMU		MPP(0, PMU, 0)
+
+#define MPP1			1
+#define MPP1_GPIO		MPP(1, 0x0, 1)
+#define MPP1_UART2_CTS		MPP(1, 0x2, 0)
+#define MPP1_SDIO0_WP		MPP(1, 0x3, 0)
+#define MPP1_LCD1_PWM		MPP(1, 0xf, 0)
+#define MPP1_PMU		MPP(1, PMU, 0)
+
+#define MPP2			2
+#define MPP2_GPIO		MPP(2, 0x0, 1)
+#define MPP2_SATA_PRSNT		MPP(2, 0x1, 0)
+#define MPP2_UART2_TXD		MPP(2, 0x2, 0)
+#define MPP2_SDIO0_BUSPWR	MPP(2, 0x3, 0)
+#define MPP2_UART1_RTS		MPP(2, 0x4, 0)
+#define MPP2_PMU		MPP(2, PMU, 0)
+
+#define MPP3			3
+#define MPP3_GPIO		MPP(3, 0x0, 1)
+#define MPP3_SATA_ACT		MPP(3, 0x1, 0)
+#define MPP3_UART2_RXD		MPP(3, 0x2, 0)
+#define MPP3_SDIO0_LEDCTRL	MPP(3, 0x3, 0)
+#define MPP3_UART1_CTS		MPP(3, 0x4, 0)
+#define MPP3_LCD_SPI_CS1	MPP(3, 0xf, 0)
+#define MPP3_PMU		MPP(3, PMU, 0)
+
+#define MPP4			4
+#define MPP4_GPIO		MPP(4, 0x0, 1)
+#define MPP4_UART3_RTS		MPP(4, 0x2, 0)
+#define MPP4_SDIO1_CD		MPP(4, 0x3, 0)
+#define MPP4_SPI1_MISO		MPP(4, 0x4, 0)
+#define MPP4_PMU		MPP(4, PMU, 0)
+
+#define MPP5			5
+#define MPP5_GPIO		MPP(5, 0x0, 1)
+#define MPP5_UART3_CTS		MPP(5, 0x2, 0)
+#define MPP5_SDIO1_WP		MPP(5, 0x3, 0)
+#define MPP5_SPI1_CS		MPP(5, 0x4, 0)
+#define MPP5_PMU		MPP(5, PMU, 0)
+
+#define MPP6			6
+#define MPP6_GPIO		MPP(6, 0x0, 1)
+#define MPP6_UART3_TXD		MPP(6, 0x2, 0)
+#define MPP6_SDIO1_BUSPWR	MPP(6, 0x3, 0)
+#define MPP6_SPI1_MOSI		MPP(6, 0x4, 0)
+#define MPP6_PMU		MPP(6, PMU, 0)
+
+#define MPP7			7
+#define MPP7_GPIO		MPP(7, 0x0, 1)
+#define MPP7_UART3_RXD		MPP(7, 0x2, 0)
+#define MPP7_SDIO1_LEDCTRL	MPP(7, 0x3, 0)
+#define MPP7_SPI1_SCK		MPP(7, 0x4, 0)
+#define MPP7_PMU		MPP(7, PMU, 0)
+
+#define MPP8			8
+#define MPP8_GPIO		MPP(8, 0x0, 1)
+#define MPP8_WATCHDOG_RSTOUT	MPP(8, 0x1, 0)
+#define MPP8_PMU		MPP(8, PMU, 0)
+
+#define MPP9			9
+#define MPP9_GPIO		MPP(9, 0x0, 1)
+#define MPP9_PEX1_CLKREQ	MPP(9, 0x5, 0)
+#define MPP9_PMU		MPP(9, PMU, 0)
+
+#define MPP10			10
+#define MPP10_GPIO		MPP(10, 0x0, 1)
+#define MPP10_SSP_SCLK		MPP(10, 0x5, 0)
+#define MPP10_PMU		MPP(10, PMU, 0)
+
+#define MPP11			11
+#define MPP11_GPIO		MPP(11, 0x0, 1)
+#define MPP11_SATA_PRSNT	MPP(11, 0x1, 0)
+#define MPP11_SATA_ACT		MPP(11, 0x2, 0)
+#define MPP11_SDIO0_LEDCTRL	MPP(11, 0x3, 0)
+#define MPP11_SDIO1_LEDCTRL	MPP(11, 0x4, 0)
+#define MPP11_PEX0_CLKREQ	MPP(11, 0x5, 0)
+#define MPP11_PMU		MPP(11, PMU, 0)
+
+#define MPP12			12
+#define MPP12_GPIO		MPP(12, 0x0, 1)
+#define MPP12_SATA_ACT		MPP(12, 0x1, 0)
+#define MPP12_UART2_RTS		MPP(12, 0x2, 0)
+#define MPP12_AUDIO0_EXTCLK	MPP(12, 0x3, 0)
+#define MPP12_SDIO1_CD		MPP(12, 0x4, 0)
+#define MPP12_PMU		MPP(12, PMU, 0)
+
+#define MPP13			13
+#define MPP13_GPIO		MPP(13, 0x0, 1)
+#define MPP13_UART2_CTS		MPP(13, 0x2, 0)
+#define MPP13_AUDIO1_EXTCLK	MPP(13, 0x3, 0)
+#define MPP13_SDIO1_WP		MPP(13, 0x4, 0)
+#define MPP13_SSP_EXTCLK	MPP(13, 0x5, 0)
+#define MPP13_PMU		MPP(13, PMU, 0)
+
+#define MPP14			14
+#define MPP14_GPIO		MPP(14, 0x0, 1)
+#define MPP14_UART2_TXD		MPP(14, 0x2, 0)
+#define MPP14_SDIO1_BUSPWR	MPP(14, 0x4, 0)
+#define MPP14_SSP_TXD		MPP(14, 0x5, 0)
+#define MPP14_PMU		MPP(14, PMU, 0)
+
+#define MPP15			15
+#define MPP15_GPIO		MPP(15, 0x0, 1)
+#define MPP15_UART2_RXD		MPP(15, 0x2, 0)
+#define MPP15_SDIO1_LEDCTRL	MPP(15, 0x4, 0)
+#define MPP15_SSP_SFRM		MPP(15, 0x5, 0)
+#define MPP15_PMU		MPP(15, PMU, 0)
+
+#define MPP16			16
+#define MPP16_GPIO		MPP(16, 0x0, 1)
+#define MPP16_UART3_RTS		MPP(16, 0x2, 0)
+#define MPP16_SDIO0_CD		MPP(16, 0x3, 0)
+#define MPP16_LCD_SPI_CS1	MPP(16, 0x4, 0)
+#define MPP16_AC97_SDI1		MPP(16, 0x5, 0)
+
+#define MPP17			17
+#define MPP17_GPIO		MPP(17, 0x0, 1)
+#define MPP17_AC97_SYSCLKO	MPP(17, 0x1, 0)
+#define MPP17_UART3_CTS		MPP(17, 0x2, 0)
+#define MPP17_SDIO0_WP		MPP(17, 0x3, 0)
+#define MPP17_TWSI_SDA		MPP(17, 0x4, 0)
+#define MPP17_AC97_SDI2		MPP(17, 0x5, 0)
+
+#define MPP18			18
+#define MPP18_GPIO		MPP(18, 0x0, 1)
+#define MPP18_UART3_TXD		MPP(18, 0x2, 0)
+#define MPP18_SDIO0_BUSPWR	MPP(18, 0x3, 0)
+#define MPP18_LCD0_PWM		MPP(18, 0x4, 0)
+#define MPP18_AC97_SDI3		MPP(18, 0x5, 0)
+
+#define MPP19			19
+#define MPP19_GPIO		MPP(19, 0x0, 1)
+#define MPP19_UART3_RXD		MPP(19, 0x2, 0)
+#define MPP19_SDIO0_LEDCTRL	MPP(19, 0x3, 0)
+#define MPP19_TWSI_SCK		MPP(19, 0x4, 0)
+
+#define MPP20			20
+#define MPP20_GPIO		MPP(20, 0x0, 1)
+#define MPP20_AC97_SYSCLKO	MPP(20, 0x1, 0)
+#define MPP20_LCD_SPI_MISO	MPP(20, 0x2, 0)
+#define MPP20_SDIO1_CD		MPP(20, 0x3, 0)
+#define MPP20_SDIO0_CD		MPP(20, 0x5, 0)
+#define MPP20_SPI1_MISO		MPP(20, 0x6, 0)
+
+#define MPP21			21
+#define MPP21_GPIO		MPP(21, 0x0, 1)
+#define MPP21_UART1_RTS		MPP(21, 0x1, 0)
+#define MPP21_LCD_SPI_CS0	MPP(21, 0x2, 0)
+#define MPP21_SDIO1_WP		MPP(21, 0x3, 0)
+#define MPP21_SSP_SFRM		MPP(21, 0x4, 0)
+#define MPP21_SDIO0_WP		MPP(21, 0x5, 0)
+#define MPP21_SPI1_CS		MPP(21, 0x6, 0)
+
+#define MPP22			22
+#define MPP22_GPIO		MPP(22, 0x0, 1)
+#define MPP22_UART1_CTS		MPP(22, 0x1, 0)
+#define MPP22_LCD_SPI_MOSI	MPP(22, 0x2, 0)
+#define MPP22_SDIO1_BUSPWR	MPP(22, 0x3, 0)
+#define MPP22_SSP_TXD		MPP(22, 0x4, 0)
+#define MPP22_SDIO0_BUSPWR	MPP(22, 0x5, 0)
+#define MPP22_SPI1_MOSI		MPP(22, 0x6, 0)
+
+#define MPP23			23
+#define MPP23_GPIO		MPP(23, 0x0, 1)
+#define MPP23_LCD_SPI_SCK	MPP(23, 0x2, 0)
+#define MPP23_SDIO1_LEDCTRL	MPP(23, 0x3, 0)
+#define MPP23_SSP_SCLK		MPP(23, 0x4, 0)
+#define MPP23_SDIO0_LEDCTRL	MPP(23, 0x5, 0)
+#define MPP23_SPI1_SCK		MPP(23, 0x6, 0)
+
+/* MPP_CAMERA = MPP[24:39] */
+#define MPP_CAMERA		24
+#define MPP_CAMERA_CAMERA	MPP(24, 0x0, 0)
+#define MPP_CAMERA_GPIO		MPP(24, 0x1, 1)
+#define MPP_CAMERA_MAX		39
+
+/* MPP_SDIO0 = MPP[40:45] */
+#define MPP_SDIO0		40
+#define MPP_SDIO0_SDIO		MPP(40, 0x0, 0)
+#define MPP_SDIO0_GPIO		MPP(40, 0x1, 1)
+#define MPP_SDIO0_MAX		45
+
+/* MPP_SDIO1 = MPP[46:51] */
+#define MPP_SDIO1		46
+#define MPP_SDIO1_SDIO		MPP(46, 0x0, 0)
+#define MPP_SDIO1_GPIO		MPP(46, 0x1, 1)
+#define MPP_SDIO1_MAX		51
+
+/* MPP_AUDIO1 = MPP[52:57] */
+#define MPP_AUDIO1		52
+#define MPP_AUDIO1_I2S_SPDIFO	MPP(52, 0x0, 0)
+#define MPP_AUDIO1_I2S		MPP(52, 0x2, 0)
+#define MPP_AUDIO1_SPDIFO	MPP(52, 0x8, 0)
+#define MPP_AUDIO1_GPIO		MPP(52, 0xa, 1)
+#define MPP_AUDIO1_TWSI		MPP(52, 0xb, 0)
+#define MPP_AUDIO1_SSP_SPDIFO	MPP(52, 0xc, 0)
+#define MPP_AUDIO1_SSP		MPP(52, 0xe, 0)
+#define MPP_AUDIO1_SSP_TWSI	MPP(52, 0xf, 0)
+#define MPP_AUDIO1_MAX		57
+
+/* MPP_SPI = MPP[58:61] */
+#define MPP_SPI			58
+#define MPP_SPI_SPI		MPP(58, 0x0, 0)
+#define MPP_SPI_GPIO		MPP(58, 0x1, 1)
+#define MPP_SPI_MAX		61
+
+/* MPP_UART1 = MPP[62:63] */
+#define MPP_UART1		62
+#define MPP_UART1_UART1		MPP(62, 0x0, 0)
+#define MPP_UART1_GPIO		MPP(62, 0x1, 1)
+#define MPP_UART1_MAX		63
+
+/* MPP_NAND = MPP[64:71] */
+#define MPP_NAND		64
+#define MPP_NAND_NAND		MPP(64, 0x0, 0)
+#define MPP_NAND_GPO		MPP(64, 0x1, 1)
+#define MPP_NAND_MAX		71
+
+/* MPP_AUDIO0 = Internal AC97/I2S mux for audio0 pins */
+#define MPP_AUDIO0		72
+#define MPP_AUDIO0_I2S		MPP(72, 0x0, 0)
+#define MPP_AUDIO0_AC97		MPP(72, 0x1, 0)
+
+/* MPP_TWSI = Internal TWSI option mux */
+#define MPP_TWSI		73
+#define MPP_TWSI_NONE		MPP(73, 0x0, 0)
+#define MPP_TWSI_OPTION1	MPP(73, 0x1, 0)
+#define MPP_TWSI_OPTION2	MPP(73, 0x2, 0)
+#define MPP_TWSI_OPTION3	MPP(73, 0x3, 0)
+
+#define MPP_MAX			MPP_TWSI
+
+u8 dove_mpp_get_gpio_caps(u8 num);
+void dove_mpp_conf(u16 *mpp_list);
+
+#endif
-- 
1.7.10.4

[U-Boot] [PATCH v3 02/10] GPIO: add gpio driver for Orion SoCs

[Sebastian Hesselbarth]

This adds a gpio driver for Marvell Orion SoCs, i.e. orion5x, kirkwood,
dove. This is based on kw_gpio but as gpio capabilities depend heavily
on the mpp configuration for dove, it allows to set gpi/gpo capabilities
from mpp. This should be compatible with the current kw_gpio and porting
mpp of kirkwood and orion5x is appreciated.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/gpio/Makefile     |    1 +
 drivers/gpio/orion_gpio.c |  167 +++++++++++++++++++++++++++++++++++++++++++++
 include/orion_gpio.h      |   64 +++++++++++++++++
 3 files changed, 232 insertions(+)
 create mode 100644 drivers/gpio/orion_gpio.c
 create mode 100644 include/orion_gpio.h

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 2d97b4f..b0ad2b5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ LIB 	:= $(obj)libgpio.o
 
 COBJS-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 COBJS-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
+COBJS-$(CONFIG_ORION_GPIO)	+= orion_gpio.o
 COBJS-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
 COBJS-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
 COBJS-$(CONFIG_MARVELL_MFP)	+= mvmfp.o
diff --git a/drivers/gpio/orion_gpio.c b/drivers/gpio/orion_gpio.c
new file mode 100644
index 0000000..209354d
--- /dev/null
+++ b/drivers/gpio/orion_gpio.c
@@ -0,0 +1,167 @@
+/*
+ * Marvell Orion SoC GPIO handling.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed orion_gpiochip struct and kernel level irq handling.
+ * Dieter Kiermaier dk-arm-linux at gmx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <orion_gpio.h>
+
+static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
+static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
+
+void __set_direction(unsigned pin, int input)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_IO_CONF(base));
+	if (input)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_IO_CONF(base));
+
+	u = readl(GPIO_IO_CONF(base));
+}
+
+void __set_level(unsigned pin, int high)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_OUT(base));
+	if (high)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_OUT(base));
+}
+
+void __set_blinking(unsigned pin, int blink)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_BLINK_EN(base));
+	if (blink)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_BLINK_EN(base));
+}
+
+int orion_gpio_is_valid(unsigned pin, int mode)
+{
+	if (pin < GPIO_MAX) {
+		if ((mode & GPIO_INPUT_OK) &&
+		    !test_bit(pin, gpio_valid_input))
+			goto err_out;
+
+		if ((mode & GPIO_OUTPUT_OK) &&
+		    !test_bit(pin, gpio_valid_output))
+			goto err_out;
+		return 0;
+	}
+
+err_out:
+	printf("%s: invalid GPIO %d/%d\n", __func__, pin, GPIO_MAX);
+	return 1;
+}
+
+void orion_gpio_set_valid(unsigned pin, int mode)
+{
+	if (mode & GPIO_INPUT_OK)
+		__set_bit(pin, gpio_valid_input);
+	else
+		__clear_bit(pin, gpio_valid_input);
+	if (mode & GPIO_OUTPUT_OK)
+		__set_bit(pin, gpio_valid_output);
+	else
+		__clear_bit(pin, gpio_valid_output);
+}
+
+/*
+ * GENERIC_GPIO primitives.
+ */
+int orion_gpio_direction_input(unsigned pin)
+{
+	if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) != 0)
+		return 1;
+
+	/* Configure GPIO direction. */
+	__set_direction(pin, 1);
+
+	return 0;
+}
+
+int orion_gpio_direction_output(unsigned pin, int value)
+{
+	if (orion_gpio_is_valid(pin, GPIO_OUTPUT_OK) != 0) {
+		printf("%s: invalid GPIO %d\n", __func__, pin);
+		return 1;
+	}
+
+	__set_blinking(pin, 0);
+
+	/* Configure GPIO output value. */
+	__set_level(pin, value);
+
+	/* Configure GPIO direction. */
+	__set_direction(pin, 0);
+
+	return 0;
+}
+
+int orion_gpio_get_value(unsigned pin)
+{
+	u32 base = GPIO_BASE(pin);
+	int val;
+
+	if (readl(GPIO_IO_CONF(base)) & (1 << (pin & 31)))
+		val = readl(GPIO_DATA_IN(base)) ^ readl(GPIO_IN_POL(base));
+	else
+		val = readl(GPIO_OUT(base));
+
+	return (val >> (pin & 31)) & 1;
+}
+
+void orion_gpio_set_value(unsigned pin, int value)
+{
+	/* Configure GPIO output value. */
+	__set_level(pin, value);
+}
+
+void orion_gpio_set_blink(unsigned pin, int blink)
+{
+	/* Set output value to zero. */
+	__set_level(pin, 0);
+
+	/* Set blinking. */
+	__set_blinking(pin, blink);
+}
diff --git a/include/orion_gpio.h b/include/orion_gpio.h
new file mode 100644
index 0000000..ba67068
--- /dev/null
+++ b/include/orion_gpio.h
@@ -0,0 +1,64 @@
+/*
+ * Marvell Orion SoCs common gpio
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ORION_GPIO_H
+#define __ORION_GPIO_H
+
+/*
+ * SoC-specific gpio.h defines
+ * GPIO_MAX and GPIO_BASE(pin) macro
+ */
+
+#define GPIO_INPUT_OK		(1 << 0)
+#define GPIO_OUTPUT_OK		(1 << 1)
+#define GPIO_LOW		0
+#define GPIO_HIGH		1
+
+/* got from kernel include/linux/bitops.h */
+#define BITS_PER_BYTE 8
+#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+
+#define GPIO_OUT(base)		((base) + 0x00)
+#define GPIO_IO_CONF(base)	((base) + 0x04)
+#define GPIO_BLINK_EN(base)	((base) + 0x08)
+#define GPIO_IN_POL(base)	((base) + 0x0c)
+#define GPIO_DATA_IN(base)	((base) + 0x10)
+#define GPIO_EDGE_CAUSE(base)	((base) + 0x14)
+#define GPIO_EDGE_MASK(base)	((base) + 0x18)
+#define GPIO_LEVEL_MASK(base)	((base) + 0x1c)
+
+/*
+ * Orion-specific GPIO API
+ */
+
+void orion_gpio_set_valid(unsigned pin, int mode);
+int orion_gpio_is_valid(unsigned pin, int mode);
+int orion_gpio_direction_input(unsigned pin);
+int orion_gpio_direction_output(unsigned pin, int value);
+int orion_gpio_get_value(unsigned pin);
+void orion_gpio_set_value(unsigned pin, int value);
+void orion_gpio_set_blink(unsigned pin, int blink);
+void orion_gpio_set_unused(unsigned pin);
+
+#endif
-- 
1.7.10.4

[U-Boot] [PATCH v3 03/10] MMC: sdhci: Add support for dove sdhci

[Sebastian Hesselbarth]

This adds a driver for the sdhci controller found on Dove SoCs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/mmc/Makefile     |    1 +
 drivers/mmc/dove_sdhci.c |  101 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 102 insertions(+)
 create mode 100644 drivers/mmc/dove_sdhci.c

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 65791aa..f7c731f 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -31,6 +31,7 @@ endif
 
 COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+COBJS-$(CONFIG_DOVE_SDHCI) += dove_sdhci.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
 COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
diff --git a/drivers/mmc/dove_sdhci.c b/drivers/mmc/dove_sdhci.c
new file mode 100644
index 0000000..ac15fd7
--- /dev/null
+++ b/drivers/mmc/dove_sdhci.c
@@ -0,0 +1,101 @@
+/*
+ *
+ * Marvell Dove SDHCI driver
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on linux drivers/mmc/host/sdhci-dove.c
+ * by: Saeed Bishara <saeed@marvell.com>
+ *     Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/arch/dove.h>
+
+static u16 dove_sdhci_readw(struct sdhci_host *host, int reg)
+{
+	u16 ret;
+
+	switch (reg) {
+	case SDHCI_HOST_VERSION:
+	case SDHCI_SLOT_INT_STATUS:
+		/* those registers don't exist */
+		return 0;
+	default:
+		ret = readw(host->ioaddr + reg);
+	}
+
+	return ret;
+}
+
+static u32 dove_sdhci_readl(struct sdhci_host *host, int reg)
+{
+	u32 ret;
+
+	switch (reg) {
+	case SDHCI_CAPABILITIES:
+		ret = readl(host->ioaddr + reg);
+		/* Mask the support for 3.0V */
+		ret &= ~SDHCI_CAN_VDD_300;
+		break;
+	default:
+		ret = readl(host->ioaddr + reg);
+	}
+
+	return ret;
+}
+
+static struct sdhci_ops dove_sdhci_ops = {
+	.read_w	= dove_sdhci_readw,
+	.read_l	= dove_sdhci_readl,
+};
+
+static struct sdhci_host hosts[2] = {
+	{
+		.name = "Dove SDHCI0",
+		.ioaddr = (void *)DOVE_SDIO0_BASE,
+	},
+	{
+		.name = "Dove SDHCI1",
+		.ioaddr = (void *)DOVE_SDIO1_BASE,
+	},
+};
+
+int dove_sdhci_init(int num)
+{
+	struct sdhci_host *host;
+
+	if (num < 0 || num > 1)
+		return 1;
+
+	host = &hosts[num];
+
+	if (host->version)
+		return 1;
+
+	host->quirks =
+		SDHCI_QUIRK_NO_HISPD_BIT |
+		SDHCI_QUIRK_BROKEN_R1B |
+		SDHCI_QUIRK_32BIT_DMA_ADDR;
+	host->version = SDHCI_SPEC_200;
+	host->ops = &dove_sdhci_ops;
+
+	add_sdhci(host, 50000000, 4000000);
+	return 0;
+}
-- 
1.7.10.4

[U-Boot] [PATCH v3 04/10] SPI: Add Orion SPI driver

[Sebastian Hesselbarth]

This adds an SPI driver found on Marvell Orion SoCs. This driver is
taken from kirkwood_spi but removes mpp configuration as dove has
dedicated spi pins. To have a common driver for orion5x, kirkwood,
and dove, mpp configuration should be handled in some cpu/board-specific
setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/spi/Makefile    |    1 +
 drivers/spi/orion_spi.c |  217 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 218 insertions(+)
 create mode 100644 drivers/spi/orion_spi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 824d357..624bb72 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_CF_SPI) += cf_spi.o
 COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
 COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
 COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
+COBJS-$(CONFIG_ORION_SPI) += orion_spi.o
 COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
 COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
diff --git a/drivers/spi/orion_spi.c b/drivers/spi/orion_spi.c
new file mode 100644
index 0000000..8a50531
--- /dev/null
+++ b/drivers/spi/orion_spi.c
@@ -0,0 +1,217 @@
+/*
+ * Marvell Orion SoCs common spi driver
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * based on kirkwood_spi.c written by
+ *  Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/arch/config.h>
+
+/* SPI Registers on orion SOC */
+struct orionspi_registers {
+	u32 ctrl;	/* 0x00 */
+	u32 cfg;	/* 0x04 */
+	u32 dout;	/* 0x08 */
+	u32 din;	/* 0x0c */
+	u32 irq_cause;	/* 0x10 */
+	u32 irq_mask;	/* 0x14 */
+};
+
+#define ORIONSPI_CLKPRESCL_MASK	0x1f
+#define ORIONSPI_CLKPRESCL_MIN	0x12
+#define ORIONSPI_CSN_ACT	1 /* Activates serial memory interface */
+#define ORIONSPI_SMEMRDY	(1 << 1) /* SerMem Data xfer ready */
+#define ORIONSPI_IRQUNMASK	1 /* unmask SPI interrupt */
+#define ORIONSPI_IRQMASK	0 /* mask SPI interrupt */
+#define ORIONSPI_SMEMRDIRQ	1 /* SerMem data xfer ready irq */
+#define ORIONSPI_XFERLEN_1BYTE	0
+#define ORIONSPI_XFERLEN_2BYTE	(1 << 5)
+#define ORIONSPI_XFERLEN_MASK	(1 << 5)
+#define ORIONSPI_ADRLEN_1BYTE	0
+#define ORIONSPI_ADRLEN_2BYTE	(1 << 8)
+#define ORIONSPI_ADRLEN_3BYTE	(2 << 8)
+#define ORIONSPI_ADRLEN_4BYTE	(3 << 8)
+#define ORIONSPI_ADRLEN_MASK	(3 << 8)
+#define ORIONSPI_TIMEOUT	10000
+
+static struct orionspi_registers *spireg =
+	(struct orionspi_registers *)ORION_SPI_BASE;
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				unsigned int max_hz, unsigned int mode)
+{
+	struct spi_slave *slave;
+	u32 data;
+	u32 kwspi_mpp_config[] = { 0, 0 };
+
+	if (!spi_cs_is_valid(bus, cs))
+		return NULL;
+
+	slave = malloc(sizeof(struct spi_slave));
+	if (!slave)
+		return NULL;
+
+	slave->bus = bus;
+	slave->cs = cs;
+
+	writel(~ORIONSPI_CSN_ACT | ORIONSPI_SMEMRDY, &spireg->ctrl);
+
+	/* calculate spi clock prescaller using max_hz */
+	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
+	data = data < ORIONSPI_CLKPRESCL_MIN ? ORIONSPI_CLKPRESCL_MIN : data;
+	data = data > ORIONSPI_CLKPRESCL_MASK ? ORIONSPI_CLKPRESCL_MASK : data;
+
+	/* program spi clock prescaller using max_hz */
+	writel(ORIONSPI_ADRLEN_3BYTE | data, &spireg->cfg);
+	debug("data = 0x%08x\n", data);
+
+	writel(ORIONSPI_SMEMRDIRQ, &spireg->irq_cause);
+	writel(ORIONSPI_IRQMASK, &spireg->irq_mask);
+
+	return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	free(slave);
+}
+
+#if defined(CONFIG_SYS_KW_SPI_MPP)
+u32 spi_mpp_backup[4];
+#endif
+
+__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return board_spi_claim_bus(slave);
+}
+
+__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
+{
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	board_spi_release_bus(slave);
+}
+
+#ifndef CONFIG_SPI_CS_IS_VALID
+/*
+ * you can define this function board specific
+ * define above CONFIG in board specific config file and
+ * provide the function in board specific src file
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return (bus == 0 && (cs == 0 || cs == 1));
+}
+#endif
+
+void spi_init(void)
+{
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	writel(readl(&spireg->ctrl) | ORIONSPI_IRQUNMASK, &spireg->ctrl);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	writel(readl(&spireg->ctrl) & ORIONSPI_IRQMASK, &spireg->ctrl);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	unsigned int tmpdout, tmpdin;
+	int tm, isread = 0;
+
+	debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
+	      slave->bus, slave->cs, dout, din, bitlen);
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	/*
+	 * handle data in 8-bit chunks
+	 * TBD: 2byte xfer mode to be enabled
+	 */
+	writel(((readl(&spireg->cfg) & ~ORIONSPI_XFERLEN_MASK) |
+		ORIONSPI_XFERLEN_1BYTE), &spireg->cfg);
+
+	while (bitlen > 4) {
+		debug("loopstart bitlen %d\n", bitlen);
+		tmpdout = 0;
+
+		/* Shift data so it's msb-justified */
+		if (dout)
+			tmpdout = *(u32 *) dout & 0x0ff;
+
+		writel(~ORIONSPI_SMEMRDIRQ, &spireg->irq_cause);
+		writel(tmpdout, &spireg->dout);	/* Write the data out */
+		debug("*** spi_xfer: ... %08x written, bitlen %d\n",
+		      tmpdout, bitlen);
+
+		/*
+		 * Wait for SPI transmit to get out
+		 * or time out (1 second = 1000 ms)
+		 * The NE event must be read and cleared first
+		 */
+		for (tm = 0, isread = 0; tm < ORIONSPI_TIMEOUT; ++tm) {
+			if (readl(&spireg->irq_cause) & ORIONSPI_SMEMRDIRQ) {
+				isread = 1;
+				tmpdin = readl(&spireg->din);
+				debug
+					("spi_xfer: din %p..%08x read\n",
+					din, tmpdin);
+
+				if (din) {
+					*((u8 *) din) = (u8) tmpdin;
+					din += 1;
+				}
+				if (dout)
+					dout += 1;
+				bitlen -= 8;
+			}
+			if (isread)
+				break;
+		}
+		if (tm >= ORIONSPI_TIMEOUT)
+			printf("*** spi_xfer: Time out during SPI transfer\n");
+
+		debug("loopend bitlen %d\n", bitlen);
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	return 0;
+}
-- 
1.7.10.4

[U-Boot] [PATCH v3 05/10] block: mvsata: add dove include

[Sebastian Hesselbarth]

Dove SoC also uses mvsata, therefore add a SoC specific include to
allow to reuse the mvsata ide driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
--
 drivers/block/mvsata_ide.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index a88d0f7..9918f80 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -29,6 +29,8 @@
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 /* SATA port registers */
-- 
1.7.10.4

[U-Boot] [PATCH v3 06/10] NET: phy: add 88E1310 PHY initialization

[Sebastian Hesselbarth]

This adds PHY initialization for Marvell Alaska 88E1310 PHY.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/net/phy/marvell.c |   48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 4b27198..1205166 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -89,6 +89,12 @@
 
 #define MIIM_88E1149_PHY_PAGE	29
 
+/* 88E1310 PHY defines */
+#define MIIM_88E1310_PHY_LED_CTRL	16
+#define MIIM_88E1310_PHY_IRQ_EN		18
+#define MIIM_88E1310_PHY_RGMII_CTRL	21
+#define MIIM_88E1310_PHY_PAGE		22
+
 /* Marvell 88E1011S */
 static int m88e1011s_config(struct phy_device *phydev)
 {
@@ -394,6 +400,37 @@ static int m88e1149_config(struct phy_device *phydev)
 	return 0;
 }
 
+/* Marvell 88E1310 */
+static int m88e1310_config(struct phy_device *phydev)
+{
+	u16 reg;
+
+	/* LED link and activity */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
+	reg = (reg & ~0xf) | 0x1;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
+
+	/* Set LED2/INT to INT mode, low active */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
+	reg = (reg & 0x77ff) | 0x0880;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
+
+	/* Set RGMII delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
+	reg |= 0x0030;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
+
+	/* Ensure to return to page 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
+
+	genphy_config_aneg(phydev);
+	phy_reset(phydev);
+
+	return 0;
+}
 
 static struct phy_driver M88E1011S_driver = {
 	.name = "Marvell 88E1011S",
@@ -465,8 +502,19 @@ static struct phy_driver M88E1149S_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver M88E1310_driver = {
+	.name = "Marvell 88E1310",
+	.uid = 0x01410e90,
+	.mask = 0xffffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &m88e1310_config,
+	.startup = &m88e1011s_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 int phy_marvell_init(void)
 {
+	phy_register(&M88E1310_driver);
 	phy_register(&M88E1149S_driver);
 	phy_register(&M88E1145_driver);
 	phy_register(&M88E1121R_driver);
-- 
1.7.10.4

[U-Boot] [PATCH v3 07/10] NET: mvgbe: add phylib support

[Sebastian Hesselbarth]

This add phylib support to the Marvell GBE driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/net/mvgbe.c |   68 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 64 insertions(+), 4 deletions(-)

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 47bf27c..192c989 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MV_PHY_ADR_REQUEST 0xee
 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 /*
  * smi_reg_read - miiphy_read callback function.
  *
@@ -184,6 +184,24 @@ static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
 }
 #endif
 
+#if defined(CONFIG_PHYLIB)
+int mvgbe_phy_read(struct mii_dev *bus, int phyAddr, int devAddr, int regAddr)
+{
+	u16 data;
+	int ret;
+	ret = smi_reg_read(bus->name, phyAddr, regAddr, &data);
+	if (ret)
+		return ret;
+	return data;
+}
+
+int mvgbe_phy_write(struct mii_dev *bus, int phyAddr, int devAddr, int regAddr,
+	u16 data)
+{
+	return smi_reg_write(bus->name, phyAddr, regAddr, data);
+}
+#endif
+
 /* Stop and checks all queues */
 static void stop_queue(u32 * qreg)
 {
@@ -467,8 +485,9 @@ static int mvgbe_init(struct eth_device *dev)
 	/* Enable port Rx. */
 	MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
 
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
-	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))   \
+	&& !defined(CONFIG_PHYLIB)		       \
+	&& defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 	/* Wait up to 5s for the link status */
 	for (i = 0; i < 5; i++) {
 		u16 phyadr;
@@ -647,6 +666,45 @@ static int mvgbe_recv(struct eth_device *dev)
 	return 0;
 }
 
+#if defined(CONFIG_PHYLIB)
+int mvgbe_phylib_init(struct eth_device *dev, int phyid)
+{
+	struct mii_dev *bus;
+	struct phy_device *phydev;
+	int ret;
+
+	bus = mdio_alloc();
+	if (!bus) {
+		printf("mdio_alloc failed\n");
+		return -ENOMEM;
+	}
+	bus->read = mvgbe_phy_read;
+	bus->write = mvgbe_phy_write;
+	sprintf(bus->name, dev->name);
+
+	ret = mdio_register(bus);
+	if (ret) {
+		printf("mdio_register failed\n");
+		free(bus);
+		return -ENOMEM;
+	}
+
+	/* Set phy address of the port */
+	mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
+
+	phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		printf("phy_connect failed\n");
+		return -ENODEV;
+	}
+
+	phy_config(phydev);
+	phy_startup(phydev);
+
+	return 0;
+}
+#endif
+
 int mvgbe_initialize(bd_t *bis)
 {
 	struct mvgbe_device *dmvgbe;
@@ -729,7 +787,9 @@ error1:
 
 		eth_register(dev);
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_PHYLIB)
+		mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
+#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 		miiphy_register(dev->name, smi_reg_read, smi_reg_write);
 		/* Set phy address of the port */
 		miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
-- 
1.7.10.4

[U-Boot] [PATCH v3 08/10] NET: mvgbe: add support for Dove

[Sebastian Hesselbarth]

Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/net/mvgbe.c |    2 ++
 drivers/net/mvgbe.h |    7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 192c989..590ea0b 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -43,6 +43,8 @@
 #include <asm/arch/kirkwood.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 #include "mvgbe.h"
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index d8a5429..7f5d98f 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -308,10 +308,17 @@
 #define EBAR_TARGET_GUNIT			0x00000007
 
 /* Window attrib */
+#if defined(CONFIG_DOVE)
+#define EBAR_DRAM_CS0				0x00000000
+#define EBAR_DRAM_CS1				0x00000000
+#define EBAR_DRAM_CS2				0x00000000
+#define EBAR_DRAM_CS3				0x00000000
+#else
 #define EBAR_DRAM_CS0				0x00000E00
 #define EBAR_DRAM_CS1				0x00000D00
 #define EBAR_DRAM_CS2				0x00000B00
 #define EBAR_DRAM_CS3				0x00000700
+#endif
 
 /* DRAM Target interface */
 #define EBAR_DRAM_NO_CACHE_COHERENCY		0x00000000
-- 
1.7.10.4

[U-Boot] [PATCH v3 09/10] Boards: Add support for SolidRun CuBox

[Sebastian Hesselbarth]

With latest support for Marvell Dove SoC, add the SolidRun CuBox as
the very first board with that SoC.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 MAINTAINERS                       |    4 +
 board/solidrun/cubox/Makefile     |   45 ++++++++++
 board/solidrun/cubox/cubox.c      |  141 ++++++++++++++++++++++++++++++
 board/solidrun/cubox/kwbimage.cfg |   76 ++++++++++++++++
 boards.cfg                        |    1 +
 include/configs/cubox.h           |  175 +++++++++++++++++++++++++++++++++++++
 6 files changed, 442 insertions(+)
 create mode 100644 board/solidrun/cubox/Makefile
 create mode 100644 board/solidrun/cubox/cubox.c
 create mode 100644 board/solidrun/cubox/kwbimage.cfg
 create mode 100644 include/configs/cubox.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 28c052d..6fc8618 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -684,6 +684,10 @@ Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
 
 	dns325		ARM926EJS (Kirkwood SoC)
 
+Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+
+	cubox		ARM ARMV7 (Dove SoC)
+
 Vaibhav Hiremath <hvaibhav@ti.com>
 
 	am3517_evm	ARM ARMV7 (AM35x SoC)
diff --git a/board/solidrun/cubox/Makefile b/board/solidrun/cubox/Makefile
new file mode 100644
index 0000000..c771d72
--- /dev/null
+++ b/board/solidrun/cubox/Makefile
@@ -0,0 +1,45 @@
+#
+# SolidRun CuBox Makefile
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cubox.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/solidrun/cubox/cubox.c b/board/solidrun/cubox/cubox.c
new file mode 100644
index 0000000..70c016f
--- /dev/null
+++ b/board/solidrun/cubox/cubox.c
@@ -0,0 +1,141 @@
+/*
+ * SolidRun CuBox board support
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/mpp.h>
+#include <orion_gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u16 mpp_config[] = {
+	MPP0_GPIO,
+	MPP1_GPIO, /* USB power enable */
+	MPP2_GPIO, /* USB over-current indication */
+	MPP3_GPIO, /* micro button beneath eSATA port */
+	MPP4_GPIO,
+	MPP5_GPIO,
+	MPP6_GPIO,
+	MPP7_GPIO,
+
+	MPP8_GPIO,
+	MPP9_GPIO,
+	MPP10_GPIO,
+	MPP11_GPIO,
+	MPP12_GPIO, /* SDIO0 card detect */
+	MPP13_AUDIO1_EXTCLK, /* Si5351a audio clock output */
+	MPP14_GPIO,
+	MPP15_GPIO,
+
+	MPP16_GPIO,
+	MPP17_GPIO,
+	MPP18_GPIO, /* Red front LED */
+	MPP19_UART3_RXD, /* IR sensor */
+	MPP20_GPIO,
+	MPP21_GPIO,
+	MPP22_GPIO,
+	MPP23_GPIO,
+
+	MPP_CAMERA_GPIO,
+	MPP_SDIO0_SDIO, /* SDIO0 */
+	MPP_SDIO1_GPIO,
+	MPP_AUDIO1_I2S_SPDIFO, /* SPDIF and HDMI audio */
+	MPP_SPI_SPI, /* SPI */
+	MPP_UART1_GPIO,
+	MPP_NAND_GPO,
+
+	MPP_AUDIO0_I2S,
+	MPP_TWSI_OPTION1, /* TWSI on dedicated pins */
+	0 };
+
+int board_early_init_f(void)
+{
+	struct dove_gpio_init gpp = {
+		.val0  = 0x00010186,
+		.oe0_n = 0xffffffff,
+		.val1  = 0x018000c0,
+		.oe1_n = 0xffffffff,
+		.val2  = 0x00000000,
+		.oe2_n = 0xffffffff,
+	};
+
+	dove_init_gpio(&gpp);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = dove_dram_start(0) + 0x100;
+
+	/* configure mpp */
+	dove_mpp_conf(mpp_config);
+
+	/* usb power enable */
+	orion_gpio_direction_output(MPP1, GPIO_HIGH);
+
+	/* blink led */
+	orion_gpio_direction_output(MPP18, GPIO_HIGH);
+	orion_gpio_set_blink(MPP18, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_MMC
+int board_mmc_init(bd_t *bis)
+{
+	dove_sdhci_init(0);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_RESET_PHY_R
+void dove_eth_phy_init(char *name)
+{
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__func__);
+		return;
+	}
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("%s PHY initialized\n", name);
+}
+
+void reset_phy(void)
+{
+	dove_eth_phy_init("egiga0");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/solidrun/cubox/kwbimage.cfg b/board/solidrun/cubox/kwbimage.cfg
new file mode 100644
index 0000000..c3f1ad9
--- /dev/null
+++ b/board/solidrun/cubox/kwbimage.cfg
@@ -0,0 +1,76 @@
+#
+# Marvell BootROM config for SolidRun CuBox
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# SDRAM initalization
+DATA 0xd0800020 0x00022430	# SDRAM Configuration register 0
+DATA 0xd0800030 0x00022430	# SDRAM Configuration register 1
+DATA 0xd0800050 0x911500c3	# SDRAM Timing register 1
+DATA 0xd0800060 0x646602c4	# SDRAM Timing register 2
+DATA 0xd0800190 0xc2003053	# SDRAM Timing register 3
+DATA 0xd08001c0 0x34f4a187	# SDRAM Timing register 4
+DATA 0xd0800650 0x000f0121	# SDRAM Timing register 5
+DATA 0xd0800660 0x04040200	# SDRAM Timing register 6
+DATA 0xd0800080 0x00000000	# SDRAM Control register 1
+DATA 0xd0800090 0x00080000	# SDRAM Control register 2
+DATA 0xd08000f0 0xc0000000	# SDRAM Control register 3
+DATA 0xd08001a0 0x20c0c009	# SDRAM Control register 4
+DATA 0xd0800280 0x010e0202	# SDRAM Control register 5
+DATA 0xd0800760 0x00000000	# SDRAM Control register 6
+DATA 0xd0800770 0x0000000a	# SDRAM Control register 7
+DATA 0xd0800140 0x20004044	# SDRAM PHY control register 3
+DATA 0xd08001d0 0x133c2339	# SDRAM PHY control register 7
+DATA 0xd08001e0 0x07700330	# SDRAM PHY control register 8
+DATA 0xd08001f0 0x00000033	# SDRAM PHY control register 9
+DATA 0xd0800200 0x0011311c	# SDRAM PHY control register 10
+DATA 0xd0800210 0x00300000	# SDRAM PHY control register 11
+DATA 0xd0800240 0x80000000	# SDRAM PHY control register 14
+DATA 0xd0800510 0x010e0101	# SDRAM MCB control register 1
+DATA 0xd0800230 0x2028006a	# SDRAM PHY control register 13
+DATA 0xd0800e10 0x00280062	# SDRAM PHY DLL control registers 2
+DATA 0xd0800e20 0x00280062	# SDRAM PHY DLL control registers 3
+DATA 0xd0800e30 0x00280062	# SDRAM PHY DLL control registers 4
+
+# SDRAM memory map (2x512MB)
+DATA 0xd0800100 0x000d0001	# SDRAM Memory Address Map register 1
+DATA 0xd0800110 0x200d0001	# SDRAM Memory Address Map register 1
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/boards.cfg b/boards.cfg
index e4b0d44..b13407e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -293,6 +293,7 @@ whistler                     arm         armv7:arm720t whistler          nvidia
 colibri_t20_iris             arm         armv7:arm720t colibri_t20_iris  toradex        tegra20
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
 snowball                     arm         armv7       snowball               st-ericsson    u8500
+cubox                        arm         armv7       cubox               solidrun       dove
 kzm9g                        arm         armv7       kzm9g               kmc            rmobile
 armadillo-800eva             arm         armv7       armadillo-800eva    atmark-techno  rmobile
 zynq                         arm         armv7       zynq                xilinx         zynq
diff --git a/include/configs/cubox.h b/include/configs/cubox.h
new file mode 100644
index 0000000..88a2fda
--- /dev/null
+++ b/include/configs/cubox.h
@@ -0,0 +1,175 @@
+/*
+ * SolidRun CuBox config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_CUBOX_H
+#define _CONFIG_CUBOX_H
+#include <asm/sizes.h>
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\SolidRun CuBox"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MACH_SOLIDRUN_CUBOX	/* Machine type */
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_ORION_GPIO               /* Orion GPIO driver */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable u-boot API for standalone programs.
+ */
+#define CONFIG_API
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Commands configuration
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFT_PARTITION
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * redefine mv-common.h macros for armv7/cubox
+ */
+#undef CONFIG_SYS_PROMPT	/* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT	"CuBox> "	/* Command Prompt */
+
+/* There is no arch_misc_init on armv7 */
+#undef CONFIG_ARCH_MISC_INIT
+
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN	(4 * 1024 * 1024) /* 4MiB for malloc() */
+
+/*
+ *  Environment variables configurations
+ */
+#if defined(CONFIG_CMD_SF)
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SECT_SIZE		0x1000	/* 4k */
+#define CONFIG_ENV_SIZE			0x20000 /* 128k */
+#define CONFIG_ENV_OFFSET		0xc0000 /* env starts here */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+
+/*
+ * Default CuBox bootscript environment
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootscript=boot.scr\0"						\
+	"loadaddr=0x02000000\0"						\
+	"mmc_started=0\0"						\
+	"ide_started=0\0"						\
+	"usb_started=0\0"						\
+	"mtdparts=mtdparts=spi0.0:768k(u-boot)ro,128k(uboot_env),128k(fdt),-(empty)\0"	\
+	"ethaddr=00:50:43:15:17:17\0"
+
+#define CONFIG_BOOTCOMMAND						\
+	"for devn in usb mmc ide ; do "					\
+	"  for part in 0 1; do "					\
+	"    for dir  in / /boot/;do "					\
+	"      for fs in ext2 fat; do "					\
+	"        echo ===> Executing ${fs}load ${devn} 0:${part} ${loadaddr} ${dir}${bootscript};" \
+	"        if itest.s $devn -eq mmc; then"			\
+	"          if itest.s $mmc_started -ne 1; then"			\
+	"            mmcinfo; setenv mmc_started '1';fi;fi;"		\
+	"        if itest.s $devn -eq usb; then"			\
+	"          if itest.s $usb_started -ne 1; then"			\
+	"            usb start; setenv usb_started '1';fi;fi;"		\
+	"        if itest.s $devn -eq ide; then"			\
+	"          if itest.s $ide_started -ne 1; then"			\
+	"            ide reset; setenv ide_started '1';fi;fi;"		\
+	"        if ${fs}load ${devn} 0:${part} ${loadaddr} ${dir}${bootscript}; then" \
+	"          source ${loadaddr}; fi;"				\
+	"        if itest.s $devn -eq usb; then"			\
+	"          echo ===> Executing ${fs}load ${devn} 1:${part} ${loadaddr} ${dir}${bootscript};" \
+	"          if ${fs}load ${devn} 1:${part} ${loadaddr} ${dir}${bootscript}; then" \
+	"            source ${loadaddr}; fi;"				\
+	"        fi;"							\
+	"      done;"							\
+	"    done;"							\
+	"  done;"							\
+	"done;"								\
+	"tftp ${loadaddr} ${bootscript};"				\
+	"source ${loadaddr};"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1}	/* enable port 0 */
+#define CONFIG_PHY_BASE_ADR	1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
+#endif /* CONFIG_CMD_NET */
+
+#ifdef CONFIG_CMD_IDE
+#undef CONFIG_IDE_LED
+#undef CONFIG_SYS_IDE_MAXBUS
+#define CONFIG_SYS_IDE_MAXBUS		1
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_CUBOX_H */
-- 
1.7.10.4

[U-Boot] [PATCH v3 10/10] tools: Add support for Dove to kwboot

[Sebastian Hesselbarth]

On Dove kwboot can also be used to boot an u-boot image into RAM.
In contrast to Kirkwood, Dove does not support the UART boot mode
sequence but requires the UART boot mode to be selected through
strap pins. The SolidRun CuBox has a push button to allow uart
boot mode but fails on the boot sequence sent by kwboot.

This patch adds another cmdline option to allow to send a boot
image without the boot sequence and adds support for Dove.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Daniel Stodden <daniel.stodden@gmail.com>
---
Cc: u-boot at lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 doc/kwboot.1   |   13 ++++++++++---
 tools/Makefile |    2 ++
 tools/kwboot.c |   25 +++++++++++++++++++------
 3 files changed, 31 insertions(+), 9 deletions(-)

diff --git a/doc/kwboot.1 b/doc/kwboot.1
index 25fe69a..ab4551b 100644
--- a/doc/kwboot.1
+++ b/doc/kwboot.1
@@ -1,17 +1,18 @@
-.TH KWBOOT 1 "2012-05-19"
+.TH KWBOOT 1 "2013-01-16"
 
 .SH NAME
-kwboot \- Boot Marvell Kirkwood SoCs over a serial link.
+kwboot \- Boot Marvell Kirkwood/Dove SoCs over a serial link.
 .SH SYNOPSIS
 .B kwboot
 .RB [ "-b \fIimage\fP" ]
+.RB [ "-n" ]
 .RB [ "-p" ]
 .RB [ "-t" ]
 .RB [ "-B \fIbaudrate\fP" ]
 .RB \fITTY\fP
 .SH "DESCRIPTION"
 
-The \fBmkimage\fP program boots boards based on Marvell's Kirkwood
+The \fBmkimage\fP program boots boards based on Marvell's Kirkwood/Dove
 platform over their integrated UART. Boot image files will typically
 contain a second stage boot loader, such as U-Boot. The image file
 must conform to Marvell's BootROM firmware image format
@@ -68,6 +69,12 @@ If standard I/O streams connect to a console, this mode will terminate
 after receiving 'ctrl-\\' followed by 'c' from console input.
 
 .TP
+.BI "\-u"
+Disables the UART boot mode sequence for platforms that do not support
+it (e.g. Dove). Usually, the UART boot mode must be selected by pressing
+a push button on power-up.
+
+.TP
 .BI "\-B \fIbaudrate\fP"
 Adjust the baud rate on \fITTY\fP. Default rate is 115200.
 
diff --git a/tools/Makefile b/tools/Makefile
index 686840a..4816812 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -72,6 +72,7 @@ BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
 BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
 BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
 BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
+BIN_FILES-$(CONFIG_DOVE) += kwboot$(SFX)
 BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
 
 # Source files which exist outside the tools directory
@@ -103,6 +104,7 @@ OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
 NOPED_OBJ_FILES-y += os_support.o
 OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
 NOPED_OBJ_FILES-y += ublimage.o
+OBJ_FILES-$(CONFIG_DOVE) += kwboot.o
 OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
 
 # Don't build by default
diff --git a/tools/kwboot.c b/tools/kwboot.c
index e773f01..1e4edb6 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -37,6 +37,10 @@ static unsigned char kwboot_msg_boot[] = {
 	0xBB, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
 };
 
+static unsigned char kwboot_msg_none[] = {
+	0x00
+};
+
 #define KWBOOT_MSG_REQ_DELAY	10 /* ms */
 #define KWBOOT_MSG_RSP_TIMEO	50 /* ms */
 
@@ -268,17 +272,21 @@ kwboot_bootmsg(int tty, void *msg)
 	int rc;
 	char c;
 
-	kwboot_printv("Sending boot message. Please reboot the target...");
+	kwboot_printv(msg != kwboot_msg_none
+	      ? "Sending boot message. Please reboot the target..."
+	      : "Sensing target. Please reboot target into UART mode...");
 
 	do {
 		rc = tcflush(tty, TCIOFLUSH);
 		if (rc)
 			break;
 
-		rc = kwboot_tty_send(tty, msg, 8);
-		if (rc) {
-			usleep(KWBOOT_MSG_REQ_DELAY * 1000);
-			continue;
+		if (msg != kwboot_msg_none) {
+			rc = kwboot_tty_send(tty, msg, 8);
+			if (rc) {
+				usleep(KWBOOT_MSG_REQ_DELAY * 1000);
+				continue;
+			}
 		}
 
 		rc = kwboot_tty_recv(tty, &c, 1, KWBOOT_MSG_RSP_TIMEO);
@@ -607,6 +615,7 @@ kwboot_usage(FILE *stream, char *progname)
 	fprintf(stream, "  -b <image>: boot <image>\n");
 	fprintf(stream, "  -p: patch <image> to type 0x69 (uart boot)\n");
 	fprintf(stream, "\n");
+	fprintf(stream, "  -n: don't send boot message\n");
 	fprintf(stream, "  -t: mini terminal\n");
 	fprintf(stream, "\n");
 	fprintf(stream, "  -B <baud>: set baud rate\n");
@@ -636,7 +645,7 @@ main(int argc, char **argv)
 	kwboot_verbose = isatty(STDOUT_FILENO);
 
 	do {
-		int c = getopt(argc, argv, "hb:ptB:");
+		int c = getopt(argc, argv, "hb:nptB:");
 		if (c < 0)
 			break;
 
@@ -646,6 +655,10 @@ main(int argc, char **argv)
 			imgpath = optarg;
 			break;
 
+		case 'n':
+			bootmsg = kwboot_msg_none;
+			break;
+
 		case 'p':
 			patch = 1;
 			break;
-- 
1.7.10.4

[U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 17 January 2013 00:55
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox
> 
> This patch set add support for the Marvell Dove 88AP510 SoC and
> the SolidRun CuBox board based on that SoC. The patch set is divided
> into the four following sections:

Dear Sabastian
First of all I express my thanks for initiating this Soc Support in the u-boot.
Secondly I express my apology since I could not review then immediately.
Please find my comments for entire patch series

> 
> (1) Patches 1-5:

I have suggestions to break down your patches as mentioned below

> Add support for the Dove SoC and related drivers. Where possible
> drivers from Marvell Kirkwood are reused (mvsata, mvgbe), or
> forked to allow more generic usage (SPI, GPIO). The SDHCI driver
> is different and a new driver is added for it. The forked drivers
> can also be reused on Kirkwood but that would have required patching
> existing boards.
> 
> (2) Patches 6-8:
> Allow mvgbe to use the phylib API, add support for 88E1310 PHY and
> allow Dove to use the driver.
> 
> (3) Patch 9
> Add the SolidRun CuBox as the first board based on Marvell Dove SoC.
> 
> (4) Patch 10
> Add support for different UART boot mode found on Dove.
> 
> Changelog:
> v1->v2:
> - respect review comments by Luka Perkov
> - fix commenting styles and typos
> - add MAINTAINERS entry
> - also update kwboot.1 manpage
> 
> v2->v3:
> - integrate kwboot patch from Daniel Stodden
> - rebase on release v2013.01
> 
> Sebastian Hesselbarth (10):
>   ARM: dove: add support for Marvell Dove SoC
>   GPIO: add gpio driver for Orion SoCs
>   MMC: sdhci: Add support for dove sdhci
>   SPI: Add Orion SPI driver
>   block: mvsata: add dove include
>   NET: phy: add 88E1310 PHY initialization
>   NET: mvgbe: add phylib support
>   NET: mvgbe: add support for Dove
>   Boards: Add support for SolidRun CuBox
>   tools: Add support for Dove to kwboot
> 
>  MAINTAINERS                             |    4 +
>  arch/arm/cpu/armv7/dove/Makefile        |   49 +++++
>  arch/arm/cpu/armv7/dove/cpu.c           |  266
> ++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/dove/dram.c          |  118 ++++++++++++
>  arch/arm/cpu/armv7/dove/lowlevel_init.S |   83 ++++++++
>  arch/arm/cpu/armv7/dove/mpp.c           |  318
> +++++++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/dove/timer.c         |  176 +++++++++++++++++
>  arch/arm/cpu/armv7/dove/usb.c           |  101 ++++++++++
>  arch/arm/include/asm/arch-dove/config.h |  153 +++++++++++++++
>  arch/arm/include/asm/arch-dove/cpu.h    |  204 ++++++++++++++++++++
>  arch/arm/include/asm/arch-dove/dove.h   |   93 +++++++++
>  arch/arm/include/asm/arch-dove/gpio.h   |   35 ++++
>  arch/arm/include/asm/arch-dove/mpp.h    |  283

Basic Dove support (one patch series)

>  drivers/gpio/Makefile                   |    1 +
>  include/dove or mv_gpio.h                    |   64 +++++++
>  drivers/gpio/dove or mv_gpio.c               |  167 ++++++++++++++++

GPIO driver support for Dove

>  drivers/spi/Makefile                    |    1 +
>  drivers/spi/dove_spi.c                 |  217

Spi driver support for dove

>  drivers/block/mvsata_ide.c              |    2 +
>  drivers/mmc/Makefile                    |    1 +
>  drivers/mmc/dove_sdhci.c                |  101 ++++++++++
>  drivers/net/mvgbe.c                     |   70 ++++++-
>  drivers/net/mvgbe.h                     |    7 +
>  drivers/net/phy/marvell.c               |   48 +++++

Other driver supports for dove (explain supported drivers)

> +++++++++++++++++++++++++++
>  board/solidrun/cubox/Makefile           |   45 +++++
>  board/solidrun/cubox/cubox.c            |  141 ++++++++++++++
>  board/solidrun/cubox/kwbimage.cfg       |   76 ++++++++
>  boards.cfg                              |    1 +
>  include/configs/cubox.h                 |  175 +++++++++++++++++

Board support patches

>  doc/kwboot.1                            |   13 +-
+++++++++++++++++++++
>  tools/Makefile                          |    2 +
>  tools/kwboot.c                          |   25 ++-

Add dove support for boot tool.

FYI: I have gone through all patches in this series

Regards...
Prafulla . . .

[U-Boot] [PATCH v2 01/10] ARM: dove: add support for Marvell Dove SoC

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 04 December 2012 14:02
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v2 01/10] ARM: dove: add support for Marvell Dove SoC
>
> This patch adds initial support for the armv7-based Marvell Dove SoC
> (88AP510).
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---

I could not locate V3 of this patch in my inbox, so please consider these comments applicable for V3 if not changed between v2-to-v3.

> Changelog:
> v1->v2:
> - fix some commenting styles
>
> Cc: u-boot at lists.denx.de
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> Cc: Andy Fleming <afleming@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Daniel Stodden <daniel.stodden@gmail.com>
> Cc: Luka Perkov <luka@openwrt.org>
> ---
>  arch/arm/cpu/armv7/dove/Makefile        |   49 +++++
>  arch/arm/cpu/armv7/dove/cpu.c           |  266
> ++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/dove/dram.c          |  118 ++++++++++++
>  arch/arm/cpu/armv7/dove/lowlevel_init.S |   83 ++++++++
>  arch/arm/cpu/armv7/dove/mpp.c           |  318
> +++++++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/dove/timer.c         |  176 +++++++++++++++++
>  arch/arm/cpu/armv7/dove/usb.c           |  101 ++++++++++
>  arch/arm/include/asm/arch-dove/config.h |  153 +++++++++++++++
>  arch/arm/include/asm/arch-dove/cpu.h    |  204 ++++++++++++++++++++
>  arch/arm/include/asm/arch-dove/dove.h   |   93 +++++++++
>  arch/arm/include/asm/arch-dove/gpio.h   |   35 ++++
>  arch/arm/include/asm/arch-dove/mpp.h    |  283
> +++++++++++++++++++++++++++
>  12 files changed, 1879 insertions(+)
>  create mode 100644 arch/arm/cpu/armv7/dove/Makefile
>  create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
>  create mode 100644 arch/arm/cpu/armv7/dove/dram.c
>  create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
>  create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
>  create mode 100644 arch/arm/cpu/armv7/dove/timer.c
>  create mode 100644 arch/arm/cpu/armv7/dove/usb.c
>  create mode 100644 arch/arm/include/asm/arch-dove/config.h
>  create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
>  create mode 100644 arch/arm/include/asm/arch-dove/dove.h
>  create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
>  create mode 100644 arch/arm/include/asm/arch-dove/mpp.h
>
> diff --git a/arch/arm/cpu/armv7/dove/Makefile
> b/arch/arm/cpu/armv7/dove/Makefile
> new file mode 100644
> index 0000000..127d67e
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/Makefile
> @@ -0,0 +1,49 @@
> +#
> +# Marvell Dove SoC Makefile
> +#
> +# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.

I don't find a file CREDITs, either add it or remove above line :-)

> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#

Recommended: remove the above lines above and you may add the people to whom you wish to give credits here itself.

> +
> +include $(TOPDIR)/config.mk
> +
> +LIB  =  $(obj)lib$(SOC).o
> +
> +SOBJS        += lowlevel_init.o
> +COBJS-y := cpu.o dram.o timer.o mpp.o
> +COBJS-$(CONFIG_USB_EHCI_MARVELL) += usb.o
> +
> +COBJS        := $(COBJS-y)
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
> +
> +all:  $(obj).depend $(LIB)
> +
> +$(LIB):      $(OBJS)
> +     $(call cmd_link_o_target, $(OBJS))
> +
> +#####################################################################
> ####
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#####################################################################
> ####
> diff --git a/arch/arm/cpu/armv7/dove/cpu.c
> b/arch/arm/cpu/armv7/dove/cpu.c
> new file mode 100644
> index 0000000..b9e708c
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/cpu.c
> @@ -0,0 +1,266 @@
> +/*
> + * Marvell Dove SoC cpu related functions
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.

Ditto

> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +#include <asm/cache.h>
> +#include <u-boot/md5.h>
> +#include <asm/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/dove.h>
> +#include <hush.h>
> +
> +void reset_cpu(unsigned long ignored)
> +{
> +     struct dovecpu_registers *cpureg =
> +         (struct dovecpu_registers *)DOVE_CPU_REG_BASE;
> +
> +     /* Enable soft reset to assert RSTOUTn */
> +     writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
> +            &cpureg->rstoutn_mask);
> +     /* Assert soft reset */
> +     writel(readl(&cpureg->sys_soft_rst) | 1,

May you please replace magic numbers with macros?

> +            &cpureg->sys_soft_rst);
> +     do {} while (1);
> +}
> +
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int dove_print_cpu(void)
> +{
> +     char *cpu;
> +     u32 idreg;
> +     u16 part, rev;
> +
> +     __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(idreg));
> +
> +     part = (idreg >> ARM_ID_PARTNUM_OFFSET) & ARM_ID_PARTNUM_MASK;
> +     rev = (idreg >> ARM_ID_REVISION_OFFSET) & ARM_ID_REVISION_MASK;
> +
> +     switch (part) {
> +     case DOVECPU_PART_SHEEVA:
> +             cpu = "Marvell Sheeva";
> +             break;
> +     default:
> +             cpu = "Unknown CPU";
> +     }
> +
> +     printf("CPU:   %s (rev %d)\n", cpu, rev);

There are more than one spaces in the display string, do you really need them? Please remove them.

> +     return 0;
> +}
> +
> +int dove_print_soc(void)
> +{
> +     char *soc, *rev;
> +     u16 devid = (readl(DOVE_REG_PCIE_DEVID) >> 16) & 0xffff;
> +     u8 revid = readl(DOVE_REG_PCIE_REVID) & 0xff;
> +
> +     switch (devid) {
> +     case DOVESOC_DEVID_AP510:
> +             soc = "AP510";
> +             break;
> +     case DOVESOC_DEVID_F6781:
> +             soc = "F6781";
> +             break;
> +     default:
> +             printf("ERROR.. %s: Unsupported SoC %04x\n", __func__, devid);
> +             return -1;
> +     }
> +
> +     switch (revid) {
> +     case DOVESOC_REVID_Z0:
> +             rev = "Z0";
> +             break;
> +     case DOVESOC_REVID_Z1:
> +             rev = "Z1";
> +             break;
> +     case DOVESOC_REVID_Y0:
> +             rev = "Y0";
> +             break;
> +     case DOVESOC_REVID_Y1:
> +             rev = "Y1";
> +             break;
> +     case DOVESOC_REVID_X0:
> +             rev = "X0";
> +             break;
> +     case DOVESOC_REVID_A0:
> +             rev = "A0";
> +             break;
> +     case DOVESOC_REVID_A1:
> +             rev = "A1";
> +             break;
> +     default:
> +             rev = "Unknown revision";
> +     };
> +
> +     printf("SoC:   Dove 88%s (%s)\n", soc, rev);

Same here...

> +     return 0;
> +}
> +
> +int print_cpuinfo(void)
> +{
> +     if (dove_print_soc())
> +             return -1;
> +     if (dove_print_cpu())
> +             return -1;
> +     return 0;
> +}
> +#endif /* CONFIG_DISPLAY_CPUINFO */
> +
> +/*
> + * dove_init_gpio - initial GPIO configuration
> + */
> +void dove_init_gpio(struct dove_gpio_init *gpp)
> +{
> +     struct dovegpio_registers *gpio0reg =
> +             (struct dovegpio_registers *)DOVE_GPIO0_BASE;
> +     struct dovegpio_registers *gpio1reg =
> +             (struct dovegpio_registers *)DOVE_GPIO1_BASE;
> +     struct dovegpio_registers *gpio2reg =
> +             (struct dovegpio_registers *)DOVE_GPIO2_BASE;
> +
> +     /* Init GPIOS to default values as per board requirement */
> +     writel(gpp->val0, &gpio0reg->dout);
> +     writel(gpp->val1, &gpio1reg->dout);
> +     writel(gpp->val2, &gpio2reg->dout);
> +     writel(gpp->oe0_n, &gpio0reg->oe);
> +     writel(gpp->oe1_n, &gpio1reg->oe);
> +     writel(gpp->oe2_n, &gpio2reg->oe);
> +}
> +
> +/*
> + * Window Size
> + * Used with the Base register to set the address window size and
> location.
> + * Must be programmed from LSB to MSB as sequence of ones followed by
> + * sequence of zeros. The number of ones specifies the size of the
> window in
> + * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16
> MByte).
> + * NOTE: A value of 0x0 specifies 64-KByte size.
> + */
> +unsigned int dove_winctrl_calcsize(unsigned int sizeval)
> +{
> +     int i;
> +     unsigned int j = 0;
> +     u32 val = sizeval >> 1;
> +
> +     for (i = 0; val >= 0x10000; i++) {

Please replace magic no by SZ_64K or something similar

> +             j |= (1 << i);
> +             val = val >> 1;
> +     }
> +     return 0x0000ffff & j;

Please replace with macro

> +}
> +
> +/*
> + * dove_config_adr_windows - Configure address Windows
> + *
> + * There are 8 address windows supported by Dove Soc to addess
> different
> + * devices. Windows 0-3 can be configured for size, BAR and remap
> addr.
> + * Windows 4-7 can be configured for size and BAR.
> + * Below configuration is standard for most of the cases
> + *
> + * If remap function not used, remap_lo must be set as base
> + */
> +int dove_config_adr_windows(void)
> +{
> +     struct dovewin_registers *winregs =
> +             (struct dovewin_registers *)DOVE_CPU_WIN_BASE;
> +
> +     /* Window 0: 1M PCIE0 IO address space */
> +     writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE0,
> +          DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE), &winregs[0].ctrl);
> +
> +     writel(DOVE_DEFADR_PCIE0_IO, &winregs[0].base);
> +     writel(DOVE_DEFADR_PCIE0_IO_REMAP, &winregs[0].remap_lo);
> +     writel(0x0, &winregs[0].remap_hi);
> +
> +     /* Window 1: 1M PCIE1 IO address space */
> +     writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE1,
> +          DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE), &winregs[1].ctrl);
> +
> +     writel(DOVE_DEFADR_PCIE1_IO, &winregs[1].base);
> +     writel(DOVE_DEFADR_PCIE1_IO_REMAP, &winregs[1].remap_lo);
> +     writel(0x0, &winregs[1].remap_hi);
> +
> +     /* Window 2: 128M PCIE0 MEM address space */
> +     writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE0,
> +          DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE),
> &winregs[2].ctrl);
> +
> +     writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].base);
> +     writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].remap_lo);
> +     writel(0x0, &winregs[2].remap_hi);
> +
> +     /* Window 3: 128M PCIE1 MEM address space */
> +     writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE1,
> +          DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE),
> &winregs[3].ctrl);
> +
> +     writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].base);
> +     writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].remap_lo);
> +     writel(0x0, &winregs[3].remap_hi);
> +
> +     /* Window 4: 1M Cryptographic SRAM address space */
> +     writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_SASRAM,
> +          DOVECPU_ATTR_SASRAM, DOVECPU_WIN_ENABLE), &winregs[4].ctrl);
> +     writel(DOVE_DEFADR_SASRAM, &winregs[4].base);
> +
> +     /* Window 5: 128M Bootrom address space */
> +     writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_BOOTROM,
> +          DOVECPU_ATTR_BOOTROM, DOVECPU_WIN_ENABLE), &winregs[5].ctrl);
> +     writel(DOVE_DEFADR_BOOTROM, &winregs[5].base);
> +
> +     /* Window 6: 1M PMU Scratchpad address space */
> +     writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PMURAM,
> +          DOVECPU_ATTR_PMURAM, DOVECPU_WIN_ENABLE), &winregs[6].ctrl);
> +     writel(DOVE_DEFADR_PMURAM, &winregs[6].base);
> +
> +     /* Window 7: Disabled */
> +     writel(DOVECPU_WIN_DISABLE, &winregs[7].ctrl);
> +
> +     return 0;
> +}
> +
> +#ifdef CONFIG_ARCH_CPU_INIT
> +int arch_cpu_init(void)
> +{
> +     dove_config_adr_windows();
> +#ifdef CONFIG_USB_EHCI_MARVELL
> +     dove_ehci_phy_init(0);
> +     dove_ehci_phy_init(1);
> +#endif /* CONFIG_USB_EHCI_MARVELL */
> +     return 0;
> +}
> +#endif /* CONFIG_ARCH_CPU_INIT */
> +
> +void enable_caches(void)
> +{
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +     /* Enable D-cache. I-cache is already enabled in lowlevel_init.S
> */
> +     dcache_enable();
> +#endif /* CONFIG_SYS_DCACHE_OFF */
> +}
> +
> +#ifdef CONFIG_MVGBE
> +int cpu_eth_init(bd_t *bis)
> +{
> +     mvgbe_initialize(bis);
> +     return 0;
> +}
> +#endif /* CONFIG_MVGBE */
> diff --git a/arch/arm/cpu/armv7/dove/dram.c
> b/arch/arm/cpu/armv7/dove/dram.c
> new file mode 100644
> index 0000000..437263c
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/dram.c
> @@ -0,0 +1,118 @@
> +/*
> + * Marvell Dove SoC DRAM initialization
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.

Ditto

> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/dove.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define DOVE_REG_DRAM_MAP(x) (DOVE_REGISTER(0x800100) + (x * 0x10))
> +#define DRAM_START_MASK              0xff800000
> +#define DRAM_SIZE_MASK               0xf
> +#define DRAM_SIZE_SHIFT              16
> +
> +/*
> + * dove_sdram_start - reads start from Memory Address Map Register n
> + */
> +u32 dove_dram_start(enum memory_bank bank)
> +{
> +     u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
> +     u32 enable = 0x01 & reg;
> +
> +     if ((!enable) || (bank > BANK1))
> +             return 0;
> +
> +     return reg & DRAM_START_MASK;
> +}
> +
> +/*
> + * dove_sdram_size - reads size from Memory Address Map Register n
> + */
> +u32 dove_dram_size(enum memory_bank bank)
> +{
> +     u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
> +     u32 enable = 0x01 & reg;
> +     u32 size;
> +
> +     if ((!enable) || (bank > BANK1))
> +             return 0;
> +
> +     /*
> +      * area_length: 7 = 8M, 8 = 16M, ..., 15 = 2048M
> +      * size = 1 << (area_length + 16)
> +      */
> +     size = (reg >> DRAM_SIZE_SHIFT) & DRAM_SIZE_MASK;
> +     size = 1 << (size + 16);
> +     return size;
> +}
> +
> +#ifndef CONFIG_SYS_BOARD_DRAM_INIT
> +int dram_init(void)
> +{
> +     int i;
> +
> +     gd->ram_size = 0;
> +     for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> +             gd->bd->bi_dram[i].start = dove_dram_start(i);
> +             gd->bd->bi_dram[i].size = dove_dram_size(i);
> +
> +             /*
> +              * It is assumed that all memory banks are consecutive
> +              * and without gaps.
> +              * If the gap is found, ram_size will be reported for
> +              * consecutive memory only
> +              */
> +             if (gd->bd->bi_dram[i].start != gd->ram_size)
> +                     break;
> +
> +             gd->ram_size += gd->bd->bi_dram[i].size;
> +
> +     }
> +
> +     for (; i < CONFIG_NR_DRAM_BANKS; i++) {
> +             /*
> +              * If above loop terminated prematurely, we need to set
> +              * remaining banks' start address & size as 0. Otherwise other
> +              * u-boot functions and Linux kernel gets wrong values which
> +              * could result in crash
> +              */
> +             gd->bd->bi_dram[i].start = 0;
> +             gd->bd->bi_dram[i].size = 0;
> +     }
> +
> +     return 0;
> +}
> +
> +/*
> + * If this function is not defined here,
> + * board.c alters dram bank zero configuration defined above.
> + */
> +void dram_init_banksize(void)
> +{
> +     dram_init();


Please correct indentation here, use tab

> +}
> +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
> diff --git a/arch/arm/cpu/armv7/dove/lowlevel_init.S
> b/arch/arm/cpu/armv7/dove/lowlevel_init.S
> new file mode 100644
> index 0000000..105d12d
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/lowlevel_init.S
> @@ -0,0 +1,83 @@
> +/*
> + * Marvell Dove SoC icache and reg base low level init
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <asm/arch/dove.h>
> +#include <generated/asm-offsets.h>
> +#include <linux/linkage.h>
> +
> +/*
> + * Enable Tauros2 L2 ICache
> + */
> +.macro init_l2cc
> +     mrc     15, 0, r0, c1, c0, 1
> +     orr     r0, r0, #0x2
> +     mcr     15, 0, r0, c1, c0, 1
> +.endm /* init_l2cc */
> +
> +/*
> + * Init internal register base addresses
> + */
> +.macro init_reg_base
> +     /* set SB reg base to 0xf1000000 */
> +     ldr     r1, =(DOVE_PREMAP_INT_REGS_BASE_ADDR)
> +     ldr     r6, =DOVE_SB_REGS_PHYS_BASE
> +     str     r6, [r1]
> +
> +     /* set NB reg base to 0xf1800000 */
> +     ldr     r1, =(DOVE_CPU_CTRL_REG)
> +     ldr     r4, =0xffff0000
> +     ldr     r6, [r1]
> +     and     r6, r6, r4
> +     ldr     r4, =DOVE_NB_REGS_PHYS_BASE
> +     lsr     r4, r6, #16
> +     orr     r6, r6, r4
> +     str     r6, [r1]
> +
> +     /* Set AXI bridge address mapping to 0xf1800000 */
> +     ldr     r1, =(DOVE_AXI_CTRL_REG)
> +     ldr     r4, =0x007fffff
> +     ldr     r6, [r1]
> +     and     r6, r6, r4
> +     ldr     r4, =DOVE_NB_REGS_PHYS_BASE
> +     orr     r6, r6, r4
> +     str     r6, [r1]
> +
> +     /* set MC configuration register decode address to 0xf1800000 */
> +     ldr     r1, =(DOVE_PREMAP_MC_DECODE_REG)
> +     ldr     r4, =0x0000ffff
> +     ldr     r6, [r1]
> +     and     r6, r6, r4
> +     ldr     r4, =DOVE_NB_REGS_PHYS_BASE
> +     orr     r6, r6, r4
> +     str     r6, [r1]
> +
> +.endm /* init_reg_base */
> +
> +.section ".text.init", "x"
> +
> +ENTRY(lowlevel_init)
> +     init_l2cc
> +     init_reg_base
> +
> +     /* r12 saved upper lr*/
> +     mov pc,lr
> +ENDPROC(lowlevel_init)
> diff --git a/arch/arm/cpu/armv7/dove/mpp.c
> b/arch/arm/cpu/armv7/dove/mpp.c
> new file mode 100644
> index 0000000..ed24b38
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/mpp.c
> @@ -0,0 +1,318 @@
> +/*
> + * Marvell Dove SoC MPP pinmux
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/dove.h>
> +#include <asm/arch/mpp.h>
> +#include <asm/arch/gpio.h>
> +
> +#define MPP_BITS     4
> +#define MPP_MASK     0xf
> +#define MPPS_PER_REG 8
> +
> +#define MPP_NUM(_x)  ((_x) & 0xff)
> +#define MPP_SEL(_x)  (((_x) >> 8) & 0x1f)
> +#define MPP_GPIO(_x) ((_x) & (1 << 15))
> +
> +#define MPP_CTRL(i)                  (DOVE_MPP_BASE + (i * MPP_BITS))
> +#define MPP_PMU_GENERAL_CTRL         (DOVE_MPP_BASE + 0x010)
> +#define  PMUG_AUDIO0_AC97_SEL                (1 << 16)
> +#define MPP4_CTRL                    (DOVE_MPP_BASE + 0x240)
> +#define  MPP4_SDIO0_GPIO_SEL         (1 << 0)
> +#define  MPP4_SDIO1_GPIO_SEL         (1 << 1)
> +#define  MPP4_CAMERA_GPIO_SEL                (1 << 2)
> +#define  MPP4_AUDIO1_GPIO_SEL                (1 << 3)
> +#define  MPP4_UART1_GPIO_SEL         (1 << 4)
> +#define  MPP4_SPI_GPIO_SEL           (1 << 5)
> +#define MPP_GENERAL_CTRL             (DOVE_PDMA_BASE + 0x403c)
> +#define  MPPG_NAND_GPIO_SEL          (1 << 0)
> +#define  MPPG_AUDIO1_SPDIFO_GPIO_SEL (1 << 1)
> +#define GENERAL_CONFIG_1             (DOVE_PDMA_BASE + 0x002c)
> +#define  GENERAL_TWSI_MUXEN_OPTION1  (1 << 7)
> +#define GENERAL_CONFIG_2             (DOVE_PDMA_BASE + 0x0030)
> +#define  GENERAL_TWSI_OPTION3_SEL    (1 << 22)
> +#define  GENERAL_TWSI_MUXEN_OPTION3  (1 << 21)
> +#define  GENERAL_TWSI_MUXEN_OPTION2  (1 << 20)
> +#define SSP_CONFIG_STATUS_1          (DOVE_PDMA_BASE + 0x0034)
> +#define  SSP_SSP_ON_AUDIO1           (1 << 0)
> +
> +/*
> + * MPP0-23 have standard MPP register layout
> + */
> +static void dove_mpp_std_set(u16 config)
> +{
> +     u8 num = MPP_NUM(config);
> +     u32 off = (num / MPPS_PER_REG) * MPP_BITS;
> +     u32 shift = (num % MPPS_PER_REG) * MPP_BITS;
> +     u32 reg;
> +
> +     /* configure standard MPP pin */
> +     reg  = readl(MPP_CTRL(off));
> +     reg &= ~(MPP_MASK << shift);
> +     reg |= MPP_SEL(config) << shift;
> +     writel(reg, MPP_CTRL(off));
> +
> +     /* configure gpio capabilities */
> +     if (MPP_GPIO(config))
> +             orion_gpio_set_valid(num, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> +     else
> +             orion_gpio_set_valid(num, 0);

Why it is orion_gpio*? it should be generic API call or SoC specific.

> +}
> +
> +/*
> + * MPP0-15 also allow to mux PMU functions
> + */
> +static void dove_mpp_pmu_set(u16 config)
> +{
> +     u8 num = MPP_NUM(config);
> +
> +     if (MPP_SEL(config) == PMU) {
> +             /* enable PMU on MPP */
> +             writel(readl(MPP_PMU_GENERAL_CTRL) | (1 << num),
> +                    MPP_PMU_GENERAL_CTRL);
> +             /* disable gpio capabilities */
> +             orion_gpio_set_valid(num, 0);

I think you are trying to reuse the framework implemented by orion,
You may move generic part from orion to common area so that you can use it. Using other SoC direct calls doesn't sound good to me.

> +     } else {
> +             /* disable PMU on MPP */
> +             writel(readl(MPP_PMU_GENERAL_CTRL) & ~(1 << num),
> +                    MPP_PMU_GENERAL_CTRL);
> +             /* configure MPP */
> +             dove_mpp_std_set(config);
> +     }
> +}
> +
> +/*
> + * MPP groups on MPP4_CTRL have different register layout
> + * and allow GPIO or special function only
> + */
> +static void dove_mpp4_set(u16 config)
> +{
> +     u32 reg = readl(MPP4_CTRL);
> +     u32 mask;
> +     u8  n, nmin, nmax;
> +     int gpio;
> +
> +     switch (MPP_NUM(config)) {
> +     case MPP_CAMERA:
> +             mask = MPP4_CAMERA_GPIO_SEL;
> +             nmin = MPP_CAMERA;
> +             nmax = MPP_CAMERA_MAX;
> +             break;
> +     case MPP_SDIO0:
> +             mask = MPP4_SDIO0_GPIO_SEL;
> +             nmin = MPP_SDIO0;
> +             nmax = MPP_SDIO0_MAX;
> +             break;
> +     case MPP_SDIO1:
> +             mask = MPP4_SDIO1_GPIO_SEL;
> +             nmin = MPP_SDIO1;
> +             nmax = MPP_SDIO1_MAX;
> +             break;
> +     case MPP_SPI:
> +             mask = MPP4_SPI_GPIO_SEL;
> +             nmin = MPP_SPI;
> +             nmax = MPP_SPI_MAX;
> +             break;
> +     case MPP_UART1:
> +             mask = MPP4_UART1_GPIO_SEL;
> +             nmin = MPP_UART1;
> +             nmax = MPP_UART1_MAX;
> +             break;
> +     default:
> +             return;
> +     }
> +
> +     reg &= ~mask;
> +     if (MPP_SEL(config))
> +             reg |= mask;
> +     writel(reg, MPP4_CTRL);
> +
> +     /* configure gpio capabilities */
> +     gpio = 0;
> +     if (MPP_GPIO(config))
> +             gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
> +     for (n = nmin; n <= nmax; n++)
> +             orion_gpio_set_valid(n, gpio);
> +}
> +
> +/*
> + * MPP_GENERAL_CTRL allows GPIO on NAND pins
> + */
> +static void dove_mpp_nand_set(u16 config)
> +{
> +     u32 reg = readl(MPP_GENERAL_CTRL);
> +     u8 n;
> +     int gpio;
> +
> +     reg &= ~MPPG_NAND_GPIO_SEL;
> +     if (config == MPP_NAND_GPO)
> +             reg |= MPPG_NAND_GPIO_SEL;
> +     writel(reg, MPP_GENERAL_CTRL);
> +
> +     /* configure gpio capabilities */
> +     gpio = (config == MPP_NAND_GPO) ? GPIO_OUTPUT_OK : 0;
> +     for (n = MPP_NAND; n <= MPP_NAND_MAX; n++)
> +             orion_gpio_set_valid(n, gpio);
> +}
> +
> +/*
> + * Dedicated audio1 pins can carry i2s, spdif, ssp or twsi
> + * and gpio in various combinations
> + */
> +#define AUDIO1_TWSI  (1 << 0)
> +#define AUDIO1_SPDIFO        (1 << 1)
> +#define AUDIO1_SSP   (1 << 2)
> +#define AUDIO1_GPIO  (1 << 3)

Move these defined on the top of in header file; preferred in header.

> +
> +static void dove_mpp_audio1_set(u16 config)
> +{
> +     u32 mpp4  = readl(MPP4_CTRL);
> +     u32 sspc1 = readl(SSP_CONFIG_STATUS_1);
> +     u32 gmpp  = readl(MPP_GENERAL_CTRL);
> +     u32 gcfg2 = readl(GENERAL_CONFIG_2);
> +     u8 n, sel = MPP_SEL(config);
> +     int gpio;
> +
> +     gcfg2 &= ~GENERAL_TWSI_OPTION3_SEL;
> +     gmpp &= ~MPPG_AUDIO1_SPDIFO_GPIO_SEL;
> +     sspc1 &= ~SSP_SSP_ON_AUDIO1;
> +     mpp4 &= ~MPP4_AUDIO1_GPIO_SEL;
> +     if (sel & AUDIO1_TWSI)
> +             gcfg2 |= GENERAL_TWSI_OPTION3_SEL;
> +     if (sel & AUDIO1_SPDIFO)
> +             gmpp |= MPPG_AUDIO1_SPDIFO_GPIO_SEL;
> +     if (sel & AUDIO1_SSP)
> +             sspc1 |= SSP_SSP_ON_AUDIO1;
> +     if (sel & AUDIO1_GPIO)
> +             mpp4 |= MPP4_AUDIO1_GPIO_SEL;
> +
> +     writel(mpp4, MPP4_CTRL);
> +     writel(sspc1, SSP_CONFIG_STATUS_1);
> +     writel(gmpp, MPP_GENERAL_CTRL);
> +     writel(gcfg2, GENERAL_CONFIG_2);
> +
> +     /* gpio allows gpio on all audio1 mpp pins */
> +     gpio = 0;
> +     if (config == MPP_AUDIO1_GPIO)
> +             gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
> +
> +     for (n = MPP_AUDIO1; n <= MPP_AUDIO1_MAX; n++)
> +             orion_gpio_set_valid(n, gpio);
> +
> +     switch (config) {
> +     /* spdifo and twsi allow gpio on mpp[52:55] */
> +     case MPP_AUDIO1_SPDIFO:
> +     case MPP_AUDIO1_TWSI:
> +             orion_gpio_set_valid(52, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> +             orion_gpio_set_valid(53, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> +             orion_gpio_set_valid(54, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> +             orion_gpio_set_valid(55, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> +             break;
> +     /* i2s and ssp allow gpio on mpp[56:57] */
> +     case MPP_AUDIO1_I2S:
> +     case MPP_AUDIO1_SSP:
> +             orion_gpio_set_valid(56, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> +             orion_gpio_set_valid(57, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> +             break;
> +     }
> +}
> +
> +/*
> + * MPP PMU switches audio0 pins to ac97 or i2s0
> + */
> +static void dove_mpp_audio0_set(u16 config)
> +{
> +     /* switch i2s or ac97 to audio0 */
> +     u32 reg = readl(MPP_PMU_GENERAL_CTRL);
> +
> +     reg &= ~PMUG_AUDIO0_AC97_SEL;
> +     if (config == MPP_AUDIO0_AC97)
> +             reg |= PMUG_AUDIO0_AC97_SEL;
> +     writel(reg, MPP_PMU_GENERAL_CTRL);
> +}
> +
> +/*
> + * TWSI has 3 optional pin sets that can be switched during runtime
> + */
> +static void dove_mpp_twsi_set(u16 config)
> +{
> +     u32 gcfg1 = readl(GENERAL_CONFIG_1);
> +     u32 gcfg2 = readl(GENERAL_CONFIG_2);
> +
> +     gcfg1 &= ~GENERAL_TWSI_MUXEN_OPTION1;
> +     gcfg2 &= ~(GENERAL_TWSI_MUXEN_OPTION2 |
> GENERAL_TWSI_MUXEN_OPTION3);
> +
> +     switch (config) {
> +     case MPP_TWSI_OPTION1:
> +             gcfg1 |= GENERAL_TWSI_MUXEN_OPTION1;
> +             break;
> +     case MPP_TWSI_OPTION2:
> +             gcfg2 |= GENERAL_TWSI_MUXEN_OPTION2;
> +             break;
> +     case MPP_TWSI_OPTION3:
> +             gcfg2 |= GENERAL_TWSI_MUXEN_OPTION3;
> +             break;
> +     }
> +
> +     writel(gcfg1, GENERAL_CONFIG_1);
> +     writel(gcfg2, GENERAL_CONFIG_2);
> +}
> +
> +void dove_mpp_conf(u16 *mpp_list)
> +{
> +     while (*mpp_list) {
> +             u8 num = MPP_NUM(*mpp_list);
> +
> +             if (num <= MPP_PMU_MAX)
> +                     dove_mpp_pmu_set(*mpp_list);
> +             else if (num <= MPP_STD_MAX)
> +                     dove_mpp_std_set(*mpp_list);
> +             else {
> +                     switch (num) {
> +                     case MPP_CAMERA:
> +                     case MPP_SDIO0:
> +                     case MPP_SDIO1:
> +                     case MPP_SPI:
> +                     case MPP_UART1:
> +                             dove_mpp4_set(*mpp_list);
> +                             break;
> +                     case MPP_NAND:
> +                             dove_mpp_nand_set(*mpp_list);
> +                             break;
> +                     case MPP_AUDIO0:
> +                             dove_mpp_audio0_set(*mpp_list);
> +                             break;
> +                     case MPP_AUDIO1:
> +                             dove_mpp_audio1_set(*mpp_list);
> +                             break;
> +                     case MPP_TWSI:
> +                             dove_mpp_twsi_set(*mpp_list);
> +                             break;
> +                     }
> +             }
> +             mpp_list++;
> +     }
> +}
> diff --git a/arch/arm/cpu/armv7/dove/timer.c
> b/arch/arm/cpu/armv7/dove/timer.c
> new file mode 100644
> index 0000000..3be9b78
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/timer.c
> @@ -0,0 +1,176 @@
> +/*
> + * Marvell Dove SoC timer
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +

There are two blank lines here,
Pls remove one.

> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/dove.h>
> +
> +#define UBOOT_CNTR   0       /* counter to use for uboot timer */
> +
> +/* Timer reload and current value registers */
> +struct dovetmr_val {
> +     u32 reload;     /* Timer reload reg */
> +     u32 val;        /* Timer value reg */
> +};
> +
> +/* Timer registers */
> +struct dovetmr_registers {
> +     u32 ctrl;       /* Timer control reg */
> +     u32 pad[3];
> +     struct dovetmr_val tmr[2];
> +     u32 wdt_reload;
> +     u32 wdt_val;
> +};
> +
> +struct dovetmr_registers *dovetmr_regs =
> +     (struct dovetmr_registers *)DOVE_TIMER_BASE;
> +
> +/*
> + * ARM Timers Registers Map
> + */
> +#define CNTMR_CTRL_REG                       &dovetmr_regs->ctrl
> +#define CNTMR_RELOAD_REG(tmrnum)     &dovetmr_regs->tmr[tmrnum].reload
> +#define CNTMR_VAL_REG(tmrnum)                &dovetmr_regs->tmr[tmrnum].val
> +
> +/*
> + * ARM Timers Control Register
> + * CPU_TIMERS_CTRL_REG (CTCR)
> + */
> +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
> +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
> +#define CTCR_ARM_TIMER_EN(cntr)              (1 <<
> CTCR_ARM_TIMER_EN_OFFS(cntr))
> +#define CTCR_ARM_TIMER_DIS(cntr)     (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
> +
> +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)       ((cntr * 2) + 1)
> +#define CTCR_ARM_TIMER_AUTO_MASK(cntr)       (1 << 1)
> +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 <<
> CTCR_ARM_TIMER_AUTO_OFFS(cntr))
> +#define CTCR_ARM_TIMER_AUTO_DIS(cntr)        (0 <<
> CTCR_ARM_TIMER_AUTO_OFFS(cntr))
> +
> +/*
> + * ARM Timer\Watchdog Reload Register
> + * CNTMR_RELOAD_REG (TRR)
> + */
> +#define TRG_ARM_TIMER_REL_OFFS               0
> +#define TRG_ARM_TIMER_REL_MASK               0xffffffff
> +
> +/*
> + * ARM Timer\Watchdog Register
> + * CNTMR_VAL_REG (TVRG)
> + */
> +#define TVR_ARM_TIMER_OFFS           0
> +#define TVR_ARM_TIMER_MASK           0xffffffff
> +#define TVR_ARM_TIMER_MAX            0xffffffff
> +#define TIMER_LOAD_VAL                       0xffffffff
> +
> +#define READ_TIMER                   (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
> +                                      (CONFIG_SYS_TCLK / 1000))
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define timestamp gd->tbl
> +#define lastdec gd->lastinc
> +
> +ulong get_timer_masked(void)
> +{
> +     ulong now = READ_TIMER;
> +
> +     if (lastdec >= now) {
> +             /* normal mode */
> +             timestamp += lastdec - now;
> +     } else {
> +             /* we have an overflow ... */
> +             timestamp += lastdec +
> +                     (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
> +     }
> +     lastdec = now;
> +
> +     return timestamp;
> +}
> +
> +ulong get_timer(ulong base)
> +{
> +     return get_timer_masked() - base;
> +}
> +
> +void __udelay(unsigned long usec)
> +{
> +     uint current;
> +     ulong delayticks;
> +
> +     current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
> +     delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
> +
> +     if (current < delayticks) {
> +             delayticks -= current;
> +             do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current);
> +             do {} while ((TIMER_LOAD_VAL - delayticks) <
> +                          readl(CNTMR_VAL_REG(UBOOT_CNTR)));
> +     } else {
> +             do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
> +                          (current - delayticks));
> +     }
> +}
> +
> +/*
> + * init the counter
> + */
> +int timer_init(void)
> +{
> +     unsigned int cntmrctrl;
> +
> +     /* load value into timer */
> +     writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
> +     writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
> +
> +     /* enable timer in auto reload mode */
> +     cntmrctrl = readl(CNTMR_CTRL_REG);
> +     cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
> +     cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
> +     writel(cntmrctrl, CNTMR_CTRL_REG);
> +
> +     /* init the timestamp and lastdec value */
> +     lastdec = READ_TIMER;
> +     timestamp = 0;
> +
> +     return 0;
> +}
> +
> +/*
> + * This function is derived from PowerPC code (read timebase as long

Does these comments stands valid, I think you reference is Kirkwood.

> long).
> + * On ARM it just returns the timer value.
> + */
> +unsigned long long get_ticks(void)
> +{
> +     return get_timer(0);
> +}
> +
> +/*
> + * This function is derived from PowerPC code (timebase clock
> frequency).
> + * On ARM it returns the number of timer ticks per second.
> + */
> +ulong get_tbclk(void)
> +{
> +     return (ulong)CONFIG_SYS_HZ;
> +}
> diff --git a/arch/arm/cpu/armv7/dove/usb.c
> b/arch/arm/cpu/armv7/dove/usb.c
> new file mode 100644
> index 0000000..1b932db
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/usb.c
> @@ -0,0 +1,101 @@
> +/*
> + * Marvell Dove SoC USB PHY init
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/dove.h>
> +
> +/* Dove USB2.0 PHY registers */
> +#define USB20_POWER_CTRL             ((base) + 0x400)
> +#define USB20_PHY_PLL_CTRL           ((base) + 0x410)
> +#define  PHY_PLL_VCO_RECALIBRATE     (1 << 21)
> +#define USB20_PHY_TX_CTRL            ((base) + 0x420)
> +#define  PHY_TX_HS_STRESS_CTRL               (1 << 31)
> +#define  PHY_TX_BLOCK_EN             (1 << 21)
> +#define  PHY_TX_IMP_CAL_VTH(x)               (x << 14)
> +#define  PHY_TX_IMP_CAL_VTH_MASK     PHY_TX_IMP_CAL_VTH(0x7)
> +#define  PHY_TX_RCAL_START           (1 << 12)
> +#define  PHY_TX_LOWVDD_EN            (1 << 11)
> +#define USB20_PHY_RX_CTRL            ((base) + 0x430)
> +#define  PHY_RX_EDGE_DET(x)          (x << 26)
> +#define  PHY_RX_EDGE_DET_MASK                PHY_RX_EDGE_DET(0x3)
> +#define  PHY_RX_CDR_FASTLOCK_EN              (1 << 21)
> +#define  PHY_RX_SQ_LENGTH(x)         (x << 15)
> +#define  PHY_RX_SQ_LENGTH_MASK               PHY_RX_SQ_LENGTH(0x3)
> +#define  PHY_RX_SQ_THRESH(x)         (x << 4)
> +#define  PHY_RX_SQ_THRESH_MASK               PHY_RX_SQ_THRESH(0xf)
> +#define  PHY_RX_LPF_COEFF(x)         (x << 2)
> +#define  PHY_RX_LPF_COEFF_MASK               PHY_RX_LPF_COEFF(0x3)
> +#define USB20_PHY_IVREF_CTRL         ((base) + 0x440)
> +#define  PHY_IVREF_TXVDD12(x)                (x << 8)
> +#define  PHY_IVREF_TXVDD12_MASK              PHY_IVREF_TXVDD12(0x3)
> +#define USB20_PHY_TESTGRP_CTRL               ((base) + 0x450)
> +#define  PHY_TESTGRP_SQ_RST          (1 << 15)
> +
> +void dove_ehci_phy_init(int port)
> +{
> +     u32 base = (port == 0) ? DOVE_USB20_0_BASE : DOVE_USB20_1_BASE;
> +     u32 reg;
> +
> +     /* USB PHY PLL control */
> +     reg = readl(USB20_PHY_PLL_CTRL);
> +     writel(reg | PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
> +     udelay(100);
> +     writel(reg & ~PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
> +
> +     /* USB PHY Tx control */
> +     reg = readl(USB20_PHY_TX_CTRL);
> +     reg &= ~PHY_TX_IMP_CAL_VTH_MASK;
> +     reg |= PHY_TX_IMP_CAL_VTH(0x5);
> +     reg |= PHY_TX_LOWVDD_EN;
> +     reg |= PHY_TX_RCAL_START;
> +     reg |= PHY_TX_BLOCK_EN;
> +     reg |= PHY_TX_HS_STRESS_CTRL;
> +     writel(reg, USB20_PHY_TX_CTRL);
> +     udelay(100);
> +     writel(reg & ~PHY_TX_RCAL_START, USB20_PHY_TX_CTRL);
> +
> +     /* USB PHY RX control */
> +     reg = readl(USB20_PHY_RX_CTRL);
> +     reg &= ~(PHY_RX_LPF_COEFF_MASK | PHY_RX_SQ_THRESH_MASK |
> +              PHY_RX_SQ_LENGTH_MASK | PHY_RX_EDGE_DET_MASK);
> +     reg |= PHY_RX_LPF_COEFF(0x1);
> +     reg |= PHY_RX_SQ_THRESH(0xc);
> +     reg |= PHY_RX_SQ_LENGTH(0x1);
> +     reg |= PHY_RX_EDGE_DET(0x0);
> +     reg &= ~PHY_RX_CDR_FASTLOCK_EN;
> +     writel(reg, USB20_PHY_RX_CTRL);
> +
> +     /* USB PHY IVREF control */
> +     reg = readl(USB20_PHY_IVREF_CTRL);
> +     reg &= ~PHY_IVREF_TXVDD12_MASK;
> +     reg |= PHY_IVREF_TXVDD12(0x3);
> +     writel(reg, USB20_PHY_IVREF_CTRL);
> +
> +     /* USB PHY TEST GROUP control */
> +     reg = readl(USB20_PHY_TESTGRP_CTRL);
> +     reg &= ~PHY_TESTGRP_SQ_RST;
> +     writel(reg, USB20_PHY_TESTGRP_CTRL);
> +}
> diff --git a/arch/arm/include/asm/arch-dove/config.h
> b/arch/arm/include/asm/arch-dove/config.h
> new file mode 100644
> index 0000000..2d94a48
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/config.h
> @@ -0,0 +1,153 @@
> +/*
> + * Marvell SoC config
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVE_CONFIG_H
> +#define _DOVE_CONFIG_H
> +
> +#include <asm/arch/dove.h>
> +
> +#define CONFIG_ARMV7                 /* Basic Architecture */
> +#define CONFIG_DOVE                  /* SOC Family Name */
> +#define CONFIG_SHEEVA_88SV581                /* CPU Core subversion */
> +#define CONFIG_SYS_CACHELINE_SIZE    32
> +                             /* default Dcache Line length for Dove */
> +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
> +#define CONFIG_SYS_DCACHE_OFF                /* Disable DCache by default */
> +
> +/*
> + * By default kwbimage.cfg from board specific folder is used

I think you should use dvbimage.cfg naming convention, since kwb stands for Kirkwood boot image, same way it will be dove boot image

> + * If for some board, different configuration file need to be used,
> + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header
> file
> + */
> +#ifndef CONFIG_SYS_KWD_CONFIG
> +#define      CONFIG_SYS_KWD_CONFIG
>       $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
> +#endif /* CONFIG_SYS_KWD_CONFIG */

Same: change all references to DOVE, secondly do you think DV is better than DOVE to shorten then name everywhere like KW for Kirkwood?

> +
> +/* Dove has 2k of Security SRAM, use it for SP */
> +#define CONFIG_SYS_INIT_SP_ADDR              0xC8012000
> +#define CONFIG_NR_DRAM_BANKS_MAX     2
> +
> +#define CONFIG_I2C_MVTWSI_BASE       DOVE_TWSI_BASE
> +#define MV_UART_CONSOLE_BASE DOVE_UART0_BASE
> +#define MV_SATA_BASE         DOVE_SATA_BASE
> +#define MV_SATA_PORT0_OFFSET DOVE_SATA_PORT0_OFFSET
> +
> +/*
> + * NAND configuration
> + */
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_NAND_KIRKWOOD         1
> +#define CONFIG_SYS_NAND_BASE         0xD8000000      /* MV_DEFADR_NANDF */
> +#define NAND_ALLOW_ERASE_ALL         1
> +#endif
> +
> +/*
> + * SPI Flash configuration
> + */
> +#ifdef CONFIG_CMD_SF
> +#define CONFIG_HARD_SPI                      1
> +#define CONFIG_ORION_SPI             1
> +#define ORION_SPI_BASE                       DOVE_SPI_BASE

???

> +#ifndef CONFIG_ENV_SPI_BUS
> +# define CONFIG_ENV_SPI_BUS          0
> +#endif
> +#ifndef CONFIG_ENV_SPI_CS
> +# define CONFIG_ENV_SPI_CS           0
> +#endif
> +#ifndef CONFIG_ENV_SPI_MAX_HZ
> +# define CONFIG_ENV_SPI_MAX_HZ               25000000
> +#endif
> +#endif
> +
> +/*
> + * Ethernet Driver configuration
> + */
> +#ifdef CONFIG_CMD_NET
> +#define CONFIG_CMD_MII
> +#define CONFIG_NETCONSOLE    /* include NetConsole support   */
> +#define CONFIG_PHYLIB
> +#define CONFIG_MVGBE         /* Enable Marvell Gbe Controller Driver */

> +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN      /* detect link using phy */
> +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
> +#endif /* CONFIG_CMD_NET */
> +
> +/*
> + * SDHCI
> + */
> +#ifdef CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_MMC
> +#define CONFIG_MMC_SDMA
> +#define CONFIG_SDHCI
> +#define CONFIG_DOVE_SDHCI    /* Enable Dove SDHCI controller driver
> */
> +#define CONFIG_MMC_SDHCI_IO_ACCESSORS
> +#define CONFIG_SYS_MMC_MAX_DEVICE    2
> +#endif
> +
> +/*
> + * USB/EHCI
> + */
> +#ifdef CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI_MARVELL
> +#define CONFIG_EHCI_IS_TDI
> +#endif /* CONFIG_CMD_USB */
> +
> +/*
> + * IDE Support on SATA ports
> + */
> +#ifdef CONFIG_CMD_IDE
> +#define __io
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_MVSATA_IDE
> +#define CONFIG_IDE_PREINIT
> +#define CONFIG_MVSATA_IDE_USE_PORT1
> +/* Needs byte-swapping for ATA data register */
> +#define CONFIG_IDE_SWAP_IO
> +/* Data, registers and alternate blocks are at the same offset */
> +#define CONFIG_SYS_ATA_DATA_OFFSET   (0x0100)
> +#define CONFIG_SYS_ATA_REG_OFFSET    (0x0100)
> +#define CONFIG_SYS_ATA_ALT_OFFSET    (0x0100)
> +/* Each 8-bit ATA register is aligned to a 4-bytes address */
> +#define CONFIG_SYS_ATA_STRIDE                4
> +/* Controller supports 48-bits LBA addressing */
> +#define CONFIG_LBA48
> +/* CONFIG_CMD_IDE requires some #defines for ATA registers */
> +#define CONFIG_SYS_IDE_MAXBUS                2
> +#define CONFIG_SYS_IDE_MAXDEVICE     2
> +/* ATA registers base is at SATA controller base */
> +#define CONFIG_SYS_ATA_BASE_ADDR     MV_SATA_BASE
> +#endif /* CONFIG_CMD_IDE */
> +
> +/*
> + * I2C related stuff
> + */
> +#ifdef CONFIG_CMD_I2C
> +#ifndef CONFIG_SOFT_I2C
> +#define CONFIG_I2C_MVTWSI
> +#endif
> +#define CONFIG_SYS_I2C_SLAVE         0x0
> +#define CONFIG_SYS_I2C_SPEED         100000
> +#endif
> +
> +#endif /* _DOVE_CONFIG_H */
> diff --git a/arch/arm/include/asm/arch-dove/cpu.h
> b/arch/arm/include/asm/arch-dove/cpu.h
> new file mode 100644
> index 0000000..718dd59
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/cpu.h
> @@ -0,0 +1,204 @@
> +/*
> + * Marvell Dove SoC CPU
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVECPU_H
> +#define _DOVECPU_H
> +
> +#include <asm/system.h>
> +
> +#ifndef __ASSEMBLY__
> +

Please give the reference of the SoC documentation that you are referring here for all enums and macros.

> +#define DOVECPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target
> << 4) \
> +                     | (attr << 8) | (dove_winctrl_calcsize(size) << 16))
> +
> +#define DOVEGBE_PORT_SERIAL_CONTROL1_REG     (DOVE_EGIGA_BASE + 0x44c)
> +#define DOVE_REG_PCIE_DEVID                  (DOVE_REG_PCIE0_BASE + 0x00)
> +#define DOVE_REG_PCIE_REVID                  (DOVE_REG_PCIE0_BASE + 0x08)
> +#define DOVE_REG_SYSRST_CNT                  (DOVE_MPP_BASE + 0x50)
> +#define SYSRST_CNT_1SEC_VAL                  (25*1000000)
> +#define DOVE_REG_MPP_OUT_DRV_REG             (DOVE_MPP_BASE + 0xE0)
> +
> +enum memory_bank {
> +     BANK0,
> +     BANK1,
> +};
> +
> +enum dovecpu_winen {
> +     DOVECPU_WIN_DISABLE,
> +     DOVECPU_WIN_ENABLE
> +};
> +
> +enum dovecpu_target {
> +     DOVECPU_TARGET_DRAM = 0x0,
> +     DOVECPU_TARGET_SASRAM = 0x3,
> +     DOVECPU_TARGET_NAND = 0xc,
> +     DOVECPU_TARGET_PMURAM = 0xd,
> +     DOVECPU_TARGET_PCIE0 = 0x4,
> +     DOVECPU_TARGET_PCIE1 = 0x8,
> +     DOVECPU_TARGET_SPI = 0x1,
> +     DOVECPU_TARGET_BOOTROM = 0x1,
> +};
> +
> +enum dovecpu_attrib {
> +     DOVECPU_ATTR_DRAM = 0x00,
> +     DOVECPU_ATTR_SASRAM = 0x00,
> +     DOVECPU_ATTR_NAND = 0x00,
> +     DOVECPU_ATTR_PMURAM = 0x00,
> +     DOVECPU_ATTR_PCIE_IO = 0xe0,
> +     DOVECPU_ATTR_PCIE_MEM = 0xe8,
> +     DOVECPU_ATTR_SPI0 = 0xfe,
> +     DOVECPU_ATTR_SPI1 = 0xfb,
> +     DOVECPU_ATTR_BOOTROM = 0xfd,
> +};
> +
> +enum dovecpu_part {
> +     DOVECPU_PART_SHEEVA = 0x581,
> +};
> +
> +enum dovesoc_devid {
> +     DOVESOC_DEVID_F6781 = 0x6781,
> +     DOVESOC_DEVID_AP510 = 0x0510,
> +};
> +
> +enum dovesoc_revid {
> +     DOVESOC_REVID_Z0 = 0,
> +     DOVESOC_REVID_Z1 = 1,
> +     DOVESOC_REVID_Y0 = 2,
> +     DOVESOC_REVID_Y1 = 3,
> +     DOVESOC_REVID_X0 = 4,
> +     DOVESOC_REVID_A0 = 6,
> +     DOVESOC_REVID_A1 = 7,
> +};
> +
> +/*
> + * Default Device Address MAP BAR values
> + */
> +#define DOVE_DEFADR_PCIE0_MEM                0xe0000000
> +#define DOVE_DEFADR_PCIE0_IO         0xf2000000
> +#define DOVE_DEFADR_PCIE0_IO_REMAP   0x00000000
> +#define DOVE_DEFADR_PCIE1_MEM                0xe8000000
> +#define DOVE_DEFADR_PCIE1_IO         0xf2100000
> +#define DOVE_DEFADR_PCIE1_IO_REMAP   0x00100000
> +#define DOVE_DEFADR_SASRAM           0xc8000000
> +#define DOVE_DEFADR_BOOTROM          0xf8000000
> +#define DOVE_DEFADR_PMURAM           0xf0000000
> +
> +/*
> + * ARM CPUID register
> + */
> +#define ARM_ID_REVISION_OFFSET       0
> +#define ARM_ID_REVISION_MASK 0xf
> +#define ARM_ID_PARTNUM_OFFSET        4
> +#define ARM_ID_PARTNUM_MASK  0xfff
> +#define ARM_ID_ARCH_OFFSET   16
> +#define ARM_ID_ARCH_MASK     0xf
> +#define ARM_ID_VAR_OFFSET    20
> +#define ARM_ID_VAR_MASK              0xf
> +#define ARM_ID_ASCII_OFFSET  24
> +#define ARM_ID_ASCII_MASK    0xff
> +
> +/*
> + * read feroceon/sheeva core extra feature register
> + * using co-proc instruction
> + */
> +static inline unsigned int readfr_extra_feature_reg(void)
> +{
> +     unsigned int val;
> +     asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
> +                     (val) : : "cc");
> +     return val;
> +}
> +
> +/*
> + * write feroceon/sheeva core extra feature register
> + * using co-proc instruction
> + */
> +static inline void writefr_extra_feature_reg(unsigned int val)
> +{
> +     asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
> +                     (val) : "cc");
> +     isb();
> +}
> +
> +/*
> + * Downstream Bridge Registers
> + */
> +struct dovewin_registers {
> +     u32 ctrl;
> +     u32 base;
> +     u32 remap_lo;
> +     u32 remap_hi;
> +};
> +
> +/*
> + * CPU control and status Registers
> + */
> +struct dovecpu_registers {
> +     u32 config;             /* 0x20100 */
> +     u32 ctrl_stat;          /* 0x20104 */
> +     u32 rstoutn_mask;       /* 0x20108 */
> +     u32 sys_soft_rst;       /* 0x2010C */
> +     u32 bridge_cause_irq;   /* 0x20110 */
> +     u32 bridge_mask_irq;    /* 0x20114 */
> +     u32 pad1;
> +     u32 pmu_ctrl;           /* 0x2011c */
> +};

Same here, documentation reference is needed.

> +
> +/*
> + * GPIO 0/1 Registers
> + * GPIO 2 Registers (no datain/irq)
> + */
> +struct dovegpio_registers {
> +     u32 dout;
> +     u32 oe;
> +     u32 blink_en;
> +     u32 din_pol;
> +     u32 din;
> +     u32 irq_cause;
> +     u32 irq_mask;
> +     u32 irq_level;
> +};
> +
> +struct dove_gpio_init {
> +     u32 val0;
> +     u32 val1;
> +     u32 val2;
> +     u32 oe0_n;
> +     u32 oe1_n;
> +     u32 oe2_n;
> +};

Pls move to gpio.h

> +
> +/*
> + * functions
> + */
> +void reset_cpu(unsigned long ignored);
> +unsigned char get_random_hex(void);
> +u32 dove_dram_start(enum memory_bank bank);
> +u32 dove_dram_size(enum memory_bank bank);
> +int dove_config_adr_windows(void);
> +void dove_init_gpio(struct dove_gpio_init *);
> +unsigned int dove_winctrl_calcsize(unsigned int sizeval);
> +
> +#endif /* __ASSEMBLY__ */
> +#endif /* _DOVECPU_H */
> diff --git a/arch/arm/include/asm/arch-dove/dove.h
> b/arch/arm/include/asm/arch-dove/dove.h
> new file mode 100644
> index 0000000..da5011b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/dove.h
> @@ -0,0 +1,93 @@
> +/*
> + * Marvell Dove SoC register offsets and config
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVE_H
> +#define _DOVE_H
> +
> +/* Dove TCLK is fixed to 166MHz */
> +#define CONFIG_SYS_TCLK                      166666667
> +
> +/* SOC specific definitions */
> +#define DOVE_PREMAP_REGS_PHYS_BASE   0xd0000000
> +#define DOVE_PREMAP_INT_REGS_BASE_ADDR  (DOVE_PREMAP_REGS_PHYS_BASE +
> 0x20080)
> +#define DOVE_PREMAP_MC_DECODE_REG       (DOVE_PREMAP_REGS_PHYS_BASE +
> 0x800010)
> +
> +#define DOVE_SB_REGS_PHYS_BASE               0xf1000000
> +#define DOVE_NB_REGS_PHYS_BASE               0xf1800000
> +#define DOVE_REGISTER(x)             (DOVE_SB_REGS_PHYS_BASE + x)
> +
> +#define DOVE_AXI_CTRL_REG            (DOVE_REGISTER(0xd0224))
> +#define DOVE_CPU_CTRL_REG            (DOVE_REGISTER(0xd025c))
> +#define DOVE_MC_CTRL_REG             (DOVE_REGISTER(0xd0260))
> +#define DOVE_MC_DECODE_REG           (DOVE_REGISTER(0x800010))
> +
> +#define DOVE_SPI_BASE                        (DOVE_REGISTER(0x10600))
> +#define DOVE_TWSI_BASE                       (DOVE_REGISTER(0x11000))
> +#define DOVE_UART0_BASE                      (DOVE_REGISTER(0x12000))
> +#define DOVE_UART1_BASE                      (DOVE_REGISTER(0x12100))
> +#define DOVE_UART2_BASE                      (DOVE_REGISTER(0x12200))
> +#define DOVE_UART3_BASE                      (DOVE_REGISTER(0x12300))
> +#define DOVE_CPU_WIN_BASE            (DOVE_REGISTER(0x20000))
> +#define DOVE_CPU_REG_BASE            (DOVE_REGISTER(0x20100))
> +#define DOVE_TIMER_BASE                      (DOVE_REGISTER(0x20300))
> +#define DOVE_REG_PCIE0_BASE          (DOVE_REGISTER(0x40000))
> +#define DOVE_REG_PCIE1_BASE          (DOVE_REGISTER(0x80000))
> +#define DOVE_USB20_0_BASE            (DOVE_REGISTER(0x50000))
> +#define DOVE_USB20_1_BASE            (DOVE_REGISTER(0x51000))
> +#define DOVE_EGIGA_BASE                      (DOVE_REGISTER(0x72000))
> +#define DOVE_SDIO1_BASE                      (DOVE_REGISTER(0x90000))
> +#define DOVE_SDIO0_BASE                      (DOVE_REGISTER(0x92000))
> +#define DOVE_CAMERA_BASE             (DOVE_REGISTER(0x94000))
> +#define DOVE_SATA_BASE                       (DOVE_REGISTER(0xa0000))
> +#define DOVE_NANDF_BASE                      (DOVE_REGISTER(0xc0000))
> +#define DOVE_PMU_BASE                        (DOVE_REGISTER(0xd0000))
> +#define DOVE_MPP_BASE                        (DOVE_REGISTER(0xd0200))
> +#define DOVE_GPIO0_BASE                      (DOVE_REGISTER(0xd0400))
> +#define DOVE_GPIO1_BASE                      (DOVE_REGISTER(0xd0420))
> +#define DOVE_RTC_BASE                        (DOVE_REGISTER(0xd8500))
> +#define DOVE_AC97_BASE                       (DOVE_REGISTER(0xe0000))
> +#define DOVE_PDMA_BASE                       (DOVE_REGISTER(0xe4000))
> +#define DOVE_GPIO2_BASE                      (DOVE_REGISTER(0xe8400))
> +#define DOVE_SSP_BASE                        (DOVE_REGISTER(0xec000))
> +
> +/* Dove Sata controller has one port */
> +#define DOVE_SATA_PORT0_OFFSET               0x2000
> +
> +/* Dove GbE controller has one port */
> +#define MAX_MVGBE_DEVS                       1
> +#define MVGBE0_BASE                  DOVE_EGIGA_BASE
> +
> +/* Dove USB Host controller */
> +#define MVUSB0_BASE                  DOVE_USB20_0_BASE
> +#define MVUSB0_CPU_ATTR_DRAM_CS0     DOVECPU_ATTR_DRAM
> +#define MVUSB0_CPU_ATTR_DRAM_CS1     DOVECPU_ATTR_DRAM
> +#define MVUSB0_CPU_ATTR_DRAM_CS2     DOVECPU_WIN_DISABLE
> +#define MVUSB0_CPU_ATTR_DRAM_CS3     DOVECPU_WIN_DISABLE
> +
> +/* Dove CPU memory windows */
> +#define MVCPU_WIN_CTRL_DATA          DOVECPU_WIN_CTRL_DATA
> +#define MVCPU_WIN_ENABLE             DOVECPU_WIN_ENABLE
> +#define MVCPU_WIN_DISABLE            DOVECPU_WIN_DISABLE
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-dove/gpio.h
> b/arch/arm/include/asm/arch-dove/gpio.h
> new file mode 100644
> index 0000000..71bef8e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/gpio.h
> @@ -0,0 +1,35 @@
> +/*
> + * Marvell Dove SoC gpio
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef __DOVE_GPIO_H
> +#define __DOVE_GPIO_H
> +
> +#include <orion_gpio.h>
> +
> +#define GPIO_MAX             70
> +#define GPIO_BASE(pin)               (((pin) >= 64) ? DOVE_GPIO2_BASE : \
> +                              ((pin) >= 32) ? DOVE_GPIO1_BASE : \
> +                              DOVE_GPIO0_BASE)
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-dove/mpp.h
> b/arch/arm/include/asm/arch-dove/mpp.h
> new file mode 100644
> index 0000000..1279ac2
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/mpp.h
> @@ -0,0 +1,283 @@
> +/*
> + * Marvell Dove SoC pinmux
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVE_MPP_H
> +#define _DOVE_MPP_H
> +
> +#define DOVE_GPI     (1 << 0)
> +#define DOVE_GPO     (1 << 1)
> +#define DOVE_GPIO    (DOVE_GPO | DOVE_GPI)
> +
> +#define MPP(_num, _sel, _gpio) (                      \
> +     /* MPP number */        ((_num) & 0xff) |        \
> +     /* MPP select value */  (((_sel) & 0x1f) << 8) | \
> +     /* is gpio config */    ((!!(_gpio)) << 15))
> +
> +/* MPP0-15 allow PMU function */
> +#define MPP_PMU_MAX          15
> +#define PMU                  (0x10)
> +/* MPP0-23 have standard mpp register layout */
> +#define MPP_STD_MAX          23
> +
> +#define MPP0                 0
> +#define MPP0_GPIO            MPP(0, 0x0, 1)
> +#define MPP0_UART2_RTS               MPP(0, 0x2, 0)
> +#define MPP0_SDIO0_CD                MPP(0, 0x3, 0)
> +#define MPP0_LCD0_PWM                MPP(0, 0xf, 0)
> +#define MPP0_PMU             MPP(0, PMU, 0)
> +
> +#define MPP1                 1
> +#define MPP1_GPIO            MPP(1, 0x0, 1)
> +#define MPP1_UART2_CTS               MPP(1, 0x2, 0)
> +#define MPP1_SDIO0_WP                MPP(1, 0x3, 0)
> +#define MPP1_LCD1_PWM                MPP(1, 0xf, 0)
> +#define MPP1_PMU             MPP(1, PMU, 0)
> +
> +#define MPP2                 2
> +#define MPP2_GPIO            MPP(2, 0x0, 1)
> +#define MPP2_SATA_PRSNT              MPP(2, 0x1, 0)
> +#define MPP2_UART2_TXD               MPP(2, 0x2, 0)
> +#define MPP2_SDIO0_BUSPWR    MPP(2, 0x3, 0)
> +#define MPP2_UART1_RTS               MPP(2, 0x4, 0)
> +#define MPP2_PMU             MPP(2, PMU, 0)
> +
> +#define MPP3                 3
> +#define MPP3_GPIO            MPP(3, 0x0, 1)
> +#define MPP3_SATA_ACT                MPP(3, 0x1, 0)
> +#define MPP3_UART2_RXD               MPP(3, 0x2, 0)
> +#define MPP3_SDIO0_LEDCTRL   MPP(3, 0x3, 0)
> +#define MPP3_UART1_CTS               MPP(3, 0x4, 0)
> +#define MPP3_LCD_SPI_CS1     MPP(3, 0xf, 0)
> +#define MPP3_PMU             MPP(3, PMU, 0)
> +
> +#define MPP4                 4
> +#define MPP4_GPIO            MPP(4, 0x0, 1)
> +#define MPP4_UART3_RTS               MPP(4, 0x2, 0)
> +#define MPP4_SDIO1_CD                MPP(4, 0x3, 0)
> +#define MPP4_SPI1_MISO               MPP(4, 0x4, 0)
> +#define MPP4_PMU             MPP(4, PMU, 0)
> +
> +#define MPP5                 5
> +#define MPP5_GPIO            MPP(5, 0x0, 1)
> +#define MPP5_UART3_CTS               MPP(5, 0x2, 0)
> +#define MPP5_SDIO1_WP                MPP(5, 0x3, 0)
> +#define MPP5_SPI1_CS         MPP(5, 0x4, 0)
> +#define MPP5_PMU             MPP(5, PMU, 0)
> +
> +#define MPP6                 6
> +#define MPP6_GPIO            MPP(6, 0x0, 1)
> +#define MPP6_UART3_TXD               MPP(6, 0x2, 0)
> +#define MPP6_SDIO1_BUSPWR    MPP(6, 0x3, 0)
> +#define MPP6_SPI1_MOSI               MPP(6, 0x4, 0)
> +#define MPP6_PMU             MPP(6, PMU, 0)
> +
> +#define MPP7                 7
> +#define MPP7_GPIO            MPP(7, 0x0, 1)
> +#define MPP7_UART3_RXD               MPP(7, 0x2, 0)
> +#define MPP7_SDIO1_LEDCTRL   MPP(7, 0x3, 0)
> +#define MPP7_SPI1_SCK                MPP(7, 0x4, 0)
> +#define MPP7_PMU             MPP(7, PMU, 0)
> +
> +#define MPP8                 8
> +#define MPP8_GPIO            MPP(8, 0x0, 1)
> +#define MPP8_WATCHDOG_RSTOUT MPP(8, 0x1, 0)
> +#define MPP8_PMU             MPP(8, PMU, 0)
> +
> +#define MPP9                 9
> +#define MPP9_GPIO            MPP(9, 0x0, 1)
> +#define MPP9_PEX1_CLKREQ     MPP(9, 0x5, 0)
> +#define MPP9_PMU             MPP(9, PMU, 0)
> +
> +#define MPP10                        10
> +#define MPP10_GPIO           MPP(10, 0x0, 1)
> +#define MPP10_SSP_SCLK               MPP(10, 0x5, 0)
> +#define MPP10_PMU            MPP(10, PMU, 0)
> +
> +#define MPP11                        11
> +#define MPP11_GPIO           MPP(11, 0x0, 1)
> +#define MPP11_SATA_PRSNT     MPP(11, 0x1, 0)
> +#define MPP11_SATA_ACT               MPP(11, 0x2, 0)
> +#define MPP11_SDIO0_LEDCTRL  MPP(11, 0x3, 0)
> +#define MPP11_SDIO1_LEDCTRL  MPP(11, 0x4, 0)
> +#define MPP11_PEX0_CLKREQ    MPP(11, 0x5, 0)
> +#define MPP11_PMU            MPP(11, PMU, 0)
> +
> +#define MPP12                        12
> +#define MPP12_GPIO           MPP(12, 0x0, 1)
> +#define MPP12_SATA_ACT               MPP(12, 0x1, 0)
> +#define MPP12_UART2_RTS              MPP(12, 0x2, 0)
> +#define MPP12_AUDIO0_EXTCLK  MPP(12, 0x3, 0)
> +#define MPP12_SDIO1_CD               MPP(12, 0x4, 0)
> +#define MPP12_PMU            MPP(12, PMU, 0)
> +
> +#define MPP13                        13
> +#define MPP13_GPIO           MPP(13, 0x0, 1)
> +#define MPP13_UART2_CTS              MPP(13, 0x2, 0)
> +#define MPP13_AUDIO1_EXTCLK  MPP(13, 0x3, 0)
> +#define MPP13_SDIO1_WP               MPP(13, 0x4, 0)
> +#define MPP13_SSP_EXTCLK     MPP(13, 0x5, 0)
> +#define MPP13_PMU            MPP(13, PMU, 0)
> +
> +#define MPP14                        14
> +#define MPP14_GPIO           MPP(14, 0x0, 1)
> +#define MPP14_UART2_TXD              MPP(14, 0x2, 0)
> +#define MPP14_SDIO1_BUSPWR   MPP(14, 0x4, 0)
> +#define MPP14_SSP_TXD                MPP(14, 0x5, 0)
> +#define MPP14_PMU            MPP(14, PMU, 0)
> +
> +#define MPP15                        15
> +#define MPP15_GPIO           MPP(15, 0x0, 1)
> +#define MPP15_UART2_RXD              MPP(15, 0x2, 0)
> +#define MPP15_SDIO1_LEDCTRL  MPP(15, 0x4, 0)
> +#define MPP15_SSP_SFRM               MPP(15, 0x5, 0)
> +#define MPP15_PMU            MPP(15, PMU, 0)
> +
> +#define MPP16                        16
> +#define MPP16_GPIO           MPP(16, 0x0, 1)
> +#define MPP16_UART3_RTS              MPP(16, 0x2, 0)
> +#define MPP16_SDIO0_CD               MPP(16, 0x3, 0)
> +#define MPP16_LCD_SPI_CS1    MPP(16, 0x4, 0)
> +#define MPP16_AC97_SDI1              MPP(16, 0x5, 0)
> +
> +#define MPP17                        17
> +#define MPP17_GPIO           MPP(17, 0x0, 1)
> +#define MPP17_AC97_SYSCLKO   MPP(17, 0x1, 0)
> +#define MPP17_UART3_CTS              MPP(17, 0x2, 0)
> +#define MPP17_SDIO0_WP               MPP(17, 0x3, 0)
> +#define MPP17_TWSI_SDA               MPP(17, 0x4, 0)
> +#define MPP17_AC97_SDI2              MPP(17, 0x5, 0)
> +
> +#define MPP18                        18
> +#define MPP18_GPIO           MPP(18, 0x0, 1)
> +#define MPP18_UART3_TXD              MPP(18, 0x2, 0)
> +#define MPP18_SDIO0_BUSPWR   MPP(18, 0x3, 0)
> +#define MPP18_LCD0_PWM               MPP(18, 0x4, 0)
> +#define MPP18_AC97_SDI3              MPP(18, 0x5, 0)
> +
> +#define MPP19                        19
> +#define MPP19_GPIO           MPP(19, 0x0, 1)
> +#define MPP19_UART3_RXD              MPP(19, 0x2, 0)
> +#define MPP19_SDIO0_LEDCTRL  MPP(19, 0x3, 0)
> +#define MPP19_TWSI_SCK               MPP(19, 0x4, 0)
> +
> +#define MPP20                        20
> +#define MPP20_GPIO           MPP(20, 0x0, 1)
> +#define MPP20_AC97_SYSCLKO   MPP(20, 0x1, 0)
> +#define MPP20_LCD_SPI_MISO   MPP(20, 0x2, 0)
> +#define MPP20_SDIO1_CD               MPP(20, 0x3, 0)
> +#define MPP20_SDIO0_CD               MPP(20, 0x5, 0)
> +#define MPP20_SPI1_MISO              MPP(20, 0x6, 0)
> +
> +#define MPP21                        21
> +#define MPP21_GPIO           MPP(21, 0x0, 1)
> +#define MPP21_UART1_RTS              MPP(21, 0x1, 0)
> +#define MPP21_LCD_SPI_CS0    MPP(21, 0x2, 0)
> +#define MPP21_SDIO1_WP               MPP(21, 0x3, 0)
> +#define MPP21_SSP_SFRM               MPP(21, 0x4, 0)
> +#define MPP21_SDIO0_WP               MPP(21, 0x5, 0)
> +#define MPP21_SPI1_CS                MPP(21, 0x6, 0)
> +
> +#define MPP22                        22
> +#define MPP22_GPIO           MPP(22, 0x0, 1)
> +#define MPP22_UART1_CTS              MPP(22, 0x1, 0)
> +#define MPP22_LCD_SPI_MOSI   MPP(22, 0x2, 0)
> +#define MPP22_SDIO1_BUSPWR   MPP(22, 0x3, 0)
> +#define MPP22_SSP_TXD                MPP(22, 0x4, 0)
> +#define MPP22_SDIO0_BUSPWR   MPP(22, 0x5, 0)
> +#define MPP22_SPI1_MOSI              MPP(22, 0x6, 0)
> +
> +#define MPP23                        23
> +#define MPP23_GPIO           MPP(23, 0x0, 1)
> +#define MPP23_LCD_SPI_SCK    MPP(23, 0x2, 0)
> +#define MPP23_SDIO1_LEDCTRL  MPP(23, 0x3, 0)
> +#define MPP23_SSP_SCLK               MPP(23, 0x4, 0)
> +#define MPP23_SDIO0_LEDCTRL  MPP(23, 0x5, 0)
> +#define MPP23_SPI1_SCK               MPP(23, 0x6, 0)
> +
> +/* MPP_CAMERA = MPP[24:39] */
> +#define MPP_CAMERA           24
> +#define MPP_CAMERA_CAMERA    MPP(24, 0x0, 0)
> +#define MPP_CAMERA_GPIO              MPP(24, 0x1, 1)
> +#define MPP_CAMERA_MAX               39
> +
> +/* MPP_SDIO0 = MPP[40:45] */
> +#define MPP_SDIO0            40
> +#define MPP_SDIO0_SDIO               MPP(40, 0x0, 0)
> +#define MPP_SDIO0_GPIO               MPP(40, 0x1, 1)
> +#define MPP_SDIO0_MAX                45
> +
> +/* MPP_SDIO1 = MPP[46:51] */
> +#define MPP_SDIO1            46
> +#define MPP_SDIO1_SDIO               MPP(46, 0x0, 0)
> +#define MPP_SDIO1_GPIO               MPP(46, 0x1, 1)
> +#define MPP_SDIO1_MAX                51
> +
> +/* MPP_AUDIO1 = MPP[52:57] */
> +#define MPP_AUDIO1           52
> +#define MPP_AUDIO1_I2S_SPDIFO        MPP(52, 0x0, 0)
> +#define MPP_AUDIO1_I2S               MPP(52, 0x2, 0)
> +#define MPP_AUDIO1_SPDIFO    MPP(52, 0x8, 0)
> +#define MPP_AUDIO1_GPIO              MPP(52, 0xa, 1)
> +#define MPP_AUDIO1_TWSI              MPP(52, 0xb, 0)
> +#define MPP_AUDIO1_SSP_SPDIFO        MPP(52, 0xc, 0)
> +#define MPP_AUDIO1_SSP               MPP(52, 0xe, 0)
> +#define MPP_AUDIO1_SSP_TWSI  MPP(52, 0xf, 0)
> +#define MPP_AUDIO1_MAX               57
> +
> +/* MPP_SPI = MPP[58:61] */
> +#define MPP_SPI                      58
> +#define MPP_SPI_SPI          MPP(58, 0x0, 0)
> +#define MPP_SPI_GPIO         MPP(58, 0x1, 1)
> +#define MPP_SPI_MAX          61
> +
> +/* MPP_UART1 = MPP[62:63] */
> +#define MPP_UART1            62
> +#define MPP_UART1_UART1              MPP(62, 0x0, 0)
> +#define MPP_UART1_GPIO               MPP(62, 0x1, 1)
> +#define MPP_UART1_MAX                63
> +
> +/* MPP_NAND = MPP[64:71] */
> +#define MPP_NAND             64
> +#define MPP_NAND_NAND                MPP(64, 0x0, 0)
> +#define MPP_NAND_GPO         MPP(64, 0x1, 1)
> +#define MPP_NAND_MAX         71
> +
> +/* MPP_AUDIO0 = Internal AC97/I2S mux for audio0 pins */
> +#define MPP_AUDIO0           72
> +#define MPP_AUDIO0_I2S               MPP(72, 0x0, 0)
> +#define MPP_AUDIO0_AC97              MPP(72, 0x1, 0)
> +
> +/* MPP_TWSI = Internal TWSI option mux */
> +#define MPP_TWSI             73
> +#define MPP_TWSI_NONE                MPP(73, 0x0, 0)
> +#define MPP_TWSI_OPTION1     MPP(73, 0x1, 0)
> +#define MPP_TWSI_OPTION2     MPP(73, 0x2, 0)
> +#define MPP_TWSI_OPTION3     MPP(73, 0x3, 0)
> +
> +#define MPP_MAX                      MPP_TWSI
> +
> +u8 dove_mpp_get_gpio_caps(u8 num);
> +void dove_mpp_conf(u16 *mpp_list);
> +
> +#endif
> --
> 1.7.10.4

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 04/10] SPI: Add Orion SPI driver

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 17 January 2013 00:55
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v3 04/10] SPI: Add Orion SPI driver
> 
> This adds an SPI driver found on Marvell Orion SoCs. This driver is
> taken from kirkwood_spi but removes mpp configuration as dove has
> dedicated spi pins. To have a common driver for orion5x, kirkwood,
> and dove, mpp configuration should be handled in some cpu/board-
> specific

the proposal of having common driver will be greatly appreciated.
Pls go ahead and do it if possible for you

I think adding orion_spi.c to enable dove support doesn't sound good.

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 05/10] block: mvsata: add dove include

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 17 January 2013 00:55
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v3 05/10] block: mvsata: add dove include
> 
> Dove SoC also uses mvsata, therefore add a SoC specific include to
> allow to reuse the mvsata ide driver.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: u-boot at lists.denx.de
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> Cc: Andy Fleming <afleming@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Daniel Stodden <daniel.stodden@gmail.com>
> Cc: Luka Perkov <luka@openwrt.org>
> --
>  drivers/block/mvsata_ide.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
> index a88d0f7..9918f80 100644
> --- a/drivers/block/mvsata_ide.c
> +++ b/drivers/block/mvsata_ide.c
> @@ -29,6 +29,8 @@
>  #include <asm/arch/orion5x.h>
>  #elif defined(CONFIG_KIRKWOOD)
>  #include <asm/arch/kirkwood.h>
> +#elif defined(CONFIG_DOVE)
> +#include <asm/arch/dove.h>
>  #endif
> 

Acked-By: Prafulla Wadaskar <prafulla@marvell.com>

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 06/10] NET: phy: add 88E1310 PHY initialization

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 17 January 2013 00:55
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v3 06/10] NET: phy: add 88E1310 PHY initialization
> 
> This adds PHY initialization for Marvell Alaska 88E1310 PHY.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: u-boot at lists.denx.de
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> Cc: Andy Fleming <afleming@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Daniel Stodden <daniel.stodden@gmail.com>
> Cc: Luka Perkov <luka@openwrt.org>
> ---
>  drivers/net/phy/marvell.c |   48
> +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
> index 4b27198..1205166 100644
> --- a/drivers/net/phy/marvell.c
> +++ b/drivers/net/phy/marvell.c
> @@ -89,6 +89,12 @@
> 
>  #define MIIM_88E1149_PHY_PAGE	29
> 
> +/* 88E1310 PHY defines */
> +#define MIIM_88E1310_PHY_LED_CTRL	16
> +#define MIIM_88E1310_PHY_IRQ_EN		18
> +#define MIIM_88E1310_PHY_RGMII_CTRL	21
> +#define MIIM_88E1310_PHY_PAGE		22
> +
>  /* Marvell 88E1011S */
>  static int m88e1011s_config(struct phy_device *phydev)
>  {
> @@ -394,6 +400,37 @@ static int m88e1149_config(struct phy_device
> *phydev)
>  	return 0;
>  }
> 
> +/* Marvell 88E1310 */
> +static int m88e1310_config(struct phy_device *phydev)
> +{
> +	u16 reg;
> +
> +	/* LED link and activity */
> +	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
> +	reg = phy_read(phydev, MDIO_DEVAD_NONE,
> MIIM_88E1310_PHY_LED_CTRL);
> +	reg = (reg & ~0xf) | 0x1;
> +	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL,
> reg);
> +
> +	/* Set LED2/INT to INT mode, low active */
> +	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
> +	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
> +	reg = (reg & 0x77ff) | 0x0880;
> +	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
> +
> +	/* Set RGMII delay */
> +	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
> +	reg = phy_read(phydev, MDIO_DEVAD_NONE,
> MIIM_88E1310_PHY_RGMII_CTRL);
> +	reg |= 0x0030;
> +	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL,
> reg);
> +
> +	/* Ensure to return to page 0 */
> +	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
> +
> +	genphy_config_aneg(phydev);
> +	phy_reset(phydev);
> +
> +	return 0;
> +}
> 
>  static struct phy_driver M88E1011S_driver = {
>  	.name = "Marvell 88E1011S",
> @@ -465,8 +502,19 @@ static struct phy_driver M88E1149S_driver = {
>  	.shutdown = &genphy_shutdown,
>  };
> 
> +static struct phy_driver M88E1310_driver = {
> +	.name = "Marvell 88E1310",
> +	.uid = 0x01410e90,
> +	.mask = 0xffffff0,
> +	.features = PHY_GBIT_FEATURES,
> +	.config = &m88e1310_config,
> +	.startup = &m88e1011s_startup,
> +	.shutdown = &genphy_shutdown,
> +};
> +
>  int phy_marvell_init(void)
>  {
> +	phy_register(&M88E1310_driver);

Please maintain an order here.

>  	phy_register(&M88E1149S_driver);
>  	phy_register(&M88E1145_driver);
>  	phy_register(&M88E1121R_driver);
> --
> 1.7.10.4

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 07/10] NET: mvgbe: add phylib support

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 17 January 2013 00:55
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v3 07/10] NET: mvgbe: add phylib support
> 
> This add phylib support to the Marvell GBE driver.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: u-boot at lists.denx.de
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> Cc: Andy Fleming <afleming@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Daniel Stodden <daniel.stodden@gmail.com>
> Cc: Luka Perkov <luka@openwrt.org>
> ---
>  drivers/net/mvgbe.c |   68
> ++++++++++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 64 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
> index 47bf27c..192c989 100644
> --- a/drivers/net/mvgbe.c
> +++ b/drivers/net/mvgbe.c
> @@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define MV_PHY_ADR_REQUEST 0xee
>  #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
> 
> -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
> +#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) ||
> defined(CONFIG_CMD_MII)
>  /*
>   * smi_reg_read - miiphy_read callback function.
>   *
> @@ -184,6 +184,24 @@ static int smi_reg_write(const char *devname, u8
> phy_adr, u8 reg_ofs, u16 data)
>  }
>  #endif
> 
> +#if defined(CONFIG_PHYLIB)
> +int mvgbe_phy_read(struct mii_dev *bus, int phyAddr, int devAddr, int
> regAddr)
> +{
> +	u16 data;
> +	int ret;
> +	ret = smi_reg_read(bus->name, phyAddr, regAddr, &data);
> +	if (ret)
> +		return ret;
> +	return data;
> +}
> +
> +int mvgbe_phy_write(struct mii_dev *bus, int phyAddr, int devAddr,
> int regAddr,
> +	u16 data)
> +{
> +	return smi_reg_write(bus->name, phyAddr, regAddr, data);
> +}
> +#endif
> +
>  /* Stop and checks all queues */
>  static void stop_queue(u32 * qreg)
>  {
> @@ -467,8 +485,9 @@ static int mvgbe_init(struct eth_device *dev)
>  	/* Enable port Rx. */
>  	MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
> 
> -#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
> -	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
> +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))   \
> +	&& !defined(CONFIG_PHYLIB)		       \
> +	&& defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
>  	/* Wait up to 5s for the link status */
>  	for (i = 0; i < 5; i++) {
>  		u16 phyadr;
> @@ -647,6 +666,45 @@ static int mvgbe_recv(struct eth_device *dev)
>  	return 0;
>  }
> 
> +#if defined(CONFIG_PHYLIB)
> +int mvgbe_phylib_init(struct eth_device *dev, int phyid)
> +{
> +	struct mii_dev *bus;
> +	struct phy_device *phydev;
> +	int ret;
> +
> +	bus = mdio_alloc();
> +	if (!bus) {
> +		printf("mdio_alloc failed\n");
> +		return -ENOMEM;
> +	}
> +	bus->read = mvgbe_phy_read;
> +	bus->write = mvgbe_phy_write;
> +	sprintf(bus->name, dev->name);
> +
> +	ret = mdio_register(bus);
> +	if (ret) {
> +		printf("mdio_register failed\n");
> +		free(bus);
> +		return -ENOMEM;
> +	}
> +
> +	/* Set phy address of the port */
> +	mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST,
> phyid);
> +
> +	phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
> +	if (!phydev) {
> +		printf("phy_connect failed\n");
> +		return -ENODEV;
> +	}
> +
> +	phy_config(phydev);
> +	phy_startup(phydev);
> +
> +	return 0;
> +}
> +#endif
> +
>  int mvgbe_initialize(bd_t *bis)
>  {
>  	struct mvgbe_device *dmvgbe;
> @@ -729,7 +787,9 @@ error1:
> 
>  		eth_register(dev);
> 
> -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
> +#if defined(CONFIG_PHYLIB)
> +		mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
> +#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
>  		miiphy_register(dev->name, smi_reg_read, smi_reg_write);
>  		/* Set phy address of the port */
>  		miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
> --

Acked-By: Prafulla Wadaskar <prafulla@marvell.com>

This patch do not have any dependency.
I suggest to detach this patch and send it as standalone patch so that Joe can pull it earliest.

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 02/10] GPIO: add gpio driver for Orion SoCs

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 17 January 2013 00:55
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v3 02/10] GPIO: add gpio driver for Orion SoCs
> 
> This adds a gpio driver for Marvell Orion SoCs, i.e. orion5x,
> kirkwood,
> dove. This is based on kw_gpio but as gpio capabilities depend heavily
> on the mpp configuration for dove, it allows to set gpi/gpo
> capabilities
> from mpp. This should be compatible with the current kw_gpio and
> porting
> mpp of kirkwood and orion5x is appreciated.

Nack, your patch series is for dove, you shouldn't add for orion, unless you are using it. If you think this is common framework can be used across the other marvell SoCs, we have strategy to name it like mv_***

So you may name this driver as mv_gpio

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 08/10] NET: mvgbe: add support for Dove

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 17 January 2013 00:55
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v3 08/10] NET: mvgbe: add support for Dove
> 
> Marvell Dove also uses mvgbe as ethernet driver, therefore add support
> for Dove to reuse the current driver.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: u-boot at lists.denx.de
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> Cc: Andy Fleming <afleming@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Daniel Stodden <daniel.stodden@gmail.com>
> Cc: Luka Perkov <luka@openwrt.org>
> ---
>  drivers/net/mvgbe.c |    2 ++
>  drivers/net/mvgbe.h |    7 +++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
> index 192c989..590ea0b 100644
> --- a/drivers/net/mvgbe.c
> +++ b/drivers/net/mvgbe.c
> @@ -43,6 +43,8 @@
>  #include <asm/arch/kirkwood.h>
>  #elif defined(CONFIG_ORION5X)
>  #include <asm/arch/orion5x.h>
> +#elif defined(CONFIG_DOVE)
> +#include <asm/arch/dove.h>
>  #endif
> 
>  #include "mvgbe.h"
> diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
> index d8a5429..7f5d98f 100644
> --- a/drivers/net/mvgbe.h
> +++ b/drivers/net/mvgbe.h
> @@ -308,10 +308,17 @@
>  #define EBAR_TARGET_GUNIT			0x00000007
> 
>  /* Window attrib */
> +#if defined(CONFIG_DOVE)
> +#define EBAR_DRAM_CS0				0x00000000
> +#define EBAR_DRAM_CS1				0x00000000
> +#define EBAR_DRAM_CS2				0x00000000
> +#define EBAR_DRAM_CS3				0x00000000

What does this means?
May you please explain?

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 09/10] Boards: Add support for SolidRun CuBox

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 17 January 2013 00:55
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v3 09/10] Boards: Add support for SolidRun CuBox
>
> With latest support for Marvell Dove SoC, add the SolidRun CuBox as
> the very first board with that SoC.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: u-boot at lists.denx.de
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> Cc: Andy Fleming <afleming@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Daniel Stodden <daniel.stodden@gmail.com>
> Cc: Luka Perkov <luka@openwrt.org>
> ---
>  MAINTAINERS                       |    4 +
>  board/solidrun/cubox/Makefile     |   45 ++++++++++
>  board/solidrun/cubox/cubox.c      |  141
> ++++++++++++++++++++++++++++++
>  board/solidrun/cubox/kwbimage.cfg |   76 ++++++++++++++++


Pls rename this as dvbimage.cfg


>  boards.cfg                        |    1 +
>  include/configs/cubox.h           |  175
> +++++++++++++++++++++++++++++++++++++
>  6 files changed, 442 insertions(+)
>  create mode 100644 board/solidrun/cubox/Makefile
>  create mode 100644 board/solidrun/cubox/cubox.c
>  create mode 100644 board/solidrun/cubox/kwbimage.cfg
>  create mode 100644 include/configs/cubox.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 28c052d..6fc8618 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -684,6 +684,10 @@ Stefan Herbrechtsmeier
> <stefan@code.herbrechtsmeier.net>
>
>       dns325          ARM926EJS (Kirkwood SoC)
>
> +Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> +
> +     cubox           ARM ARMV7 (Dove SoC)
> +
>  Vaibhav Hiremath <hvaibhav@ti.com>
>
>       am3517_evm      ARM ARMV7 (AM35x SoC)
> diff --git a/board/solidrun/cubox/Makefile
> b/board/solidrun/cubox/Makefile
> new file mode 100644
> index 0000000..c771d72
> --- /dev/null
> +++ b/board/solidrun/cubox/Makefile
> @@ -0,0 +1,45 @@
> +#
> +# SolidRun CuBox Makefile
> +#
> +# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.        See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> +# MA 02110-1301 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB  = $(obj)lib$(BOARD).o
> +
> +COBJS        := cubox.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS        := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB):      $(obj).depend $(OBJS) $(SOBJS)
> +     $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +#####################################################################
> ####
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#####################################################################
> ####
> diff --git a/board/solidrun/cubox/cubox.c
> b/board/solidrun/cubox/cubox.c
> new file mode 100644
> index 0000000..70c016f
> --- /dev/null
> +++ b/board/solidrun/cubox/cubox.c
> @@ -0,0 +1,141 @@
> +/*
> + * SolidRun CuBox board support
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <miiphy.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/dove.h>
> +#include <asm/arch/mpp.h>
> +#include <orion_gpio.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static u16 mpp_config[] = {
> +     MPP0_GPIO,
> +     MPP1_GPIO, /* USB power enable */
> +     MPP2_GPIO, /* USB over-current indication */
> +     MPP3_GPIO, /* micro button beneath eSATA port */
> +     MPP4_GPIO,
> +     MPP5_GPIO,
> +     MPP6_GPIO,
> +     MPP7_GPIO,

May you please comment about functionality associated with uncommented GPIOs being configured here,
If you don't use these GPIOs at all on your board then you can remove them from this configuration.

> +
> +     MPP8_GPIO,
> +     MPP9_GPIO,
> +     MPP10_GPIO,
> +     MPP11_GPIO,
> +     MPP12_GPIO, /* SDIO0 card detect */
> +     MPP13_AUDIO1_EXTCLK, /* Si5351a audio clock output */
> +     MPP14_GPIO,
> +     MPP15_GPIO,
> +
> +     MPP16_GPIO,
> +     MPP17_GPIO,
> +     MPP18_GPIO, /* Red front LED */
> +     MPP19_UART3_RXD, /* IR sensor */
> +     MPP20_GPIO,
> +     MPP21_GPIO,
> +     MPP22_GPIO,
> +     MPP23_GPIO,
> +
> +     MPP_CAMERA_GPIO,


On which MPP this function is loaded? Is it MPP24? Then naming it as MPP24_XX makes sense to me.

> +     MPP_SDIO0_SDIO, /* SDIO0 */
> +     MPP_SDIO1_GPIO,
> +     MPP_AUDIO1_I2S_SPDIFO, /* SPDIF and HDMI audio */
> +     MPP_SPI_SPI, /* SPI */
> +     MPP_UART1_GPIO,
> +     MPP_NAND_GPO,
> +
> +     MPP_AUDIO0_I2S,
> +     MPP_TWSI_OPTION1, /* TWSI on dedicated pins */
> +     0 };
> +
> +int board_early_init_f(void)
> +{
> +     struct dove_gpio_init gpp = {
> +             .val0  = 0x00010186,
> +             .oe0_n = 0xffffffff,
> +             .val1  = 0x018000c0,
> +             .oe1_n = 0xffffffff,
> +             .val2  = 0x00000000,
> +             .oe2_n = 0xffffffff,
> +     };
> +
> +     dove_init_gpio(&gpp);
> +
> +     return 0;
> +}
> +
> +int board_init(void)
> +{
> +     /* adress of boot parameters */
> +     gd->bd->bi_boot_params = dove_dram_start(0) + 0x100;
> +
> +     /* configure mpp */
> +     dove_mpp_conf(mpp_config);
> +
> +     /* usb power enable */
> +     orion_gpio_direction_output(MPP1, GPIO_HIGH);
??

> +
> +     /* blink led */
> +     orion_gpio_direction_output(MPP18, GPIO_HIGH);
??

> +     orion_gpio_set_blink(MPP18, 1);
??

> +
> +     return 0;
> +}
> +
> +#ifdef CONFIG_MMC
> +int board_mmc_init(bd_t *bis)
> +{
> +     dove_sdhci_init(0);
> +     return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_RESET_PHY_R
> +void dove_eth_phy_init(char *name)
> +{
> +     u16 devadr;
> +
> +     if (miiphy_set_current_dev(name))
> +             return;
> +
> +     /* command to read PHY dev address */
> +     if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
> +             printf("Err..%s could not read PHY dev address\n",
> +                     __func__);
> +             return;
> +     }
> +
> +     /* reset the phy */
> +     miiphy_reset(name, devadr);
> +
> +     printf("%s PHY initialized\n", name);
> +}
> +
> +void reset_phy(void)
> +{
> +     dove_eth_phy_init("egiga0");
> +}
> +#endif /* CONFIG_RESET_PHY_R */
> diff --git a/board/solidrun/cubox/kwbimage.cfg
> b/board/solidrun/cubox/kwbimage.cfg
> new file mode 100644
> index 0000000..c3f1ad9
> --- /dev/null
> +++ b/board/solidrun/cubox/kwbimage.cfg
> @@ -0,0 +1,76 @@
> +#
> +# Marvell BootROM config for SolidRun CuBox
> +#
> +# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> +# MA 02110-1301 USA
> +#
> +# Refer docs/README.kwimage for more details about how-to configure
> +# and create kirkwood boot image
> +#
> +
> +# Boot Media configurations
> +BOOT_FROM    spi
> +
> +# SOC registers configuration using bootrom header extension
> +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> +
> +DATA 0xd0020104 0x00000000   # CPU Control and Status register
> +
> +# SDRAM initalization
> +DATA 0xd0800020 0x00022430   # SDRAM Configuration register 0
> +DATA 0xd0800030 0x00022430   # SDRAM Configuration register 1
> +DATA 0xd0800050 0x911500c3   # SDRAM Timing register 1
> +DATA 0xd0800060 0x646602c4   # SDRAM Timing register 2
> +DATA 0xd0800190 0xc2003053   # SDRAM Timing register 3
> +DATA 0xd08001c0 0x34f4a187   # SDRAM Timing register 4
> +DATA 0xd0800650 0x000f0121   # SDRAM Timing register 5
> +DATA 0xd0800660 0x04040200   # SDRAM Timing register 6
> +DATA 0xd0800080 0x00000000   # SDRAM Control register 1
> +DATA 0xd0800090 0x00080000   # SDRAM Control register 2
> +DATA 0xd08000f0 0xc0000000   # SDRAM Control register 3
> +DATA 0xd08001a0 0x20c0c009   # SDRAM Control register 4
> +DATA 0xd0800280 0x010e0202   # SDRAM Control register 5
> +DATA 0xd0800760 0x00000000   # SDRAM Control register 6
> +DATA 0xd0800770 0x0000000a   # SDRAM Control register 7
> +DATA 0xd0800140 0x20004044   # SDRAM PHY control register 3
> +DATA 0xd08001d0 0x133c2339   # SDRAM PHY control register 7
> +DATA 0xd08001e0 0x07700330   # SDRAM PHY control register 8
> +DATA 0xd08001f0 0x00000033   # SDRAM PHY control register 9
> +DATA 0xd0800200 0x0011311c   # SDRAM PHY control register 10
> +DATA 0xd0800210 0x00300000   # SDRAM PHY control register 11
> +DATA 0xd0800240 0x80000000   # SDRAM PHY control register 14
> +DATA 0xd0800510 0x010e0101   # SDRAM MCB control register 1
> +DATA 0xd0800230 0x2028006a   # SDRAM PHY control register 13
> +DATA 0xd0800e10 0x00280062   # SDRAM PHY DLL control registers 2
> +DATA 0xd0800e20 0x00280062   # SDRAM PHY DLL control registers 3
> +DATA 0xd0800e30 0x00280062   # SDRAM PHY DLL control registers 4
> +
> +# SDRAM memory map (2x512MB)
> +DATA 0xd0800100 0x000d0001   # SDRAM Memory Address Map register 1
> +DATA 0xd0800110 0x200d0001   # SDRAM Memory Address Map register 1
> +
> +DATA 0xd0020104 0x00000000   # CPU Control and Status register
> +DATA 0xd0020104 0x00000000   # CPU Control and Status register
> +DATA 0xd0020104 0x00000000   # CPU Control and Status register
> +DATA 0xd0020104 0x00000000   # CPU Control and Status register
> +DATA 0xd0020104 0x00000000   # CPU Control and Status register

Have you purposely repeated above lines? Why?

> +
> +# End of Header extension
> +DATA 0x0 0x0
> diff --git a/boards.cfg b/boards.cfg
> index e4b0d44..b13407e 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -293,6 +293,7 @@ whistler                     arm
> armv7:arm720t whistler          nvidia
>  colibri_t20_iris             arm         armv7:arm720t
> colibri_t20_iris  toradex        tegra20
>  u8500_href                   arm         armv7       u8500
> st-ericsson    u8500
>  snowball                     arm         armv7       snowball
> st-ericsson    u8500
> +cubox                        arm         armv7       cubox

Please check it is in order

> solidrun       dove
>  kzm9g                        arm         armv7       kzm9g
> kmc            rmobile
>  armadillo-800eva             arm         armv7       armadillo-800eva
> atmark-techno  rmobile
>  zynq                         arm         armv7       zynq
> xilinx         zynq
> diff --git a/include/configs/cubox.h b/include/configs/cubox.h
> new file mode 100644
> index 0000000..88a2fda
> --- /dev/null
> +++ b/include/configs/cubox.h
> @@ -0,0 +1,175 @@
> +/*
> + * SolidRun CuBox config
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _CONFIG_CUBOX_H
> +#define _CONFIG_CUBOX_H
> +#include <asm/sizes.h>
> +
> +/*
> + * Version number information
> + */
> +#define CONFIG_IDENT_STRING  "\SolidRun CuBox"
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_MACH_SOLIDRUN_CUBOX   /* Machine type */
> +#define CONFIG_SHOW_BOOT_PROGRESS
> +#define CONFIG_ORION_GPIO               /* Orion GPIO driver */
> +
> +#define CONFIG_SYS_NO_FLASH
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> +
> +/*
> + * Enable u-boot API for standalone programs.
> + */
> +#define CONFIG_API
> +
> +/*
> + * Enable device tree support
> + */
> +#define CONFIG_OF_LIBFDT
> +
> +/*
> + * Commands configuration
> + */
> +#include <config_cmd_default.h>
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_ENV
> +#define CONFIG_CMD_IDE
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_SF
> +#define CONFIG_CMD_SPI
> +#define CONFIG_CMD_USB
> +#define CONFIG_CMD_MMC
> +
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_EFT_PARTITION
> +
> +/*
> + * mv-common.h should be defined after CMD configs since it used them
> + * to enable certain macros
> + */
> +#include "mv-common.h"
> +
> +/*
> + * redefine mv-common.h macros for armv7/cubox
> + */
> +#undef CONFIG_SYS_PROMPT     /* previously defined in mv-common.h */
> +#define CONFIG_SYS_PROMPT    "CuBox> "       /* Command Prompt */
> +
> +/* There is no arch_misc_init on armv7 */
> +#undef CONFIG_ARCH_MISC_INIT
> +
> +#undef CONFIG_SYS_MALLOC_LEN
> +#define CONFIG_SYS_MALLOC_LEN        (4 * 1024 * 1024) /* 4MiB for
> malloc() */
> +
> +/*
> + *  Environment variables configurations
> + */
> +#if defined(CONFIG_CMD_SF)
> +#define CONFIG_SPI_FLASH_WINBOND
> +#define CONFIG_ENV_IS_IN_SPI_FLASH   1
> +#define CONFIG_ENV_SECT_SIZE         0x1000  /* 4k */
> +#define CONFIG_ENV_SIZE                      0x20000 /* 128k */
> +#define CONFIG_ENV_OFFSET            0xc0000 /* env starts here */
> +#else
> +#define CONFIG_ENV_IS_NOWHERE                1       /* if env in SDRAM */
> +#endif
> +
> +/*
> + * Default CuBox bootscript environment
> + */
> +#define CONFIG_EXTRA_ENV_SETTINGS                                    \
> +     "bootscript=boot.scr\0"                                         \
> +     "loadaddr=0x02000000\0"                                         \
> +     "mmc_started=0\0"                                               \
> +     "ide_started=0\0"                                               \
> +     "usb_started=0\0"                                               \
> +     "mtdparts=mtdparts=spi0.0:768k(u-
> boot)ro,128k(uboot_env),128k(fdt),-(empty)\0" \
> +     "ethaddr=00:50:43:15:17:17\0"

NACK: hard coding Ethernet address not allowed.

> +
> +#define CONFIG_BOOTCOMMAND                                           \
> +     "for devn in usb mmc ide ; do "                                 \
> +     "  for part in 0 1; do "                                        \
> +     "    for dir  in / /boot/;do "                                  \
> +     "      for fs in ext2 fat; do "                                 \
> +     "        echo ===> Executing ${fs}load ${devn} 0:${part}
> ${loadaddr} ${dir}${bootscript};" \
> +     "        if itest.s $devn -eq mmc; then"                        \
> +     "          if itest.s $mmc_started -ne 1; then"                 \
> +     "            mmcinfo; setenv mmc_started '1';fi;fi;"            \
> +     "        if itest.s $devn -eq usb; then"                        \
> +     "          if itest.s $usb_started -ne 1; then"                 \
> +     "            usb start; setenv usb_started '1';fi;fi;"          \
> +     "        if itest.s $devn -eq ide; then"                        \
> +     "          if itest.s $ide_started -ne 1; then"                 \
> +     "            ide reset; setenv ide_started '1';fi;fi;"          \
> +     "        if ${fs}load ${devn} 0:${part} ${loadaddr}
> ${dir}${bootscript}; then" \
> +     "          source ${loadaddr}; fi;"                             \
> +     "        if itest.s $devn -eq usb; then"                        \
> +     "          echo ===> Executing ${fs}load ${devn} 1:${part}
> ${loadaddr} ${dir}${bootscript};" \
> +     "          if ${fs}load ${devn} 1:${part} ${loadaddr}
> ${dir}${bootscript}; then" \
> +     "            source ${loadaddr}; fi;"                           \
> +     "        fi;"                                                   \
> +     "      done;"                                                   \
> +     "    done;"                                                     \
> +     "  done;"                                                       \
> +     "done;"                                                         \
> +     "tftp ${loadaddr} ${bootscript};"                               \
> +     "source ${loadaddr};"
> +
> +/*
> + * Ethernet Driver configuration
> + */
> +#ifdef CONFIG_CMD_NET
> +#define CONFIG_MVGBE_PORTS   {1}     /* enable port 0 */
> +#define CONFIG_PHY_BASE_ADR  1
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MARVELL
> +#endif /* CONFIG_CMD_NET */
> +
> +#ifdef CONFIG_CMD_IDE
> +#undef CONFIG_IDE_LED
> +#undef CONFIG_SYS_IDE_MAXBUS
> +#define CONFIG_SYS_IDE_MAXBUS                1
> +#undef CONFIG_SYS_IDE_MAXDEVICE
> +#define CONFIG_SYS_IDE_MAXDEVICE     1
> +#define CONFIG_SYS_ATA_IDE0_OFFSET   MV_SATA_PORT0_OFFSET
> +#endif
> +
> +/*
> + * File system
> + */
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_EXT4
> +#define CONFIG_CMD_FAT
> +#define CONFIG_RBTREE
> +#define CONFIG_MTD_DEVICE               /* needed for mtdparts
> commands */
> +#define CONFIG_MTD_PARTITIONS
> +#define CONFIG_CMD_MTDPARTS
> +#define CONFIG_LZO
> +
> +#endif /* _CONFIG_CUBOX_H */
> --
> 1.7.10.4

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 10/10] tools: Add support for Dove to kwboot

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 17 January 2013 00:55
> To: Sebastian Hesselbarth
> Cc: Daniel Stodden; u-boot at lists.denx.de; Rabeeh Khoury; Albert
> Aribaud; Prafulla Wadaskar; Andy Fleming; Joe Hershberger; Luka Perkov
> Subject: [PATCH v3 10/10] tools: Add support for Dove to kwboot
> 
> On Dove kwboot can also be used to boot an u-boot image into RAM.
> In contrast to Kirkwood, Dove does not support the UART boot mode
> sequence but requires the UART boot mode to be selected through
> strap pins. The SolidRun CuBox has a push button to allow uart
> boot mode but fails on the boot sequence sent by kwboot.
> 
> This patch adds another cmdline option to allow to send a boot
> image without the boot sequence and adds support for Dove.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Signed-off-by: Daniel Stodden <daniel.stodden@gmail.com>
> ---
> Cc: u-boot at lists.denx.de
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> Cc: Andy Fleming <afleming@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@gmail.com>
> Cc: Daniel Stodden <daniel.stodden@gmail.com>
> Cc: Luka Perkov <luka@openwrt.org>
> ---
>  doc/kwboot.1   |   13 ++++++++++---
>  tools/Makefile |    2 ++
>  tools/kwboot.c |   25 +++++++++++++++++++------
>  3 files changed, 31 insertions(+), 9 deletions(-)
> 
> diff --git a/doc/kwboot.1 b/doc/kwboot.1
> index 25fe69a..ab4551b 100644
> --- a/doc/kwboot.1
> +++ b/doc/kwboot.1
> @@ -1,17 +1,18 @@
> -.TH KWBOOT 1 "2012-05-19"
> +.TH KWBOOT 1 "2013-01-16"
> 
>  .SH NAME
> -kwboot \- Boot Marvell Kirkwood SoCs over a serial link.
> +kwboot \- Boot Marvell Kirkwood/Dove SoCs over a serial link.
>  .SH SYNOPSIS
>  .B kwboot
>  .RB [ "-b \fIimage\fP" ]
> +.RB [ "-n" ]
>  .RB [ "-p" ]
>  .RB [ "-t" ]
>  .RB [ "-B \fIbaudrate\fP" ]
>  .RB \fITTY\fP
>  .SH "DESCRIPTION"
> 
> -The \fBmkimage\fP program boots boards based on Marvell's Kirkwood
> +The \fBmkimage\fP program boots boards based on Marvell's
> Kirkwood/Dove
>  platform over their integrated UART. Boot image files will typically
>  contain a second stage boot loader, such as U-Boot. The image file
>  must conform to Marvell's BootROM firmware image format
> @@ -68,6 +69,12 @@ If standard I/O streams connect to a console, this
> mode will terminate
>  after receiving 'ctrl-\\' followed by 'c' from console input.
> 
>  .TP
> +.BI "\-u"
> +Disables the UART boot mode sequence for platforms that do not
> support
> +it (e.g. Dove). Usually, the UART boot mode must be selected by
> pressing
> +a push button on power-up.
> +
> +.TP
>  .BI "\-B \fIbaudrate\fP"
>  Adjust the baud rate on \fITTY\fP. Default rate is 115200.
> 
> diff --git a/tools/Makefile b/tools/Makefile
> index 686840a..4816812 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -72,6 +72,7 @@ BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
>  BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
>  BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
>  BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
> +BIN_FILES-$(CONFIG_DOVE) += kwboot$(SFX)
>  BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
> 
>  # Source files which exist outside the tools directory
> @@ -103,6 +104,7 @@ OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
>  NOPED_OBJ_FILES-y += os_support.o
>  OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
>  NOPED_OBJ_FILES-y += ublimage.o
> +OBJ_FILES-$(CONFIG_DOVE) += kwboot.o
>  OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
> 
>  # Don't build by default
> diff --git a/tools/kwboot.c b/tools/kwboot.c
> index e773f01..1e4edb6 100644
> --- a/tools/kwboot.c
> +++ b/tools/kwboot.c
> @@ -37,6 +37,10 @@ static unsigned char kwboot_msg_boot[] = {
>  	0xBB, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
>  };
> 
> +static unsigned char kwboot_msg_none[] = {
> +	0x00
> +};
> +
>  #define KWBOOT_MSG_REQ_DELAY	10 /* ms */
>  #define KWBOOT_MSG_RSP_TIMEO	50 /* ms */
> 
> @@ -268,17 +272,21 @@ kwboot_bootmsg(int tty, void *msg)
>  	int rc;
>  	char c;
> 
> -	kwboot_printv("Sending boot message. Please reboot the
> target...");
> +	kwboot_printv(msg != kwboot_msg_none
> +	      ? "Sending boot message. Please reboot the target..."
> +	      : "Sensing target. Please reboot target into UART mode...");
> 
>  	do {
>  		rc = tcflush(tty, TCIOFLUSH);
>  		if (rc)
>  			break;
> 
> -		rc = kwboot_tty_send(tty, msg, 8);
> -		if (rc) {
> -			usleep(KWBOOT_MSG_REQ_DELAY * 1000);
> -			continue;
> +		if (msg != kwboot_msg_none) {
> +			rc = kwboot_tty_send(tty, msg, 8);
> +			if (rc) {
> +				usleep(KWBOOT_MSG_REQ_DELAY * 1000);
> +				continue;
> +			}
>  		}
> 
>  		rc = kwboot_tty_recv(tty, &c, 1, KWBOOT_MSG_RSP_TIMEO);
> @@ -607,6 +615,7 @@ kwboot_usage(FILE *stream, char *progname)
>  	fprintf(stream, "  -b <image>: boot <image>\n");
>  	fprintf(stream, "  -p: patch <image> to type 0x69 (uart boot)\n");
>  	fprintf(stream, "\n");
> +	fprintf(stream, "  -n: don't send boot message\n");
>  	fprintf(stream, "  -t: mini terminal\n");
>  	fprintf(stream, "\n");
>  	fprintf(stream, "  -B <baud>: set baud rate\n");
> @@ -636,7 +645,7 @@ main(int argc, char **argv)
>  	kwboot_verbose = isatty(STDOUT_FILENO);
> 
>  	do {
> -		int c = getopt(argc, argv, "hb:ptB:");
> +		int c = getopt(argc, argv, "hb:nptB:");
>  		if (c < 0)
>  			break;
> 
> @@ -646,6 +655,10 @@ main(int argc, char **argv)
>  			imgpath = optarg;
>  			break;
> 
> +		case 'n':
> +			bootmsg = kwboot_msg_none;
> +			break;
> +
>  		case 'p':
>  			patch = 1;
>  			break;
> --
> 1.7.10.4

Acked-By: Prafulla Wadaskar <prafulla@marvell.com>

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox

[Sebastian Hesselbarth]

On 02/11/2013 04:39 AM, Prafulla Wadaskar wrote:
>> -----Original Message-----
>> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
>> Sent: 17 January 2013 00:55
>> To: Sebastian Hesselbarth
>> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
>> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
>> Subject: [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox
>>
>> This patch set add support for the Marvell Dove 88AP510 SoC and
>> the SolidRun CuBox board based on that SoC. The patch set is divided
>> into the four following sections:
>
> Dear Sabastian
> First of all I express my thanks for initiating this Soc Support in the u-boot.
> Secondly I express my apology since I could not review then immediately.
> Please find my comments for entire patch series

Prafulla,

thanks for the detailled review! I will quickly give some comments about
some of your review questions and will do a full re-review later.

* About the orion/dove/kirkwood naming convention in linux kernel (that
this patch set picks up):

When I started hacking on linux and marvell SoCs in particular there
was support for orion5x, mv78xx0, kirkwood, and dove. As those SoCs
share a bunch of internal peripherals (you might know better) the
drivers shared between those SoCs were prepended with "orion_" that
should reflect the family of SoCs with that peripherals. I personally
find the naming collision with orion5x "unlucky" but that is the way
it is.

Then there came some effort to also mainline Armada 370/XP series that
of course also share "orion" drivers. The final name for all SoCs
(including "orion") was mvebu as it is the only common naming scheme
that fit (mvebu stands for some business unit within Marvell).

Plans for using just "marvell" or "mv" were rejected because there are
also pxa SoCs from marvell sitting in the kernel tree. They likely share
some of the internal peripherals but that is not reflected within kernel
tree, as there are two different hacking communities I guess.

New drivers that fit all SoCs (namely pinctrl and gpio, because linux
API changes required new drivers from scratch) get mvebu_, drivers that
still fit in "orion" get orion_, new soc specific ones get either
dove_, kirkwood_, armada_370_, or whatever the code name of that SoC is.
Old driver names remain untouched even if they are reused on Armada
370/XP.

Whenever I used orion_ in this patch set this refers to orion as in SoC
family, not orion5x that you might have been irritated with.

* About the kwboot/kwbimage patches:
u-boot has kwboot for kirkwood since ages, but the general functionality
to boot through UART boot mode also applies to above SoCs. I took
kwbimage to reflect that kwboot should be used for booting this image.
IMHO introducing new abbreviated image names like dvbimage will just
distract people from using the correct tool to boot it. kwboot will not
be renamed, will it?

* About the ordering of patches/patch sets:
>> (1) Patches 1-5:
>
> I have suggestions to break down your patches as mentioned below
>
>> Add support for the Dove SoC and related drivers. Where possible
>> drivers from Marvell Kirkwood are reused (mvsata, mvgbe), or
>> forked to allow more generic usage (SPI, GPIO). The SDHCI driver
>> is different and a new driver is added for it. The forked drivers
>> can also be reused on Kirkwood but that would have required patching
>> existing boards.
>>
>> (2) Patches 6-8:
>> Allow mvgbe to use the phylib API, add support for 88E1310 PHY and
>> allow Dove to use the driver.
>>
>> (3) Patch 9
>> Add the SolidRun CuBox as the first board based on Marvell Dove SoC.
>>
>> (4) Patch 10
>> Add support for different UART boot mode found on Dove.
>>
>> Changelog:
>> v1->v2:
>> - respect review comments by Luka Perkov
>> - fix commenting styles and typos
>> - add MAINTAINERS entry
>> - also update kwboot.1 manpage
>>
>> v2->v3:
>> - integrate kwboot patch from Daniel Stodden
>> - rebase on release v2013.01
>>
>> Sebastian Hesselbarth (10):
>>    ARM: dove: add support for Marvell Dove SoC
>>    GPIO: add gpio driver for Orion SoCs
>>    MMC: sdhci: Add support for dove sdhci
>>    SPI: Add Orion SPI driver
>>    block: mvsata: add dove include
>>    NET: phy: add 88E1310 PHY initialization
>>    NET: mvgbe: add phylib support
>>    NET: mvgbe: add support for Dove
>>    Boards: Add support for SolidRun CuBox
>>    tools: Add support for Dove to kwboot
>>
>>   MAINTAINERS                             |    4 +
>>   arch/arm/cpu/armv7/dove/Makefile        |   49 +++++
>>   arch/arm/cpu/armv7/dove/cpu.c           |  266
>> ++++++++++++++++++++++++++
>>   arch/arm/cpu/armv7/dove/dram.c          |  118 ++++++++++++
>>   arch/arm/cpu/armv7/dove/lowlevel_init.S |   83 ++++++++
>>   arch/arm/cpu/armv7/dove/mpp.c           |  318
>> +++++++++++++++++++++++++++++++
>>   arch/arm/cpu/armv7/dove/timer.c         |  176 +++++++++++++++++
>>   arch/arm/cpu/armv7/dove/usb.c           |  101 ++++++++++
>>   arch/arm/include/asm/arch-dove/config.h |  153 +++++++++++++++
>>   arch/arm/include/asm/arch-dove/cpu.h    |  204 ++++++++++++++++++++
>>   arch/arm/include/asm/arch-dove/dove.h   |   93 +++++++++
>>   arch/arm/include/asm/arch-dove/gpio.h   |   35 ++++
>>   arch/arm/include/asm/arch-dove/mpp.h    |  283
>
> Basic Dove support (one patch series)

Ok. Just to make sure, you want me to leave driver specific stuff, e.g.
orion_spi_* out of this patch set and re-add the calls within the
corresponding driver patches?

>>   drivers/gpio/Makefile                   |    1 +
>>   include/dove or mv_gpio.h                    |   64 +++++++
>>   drivers/gpio/dove or mv_gpio.c               |  167 ++++++++++++++++
>
> GPIO driver support for Dove

With the above comments about SoC naming, I'd like to stick with
either orion_ or mvebu_ if the basic driver framework can be reused
on Armada 370/XP (when they get mainline support in u-boot).

>>   drivers/spi/Makefile                    |    1 +
>>   drivers/spi/dove_spi.c                 |  217
>
> Spi driver support for dove

Ditto.

>>   drivers/block/mvsata_ide.c              |    2 +
>>   drivers/mmc/Makefile                    |    1 +
>>   drivers/mmc/dove_sdhci.c                |  101 ++++++++++
>>   drivers/net/mvgbe.c                     |   70 ++++++-
>>   drivers/net/mvgbe.h                     |    7 +
>>   drivers/net/phy/marvell.c               |   48 +++++
>
> Other driver supports for dove (explain supported drivers)

Ack.

>> +++++++++++++++++++++++++++
>>   board/solidrun/cubox/Makefile           |   45 +++++
>>   board/solidrun/cubox/cubox.c            |  141 ++++++++++++++
>>   board/solidrun/cubox/kwbimage.cfg       |   76 ++++++++
>>   boards.cfg                              |    1 +
>>   include/configs/cubox.h                 |  175 +++++++++++++++++
>
> Board support patches

Ack.

>>   doc/kwboot.1                            |   13 +-
> +++++++++++++++++++++
>>   tools/Makefile                          |    2 +
>>   tools/kwboot.c                          |   25 ++-
>
> Add dove support for boot tool.

Ack.

> FYI: I have gone through all patches in this series

Thanks for that again! I will flip through all the individual patches
later and give detailled comments for sure.

Regards,
   Sebastian

[U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox

[Luka Perkov]

On Mon, Feb 11, 2013 at 10:43:00AM +0100, Sebastian Hesselbarth wrote:
> u-boot has kwboot for kirkwood since ages, but the general functionality
> to boot through UART boot mode also applies to above SoCs. I took
> kwbimage to reflect that kwboot should be used for booting this image.
> IMHO introducing new abbreviated image names like dvbimage will just
> distract people from using the correct tool to boot it. kwboot will not
> be renamed, will it?

I don't mind if we rename kwboot to lets say mvebu-boot. That name would
fit for kirkwood, dove and armada SoCs in the future...

Luka

[U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox

[Prafulla Wadaskar]

> -----Original Message-----
> From: Luka Perkov [mailto:luka at openwrt.org]
> Sent: 11 February 2013 02:08
> To: Sebastian Hesselbarth
> Cc: Prafulla Wadaskar; u-boot at lists.denx.de; Rabeeh Khoury; Albert
> Aribaud; Andy Fleming; Joe Hershberger; Daniel Stodden
> Subject: Re: [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox
> 
> On Mon, Feb 11, 2013 at 10:43:00AM +0100, Sebastian Hesselbarth wrote:
> > u-boot has kwboot for kirkwood since ages, but the general
> functionality
> > to boot through UART boot mode also applies to above SoCs. I took
> > kwbimage to reflect that kwboot should be used for booting this
> image.
> > IMHO introducing new abbreviated image names like dvbimage will just
> > distract people from using the correct tool to boot it. kwboot will
> not
> > be renamed, will it?
> 
> I don't mind if we rename kwboot to lets say mvebu-boot. That name
> would
> fit for kirkwood, dove and armada SoCs in the future...

That's good idea.
I vote for renaming kwboot as "mvboot", that will inline with predefined file naming strategy.

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox

[Jason Cooper]

On Mon, Feb 11, 2013 at 02:46:57PM -0800, Prafulla Wadaskar wrote:
> 
> 
> > -----Original Message-----
> > From: Luka Perkov [mailto:luka at openwrt.org]
> > Sent: 11 February 2013 02:08
> > To: Sebastian Hesselbarth
> > Cc: Prafulla Wadaskar; u-boot at lists.denx.de; Rabeeh Khoury; Albert
> > Aribaud; Andy Fleming; Joe Hershberger; Daniel Stodden
> > Subject: Re: [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox
> > 
> > On Mon, Feb 11, 2013 at 10:43:00AM +0100, Sebastian Hesselbarth wrote:
> > > u-boot has kwboot for kirkwood since ages, but the general
> > functionality
> > > to boot through UART boot mode also applies to above SoCs. I took
> > > kwbimage to reflect that kwboot should be used for booting this
> > image.
> > > IMHO introducing new abbreviated image names like dvbimage will just
> > > distract people from using the correct tool to boot it. kwboot will
> > not
> > > be renamed, will it?
> > 
> > I don't mind if we rename kwboot to lets say mvebu-boot. That name
> > would
> > fit for kirkwood, dove and armada SoCs in the future...
> 
> That's good idea.
> I vote for renaming kwboot as "mvboot", that will inline with predefined file naming strategy.

Is kwboot practically extensible to mmp and pxa?

thx,

Jason.

[U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox

[Daniel Stodden]

On Thu, 2013-02-14 at 13:38 -0500, Jason Cooper wrote:
> On Mon, Feb 11, 2013 at 02:46:57PM -0800, Prafulla Wadaskar wrote:
> > 
> > 
> > > -----Original Message-----
> > > From: Luka Perkov [mailto:luka at openwrt.org]
> > > Sent: 11 February 2013 02:08
> > > To: Sebastian Hesselbarth
> > > Cc: Prafulla Wadaskar; u-boot at lists.denx.de; Rabeeh Khoury; Albert
> > > Aribaud; Andy Fleming; Joe Hershberger; Daniel Stodden
> > > Subject: Re: [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox
> > > 
> > > On Mon, Feb 11, 2013 at 10:43:00AM +0100, Sebastian Hesselbarth wrote:
> > > > u-boot has kwboot for kirkwood since ages, but the general
> > > functionality
> > > > to boot through UART boot mode also applies to above SoCs. I took
> > > > kwbimage to reflect that kwboot should be used for booting this
> > > image.
> > > > IMHO introducing new abbreviated image names like dvbimage will just
> > > > distract people from using the correct tool to boot it. kwboot will
> > > not
> > > > be renamed, will it?
> > > 
> > > I don't mind if we rename kwboot to lets say mvebu-boot. That name
> > > would
> > > fit for kirkwood, dove and armada SoCs in the future...
> > 
> > That's good idea.
> > I vote for renaming kwboot as "mvboot", that will inline with predefined file naming strategy.
> 
> Is kwboot practically extensible to mmp and pxa?

If those have a similar mechanism, and it happens to be based on Xmodem,
then there's probably sharable ground.

The boot message protocol on Marvell chips is a fairly ad-hoc construct.

Daniel

[U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox

[Jason Cooper]

On Thu, Feb 14, 2013 at 01:35:47PM -0800, Daniel Stodden wrote:
> On Thu, 2013-02-14 at 13:38 -0500, Jason Cooper wrote:
> > On Mon, Feb 11, 2013 at 02:46:57PM -0800, Prafulla Wadaskar wrote:
> > > 
> > > 
> > > > -----Original Message-----
> > > > From: Luka Perkov [mailto:luka at openwrt.org]
> > > > Sent: 11 February 2013 02:08
> > > > To: Sebastian Hesselbarth
> > > > Cc: Prafulla Wadaskar; u-boot at lists.denx.de; Rabeeh Khoury; Albert
> > > > Aribaud; Andy Fleming; Joe Hershberger; Daniel Stodden
> > > > Subject: Re: [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox
> > > > 
> > > > On Mon, Feb 11, 2013 at 10:43:00AM +0100, Sebastian Hesselbarth wrote:
> > > > > u-boot has kwboot for kirkwood since ages, but the general
> > > > functionality
> > > > > to boot through UART boot mode also applies to above SoCs. I took
> > > > > kwbimage to reflect that kwboot should be used for booting this
> > > > image.
> > > > > IMHO introducing new abbreviated image names like dvbimage will just
> > > > > distract people from using the correct tool to boot it. kwboot will
> > > > not
> > > > > be renamed, will it?
> > > > 
> > > > I don't mind if we rename kwboot to lets say mvebu-boot. That name
> > > > would
> > > > fit for kirkwood, dove and armada SoCs in the future...
> > > 
> > > That's good idea.
> > > I vote for renaming kwboot as "mvboot", that will inline with predefined file naming strategy.
> > 
> > Is kwboot practically extensible to mmp and pxa?
> 
> If those have a similar mechanism, and it happens to be based on Xmodem,
> then there's probably sharable ground.
> 
> The boot message protocol on Marvell chips is a fairly ad-hoc construct.

right, I was more concerned with the naming convention.  At least in the
kernel, mvebu includes all Marvell SoCs _except_ mmp and pxa.  I would
presume mv would be an all-inclusive name.

I didn't really have a strong opinion on it, so I'm fine either way.  In
hindsight, I'd prefer not to type 'mvebu-boot'...

thx,

Jason.

[U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox

[Prafulla Wadaskar]

> -----Original Message-----
> From: Jason Cooper [mailto:jason at lakedaemon.net]
> Sent: 14 February 2013 13:44
> To: Daniel Stodden
> Cc: Prafulla Wadaskar; Luka Perkov; Sebastian Hesselbarth; Rabeeh
> Khoury; u-boot at lists.denx.de; Andy at theia.denx.de; Fleming
> Subject: Re: [U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun
> CuBox
> 
> On Thu, Feb 14, 2013 at 01:35:47PM -0800, Daniel Stodden wrote:
> > On Thu, 2013-02-14 at 13:38 -0500, Jason Cooper wrote:
> > > On Mon, Feb 11, 2013 at 02:46:57PM -0800, Prafulla Wadaskar wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Luka Perkov [mailto:luka at openwrt.org]
> > > > > Sent: 11 February 2013 02:08
> > > > > To: Sebastian Hesselbarth
> > > > > Cc: Prafulla Wadaskar; u-boot at lists.denx.de; Rabeeh Khoury;
> Albert
> > > > > Aribaud; Andy Fleming; Joe Hershberger; Daniel Stodden
> > > > > Subject: Re: [PATCH v3 00/10] Add Marvell Dove and SolidRun
> CuBox
> > > > >
> > > > > On Mon, Feb 11, 2013 at 10:43:00AM +0100, Sebastian
> Hesselbarth wrote:
> > > > > > u-boot has kwboot for kirkwood since ages, but the general
> > > > > functionality
> > > > > > to boot through UART boot mode also applies to above SoCs. I
> took
> > > > > > kwbimage to reflect that kwboot should be used for booting
> this
> > > > > image.
> > > > > > IMHO introducing new abbreviated image names like dvbimage
> will just
> > > > > > distract people from using the correct tool to boot it.
> kwboot will
> > > > > not
> > > > > > be renamed, will it?
> > > > >
> > > > > I don't mind if we rename kwboot to lets say mvebu-boot. That
> name
> > > > > would
> > > > > fit for kirkwood, dove and armada SoCs in the future...
> > > >
> > > > That's good idea.
> > > > I vote for renaming kwboot as "mvboot", that will inline with
> predefined file naming strategy.
> > >
> > > Is kwboot practically extensible to mmp and pxa?
> >
> > If those have a similar mechanism, and it happens to be based on
> Xmodem,
> > then there's probably sharable ground.
> >
> > The boot message protocol on Marvell chips is a fairly ad-hoc
> construct.
> 
> right, I was more concerned with the naming convention.  At least in
> the
> kernel, mvebu includes all Marvell SoCs _except_ mmp and pxa.  I would
> presume mv would be an all-inclusive name.
> 
> I didn't really have a strong opinion on it, so I'm fine either way.
> In
> hindsight, I'd prefer not to type 'mvebu-boot'...

If the code or tool is being shared between more that one Marvell SoCs, it makes sense to use mv_** naming convention. This is to inline with the Marvell's naming strategy implemented so far in u-boot code.

Whereas, we can always have <soc>_<functionality> type of naming conventions for specific implementation.

At present, kwboot is specific to Kirkwood, the support is being extended for Dove and latter few more.. so it makes sense to rename it as mvboot.

I need to check whether kwboot is practically extensible to mmp and pxa, but it makes sense to rename it as mvboot since it supports more than Kirkwood.

Regards..
Prafulla . . .

[U-Boot] [PATCH v2 01/10] ARM: dove: add support for Marvell Dove SoC

[Sebastian Hesselbarth]

Prafulla,

thanks for the review. I added some notes below at your comments.

On 02/11/2013 04:39 AM, Prafulla Wadaskar wrote:
>>
>> [...]
>>
>> diff --git a/arch/arm/cpu/armv7/dove/mpp.c
>> b/arch/arm/cpu/armv7/dove/mpp.c
>> new file mode 100644
>> index 0000000..ed24b38
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7/dove/mpp.c
>> @@ -0,0 +1,318 @@
>>
>> [...]
>>
>> +/*
>> + * MPP0-23 have standard MPP register layout
>> + */
>> +static void dove_mpp_std_set(u16 config)
>> +{
>> +     u8 num = MPP_NUM(config);
>> +     u32 off = (num / MPPS_PER_REG) * MPP_BITS;
>> +     u32 shift = (num % MPPS_PER_REG) * MPP_BITS;
>> +     u32 reg;
>> +
>> +     /* configure standard MPP pin */
>> +     reg  = readl(MPP_CTRL(off));
>> +     reg&= ~(MPP_MASK<<  shift);
>> +     reg |= MPP_SEL(config)<<  shift;
>> +     writel(reg, MPP_CTRL(off));
>> +
>> +     /* configure gpio capabilities */
>> +     if (MPP_GPIO(config))
>> +             orion_gpio_set_valid(num, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
>> +     else
>> +             orion_gpio_set_valid(num, 0);
>
> Why it is orion_gpio*? it should be generic API call or SoC specific.

Dove is reusing orion gpio, orion refers to the SoC family not orion5x.

>> +}
>> +
>> +/*
>> + * MPP0-15 also allow to mux PMU functions
>> + */
>> +static void dove_mpp_pmu_set(u16 config)
>> +{
>> +     u8 num = MPP_NUM(config);
>> +
>> +     if (MPP_SEL(config) == PMU) {
>> +             /* enable PMU on MPP */
>> +             writel(readl(MPP_PMU_GENERAL_CTRL) | (1<<  num),
>> +                    MPP_PMU_GENERAL_CTRL);
>> +             /* disable gpio capabilities */
>> +             orion_gpio_set_valid(num, 0);
>
> I think you are trying to reuse the framework implemented by orion,
> You may move generic part from orion to common area so that you can use it. Using other SoC direct calls doesn't sound good to me.

Kirkwood and others using orion_gpio have very regular layout of mpp pins and
gpio functionality, i.e. you have one pin with one mpp layout and if you want
it to be gpio you choose "gpio" as it's mpp function.

Well, Dove is different here. You first have mpp0-15 which can be either
"normal" mpp pins _or_ assigned to power management unit (pmu). Then there
are mpp groups where more than one pin is controlled by a single mpp register
value. As there are some groups that have some of the pins configured as gpios
while others carry a special function, I chose to have gpio capabilities
configured by mpp code not by gpio function.

>> [...]
>>
>> diff --git a/arch/arm/include/asm/arch-dove/config.h
>> b/arch/arm/include/asm/arch-dove/config.h
>> new file mode 100644
>> index 0000000..2d94a48
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-dove/config.h
>> @@ -0,0 +1,153 @@
>>
>> [...]
>>
>> +/*
>> + * By default kwbimage.cfg from board specific folder is used
>
> I think you should use dvbimage.cfg naming convention, since kwb stands for Kirkwood boot image, same way it will be dove boot image

With recent discussion about renaming kwboot to mvboot, shouldn't this
become mvbimage.cfg?

>> + * If for some board, different configuration file need to be used,
>> + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header
>> file
>> + */
>> +#ifndef CONFIG_SYS_KWD_CONFIG
>> +#define      CONFIG_SYS_KWD_CONFIG
>>        $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
>> +#endif /* CONFIG_SYS_KWD_CONFIG */
>
> Same: change all references to DOVE, secondly do you think DV is better than DOVE to shorten then name everywhere like KW for Kirkwood?

Ditto, rename KWD to MV or MVB?

>> [...]
>> +/*
>> + * SPI Flash configuration
>> + */
>> +#ifdef CONFIG_CMD_SF
>> +#define CONFIG_HARD_SPI                      1
>> +#define CONFIG_ORION_SPI             1
>> +#define ORION_SPI_BASE                       DOVE_SPI_BASE
>
> ???

Again, Orion refers to SoC family and Dove is reusing the driver.

Sebastian

[U-Boot] [PATCH v3 02/10] GPIO: add gpio driver for Orion SoCs

[Sebastian Hesselbarth]

On 02/11/2013 04:39 AM, Prafulla Wadaskar wrote:
>> -----Original Message----- From: Sebastian Hesselbarth
>> [mailto:sebastian.hesselbarth at gmail.com] Sent: 17 January 2013 00:55 To: Sebastian Hesselbarth
>> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla Wadaskar; Andy Fleming; Joe
>> Hershberger; Daniel Stodden; Luka Perkov Subject: [PATCH v3 02/10] GPIO: add gpio driver for
>> Orion SoCs
>>
>> This adds a gpio driver for Marvell Orion SoCs, i.e. orion5x, kirkwood, dove. This is based on
>> kw_gpio but as gpio capabilities depend heavily on the mpp configuration for dove, it allows to
>> set gpi/gpo capabilities from mpp. This should be compatible with the current kw_gpio and
>> porting mpp of kirkwood and orion5x is appreciated.
>
> Nack, your patch series is for dove, you shouldn't add for orion, unless you are using it. If you
> think this is common framework can be used across the other marvell SoCs, we have strategy to
> name it like mv_***
>
> So you may name this driver as mv_gpio

Prafulla,

I still think that mv_ as a prefix is too short. Remember that Marvell also has
pxa SoCs and with latest SoCs handling of gpio may change dramatically.

We should rather stick to orion_ for Orion5x, Kirkwood, Dove or move to
mvebu_ for above plus Armada XP/370.

Sebastian

[U-Boot] [PATCH v3 08/10] NET: mvgbe: add support for Dove

[Sebastian Hesselbarth]

On 02/11/2013 04:39 AM, Prafulla Wadaskar wrote:
>> -----Original Message-----
>> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
>> Sent: 17 January 2013 00:55
>> To: Sebastian Hesselbarth
>> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
>> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
>> Subject: [PATCH v3 08/10] NET: mvgbe: add support for Dove
>>
>> Marvell Dove also uses mvgbe as ethernet driver, therefore add support
>> for Dove to reuse the current driver.
>>
>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>
>> ---
>> Cc: u-boot at lists.denx.de
>> Cc: Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>
>> Cc: Rabeeh Khoury<rabeeh@solid-run.com>
>> Cc: Albert Aribaud<albert.u.boot@aribaud.net>
>> Cc: Prafulla Wadaskar<prafulla@marvell.com>
>> Cc: Andy Fleming<afleming@gmail.com>
>> Cc: Joe Hershberger<joe.hershberger@gmail.com>
>> Cc: Daniel Stodden<daniel.stodden@gmail.com>
>> Cc: Luka Perkov<luka@openwrt.org>
>> ---
>>   drivers/net/mvgbe.c |    2 ++
>>   drivers/net/mvgbe.h |    7 +++++++
>>   2 files changed, 9 insertions(+)
>>
>> diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
>> index 192c989..590ea0b 100644
>> --- a/drivers/net/mvgbe.c
>> +++ b/drivers/net/mvgbe.c
>> @@ -43,6 +43,8 @@
>>   #include<asm/arch/kirkwood.h>
>>   #elif defined(CONFIG_ORION5X)
>>   #include<asm/arch/orion5x.h>
>> +#elif defined(CONFIG_DOVE)
>> +#include<asm/arch/dove.h>
>>   #endif
>>
>>   #include "mvgbe.h"
>> diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
>> index d8a5429..7f5d98f 100644
>> --- a/drivers/net/mvgbe.h
>> +++ b/drivers/net/mvgbe.h
>> @@ -308,10 +308,17 @@
>>   #define EBAR_TARGET_GUNIT			0x00000007
>>
>>   /* Window attrib */
>> +#if defined(CONFIG_DOVE)
>> +#define EBAR_DRAM_CS0				0x00000000
>> +#define EBAR_DRAM_CS1				0x00000000
>> +#define EBAR_DRAM_CS2				0x00000000
>> +#define EBAR_DRAM_CS3				0x00000000
>
> What does this means?
> May you please explain?

These are ORed with other BAR values within mvgbe and control access
of mvgbe bus master to sdram. In contrast to Kirkwood, Dove has only
one sdram target interface with attribute 0x0 while Kirkwood has four
different target IDs each for one sdram bank.

Sebastian

[U-Boot] [PATCH v3 08/10] NET: mvgbe: add support for Dove

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth
> [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 03 March 2013 17:14
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert
> Aribaud; Andy Fleming; Joe Hershberger; Daniel Stodden;
> Luka Perkov
> Subject: Re: [PATCH v3 08/10] NET: mvgbe: add support
> for Dove
> 
> On 02/11/2013 04:39 AM, Prafulla Wadaskar wrote:
> >> -----Original Message-----
> >> From: Sebastian Hesselbarth
> [mailto:sebastian.hesselbarth at gmail.com]
> >> Sent: 17 January 2013 00:55
> >> To: Sebastian Hesselbarth
> >> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert
> Aribaud; Prafulla
> >> Wadaskar; Andy Fleming; Joe Hershberger; Daniel
> Stodden; Luka Perkov
> >> Subject: [PATCH v3 08/10] NET: mvgbe: add support
> for Dove
> >>
> >> Marvell Dove also uses mvgbe as ethernet driver,
> therefore add support
> >> for Dove to reuse the current driver.
> >>
> >> Signed-off-by: Sebastian
> Hesselbarth<sebastian.hesselbarth@gmail.com>
> >> ---
> >> Cc: u-boot at lists.denx.de
> >> Cc: Sebastian
> Hesselbarth<sebastian.hesselbarth@gmail.com>
> >> Cc: Rabeeh Khoury<rabeeh@solid-run.com>
> >> Cc: Albert Aribaud<albert.u.boot@aribaud.net>
> >> Cc: Prafulla Wadaskar<prafulla@marvell.com>
> >> Cc: Andy Fleming<afleming@gmail.com>
> >> Cc: Joe Hershberger<joe.hershberger@gmail.com>
> >> Cc: Daniel Stodden<daniel.stodden@gmail.com>
> >> Cc: Luka Perkov<luka@openwrt.org>
> >> ---
> >>   drivers/net/mvgbe.c |    2 ++
> >>   drivers/net/mvgbe.h |    7 +++++++
> >>   2 files changed, 9 insertions(+)
> >>
> >> diff --git a/drivers/net/mvgbe.c
> b/drivers/net/mvgbe.c
> >> index 192c989..590ea0b 100644
> >> --- a/drivers/net/mvgbe.c
> >> +++ b/drivers/net/mvgbe.c
> >> @@ -43,6 +43,8 @@
> >>   #include<asm/arch/kirkwood.h>
> >>   #elif defined(CONFIG_ORION5X)
> >>   #include<asm/arch/orion5x.h>
> >> +#elif defined(CONFIG_DOVE)
> >> +#include<asm/arch/dove.h>
> >>   #endif
> >>
> >>   #include "mvgbe.h"
> >> diff --git a/drivers/net/mvgbe.h
> b/drivers/net/mvgbe.h
> >> index d8a5429..7f5d98f 100644
> >> --- a/drivers/net/mvgbe.h
> >> +++ b/drivers/net/mvgbe.h
> >> @@ -308,10 +308,17 @@
> >>   #define EBAR_TARGET_GUNIT			0x00000007
> >>
> >>   /* Window attrib */
> >> +#if defined(CONFIG_DOVE)
> >> +#define EBAR_DRAM_CS0				0x00000000
> >> +#define EBAR_DRAM_CS1				0x00000000
> >> +#define EBAR_DRAM_CS2				0x00000000
> >> +#define EBAR_DRAM_CS3				0x00000000
> >
> > What does this means?
> > May you please explain?
> 
> These are ORed with other BAR values within mvgbe and
> control access
> of mvgbe bus master to sdram. In contrast to Kirkwood,
> Dove has only
> one sdram target interface with attribute 0x0 while
> Kirkwood has four
> different target IDs each for one sdram bank.
> 

Dear Sebastian
Since dove has only one SDRAM bank
You should do
#undef EBAR_DRAM_CS1/2/3 instead of defining them zero, and manage the same effectively in the code.

To me, defining unavailable banks doesn't sound good.

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 02/10] GPIO: add gpio driver for Orion SoCs

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth
> [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 03 March 2013 17:07
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert
> Aribaud; Andy Fleming; Joe Hershberger; Daniel Stodden;
> Luka Perkov
> Subject: Re: [PATCH v3 02/10] GPIO: add gpio driver for
> Orion SoCs
> 
> On 02/11/2013 04:39 AM, Prafulla Wadaskar wrote:
> >> -----Original Message----- From: Sebastian
> Hesselbarth
> >> [mailto:sebastian.hesselbarth at gmail.com] Sent: 17
> January 2013 00:55 To: Sebastian Hesselbarth
> >> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert
> Aribaud; Prafulla Wadaskar; Andy Fleming; Joe
> >> Hershberger; Daniel Stodden; Luka Perkov Subject:
> [PATCH v3 02/10] GPIO: add gpio driver for
> >> Orion SoCs
> >>
> >> This adds a gpio driver for Marvell Orion SoCs, i.e.
> orion5x, kirkwood, dove. This is based on
> >> kw_gpio but as gpio capabilities depend heavily on
> the mpp configuration for dove, it allows to
> >> set gpi/gpo capabilities from mpp. This should be
> compatible with the current kw_gpio and
> >> porting mpp of kirkwood and orion5x is appreciated.
> >
> > Nack, your patch series is for dove, you shouldn't
> add for orion, unless you are using it. If you
> > think this is common framework can be used across the
> other marvell SoCs, we have strategy to
> > name it like mv_***
> >
> > So you may name this driver as mv_gpio
> 
> Prafulla,
> 
> I still think that mv_ as a prefix is too short.
> Remember that Marvell also has
> pxa SoCs and with latest SoCs handling of gpio may
> change dramatically.

Dear Sabastian,
We already have code with this naming convention sitting in u-boot from long, so to sync with that we should use "mv".

Pxa is handled separately at this moment, it is outside our scope at this moment. In case if it conflicts pxa developer may consider a prefix "mvpxa"
 
> 
> We should rather stick to orion_ for Orion5x, Kirkwood,
> Dove or move to
> mvebu_ for above plus Armada XP/370.

Orion_, Kirkwood_ fine with me, but mvebu doesn't sound good for dove (ebu is business unit name), if "dv" does not sound good then you can use "dove" prefix.

Shorter names gives smaller source code :-)

Regards...
Prafulla . . .

> 
> Sebastian

[U-Boot] [PATCH v2 01/10] ARM: dove: add support for Marvell Dove SoC

[Prafulla Wadaskar]

> -----Original Message-----
> From: Sebastian Hesselbarth
> [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 03 March 2013 17:01
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert
> Aribaud; Andy Fleming; Joe Hershberger; Daniel Stodden;
> Luka Perkov
> Subject: Re: [PATCH v2 01/10] ARM: dove: add support
> for Marvell Dove SoC
> 
> Prafulla,
> 
> thanks for the review. I added some notes below at your
> comments.
> 
> On 02/11/2013 04:39 AM, Prafulla Wadaskar wrote:
> >>
> >> [...]
> >>
> >> diff --git a/arch/arm/cpu/armv7/dove/mpp.c
> >> b/arch/arm/cpu/armv7/dove/mpp.c
> >> new file mode 100644
> >> index 0000000..ed24b38
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/armv7/dove/mpp.c
> >> @@ -0,0 +1,318 @@
> >>
> >> [...]
> >>
> >> +/*
> >> + * MPP0-23 have standard MPP register layout
> >> + */
> >> +static void dove_mpp_std_set(u16 config)
> >> +{
> >> +     u8 num = MPP_NUM(config);
> >> +     u32 off = (num / MPPS_PER_REG) * MPP_BITS;
> >> +     u32 shift = (num % MPPS_PER_REG) * MPP_BITS;
> >> +     u32 reg;
> >> +
> >> +     /* configure standard MPP pin */
> >> +     reg  = readl(MPP_CTRL(off));
> >> +     reg&= ~(MPP_MASK<<  shift);
> >> +     reg |= MPP_SEL(config)<<  shift;
> >> +     writel(reg, MPP_CTRL(off));
> >> +
> >> +     /* configure gpio capabilities */
> >> +     if (MPP_GPIO(config))
> >> +             orion_gpio_set_valid(num,
> GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> >> +     else
> >> +             orion_gpio_set_valid(num, 0);
> >
> > Why it is orion_gpio*? it should be generic API call
> or SoC specific.
> 
> Dove is reusing orion gpio, orion refers to the SoC
> family not orion5x.

So let's rename them as "mv" as per strategy.
I don't have any issue to refer "mv_gpio" in dove code.

> 
> >> +}
> >> +
> >> +/*
> >> + * MPP0-15 also allow to mux PMU functions
> >> + */
> >> +static void dove_mpp_pmu_set(u16 config)
> >> +{
> >> +     u8 num = MPP_NUM(config);
> >> +
> >> +     if (MPP_SEL(config) == PMU) {
> >> +             /* enable PMU on MPP */
> >> +             writel(readl(MPP_PMU_GENERAL_CTRL) |
> (1<<  num),
> >> +                    MPP_PMU_GENERAL_CTRL);
> >> +             /* disable gpio capabilities */
> >> +             orion_gpio_set_valid(num, 0);
> >
> > I think you are trying to reuse the framework
> implemented by orion,
> > You may move generic part from orion to common area
> so that you can use it. Using other SoC direct calls
> doesn't sound good to me.
> 
> Kirkwood and others using orion_gpio have very regular
> layout of mpp pins and
> gpio functionality, i.e. you have one pin with one mpp
> layout and if you want
> it to be gpio you choose "gpio" as it's mpp function.
> 
> Well, Dove is different here. You first have mpp0-15
> which can be either
> "normal" mpp pins _or_ assigned to power management
> unit (pmu). Then there
> are mpp groups where more than one pin is controlled by
> a single mpp register
> value. As there are some groups that have some of the
> pins configured as gpios
> while others carry a special function, I chose to have
> gpio capabilities
> configured by mpp code not by gpio function.

So we can have generic mv specific APIs and the SoC specific layer can be abstracted if possible.
If the integration is not possible with generic code then you can always have dove_gpio driver.

> 
> >> [...]
> >>
> >> diff --git a/arch/arm/include/asm/arch-dove/config.h
> >> b/arch/arm/include/asm/arch-dove/config.h
> >> new file mode 100644
> >> index 0000000..2d94a48
> >> --- /dev/null
> >> +++ b/arch/arm/include/asm/arch-dove/config.h
> >> @@ -0,0 +1,153 @@
> >>
> >> [...]
> >>
> >> +/*
> >> + * By default kwbimage.cfg from board specific
> folder is used
> >
> > I think you should use dvbimage.cfg naming
> convention, since kwb stands for Kirkwood boot image,
> same way it will be dove boot image
> 
> With recent discussion about renaming kwboot to mvboot,
> shouldn't this
> become mvbimage.cfg?

Tool could be mvboot, configuration image can be mv/kw/dvbimage.cfg. But I don't have any issue with name mvbimage.cfg

> 
> >> + * If for some board, different configuration file
> need to be used,
> >> + * CONFIG_SYS_KWD_CONFIG should be defined in board
> specific header
> >> file
> >> + */
> >> +#ifndef CONFIG_SYS_KWD_CONFIG
> >> +#define      CONFIG_SYS_KWD_CONFIG
> >>        $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
> >> +#endif /* CONFIG_SYS_KWD_CONFIG */
> >
> > Same: change all references to DOVE, secondly do you
> think DV is better than DOVE to shorten then name
> everywhere like KW for Kirkwood?
> 
> Ditto, rename KWD to MV or MVB?
> 
> >> [...]
> >> +/*
> >> + * SPI Flash configuration
> >> + */
> >> +#ifdef CONFIG_CMD_SF
> >> +#define CONFIG_HARD_SPI                      1
> >> +#define CONFIG_ORION_SPI             1
> >> +#define ORION_SPI_BASE
> DOVE_SPI_BASE
> >
> > ???
> 
> Again, Orion refers to SoC family and Dove is reusing
> the driver.

Let's use mv if the code is being shared.

Regards...
Prafulla . . .

> 
> Sebastian

[U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox

[Sascha Silbe]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> This patch set add support for the Marvell Dove 88AP510 SoC and
> the SolidRun CuBox board based on that SoC. The patch set is divided
> into the four following sections:
[...]

What's the state of this? I tried applying your patch series on top of
current master and getting it to work on a CuBox Pro (2GiB SDRAM instead
of 1GiB), but with no success so far. I changed kwbimage.cfg to match
dramregs_cubox_2gb.txt in Rabeeh's tree and fixed
arch/arm/cpu/armv7/dove/timer.c to work with the generic global_data
(introduced by baa1e53 and 50b1fa3). However there seems to be something
else missing or broken as there's no output whatsoever on the serial
console after booting the new image via UART. The same boot procedure
works fine with an image built using Rabeeh's tree.

Sascha
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[U-Boot] [PATCH v4 00/10] Add Marvell Dove and SolidRun CuBox support

[Sascha Silbe]

Got this to work. The problem was that I didn't know about "make
u-boot.kwb", so I tried invoking mkimage using the load address and
entry point used in Rabeeh's tree. For some reason, the entry point is
different in mainline U-Boot.

Changes compared to v3 from Sebastian:
- rebased on master (using generic global_data)
- added support for CuBox Pro and UART boot
- second USB port works now
- drives > 2TiB work now
- using dove_* naming convention rather than orion_* (mv is already
  taken, at least for GPIO)
- removed EBAR_DRAM_CS* for dove (dove doesn't encode SDRAM bank in
  attributes)
- removed hard-coded ethaddr
- general clean-ups (checkpatch clean except for one spot now)


I'm assuming Sebastian (CC'ed) is still willing to be the maintainer.


Sascha Silbe (1):
  usb: ehci-marvell: add support for second USB controller

Sebastian Hesselbarth (9):
  ARM: dove: add support for Marvell Dove SoC
  GPIO: add gpio driver for Dove SoCs
  MMC: sdhci: Add support for dove sdhci
  SPI: Add Dove SPI driver
  block: mvsata: add dove include
  NET: phy: add 88E1310 PHY initialization
  NET: mvgbe: add phylib support
  NET: mvgbe: add support for Dove
  Boards: Add support for SolidRun CuBox

 MAINTAINERS                               |   4 +
 arch/arm/cpu/armv7/dove/Makefile          |  49 +++++
 arch/arm/cpu/armv7/dove/cpu.c             | 274 +++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/dram.c            | 117 +++++++++++
 arch/arm/cpu/armv7/dove/lowlevel_init.S   |  83 ++++++++
 arch/arm/cpu/armv7/dove/mpp.c             | 318 ++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/timer.c           | 176 +++++++++++++++++
 arch/arm/cpu/armv7/dove/usb.c             | 101 ++++++++++
 arch/arm/include/asm/arch-dove/config.h   | 153 ++++++++++++++
 arch/arm/include/asm/arch-dove/cpu.h      | 204 +++++++++++++++++++
 arch/arm/include/asm/arch-dove/dove.h     |  98 +++++++++
 arch/arm/include/asm/arch-dove/gpio.h     |  35 ++++
 arch/arm/include/asm/arch-dove/mmc.h      |  27 +++
 arch/arm/include/asm/arch-dove/mpp.h      | 283 ++++++++++++++++++++++++++
 arch/arm/include/asm/arch-dove/usb.h      |  27 +++
 board/solidrun/cubox/Makefile             |  45 +++++
 board/solidrun/cubox/cubox.c              | 142 +++++++++++++
 board/solidrun/cubox/kwbimage-spi-1gb.cfg |  76 +++++++
 board/solidrun/cubox/kwbimage-spi-2gb.cfg |  76 +++++++
 board/solidrun/cubox/kwbimage-uart.cfg    |  76 +++++++
 boards.cfg                                |   3 +
 drivers/block/mvsata_ide.c                |   2 +
 drivers/gpio/Makefile                     |   1 +
 drivers/gpio/dove_gpio.c                  | 167 ++++++++++++++++
 drivers/mmc/Makefile                      |   1 +
 drivers/mmc/dove_sdhci.c                  | 101 ++++++++++
 drivers/net/mvgbe.c                       |  83 +++++++-
 drivers/net/mvgbe.h                       |   2 +
 drivers/net/phy/marvell.c                 |  48 +++++
 drivers/spi/Makefile                      |   1 +
 drivers/spi/dove_spi.c                    | 212 ++++++++++++++++++++
 drivers/usb/host/ehci-marvell.c           |  35 ++--
 include/configs/cubox.h                   | 185 +++++++++++++++++
 include/dove_gpio.h                       |  64 ++++++
 34 files changed, 3251 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/dove/Makefile
 create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
 create mode 100644 arch/arm/cpu/armv7/dove/dram.c
 create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
 create mode 100644 arch/arm/cpu/armv7/dove/timer.c
 create mode 100644 arch/arm/cpu/armv7/dove/usb.c
 create mode 100644 arch/arm/include/asm/arch-dove/config.h
 create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
 create mode 100644 arch/arm/include/asm/arch-dove/dove.h
 create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
 create mode 100644 arch/arm/include/asm/arch-dove/mmc.h
 create mode 100644 arch/arm/include/asm/arch-dove/mpp.h
 create mode 100644 arch/arm/include/asm/arch-dove/usb.h
 create mode 100644 board/solidrun/cubox/Makefile
 create mode 100644 board/solidrun/cubox/cubox.c
 create mode 100644 board/solidrun/cubox/kwbimage-spi-1gb.cfg
 create mode 100644 board/solidrun/cubox/kwbimage-spi-2gb.cfg
 create mode 100644 board/solidrun/cubox/kwbimage-uart.cfg
 create mode 100644 drivers/gpio/dove_gpio.c
 create mode 100644 drivers/mmc/dove_sdhci.c
 create mode 100644 drivers/spi/dove_spi.c
 create mode 100644 include/configs/cubox.h
 create mode 100644 include/dove_gpio.h

-- 
1.8.2.1

[U-Boot] [PATCH v4 01/10] ARM: dove: add support for Marvell Dove SoC

[Sascha Silbe]

From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

This patch adds initial support for the armv7-based Marvell Dove SoC
(88AP510).

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v3->v4: added second USB port; added support for hard disks > 2TiB;
         adapted to generic global_data; added usb.h to define
         dove_ehci_phy_init for cpu.c; made checkpatch clean

 arch/arm/cpu/armv7/dove/Makefile        |  49 +++++
 arch/arm/cpu/armv7/dove/cpu.c           | 274 +++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/dram.c          | 117 ++++++++++++
 arch/arm/cpu/armv7/dove/lowlevel_init.S |  83 +++++++++
 arch/arm/cpu/armv7/dove/mpp.c           | 318 ++++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/timer.c         | 176 ++++++++++++++++++
 arch/arm/cpu/armv7/dove/usb.c           | 101 ++++++++++
 arch/arm/include/asm/arch-dove/config.h | 153 +++++++++++++++
 arch/arm/include/asm/arch-dove/cpu.h    | 204 ++++++++++++++++++++
 arch/arm/include/asm/arch-dove/dove.h   |  98 ++++++++++
 arch/arm/include/asm/arch-dove/gpio.h   |  35 ++++
 arch/arm/include/asm/arch-dove/mpp.h    | 283 ++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-dove/usb.h    |  27 +++
 13 files changed, 1918 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/dove/Makefile
 create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
 create mode 100644 arch/arm/cpu/armv7/dove/dram.c
 create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
 create mode 100644 arch/arm/cpu/armv7/dove/timer.c
 create mode 100644 arch/arm/cpu/armv7/dove/usb.c
 create mode 100644 arch/arm/include/asm/arch-dove/config.h
 create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
 create mode 100644 arch/arm/include/asm/arch-dove/dove.h
 create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
 create mode 100644 arch/arm/include/asm/arch-dove/mpp.h
 create mode 100644 arch/arm/include/asm/arch-dove/usb.h

diff --git a/arch/arm/cpu/armv7/dove/Makefile b/arch/arm/cpu/armv7/dove/Makefile
new file mode 100644
index 0000000..127d67e
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/Makefile
@@ -0,0 +1,49 @@
+#
+# Marvell Dove SoC Makefile
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	+= lowlevel_init.o
+COBJS-y := cpu.o dram.o timer.o mpp.o
+COBJS-$(CONFIG_USB_EHCI_MARVELL) += usb.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/dove/cpu.c b/arch/arm/cpu/armv7/dove/cpu.c
new file mode 100644
index 0000000..b5320b7
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/cpu.c
@@ -0,0 +1,274 @@
+/*
+ * Marvell Dove SoC cpu related functions
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <u-boot/md5.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/usb.h>
+#include <hush.h>
+
+void reset_cpu(unsigned long ignored)
+{
+	struct dovecpu_registers *cpureg =
+	    (struct dovecpu_registers *)DOVE_CPU_REG_BASE;
+
+	/* Enable soft reset to assert RSTOUTn */
+	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+	       &cpureg->rstoutn_mask);
+	/* Assert soft reset */
+	writel(readl(&cpureg->sys_soft_rst) | 1,
+	       &cpureg->sys_soft_rst);
+	do {} while (1);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int dove_print_cpu(void)
+{
+	char *cpu;
+	u32 idreg;
+	u16 part, rev;
+
+	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(idreg));
+
+	part = (idreg >> ARM_ID_PARTNUM_OFFSET) & ARM_ID_PARTNUM_MASK;
+	rev = (idreg >> ARM_ID_REVISION_OFFSET) & ARM_ID_REVISION_MASK;
+
+	switch (part) {
+	case DOVECPU_PART_SHEEVA:
+		cpu = "Marvell Sheeva";
+		break;
+	default:
+		cpu = "Unknown CPU";
+	}
+
+	printf("CPU:   %s (rev %d)\n", cpu, rev);
+	return 0;
+}
+
+int dove_print_soc(void)
+{
+	char *soc, *rev;
+	u16 devid = (readl(DOVE_REG_PCIE_DEVID) >> 16) & 0xffff;
+	u8 revid = readl(DOVE_REG_PCIE_REVID) & 0xff;
+
+	switch (devid) {
+	case DOVESOC_DEVID_AP510:
+		soc = "AP510";
+		break;
+	case DOVESOC_DEVID_F6781:
+		soc = "F6781";
+		break;
+	default:
+		printf("ERROR.. %s: Unsupported SoC %04x\n", __func__, devid);
+		return -1;
+	}
+
+	switch (revid) {
+	case DOVESOC_REVID_Z0:
+		rev = "Z0";
+		break;
+	case DOVESOC_REVID_Z1:
+		rev = "Z1";
+		break;
+	case DOVESOC_REVID_Y0:
+		rev = "Y0";
+		break;
+	case DOVESOC_REVID_Y1:
+		rev = "Y1";
+		break;
+	case DOVESOC_REVID_X0:
+		rev = "X0";
+		break;
+	case DOVESOC_REVID_A0:
+		rev = "A0";
+		break;
+	case DOVESOC_REVID_A1:
+		rev = "A1";
+		break;
+	default:
+		rev = "Unknown revision";
+	};
+
+	printf("SoC:   Dove 88%s (%s)\n", soc, rev);
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	if (dove_print_soc())
+		return -1;
+	if (dove_print_cpu())
+		return -1;
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*
+ * dove_init_gpio - initial GPIO configuration
+ */
+void dove_init_gpio(struct dove_gpio_init *gpp)
+{
+	struct dovegpio_registers *gpio0reg =
+		(struct dovegpio_registers *)DOVE_GPIO0_BASE;
+	struct dovegpio_registers *gpio1reg =
+		(struct dovegpio_registers *)DOVE_GPIO1_BASE;
+	struct dovegpio_registers *gpio2reg =
+		(struct dovegpio_registers *)DOVE_GPIO2_BASE;
+
+	/* Init GPIOS to default values as per board requirement */
+	writel(gpp->val0, &gpio0reg->dout);
+	writel(gpp->val1, &gpio1reg->dout);
+	writel(gpp->val2, &gpio2reg->dout);
+	writel(gpp->oe0_n, &gpio0reg->oe);
+	writel(gpp->oe1_n, &gpio1reg->oe);
+	writel(gpp->oe2_n, &gpio2reg->oe);
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int dove_winctrl_calcsize(unsigned int sizeval)
+{
+	int i;
+	unsigned int j = 0;
+	u32 val = sizeval >> 1;
+
+	for (i = 0; val >= 0x10000; i++) {
+		j |= (1 << i);
+		val = val >> 1;
+	}
+	return 0x0000ffff & j;
+}
+
+/*
+ * dove_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Dove Soc to addess different
+ * devices. Windows 0-3 can be configured for size, BAR and remap addr.
+ * Windows 4-7 can be configured for size and BAR.
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ */
+int dove_config_adr_windows(void)
+{
+	struct dovewin_registers *winregs =
+		(struct dovewin_registers *)DOVE_CPU_WIN_BASE;
+
+	/* Window 0: 1M PCIE0 IO address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE0,
+				     DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE),
+	       &winregs[0].ctrl);
+
+	writel(DOVE_DEFADR_PCIE0_IO, &winregs[0].base);
+	writel(DOVE_DEFADR_PCIE0_IO_REMAP, &winregs[0].remap_lo);
+	writel(0x0, &winregs[0].remap_hi);
+
+	/* Window 1: 1M PCIE1 IO address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE1,
+				     DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE),
+	       &winregs[1].ctrl);
+
+	writel(DOVE_DEFADR_PCIE1_IO, &winregs[1].base);
+	writel(DOVE_DEFADR_PCIE1_IO_REMAP, &winregs[1].remap_lo);
+	writel(0x0, &winregs[1].remap_hi);
+
+	/* Window 2: 128M PCIE0 MEM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE0,
+				     DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE),
+	       &winregs[2].ctrl);
+
+	writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].base);
+	writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].remap_lo);
+	writel(0x0, &winregs[2].remap_hi);
+
+	/* Window 3: 128M PCIE1 MEM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE1,
+				     DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE),
+	       &winregs[3].ctrl);
+
+	writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].base);
+	writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].remap_lo);
+	writel(0x0, &winregs[3].remap_hi);
+
+	/* Window 4: 1M Cryptographic SRAM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_SASRAM,
+				     DOVECPU_ATTR_SASRAM, DOVECPU_WIN_ENABLE),
+	       &winregs[4].ctrl);
+	writel(DOVE_DEFADR_SASRAM, &winregs[4].base);
+
+	/* Window 5: 128M Bootrom address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_BOOTROM,
+				     DOVECPU_ATTR_BOOTROM, DOVECPU_WIN_ENABLE),
+	       &winregs[5].ctrl);
+	writel(DOVE_DEFADR_BOOTROM, &winregs[5].base);
+
+	/* Window 6: 1M PMU Scratchpad address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PMURAM,
+				     DOVECPU_ATTR_PMURAM, DOVECPU_WIN_ENABLE),
+	       &winregs[6].ctrl);
+	writel(DOVE_DEFADR_PMURAM, &winregs[6].base);
+
+	/* Window 7: Disabled */
+	writel(DOVECPU_WIN_DISABLE, &winregs[7].ctrl);
+
+	return 0;
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	dove_config_adr_windows();
+#ifdef CONFIG_USB_EHCI_MARVELL
+	dove_ehci_phy_init(0);
+	dove_ehci_phy_init(1);
+#endif /* CONFIG_USB_EHCI_MARVELL */
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Enable D-cache. I-cache is already enabled in lowlevel_init.S */
+	dcache_enable();
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+#ifdef CONFIG_MVGBE
+int cpu_eth_init(bd_t *bis)
+{
+	mvgbe_initialize(bis);
+	return 0;
+}
+#endif /* CONFIG_MVGBE */
diff --git a/arch/arm/cpu/armv7/dove/dram.c b/arch/arm/cpu/armv7/dove/dram.c
new file mode 100644
index 0000000..ce535f3
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/dram.c
@@ -0,0 +1,117 @@
+/*
+ * Marvell Dove SoC DRAM initialization
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DOVE_REG_DRAM_MAP(x)	(DOVE_REGISTER(0x800100) + (x * 0x10))
+#define DRAM_START_MASK		0xff800000
+#define DRAM_SIZE_MASK		0xf
+#define DRAM_SIZE_SHIFT		16
+
+/*
+ * dove_sdram_start - reads start from Memory Address Map Register n
+ */
+u32 dove_dram_start(enum memory_bank bank)
+{
+	u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
+	u32 enable = 0x01 & reg;
+
+	if ((!enable) || (bank > BANK1))
+		return 0;
+
+	return reg & DRAM_START_MASK;
+}
+
+/*
+ * dove_sdram_size - reads size from Memory Address Map Register n
+ */
+u32 dove_dram_size(enum memory_bank bank)
+{
+	u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
+	u32 enable = 0x01 & reg;
+	u32 size;
+
+	if ((!enable) || (bank > BANK1))
+		return 0;
+
+	/*
+	 * area_length: 7 = 8M, 8 = 16M, ..., 15 = 2048M
+	 * size = 1 << (area_length + 16)
+	 */
+	size = (reg >> DRAM_SIZE_SHIFT) & DRAM_SIZE_MASK;
+	size = 1 << (size + 16);
+	return size;
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = dove_dram_start(i);
+		gd->bd->bi_dram[i].size = dove_dram_size(i);
+
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/*
+		 * If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash
+		 */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/armv7/dove/lowlevel_init.S b/arch/arm/cpu/armv7/dove/lowlevel_init.S
new file mode 100644
index 0000000..105d12d
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/lowlevel_init.S
@@ -0,0 +1,83 @@
+/*
+ * Marvell Dove SoC icache and reg base low level init
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/dove.h>
+#include <generated/asm-offsets.h>
+#include <linux/linkage.h>
+
+/*
+ * Enable Tauros2 L2 ICache
+ */
+.macro init_l2cc
+	mrc	15, 0, r0, c1, c0, 1
+	orr	r0, r0, #0x2
+	mcr	15, 0, r0, c1, c0, 1
+.endm /* init_l2cc */
+
+/*
+ * Init internal register base addresses
+ */
+.macro init_reg_base
+	/* set SB reg base to 0xf1000000 */
+	ldr	r1, =(DOVE_PREMAP_INT_REGS_BASE_ADDR)
+	ldr	r6, =DOVE_SB_REGS_PHYS_BASE
+	str	r6, [r1]
+
+	/* set NB reg base to 0xf1800000 */
+	ldr	r1, =(DOVE_CPU_CTRL_REG)
+	ldr	r4, =0xffff0000
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	lsr	r4, r6, #16
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+	/* Set AXI bridge address mapping to 0xf1800000 */
+	ldr	r1, =(DOVE_AXI_CTRL_REG)
+	ldr	r4, =0x007fffff
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+	/* set MC configuration register decode address to 0xf1800000 */
+	ldr	r1, =(DOVE_PREMAP_MC_DECODE_REG)
+	ldr	r4, =0x0000ffff
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+.endm /* init_reg_base */
+
+.section ".text.init", "x"
+
+ENTRY(lowlevel_init)
+	init_l2cc
+	init_reg_base
+
+	/* r12 saved upper lr*/
+	mov pc,lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/dove/mpp.c b/arch/arm/cpu/armv7/dove/mpp.c
new file mode 100644
index 0000000..55311c5
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/mpp.c
@@ -0,0 +1,318 @@
+/*
+ * Marvell Dove SoC MPP pinmux
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define MPP_BITS	4
+#define MPP_MASK	0xf
+#define MPPS_PER_REG	8
+
+#define MPP_NUM(_x)	((_x) & 0xff)
+#define MPP_SEL(_x)	(((_x) >> 8) & 0x1f)
+#define MPP_GPIO(_x)	((_x) & (1 << 15))
+
+#define MPP_CTRL(i)			(DOVE_MPP_BASE + (i * MPP_BITS))
+#define MPP_PMU_GENERAL_CTRL		(DOVE_MPP_BASE + 0x010)
+#define  PMUG_AUDIO0_AC97_SEL		(1 << 16)
+#define MPP4_CTRL			(DOVE_MPP_BASE + 0x240)
+#define  MPP4_SDIO0_GPIO_SEL		(1 << 0)
+#define  MPP4_SDIO1_GPIO_SEL		(1 << 1)
+#define  MPP4_CAMERA_GPIO_SEL		(1 << 2)
+#define  MPP4_AUDIO1_GPIO_SEL		(1 << 3)
+#define  MPP4_UART1_GPIO_SEL		(1 << 4)
+#define  MPP4_SPI_GPIO_SEL		(1 << 5)
+#define MPP_GENERAL_CTRL		(DOVE_PDMA_BASE + 0x403c)
+#define  MPPG_NAND_GPIO_SEL		(1 << 0)
+#define  MPPG_AUDIO1_SPDIFO_GPIO_SEL	(1 << 1)
+#define GENERAL_CONFIG_1		(DOVE_PDMA_BASE + 0x002c)
+#define  GENERAL_TWSI_MUXEN_OPTION1	(1 << 7)
+#define GENERAL_CONFIG_2		(DOVE_PDMA_BASE + 0x0030)
+#define  GENERAL_TWSI_OPTION3_SEL	(1 << 22)
+#define  GENERAL_TWSI_MUXEN_OPTION3	(1 << 21)
+#define  GENERAL_TWSI_MUXEN_OPTION2	(1 << 20)
+#define SSP_CONFIG_STATUS_1		(DOVE_PDMA_BASE + 0x0034)
+#define  SSP_SSP_ON_AUDIO1		(1 << 0)
+
+/*
+ * MPP0-23 have standard MPP register layout
+ */
+static void dove_mpp_std_set(u16 config)
+{
+	u8 num = MPP_NUM(config);
+	u32 off = (num / MPPS_PER_REG) * MPP_BITS;
+	u32 shift = (num % MPPS_PER_REG) * MPP_BITS;
+	u32 reg;
+
+	/* configure standard MPP pin */
+	reg  = readl(MPP_CTRL(off));
+	reg &= ~(MPP_MASK << shift);
+	reg |= MPP_SEL(config) << shift;
+	writel(reg, MPP_CTRL(off));
+
+	/* configure gpio capabilities */
+	if (MPP_GPIO(config))
+		dove_gpio_set_valid(num, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+	else
+		dove_gpio_set_valid(num, 0);
+}
+
+/*
+ * MPP0-15 also allow to mux PMU functions
+ */
+static void dove_mpp_pmu_set(u16 config)
+{
+	u8 num = MPP_NUM(config);
+
+	if (MPP_SEL(config) == PMU) {
+		/* enable PMU on MPP */
+		writel(readl(MPP_PMU_GENERAL_CTRL) | (1 << num),
+		       MPP_PMU_GENERAL_CTRL);
+		/* disable gpio capabilities */
+		dove_gpio_set_valid(num, 0);
+	} else {
+		/* disable PMU on MPP */
+		writel(readl(MPP_PMU_GENERAL_CTRL) & ~(1 << num),
+		       MPP_PMU_GENERAL_CTRL);
+		/* configure MPP */
+		dove_mpp_std_set(config);
+	}
+}
+
+/*
+ * MPP groups on MPP4_CTRL have different register layout
+ * and allow GPIO or special function only
+ */
+static void dove_mpp4_set(u16 config)
+{
+	u32 reg = readl(MPP4_CTRL);
+	u32 mask;
+	u8  n, nmin, nmax;
+	int gpio;
+
+	switch (MPP_NUM(config)) {
+	case MPP_CAMERA:
+		mask = MPP4_CAMERA_GPIO_SEL;
+		nmin = MPP_CAMERA;
+		nmax = MPP_CAMERA_MAX;
+		break;
+	case MPP_SDIO0:
+		mask = MPP4_SDIO0_GPIO_SEL;
+		nmin = MPP_SDIO0;
+		nmax = MPP_SDIO0_MAX;
+		break;
+	case MPP_SDIO1:
+		mask = MPP4_SDIO1_GPIO_SEL;
+		nmin = MPP_SDIO1;
+		nmax = MPP_SDIO1_MAX;
+		break;
+	case MPP_SPI:
+		mask = MPP4_SPI_GPIO_SEL;
+		nmin = MPP_SPI;
+		nmax = MPP_SPI_MAX;
+		break;
+	case MPP_UART1:
+		mask = MPP4_UART1_GPIO_SEL;
+		nmin = MPP_UART1;
+		nmax = MPP_UART1_MAX;
+		break;
+	default:
+		return;
+	}
+
+	reg &= ~mask;
+	if (MPP_SEL(config))
+		reg |= mask;
+	writel(reg, MPP4_CTRL);
+
+	/* configure gpio capabilities */
+	gpio = 0;
+	if (MPP_GPIO(config))
+		gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+	for (n = nmin; n <= nmax; n++)
+		dove_gpio_set_valid(n, gpio);
+}
+
+/*
+ * MPP_GENERAL_CTRL allows GPIO on NAND pins
+ */
+static void dove_mpp_nand_set(u16 config)
+{
+	u32 reg = readl(MPP_GENERAL_CTRL);
+	u8 n;
+	int gpio;
+
+	reg &= ~MPPG_NAND_GPIO_SEL;
+	if (config == MPP_NAND_GPO)
+		reg |= MPPG_NAND_GPIO_SEL;
+	writel(reg, MPP_GENERAL_CTRL);
+
+	/* configure gpio capabilities */
+	gpio = (config == MPP_NAND_GPO) ? GPIO_OUTPUT_OK : 0;
+	for (n = MPP_NAND; n <= MPP_NAND_MAX; n++)
+		dove_gpio_set_valid(n, gpio);
+}
+
+/*
+ * Dedicated audio1 pins can carry i2s, spdif, ssp or twsi
+ * and gpio in various combinations
+ */
+#define AUDIO1_TWSI	(1 << 0)
+#define AUDIO1_SPDIFO	(1 << 1)
+#define AUDIO1_SSP	(1 << 2)
+#define AUDIO1_GPIO	(1 << 3)
+
+static void dove_mpp_audio1_set(u16 config)
+{
+	u32 mpp4  = readl(MPP4_CTRL);
+	u32 sspc1 = readl(SSP_CONFIG_STATUS_1);
+	u32 gmpp  = readl(MPP_GENERAL_CTRL);
+	u32 gcfg2 = readl(GENERAL_CONFIG_2);
+	u8 n, sel = MPP_SEL(config);
+	int gpio;
+
+	gcfg2 &= ~GENERAL_TWSI_OPTION3_SEL;
+	gmpp &= ~MPPG_AUDIO1_SPDIFO_GPIO_SEL;
+	sspc1 &= ~SSP_SSP_ON_AUDIO1;
+	mpp4 &= ~MPP4_AUDIO1_GPIO_SEL;
+	if (sel & AUDIO1_TWSI)
+		gcfg2 |= GENERAL_TWSI_OPTION3_SEL;
+	if (sel & AUDIO1_SPDIFO)
+		gmpp |= MPPG_AUDIO1_SPDIFO_GPIO_SEL;
+	if (sel & AUDIO1_SSP)
+		sspc1 |= SSP_SSP_ON_AUDIO1;
+	if (sel & AUDIO1_GPIO)
+		mpp4 |= MPP4_AUDIO1_GPIO_SEL;
+
+	writel(mpp4, MPP4_CTRL);
+	writel(sspc1, SSP_CONFIG_STATUS_1);
+	writel(gmpp, MPP_GENERAL_CTRL);
+	writel(gcfg2, GENERAL_CONFIG_2);
+
+	/* gpio allows gpio on all audio1 mpp pins */
+	gpio = 0;
+	if (config == MPP_AUDIO1_GPIO)
+		gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+
+	for (n = MPP_AUDIO1; n <= MPP_AUDIO1_MAX; n++)
+		dove_gpio_set_valid(n, gpio);
+
+	switch (config) {
+	/* spdifo and twsi allow gpio on mpp[52:55] */
+	case MPP_AUDIO1_SPDIFO:
+	case MPP_AUDIO1_TWSI:
+		dove_gpio_set_valid(52, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		dove_gpio_set_valid(53, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		dove_gpio_set_valid(54, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		dove_gpio_set_valid(55, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		break;
+	/* i2s and ssp allow gpio on mpp[56:57] */
+	case MPP_AUDIO1_I2S:
+	case MPP_AUDIO1_SSP:
+		dove_gpio_set_valid(56, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		dove_gpio_set_valid(57, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		break;
+	}
+}
+
+/*
+ * MPP PMU switches audio0 pins to ac97 or i2s0
+ */
+static void dove_mpp_audio0_set(u16 config)
+{
+	/* switch i2s or ac97 to audio0 */
+	u32 reg = readl(MPP_PMU_GENERAL_CTRL);
+
+	reg &= ~PMUG_AUDIO0_AC97_SEL;
+	if (config == MPP_AUDIO0_AC97)
+		reg |= PMUG_AUDIO0_AC97_SEL;
+	writel(reg, MPP_PMU_GENERAL_CTRL);
+}
+
+/*
+ * TWSI has 3 optional pin sets that can be switched during runtime
+ */
+static void dove_mpp_twsi_set(u16 config)
+{
+	u32 gcfg1 = readl(GENERAL_CONFIG_1);
+	u32 gcfg2 = readl(GENERAL_CONFIG_2);
+
+	gcfg1 &= ~GENERAL_TWSI_MUXEN_OPTION1;
+	gcfg2 &= ~(GENERAL_TWSI_MUXEN_OPTION2 | GENERAL_TWSI_MUXEN_OPTION3);
+
+	switch (config) {
+	case MPP_TWSI_OPTION1:
+		gcfg1 |= GENERAL_TWSI_MUXEN_OPTION1;
+		break;
+	case MPP_TWSI_OPTION2:
+		gcfg2 |= GENERAL_TWSI_MUXEN_OPTION2;
+		break;
+	case MPP_TWSI_OPTION3:
+		gcfg2 |= GENERAL_TWSI_MUXEN_OPTION3;
+		break;
+	}
+
+	writel(gcfg1, GENERAL_CONFIG_1);
+	writel(gcfg2, GENERAL_CONFIG_2);
+}
+
+void dove_mpp_conf(u16 *mpp_list)
+{
+	while (*mpp_list) {
+		u8 num = MPP_NUM(*mpp_list);
+
+		if (num <= MPP_PMU_MAX) {
+			dove_mpp_pmu_set(*mpp_list);
+		} else if (num <= MPP_STD_MAX) {
+			dove_mpp_std_set(*mpp_list);
+		} else {
+			switch (num) {
+			case MPP_CAMERA:
+			case MPP_SDIO0:
+			case MPP_SDIO1:
+			case MPP_SPI:
+			case MPP_UART1:
+				dove_mpp4_set(*mpp_list);
+				break;
+			case MPP_NAND:
+				dove_mpp_nand_set(*mpp_list);
+				break;
+			case MPP_AUDIO0:
+				dove_mpp_audio0_set(*mpp_list);
+				break;
+			case MPP_AUDIO1:
+				dove_mpp_audio1_set(*mpp_list);
+				break;
+			case MPP_TWSI:
+				dove_mpp_twsi_set(*mpp_list);
+				break;
+			}
+		}
+		mpp_list++;
+	}
+}
diff --git a/arch/arm/cpu/armv7/dove/timer.c b/arch/arm/cpu/armv7/dove/timer.c
new file mode 100644
index 0000000..3055369
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/timer.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Dove SoC timer
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dove.h>
+
+#define UBOOT_CNTR	0	/* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct dovetmr_val {
+	u32 reload;	/* Timer reload reg */
+	u32 val;	/* Timer value reg */
+};
+
+/* Timer registers */
+struct dovetmr_registers {
+	u32 ctrl;	/* Timer control reg */
+	u32 pad[3];
+	struct dovetmr_val tmr[2];
+	u32 wdt_reload;
+	u32 wdt_val;
+};
+
+struct dovetmr_registers *dovetmr_regs =
+	(struct dovetmr_registers *)DOVE_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG			&dovetmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum)	&dovetmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum)		&dovetmr_regs->tmr[tmrnum].val
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS		0
+#define TRG_ARM_TIMER_REL_MASK		0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS		0
+#define TVR_ARM_TIMER_MASK		0xffffffff
+#define TVR_ARM_TIMER_MAX		0xffffffff
+#define TIMER_LOAD_VAL			0xffffffff
+
+#define READ_TIMER			(readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
+					 (CONFIG_SYS_TCLK / 1000))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER;
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec +
+			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	uint current;
+	ulong delayticks;
+
+	current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
+	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+	if (current < delayticks) {
+		delayticks -= current;
+		do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current);
+		do {} while ((TIMER_LOAD_VAL - delayticks) <
+			     readl(CNTMR_VAL_REG(UBOOT_CNTR)));
+	} else {
+		do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
+			     (current - delayticks));
+	}
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+	unsigned int cntmrctrl;
+
+	/* load value into timer */
+	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+	/* enable timer in auto reload mode */
+	cntmrctrl = readl(CNTMR_CTRL_REG);
+	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+	writel(cntmrctrl, CNTMR_CTRL_REG);
+
+	/* init the timestamp and lastdec value */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/armv7/dove/usb.c b/arch/arm/cpu/armv7/dove/usb.c
new file mode 100644
index 0000000..1b932db
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/usb.c
@@ -0,0 +1,101 @@
+/*
+ * Marvell Dove SoC USB PHY init
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+
+/* Dove USB2.0 PHY registers */
+#define USB20_POWER_CTRL		((base) + 0x400)
+#define USB20_PHY_PLL_CTRL		((base) + 0x410)
+#define  PHY_PLL_VCO_RECALIBRATE	(1 << 21)
+#define USB20_PHY_TX_CTRL		((base) + 0x420)
+#define  PHY_TX_HS_STRESS_CTRL		(1 << 31)
+#define  PHY_TX_BLOCK_EN		(1 << 21)
+#define  PHY_TX_IMP_CAL_VTH(x)		(x << 14)
+#define  PHY_TX_IMP_CAL_VTH_MASK	PHY_TX_IMP_CAL_VTH(0x7)
+#define  PHY_TX_RCAL_START		(1 << 12)
+#define  PHY_TX_LOWVDD_EN		(1 << 11)
+#define USB20_PHY_RX_CTRL		((base) + 0x430)
+#define  PHY_RX_EDGE_DET(x)		(x << 26)
+#define  PHY_RX_EDGE_DET_MASK		PHY_RX_EDGE_DET(0x3)
+#define  PHY_RX_CDR_FASTLOCK_EN		(1 << 21)
+#define  PHY_RX_SQ_LENGTH(x)		(x << 15)
+#define  PHY_RX_SQ_LENGTH_MASK		PHY_RX_SQ_LENGTH(0x3)
+#define  PHY_RX_SQ_THRESH(x)		(x << 4)
+#define  PHY_RX_SQ_THRESH_MASK		PHY_RX_SQ_THRESH(0xf)
+#define  PHY_RX_LPF_COEFF(x)		(x << 2)
+#define  PHY_RX_LPF_COEFF_MASK		PHY_RX_LPF_COEFF(0x3)
+#define USB20_PHY_IVREF_CTRL		((base) + 0x440)
+#define  PHY_IVREF_TXVDD12(x)		(x << 8)
+#define  PHY_IVREF_TXVDD12_MASK		PHY_IVREF_TXVDD12(0x3)
+#define USB20_PHY_TESTGRP_CTRL		((base) + 0x450)
+#define  PHY_TESTGRP_SQ_RST		(1 << 15)
+
+void dove_ehci_phy_init(int port)
+{
+	u32 base = (port == 0) ? DOVE_USB20_0_BASE : DOVE_USB20_1_BASE;
+	u32 reg;
+
+	/* USB PHY PLL control */
+	reg = readl(USB20_PHY_PLL_CTRL);
+	writel(reg | PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
+	udelay(100);
+	writel(reg & ~PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
+
+	/* USB PHY Tx control */
+	reg = readl(USB20_PHY_TX_CTRL);
+	reg &= ~PHY_TX_IMP_CAL_VTH_MASK;
+	reg |= PHY_TX_IMP_CAL_VTH(0x5);
+	reg |= PHY_TX_LOWVDD_EN;
+	reg |= PHY_TX_RCAL_START;
+	reg |= PHY_TX_BLOCK_EN;
+	reg |= PHY_TX_HS_STRESS_CTRL;
+	writel(reg, USB20_PHY_TX_CTRL);
+	udelay(100);
+	writel(reg & ~PHY_TX_RCAL_START, USB20_PHY_TX_CTRL);
+
+	/* USB PHY RX control */
+	reg = readl(USB20_PHY_RX_CTRL);
+	reg &= ~(PHY_RX_LPF_COEFF_MASK | PHY_RX_SQ_THRESH_MASK |
+		 PHY_RX_SQ_LENGTH_MASK | PHY_RX_EDGE_DET_MASK);
+	reg |= PHY_RX_LPF_COEFF(0x1);
+	reg |= PHY_RX_SQ_THRESH(0xc);
+	reg |= PHY_RX_SQ_LENGTH(0x1);
+	reg |= PHY_RX_EDGE_DET(0x0);
+	reg &= ~PHY_RX_CDR_FASTLOCK_EN;
+	writel(reg, USB20_PHY_RX_CTRL);
+
+	/* USB PHY IVREF control */
+	reg = readl(USB20_PHY_IVREF_CTRL);
+	reg &= ~PHY_IVREF_TXVDD12_MASK;
+	reg |= PHY_IVREF_TXVDD12(0x3);
+	writel(reg, USB20_PHY_IVREF_CTRL);
+
+	/* USB PHY TEST GROUP control */
+	reg = readl(USB20_PHY_TESTGRP_CTRL);
+	reg &= ~PHY_TESTGRP_SQ_RST;
+	writel(reg, USB20_PHY_TESTGRP_CTRL);
+}
diff --git a/arch/arm/include/asm/arch-dove/config.h b/arch/arm/include/asm/arch-dove/config.h
new file mode 100644
index 0000000..3cb71b1
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/config.h
@@ -0,0 +1,153 @@
+/*
+ * Marvell SoC config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_CONFIG_H
+#define _DOVE_CONFIG_H
+
+#include <asm/arch/dove.h>
+
+#define CONFIG_ARMV7			/* Basic Architecture */
+#define CONFIG_DOVE			/* SOC Family Name */
+#define CONFIG_SHEEVA_88SV581		/* CPU Core subversion */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+				/* default Dcache Line length for Dove */
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#define CONFIG_SYS_DCACHE_OFF		/* Disable DCache by default */
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Dove has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#define CONFIG_I2C_MVTWSI_BASE	DOVE_TWSI_BASE
+#define MV_UART_CONSOLE_BASE	DOVE_UART0_BASE
+#define MV_SATA_BASE		DOVE_SATA_BASE
+#define MV_SATA_PORT0_OFFSET	DOVE_SATA_PORT0_OFFSET
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD		1
+#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL		1
+#endif
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI			1
+#define CONFIG_DOVE_SPI			1
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS		0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS		0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ		25000000
+#endif
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_PHYLIB
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SDHCI
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_SDHCI
+#define CONFIG_DOVE_SDHCI	/* Enable Dove SDHCI controller driver */
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS
+#define CONFIG_SYS_MMC_MAX_DEVICE	2
+#endif
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * IDE Support on SATA ports
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+#define CONFIG_SYS_64BIT_LBA
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#ifndef CONFIG_SOFT_I2C
+#define CONFIG_I2C_MVTWSI
+#endif
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#endif /* _DOVE_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-dove/cpu.h b/arch/arm/include/asm/arch-dove/cpu.h
new file mode 100644
index 0000000..718dd59
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/cpu.h
@@ -0,0 +1,204 @@
+/*
+ * Marvell Dove SoC CPU
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVECPU_H
+#define _DOVECPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define DOVECPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+			| (attr << 8) | (dove_winctrl_calcsize(size) << 16))
+
+#define DOVEGBE_PORT_SERIAL_CONTROL1_REG	(DOVE_EGIGA_BASE + 0x44c)
+#define DOVE_REG_PCIE_DEVID			(DOVE_REG_PCIE0_BASE + 0x00)
+#define DOVE_REG_PCIE_REVID			(DOVE_REG_PCIE0_BASE + 0x08)
+#define DOVE_REG_SYSRST_CNT			(DOVE_MPP_BASE + 0x50)
+#define SYSRST_CNT_1SEC_VAL			(25*1000000)
+#define DOVE_REG_MPP_OUT_DRV_REG		(DOVE_MPP_BASE + 0xE0)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+};
+
+enum dovecpu_winen {
+	DOVECPU_WIN_DISABLE,
+	DOVECPU_WIN_ENABLE
+};
+
+enum dovecpu_target {
+	DOVECPU_TARGET_DRAM = 0x0,
+	DOVECPU_TARGET_SASRAM = 0x3,
+	DOVECPU_TARGET_NAND = 0xc,
+	DOVECPU_TARGET_PMURAM = 0xd,
+	DOVECPU_TARGET_PCIE0 = 0x4,
+	DOVECPU_TARGET_PCIE1 = 0x8,
+	DOVECPU_TARGET_SPI = 0x1,
+	DOVECPU_TARGET_BOOTROM = 0x1,
+};
+
+enum dovecpu_attrib {
+	DOVECPU_ATTR_DRAM = 0x00,
+	DOVECPU_ATTR_SASRAM = 0x00,
+	DOVECPU_ATTR_NAND = 0x00,
+	DOVECPU_ATTR_PMURAM = 0x00,
+	DOVECPU_ATTR_PCIE_IO = 0xe0,
+	DOVECPU_ATTR_PCIE_MEM = 0xe8,
+	DOVECPU_ATTR_SPI0 = 0xfe,
+	DOVECPU_ATTR_SPI1 = 0xfb,
+	DOVECPU_ATTR_BOOTROM = 0xfd,
+};
+
+enum dovecpu_part {
+	DOVECPU_PART_SHEEVA = 0x581,
+};
+
+enum dovesoc_devid {
+	DOVESOC_DEVID_F6781 = 0x6781,
+	DOVESOC_DEVID_AP510 = 0x0510,
+};
+
+enum dovesoc_revid {
+	DOVESOC_REVID_Z0 = 0,
+	DOVESOC_REVID_Z1 = 1,
+	DOVESOC_REVID_Y0 = 2,
+	DOVESOC_REVID_Y1 = 3,
+	DOVESOC_REVID_X0 = 4,
+	DOVESOC_REVID_A0 = 6,
+	DOVESOC_REVID_A1 = 7,
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define DOVE_DEFADR_PCIE0_MEM		0xe0000000
+#define DOVE_DEFADR_PCIE0_IO		0xf2000000
+#define DOVE_DEFADR_PCIE0_IO_REMAP	0x00000000
+#define DOVE_DEFADR_PCIE1_MEM		0xe8000000
+#define DOVE_DEFADR_PCIE1_IO		0xf2100000
+#define DOVE_DEFADR_PCIE1_IO_REMAP	0x00100000
+#define DOVE_DEFADR_SASRAM		0xc8000000
+#define DOVE_DEFADR_BOOTROM		0xf8000000
+#define DOVE_DEFADR_PMURAM		0xf0000000
+
+/*
+ * ARM CPUID register
+ */
+#define ARM_ID_REVISION_OFFSET	0
+#define ARM_ID_REVISION_MASK	0xf
+#define ARM_ID_PARTNUM_OFFSET	4
+#define ARM_ID_PARTNUM_MASK	0xfff
+#define ARM_ID_ARCH_OFFSET	16
+#define ARM_ID_ARCH_MASK	0xf
+#define ARM_ID_VAR_OFFSET	20
+#define ARM_ID_VAR_MASK		0xf
+#define ARM_ID_ASCII_OFFSET	24
+#define ARM_ID_ASCII_MASK	0xff
+
+/*
+ * read feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+	unsigned int val;
+	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
+			(val) : : "cc");
+	return val;
+}
+
+/*
+ * write feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
+			(val) : "cc");
+	isb();
+}
+
+/*
+ * Downstream Bridge Registers
+ */
+struct dovewin_registers {
+	u32 ctrl;
+	u32 base;
+	u32 remap_lo;
+	u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ */
+struct dovecpu_registers {
+	u32 config;		/* 0x20100 */
+	u32 ctrl_stat;		/* 0x20104 */
+	u32 rstoutn_mask;	/* 0x20108 */
+	u32 sys_soft_rst;	/* 0x2010C */
+	u32 bridge_cause_irq;	/* 0x20110 */
+	u32 bridge_mask_irq;	/* 0x20114 */
+	u32 pad1;
+	u32 pmu_ctrl;		/* 0x2011c */
+};
+
+/*
+ * GPIO 0/1 Registers
+ * GPIO 2 Registers (no datain/irq)
+ */
+struct dovegpio_registers {
+	u32 dout;
+	u32 oe;
+	u32 blink_en;
+	u32 din_pol;
+	u32 din;
+	u32 irq_cause;
+	u32 irq_mask;
+	u32 irq_level;
+};
+
+struct dove_gpio_init {
+	u32 val0;
+	u32 val1;
+	u32 val2;
+	u32 oe0_n;
+	u32 oe1_n;
+	u32 oe2_n;
+};
+
+/*
+ * functions
+ */
+void reset_cpu(unsigned long ignored);
+unsigned char get_random_hex(void);
+u32 dove_dram_start(enum memory_bank bank);
+u32 dove_dram_size(enum memory_bank bank);
+int dove_config_adr_windows(void);
+void dove_init_gpio(struct dove_gpio_init *);
+unsigned int dove_winctrl_calcsize(unsigned int sizeval);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _DOVECPU_H */
diff --git a/arch/arm/include/asm/arch-dove/dove.h b/arch/arm/include/asm/arch-dove/dove.h
new file mode 100644
index 0000000..f310719
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/dove.h
@@ -0,0 +1,98 @@
+/*
+ * Marvell Dove SoC register offsets and config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_H
+#define _DOVE_H
+
+/* Dove TCLK is fixed to 166MHz */
+#define CONFIG_SYS_TCLK			166666667
+
+/* SOC specific definitions */
+#define DOVE_PREMAP_REGS_PHYS_BASE	0xd0000000
+#define DOVE_PREMAP_INT_REGS_BASE_ADDR  (DOVE_PREMAP_REGS_PHYS_BASE + 0x20080)
+#define DOVE_PREMAP_MC_DECODE_REG       (DOVE_PREMAP_REGS_PHYS_BASE + 0x800010)
+
+#define DOVE_SB_REGS_PHYS_BASE		0xf1000000
+#define DOVE_NB_REGS_PHYS_BASE		0xf1800000
+#define DOVE_REGISTER(x)		(DOVE_SB_REGS_PHYS_BASE + x)
+
+#define DOVE_AXI_CTRL_REG		(DOVE_REGISTER(0xd0224))
+#define DOVE_CPU_CTRL_REG		(DOVE_REGISTER(0xd025c))
+#define DOVE_MC_CTRL_REG		(DOVE_REGISTER(0xd0260))
+#define DOVE_MC_DECODE_REG		(DOVE_REGISTER(0x800010))
+
+#define DOVE_SPI_BASE			(DOVE_REGISTER(0x10600))
+#define DOVE_TWSI_BASE			(DOVE_REGISTER(0x11000))
+#define DOVE_UART0_BASE			(DOVE_REGISTER(0x12000))
+#define DOVE_UART1_BASE			(DOVE_REGISTER(0x12100))
+#define DOVE_UART2_BASE			(DOVE_REGISTER(0x12200))
+#define DOVE_UART3_BASE			(DOVE_REGISTER(0x12300))
+#define DOVE_CPU_WIN_BASE		(DOVE_REGISTER(0x20000))
+#define DOVE_CPU_REG_BASE		(DOVE_REGISTER(0x20100))
+#define DOVE_TIMER_BASE			(DOVE_REGISTER(0x20300))
+#define DOVE_REG_PCIE0_BASE		(DOVE_REGISTER(0x40000))
+#define DOVE_REG_PCIE1_BASE		(DOVE_REGISTER(0x80000))
+#define DOVE_USB20_0_BASE		(DOVE_REGISTER(0x50000))
+#define DOVE_USB20_1_BASE		(DOVE_REGISTER(0x51000))
+#define DOVE_EGIGA_BASE			(DOVE_REGISTER(0x72000))
+#define DOVE_SDIO1_BASE			(DOVE_REGISTER(0x90000))
+#define DOVE_SDIO0_BASE			(DOVE_REGISTER(0x92000))
+#define DOVE_CAMERA_BASE		(DOVE_REGISTER(0x94000))
+#define DOVE_SATA_BASE			(DOVE_REGISTER(0xa0000))
+#define DOVE_NANDF_BASE			(DOVE_REGISTER(0xc0000))
+#define DOVE_PMU_BASE			(DOVE_REGISTER(0xd0000))
+#define DOVE_MPP_BASE			(DOVE_REGISTER(0xd0200))
+#define DOVE_GPIO0_BASE			(DOVE_REGISTER(0xd0400))
+#define DOVE_GPIO1_BASE			(DOVE_REGISTER(0xd0420))
+#define DOVE_RTC_BASE			(DOVE_REGISTER(0xd8500))
+#define DOVE_AC97_BASE			(DOVE_REGISTER(0xe0000))
+#define DOVE_PDMA_BASE			(DOVE_REGISTER(0xe4000))
+#define DOVE_GPIO2_BASE			(DOVE_REGISTER(0xe8400))
+#define DOVE_SSP_BASE			(DOVE_REGISTER(0xec000))
+
+/* Dove Sata controller has one port */
+#define DOVE_SATA_PORT0_OFFSET		0x2000
+
+/* Dove GbE controller has one port */
+#define MAX_MVGBE_DEVS			1
+#define MVGBE0_BASE			DOVE_EGIGA_BASE
+
+/* Dove USB Host controller */
+#define MVUSB0_BASE			DOVE_USB20_0_BASE
+#define MVUSB0_CPU_ATTR_DRAM_CS0	DOVECPU_ATTR_DRAM
+#define MVUSB0_CPU_ATTR_DRAM_CS1	DOVECPU_ATTR_DRAM
+#define MVUSB0_CPU_ATTR_DRAM_CS2	DOVECPU_WIN_DISABLE
+#define MVUSB0_CPU_ATTR_DRAM_CS3	DOVECPU_WIN_DISABLE
+#define MVUSB1_BASE			DOVE_USB20_1_BASE
+#define MVUSB1_CPU_ATTR_DRAM_CS0	DOVECPU_ATTR_DRAM
+#define MVUSB1_CPU_ATTR_DRAM_CS1	DOVECPU_ATTR_DRAM
+#define MVUSB1_CPU_ATTR_DRAM_CS2	DOVECPU_WIN_DISABLE
+#define MVUSB1_CPU_ATTR_DRAM_CS3	DOVECPU_WIN_DISABLE
+
+/* Dove CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA		DOVECPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE		DOVECPU_WIN_ENABLE
+#define MVCPU_WIN_DISABLE		DOVECPU_WIN_DISABLE
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/gpio.h b/arch/arm/include/asm/arch-dove/gpio.h
new file mode 100644
index 0000000..363d7d2
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Marvell Dove SoC gpio
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARCH_DOVE_GPIO_H
+#define __ARCH_DOVE_GPIO_H
+
+#include <dove_gpio.h>
+
+#define GPIO_MAX		70
+#define GPIO_BASE(pin)		(((pin) >= 64) ? DOVE_GPIO2_BASE : \
+				 ((pin) >= 32) ? DOVE_GPIO1_BASE : \
+				 DOVE_GPIO0_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/mpp.h b/arch/arm/include/asm/arch-dove/mpp.h
new file mode 100644
index 0000000..1279ac2
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/mpp.h
@@ -0,0 +1,283 @@
+/*
+ * Marvell Dove SoC pinmux
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_MPP_H
+#define _DOVE_MPP_H
+
+#define DOVE_GPI	(1 << 0)
+#define DOVE_GPO	(1 << 1)
+#define DOVE_GPIO	(DOVE_GPO | DOVE_GPI)
+
+#define MPP(_num, _sel, _gpio) (			 \
+	/* MPP number */	((_num) & 0xff) |	 \
+	/* MPP select value */	(((_sel) & 0x1f) << 8) | \
+	/* is gpio config */	((!!(_gpio)) << 15))
+
+/* MPP0-15 allow PMU function */
+#define MPP_PMU_MAX		15
+#define PMU			(0x10)
+/* MPP0-23 have standard mpp register layout */
+#define MPP_STD_MAX		23
+
+#define MPP0			0
+#define MPP0_GPIO		MPP(0, 0x0, 1)
+#define MPP0_UART2_RTS		MPP(0, 0x2, 0)
+#define MPP0_SDIO0_CD		MPP(0, 0x3, 0)
+#define MPP0_LCD0_PWM		MPP(0, 0xf, 0)
+#define MPP0_PMU		MPP(0, PMU, 0)
+
+#define MPP1			1
+#define MPP1_GPIO		MPP(1, 0x0, 1)
+#define MPP1_UART2_CTS		MPP(1, 0x2, 0)
+#define MPP1_SDIO0_WP		MPP(1, 0x3, 0)
+#define MPP1_LCD1_PWM		MPP(1, 0xf, 0)
+#define MPP1_PMU		MPP(1, PMU, 0)
+
+#define MPP2			2
+#define MPP2_GPIO		MPP(2, 0x0, 1)
+#define MPP2_SATA_PRSNT		MPP(2, 0x1, 0)
+#define MPP2_UART2_TXD		MPP(2, 0x2, 0)
+#define MPP2_SDIO0_BUSPWR	MPP(2, 0x3, 0)
+#define MPP2_UART1_RTS		MPP(2, 0x4, 0)
+#define MPP2_PMU		MPP(2, PMU, 0)
+
+#define MPP3			3
+#define MPP3_GPIO		MPP(3, 0x0, 1)
+#define MPP3_SATA_ACT		MPP(3, 0x1, 0)
+#define MPP3_UART2_RXD		MPP(3, 0x2, 0)
+#define MPP3_SDIO0_LEDCTRL	MPP(3, 0x3, 0)
+#define MPP3_UART1_CTS		MPP(3, 0x4, 0)
+#define MPP3_LCD_SPI_CS1	MPP(3, 0xf, 0)
+#define MPP3_PMU		MPP(3, PMU, 0)
+
+#define MPP4			4
+#define MPP4_GPIO		MPP(4, 0x0, 1)
+#define MPP4_UART3_RTS		MPP(4, 0x2, 0)
+#define MPP4_SDIO1_CD		MPP(4, 0x3, 0)
+#define MPP4_SPI1_MISO		MPP(4, 0x4, 0)
+#define MPP4_PMU		MPP(4, PMU, 0)
+
+#define MPP5			5
+#define MPP5_GPIO		MPP(5, 0x0, 1)
+#define MPP5_UART3_CTS		MPP(5, 0x2, 0)
+#define MPP5_SDIO1_WP		MPP(5, 0x3, 0)
+#define MPP5_SPI1_CS		MPP(5, 0x4, 0)
+#define MPP5_PMU		MPP(5, PMU, 0)
+
+#define MPP6			6
+#define MPP6_GPIO		MPP(6, 0x0, 1)
+#define MPP6_UART3_TXD		MPP(6, 0x2, 0)
+#define MPP6_SDIO1_BUSPWR	MPP(6, 0x3, 0)
+#define MPP6_SPI1_MOSI		MPP(6, 0x4, 0)
+#define MPP6_PMU		MPP(6, PMU, 0)
+
+#define MPP7			7
+#define MPP7_GPIO		MPP(7, 0x0, 1)
+#define MPP7_UART3_RXD		MPP(7, 0x2, 0)
+#define MPP7_SDIO1_LEDCTRL	MPP(7, 0x3, 0)
+#define MPP7_SPI1_SCK		MPP(7, 0x4, 0)
+#define MPP7_PMU		MPP(7, PMU, 0)
+
+#define MPP8			8
+#define MPP8_GPIO		MPP(8, 0x0, 1)
+#define MPP8_WATCHDOG_RSTOUT	MPP(8, 0x1, 0)
+#define MPP8_PMU		MPP(8, PMU, 0)
+
+#define MPP9			9
+#define MPP9_GPIO		MPP(9, 0x0, 1)
+#define MPP9_PEX1_CLKREQ	MPP(9, 0x5, 0)
+#define MPP9_PMU		MPP(9, PMU, 0)
+
+#define MPP10			10
+#define MPP10_GPIO		MPP(10, 0x0, 1)
+#define MPP10_SSP_SCLK		MPP(10, 0x5, 0)
+#define MPP10_PMU		MPP(10, PMU, 0)
+
+#define MPP11			11
+#define MPP11_GPIO		MPP(11, 0x0, 1)
+#define MPP11_SATA_PRSNT	MPP(11, 0x1, 0)
+#define MPP11_SATA_ACT		MPP(11, 0x2, 0)
+#define MPP11_SDIO0_LEDCTRL	MPP(11, 0x3, 0)
+#define MPP11_SDIO1_LEDCTRL	MPP(11, 0x4, 0)
+#define MPP11_PEX0_CLKREQ	MPP(11, 0x5, 0)
+#define MPP11_PMU		MPP(11, PMU, 0)
+
+#define MPP12			12
+#define MPP12_GPIO		MPP(12, 0x0, 1)
+#define MPP12_SATA_ACT		MPP(12, 0x1, 0)
+#define MPP12_UART2_RTS		MPP(12, 0x2, 0)
+#define MPP12_AUDIO0_EXTCLK	MPP(12, 0x3, 0)
+#define MPP12_SDIO1_CD		MPP(12, 0x4, 0)
+#define MPP12_PMU		MPP(12, PMU, 0)
+
+#define MPP13			13
+#define MPP13_GPIO		MPP(13, 0x0, 1)
+#define MPP13_UART2_CTS		MPP(13, 0x2, 0)
+#define MPP13_AUDIO1_EXTCLK	MPP(13, 0x3, 0)
+#define MPP13_SDIO1_WP		MPP(13, 0x4, 0)
+#define MPP13_SSP_EXTCLK	MPP(13, 0x5, 0)
+#define MPP13_PMU		MPP(13, PMU, 0)
+
+#define MPP14			14
+#define MPP14_GPIO		MPP(14, 0x0, 1)
+#define MPP14_UART2_TXD		MPP(14, 0x2, 0)
+#define MPP14_SDIO1_BUSPWR	MPP(14, 0x4, 0)
+#define MPP14_SSP_TXD		MPP(14, 0x5, 0)
+#define MPP14_PMU		MPP(14, PMU, 0)
+
+#define MPP15			15
+#define MPP15_GPIO		MPP(15, 0x0, 1)
+#define MPP15_UART2_RXD		MPP(15, 0x2, 0)
+#define MPP15_SDIO1_LEDCTRL	MPP(15, 0x4, 0)
+#define MPP15_SSP_SFRM		MPP(15, 0x5, 0)
+#define MPP15_PMU		MPP(15, PMU, 0)
+
+#define MPP16			16
+#define MPP16_GPIO		MPP(16, 0x0, 1)
+#define MPP16_UART3_RTS		MPP(16, 0x2, 0)
+#define MPP16_SDIO0_CD		MPP(16, 0x3, 0)
+#define MPP16_LCD_SPI_CS1	MPP(16, 0x4, 0)
+#define MPP16_AC97_SDI1		MPP(16, 0x5, 0)
+
+#define MPP17			17
+#define MPP17_GPIO		MPP(17, 0x0, 1)
+#define MPP17_AC97_SYSCLKO	MPP(17, 0x1, 0)
+#define MPP17_UART3_CTS		MPP(17, 0x2, 0)
+#define MPP17_SDIO0_WP		MPP(17, 0x3, 0)
+#define MPP17_TWSI_SDA		MPP(17, 0x4, 0)
+#define MPP17_AC97_SDI2		MPP(17, 0x5, 0)
+
+#define MPP18			18
+#define MPP18_GPIO		MPP(18, 0x0, 1)
+#define MPP18_UART3_TXD		MPP(18, 0x2, 0)
+#define MPP18_SDIO0_BUSPWR	MPP(18, 0x3, 0)
+#define MPP18_LCD0_PWM		MPP(18, 0x4, 0)
+#define MPP18_AC97_SDI3		MPP(18, 0x5, 0)
+
+#define MPP19			19
+#define MPP19_GPIO		MPP(19, 0x0, 1)
+#define MPP19_UART3_RXD		MPP(19, 0x2, 0)
+#define MPP19_SDIO0_LEDCTRL	MPP(19, 0x3, 0)
+#define MPP19_TWSI_SCK		MPP(19, 0x4, 0)
+
+#define MPP20			20
+#define MPP20_GPIO		MPP(20, 0x0, 1)
+#define MPP20_AC97_SYSCLKO	MPP(20, 0x1, 0)
+#define MPP20_LCD_SPI_MISO	MPP(20, 0x2, 0)
+#define MPP20_SDIO1_CD		MPP(20, 0x3, 0)
+#define MPP20_SDIO0_CD		MPP(20, 0x5, 0)
+#define MPP20_SPI1_MISO		MPP(20, 0x6, 0)
+
+#define MPP21			21
+#define MPP21_GPIO		MPP(21, 0x0, 1)
+#define MPP21_UART1_RTS		MPP(21, 0x1, 0)
+#define MPP21_LCD_SPI_CS0	MPP(21, 0x2, 0)
+#define MPP21_SDIO1_WP		MPP(21, 0x3, 0)
+#define MPP21_SSP_SFRM		MPP(21, 0x4, 0)
+#define MPP21_SDIO0_WP		MPP(21, 0x5, 0)
+#define MPP21_SPI1_CS		MPP(21, 0x6, 0)
+
+#define MPP22			22
+#define MPP22_GPIO		MPP(22, 0x0, 1)
+#define MPP22_UART1_CTS		MPP(22, 0x1, 0)
+#define MPP22_LCD_SPI_MOSI	MPP(22, 0x2, 0)
+#define MPP22_SDIO1_BUSPWR	MPP(22, 0x3, 0)
+#define MPP22_SSP_TXD		MPP(22, 0x4, 0)
+#define MPP22_SDIO0_BUSPWR	MPP(22, 0x5, 0)
+#define MPP22_SPI1_MOSI		MPP(22, 0x6, 0)
+
+#define MPP23			23
+#define MPP23_GPIO		MPP(23, 0x0, 1)
+#define MPP23_LCD_SPI_SCK	MPP(23, 0x2, 0)
+#define MPP23_SDIO1_LEDCTRL	MPP(23, 0x3, 0)
+#define MPP23_SSP_SCLK		MPP(23, 0x4, 0)
+#define MPP23_SDIO0_LEDCTRL	MPP(23, 0x5, 0)
+#define MPP23_SPI1_SCK		MPP(23, 0x6, 0)
+
+/* MPP_CAMERA = MPP[24:39] */
+#define MPP_CAMERA		24
+#define MPP_CAMERA_CAMERA	MPP(24, 0x0, 0)
+#define MPP_CAMERA_GPIO		MPP(24, 0x1, 1)
+#define MPP_CAMERA_MAX		39
+
+/* MPP_SDIO0 = MPP[40:45] */
+#define MPP_SDIO0		40
+#define MPP_SDIO0_SDIO		MPP(40, 0x0, 0)
+#define MPP_SDIO0_GPIO		MPP(40, 0x1, 1)
+#define MPP_SDIO0_MAX		45
+
+/* MPP_SDIO1 = MPP[46:51] */
+#define MPP_SDIO1		46
+#define MPP_SDIO1_SDIO		MPP(46, 0x0, 0)
+#define MPP_SDIO1_GPIO		MPP(46, 0x1, 1)
+#define MPP_SDIO1_MAX		51
+
+/* MPP_AUDIO1 = MPP[52:57] */
+#define MPP_AUDIO1		52
+#define MPP_AUDIO1_I2S_SPDIFO	MPP(52, 0x0, 0)
+#define MPP_AUDIO1_I2S		MPP(52, 0x2, 0)
+#define MPP_AUDIO1_SPDIFO	MPP(52, 0x8, 0)
+#define MPP_AUDIO1_GPIO		MPP(52, 0xa, 1)
+#define MPP_AUDIO1_TWSI		MPP(52, 0xb, 0)
+#define MPP_AUDIO1_SSP_SPDIFO	MPP(52, 0xc, 0)
+#define MPP_AUDIO1_SSP		MPP(52, 0xe, 0)
+#define MPP_AUDIO1_SSP_TWSI	MPP(52, 0xf, 0)
+#define MPP_AUDIO1_MAX		57
+
+/* MPP_SPI = MPP[58:61] */
+#define MPP_SPI			58
+#define MPP_SPI_SPI		MPP(58, 0x0, 0)
+#define MPP_SPI_GPIO		MPP(58, 0x1, 1)
+#define MPP_SPI_MAX		61
+
+/* MPP_UART1 = MPP[62:63] */
+#define MPP_UART1		62
+#define MPP_UART1_UART1		MPP(62, 0x0, 0)
+#define MPP_UART1_GPIO		MPP(62, 0x1, 1)
+#define MPP_UART1_MAX		63
+
+/* MPP_NAND = MPP[64:71] */
+#define MPP_NAND		64
+#define MPP_NAND_NAND		MPP(64, 0x0, 0)
+#define MPP_NAND_GPO		MPP(64, 0x1, 1)
+#define MPP_NAND_MAX		71
+
+/* MPP_AUDIO0 = Internal AC97/I2S mux for audio0 pins */
+#define MPP_AUDIO0		72
+#define MPP_AUDIO0_I2S		MPP(72, 0x0, 0)
+#define MPP_AUDIO0_AC97		MPP(72, 0x1, 0)
+
+/* MPP_TWSI = Internal TWSI option mux */
+#define MPP_TWSI		73
+#define MPP_TWSI_NONE		MPP(73, 0x0, 0)
+#define MPP_TWSI_OPTION1	MPP(73, 0x1, 0)
+#define MPP_TWSI_OPTION2	MPP(73, 0x2, 0)
+#define MPP_TWSI_OPTION3	MPP(73, 0x3, 0)
+
+#define MPP_MAX			MPP_TWSI
+
+u8 dove_mpp_get_gpio_caps(u8 num);
+void dove_mpp_conf(u16 *mpp_list);
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/usb.h b/arch/arm/include/asm/arch-dove/usb.h
new file mode 100644
index 0000000..f288489
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/usb.h
@@ -0,0 +1,27 @@
+/*
+ * Marvell Dove SoC USB
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVEUSB_H
+#define _DOVEUSB_H
+
+void dove_ehci_phy_init(int port);
+#endif /* _DOVEUSB_H */
-- 
1.8.2.1

[U-Boot] [PATCH v4 02/10] usb: ehci-marvell: add support for second USB controller

[Sascha Silbe]

From: Sascha Silbe <sascha-pgp@silbe.org>

Marvell 88AP510 (Armada 510, dove) has two separate USB
controllers. Use the index parameter that already gets passed in to
calculate the base address of the controller.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v3->v4: new patch

 drivers/usb/host/ehci-marvell.c | 35 ++++++++++++++++++++++++-----------
 1 file changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 2b73e4a..d2cf026 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -28,7 +28,9 @@
 #include "ehci.h"
 #include <asm/arch/cpu.h>
 
-#if defined(CONFIG_KIRKWOOD)
+#if defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
+#elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
@@ -36,8 +38,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define rdl(off)	readl(MVUSB0_BASE + (off))
-#define wrl(off, val)	writel((val), MVUSB0_BASE + (off))
+#define rdl(base, off)		readl((base) + (off))
+#define wrl(base, off, val)	writel((val), (base) + (off))
 
 #define USB_WINDOW_CTRL(i)	(0x320 + ((i) << 4))
 #define USB_WINDOW_BASE(i)	(0x324 + ((i) << 4))
@@ -46,10 +48,15 @@ DECLARE_GLOBAL_DATA_PTR;
 /*
  * USB 2.0 Bridge Address Decoding registers setup
  */
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(int index)
 {
 	int i;
 	u32 size, base, attrib;
+#ifdef MVUSB1_BASE
+	u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
+#else
+	u32 usb_base = MVUSB0_BASE;
+#endif
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 
@@ -76,13 +83,13 @@ static void usb_brg_adrdec_setup(void)
 		size = gd->bd->bi_dram[i].size;
 		base = gd->bd->bi_dram[i].start;
 		if ((size) && (attrib))
-			wrl(USB_WINDOW_CTRL(i),
-				MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
-					attrib, MVCPU_WIN_ENABLE));
+			wrl(usb_base, USB_WINDOW_CTRL(i),
+			    MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+						attrib, MVCPU_WIN_ENABLE));
 		else
-			wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
+			wrl(usb_base, USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
 
-		wrl(USB_WINDOW_BASE(i), base);
+		wrl(usb_base, USB_WINDOW_BASE(i), base);
 	}
 }
 
@@ -92,9 +99,15 @@ static void usb_brg_adrdec_setup(void)
  */
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	usb_brg_adrdec_setup();
+#ifdef MVUSB1_BASE
+	u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
+#else
+	u32 usb_base = MVUSB0_BASE;
+#endif
 
-	*hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+	usb_brg_adrdec_setup(index);
+
+	*hccr = (struct ehci_hccr *)(usb_base + 0x100);
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr
 			+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 
-- 
1.8.2.1

[U-Boot] [PATCH v4 03/10] GPIO: add gpio driver for Dove SoCs

[Sascha Silbe]

From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

This adds a gpio driver for Marvell Dove SoCs. It is based on kw_gpio;
but as gpio capabilities depend heavily on the mpp configuration for
dove, it allows to set gpi/gpo capabilities from mpp.

While it's currently targeted at Dove SoCs only, the driver should in
large parts be compatible with orion5x and kirkwood. As a future
clean-up step, the MPP and GPIO code for the three platforms could be
merged.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v3->v4: renamed to dove_gpio, adjusted description

 drivers/gpio/Makefile    |   1 +
 drivers/gpio/dove_gpio.c | 167 +++++++++++++++++++++++++++++++++++++++++++++++
 include/dove_gpio.h      |  64 ++++++++++++++++++
 3 files changed, 232 insertions(+)
 create mode 100644 drivers/gpio/dove_gpio.c
 create mode 100644 include/dove_gpio.h

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 830e8e6..6d44bfd 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 LIB 	:= $(obj)libgpio.o
 
 COBJS-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
+COBJS-$(CONFIG_DOVE_GPIO)	+= dove_gpio.o
 COBJS-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
 COBJS-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
 COBJS-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
diff --git a/drivers/gpio/dove_gpio.c b/drivers/gpio/dove_gpio.c
new file mode 100644
index 0000000..d16e641
--- /dev/null
+++ b/drivers/gpio/dove_gpio.c
@@ -0,0 +1,167 @@
+/*
+ * Marvell Dove SoC GPIO handling.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed orion_gpiochip struct and kernel level irq handling.
+ * Dieter Kiermaier dk-arm-linux at gmx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <dove_gpio.h>
+
+static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
+static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
+
+void __set_direction(unsigned pin, int input)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_IO_CONF(base));
+	if (input)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_IO_CONF(base));
+
+	u = readl(GPIO_IO_CONF(base));
+}
+
+void __set_level(unsigned pin, int high)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_OUT(base));
+	if (high)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_OUT(base));
+}
+
+void __set_blinking(unsigned pin, int blink)
+{
+	u32 base = GPIO_BASE(pin);
+	u32 u;
+
+	u = readl(GPIO_BLINK_EN(base));
+	if (blink)
+		u |= 1 << (pin & 31);
+	else
+		u &= ~(1 << (pin & 31));
+	writel(u, GPIO_BLINK_EN(base));
+}
+
+int dove_gpio_is_valid(unsigned pin, int mode)
+{
+	if (pin < GPIO_MAX) {
+		if ((mode & GPIO_INPUT_OK) &&
+		    !test_bit(pin, gpio_valid_input))
+			goto err_out;
+
+		if ((mode & GPIO_OUTPUT_OK) &&
+		    !test_bit(pin, gpio_valid_output))
+			goto err_out;
+		return 0;
+	}
+
+err_out:
+	printf("%s: invalid GPIO %d/%d\n", __func__, pin, GPIO_MAX);
+	return 1;
+}
+
+void dove_gpio_set_valid(unsigned pin, int mode)
+{
+	if (mode & GPIO_INPUT_OK)
+		__set_bit(pin, gpio_valid_input);
+	else
+		__clear_bit(pin, gpio_valid_input);
+	if (mode & GPIO_OUTPUT_OK)
+		__set_bit(pin, gpio_valid_output);
+	else
+		__clear_bit(pin, gpio_valid_output);
+}
+
+/*
+ * GENERIC_GPIO primitives.
+ */
+int dove_gpio_direction_input(unsigned pin)
+{
+	if (dove_gpio_is_valid(pin, GPIO_INPUT_OK) != 0)
+		return 1;
+
+	/* Configure GPIO direction. */
+	__set_direction(pin, 1);
+
+	return 0;
+}
+
+int dove_gpio_direction_output(unsigned pin, int value)
+{
+	if (dove_gpio_is_valid(pin, GPIO_OUTPUT_OK) != 0) {
+		printf("%s: invalid GPIO %d\n", __func__, pin);
+		return 1;
+	}
+
+	__set_blinking(pin, 0);
+
+	/* Configure GPIO output value. */
+	__set_level(pin, value);
+
+	/* Configure GPIO direction. */
+	__set_direction(pin, 0);
+
+	return 0;
+}
+
+int dove_gpio_get_value(unsigned pin)
+{
+	u32 base = GPIO_BASE(pin);
+	int val;
+
+	if (readl(GPIO_IO_CONF(base)) & (1 << (pin & 31)))
+		val = readl(GPIO_DATA_IN(base)) ^ readl(GPIO_IN_POL(base));
+	else
+		val = readl(GPIO_OUT(base));
+
+	return (val >> (pin & 31)) & 1;
+}
+
+void dove_gpio_set_value(unsigned pin, int value)
+{
+	/* Configure GPIO output value. */
+	__set_level(pin, value);
+}
+
+void dove_gpio_set_blink(unsigned pin, int blink)
+{
+	/* Set output value to zero. */
+	__set_level(pin, 0);
+
+	/* Set blinking. */
+	__set_blinking(pin, blink);
+}
diff --git a/include/dove_gpio.h b/include/dove_gpio.h
new file mode 100644
index 0000000..ab356bc
--- /dev/null
+++ b/include/dove_gpio.h
@@ -0,0 +1,64 @@
+/*
+ * Marvell Dove SoCs common gpio
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __DOVE_GPIO_H
+#define __DOVE_GPIO_H
+
+/*
+ * SoC-specific gpio.h defines
+ * GPIO_MAX and GPIO_BASE(pin) macro
+ */
+
+#define GPIO_INPUT_OK		(1 << 0)
+#define GPIO_OUTPUT_OK		(1 << 1)
+#define GPIO_LOW		0
+#define GPIO_HIGH		1
+
+/* got from kernel include/linux/bitops.h */
+#define BITS_PER_BYTE 8
+#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+
+#define GPIO_OUT(base)		((base) + 0x00)
+#define GPIO_IO_CONF(base)	((base) + 0x04)
+#define GPIO_BLINK_EN(base)	((base) + 0x08)
+#define GPIO_IN_POL(base)	((base) + 0x0c)
+#define GPIO_DATA_IN(base)	((base) + 0x10)
+#define GPIO_EDGE_CAUSE(base)	((base) + 0x14)
+#define GPIO_EDGE_MASK(base)	((base) + 0x18)
+#define GPIO_LEVEL_MASK(base)	((base) + 0x1c)
+
+/*
+ * Dove-specific GPIO API
+ */
+
+void dove_gpio_set_valid(unsigned pin, int mode);
+int dove_gpio_is_valid(unsigned pin, int mode);
+int dove_gpio_direction_input(unsigned pin);
+int dove_gpio_direction_output(unsigned pin, int value);
+int dove_gpio_get_value(unsigned pin);
+void dove_gpio_set_value(unsigned pin, int value);
+void dove_gpio_set_blink(unsigned pin, int blink);
+void dove_gpio_set_unused(unsigned pin);
+
+#endif
-- 
1.8.2.1

[U-Boot] [PATCH v4 04/10] MMC: sdhci: Add support for dove sdhci

[Sascha Silbe]

From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

This adds a driver for the sdhci controller found on Dove SoCs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v3->v4: added header file with exported function

 arch/arm/include/asm/arch-dove/mmc.h |  27 ++++++++++
 drivers/mmc/Makefile                 |   1 +
 drivers/mmc/dove_sdhci.c             | 101 +++++++++++++++++++++++++++++++++++
 3 files changed, 129 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-dove/mmc.h
 create mode 100644 drivers/mmc/dove_sdhci.c

diff --git a/arch/arm/include/asm/arch-dove/mmc.h b/arch/arm/include/asm/arch-dove/mmc.h
new file mode 100644
index 0000000..579396c
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/mmc.h
@@ -0,0 +1,27 @@
+/*
+ * Marvell Dove SoC SDHCI
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVEMMC_H
+#define _DOVEMMC_H
+
+int dove_sdhci_init(int num);
+#endif /* _DOVEMMC_H */
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index fb6b502..cdff33d 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -31,6 +31,7 @@ endif
 
 COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+COBJS-$(CONFIG_DOVE_SDHCI) += dove_sdhci.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
 COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
diff --git a/drivers/mmc/dove_sdhci.c b/drivers/mmc/dove_sdhci.c
new file mode 100644
index 0000000..ac15fd7
--- /dev/null
+++ b/drivers/mmc/dove_sdhci.c
@@ -0,0 +1,101 @@
+/*
+ *
+ * Marvell Dove SDHCI driver
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on linux drivers/mmc/host/sdhci-dove.c
+ * by: Saeed Bishara <saeed@marvell.com>
+ *     Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/arch/dove.h>
+
+static u16 dove_sdhci_readw(struct sdhci_host *host, int reg)
+{
+	u16 ret;
+
+	switch (reg) {
+	case SDHCI_HOST_VERSION:
+	case SDHCI_SLOT_INT_STATUS:
+		/* those registers don't exist */
+		return 0;
+	default:
+		ret = readw(host->ioaddr + reg);
+	}
+
+	return ret;
+}
+
+static u32 dove_sdhci_readl(struct sdhci_host *host, int reg)
+{
+	u32 ret;
+
+	switch (reg) {
+	case SDHCI_CAPABILITIES:
+		ret = readl(host->ioaddr + reg);
+		/* Mask the support for 3.0V */
+		ret &= ~SDHCI_CAN_VDD_300;
+		break;
+	default:
+		ret = readl(host->ioaddr + reg);
+	}
+
+	return ret;
+}
+
+static struct sdhci_ops dove_sdhci_ops = {
+	.read_w	= dove_sdhci_readw,
+	.read_l	= dove_sdhci_readl,
+};
+
+static struct sdhci_host hosts[2] = {
+	{
+		.name = "Dove SDHCI0",
+		.ioaddr = (void *)DOVE_SDIO0_BASE,
+	},
+	{
+		.name = "Dove SDHCI1",
+		.ioaddr = (void *)DOVE_SDIO1_BASE,
+	},
+};
+
+int dove_sdhci_init(int num)
+{
+	struct sdhci_host *host;
+
+	if (num < 0 || num > 1)
+		return 1;
+
+	host = &hosts[num];
+
+	if (host->version)
+		return 1;
+
+	host->quirks =
+		SDHCI_QUIRK_NO_HISPD_BIT |
+		SDHCI_QUIRK_BROKEN_R1B |
+		SDHCI_QUIRK_32BIT_DMA_ADDR;
+	host->version = SDHCI_SPEC_200;
+	host->ops = &dove_sdhci_ops;
+
+	add_sdhci(host, 50000000, 4000000);
+	return 0;
+}
-- 
1.8.2.1

[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Sascha Silbe]

From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

This adds an SPI driver for Marvell Dove SoCs. This driver is taken
from kirkwood_spi but removes mpp configuration as dove has dedicated
spi pins.

As a future clean-up step, the code for orion5x, kirkwood and dove
could be merged, with MPP configuration being be handled as part of
cpu/board-specific setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v3->v4: renamed to dove, adjusted description, removed unused
         variable, made checkpatch clean

 drivers/spi/Makefile   |   1 +
 drivers/spi/dove_spi.c | 212 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 213 insertions(+)
 create mode 100644 drivers/spi/dove_spi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..62ad970 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
 COBJS-$(CONFIG_CF_SPI) += cf_spi.o
 COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
 COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_DOVE_SPI) += dove_spi.o
 COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 COBJS-$(CONFIG_ICH_SPI) +=  ich.o
 COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/dove_spi.c b/drivers/spi/dove_spi.c
new file mode 100644
index 0000000..c61ba89
--- /dev/null
+++ b/drivers/spi/dove_spi.c
@@ -0,0 +1,212 @@
+/*
+ * Marvell Dove SoCs common spi driver
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * based on kirkwood_spi.c written by
+ *  Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/arch/config.h>
+
+/* SPI Registers on dove SOC */
+struct dovespi_registers {
+	u32 ctrl;	/* 0x00 */
+	u32 cfg;	/* 0x04 */
+	u32 dout;	/* 0x08 */
+	u32 din;	/* 0x0c */
+	u32 irq_cause;	/* 0x10 */
+	u32 irq_mask;	/* 0x14 */
+};
+
+#define DOVESPI_CLKPRESCL_MASK	0x1f
+#define DOVESPI_CLKPRESCL_MIN	0x12
+#define DOVESPI_CSN_ACT	1 /* Activates serial memory interface */
+#define DOVESPI_SMEMRDY	(1 << 1) /* SerMem Data xfer ready */
+#define DOVESPI_IRQUNMASK	1 /* unmask SPI interrupt */
+#define DOVESPI_IRQMASK	0 /* mask SPI interrupt */
+#define DOVESPI_SMEMRDIRQ	1 /* SerMem data xfer ready irq */
+#define DOVESPI_XFERLEN_1BYTE	0
+#define DOVESPI_XFERLEN_2BYTE	(1 << 5)
+#define DOVESPI_XFERLEN_MASK	(1 << 5)
+#define DOVESPI_ADRLEN_1BYTE	0
+#define DOVESPI_ADRLEN_2BYTE	(1 << 8)
+#define DOVESPI_ADRLEN_3BYTE	(2 << 8)
+#define DOVESPI_ADRLEN_4BYTE	(3 << 8)
+#define DOVESPI_ADRLEN_MASK	(3 << 8)
+#define DOVESPI_TIMEOUT	10000
+
+static struct dovespi_registers *spireg =
+	(struct dovespi_registers *)DOVE_SPI_BASE;
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				unsigned int max_hz, unsigned int mode)
+{
+	struct spi_slave *slave;
+	u32 data;
+
+	if (!spi_cs_is_valid(bus, cs))
+		return NULL;
+
+	slave = malloc(sizeof(struct spi_slave));
+	if (!slave)
+		return NULL;
+
+	slave->bus = bus;
+	slave->cs = cs;
+
+	writel(~DOVESPI_CSN_ACT | DOVESPI_SMEMRDY, &spireg->ctrl);
+
+	/* calculate spi clock prescaller using max_hz */
+	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
+	data = data < DOVESPI_CLKPRESCL_MIN ? DOVESPI_CLKPRESCL_MIN : data;
+	data = data > DOVESPI_CLKPRESCL_MASK ? DOVESPI_CLKPRESCL_MASK : data;
+
+	/* program spi clock prescaller using max_hz */
+	writel(DOVESPI_ADRLEN_3BYTE | data, &spireg->cfg);
+	debug("data = 0x%08x\n", data);
+
+	writel(DOVESPI_SMEMRDIRQ, &spireg->irq_cause);
+	writel(DOVESPI_IRQMASK, &spireg->irq_mask);
+
+	return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	free(slave);
+}
+
+__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return board_spi_claim_bus(slave);
+}
+
+__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
+{
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	board_spi_release_bus(slave);
+}
+
+#ifndef CONFIG_SPI_CS_IS_VALID
+/*
+ * you can define this function board specific
+ * define above CONFIG in board specific config file and
+ * provide the function in board specific src file
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return (bus == 0 && (cs == 0 || cs == 1));
+}
+#endif
+
+void spi_init(void)
+{
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	writel(readl(&spireg->ctrl) | DOVESPI_IRQUNMASK, &spireg->ctrl);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	writel(readl(&spireg->ctrl) & DOVESPI_IRQMASK, &spireg->ctrl);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	unsigned int tmpdout, tmpdin;
+	int tm, isread = 0;
+
+	debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
+	      slave->bus, slave->cs, dout, din, bitlen);
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	/*
+	 * handle data in 8-bit chunks
+	 * TBD: 2byte xfer mode to be enabled
+	 */
+	writel(((readl(&spireg->cfg) & ~DOVESPI_XFERLEN_MASK) |
+		DOVESPI_XFERLEN_1BYTE), &spireg->cfg);
+
+	while (bitlen > 4) {
+		debug("loopstart bitlen %d\n", bitlen);
+		tmpdout = 0;
+
+		/* Shift data so it's msb-justified */
+		if (dout)
+			tmpdout = *(u32 *)dout & 0x0ff;
+
+		writel(~DOVESPI_SMEMRDIRQ, &spireg->irq_cause);
+		writel(tmpdout, &spireg->dout);	/* Write the data out */
+		debug("*** spi_xfer: ... %08x written, bitlen %d\n",
+		      tmpdout, bitlen);
+
+		/*
+		 * Wait for SPI transmit to get out
+		 * or time out (1 second = 1000 ms)
+		 * The NE event must be read and cleared first
+		 */
+		for (tm = 0, isread = 0; tm < DOVESPI_TIMEOUT; ++tm) {
+			if (readl(&spireg->irq_cause) & DOVESPI_SMEMRDIRQ) {
+				isread = 1;
+				tmpdin = readl(&spireg->din);
+				debug
+					("spi_xfer: din %p..%08x read\n",
+					din, tmpdin);
+
+				if (din) {
+					*((u8 *)din) = (u8)tmpdin;
+					din += 1;
+				}
+				if (dout)
+					dout += 1;
+				bitlen -= 8;
+			}
+			if (isread)
+				break;
+		}
+		if (tm >= DOVESPI_TIMEOUT)
+			printf("*** spi_xfer: Time out during SPI transfer\n");
+
+		debug("loopend bitlen %d\n", bitlen);
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	return 0;
+}
-- 
1.8.2.1

[U-Boot] [PATCH v4 06/10] block: mvsata: add dove include

[Sascha Silbe]

From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Dove SoC also uses mvsata, therefore add a SoC specific include to
allow to reuse the mvsata ide driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
---
 drivers/block/mvsata_ide.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index 42c177f..500f13c 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -29,6 +29,8 @@
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 /* SATA port registers */
-- 
1.8.2.1

[U-Boot] [PATCH v4 07/10] NET: phy: add 88E1310 PHY initialization

[Sascha Silbe]

From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

This adds PHY initialization for Marvell Alaska 88E1310 PHY.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
 drivers/net/phy/marvell.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 4b27198..1205166 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -89,6 +89,12 @@
 
 #define MIIM_88E1149_PHY_PAGE	29
 
+/* 88E1310 PHY defines */
+#define MIIM_88E1310_PHY_LED_CTRL	16
+#define MIIM_88E1310_PHY_IRQ_EN		18
+#define MIIM_88E1310_PHY_RGMII_CTRL	21
+#define MIIM_88E1310_PHY_PAGE		22
+
 /* Marvell 88E1011S */
 static int m88e1011s_config(struct phy_device *phydev)
 {
@@ -394,6 +400,37 @@ static int m88e1149_config(struct phy_device *phydev)
 	return 0;
 }
 
+/* Marvell 88E1310 */
+static int m88e1310_config(struct phy_device *phydev)
+{
+	u16 reg;
+
+	/* LED link and activity */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
+	reg = (reg & ~0xf) | 0x1;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
+
+	/* Set LED2/INT to INT mode, low active */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
+	reg = (reg & 0x77ff) | 0x0880;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
+
+	/* Set RGMII delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
+	reg |= 0x0030;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
+
+	/* Ensure to return to page 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
+
+	genphy_config_aneg(phydev);
+	phy_reset(phydev);
+
+	return 0;
+}
 
 static struct phy_driver M88E1011S_driver = {
 	.name = "Marvell 88E1011S",
@@ -465,8 +502,19 @@ static struct phy_driver M88E1149S_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver M88E1310_driver = {
+	.name = "Marvell 88E1310",
+	.uid = 0x01410e90,
+	.mask = 0xffffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &m88e1310_config,
+	.startup = &m88e1011s_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 int phy_marvell_init(void)
 {
+	phy_register(&M88E1310_driver);
 	phy_register(&M88E1149S_driver);
 	phy_register(&M88E1145_driver);
 	phy_register(&M88E1121R_driver);
-- 
1.8.2.1

[U-Boot] [PATCH v4 08/10] NET: mvgbe: add phylib support

[Sascha Silbe]

From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

This add phylib support to the Marvell GBE driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v3->v4: avoided unused variable warning; made checkpatch clean

 drivers/net/mvgbe.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 68 insertions(+), 6 deletions(-)

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 47bf27c..7f0ddf5 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MV_PHY_ADR_REQUEST 0xee
 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 /*
  * smi_reg_read - miiphy_read callback function.
  *
@@ -184,6 +184,25 @@ static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
 }
 #endif
 
+#if defined(CONFIG_PHYLIB)
+int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
+	int reg_addr)
+{
+	u16 data;
+	int ret;
+	ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data);
+	if (ret)
+		return ret;
+	return data;
+}
+
+int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
+	int reg_addr, u16 data)
+{
+	return smi_reg_write(bus->name, phy_addr, reg_addr, data);
+}
+#endif
+
 /* Stop and checks all queues */
 static void stop_queue(u32 * qreg)
 {
@@ -415,8 +434,9 @@ static int mvgbe_init(struct eth_device *dev)
 {
 	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 	struct mvgbe_registers *regs = dmvgbe->regs;
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
-	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) &&  \
+	!defined(CONFIG_PHYLIB) &&			 \
+	defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 	int i;
 #endif
 	/* setup RX rings */
@@ -467,8 +487,9 @@ static int mvgbe_init(struct eth_device *dev)
 	/* Enable port Rx. */
 	MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
 
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
-	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) &&  \
+	!defined(CONFIG_PHYLIB) &&			 \
+	defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 	/* Wait up to 5s for the link status */
 	for (i = 0; i < 5; i++) {
 		u16 phyadr;
@@ -647,6 +668,45 @@ static int mvgbe_recv(struct eth_device *dev)
 	return 0;
 }
 
+#if defined(CONFIG_PHYLIB)
+int mvgbe_phylib_init(struct eth_device *dev, int phyid)
+{
+	struct mii_dev *bus;
+	struct phy_device *phydev;
+	int ret;
+
+	bus = mdio_alloc();
+	if (!bus) {
+		printf("mdio_alloc failed\n");
+		return -ENOMEM;
+	}
+	bus->read = mvgbe_phy_read;
+	bus->write = mvgbe_phy_write;
+	sprintf(bus->name, dev->name);
+
+	ret = mdio_register(bus);
+	if (ret) {
+		printf("mdio_register failed\n");
+		free(bus);
+		return -ENOMEM;
+	}
+
+	/* Set phy address of the port */
+	mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
+
+	phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		printf("phy_connect failed\n");
+		return -ENODEV;
+	}
+
+	phy_config(phydev);
+	phy_startup(phydev);
+
+	return 0;
+}
+#endif
+
 int mvgbe_initialize(bd_t *bis)
 {
 	struct mvgbe_device *dmvgbe;
@@ -729,7 +789,9 @@ error1:
 
 		eth_register(dev);
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_PHYLIB)
+		mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
+#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 		miiphy_register(dev->name, smi_reg_read, smi_reg_write);
 		/* Set phy address of the port */
 		miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
-- 
1.8.2.1

[U-Boot] [PATCH v4 09/10] NET: mvgbe: add support for Dove

[Sascha Silbe]

From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v3->v4: removed EBAR_DRAM_CS* for Dove

 drivers/net/mvgbe.c | 9 ++++++++-
 drivers/net/mvgbe.h | 2 ++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 7f0ddf5..57692e3 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -43,6 +43,8 @@
 #include <asm/arch/kirkwood.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 #include "mvgbe.h"
@@ -286,7 +288,11 @@ static void set_dram_access(struct mvgbe_registers *regs)
 		else
 			win_param.enable = 1;	/* Enable the access */
 
-		/* Enable DRAM bank */
+#ifdef CONFIG_DOVE
+		/* Choose DRAM as target */
+		win_param.attrib = 0;
+#else
+		/* Choose one DRAM bank (chip select line) as target */
 		switch (i) {
 		case 0:
 			win_param.attrib = EBAR_DRAM_CS0;
@@ -306,6 +312,7 @@ static void set_dram_access(struct mvgbe_registers *regs)
 			win_param.attrib = 0;
 			break;
 		}
+#endif
 		/* Set the access control for address window(EPAPR) RD/WR */
 		set_access_control(regs, &win_param);
 	}
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index d8a5429..22b571e 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -308,10 +308,12 @@
 #define EBAR_TARGET_GUNIT			0x00000007
 
 /* Window attrib */
+#if !defined(CONFIG_DOVE)
 #define EBAR_DRAM_CS0				0x00000E00
 #define EBAR_DRAM_CS1				0x00000D00
 #define EBAR_DRAM_CS2				0x00000B00
 #define EBAR_DRAM_CS3				0x00000700
+#endif
 
 /* DRAM Target interface */
 #define EBAR_DRAM_NO_CACHE_COHERENCY		0x00000000
-- 
1.8.2.1

[U-Boot] [PATCH v4 10/10] Boards: Add support for SolidRun CuBox

[Sascha Silbe]

From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

With latest support for Marvell Dove SoC, add the SolidRun CuBox as
the very first board with that SoC.

Three variants are provided:

1. A regular SPI boot image for CuBox (1GiB)

   The CuBox (without "Pro") has 1GiB of memory.

2. A regular SPI boot image for CuBox Pro (2GiB)

   The CuBox Pro has 2GiB of memory. Because larger SDRAM chips are
   used, tRFC needs to be longer than on the 1GiB variant.

3. A UART boot image for both CuBox and CuBox Pro

   This is just for recovery purposes, so the smaller memory map (on
   CuBox Pro) and slower SDRAM access (on CuBox) doesn't
   matter. Having a single image that works on both hardware variants
   is quite convenient during recovery.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>

---
 v3->v4: added second USB port; added 2GiB and UART variants; removed
         hardcoded MAC address; fixed some typos; made checkpatch
         clean

 Tested on CuBox Pro (SPI and UART boot).

 MAINTAINERS                               |   4 +
 board/solidrun/cubox/Makefile             |  45 ++++++++
 board/solidrun/cubox/cubox.c              | 142 +++++++++++++++++++++++
 board/solidrun/cubox/kwbimage-spi-1gb.cfg |  76 ++++++++++++
 board/solidrun/cubox/kwbimage-spi-2gb.cfg |  76 ++++++++++++
 board/solidrun/cubox/kwbimage-uart.cfg    |  76 ++++++++++++
 boards.cfg                                |   3 +
 include/configs/cubox.h                   | 185 ++++++++++++++++++++++++++++++
 8 files changed, 607 insertions(+)
 create mode 100644 board/solidrun/cubox/Makefile
 create mode 100644 board/solidrun/cubox/cubox.c
 create mode 100644 board/solidrun/cubox/kwbimage-spi-1gb.cfg
 create mode 100644 board/solidrun/cubox/kwbimage-spi-2gb.cfg
 create mode 100644 board/solidrun/cubox/kwbimage-uart.cfg
 create mode 100644 include/configs/cubox.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 643a5ac..07faf39 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -693,6 +693,10 @@ Lauri Hintsala <lauri.hintsala@bluegiga.com>
 
 	apx4devkit	i.MX28
 
+Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+
+	cubox		ARM ARMV7 (Dove SoC)
+
 Vaibhav Hiremath <hvaibhav@ti.com>
 
 	am3517_evm	ARM ARMV7 (AM35x SoC)
diff --git a/board/solidrun/cubox/Makefile b/board/solidrun/cubox/Makefile
new file mode 100644
index 0000000..c771d72
--- /dev/null
+++ b/board/solidrun/cubox/Makefile
@@ -0,0 +1,45 @@
+#
+# SolidRun CuBox Makefile
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cubox.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/solidrun/cubox/cubox.c b/board/solidrun/cubox/cubox.c
new file mode 100644
index 0000000..3d8140d
--- /dev/null
+++ b/board/solidrun/cubox/cubox.c
@@ -0,0 +1,142 @@
+/*
+ * SolidRun CuBox board support
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/mmc.h>
+#include <dove_gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u16 mpp_config[] = {
+	MPP0_GPIO,
+	MPP1_GPIO, /* USB power enable */
+	MPP2_GPIO, /* USB over-current indication */
+	MPP3_GPIO, /* micro button beneath eSATA port */
+	MPP4_GPIO,
+	MPP5_GPIO,
+	MPP6_GPIO,
+	MPP7_GPIO,
+
+	MPP8_GPIO,
+	MPP9_GPIO,
+	MPP10_GPIO,
+	MPP11_GPIO,
+	MPP12_GPIO, /* SDIO0 card detect */
+	MPP13_AUDIO1_EXTCLK, /* Si5351a audio clock output */
+	MPP14_GPIO,
+	MPP15_GPIO,
+
+	MPP16_GPIO,
+	MPP17_GPIO,
+	MPP18_GPIO, /* Red front LED */
+	MPP19_UART3_RXD, /* IR sensor */
+	MPP20_GPIO,
+	MPP21_GPIO,
+	MPP22_GPIO,
+	MPP23_GPIO,
+
+	MPP_CAMERA_GPIO,
+	MPP_SDIO0_SDIO, /* SDIO0 */
+	MPP_SDIO1_GPIO,
+	MPP_AUDIO1_I2S_SPDIFO, /* SPDIF and HDMI audio */
+	MPP_SPI_SPI, /* SPI */
+	MPP_UART1_GPIO,
+	MPP_NAND_GPO,
+
+	MPP_AUDIO0_I2S,
+	MPP_TWSI_OPTION1, /* TWSI on dedicated pins */
+	0 };
+
+int board_early_init_f(void)
+{
+	struct dove_gpio_init gpp = {
+		.val0  = 0x00010186,
+		.oe0_n = 0xffffffff,
+		.val1  = 0x018000c0,
+		.oe1_n = 0xffffffff,
+		.val2  = 0x00000000,
+		.oe2_n = 0xffffffff,
+	};
+
+	dove_init_gpio(&gpp);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = dove_dram_start(0) + 0x100;
+
+	/* configure mpp */
+	dove_mpp_conf(mpp_config);
+
+	/* usb power enable */
+	dove_gpio_direction_output(MPP1, GPIO_HIGH);
+
+	/* blink led */
+	dove_gpio_direction_output(MPP18, GPIO_HIGH);
+	dove_gpio_set_blink(MPP18, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_MMC
+int board_mmc_init(bd_t *bis)
+{
+	dove_sdhci_init(0);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_RESET_PHY_R
+void dove_eth_phy_init(char *name)
+{
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+		       __func__);
+		return;
+	}
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("%s PHY initialized\n", name);
+}
+
+void reset_phy(void)
+{
+	dove_eth_phy_init("egiga0");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/solidrun/cubox/kwbimage-spi-1gb.cfg b/board/solidrun/cubox/kwbimage-spi-1gb.cfg
new file mode 100644
index 0000000..c3f1ad9
--- /dev/null
+++ b/board/solidrun/cubox/kwbimage-spi-1gb.cfg
@@ -0,0 +1,76 @@
+#
+# Marvell BootROM config for SolidRun CuBox
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# SDRAM initalization
+DATA 0xd0800020 0x00022430	# SDRAM Configuration register 0
+DATA 0xd0800030 0x00022430	# SDRAM Configuration register 1
+DATA 0xd0800050 0x911500c3	# SDRAM Timing register 1
+DATA 0xd0800060 0x646602c4	# SDRAM Timing register 2
+DATA 0xd0800190 0xc2003053	# SDRAM Timing register 3
+DATA 0xd08001c0 0x34f4a187	# SDRAM Timing register 4
+DATA 0xd0800650 0x000f0121	# SDRAM Timing register 5
+DATA 0xd0800660 0x04040200	# SDRAM Timing register 6
+DATA 0xd0800080 0x00000000	# SDRAM Control register 1
+DATA 0xd0800090 0x00080000	# SDRAM Control register 2
+DATA 0xd08000f0 0xc0000000	# SDRAM Control register 3
+DATA 0xd08001a0 0x20c0c009	# SDRAM Control register 4
+DATA 0xd0800280 0x010e0202	# SDRAM Control register 5
+DATA 0xd0800760 0x00000000	# SDRAM Control register 6
+DATA 0xd0800770 0x0000000a	# SDRAM Control register 7
+DATA 0xd0800140 0x20004044	# SDRAM PHY control register 3
+DATA 0xd08001d0 0x133c2339	# SDRAM PHY control register 7
+DATA 0xd08001e0 0x07700330	# SDRAM PHY control register 8
+DATA 0xd08001f0 0x00000033	# SDRAM PHY control register 9
+DATA 0xd0800200 0x0011311c	# SDRAM PHY control register 10
+DATA 0xd0800210 0x00300000	# SDRAM PHY control register 11
+DATA 0xd0800240 0x80000000	# SDRAM PHY control register 14
+DATA 0xd0800510 0x010e0101	# SDRAM MCB control register 1
+DATA 0xd0800230 0x2028006a	# SDRAM PHY control register 13
+DATA 0xd0800e10 0x00280062	# SDRAM PHY DLL control registers 2
+DATA 0xd0800e20 0x00280062	# SDRAM PHY DLL control registers 3
+DATA 0xd0800e30 0x00280062	# SDRAM PHY DLL control registers 4
+
+# SDRAM memory map (2x512MB)
+DATA 0xd0800100 0x000d0001	# SDRAM Memory Address Map register 1
+DATA 0xd0800110 0x200d0001	# SDRAM Memory Address Map register 1
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/solidrun/cubox/kwbimage-spi-2gb.cfg b/board/solidrun/cubox/kwbimage-spi-2gb.cfg
new file mode 100644
index 0000000..7113c66
--- /dev/null
+++ b/board/solidrun/cubox/kwbimage-spi-2gb.cfg
@@ -0,0 +1,76 @@
+#
+# Marvell BootROM config for SolidRun CuBox
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# SDRAM initalization
+DATA 0xd0800020 0x00022530	# SDRAM Configuration register 0
+DATA 0xd0800030 0x00022530	# SDRAM Configuration register 1
+DATA 0xd0800050 0x911500c3	# SDRAM Timing register 1
+DATA 0xd0800060 0x64660784	# SDRAM Timing register 2
+DATA 0xd0800190 0xc2003053	# SDRAM Timing register 3
+DATA 0xd08001c0 0x34f4a187	# SDRAM Timing register 4
+DATA 0xd0800650 0x000f0121	# SDRAM Timing register 5
+DATA 0xd0800660 0x04040200	# SDRAM Timing register 6
+DATA 0xd0800080 0x00000000	# SDRAM Control register 1
+DATA 0xd0800090 0x00080000	# SDRAM Control register 2
+DATA 0xd08000f0 0xc0000000	# SDRAM Control register 3
+DATA 0xd08001a0 0x20c0c009	# SDRAM Control register 4
+DATA 0xd0800280 0x010e0202	# SDRAM Control register 5
+DATA 0xd0800760 0x00000000	# SDRAM Control register 6
+DATA 0xd0800770 0x0000000a	# SDRAM Control register 7
+DATA 0xd0800140 0x20004044	# SDRAM PHY control register 3
+DATA 0xd08001d0 0x133c2339	# SDRAM PHY control register 7
+DATA 0xd08001e0 0x07700330	# SDRAM PHY control register 8
+DATA 0xd08001f0 0x00000033	# SDRAM PHY control register 9
+DATA 0xd0800200 0x0011311c	# SDRAM PHY control register 10
+DATA 0xd0800210 0x00300000	# SDRAM PHY control register 11
+DATA 0xd0800240 0x80000000	# SDRAM PHY control register 14
+DATA 0xd0800510 0x010e0101	# SDRAM MCB control register 1
+DATA 0xd0800230 0x2028006a	# SDRAM PHY control register 13
+DATA 0xd0800e10 0x00280062	# SDRAM PHY DLL control registers 2
+DATA 0xd0800e20 0x00280062	# SDRAM PHY DLL control registers 3
+DATA 0xd0800e30 0x00280062	# SDRAM PHY DLL control registers 4
+
+# SDRAM memory map (2x1GiB)
+DATA 0xd0800100 0x000e0001	# SDRAM Memory Address Map register 1
+DATA 0xd0800110 0x400e0001	# SDRAM Memory Address Map register 1
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/solidrun/cubox/kwbimage-uart.cfg b/board/solidrun/cubox/kwbimage-uart.cfg
new file mode 100644
index 0000000..0077615
--- /dev/null
+++ b/board/solidrun/cubox/kwbimage-uart.cfg
@@ -0,0 +1,76 @@
+#
+# Marvell BootROM config for SolidRun CuBox
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more deta+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	uart
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# SDRAM initalization
+DATA 0xd0800020 0x00022430	# SDRAM Configuration register 0
+DATA 0xd0800030 0x00022430	# SDRAM Configuration register 1
+DATA 0xd0800050 0x911500c3	# SDRAM Timing register 1
+DATA 0xd0800060 0x64660784	# SDRAM Timing register 2
+DATA 0xd0800190 0xc2003053	# SDRAM Timing register 3
+DATA 0xd08001c0 0x34f4a187	# SDRAM Timing register 4
+DATA 0xd0800650 0x000f0121	# SDRAM Timing register 5
+DATA 0xd0800660 0x04040200	# SDRAM Timing register 6
+DATA 0xd0800080 0x00000000	# SDRAM Control register 1
+DATA 0xd0800090 0x00080000	# SDRAM Control register 2
+DATA 0xd08000f0 0xc0000000	# SDRAM Control register 3
+DATA 0xd08001a0 0x20c0c009	# SDRAM Control register 4
+DATA 0xd0800280 0x010e0202	# SDRAM Control register 5
+DATA 0xd0800760 0x00000000	# SDRAM Control register 6
+DATA 0xd0800770 0x0000000a	# SDRAM Control register 7
+DATA 0xd0800140 0x20004044	# SDRAM PHY control register 3
+DATA 0xd08001d0 0x133c2339	# SDRAM PHY control register 7
+DATA 0xd08001e0 0x07700330	# SDRAM PHY control register 8
+DATA 0xd08001f0 0x00000033	# SDRAM PHY control register 9
+DATA 0xd0800200 0x0011311c	# SDRAM PHY control register 10
+DATA 0xd0800210 0x00300000	# SDRAM PHY control register 11
+DATA 0xd0800240 0x80000000	# SDRAM PHY control register 14
+DATA 0xd0800510 0x010e0101	# SDRAM MCB control register 1
+DATA 0xd0800230 0x2028006a	# SDRAM PHY control register 13
+DATA 0xd0800e10 0x00280062	# SDRAM PHY DLL control registers 2
+DATA 0xd0800e20 0x00280062	# SDRAM PHY DLL control registers 3
+DATA 0xd0800e30 0x00280062	# SDRAM PHY DLL control registers 4
+
+# SDRAM memory map (2x512MB)
+DATA 0xd0800100 0x000d0001	# SDRAM Memory Address Map register 1
+DATA 0xd0800110 0x200d0001	# SDRAM Memory Address Map register 1
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/boards.cfg b/boards.cfg
index 5d78064..425b5c5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -316,6 +316,9 @@ dalmore                      arm         armv7:arm720t dalmore           nvidia
 colibri_t20_iris             arm         armv7:arm720t colibri_t20_iris  toradex        tegra20
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
 snowball                     arm         armv7       snowball               st-ericsson    u8500
+cubox                        arm         armv7       cubox               solidrun       dove        cubox:CUBOX_1GB
+cubox_pro                    arm         armv7       cubox               solidrun       dove        cubox:CUBOX_2GB
+cubox_uart                   arm         armv7       cubox               solidrun       dove        cubox:CUBOX_UART_BOOT
 kzm9g                        arm         armv7       kzm9g               kmc            rmobile
 armadillo-800eva             arm         armv7       armadillo-800eva    atmark-techno  rmobile
 zynq                         arm         armv7       zynq                xilinx         zynq
diff --git a/include/configs/cubox.h b/include/configs/cubox.h
new file mode 100644
index 0000000..ab94cc5
--- /dev/null
+++ b/include/configs/cubox.h
@@ -0,0 +1,185 @@
+/*
+ * SolidRun CuBox config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_CUBOX_H
+#define _CONFIG_CUBOX_H
+#include <asm/sizes.h>
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"SolidRun CuBox"
+
+#undef CONFIG_SYS_KWD_CONFIG
+#if defined(CONFIG_CUBOX_UART_BOOT)
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-uart.cfg
+#elif defined(CONFIG_CUBOX_1GB)
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-spi-1gb.cfg
+#elif defined(CONFIG_CUBOX_2GB)
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-spi-2gb.cfg
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MACH_SOLIDRUN_CUBOX	/* Machine type */
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_DOVE_GPIO
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable u-boot API for standalone programs.
+ */
+#define CONFIG_API
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Commands configuration
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * redefine mv-common.h macros for armv7/cubox
+ */
+#undef CONFIG_SYS_PROMPT	/* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT	"CuBox> "	/* Command Prompt */
+
+/* There is no arch_misc_init on armv7 */
+#undef CONFIG_ARCH_MISC_INIT
+
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN	(4 * 1024 * 1024) /* 4MiB for malloc() */
+
+/*
+ *  Environment variables configurations
+ */
+#if defined(CONFIG_CMD_SF)
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SECT_SIZE		0x1000	/* 4k */
+#define CONFIG_ENV_SIZE			0x20000 /* 128k */
+#define CONFIG_ENV_OFFSET		0xc0000 /* env starts here */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+
+/*
+ * Default CuBox bootscript environment
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootscript=boot.scr\0"						\
+	"loadaddr=0x02000000\0"						\
+	"mmc_started=0\0"						\
+	"ide_started=0\0"						\
+	"usb_started=0\0"						\
+	"mtdparts=mtdparts=spi0.0:768k(u-boot)ro,128k(uboot_env),128k(fdt),-(empty)\0"
+
+#define CONFIG_BOOTCOMMAND						\
+	"for devn in usb mmc ide ; do "					\
+	"  for part in 0 1; do "					\
+	"    for dir  in / /boot/;do "					\
+	"      for fs in ext2 fat; do "					\
+	"        echo ===> Executing ${fs}load ${devn} 0:${part} ${loadaddr} ${dir}${bootscript};" \
+	"        if itest.s $devn -eq mmc; then"			\
+	"          if itest.s $mmc_started -ne 1; then"			\
+	"            mmcinfo; setenv mmc_started '1';fi;fi;"		\
+	"        if itest.s $devn -eq usb; then"			\
+	"          if itest.s $usb_started -ne 1; then"			\
+	"            usb start; setenv usb_started '1';fi;fi;"		\
+	"        if itest.s $devn -eq ide; then"			\
+	"          if itest.s $ide_started -ne 1; then"			\
+	"            ide reset; setenv ide_started '1';fi;fi;"		\
+	"        if ${fs}load ${devn} 0:${part} ${loadaddr} ${dir}${bootscript}; then" \
+	"          source ${loadaddr}; fi;"				\
+	"        if itest.s $devn -eq usb; then"			\
+	"          echo ===> Executing ${fs}load ${devn} 1:${part} ${loadaddr} ${dir}${bootscript};" \
+	"          if ${fs}load ${devn} 1:${part} ${loadaddr} ${dir}${bootscript}; then" \
+	"            source ${loadaddr}; fi;"				\
+	"        fi;"							\
+	"      done;"							\
+	"    done;"							\
+	"  done;"							\
+	"done;"								\
+	"tftp ${loadaddr} ${bootscript};"				\
+	"source ${loadaddr};"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1}	/* enable port 0 */
+#define CONFIG_PHY_BASE_ADR	1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
+#endif /* CONFIG_CMD_NET */
+
+#ifdef CONFIG_CMD_IDE
+#undef CONFIG_IDE_LED
+#undef CONFIG_SYS_IDE_MAXBUS
+#define CONFIG_SYS_IDE_MAXBUS		1
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_CUBOX_H */
-- 
1.8.2.1

[U-Boot] [PATCH v4 08/10] NET: mvgbe: add phylib support

[Prafulla Wadaskar]

> -----Original Message-----
> From: u-boot-bounces at lists.denx.de [mailto:u-boot-
> bounces at lists.denx.de] On Behalf Of Sascha Silbe
> Sent: 27 May 2013 00:07
> To: u-boot at lists.denx.de
> Cc: Rabeeh Khoury; Luka Perkov; Daniel Stodden; Andy
> Fleming
> Subject: [U-Boot] [PATCH v4 08/10] NET: mvgbe: add
> phylib support
> 
> From: Sebastian Hesselbarth
> <sebastian.hesselbarth@gmail.com>
> 
> This add phylib support to the Marvell GBE driver.
> 
> Signed-off-by: Sebastian Hesselbarth
> <sebastian.hesselbarth@gmail.com>
> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
> ---
>  v3->v4: avoided unused variable warning; made
> checkpatch clean
> 
>  drivers/net/mvgbe.c | 74
> ++++++++++++++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 68 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
> index 47bf27c..7f0ddf5 100644
> --- a/drivers/net/mvgbe.c
> +++ b/drivers/net/mvgbe.c
> @@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define MV_PHY_ADR_REQUEST 0xee
>  #define MVGBE_SMI_REG (((struct mvgbe_registers
> *)MVGBE0_BASE)->smi)
> 
> -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
> +#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) ||
> defined(CONFIG_CMD_MII)
>  /*
>   * smi_reg_read - miiphy_read callback function.
>   *
> @@ -184,6 +184,25 @@ static int smi_reg_write(const
> char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
>  }
>  #endif
> 
> +#if defined(CONFIG_PHYLIB)
> +int mvgbe_phy_read(struct mii_dev *bus, int phy_addr,
> int dev_addr,
> +	int reg_addr)
> +{
> +	u16 data;
> +	int ret;
> +	ret = smi_reg_read(bus->name, phy_addr, reg_addr,
> &data);
> +	if (ret)
> +		return ret;
> +	return data;
> +}
> +
> +int mvgbe_phy_write(struct mii_dev *bus, int phy_addr,
> int dev_addr,
> +	int reg_addr, u16 data)
> +{
> +	return smi_reg_write(bus->name, phy_addr, reg_addr,
> data);
> +}
> +#endif
> +
>  /* Stop and checks all queues */
>  static void stop_queue(u32 * qreg)
>  {
> @@ -415,8 +434,9 @@ static int mvgbe_init(struct
> eth_device *dev)
>  {
>  	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
>  	struct mvgbe_registers *regs = dmvgbe->regs;
> -#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII))
> \
> -	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
> +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
> &&  \
> +	!defined(CONFIG_PHYLIB) &&			 \
> +	defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
>  	int i;
>  #endif
>  	/* setup RX rings */
> @@ -467,8 +487,9 @@ static int mvgbe_init(struct
> eth_device *dev)
>  	/* Enable port Rx. */
>  	MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
> 
> -#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII))
> \
> -	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
> +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
> &&  \
> +	!defined(CONFIG_PHYLIB) &&			 \
> +	defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
>  	/* Wait up to 5s for the link status */
>  	for (i = 0; i < 5; i++) {
>  		u16 phyadr;
> @@ -647,6 +668,45 @@ static int mvgbe_recv(struct
> eth_device *dev)
>  	return 0;
>  }
> 
> +#if defined(CONFIG_PHYLIB)
> +int mvgbe_phylib_init(struct eth_device *dev, int
> phyid)
> +{
> +	struct mii_dev *bus;
> +	struct phy_device *phydev;
> +	int ret;
> +
> +	bus = mdio_alloc();
> +	if (!bus) {
> +		printf("mdio_alloc failed\n");
> +		return -ENOMEM;
> +	}
> +	bus->read = mvgbe_phy_read;
> +	bus->write = mvgbe_phy_write;
> +	sprintf(bus->name, dev->name);
> +
> +	ret = mdio_register(bus);
> +	if (ret) {
> +		printf("mdio_register failed\n");
> +		free(bus);
> +		return -ENOMEM;
> +	}
> +
> +	/* Set phy address of the port */
> +	mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0,
> MV_PHY_ADR_REQUEST, phyid);
> +
> +	phydev = phy_connect(bus, phyid, dev,
> PHY_INTERFACE_MODE_RGMII);
> +	if (!phydev) {
> +		printf("phy_connect failed\n");
> +		return -ENODEV;
> +	}
> +
> +	phy_config(phydev);
> +	phy_startup(phydev);
> +
> +	return 0;
> +}
> +#endif
> +
>  int mvgbe_initialize(bd_t *bis)
>  {
>  	struct mvgbe_device *dmvgbe;
> @@ -729,7 +789,9 @@ error1:
> 
>  		eth_register(dev);
> 
> -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
> +#if defined(CONFIG_PHYLIB)
> +		mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
> +#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
>  		miiphy_register(dev->name, smi_reg_read,
> smi_reg_write);
>  		/* Set phy address of the port */
>  		miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
> --
> 1.8.2.1

Acked-by: Prafulla Wadaskar <prafulla@marvell.com>

Regards...
Prafulla . . .

[U-Boot] [PATCH v3 04/10] SPI: Add Orion SPI driver

[Jagan Teki]

Hi,

Does this tested on hw, please re-base the tree and send the next version patch.
Let me know if it ok to review under current tree.

--
Thanks,
Jagan.

On Mon, Feb 11, 2013 at 9:09 AM, Prafulla Wadaskar <prafulla@marvell.com> wrote:
>
>
>> -----Original Message-----
>> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
>> Sent: 17 January 2013 00:55
>> To: Sebastian Hesselbarth
>> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
>> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
>> Subject: [PATCH v3 04/10] SPI: Add Orion SPI driver
>>
>> This adds an SPI driver found on Marvell Orion SoCs. This driver is
>> taken from kirkwood_spi but removes mpp configuration as dove has
>> dedicated spi pins. To have a common driver for orion5x, kirkwood,
>> and dove, mpp configuration should be handled in some cpu/board-
>> specific
>
> the proposal of having common driver will be greatly appreciated.
> Pls go ahead and do it if possible for you
>
> I think adding orion_spi.c to enable dove support doesn't sound good.
>
> Regards...
> Prafulla . . .
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 04/10] SPI: Add Orion SPI driver

[Sascha Silbe]

Dear Jagan,

Jagan Teki <jagannadh.teki@gmail.com> writes:

> Does this tested on hw, please re-base the tree and send the next version patch.
> Let me know if it ok to review under current tree.

I'd appreciate a review of the latest patch [1,2]. There have been no
changes in master to the files touched by the patch since I sent
it. After rebasing the entire series on today's master (d6639d1) I've
successfully verified SPI flash functionality on CuBox Pro.

Sascha

[1] mid:1369593423-19763-6-git-send-email-t-uboot at infra-silbe.de
[2] http://patchwork.ozlabs.org/patch/246468/
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[U-Boot] [PATCH v3 04/10] SPI: Add Orion SPI driver

[Jagan Teki]

On Mon, Jun 3, 2013 at 11:01 PM, Sascha Silbe <t-uboot@infra-silbe.de> wrote:
> Dear Jagan,
>
> Jagan Teki <jagannadh.teki@gmail.com> writes:
>
>> Does this tested on hw, please re-base the tree and send the next version patch.
>> Let me know if it ok to review under current tree.
>
> I'd appreciate a review of the latest patch [1,2]. There have been no
> changes in master to the files touched by the patch since I sent
> it. After rebasing the entire series on today's master (d6639d1) I've
> successfully verified SPI flash functionality on CuBox Pro.
>
> Sascha
>
> [1] mid:1369593423-19763-6-git-send-email-t-uboot at infra-silbe.de
> [2] http://patchwork.ozlabs.org/patch/246468/

Thank you, means this v4 is the latest one?
http://patchwork.ozlabs.org/patch/246468/

--
Thanks,
Jagan.

[U-Boot] [PATCH v3 04/10] SPI: Add Orion SPI driver

[Sascha Silbe]

Dear Jagan,

Jagan Teki <jagannadh.teki@gmail.com> writes:

>> I'd appreciate a review of the latest patch [1,2]. [...]
>> [1] mid:1369593423-19763-6-git-send-email-t-uboot at infra-silbe.de
>> [2] http://patchwork.ozlabs.org/patch/246468/
>
> Thank you, means this v4 is the latest one?
> http://patchwork.ozlabs.org/patch/246468/

Yes, it is.

Sascha
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[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Jagan Teki]

Hi,

Looks ok to me as per coding style after a quick look.

On Mon, May 27, 2013 at 12:06 AM, Sascha Silbe <t-uboot@infra-silbe.de> wrote:
> From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>
> This adds an SPI driver for Marvell Dove SoCs. This driver is taken
> from kirkwood_spi but removes mpp configuration as dove has dedicated
> spi pins.
>
> As a future clean-up step, the code for orion5x, kirkwood and dove
> could be merged, with MPP configuration being be handled as part of
> cpu/board-specific setup.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
> ---
>  v3->v4: renamed to dove, adjusted description, removed unused
>          variable, made checkpatch clean
>
>  drivers/spi/Makefile   |   1 +
>  drivers/spi/dove_spi.c | 212 +++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 213 insertions(+)
>  create mode 100644 drivers/spi/dove_spi.c
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index d08609e..62ad970 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
>  COBJS-$(CONFIG_CF_SPI) += cf_spi.o
>  COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
>  COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
> +COBJS-$(CONFIG_DOVE_SPI) += dove_spi.o
>  COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
>  COBJS-$(CONFIG_ICH_SPI) +=  ich.o
>  COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
> diff --git a/drivers/spi/dove_spi.c b/drivers/spi/dove_spi.c
> new file mode 100644
> index 0000000..c61ba89
> --- /dev/null
> +++ b/drivers/spi/dove_spi.c
> @@ -0,0 +1,212 @@
> +/*
> + * Marvell Dove SoCs common spi driver
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + * based on kirkwood_spi.c written by
> + *  Prafulla Wadaskar <prafulla@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <spi.h>
> +#include <asm/io.h>
> +#include <asm/arch/config.h>
> +
> +/* SPI Registers on dove SOC */
> +struct dovespi_registers {
> +       u32 ctrl;       /* 0x00 */
> +       u32 cfg;        /* 0x04 */
> +       u32 dout;       /* 0x08 */
> +       u32 din;        /* 0x0c */
> +       u32 irq_cause;  /* 0x10 */
> +       u32 irq_mask;   /* 0x14 */
> +};
> +
> +#define DOVESPI_CLKPRESCL_MASK 0x1f
> +#define DOVESPI_CLKPRESCL_MIN  0x12
> +#define DOVESPI_CSN_ACT        1 /* Activates serial memory interface */
> +#define DOVESPI_SMEMRDY        (1 << 1) /* SerMem Data xfer ready */
> +#define DOVESPI_IRQUNMASK      1 /* unmask SPI interrupt */
> +#define DOVESPI_IRQMASK        0 /* mask SPI interrupt */
> +#define DOVESPI_SMEMRDIRQ      1 /* SerMem data xfer ready irq */
> +#define DOVESPI_XFERLEN_1BYTE  0
> +#define DOVESPI_XFERLEN_2BYTE  (1 << 5)
> +#define DOVESPI_XFERLEN_MASK   (1 << 5)
> +#define DOVESPI_ADRLEN_1BYTE   0
> +#define DOVESPI_ADRLEN_2BYTE   (1 << 8)
> +#define DOVESPI_ADRLEN_3BYTE   (2 << 8)
> +#define DOVESPI_ADRLEN_4BYTE   (3 << 8)
> +#define DOVESPI_ADRLEN_MASK    (3 << 8)
> +#define DOVESPI_TIMEOUT        10000
> +
> +static struct dovespi_registers *spireg =
> +       (struct dovespi_registers *)DOVE_SPI_BASE;
> +
> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> +                               unsigned int max_hz, unsigned int mode)
> +{
> +       struct spi_slave *slave;
> +       u32 data;
> +
> +       if (!spi_cs_is_valid(bus, cs))
> +               return NULL;
> +

Done use the below tag code instead go for spi_alloc_slave()
see the sample code on "drivers/spi/exynos_spi.c"

----------------------- TAG+
> +       slave = malloc(sizeof(struct spi_slave));
> +       if (!slave)
> +               return NULL;
> +
> +       slave->bus = bus;
> +       slave->cs = cs;
> +
--------------------- TAG-

> +       writel(~DOVESPI_CSN_ACT | DOVESPI_SMEMRDY, &spireg->ctrl);
> +
> +       /* calculate spi clock prescaller using max_hz */
> +       data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
> +       data = data < DOVESPI_CLKPRESCL_MIN ? DOVESPI_CLKPRESCL_MIN : data;
> +       data = data > DOVESPI_CLKPRESCL_MASK ? DOVESPI_CLKPRESCL_MASK : data;
> +
> +       /* program spi clock prescaller using max_hz */
> +       writel(DOVESPI_ADRLEN_3BYTE | data, &spireg->cfg);
> +       debug("data = 0x%08x\n", data);
> +
> +       writel(DOVESPI_SMEMRDIRQ, &spireg->irq_cause);
> +       writel(DOVESPI_IRQMASK, &spireg->irq_mask);
> +
> +       return slave;
> +}
> +
> +void spi_free_slave(struct spi_slave *slave)
> +{
> +       free(slave);
> +}
> +
> +__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)

Why your using __attribute__((weak)) here, may be use to pre-load the
symbol library
but what is the use case here?

--
Thanks,
Jagan.

[U-Boot] [PATCH v3 04/10] SPI: Add Orion SPI driver

[Sebastian Hesselbarth]

On 06/03/2013 07:31 PM, Sascha Silbe wrote:
> From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>
> This adds an SPI driver for Marvell Dove SoCs. This driver is taken
> from kirkwood_spi but removes mpp configuration as dove has dedicated
> spi pins.
>
> As a future clean-up step, the code for orion5x, kirkwood and dove
> could be merged, with MPP configuration being be handled as part of
> cpu/board-specific setup.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
> ---
>  v3->v4: renamed to dove, adjusted description, removed unused
>          variable, made checkpatch clean

Sascha,

renaming it to dove_spi to obfuscate it is actually a copy of
kirkwood_spi that will also work for orion5x and mv78x00 does _not_
match my intention when I posted this driver. Feel free to pick up the
patches but it should remain generic for all Orion SoCs.

kirkwood_spi has mpp stuff inside that is totally wrong there, move it
to board setup and just rename kirkwood_spi to something more generic.

Sebastian

[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Jagan Teki]

Hi,

On 03-06-2013 23:50, Jagan Teki wrote:
> Hi,
>
> Looks ok to me as per coding style after a quick look.
>
> On Mon, May 27, 2013 at 12:06 AM, Sascha Silbe <t-uboot@infra-silbe.de> wrote:
>> From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>>
>> This adds an SPI driver for Marvell Dove SoCs. This driver is taken
>> from kirkwood_spi but removes mpp configuration as dove has dedicated
>> spi pins.
>>
>> As a future clean-up step, the code for orion5x, kirkwood and dove
>> could be merged, with MPP configuration being be handled as part of
>> cpu/board-specific setup.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
>> ---
>>   v3->v4: renamed to dove, adjusted description, removed unused
>>           variable, made checkpatch clean
>>
>>   drivers/spi/Makefile   |   1 +
>>   drivers/spi/dove_spi.c | 212 +++++++++++++++++++++++++++++++++++++++++++++++++
>>   2 files changed, 213 insertions(+)
>>   create mode 100644 drivers/spi/dove_spi.c
>>
>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>> index d08609e..62ad970 100644
>> --- a/drivers/spi/Makefile
>> +++ b/drivers/spi/Makefile
>> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
>>   COBJS-$(CONFIG_CF_SPI) += cf_spi.o
>>   COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
>>   COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
>> +COBJS-$(CONFIG_DOVE_SPI) += dove_spi.o
>>   COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
>>   COBJS-$(CONFIG_ICH_SPI) +=  ich.o
>>   COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
>> diff --git a/drivers/spi/dove_spi.c b/drivers/spi/dove_spi.c
>> new file mode 100644
>> index 0000000..c61ba89
>> --- /dev/null
>> +++ b/drivers/spi/dove_spi.c
>> @@ -0,0 +1,212 @@
>> +/*
>> + * Marvell Dove SoCs common spi driver
>> + *
>> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> + * based on kirkwood_spi.c written by
>> + *  Prafulla Wadaskar <prafulla@marvell.com>
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>> + */
>> +
>> +#include <common.h>
>> +#include <malloc.h>
>> +#include <spi.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/config.h>
>> +
>> +/* SPI Registers on dove SOC */
>> +struct dovespi_registers {
>> +       u32 ctrl;       /* 0x00 */
>> +       u32 cfg;        /* 0x04 */
>> +       u32 dout;       /* 0x08 */
>> +       u32 din;        /* 0x0c */
>> +       u32 irq_cause;  /* 0x10 */
>> +       u32 irq_mask;   /* 0x14 */
>> +};
>> +
>> +#define DOVESPI_CLKPRESCL_MASK 0x1f
>> +#define DOVESPI_CLKPRESCL_MIN  0x12
>> +#define DOVESPI_CSN_ACT        1 /* Activates serial memory interface */
>> +#define DOVESPI_SMEMRDY        (1 << 1) /* SerMem Data xfer ready */
>> +#define DOVESPI_IRQUNMASK      1 /* unmask SPI interrupt */
>> +#define DOVESPI_IRQMASK        0 /* mask SPI interrupt */
>> +#define DOVESPI_SMEMRDIRQ      1 /* SerMem data xfer ready irq */
>> +#define DOVESPI_XFERLEN_1BYTE  0
>> +#define DOVESPI_XFERLEN_2BYTE  (1 << 5)
>> +#define DOVESPI_XFERLEN_MASK   (1 << 5)
>> +#define DOVESPI_ADRLEN_1BYTE   0
>> +#define DOVESPI_ADRLEN_2BYTE   (1 << 8)
>> +#define DOVESPI_ADRLEN_3BYTE   (2 << 8)
>> +#define DOVESPI_ADRLEN_4BYTE   (3 << 8)
>> +#define DOVESPI_ADRLEN_MASK    (3 << 8)
>> +#define DOVESPI_TIMEOUT        10000
>> +
>> +static struct dovespi_registers *spireg =
>> +       (struct dovespi_registers *)DOVE_SPI_BASE;
>> +
>> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
>> +                               unsigned int max_hz, unsigned int mode)
>> +{
>> +       struct spi_slave *slave;
>> +       u32 data;
>> +
>> +       if (!spi_cs_is_valid(bus, cs))
>> +               return NULL;
>> +
>
> Done use the below tag code instead go for spi_alloc_slave()
> see the sample code on "drivers/spi/exynos_spi.c"
>
> ----------------------- TAG+
>> +       slave = malloc(sizeof(struct spi_slave));
>> +       if (!slave)
>> +               return NULL;
>> +
>> +       slave->bus = bus;
>> +       slave->cs = cs;
>> +
> --------------------- TAG-
>
>> +       writel(~DOVESPI_CSN_ACT | DOVESPI_SMEMRDY, &spireg->ctrl);
>> +
>> +       /* calculate spi clock prescaller using max_hz */
>> +       data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
>> +       data = data < DOVESPI_CLKPRESCL_MIN ? DOVESPI_CLKPRESCL_MIN : data;
>> +       data = data > DOVESPI_CLKPRESCL_MASK ? DOVESPI_CLKPRESCL_MASK : data;
>> +
>> +       /* program spi clock prescaller using max_hz */
>> +       writel(DOVESPI_ADRLEN_3BYTE | data, &spireg->cfg);
>> +       debug("data = 0x%08x\n", data);
>> +
>> +       writel(DOVESPI_SMEMRDIRQ, &spireg->irq_cause);
>> +       writel(DOVESPI_IRQMASK, &spireg->irq_mask);
>> +
>> +       return slave;
>> +}
>> +
>> +void spi_free_slave(struct spi_slave *slave)
>> +{
>> +       free(slave);
>> +}
>> +
>> +__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
>
> Why your using __attribute__((weak)) here, may be use to pre-load the
> symbol library
> but what is the use case here?
>
> --
> Thanks,
> Jagan.
>
Any update on this.

Thanks,
Jagan.

[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Sebastian Hesselbarth]

On 06/12/2013 08:58 PM, Jagan Teki wrote:
> On 03-06-2013 23:50, Jagan Teki wrote:
>> Looks ok to me as per coding style after a quick look.
>> On Mon, May 27, 2013 at 12:06 AM, Sascha Silbe
>> <t-uboot@infra-silbe.de> wrote:
>>> From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>>>
>>> This adds an SPI driver for Marvell Dove SoCs. This driver is taken
>>> from kirkwood_spi but removes mpp configuration as dove has dedicated
>>> spi pins.
>>>
>>> As a future clean-up step, the code for orion5x, kirkwood and dove
>>> could be merged, with MPP configuration being be handled as part of
>>> cpu/board-specific setup.
>>>
>>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>>> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
>>> ---
>>> v3->v4: renamed to dove, adjusted description, removed unused
>>> variable, made checkpatch clean
[...]
> Any update on this.

Is any of you even listening? Please do _not_ name it after Dove! It is
compatible with _at least_ Kirkwood, Orion5x and MV78x00. Now is the
chance to have a common name or you will end up with either non-sense
naming or four copies of that very driver.

Originally, it was named after the Linux group of SoCs compatible with
Dove (orion-spi), IIRC Prafulla suggested mv-spi.

Sebastian

[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Jagan Teki]

On Thu, Jun 13, 2013 at 12:56 AM, Sebastian Hesselbarth
<sebastian.hesselbarth@gmail.com> wrote:
> On 06/12/2013 08:58 PM, Jagan Teki wrote:
>>
>> On 03-06-2013 23:50, Jagan Teki wrote:
>>>
>>> Looks ok to me as per coding style after a quick look.
>>> On Mon, May 27, 2013 at 12:06 AM, Sascha Silbe
>>> <t-uboot@infra-silbe.de> wrote:
>>>>
>>>> From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>>>>
>>>> This adds an SPI driver for Marvell Dove SoCs. This driver is taken
>>>> from kirkwood_spi but removes mpp configuration as dove has dedicated
>>>> spi pins.
>>>>
>>>> As a future clean-up step, the code for orion5x, kirkwood and dove
>>>> could be merged, with MPP configuration being be handled as part of
>>>> cpu/board-specific setup.
>>>>
>>>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>>>> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
>>>> ---
>>>> v3->v4: renamed to dove, adjusted description, removed unused
>>>> variable, made checkpatch clean
>
> [...]
>>
>> Any update on this.
>
>
> Is any of you even listening? Please do _not_ name it after Dove! It is
> compatible with _at least_ Kirkwood, Orion5x and MV78x00. Now is the
> chance to have a common name or you will end up with either non-sense
> naming or four copies of that very driver.
>
> Originally, it was named after the Linux group of SoCs compatible with
> Dove (orion-spi), IIRC Prafulla suggested mv-spi.
>
> Sebastian

Common to use means orion_spi instead of Dove?

--
Thanks,
Jagan.

[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Sebastian Hesselbarth]

On 06/12/2013 09:30 PM, Jagan Teki wrote:
> On Thu, Jun 13, 2013 at 12:56 AM, Sebastian Hesselbarth
> <sebastian.hesselbarth@gmail.com>  wrote:
>> Is any of you even listening? Please do _not_ name it after Dove! It is
>> compatible with _at least_ Kirkwood, Orion5x and MV78x00. Now is the
>> chance to have a common name or you will end up with either non-sense
>> naming or four copies of that very driver.
>>
>> Originally, it was named after the Linux group of SoCs compatible with
>> Dove (orion-spi), IIRC Prafulla suggested mv-spi.
>
> Common to use means orion_spi instead of Dove?

Either orion_spi as it was named originally, or mv_spi as Prafulla
suggested. Then move mpp (pinctrl) from kirkwood_spi to corresponding
boards, switch to orion_/mv_spi, and remove kirkwood_spi.

I suggest orion_spi, but Prafulla had his word so it should be mv_spi
I guess.

Sebastian

[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Sascha Silbe]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> Either orion_spi as it was named originally, or mv_spi as Prafulla
> suggested. Then move mpp (pinctrl) from kirkwood_spi to corresponding
> boards, switch to orion_/mv_spi, and remove kirkwood_spi.
>
> I suggest orion_spi, but Prafulla had his word so it should be mv_spi
> I guess.

I've given it a try and modified the Kirkwood GPIO and SPI drivers
rather than duplicating their code. As I neither know the Dove SoCs nor
have any hardware using them, I don't feel comfortable merging this with
any existing orion code. For similar reasons and also for a lack of time
I've left the MPP support code in place, just protected with
CONFIG_KIRKWOOD.

As for the naming: there's already a GPIO driver called mvgpio that
looks quite different from the Kirkwood / Dove one. Naming the latter
one mv_gpio would work for the build tools, but needlessly cause
confusion to developers. Therefore I chose to keep the current names of
the Kirkwood drivers (kw_gpio, kirkwood_spi). If anyone has a better
suggestion, I'm happy to change the names.

Sebastian, does the resulting code still match your intentions or would
you like me to remove your Signed-off-by from those two patches when
posting the updated patch series?

Sascha
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[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Sebastian Hesselbarth]

On 06/25/2013 09:33 PM, Sascha Silbe wrote:
> Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>  writes:
>> Either orion_spi as it was named originally, or mv_spi as Prafulla
>> suggested. Then move mpp (pinctrl) from kirkwood_spi to corresponding
>> boards, switch to orion_/mv_spi, and remove kirkwood_spi.
>>
>> I suggest orion_spi, but Prafulla had his word so it should be mv_spi
>> I guess.
>
> I've given it a try and modified the Kirkwood GPIO and SPI drivers
> rather than duplicating their code. As I neither know the Dove SoCs nor
> have any hardware using them, I don't feel comfortable merging this with
> any existing orion code. For similar reasons and also for a lack of time
> I've left the MPP support code in place, just protected with
> CONFIG_KIRKWOOD.

Sascha,

I was under the impression that you resent the patches because you have
a CuBox you want to get supported. Anyway, I will not get back to
u-boot Dove support anytime soon. It just takes to long to get any
valuable review/ack from Marvell maintainer.

> As for the naming: there's already a GPIO driver called mvgpio that
> looks quite different from the Kirkwood / Dove one. Naming the latter
> one mv_gpio would work for the build tools, but needlessly cause
> confusion to developers. Therefore I chose to keep the current names of
> the Kirkwood drivers (kw_gpio, kirkwood_spi). If anyone has a better
> suggestion, I'm happy to change the names.

Naming was the main discussion of this patch set back then, there have
been some "???" on the mpp stuff. I suggested  several times not to use
"mv" as I knew that Marvell PXA also uses "mv" as prefix all over.

The PXA SPI controller is based on different IP. Unfortunately PXA
naming is not consitent over SoCs, Dove is also nick-named PXA510
sometimes.

Actually, we are merging Orion SoCs and Armada 370/XP to mach-mvebu -
so the best name would be mvebu_spi as the spi controller is also in
Armada 370/XP.

But Prafulla is u-boot Marvell maintainer, he said to use mv prefix -
not my call anymore.

> Sebastian, does the resulting code still match your intentions or would
> you like me to remove your Signed-off-by from those two patches when
> posting the updated patch series?

Uhm, did you forget to send code?

I will not likely get back to Dove support on u-boot. I cannot really
re-test on Kirkwood and it just takes to long to get feedback.
I suggest to remove my Signed-off-by and especially the MAINTAINERS
entry.

Sebastian

[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Sascha Silbe]

Hello Jagan,

Jagan Teki <jagannadh.teki@gmail.com> writes:

> Looks ok to me as per coding style after a quick look.

Thanks for the review.


[...]
> Done use the below tag code instead go for spi_alloc_slave()
> see the sample code on "drivers/spi/exynos_spi.c"
>
> ----------------------- TAG+
>> +       slave = malloc(sizeof(struct spi_slave));
>> +       if (!slave)
>> +               return NULL;
>> +
>> +       slave->bus = bus;
>> +       slave->cs = cs;
>> +
> --------------------- TAG-

That's going to be fixed in the next version which builds directly on
kirkwood_spi (rather than duplicating it), which already uses
spi_alloc_slave().


>> +__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
>
> Why your using __attribute__((weak)) here, may be use to pre-load the
> symbol library
> but what is the use case here?

That's coming from kirkwood_spi. The Keymile boards apparently use it to
select between NAND and SPI flash (see board/keymile/km_arm/km_arm.c).

Sascha
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[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Sascha Silbe]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

[...]
> I was under the impression that you resent the patches because you have
> a CuBox you want to get supported.

Exactly. I'd like to see support for CuBox enter mainline
U-Boot. However, there's also a limit to the amount of time I can afford
to spend on it (both per week and in total). TBH, I would have hoped the
_vendor_ (SolidRun) would take a more active role in this. For that
reason I'm now going to evaluate a Wandboard Quad, where more effort
seems to get spent on upstreaming (not to mention that the schematics
are available, which makes working on board support a lot easier). When
I ordered the CuBox Pro, the then-existing Wandboard variants (Solo and
DualLite) lacked SATA support, but the Quad meets my requirements.


> Naming was the main discussion of this patch set back then, there have
> been some "???" on the mpp stuff. I suggested  several times not to use
> "mv" as I knew that Marvell PXA also uses "mv" as prefix all over.
>
> The PXA SPI controller is based on different IP. Unfortunately PXA
> naming is not consitent over SoCs, Dove is also nick-named PXA510
> sometimes.
>
> Actually, we are merging Orion SoCs and Armada 370/XP to mach-mvebu -
> so the best name would be mvebu_spi as the spi controller is also in
> Armada 370/XP.

You're confusing me even more than I already was. :)

It's probably best to leave this reorganisation to someone else who
better knows the relationships between the several SoC families from
Marvell.


[...]
> Uhm, did you forget to send code?

No, I was holding back until I knew whether you still feel comfortable
being associated with the patches. I'll send them out now.


> I will not likely get back to Dove support on u-boot. I cannot really
> re-test on Kirkwood and it just takes to long to get feedback.
> I suggest to remove my Signed-off-by and especially the MAINTAINERS
> entry.

OK, will do. Sorry you feel that way.

Sascha
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[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver

[Sebastian Hesselbarth]

On 06/25/2013 10:38 PM, Sascha Silbe wrote:
> Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>  writes:
> [...]
>> I was under the impression that you resent the patches because you have
>> a CuBox you want to get supported.
>
> Exactly. I'd like to see support for CuBox enter mainline
> U-Boot. However, there's also a limit to the amount of time I can afford
> to spend on it (both per week and in total). TBH, I would have hoped the
> _vendor_ (SolidRun) would take a more active role in this. For that
> reason I'm now going to evaluate a Wandboard Quad, where more effort
> seems to get spent on upstreaming (not to mention that the schematics
> are available, which makes working on board support a lot easier). When
> I ordered the CuBox Pro, the then-existing Wandboard variants (Solo and
> DualLite) lacked SATA support, but the Quad meets my requirements.

 From what I know, Rabeeh would love to add support for CuBox to u-boot.
But I guess his spare time is very limited, too.

>> Naming was the main discussion of this patch set back then, there have
>> been some "???" on the mpp stuff. I suggested  several times not to use
>> "mv" as I knew that Marvell PXA also uses "mv" as prefix all over.
>>
>> The PXA SPI controller is based on different IP. Unfortunately PXA
>> naming is not consitent over SoCs, Dove is also nick-named PXA510
>> sometimes.
>>
>> Actually, we are merging Orion SoCs and Armada 370/XP to mach-mvebu -
>> so the best name would be mvebu_spi as the spi controller is also in
>> Armada 370/XP.
>
> You're confusing me even more than I already was. :)
>
> It's probably best to leave this reorganisation to someone else who
> better knows the relationships between the several SoC families from
> Marvell.

Linux has some good overview of the non-PXA Marvell SoCs. Naming is
a mess and IP is reused often. But from what I can say, Orion matches
Dove, Kirkwood, Orion5x, and Discovery Innovation (mv78x00). Armada
370/XP share some of the peripheral IP but especially irq is different.

With respect to SPI, mvebu (Orion + Armada 370/XP) maybe matches best
as it is used in all of them with minor differences. PXA type SoCs use
a different IP for SPI.

> [...]
>> Uhm, did you forget to send code?
>
> No, I was holding back until I knew whether you still feel comfortable
> being associated with the patches. I'll send them out now.

Ok, I will try to give it a review at least.

Sebastian

[U-Boot] [PATCH v5 0/8] Add Marvell Dove and SolidRun CuBox support

[Sascha Silbe]

Changes from v4:
- some patches got included in master, so they've been dropped from
  the series
- removed Sebastian Hesselbarth's Signed-off-by and MAINTAINERS entry
  on his request
- modified Kirkwood GPIO and SPI drivers rather than duplicating them


This version has only been tested (lightly) on CuBox Pro, not on
OpenRD (Kirkwood). The latter box is in production use, so I'd like to
know whether the current approach is acceptable before I spend
considerable time on testing.


Sascha Silbe (8):
  ARM: dove: add support for Marvell Dove SoC
  usb: ehci-marvell: add support for second USB controller
  GPIO: add Dove support to Kirkwood GPIO driver
  MMC: sdhci: Add support for dove sdhci
  SPI: add Dove support to Kirkwood SPI driver
  block: mvsata: add dove include
  NET: mvgbe: avoid unused variable warning when used without phylib
    support
  Boards: Add support for SolidRun CuBox

 arch/arm/cpu/armv7/dove/Makefile                   |  49 ++++
 arch/arm/cpu/armv7/dove/cpu.c                      | 274 ++++++++++++++++++
 arch/arm/cpu/armv7/dove/dram.c                     | 117 ++++++++
 arch/arm/cpu/armv7/dove/lowlevel_init.S            |  83 ++++++
 arch/arm/cpu/armv7/dove/mpp.c                      | 318 +++++++++++++++++++++
 arch/arm/cpu/armv7/dove/timer.c                    | 176 ++++++++++++
 arch/arm/cpu/armv7/dove/usb.c                      | 101 +++++++
 arch/arm/include/asm/arch-dove/config.h            | 153 ++++++++++
 arch/arm/include/asm/arch-dove/cpu.h               | 204 +++++++++++++
 arch/arm/include/asm/arch-dove/dove.h              |  98 +++++++
 arch/arm/include/asm/arch-dove/gpio.h              |  35 +++
 arch/arm/include/asm/arch-dove/mmc.h               |  27 ++
 arch/arm/include/asm/arch-dove/mpp.h               | 283 ++++++++++++++++++
 arch/arm/include/asm/arch-dove/usb.h               |  27 ++
 arch/arm/include/asm/arch-kirkwood/gpio.h          |  42 +--
 arch/arm/include/asm/arch-kirkwood/spi.h           |  27 --
 board/solidrun/cubox/Makefile                      |  45 +++
 board/solidrun/cubox/cubox.c                       | 142 +++++++++
 board/solidrun/cubox/kwbimage-spi-1gb.cfg          |  76 +++++
 board/solidrun/cubox/kwbimage-spi-2gb.cfg          |  76 +++++
 board/solidrun/cubox/kwbimage-uart.cfg             |  76 +++++
 boards.cfg                                         |   3 +
 drivers/block/mvsata_ide.c                         |   2 +
 drivers/gpio/kw_gpio.c                             |  43 +--
 drivers/mmc/Makefile                               |   1 +
 drivers/mmc/dove_sdhci.c                           | 101 +++++++
 drivers/net/mvgbe.c                                |   5 +-
 drivers/spi/kirkwood_spi.c                         |  47 ++-
 drivers/usb/host/ehci-marvell.c                    |  35 ++-
 include/configs/cubox.h                            | 185 ++++++++++++
 .../asm/arch-kirkwood/gpio.h => include/kw_gpio.h  |  43 ++-
 31 files changed, 2769 insertions(+), 125 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/dove/Makefile
 create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
 create mode 100644 arch/arm/cpu/armv7/dove/dram.c
 create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
 create mode 100644 arch/arm/cpu/armv7/dove/timer.c
 create mode 100644 arch/arm/cpu/armv7/dove/usb.c
 create mode 100644 arch/arm/include/asm/arch-dove/config.h
 create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
 create mode 100644 arch/arm/include/asm/arch-dove/dove.h
 create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
 create mode 100644 arch/arm/include/asm/arch-dove/mmc.h
 create mode 100644 arch/arm/include/asm/arch-dove/mpp.h
 create mode 100644 arch/arm/include/asm/arch-dove/usb.h
 create mode 100644 board/solidrun/cubox/Makefile
 create mode 100644 board/solidrun/cubox/cubox.c
 create mode 100644 board/solidrun/cubox/kwbimage-spi-1gb.cfg
 create mode 100644 board/solidrun/cubox/kwbimage-spi-2gb.cfg
 create mode 100644 board/solidrun/cubox/kwbimage-uart.cfg
 create mode 100644 drivers/mmc/dove_sdhci.c
 create mode 100644 include/configs/cubox.h
 copy arch/arm/include/asm/arch-kirkwood/gpio.h => include/kw_gpio.h (60%)

-- 
1.8.2.1

[U-Boot] [PATCH v5 1/8] ARM: dove: add support for Marvell Dove SoC

[Sascha Silbe]

This patch adds initial support for the armv7-based Marvell Dove SoC
(88AP510).

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
v4->v5: some adjustments for the GPIO and SPI driver changes

 arch/arm/cpu/armv7/dove/Makefile        |  49 +++++
 arch/arm/cpu/armv7/dove/cpu.c           | 274 +++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/dram.c          | 117 ++++++++++++
 arch/arm/cpu/armv7/dove/lowlevel_init.S |  83 +++++++++
 arch/arm/cpu/armv7/dove/mpp.c           | 318 ++++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/dove/timer.c         | 176 ++++++++++++++++++
 arch/arm/cpu/armv7/dove/usb.c           | 101 ++++++++++
 arch/arm/include/asm/arch-dove/config.h | 153 +++++++++++++++
 arch/arm/include/asm/arch-dove/cpu.h    | 204 ++++++++++++++++++++
 arch/arm/include/asm/arch-dove/dove.h   |  98 ++++++++++
 arch/arm/include/asm/arch-dove/gpio.h   |  35 ++++
 arch/arm/include/asm/arch-dove/mpp.h    | 283 ++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-dove/usb.h    |  27 +++
 13 files changed, 1918 insertions(+)

diff --git a/arch/arm/cpu/armv7/dove/Makefile b/arch/arm/cpu/armv7/dove/Makefile
new file mode 100644
index 0000000..127d67e
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/Makefile
@@ -0,0 +1,49 @@
+#
+# Marvell Dove SoC Makefile
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	+= lowlevel_init.o
+COBJS-y := cpu.o dram.o timer.o mpp.o
+COBJS-$(CONFIG_USB_EHCI_MARVELL) += usb.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/dove/cpu.c b/arch/arm/cpu/armv7/dove/cpu.c
new file mode 100644
index 0000000..b5320b7
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/cpu.c
@@ -0,0 +1,274 @@
+/*
+ * Marvell Dove SoC cpu related functions
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <u-boot/md5.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/usb.h>
+#include <hush.h>
+
+void reset_cpu(unsigned long ignored)
+{
+	struct dovecpu_registers *cpureg =
+	    (struct dovecpu_registers *)DOVE_CPU_REG_BASE;
+
+	/* Enable soft reset to assert RSTOUTn */
+	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+	       &cpureg->rstoutn_mask);
+	/* Assert soft reset */
+	writel(readl(&cpureg->sys_soft_rst) | 1,
+	       &cpureg->sys_soft_rst);
+	do {} while (1);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int dove_print_cpu(void)
+{
+	char *cpu;
+	u32 idreg;
+	u16 part, rev;
+
+	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(idreg));
+
+	part = (idreg >> ARM_ID_PARTNUM_OFFSET) & ARM_ID_PARTNUM_MASK;
+	rev = (idreg >> ARM_ID_REVISION_OFFSET) & ARM_ID_REVISION_MASK;
+
+	switch (part) {
+	case DOVECPU_PART_SHEEVA:
+		cpu = "Marvell Sheeva";
+		break;
+	default:
+		cpu = "Unknown CPU";
+	}
+
+	printf("CPU:   %s (rev %d)\n", cpu, rev);
+	return 0;
+}
+
+int dove_print_soc(void)
+{
+	char *soc, *rev;
+	u16 devid = (readl(DOVE_REG_PCIE_DEVID) >> 16) & 0xffff;
+	u8 revid = readl(DOVE_REG_PCIE_REVID) & 0xff;
+
+	switch (devid) {
+	case DOVESOC_DEVID_AP510:
+		soc = "AP510";
+		break;
+	case DOVESOC_DEVID_F6781:
+		soc = "F6781";
+		break;
+	default:
+		printf("ERROR.. %s: Unsupported SoC %04x\n", __func__, devid);
+		return -1;
+	}
+
+	switch (revid) {
+	case DOVESOC_REVID_Z0:
+		rev = "Z0";
+		break;
+	case DOVESOC_REVID_Z1:
+		rev = "Z1";
+		break;
+	case DOVESOC_REVID_Y0:
+		rev = "Y0";
+		break;
+	case DOVESOC_REVID_Y1:
+		rev = "Y1";
+		break;
+	case DOVESOC_REVID_X0:
+		rev = "X0";
+		break;
+	case DOVESOC_REVID_A0:
+		rev = "A0";
+		break;
+	case DOVESOC_REVID_A1:
+		rev = "A1";
+		break;
+	default:
+		rev = "Unknown revision";
+	};
+
+	printf("SoC:   Dove 88%s (%s)\n", soc, rev);
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	if (dove_print_soc())
+		return -1;
+	if (dove_print_cpu())
+		return -1;
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*
+ * dove_init_gpio - initial GPIO configuration
+ */
+void dove_init_gpio(struct dove_gpio_init *gpp)
+{
+	struct dovegpio_registers *gpio0reg =
+		(struct dovegpio_registers *)DOVE_GPIO0_BASE;
+	struct dovegpio_registers *gpio1reg =
+		(struct dovegpio_registers *)DOVE_GPIO1_BASE;
+	struct dovegpio_registers *gpio2reg =
+		(struct dovegpio_registers *)DOVE_GPIO2_BASE;
+
+	/* Init GPIOS to default values as per board requirement */
+	writel(gpp->val0, &gpio0reg->dout);
+	writel(gpp->val1, &gpio1reg->dout);
+	writel(gpp->val2, &gpio2reg->dout);
+	writel(gpp->oe0_n, &gpio0reg->oe);
+	writel(gpp->oe1_n, &gpio1reg->oe);
+	writel(gpp->oe2_n, &gpio2reg->oe);
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int dove_winctrl_calcsize(unsigned int sizeval)
+{
+	int i;
+	unsigned int j = 0;
+	u32 val = sizeval >> 1;
+
+	for (i = 0; val >= 0x10000; i++) {
+		j |= (1 << i);
+		val = val >> 1;
+	}
+	return 0x0000ffff & j;
+}
+
+/*
+ * dove_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Dove Soc to addess different
+ * devices. Windows 0-3 can be configured for size, BAR and remap addr.
+ * Windows 4-7 can be configured for size and BAR.
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ */
+int dove_config_adr_windows(void)
+{
+	struct dovewin_registers *winregs =
+		(struct dovewin_registers *)DOVE_CPU_WIN_BASE;
+
+	/* Window 0: 1M PCIE0 IO address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE0,
+				     DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE),
+	       &winregs[0].ctrl);
+
+	writel(DOVE_DEFADR_PCIE0_IO, &winregs[0].base);
+	writel(DOVE_DEFADR_PCIE0_IO_REMAP, &winregs[0].remap_lo);
+	writel(0x0, &winregs[0].remap_hi);
+
+	/* Window 1: 1M PCIE1 IO address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE1,
+				     DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE),
+	       &winregs[1].ctrl);
+
+	writel(DOVE_DEFADR_PCIE1_IO, &winregs[1].base);
+	writel(DOVE_DEFADR_PCIE1_IO_REMAP, &winregs[1].remap_lo);
+	writel(0x0, &winregs[1].remap_hi);
+
+	/* Window 2: 128M PCIE0 MEM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE0,
+				     DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE),
+	       &winregs[2].ctrl);
+
+	writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].base);
+	writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].remap_lo);
+	writel(0x0, &winregs[2].remap_hi);
+
+	/* Window 3: 128M PCIE1 MEM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE1,
+				     DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE),
+	       &winregs[3].ctrl);
+
+	writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].base);
+	writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].remap_lo);
+	writel(0x0, &winregs[3].remap_hi);
+
+	/* Window 4: 1M Cryptographic SRAM address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_SASRAM,
+				     DOVECPU_ATTR_SASRAM, DOVECPU_WIN_ENABLE),
+	       &winregs[4].ctrl);
+	writel(DOVE_DEFADR_SASRAM, &winregs[4].base);
+
+	/* Window 5: 128M Bootrom address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_BOOTROM,
+				     DOVECPU_ATTR_BOOTROM, DOVECPU_WIN_ENABLE),
+	       &winregs[5].ctrl);
+	writel(DOVE_DEFADR_BOOTROM, &winregs[5].base);
+
+	/* Window 6: 1M PMU Scratchpad address space */
+	writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PMURAM,
+				     DOVECPU_ATTR_PMURAM, DOVECPU_WIN_ENABLE),
+	       &winregs[6].ctrl);
+	writel(DOVE_DEFADR_PMURAM, &winregs[6].base);
+
+	/* Window 7: Disabled */
+	writel(DOVECPU_WIN_DISABLE, &winregs[7].ctrl);
+
+	return 0;
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	dove_config_adr_windows();
+#ifdef CONFIG_USB_EHCI_MARVELL
+	dove_ehci_phy_init(0);
+	dove_ehci_phy_init(1);
+#endif /* CONFIG_USB_EHCI_MARVELL */
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Enable D-cache. I-cache is already enabled in lowlevel_init.S */
+	dcache_enable();
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+#ifdef CONFIG_MVGBE
+int cpu_eth_init(bd_t *bis)
+{
+	mvgbe_initialize(bis);
+	return 0;
+}
+#endif /* CONFIG_MVGBE */
diff --git a/arch/arm/cpu/armv7/dove/dram.c b/arch/arm/cpu/armv7/dove/dram.c
new file mode 100644
index 0000000..ce535f3
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/dram.c
@@ -0,0 +1,117 @@
+/*
+ * Marvell Dove SoC DRAM initialization
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DOVE_REG_DRAM_MAP(x)	(DOVE_REGISTER(0x800100) + (x * 0x10))
+#define DRAM_START_MASK		0xff800000
+#define DRAM_SIZE_MASK		0xf
+#define DRAM_SIZE_SHIFT		16
+
+/*
+ * dove_sdram_start - reads start from Memory Address Map Register n
+ */
+u32 dove_dram_start(enum memory_bank bank)
+{
+	u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
+	u32 enable = 0x01 & reg;
+
+	if ((!enable) || (bank > BANK1))
+		return 0;
+
+	return reg & DRAM_START_MASK;
+}
+
+/*
+ * dove_sdram_size - reads size from Memory Address Map Register n
+ */
+u32 dove_dram_size(enum memory_bank bank)
+{
+	u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
+	u32 enable = 0x01 & reg;
+	u32 size;
+
+	if ((!enable) || (bank > BANK1))
+		return 0;
+
+	/*
+	 * area_length: 7 = 8M, 8 = 16M, ..., 15 = 2048M
+	 * size = 1 << (area_length + 16)
+	 */
+	size = (reg >> DRAM_SIZE_SHIFT) & DRAM_SIZE_MASK;
+	size = 1 << (size + 16);
+	return size;
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = dove_dram_start(i);
+		gd->bd->bi_dram[i].size = dove_dram_size(i);
+
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/*
+		 * If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash
+		 */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/armv7/dove/lowlevel_init.S b/arch/arm/cpu/armv7/dove/lowlevel_init.S
new file mode 100644
index 0000000..105d12d
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/lowlevel_init.S
@@ -0,0 +1,83 @@
+/*
+ * Marvell Dove SoC icache and reg base low level init
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/dove.h>
+#include <generated/asm-offsets.h>
+#include <linux/linkage.h>
+
+/*
+ * Enable Tauros2 L2 ICache
+ */
+.macro init_l2cc
+	mrc	15, 0, r0, c1, c0, 1
+	orr	r0, r0, #0x2
+	mcr	15, 0, r0, c1, c0, 1
+.endm /* init_l2cc */
+
+/*
+ * Init internal register base addresses
+ */
+.macro init_reg_base
+	/* set SB reg base to 0xf1000000 */
+	ldr	r1, =(DOVE_PREMAP_INT_REGS_BASE_ADDR)
+	ldr	r6, =DOVE_SB_REGS_PHYS_BASE
+	str	r6, [r1]
+
+	/* set NB reg base to 0xf1800000 */
+	ldr	r1, =(DOVE_CPU_CTRL_REG)
+	ldr	r4, =0xffff0000
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	lsr	r4, r6, #16
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+	/* Set AXI bridge address mapping to 0xf1800000 */
+	ldr	r1, =(DOVE_AXI_CTRL_REG)
+	ldr	r4, =0x007fffff
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+	/* set MC configuration register decode address to 0xf1800000 */
+	ldr	r1, =(DOVE_PREMAP_MC_DECODE_REG)
+	ldr	r4, =0x0000ffff
+	ldr	r6, [r1]
+	and	r6, r6, r4
+	ldr	r4, =DOVE_NB_REGS_PHYS_BASE
+	orr	r6, r6, r4
+	str	r6, [r1]
+
+.endm /* init_reg_base */
+
+.section ".text.init", "x"
+
+ENTRY(lowlevel_init)
+	init_l2cc
+	init_reg_base
+
+	/* r12 saved upper lr*/
+	mov pc,lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/dove/mpp.c b/arch/arm/cpu/armv7/dove/mpp.c
new file mode 100644
index 0000000..e929702
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/mpp.c
@@ -0,0 +1,318 @@
+/*
+ * Marvell Dove SoC MPP pinmux
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define MPP_BITS	4
+#define MPP_MASK	0xf
+#define MPPS_PER_REG	8
+
+#define MPP_NUM(_x)	((_x) & 0xff)
+#define MPP_SEL(_x)	(((_x) >> 8) & 0x1f)
+#define MPP_GPIO(_x)	((_x) & (1 << 15))
+
+#define MPP_CTRL(i)			(DOVE_MPP_BASE + (i * MPP_BITS))
+#define MPP_PMU_GENERAL_CTRL		(DOVE_MPP_BASE + 0x010)
+#define  PMUG_AUDIO0_AC97_SEL		(1 << 16)
+#define MPP4_CTRL			(DOVE_MPP_BASE + 0x240)
+#define  MPP4_SDIO0_GPIO_SEL		(1 << 0)
+#define  MPP4_SDIO1_GPIO_SEL		(1 << 1)
+#define  MPP4_CAMERA_GPIO_SEL		(1 << 2)
+#define  MPP4_AUDIO1_GPIO_SEL		(1 << 3)
+#define  MPP4_UART1_GPIO_SEL		(1 << 4)
+#define  MPP4_SPI_GPIO_SEL		(1 << 5)
+#define MPP_GENERAL_CTRL		(DOVE_PDMA_BASE + 0x403c)
+#define  MPPG_NAND_GPIO_SEL		(1 << 0)
+#define  MPPG_AUDIO1_SPDIFO_GPIO_SEL	(1 << 1)
+#define GENERAL_CONFIG_1		(DOVE_PDMA_BASE + 0x002c)
+#define  GENERAL_TWSI_MUXEN_OPTION1	(1 << 7)
+#define GENERAL_CONFIG_2		(DOVE_PDMA_BASE + 0x0030)
+#define  GENERAL_TWSI_OPTION3_SEL	(1 << 22)
+#define  GENERAL_TWSI_MUXEN_OPTION3	(1 << 21)
+#define  GENERAL_TWSI_MUXEN_OPTION2	(1 << 20)
+#define SSP_CONFIG_STATUS_1		(DOVE_PDMA_BASE + 0x0034)
+#define  SSP_SSP_ON_AUDIO1		(1 << 0)
+
+/*
+ * MPP0-23 have standard MPP register layout
+ */
+static void dove_mpp_std_set(u16 config)
+{
+	u8 num = MPP_NUM(config);
+	u32 off = (num / MPPS_PER_REG) * MPP_BITS;
+	u32 shift = (num % MPPS_PER_REG) * MPP_BITS;
+	u32 reg;
+
+	/* configure standard MPP pin */
+	reg  = readl(MPP_CTRL(off));
+	reg &= ~(MPP_MASK << shift);
+	reg |= MPP_SEL(config) << shift;
+	writel(reg, MPP_CTRL(off));
+
+	/* configure gpio capabilities */
+	if (MPP_GPIO(config))
+		kw_gpio_set_valid(num, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+	else
+		kw_gpio_set_valid(num, 0);
+}
+
+/*
+ * MPP0-15 also allow to mux PMU functions
+ */
+static void dove_mpp_pmu_set(u16 config)
+{
+	u8 num = MPP_NUM(config);
+
+	if (MPP_SEL(config) == PMU) {
+		/* enable PMU on MPP */
+		writel(readl(MPP_PMU_GENERAL_CTRL) | (1 << num),
+		       MPP_PMU_GENERAL_CTRL);
+		/* disable gpio capabilities */
+		kw_gpio_set_valid(num, 0);
+	} else {
+		/* disable PMU on MPP */
+		writel(readl(MPP_PMU_GENERAL_CTRL) & ~(1 << num),
+		       MPP_PMU_GENERAL_CTRL);
+		/* configure MPP */
+		dove_mpp_std_set(config);
+	}
+}
+
+/*
+ * MPP groups on MPP4_CTRL have different register layout
+ * and allow GPIO or special function only
+ */
+static void dove_mpp4_set(u16 config)
+{
+	u32 reg = readl(MPP4_CTRL);
+	u32 mask;
+	u8  n, nmin, nmax;
+	int gpio;
+
+	switch (MPP_NUM(config)) {
+	case MPP_CAMERA:
+		mask = MPP4_CAMERA_GPIO_SEL;
+		nmin = MPP_CAMERA;
+		nmax = MPP_CAMERA_MAX;
+		break;
+	case MPP_SDIO0:
+		mask = MPP4_SDIO0_GPIO_SEL;
+		nmin = MPP_SDIO0;
+		nmax = MPP_SDIO0_MAX;
+		break;
+	case MPP_SDIO1:
+		mask = MPP4_SDIO1_GPIO_SEL;
+		nmin = MPP_SDIO1;
+		nmax = MPP_SDIO1_MAX;
+		break;
+	case MPP_SPI:
+		mask = MPP4_SPI_GPIO_SEL;
+		nmin = MPP_SPI;
+		nmax = MPP_SPI_MAX;
+		break;
+	case MPP_UART1:
+		mask = MPP4_UART1_GPIO_SEL;
+		nmin = MPP_UART1;
+		nmax = MPP_UART1_MAX;
+		break;
+	default:
+		return;
+	}
+
+	reg &= ~mask;
+	if (MPP_SEL(config))
+		reg |= mask;
+	writel(reg, MPP4_CTRL);
+
+	/* configure gpio capabilities */
+	gpio = 0;
+	if (MPP_GPIO(config))
+		gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+	for (n = nmin; n <= nmax; n++)
+		kw_gpio_set_valid(n, gpio);
+}
+
+/*
+ * MPP_GENERAL_CTRL allows GPIO on NAND pins
+ */
+static void dove_mpp_nand_set(u16 config)
+{
+	u32 reg = readl(MPP_GENERAL_CTRL);
+	u8 n;
+	int gpio;
+
+	reg &= ~MPPG_NAND_GPIO_SEL;
+	if (config == MPP_NAND_GPO)
+		reg |= MPPG_NAND_GPIO_SEL;
+	writel(reg, MPP_GENERAL_CTRL);
+
+	/* configure gpio capabilities */
+	gpio = (config == MPP_NAND_GPO) ? GPIO_OUTPUT_OK : 0;
+	for (n = MPP_NAND; n <= MPP_NAND_MAX; n++)
+		kw_gpio_set_valid(n, gpio);
+}
+
+/*
+ * Dedicated audio1 pins can carry i2s, spdif, ssp or twsi
+ * and gpio in various combinations
+ */
+#define AUDIO1_TWSI	(1 << 0)
+#define AUDIO1_SPDIFO	(1 << 1)
+#define AUDIO1_SSP	(1 << 2)
+#define AUDIO1_GPIO	(1 << 3)
+
+static void dove_mpp_audio1_set(u16 config)
+{
+	u32 mpp4  = readl(MPP4_CTRL);
+	u32 sspc1 = readl(SSP_CONFIG_STATUS_1);
+	u32 gmpp  = readl(MPP_GENERAL_CTRL);
+	u32 gcfg2 = readl(GENERAL_CONFIG_2);
+	u8 n, sel = MPP_SEL(config);
+	int gpio;
+
+	gcfg2 &= ~GENERAL_TWSI_OPTION3_SEL;
+	gmpp &= ~MPPG_AUDIO1_SPDIFO_GPIO_SEL;
+	sspc1 &= ~SSP_SSP_ON_AUDIO1;
+	mpp4 &= ~MPP4_AUDIO1_GPIO_SEL;
+	if (sel & AUDIO1_TWSI)
+		gcfg2 |= GENERAL_TWSI_OPTION3_SEL;
+	if (sel & AUDIO1_SPDIFO)
+		gmpp |= MPPG_AUDIO1_SPDIFO_GPIO_SEL;
+	if (sel & AUDIO1_SSP)
+		sspc1 |= SSP_SSP_ON_AUDIO1;
+	if (sel & AUDIO1_GPIO)
+		mpp4 |= MPP4_AUDIO1_GPIO_SEL;
+
+	writel(mpp4, MPP4_CTRL);
+	writel(sspc1, SSP_CONFIG_STATUS_1);
+	writel(gmpp, MPP_GENERAL_CTRL);
+	writel(gcfg2, GENERAL_CONFIG_2);
+
+	/* gpio allows gpio on all audio1 mpp pins */
+	gpio = 0;
+	if (config == MPP_AUDIO1_GPIO)
+		gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+
+	for (n = MPP_AUDIO1; n <= MPP_AUDIO1_MAX; n++)
+		kw_gpio_set_valid(n, gpio);
+
+	switch (config) {
+	/* spdifo and twsi allow gpio on mpp[52:55] */
+	case MPP_AUDIO1_SPDIFO:
+	case MPP_AUDIO1_TWSI:
+		kw_gpio_set_valid(52, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		kw_gpio_set_valid(53, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		kw_gpio_set_valid(54, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		kw_gpio_set_valid(55, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		break;
+	/* i2s and ssp allow gpio on mpp[56:57] */
+	case MPP_AUDIO1_I2S:
+	case MPP_AUDIO1_SSP:
+		kw_gpio_set_valid(56, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		kw_gpio_set_valid(57, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
+		break;
+	}
+}
+
+/*
+ * MPP PMU switches audio0 pins to ac97 or i2s0
+ */
+static void dove_mpp_audio0_set(u16 config)
+{
+	/* switch i2s or ac97 to audio0 */
+	u32 reg = readl(MPP_PMU_GENERAL_CTRL);
+
+	reg &= ~PMUG_AUDIO0_AC97_SEL;
+	if (config == MPP_AUDIO0_AC97)
+		reg |= PMUG_AUDIO0_AC97_SEL;
+	writel(reg, MPP_PMU_GENERAL_CTRL);
+}
+
+/*
+ * TWSI has 3 optional pin sets that can be switched during runtime
+ */
+static void dove_mpp_twsi_set(u16 config)
+{
+	u32 gcfg1 = readl(GENERAL_CONFIG_1);
+	u32 gcfg2 = readl(GENERAL_CONFIG_2);
+
+	gcfg1 &= ~GENERAL_TWSI_MUXEN_OPTION1;
+	gcfg2 &= ~(GENERAL_TWSI_MUXEN_OPTION2 | GENERAL_TWSI_MUXEN_OPTION3);
+
+	switch (config) {
+	case MPP_TWSI_OPTION1:
+		gcfg1 |= GENERAL_TWSI_MUXEN_OPTION1;
+		break;
+	case MPP_TWSI_OPTION2:
+		gcfg2 |= GENERAL_TWSI_MUXEN_OPTION2;
+		break;
+	case MPP_TWSI_OPTION3:
+		gcfg2 |= GENERAL_TWSI_MUXEN_OPTION3;
+		break;
+	}
+
+	writel(gcfg1, GENERAL_CONFIG_1);
+	writel(gcfg2, GENERAL_CONFIG_2);
+}
+
+void dove_mpp_conf(u16 *mpp_list)
+{
+	while (*mpp_list) {
+		u8 num = MPP_NUM(*mpp_list);
+
+		if (num <= MPP_PMU_MAX) {
+			dove_mpp_pmu_set(*mpp_list);
+		} else if (num <= MPP_STD_MAX) {
+			dove_mpp_std_set(*mpp_list);
+		} else {
+			switch (num) {
+			case MPP_CAMERA:
+			case MPP_SDIO0:
+			case MPP_SDIO1:
+			case MPP_SPI:
+			case MPP_UART1:
+				dove_mpp4_set(*mpp_list);
+				break;
+			case MPP_NAND:
+				dove_mpp_nand_set(*mpp_list);
+				break;
+			case MPP_AUDIO0:
+				dove_mpp_audio0_set(*mpp_list);
+				break;
+			case MPP_AUDIO1:
+				dove_mpp_audio1_set(*mpp_list);
+				break;
+			case MPP_TWSI:
+				dove_mpp_twsi_set(*mpp_list);
+				break;
+			}
+		}
+		mpp_list++;
+	}
+}
diff --git a/arch/arm/cpu/armv7/dove/timer.c b/arch/arm/cpu/armv7/dove/timer.c
new file mode 100644
index 0000000..3055369
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/timer.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Dove SoC timer
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dove.h>
+
+#define UBOOT_CNTR	0	/* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct dovetmr_val {
+	u32 reload;	/* Timer reload reg */
+	u32 val;	/* Timer value reg */
+};
+
+/* Timer registers */
+struct dovetmr_registers {
+	u32 ctrl;	/* Timer control reg */
+	u32 pad[3];
+	struct dovetmr_val tmr[2];
+	u32 wdt_reload;
+	u32 wdt_val;
+};
+
+struct dovetmr_registers *dovetmr_regs =
+	(struct dovetmr_registers *)DOVE_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG			&dovetmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum)	&dovetmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum)		&dovetmr_regs->tmr[tmrnum].val
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS		0
+#define TRG_ARM_TIMER_REL_MASK		0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS		0
+#define TVR_ARM_TIMER_MASK		0xffffffff
+#define TVR_ARM_TIMER_MAX		0xffffffff
+#define TIMER_LOAD_VAL			0xffffffff
+
+#define READ_TIMER			(readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
+					 (CONFIG_SYS_TCLK / 1000))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER;
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec +
+			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	uint current;
+	ulong delayticks;
+
+	current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
+	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+	if (current < delayticks) {
+		delayticks -= current;
+		do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current);
+		do {} while ((TIMER_LOAD_VAL - delayticks) <
+			     readl(CNTMR_VAL_REG(UBOOT_CNTR)));
+	} else {
+		do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
+			     (current - delayticks));
+	}
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+	unsigned int cntmrctrl;
+
+	/* load value into timer */
+	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+	/* enable timer in auto reload mode */
+	cntmrctrl = readl(CNTMR_CTRL_REG);
+	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+	writel(cntmrctrl, CNTMR_CTRL_REG);
+
+	/* init the timestamp and lastdec value */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/armv7/dove/usb.c b/arch/arm/cpu/armv7/dove/usb.c
new file mode 100644
index 0000000..1b932db
--- /dev/null
+++ b/arch/arm/cpu/armv7/dove/usb.c
@@ -0,0 +1,101 @@
+/*
+ * Marvell Dove SoC USB PHY init
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+
+/* Dove USB2.0 PHY registers */
+#define USB20_POWER_CTRL		((base) + 0x400)
+#define USB20_PHY_PLL_CTRL		((base) + 0x410)
+#define  PHY_PLL_VCO_RECALIBRATE	(1 << 21)
+#define USB20_PHY_TX_CTRL		((base) + 0x420)
+#define  PHY_TX_HS_STRESS_CTRL		(1 << 31)
+#define  PHY_TX_BLOCK_EN		(1 << 21)
+#define  PHY_TX_IMP_CAL_VTH(x)		(x << 14)
+#define  PHY_TX_IMP_CAL_VTH_MASK	PHY_TX_IMP_CAL_VTH(0x7)
+#define  PHY_TX_RCAL_START		(1 << 12)
+#define  PHY_TX_LOWVDD_EN		(1 << 11)
+#define USB20_PHY_RX_CTRL		((base) + 0x430)
+#define  PHY_RX_EDGE_DET(x)		(x << 26)
+#define  PHY_RX_EDGE_DET_MASK		PHY_RX_EDGE_DET(0x3)
+#define  PHY_RX_CDR_FASTLOCK_EN		(1 << 21)
+#define  PHY_RX_SQ_LENGTH(x)		(x << 15)
+#define  PHY_RX_SQ_LENGTH_MASK		PHY_RX_SQ_LENGTH(0x3)
+#define  PHY_RX_SQ_THRESH(x)		(x << 4)
+#define  PHY_RX_SQ_THRESH_MASK		PHY_RX_SQ_THRESH(0xf)
+#define  PHY_RX_LPF_COEFF(x)		(x << 2)
+#define  PHY_RX_LPF_COEFF_MASK		PHY_RX_LPF_COEFF(0x3)
+#define USB20_PHY_IVREF_CTRL		((base) + 0x440)
+#define  PHY_IVREF_TXVDD12(x)		(x << 8)
+#define  PHY_IVREF_TXVDD12_MASK		PHY_IVREF_TXVDD12(0x3)
+#define USB20_PHY_TESTGRP_CTRL		((base) + 0x450)
+#define  PHY_TESTGRP_SQ_RST+
+void dove_ehci_phy_init(int port)
+{
+	u32 base = (port == 0) ? DOVE_USB20_0_BASE : DOVE_USB20_1_BASE;
+	u32 reg;
+
+	/* USB PHY PLL control */
+	reg = readl(USB20_PHY_PLL_CTRL);
+	writel(reg | PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
+	udelay(100);
+	writel(reg & ~PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
+
+	/* USB PHY Tx control */
+	reg = readl(USB20_PHY_TX_CTRL);
+	reg &= ~PHY_TX_IMP_CAL_VTH_MASK;
+	reg |= PHY_TX_IMP_CAL_VTH(0x5);
+	reg |= PHY_TX_LOWVDD_EN;
+	reg |= PHY_TX_RCAL_START;
+	reg |= PHY_TX_BLOCK_EN;
+	reg |= PHY_TX_HS_STRESS_CTRL;
+	writel(reg, USB20_PHY_TX_CTRL);
+	udelay(100);
+	writel(reg & ~PHY_TX_RCAL_START, USB20_PHY_TX_CTRL);
+
+	/* USB PHY RX control */
+	reg = readl(USB20_PHY_RX_CTRL);
+	reg &= ~(PHY_RX_LPF_COEFF_MASK | PHY_RX_SQ_THRESH_MASK |
+		 PHY_RX_SQ_LENGTH_MASK | PHY_RX_EDGE_DET_MASK);
+	reg |= PHY_RX_LPF_COEFF(0x1);
+	reg |= PHY_RX_SQ_THRESH(0xc);
+	reg |= PHY_RX_SQ_LENGTH(0x1);
+	reg |= PHY_RX_EDGE_DET(0x0);
+	reg &= ~PHY_RX_CDR_FASTLOCK_EN;
+	writel(reg, USB20_PHY_RX_CTRL);
+
+	/* USB PHY IVREF control */
+	reg = readl(USB20_PHY_IVREF_CTRL);
+	reg &= ~PHY_IVREF_TXVDD12_MASK;
+	reg |= PHY_IVREF_TXVDD12(0x3);
+	writel(reg, USB20_PHY_IVREF_CTRL);
+
+	/* USB PHY TEST GROUP control */
+	reg = readl(USB20_PHY_TESTGRP_CTRL);
+	reg &= ~PHY_TESTGRP_SQ_RST;
+	writel(reg, USB20_PHY_TESTGRP_CTRL);
+}
diff --git a/arch/arm/include/asm/arch-dove/config.h b/arch/arm/include/asm/arch-dove/config.h
new file mode 100644
index 0000000..38bf6ce
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/config.h
@@ -0,0 +1,153 @@
+/*
+ * Marvell SoC config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_CONFIG_H
+#define _DOVE_CONFIG_H
+
+#include <asm/arch/dove.h>
+
+#define CONFIG_ARMV7			/* Basic Architecture */
+#define CONFIG_DOVE			/* SOC Family Name */
+#define CONFIG_SHEEVA_88SV581		/* CPU Core subversion */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+				/* default Dcache Line length for Dove */
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#define CONFIG_SYS_DCACHE_OFF		/* Disable DCache by default */
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Dove has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#define CONFIG_I2C_MVTWSI_BASE	DOVE_TWSI_BASE
+#define MV_UART_CONSOLE_BASE	DOVE_UART0_BASE
+#define MV_SATA_BASE		DOVE_SATA_BASE
+#define MV_SATA_PORT0_OFFSET	DOVE_SATA_PORT0_OFFSET
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD		1
+#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL		1
+#endif
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI			1
+#define CONFIG_KIRKWOOD_SPI		1
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS		0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS		0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ		25000000
+#endif
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_PHYLIB
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SDHCI
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_SDHCI
+#define CONFIG_DOVE_SDHCI	/* Enable Dove SDHCI controller driver */
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS
+#define CONFIG_SYS_MMC_MAX_DEVICE	2
+#endif
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * IDE Support on SATA ports
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+#define CONFIG_SYS_64BIT_LBA
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#ifndef CONFIG_SOFT_I2C
+#define CONFIG_I2C_MVTWSI
+#endif
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#endif /* _DOVE_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-dove/cpu.h b/arch/arm/include/asm/arch-dove/cpu.h
new file mode 100644
index 0000000..718dd59
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/cpu.h
@@ -0,0 +1,204 @@
+/*
+ * Marvell Dove SoC CPU
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVECPU_H
+#define _DOVECPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define DOVECPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+			| (attr << 8) | (dove_winctrl_calcsize(size) << 16))
+
+#define DOVEGBE_PORT_SERIAL_CONTROL1_REG	(DOVE_EGIGA_BASE + 0x44c)
+#define DOVE_REG_PCIE_DEVID			(DOVE_REG_PCIE0_BASE + 0x00)
+#define DOVE_REG_PCIE_REVID			(DOVE_REG_PCIE0_BASE + 0x08)
+#define DOVE_REG_SYSRST_CNT			(DOVE_MPP_BASE + 0x50)
+#define SYSRST_CNT_1SEC_VAL			(25*1000000)
+#define DOVE_REG_MPP_OUT_DRV_REG		(DOVE_MPP_BASE + 0xE0)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+};
+
+enum dovecpu_winen {
+	DOVECPU_WIN_DISABLE,
+	DOVECPU_WIN_ENABLE
+};
+
+enum dovecpu_target {
+	DOVECPU_TARGET_DRAM = 0x0,
+	DOVECPU_TARGET_SASRAM = 0x3,
+	DOVECPU_TARGET_NAND = 0xc,
+	DOVECPU_TARGET_PMURAM = 0xd,
+	DOVECPU_TARGET_PCIE0 = 0x4,
+	DOVECPU_TARGET_PCIE1 = 0x8,
+	DOVECPU_TARGET_SPI = 0x1,
+	DOVECPU_TARGET_BOOTROM = 0x1,
+};
+
+enum dovecpu_attrib {
+	DOVECPU_ATTR_DRAM = 0x00,
+	DOVECPU_ATTR_SASRAM = 0x00,
+	DOVECPU_ATTR_NAND = 0x00,
+	DOVECPU_ATTR_PMURAM = 0x00,
+	DOVECPU_ATTR_PCIE_IO = 0xe0,
+	DOVECPU_ATTR_PCIE_MEM = 0xe8,
+	DOVECPU_ATTR_SPI0 = 0xfe,
+	DOVECPU_ATTR_SPI1 = 0xfb,
+	DOVECPU_ATTR_BOOTROM = 0xfd,
+};
+
+enum dovecpu_part {
+	DOVECPU_PART_SHEEVA = 0x581,
+};
+
+enum dovesoc_devid {
+	DOVESOC_DEVID_F6781 = 0x6781,
+	DOVESOC_DEVID_AP510 = 0x0510,
+};
+
+enum dovesoc_revid {
+	DOVESOC_REVID_Z0 = 0,
+	DOVESOC_REVID_Z1 = 1,
+	DOVESOC_REVID_Y0 = 2,
+	DOVESOC_REVID_Y1 = 3,
+	DOVESOC_REVID_X0 = 4,
+	DOVESOC_REVID_A0 = 6,
+	DOVESOC_REVID_A1 = 7,
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define DOVE_DEFADR_PCIE0_MEM		0xe0000000
+#define DOVE_DEFADR_PCIE0_IO		0xf2000000
+#define DOVE_DEFADR_PCIE0_IO_REMAP	0x00000000
+#define DOVE_DEFADR_PCIE1_MEM		0xe8000000
+#define DOVE_DEFADR_PCIE1_IO		0xf2100000
+#define DOVE_DEFADR_PCIE1_IO_REMAP	0x00100000
+#define DOVE_DEFADR_SASRAM		0xc8000000
+#define DOVE_DEFADR_BOOTROM		0xf8000000
+#define DOVE_DEFADR_PMURAM		0xf0000000
+
+/*
+ * ARM CPUID register
+ */
+#define ARM_ID_REVISION_OFFSET	0
+#define ARM_ID_REVISION_MASK	0xf
+#define ARM_ID_PARTNUM_OFFSET	4
+#define ARM_ID_PARTNUM_MASK	0xfff
+#define ARM_ID_ARCH_OFFSET	16
+#define ARM_ID_ARCH_MASK	0xf
+#define ARM_ID_VAR_OFFSET	20
+#define ARM_ID_VAR_MASK		0xf
+#define ARM_ID_ASCII_OFFSET	24
+#define ARM_ID_ASCII_MASK	0xff
+
+/*
+ * read feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+	unsigned int val;
+	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
+			(val) : : "cc");
+	return val;
+}
+
+/*
+ * write feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
+			(val) : "cc");
+	isb();
+}
+
+/*
+ * Downstream Bridge Registers
+ */
+struct dovewin_registers {
+	u32 ctrl;
+	u32 base;
+	u32 remap_lo;
+	u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ */
+struct dovecpu_registers {
+	u32 config;		/* 0x20100 */
+	u32 ctrl_stat;		/* 0x20104 */
+	u32 rstoutn_mask;	/* 0x20108 */
+	u32 sys_soft_rst;	/* 0x2010C */
+	u32 bridge_cause_irq;	/* 0x20110 */
+	u32 bridge_mask_irq;	/* 0x20114 */
+	u32 pad1;
+	u32 pmu_ctrl;		/* 0x2011c */
+};
+
+/*
+ * GPIO 0/1 Registers
+ * GPIO 2 Registers (no datain/irq)
+ */
+struct dovegpio_registers {
+	u32 dout;
+	u32 oe;
+	u32 blink_en;
+	u32 din_pol;
+	u32 din;
+	u32 irq_cause;
+	u32 irq_mask;
+	u32 irq_level;
+};
+
+struct dove_gpio_init {
+	u32 val0;
+	u32 val1;
+	u32 val2;
+	u32 oe0_n;
+	u32 oe1_n;
+	u32 oe2_n;
+};
+
+/*
+ * functions
+ */
+void reset_cpu(unsigned long ignored);
+unsigned char get_random_hex(void);
+u32 dove_dram_start(enum memory_bank bank);
+u32 dove_dram_size(enum memory_bank bank);
+int dove_config_adr_windows(void);
+void dove_init_gpio(struct dove_gpio_init *);
+unsigned int dove_winctrl_calcsize(unsigned int sizeval);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _DOVECPU_H */
diff --git a/arch/arm/include/asm/arch-dove/dove.h b/arch/arm/include/asm/arch-dove/dove.h
new file mode 100644
index 0000000..f310719
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/dove.h
@@ -0,0 +1,98 @@
+/*
+ * Marvell Dove SoC register offsets and config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_H
+#define _DOVE_H
+
+/* Dove TCLK is fixed to 166MHz */
+#define CONFIG_SYS_TCLK			166666667
+
+/* SOC specific definitions */
+#define DOVE_PREMAP_REGS_PHYS_BASE	0xd0000000
+#define DOVE_PREMAP_INT_REGS_BASE_ADDR  (DOVE_PREMAP_REGS_PHYS_BASE + 0x20080)
+#define DOVE_PREMAP_MC_DECODE_REG       (DOVE_PREMAP_REGS_PHYS_BASE + 0x800010)
+
+#define DOVE_SB_REGS_PHYS_BASE		0xf1000000
+#define DOVE_NB_REGS_PHYS_BASE		0xf1800000
+#define DOVE_REGISTER(x)		(DOVE_SB_REGS_PHYS_BASE + x)
+
+#define DOVE_AXI_CTRL_REG		(DOVE_REGISTER(0xd0224))
+#define DOVE_CPU_CTRL_REG		(DOVE_REGISTER(0xd025c))
+#define DOVE_MC_CTRL_REG		(DOVE_REGISTER(0xd0260))
+#define DOVE_MC_DECODE_REG		(DOVE_REGISTER(0x800010))
+
+#define DOVE_SPI_BASE			(DOVE_REGISTER(0x10600))
+#define DOVE_TWSI_BASE			(DOVE_REGISTER(0x11000))
+#define DOVE_UART0_BASE			(DOVE_REGISTER(0x12000))
+#define DOVE_UART1_BASE			(DOVE_REGISTER(0x12100))
+#define DOVE_UART2_BASE			(DOVE_REGISTER(0x12200))
+#define DOVE_UART3_BASE			(DOVE_REGISTER(0x12300))
+#define DOVE_CPU_WIN_BASE		(DOVE_REGISTER(0x20000))
+#define DOVE_CPU_REG_BASE		(DOVE_REGISTER(0x20100))
+#define DOVE_TIMER_BASE			(DOVE_REGISTER(0x20300))
+#define DOVE_REG_PCIE0_BASE		(DOVE_REGISTER(0x40000))
+#define DOVE_REG_PCIE1_BASE		(DOVE_REGISTER(0x80000))
+#define DOVE_USB20_0_BASE		(DOVE_REGISTER(0x50000))
+#define DOVE_USB20_1_BASE		(DOVE_REGISTER(0x51000))
+#define DOVE_EGIGA_BASE			(DOVE_REGISTER(0x72000))
+#define DOVE_SDIO1_BASE			(DOVE_REGISTER(0x90000))
+#define DOVE_SDIO0_BASE			(DOVE_REGISTER(0x92000))
+#define DOVE_CAMERA_BASE		(DOVE_REGISTER(0x94000))
+#define DOVE_SATA_BASE			(DOVE_REGISTER(0xa0000))
+#define DOVE_NANDF_BASE			(DOVE_REGISTER(0xc0000))
+#define DOVE_PMU_BASE			(DOVE_REGISTER(0xd0000))
+#define DOVE_MPP_BASE			(DOVE_REGISTER(0xd0200))
+#define DOVE_GPIO0_BASE			(DOVE_REGISTER(0xd0400))
+#define DOVE_GPIO1_BASE			(DOVE_REGISTER(0xd0420))
+#define DOVE_RTC_BASE			(DOVE_REGISTER(0xd8500))
+#define DOVE_AC97_BASE			(DOVE_REGISTER(0xe0000))
+#define DOVE_PDMA_BASE			(DOVE_REGISTER(0xe4000))
+#define DOVE_GPIO2_BASE			(DOVE_REGISTER(0xe8400))
+#define DOVE_SSP_BASE			(DOVE_REGISTER(0xec000))
+
+/* Dove Sata controller has one port */
+#define DOVE_SATA_PORT0_OFFSET		0x2000
+
+/* Dove GbE controller has one port */
+#define MAX_MVGBE_DEVS			1
+#define MVGBE0_BASE			DOVE_EGIGA_BASE
+
+/* Dove USB Host controller */
+#define MVUSB0_BASE			DOVE_USB20_0_BASE
+#define MVUSB0_CPU_ATTR_DRAM_CS0	DOVECPU_ATTR_DRAM
+#define MVUSB0_CPU_ATTR_DRAM_CS1	DOVECPU_ATTR_DRAM
+#define MVUSB0_CPU_ATTR_DRAM_CS2	DOVECPU_WIN_DISABLE
+#define MVUSB0_CPU_ATTR_DRAM_CS3	DOVECPU_WIN_DISABLE
+#define MVUSB1_BASE			DOVE_USB20_1_BASE
+#define MVUSB1_CPU_ATTR_DRAM_CS0	DOVECPU_ATTR_DRAM
+#define MVUSB1_CPU_ATTR_DRAM_CS1	DOVECPU_ATTR_DRAM
+#define MVUSB1_CPU_ATTR_DRAM_CS2	DOVECPU_WIN_DISABLE
+#define MVUSB1_CPU_ATTR_DRAM_CS3	DOVECPU_WIN_DISABLE
+
+/* Dove CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA		DOVECPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE		DOVECPU_WIN_ENABLE
+#define MVCPU_WIN_DISABLE		DOVECPU_WIN_DISABLE
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/gpio.h b/arch/arm/include/asm/arch-dove/gpio.h
new file mode 100644
index 0000000..adcc91a
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Marvell Dove SoC gpio
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARCH_DOVE_GPIO_H
+#define __ARCH_DOVE_GPIO_H
+
+#include <kw_gpio.h>
+
+#define GPIO_MAX		70
+#define GPIO_BASE(pin)		(((pin) >= 64) ? DOVE_GPIO2_BASE : \
+				 ((pin) >= 32) ? DOVE_GPIO1_BASE : \
+				 DOVE_GPIO0_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/mpp.h b/arch/arm/include/asm/arch-dove/mpp.h
new file mode 100644
index 0000000..1279ac2
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/mpp.h
@@ -0,0 +1,283 @@
+/*
+ * Marvell Dove SoC pinmux
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVE_MPP_H
+#define _DOVE_MPP_H
+
+#define DOVE_GPI	(1 << 0)
+#define DOVE_GPO	(1 << 1)
+#define DOVE_GPIO	(DOVE_GPO | DOVE_GPI)
+
+#define MPP(_num, _sel, _gpio) (			 \
+	/* MPP number */	((_num) & 0xff) |	 \
+	/* MPP select value */	(((_sel) & 0x1f) << 8) | \
+	/* is gpio config */	((!!(_gpio)) << 15))
+
+/* MPP0-15 allow PMU function */
+#define MPP_PMU_MAX		15
+#define PMU			(0x10)
+/* MPP0-23 have standard mpp register layout */
+#define MPP_STD_MAX		23
+
+#define MPP0			0
+#define MPP0_GPIO		MPP(0, 0x0, 1)
+#define MPP0_UART2_RTS		MPP(0, 0x2, 0)
+#define MPP0_SDIO0_CD		MPP(0, 0x3, 0)
+#define MPP0_LCD0_PWM		MPP(0, 0xf, 0)
+#define MPP0_PMU		MPP(0, PMU, 0)
+
+#define MPP1			1
+#define MPP1_GPIO		MPP(1, 0x0, 1)
+#define MPP1_UART2_CTS		MPP(1, 0x2, 0)
+#define MPP1_SDIO0_WP		MPP(1, 0x3, 0)
+#define MPP1_LCD1_PWM		MPP(1, 0xf, 0)
+#define MPP1_PMU		MPP(1, PMU, 0)
+
+#define MPP2			2
+#define MPP2_GPIO		MPP(2, 0x0, 1)
+#define MPP2_SATA_PRSNT		MPP(2, 0x1, 0)
+#define MPP2_UART2_TXD		MPP(2, 0x2, 0)
+#define MPP2_SDIO0_BUSPWR	MPP(2, 0x3, 0)
+#define MPP2_UART1_RTS		MPP(2, 0x4, 0)
+#define MPP2_PMU		MPP(2, PMU, 0)
+
+#define MPP3			3
+#define MPP3_GPIO		MPP(3, 0x0, 1)
+#define MPP3_SATA_ACT		MPP(3, 0x1, 0)
+#define MPP3_UART2_RXD		MPP(3, 0x2, 0)
+#define MPP3_SDIO0_LEDCTRL	MPP(3, 0x3, 0)
+#define MPP3_UART1_CTS		MPP(3, 0x4, 0)
+#define MPP3_LCD_SPI_CS1	MPP(3, 0xf, 0)
+#define MPP3_PMU		MPP(3, PMU, 0)
+
+#define MPP4			4
+#define MPP4_GPIO		MPP(4, 0x0, 1)
+#define MPP4_UART3_RTS		MPP(4, 0x2, 0)
+#define MPP4_SDIO1_CD		MPP(4, 0x3, 0)
+#define MPP4_SPI1_MISO		MPP(4, 0x4, 0)
+#define MPP4_PMU		MPP(4, PMU, 0)
+
+#define MPP5			5
+#define MPP5_GPIO		MPP(5, 0x0, 1)
+#define MPP5_UART3_CTS		MPP(5, 0x2, 0)
+#define MPP5_SDIO1_WP		MPP(5, 0x3, 0)
+#define MPP5_SPI1_CS		MPP(5, 0x4, 0)
+#define MPP5_PMU		MPP(5, PMU, 0)
+
+#define MPP6			6
+#define MPP6_GPIO		MPP(6, 0x0, 1)
+#define MPP6_UART3_TXD		MPP(6, 0x2, 0)
+#define MPP6_SDIO1_BUSPWR	MPP(6, 0x3, 0)
+#define MPP6_SPI1_MOSI		MPP(6, 0x4, 0)
+#define MPP6_PMU		MPP(6, PMU, 0)
+
+#define MPP7			7
+#define MPP7_GPIO		MPP(7, 0x0, 1)
+#define MPP7_UART3_RXD		MPP(7, 0x2, 0)
+#define MPP7_SDIO1_LEDCTRL	MPP(7, 0x3, 0)
+#define MPP7_SPI1_SCK		MPP(7, 0x4, 0)
+#define MPP7_PMU		MPP(7, PMU, 0)
+
+#define MPP8			8
+#define MPP8_GPIO		MPP(8, 0x0, 1)
+#define MPP8_WATCHDOG_RSTOUT	MPP(8, 0x1, 0)
+#define MPP8_PMU		MPP(8, PMU, 0)
+
+#define MPP9			9
+#define MPP9_GPIO		MPP(9, 0x0, 1)
+#define MPP9_PEX1_CLKREQ	MPP(9, 0x5, 0)
+#define MPP9_PMU		MPP(9, PMU, 0)
+
+#define MPP10			10
+#define MPP10_GPIO		MPP(10, 0x0, 1)
+#define MPP10_SSP_SCLK		MPP(10, 0x5, 0)
+#define MPP10_PMU		MPP(10, PMU, 0)
+
+#define MPP11			11
+#define MPP11_GPIO		MPP(11, 0x0, 1)
+#define MPP11_SATA_PRSNT	MPP(11, 0x1, 0)
+#define MPP11_SATA_ACT		MPP(11, 0x2, 0)
+#define MPP11_SDIO0_LEDCTRL	MPP(11, 0x3, 0)
+#define MPP11_SDIO1_LEDCTRL	MPP(11, 0x4, 0)
+#define MPP11_PEX0_CLKREQ	MPP(11, 0x5, 0)
+#define MPP11_PMU		MPP(11, PMU, 0)
+
+#define MPP12			12
+#define MPP12_GPIO		MPP(12, 0x0, 1)
+#define MPP12_SATA_ACT		MPP(12, 0x1, 0)
+#define MPP12_UART2_RTS		MPP(12, 0x2, 0)
+#define MPP12_AUDIO0_EXTCLK	MPP(12, 0x3, 0)
+#define MPP12_SDIO1_CD		MPP(12, 0x4, 0)
+#define MPP12_PMU		MPP(12, PMU, 0)
+
+#define MPP13			13
+#define MPP13_GPIO		MPP(13, 0x0, 1)
+#define MPP13_UART2_CTS		MPP(13, 0x2, 0)
+#define MPP13_AUDIO1_EXTCLK	MPP(13, 0x3, 0)
+#define MPP13_SDIO1_WP		MPP(13, 0x4, 0)
+#define MPP13_SSP_EXTCLK	MPP(13, 0x5, 0)
+#define MPP13_PMU		MPP(13, PMU, 0)
+
+#define MPP14			14
+#define MPP14_GPIO		MPP(14, 0x0, 1)
+#define MPP14_UART2_TXD		MPP(14, 0x2, 0)
+#define MPP14_SDIO1_BUSPWR	MPP(14, 0x4, 0)
+#define MPP14_SSP_TXD		MPP(14, 0x5, 0)
+#define MPP14_PMU		MPP(14, PMU, 0)
+
+#define MPP15			15
+#define MPP15_GPIO		MPP(15, 0x0, 1)
+#define MPP15_UART2_RXD		MPP(15, 0x2, 0)
+#define MPP15_SDIO1_LEDCTRL	MPP(15, 0x4, 0)
+#define MPP15_SSP_SFRM		MPP(15, 0x5, 0)
+#define MPP15_PMU		MPP(15, PMU, 0)
+
+#define MPP16			16
+#define MPP16_GPIO		MPP(16, 0x0, 1)
+#define MPP16_UART3_RTS		MPP(16, 0x2, 0)
+#define MPP16_SDIO0_CD		MPP(16, 0x3, 0)
+#define MPP16_LCD_SPI_CS1	MPP(16, 0x4, 0)
+#define MPP16_AC97_SDI1		MPP(16, 0x5, 0)
+
+#define MPP17			17
+#define MPP17_GPIO		MPP(17, 0x0, 1)
+#define MPP17_AC97_SYSCLKO	MPP(17, 0x1, 0)
+#define MPP17_UART3_CTS		MPP(17, 0x2, 0)
+#define MPP17_SDIO0_WP		MPP(17, 0x3, 0)
+#define MPP17_TWSI_SDA		MPP(17, 0x4, 0)
+#define MPP17_AC97_SDI2		MPP(17, 0x5, 0)
+
+#define MPP18			18
+#define MPP18_GPIO		MPP(18, 0x0, 1)
+#define MPP18_UART3_TXD		MPP(18, 0x2, 0)
+#define MPP18_SDIO0_BUSPWR	MPP(18, 0x3, 0)
+#define MPP18_LCD0_PWM		MPP(18, 0x4, 0)
+#define MPP18_AC97_SDI3		MPP(18, 0x5, 0)
+
+#define MPP19			19
+#define MPP19_GPIO		MPP(19, 0x0, 1)
+#define MPP19_UART3_RXD		MPP(19, 0x2, 0)
+#define MPP19_SDIO0_LEDCTRL	MPP(19, 0x3, 0)
+#define MPP19_TWSI_SCK		MPP(19, 0x4, 0)
+
+#define MPP20			20
+#define MPP20_GPIO		MPP(20, 0x0, 1)
+#define MPP20_AC97_SYSCLKO	MPP(20, 0x1, 0)
+#define MPP20_LCD_SPI_MISO	MPP(20, 0x2, 0)
+#define MPP20_SDIO1_CD		MPP(20, 0x3, 0)
+#define MPP20_SDIO0_CD		MPP(20, 0x5, 0)
+#define MPP20_SPI1_MISO		MPP(20, 0x6, 0)
+
+#define MPP21			21
+#define MPP21_GPIO		MPP(21, 0x0, 1)
+#define MPP21_UART1_RTS		MPP(21, 0x1, 0)
+#define MPP21_LCD_SPI_CS0	MPP(21, 0x2, 0)
+#define MPP21_SDIO1_WP		MPP(21, 0x3, 0)
+#define MPP21_SSP_SFRM		MPP(21, 0x4, 0)
+#define MPP21_SDIO0_WP		MPP(21, 0x5, 0)
+#define MPP21_SPI1_CS		MPP(21, 0x6, 0)
+
+#define MPP22			22
+#define MPP22_GPIO		MPP(22, 0x0, 1)
+#define MPP22_UART1_CTS		MPP(22, 0x1, 0)
+#define MPP22_LCD_SPI_MOSI	MPP(22, 0x2, 0)
+#define MPP22_SDIO1_BUSPWR	MPP(22, 0x3, 0)
+#define MPP22_SSP_TXD		MPP(22, 0x4, 0)
+#define MPP22_SDIO0_BUSPWR	MPP(22, 0x5, 0)
+#define MPP22_SPI1_MOSI		MPP(22, 0x6, 0)
+
+#define MPP23			23
+#define MPP23_GPIO		MPP(23, 0x0, 1)
+#define MPP23_LCD_SPI_SCK	MPP(23, 0x2, 0)
+#define MPP23_SDIO1_LEDCTRL	MPP(23, 0x3, 0)
+#define MPP23_SSP_SCLK		MPP(23, 0x4, 0)
+#define MPP23_SDIO0_LEDCTRL	MPP(23, 0x5, 0)
+#define MPP23_SPI1_SCK		MPP(23, 0x6, 0)
+
+/* MPP_CAMERA = MPP[24:39] */
+#define MPP_CAMERA		24
+#define MPP_CAMERA_CAMERA	MPP(24, 0x0, 0)
+#define MPP_CAMERA_GPIO		MPP(24, 0x1, 1)
+#define MPP_CAMERA_MAX		39
+
+/* MPP_SDIO0 = MPP[40:45] */
+#define MPP_SDIO0		40
+#define MPP_SDIO0_SDIO		MPP(40, 0x0, 0)
+#define MPP_SDIO0_GPIO		MPP(40, 0x1, 1)
+#define MPP_SDIO0_MAX		45
+
+/* MPP_SDIO1 = MPP[46:51] */
+#define MPP_SDIO1		46
+#define MPP_SDIO1_SDIO		MPP(46, 0x0, 0)
+#define MPP_SDIO1_GPIO		MPP(46, 0x1, 1)
+#define MPP_SDIO1_MAX		51
+
+/* MPP_AUDIO1 = MPP[52:57] */
+#define MPP_AUDIO1		52
+#define MPP_AUDIO1_I2S_SPDIFO	MPP(52, 0x0, 0)
+#define MPP_AUDIO1_I2S		MPP(52, 0x2, 0)
+#define MPP_AUDIO1_SPDIFO	MPP(52, 0x8, 0)
+#define MPP_AUDIO1_GPIO		MPP(52, 0xa, 1)
+#define MPP_AUDIO1_TWSI		MPP(52, 0xb, 0)
+#define MPP_AUDIO1_SSP_SPDIFO	MPP(52, 0xc, 0)
+#define MPP_AUDIO1_SSP		MPP(52, 0xe, 0)
+#define MPP_AUDIO1_SSP_TWSI	MPP(52, 0xf, 0)
+#define MPP_AUDIO1_MAX		57
+
+/* MPP_SPI = MPP[58:61] */
+#define MPP_SPI			58
+#define MPP_SPI_SPI		MPP(58, 0x0, 0)
+#define MPP_SPI_GPIO		MPP(58, 0x1, 1)
+#define MPP_SPI_MAX		61
+
+/* MPP_UART1 = MPP[62:63] */
+#define MPP_UART1		62
+#define MPP_UART1_UART1		MPP(62, 0x0, 0)
+#define MPP_UART1_GPIO		MPP(62, 0x1, 1)
+#define MPP_UART1_MAX		63
+
+/* MPP_NAND = MPP[64:71] */
+#define MPP_NAND		64
+#define MPP_NAND_NAND		MPP(64, 0x0, 0)
+#define MPP_NAND_GPO		MPP(64, 0x1, 1)
+#define MPP_NAND_MAX		71
+
+/* MPP_AUDIO0 = Internal AC97/I2S mux for audio0 pins */
+#define MPP_AUDIO0		72
+#define MPP_AUDIO0_I2S		MPP(72, 0x0, 0)
+#define MPP_AUDIO0_AC97		MPP(72, 0x1, 0)
+
+/* MPP_TWSI = Internal TWSI option mux */
+#define MPP_TWSI		73
+#define MPP_TWSI_NONE		MPP(73, 0x0, 0)
+#define MPP_TWSI_OPTION1	MPP(73, 0x1, 0)
+#define MPP_TWSI_OPTION2	MPP(73, 0x2, 0)
+#define MPP_TWSI_OPTION3	MPP(73, 0x3, 0)
+
+#define MPP_MAX			MPP_TWSI
+
+u8 dove_mpp_get_gpio_caps(u8 num);
+void dove_mpp_conf(u16 *mpp_list);
+
+#endif
diff --git a/arch/arm/include/asm/arch-dove/usb.h b/arch/arm/include/asm/arch-dove/usb.h
new file mode 100644
index 0000000..f288489
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/usb.h
@@ -0,0 +1,27 @@
+/*
+ * Marvell Dove SoC USB
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVEUSB_H
+#define _DOVEUSB_H
+
+void dove_ehci_phy_init(int port);
+#endif /* _DOVEUSB_H */
-- 
1.8.2.1

[U-Boot] [PATCH v5 2/8] usb: ehci-marvell: add support for second USB controller

[Sascha Silbe]

From: Sascha Silbe <sascha-pgp@silbe.org>

Marvell 88AP510 (Armada 510, dove) has two separate USB
controllers. Use the index parameter that already gets passed in to
calculate the base address of the controller.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v4->v5: no changes

 drivers/usb/host/ehci-marvell.c | 35 ++++++++++++++++++++++++-----------
 1 file changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 2b73e4a..d2cf026 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -28,7 +28,9 @@
 #include "ehci.h"
 #include <asm/arch/cpu.h>
 
-#if defined(CONFIG_KIRKWOOD)
+#if defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
+#elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
@@ -36,8 +38,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define rdl(off)	readl(MVUSB0_BASE + (off))
-#define wrl(off, val)	writel((val), MVUSB0_BASE + (off))
+#define rdl(base, off)		readl((base) + (off))
+#define wrl(base, off, val)	writel((val), (base) + (off))
 
 #define USB_WINDOW_CTRL(i)	(0x320 + ((i) << 4))
 #define USB_WINDOW_BASE(i)	(0x324 + ((i) << 4))
@@ -46,10 +48,15 @@ DECLARE_GLOBAL_DATA_PTR;
 /*
  * USB 2.0 Bridge Address Decoding registers setup
  */
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(int index)
 {
 	int i;
 	u32 size, base, attrib;
+#ifdef MVUSB1_BASE
+	u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
+#else
+	u32 usb_base = MVUSB0_BASE;
+#endif
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 
@@ -76,13 +83,13 @@ static void usb_brg_adrdec_setup(void)
 		size = gd->bd->bi_dram[i].size;
 		base = gd->bd->bi_dram[i].start;
 		if ((size) && (attrib))
-			wrl(USB_WINDOW_CTRL(i),
-				MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
-					attrib, MVCPU_WIN_ENABLE));
+			wrl(usb_base, USB_WINDOW_CTRL(i),
+			    MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+						attrib, MVCPU_WIN_ENABLE));
 		else
-			wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
+			wrl(usb_base, USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
 
-		wrl(USB_WINDOW_BASE(i), base);
+		wrl(usb_base, USB_WINDOW_BASE(i), base);
 	}
 }
 
@@ -92,9 +99,15 @@ static void usb_brg_adrdec_setup(void)
  */
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	usb_brg_adrdec_setup();
+#ifdef MVUSB1_BASE
+	u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
+#else
+	u32 usb_base = MVUSB0_BASE;
+#endif
 
-	*hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+	usb_brg_adrdec_setup(index);
+
+	*hccr = (struct ehci_hccr *)(usb_base + 0x100);
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr
 			+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 
-- 
1.8.2.1

[U-Boot] [PATCH v5 3/8] GPIO: add Dove support to Kirkwood GPIO driver

[Sascha Silbe]

The GPIO support of Dove is very similar to that on Kirkwood (and
possibly orion5x as well). Instead of duplicating the code, we tweak
the Kirkwood driver so it works for Dove, too.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v4->v5: Modify Kirkwood driver rather than duplicating it.

 The patch description might do with slightly more detail, but I'd
 like some feedback on the approach first. The patch itself should be
 pretty self-explanatory.

 arch/arm/include/asm/arch-kirkwood/gpio.h          | 42 ++-------------------
 drivers/gpio/kw_gpio.c                             | 43 +++++++++++-----------
 .../asm/arch-kirkwood/gpio.h => include/kw_gpio.h  | 43 +++++++++++-----------
 3 files changed, 47 insertions(+), 81 deletions(-)

diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h
index cd1bc00..8c8f239 100644
--- a/arch/arm/include/asm/arch-kirkwood/gpio.h
+++ b/arch/arm/include/asm/arch-kirkwood/gpio.h
@@ -20,46 +20,12 @@
  * MA 02110-1301 USA
  */
 
-/*
- * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
- * Removed kernel level irq handling. Took some macros from kernel to
- * allow build.
- *
- * Dieter Kiermaier dk-arm-linux at gmx.de
- */
+#ifndef __ARCH_KIRKWOOD_GPIO_H
+#define __ARCH_KIRKWOOD_GPIO_H
 
-#ifndef __KIRKWOOD_GPIO_H
-#define __KIRKWOOD_GPIO_H
-
-/* got from kernel include/linux/bitops.h */
-#define BITS_PER_BYTE 8
-#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+#include <kw_gpio.h>
 
 #define GPIO_MAX		50
-#define GPIO_OFF(pin)		(((pin) >> 5) ? 0x0040 : 0x0000)
-#define GPIO_OUT(pin)		(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
-
-/*
- * Kirkwood-specific GPIO API
- */
-
-void kw_gpio_set_valid(unsigned pin, int mode);
-int kw_gpio_is_valid(unsigned pin, int mode);
-int kw_gpio_direction_input(unsigned pin);
-int kw_gpio_direction_output(unsigned pin, int value);
-int kw_gpio_get_value(unsigned pin);
-void kw_gpio_set_value(unsigned pin, int value);
-void kw_gpio_set_blink(unsigned pin, int blink);
-void kw_gpio_set_unused(unsigned pin);
-
-#define GPIO_INPUT_OK		(1 << 0)
-#define GPIO_OUTPUT_OK		(1 << 1)
+#define GPIO_BASE(pin)		(((pin) >> 5) ? (KW_GPIO0_BASE + 0x0040) : KW_GPIO0_BASE)
 
 #endif
diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c
index 51a826d..d6fdb69 100644
--- a/drivers/gpio/kw_gpio.c
+++ b/drivers/gpio/kw_gpio.c
@@ -1,7 +1,11 @@
 /*
- * arch/arm/plat-orion/gpio.c
+ * Marvell Dove and Kirkwood SoC GPIO handling
  *
- * Marvell Orion SoC GPIO handling.
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed orion_gpiochip struct and kernel level irq handling.
+ * Dieter Kiermaier dk-arm-linux at gmx.de
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -22,58 +26,54 @@
  * MA 02110-1301 USA
  */
 
-/*
- * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
- * Removed orion_gpiochip struct and kernel level irq handling.
- *
- * Dieter Kiermaier dk-arm-linux at gmx.de
- */
-
 #include <common.h>
 #include <asm/bitops.h>
 #include <asm/io.h>
-#include <asm/arch/kirkwood.h>
 #include <asm/arch/gpio.h>
+#include <kw_gpio.h>
 
 static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
 static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
 
 void __set_direction(unsigned pin, int input)
 {
+	u32 base = GPIO_BASE(pin);
 	u32 u;
 
-	u = readl(GPIO_IO_CONF(pin));
+	u = readl(GPIO_IO_CONF(base));
 	if (input)
 		u |= 1 << (pin & 31);
 	else
 		u &= ~(1 << (pin & 31));
-	writel(u, GPIO_IO_CONF(pin));
+	writel(u, GPIO_IO_CONF(base));
 
-	u = readl(GPIO_IO_CONF(pin));
+	u = readl(GPIO_IO_CONF(base));
 }
 
 void __set_level(unsigned pin, int high)
 {
+	u32 base = GPIO_BASE(pin);
 	u32 u;
 
-	u = readl(GPIO_OUT(pin));
+	u = readl(GPIO_OUT(base));
 	if (high)
 		u |= 1 << (pin & 31);
 	else
 		u &= ~(1 << (pin & 31));
-	writel(u, GPIO_OUT(pin));
+	writel(u, GPIO_OUT(base));
 }
 
 void __set_blinking(unsigned pin, int blink)
 {
+	u32 base = GPIO_BASE(pin);
 	u32 u;
 
-	u = readl(GPIO_BLINK_EN(pin));
+	u = readl(GPIO_BLINK_EN(base));
 	if (blink)
 		u |= 1 << (pin & 31);
 	else
 		u &= ~(1 << (pin & 31));
-	writel(u, GPIO_BLINK_EN(pin));
+	writel(u, GPIO_BLINK_EN(base));
 }
 
 int kw_gpio_is_valid(unsigned pin, int mode)
@@ -88,7 +88,7 @@ int kw_gpio_is_valid(unsigned pin, int mode)
 	}
 
 err_out:
-		printf("%s: invalid GPIO %d\n", __func__, pin);
+        printf("%s: invalid GPIO %d/%d\n", __func__, pin, GPIO_MAX);
 	return 1;
 }
 
@@ -140,12 +140,13 @@ int kw_gpio_direction_output(unsigned pin, int value)
 
 int kw_gpio_get_value(unsigned pin)
 {
+	u32 base = GPIO_BASE(pin);
 	int val;
 
-	if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
-		val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
+	if (readl(GPIO_IO_CONF(base)) & (1 << (pin & 31)))
+		val = readl(GPIO_DATA_IN(base)) ^ readl(GPIO_IN_POL(base));
 	else
-		val = readl(GPIO_OUT(pin));
+		val = readl(GPIO_OUT(base));
 
 	return (val >> (pin & 31)) & 1;
 }
diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/include/kw_gpio.h
similarity index 60%
copy from arch/arm/include/asm/arch-kirkwood/gpio.h
copy to include/kw_gpio.h
index cd1bc00..7e35833 100644
--- a/arch/arm/include/asm/arch-kirkwood/gpio.h
+++ b/include/kw_gpio.h
@@ -1,5 +1,7 @@
 /*
- * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
+ * Marvell Dove and Kirkwood SoCs common gpio
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -20,34 +22,34 @@
  * MA 02110-1301 USA
  */
 
+#ifndef __KW_GPIO_H
+#define __KW_GPIO_H
+
 /*
- * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
- * Removed kernel level irq handling. Took some macros from kernel to
- * allow build.
- *
- * Dieter Kiermaier dk-arm-linux at gmx.de
+ * SoC-specific gpio.h defines
+ * GPIO_MAX and GPIO_BASE(pin) macro
  */
 
-#ifndef __KIRKWOOD_GPIO_H
-#define __KIRKWOOD_GPIO_H
+#define GPIO_INPUT_OK		(1 << 0)
+#define GPIO_OUTPUT_OK		(1 << 1)
+#define GPIO_LOW		0
+#define GPIO_HIGH		1
 
 /* got from kernel include/linux/bitops.h */
 #define BITS_PER_BYTE 8
 #define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
 
-#define GPIO_MAX		50
-#define GPIO_OFF(pin)		(((pin) >> 5) ? 0x0040 : 0x0000)
-#define GPIO_OUT(pin)		(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
+#define GPIO_OUT(base)		((base) + 0x00)
+#define GPIO_IO_CONF(base)	((base) + 0x04)
+#define GPIO_BLINK_EN(base)	((base) + 0x08)
+#define GPIO_IN_POL(base)	((base) + 0x0c)
+#define GPIO_DATA_IN(base)	((base) + 0x10)
+#define GPIO_EDGE_CAUSE(base)	((base) + 0x14)
+#define GPIO_EDGE_MASK(base)	((base) + 0x18)
+#define GPIO_LEVEL_MASK(base)	((base) + 0x1c)
 
 /*
- * Kirkwood-specific GPIO API
+ * Dove/Kirkwood-specific GPIO API
  */
 
 void kw_gpio_set_valid(unsigned pin, int mode);
@@ -59,7 +61,4 @@ void kw_gpio_set_value(unsigned pin, int value);
 void kw_gpio_set_blink(unsigned pin, int blink);
 void kw_gpio_set_unused(unsigned pin);
 
-#define GPIO_INPUT_OK		(1 << 0)
-#define GPIO_OUTPUT_OK		(1 << 1)
-
 #endif
-- 
1.8.2.1

[U-Boot] [PATCH v5 4/8] MMC: sdhci: Add support for dove sdhci

[Sascha Silbe]

This adds a driver for the sdhci controller found on Dove SoCs.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v4->v5: no changes

 arch/arm/include/asm/arch-dove/mmc.h |  27 ++++++++++
 drivers/mmc/Makefile                 |   1 +
 drivers/mmc/dove_sdhci.c             | 101 +++++++++++++++++++++++++++++++++++
 3 files changed, 129 insertions(+)

diff --git a/arch/arm/include/asm/arch-dove/mmc.h b/arch/arm/include/asm/arch-dove/mmc.h
new file mode 100644
index 0000000..579396c
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/mmc.h
@@ -0,0 +1,27 @@
+/*
+ * Marvell Dove SoC SDHCI
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVEMMC_H
+#define _DOVEMMC_H
+
+int dove_sdhci_init(int num);
+#endif /* _DOVEMMC_H */
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 24648a2..074af75 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -28,6 +28,7 @@ LIB	:= $(obj)libmmc.o
 
 COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+COBJS-$(CONFIG_DOVE_SDHCI) += dove_sdhci.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 COBJS-$(CONFIG_FTSDC010) += ftsdc010_mci.o
 COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
diff --git a/drivers/mmc/dove_sdhci.c b/drivers/mmc/dove_sdhci.c
new file mode 100644
index 0000000..ac15fd7
--- /dev/null
+++ b/drivers/mmc/dove_sdhci.c
@@ -0,0 +1,101 @@
+/*
+ *
+ * Marvell Dove SDHCI driver
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on linux drivers/mmc/host/sdhci-dove.c
+ * by: Saeed Bishara <saeed@marvell.com>
+ *     Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/arch/dove.h>
+
+static u16 dove_sdhci_readw(struct sdhci_host *host, int reg)
+{
+	u16 ret;
+
+	switch (reg) {
+	case SDHCI_HOST_VERSION:
+	case SDHCI_SLOT_INT_STATUS:
+		/* those registers don't exist */
+		return 0;
+	default:
+		ret = readw(host->ioaddr + reg);
+	}
+
+	return ret;
+}
+
+static u32 dove_sdhci_readl(struct sdhci_host *host, int reg)
+{
+	u32 ret;
+
+	switch (reg) {
+	case SDHCI_CAPABILITIES:
+		ret = readl(host->ioaddr + reg);
+		/* Mask the support for 3.0V */
+		ret &= ~SDHCI_CAN_VDD_300;
+		break;
+	default:
+		ret = readl(host->ioaddr + reg);
+	}
+
+	return ret;
+}
+
+static struct sdhci_ops dove_sdhci_ops = {
+	.read_w	= dove_sdhci_readw,
+	.read_l	= dove_sdhci_readl,
+};
+
+static struct sdhci_host hosts[2] = {
+	{
+		.name = "Dove SDHCI0",
+		.ioaddr = (void *)DOVE_SDIO0_BASE,
+	},
+	{
+		.name = "Dove SDHCI1",
+		.ioaddr = (void *)DOVE_SDIO1_BASE,
+	},
+};
+
+int dove_sdhci_init(int num)
+{
+	struct sdhci_host *host;
+
+	if (num < 0 || num > 1)
+		return 1;
+
+	host = &hosts[num];
+
+	if (host->version)
+		return 1;
+
+	host->quirks =
+		SDHCI_QUIRK_NO_HISPD_BIT |
+		SDHCI_QUIRK_BROKEN_R1B |
+		SDHCI_QUIRK_32BIT_DMA_ADDR;
+	host->version = SDHCI_SPEC_200;
+	host->ops = &dove_sdhci_ops;
+
+	add_sdhci(host, 50000000, 4000000);
+	return 0;
+}
-- 
1.8.2.1

[U-Boot] [PATCH v5 5/8] SPI: add Dove support to Kirkwood SPI driver

[Sascha Silbe]

The SPI support on Dove is very similar to that on Kirkwood (and
possibly orion5x as well). Instead of duplicating the code, we tweak
the Kirkwood driver so it works for Dove, too.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v4->v5: Modify Kirkwood driver rather than duplicating it.

 The patch description might do with slightly more detail, but I'd
 like some feedback on the approach first. The patch itself should be
 pretty self-explanatory.

 arch/arm/include/asm/arch-kirkwood/spi.h | 27 ------------------
 drivers/spi/kirkwood_spi.c               | 47 +++++++++++++++++++++++++++++---
 2 files changed, 43 insertions(+), 31 deletions(-)

diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h
index 113f258..4145f62 100644
--- a/arch/arm/include/asm/arch-kirkwood/spi.h
+++ b/arch/arm/include/asm/arch-kirkwood/spi.h
@@ -27,16 +27,6 @@
 #ifndef __KW_SPI_H__
 #define __KW_SPI_H__
 
-/* SPI Registers on kirkwood SOC */
-struct kwspi_registers {
-	u32 ctrl;	/* 0x10600 */
-	u32 cfg;	/* 0x10604 */
-	u32 dout;	/* 0x10608 */
-	u32 din;	/* 0x1060c */
-	u32 irq_cause;	/* 0x10610 */
-	u32 irq_mask;	/* 0x10614 */
-};
-
 /* They are used to define CONFIG_SYS_KW_SPI_MPP
  * each of the below #defines selects which mpp is
  * configured for each SPI signal in spi_claim_bus
@@ -48,21 +38,4 @@ struct kwspi_registers {
 #define SCK_MPP10	(1 << 1)
 #define MISO_MPP11	(1 << 2)
 
-#define KWSPI_CLKPRESCL_MASK	0x1f
-#define KWSPI_CLKPRESCL_MIN	0x12
-#define KWSPI_CSN_ACT		1 /* Activates serial memory interface */
-#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
-#define KWSPI_XFERLEN_1BYTE	0
-#define KWSPI_XFERLEN_2BYTE	(1 << 5)
-#define KWSPI_XFERLEN_MASK	(1 << 5)
-#define KWSPI_ADRLEN_1BYTE	0
-#define KWSPI_ADRLEN_2BYTE	1 << 8
-#define KWSPI_ADRLEN_3BYTE	2 << 8
-#define KWSPI_ADRLEN_4BYTE	3 << 8
-#define KWSPI_ADRLEN_MASK	3 << 8
-#define KWSPI_TIMEOUT		10000
-
 #endif /* __KW_SPI_H__ */
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index caa91e3..4e4c814 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -28,23 +28,58 @@
 #include <malloc.h>
 #include <spi.h>
 #include <asm/io.h>
-#include <asm/arch/kirkwood.h>
-#include <asm/arch/spi.h>
-#include <asm/arch/mpp.h>
+#include <asm/arch/config.h>
 
-static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
+/* SPI Registers on Dove/Kirkwood SOC */
+struct kwspi_registers {
+	u32 ctrl;	/* 0x00 */
+	u32 cfg;	/* 0x04 */
+	u32 dout;	/* 0x08 */
+	u32 din;	/* 0x0c */
+	u32 irq_cause;	/* 0x10 */
+	u32 irq_mask;	/* 0x14 */
+};
 
+#if defined(CONFIG_KIRKWOOD)
+static struct kwspi_registers *spireg =
+        (struct kwspi_registers *)KW_SPI_BASE;
+#elif defined(CONFIG_DOVE)
+static struct kwspi_registers *spireg =
+        (struct kwspi_registers *)DOVE_SPI_BASE;
+#endif
+
+#define KWSPI_CLKPRESCL_MASK	0x1f
+#define KWSPI_CLKPRESCL_MIN	0x12
+#define KWSPI_CSN_ACT		1 /* Activates serial memory interface */
+#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
+#define KWSPI_XFERLEN_1BYTE	0
+#define KWSPI_XFERLEN_2BYTE	(1 << 5)
+#define KWSPI_XFERLEN_MASK	(1 << 5)
+#define KWSPI_ADRLEN_1BYTE	0
+#define KWSPI_ADRLEN_2BYTE	(1 << 8)
+#define KWSPI_ADRLEN_3BYTE	(2 << 8)
+#define KWSPI_ADRLEN_4BYTE	(3 << 8)
+#define KWSPI_ADRLEN_MASK	(3 << 8)
+#define KWSPI_TIMEOUT		10000
+
+#if defined(CONFIG_KIRKWOOD)
 u32 cs_spi_mpp_back[2];
+#endif
 
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 				unsigned int max_hz, unsigned int mode)
 {
 	struct spi_slave *slave;
 	u32 data;
+#if defined(CONFIG_KIRKWOOD)
 	static const u32 kwspi_mpp_config[2][2] = {
 		{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
 		{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
 	};
+#endif
 
 	if (!spi_cs_is_valid(bus, cs))
 		return NULL;
@@ -67,15 +102,19 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
 	writel(KWSPI_IRQMASK, &spireg->irq_mask);
 
+#if defined(CONFIG_KIRKWOOD)
 	/* program mpp registers to select  SPI_CSn */
 	kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
+#endif
 
 	return slave;
 }
 
 void spi_free_slave(struct spi_slave *slave)
 {
+#if defined(CONFIG_KIRKWOOD)
 	kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
+#endif
 	free(slave);
 }
 
-- 
1.8.2.1

[U-Boot] [PATCH v5 6/8] block: mvsata: add dove include

[Sascha Silbe]

Dove SoC also uses mvsata, therefore add a SoC specific include to
allow to reuse the mvsata ide driver.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
---
 v4->v5: no changes

 drivers/block/mvsata_ide.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index 42c177f..500f13c 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -29,6 +29,8 @@
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 /* SATA port registers */
-- 
1.8.2.1

[U-Boot] [PATCH v5 7/8] NET: mvgbe: avoid unused variable warning when used without phylib support

[Sascha Silbe]

Avoid a recently introduced unused variable warning for boards that
use mvgbe but not phylib.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v4->v5: Most of the original patch ("NET: mvgbe: add phylib support")
         was merged to master, only this clean-up remains.

 drivers/net/mvgbe.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 319fe8a..e19696a 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -436,8 +436,9 @@ static int mvgbe_init(struct eth_device *dev)
 {
 	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 	struct mvgbe_registers *regs = dmvgbe->regs;
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
-	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) &&  \
+	!defined(CONFIG_PHYLIB) &&			 \
+	defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 	int i;
 #endif
 	/* setup RX rings */
-- 
1.8.2.1

[U-Boot] [PATCH v5 8/8] Boards: Add support for SolidRun CuBox

[Sascha Silbe]

With latest support for Marvell Dove SoC, add the SolidRun CuBox as
the very first board with that SoC.

Three variants are provided:

1. A regular SPI boot image for CuBox (1GiB)

   The CuBox (without "Pro") has 1GiB of memory.

2. A regular SPI boot image for CuBox Pro (2GiB)

   The CuBox Pro has 2GiB of memory. Because larger SDRAM chips are
   used, tRFC needs to be longer than on the 1GiB variant.

3. A UART boot image for both CuBox and CuBox Pro

   This is just for recovery purposes, so the smaller memory map (on
   CuBox Pro) and slower SDRAM access (on CuBox) doesn't
   matter. Having a single image that works on both hardware variants
   is quite convenient during recovery.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v4->v5:
 - dropped MAINTAINERS entry on Sebastian Hesselbarth's request
 - some adjustments to account for GPIO and SPI driver changes

 board/solidrun/cubox/Makefile             |  45 ++++++++
 board/solidrun/cubox/cubox.c              | 142 +++++++++++++++++++++++
 board/solidrun/cubox/kwbimage-spi-1gb.cfg |  76 ++++++++++++
 board/solidrun/cubox/kwbimage-spi-2gb.cfg |  76 ++++++++++++
 board/solidrun/cubox/kwbimage-uart.cfg    |  76 ++++++++++++
 boards.cfg                                |   3 +
 include/configs/cubox.h                   | 185 ++++++++++++++++++++++++++++++
 7 files changed, 603 insertions(+)

diff --git a/board/solidrun/cubox/Makefile b/board/solidrun/cubox/Makefile
new file mode 100644
index 0000000..c771d72
--- /dev/null
+++ b/board/solidrun/cubox/Makefile
@@ -0,0 +1,45 @@
+#
+# SolidRun CuBox Makefile
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cubox.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/solidrun/cubox/cubox.c b/board/solidrun/cubox/cubox.c
new file mode 100644
index 0000000..7d265e4
--- /dev/null
+++ b/board/solidrun/cubox/cubox.c
@@ -0,0 +1,142 @@
+/*
+ * SolidRun CuBox board support
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dove.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/mmc.h>
+#include <kw_gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u16 mpp_config[] = {
+	MPP0_GPIO,
+	MPP1_GPIO, /* USB power enable */
+	MPP2_GPIO, /* USB over-current indication */
+	MPP3_GPIO, /* micro button beneath eSATA port */
+	MPP4_GPIO,
+	MPP5_GPIO,
+	MPP6_GPIO,
+	MPP7_GPIO,
+
+	MPP8_GPIO,
+	MPP9_GPIO,
+	MPP10_GPIO,
+	MPP11_GPIO,
+	MPP12_GPIO, /* SDIO0 card detect */
+	MPP13_AUDIO1_EXTCLK, /* Si5351a audio clock output */
+	MPP14_GPIO,
+	MPP15_GPIO,
+
+	MPP16_GPIO,
+	MPP17_GPIO,
+	MPP18_GPIO, /* Red front LED */
+	MPP19_UART3_RXD, /* IR sensor */
+	MPP20_GPIO,
+	MPP21_GPIO,
+	MPP22_GPIO,
+	MPP23_GPIO,
+
+	MPP_CAMERA_GPIO,
+	MPP_SDIO0_SDIO, /* SDIO0 */
+	MPP_SDIO1_GPIO,
+	MPP_AUDIO1_I2S_SPDIFO, /* SPDIF and HDMI audio */
+	MPP_SPI_SPI, /* SPI */
+	MPP_UART1_GPIO,
+	MPP_NAND_GPO,
+
+	MPP_AUDIO0_I2S,
+	MPP_TWSI_OPTION1, /* TWSI on dedicated pins */
+	0 };
+
+int board_early_init_f(void)
+{
+	struct dove_gpio_init gpp = {
+		.val0  = 0x00010186,
+		.oe0_n = 0xffffffff,
+		.val1  = 0x018000c0,
+		.oe1_n = 0xffffffff,
+		.val2  = 0x00000000,
+		.oe2_n = 0xffffffff,
+	};
+
+	dove_init_gpio(&gpp);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = dove_dram_start(0) + 0x100;
+
+	/* configure mpp */
+	dove_mpp_conf(mpp_config);
+
+	/* usb power enable */
+	kw_gpio_direction_output(MPP1, GPIO_HIGH);
+
+	/* blink led */
+	kw_gpio_direction_output(MPP18, GPIO_HIGH);
+	kw_gpio_set_blink(MPP18, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_MMC
+int board_mmc_init(bd_t *bis)
+{
+	dove_sdhci_init(0);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_RESET_PHY_R
+void dove_eth_phy_init(char *name)
+{
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+		       __func__);
+		return;
+	}
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("%s PHY initialized\n", name);
+}
+
+void reset_phy(void)
+{
+	dove_eth_phy_init("egiga0");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/solidrun/cubox/kwbimage-spi-1gb.cfg b/board/solidrun/cubox/kwbimage-spi-1gb.cfg
new file mode 100644
index 0000000..c3f1ad9
--- /dev/null
+++ b/board/solidrun/cubox/kwbimage-spi-1gb.cfg
@@ -0,0 +1,76 @@
+#
+# Marvell BootROM config for SolidRun CuBox
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# SDRAM initalization
+DATA 0xd0800020 0x00022430	# SDRAM Configuration register 0
+DATA 0xd0800030 0x00022430	# SDRAM Configuration register 1
+DATA 0xd0800050 0x911500c3	# SDRAM Timing register 1
+DATA 0xd0800060 0x646602c4	# SDRAM Timing register 2
+DATA 0xd0800190 0xc2003053	# SDRAM Timing register 3
+DATA 0xd08001c0 0x34f4a187	# SDRAM Timing register 4
+DATA 0xd0800650 0x000f0121	# SDRAM Timing register 5
+DATA 0xd0800660 0x04040200	# SDRAM Timing register 6
+DATA 0xd0800080 0x00000000	# SDRAM Control register 1
+DATA 0xd0800090 0x00080000	# SDRAM Control register 2
+DATA 0xd08000f0 0xc0000000	# SDRAM Control register 3
+DATA 0xd08001a0 0x20c0c009	# SDRAM Control register 4
+DATA 0xd0800280 0x010e0202	# SDRAM Control register 5
+DATA 0xd0800760 0x00000000	# SDRAM Control register 6
+DATA 0xd0800770 0x0000000a	# SDRAM Control register 7
+DATA 0xd0800140 0x20004044	# SDRAM PHY control register 3
+DATA 0xd08001d0 0x133c2339	# SDRAM PHY control register 7
+DATA 0xd08001e0 0x07700330	# SDRAM PHY control register 8
+DATA 0xd08001f0 0x00000033	# SDRAM PHY control register 9
+DATA 0xd0800200 0x0011311c	# SDRAM PHY control register 10
+DATA 0xd0800210 0x00300000	# SDRAM PHY control register 11
+DATA 0xd0800240 0x80000000	# SDRAM PHY control register 14
+DATA 0xd0800510 0x010e0101	# SDRAM MCB control register 1
+DATA 0xd0800230 0x2028006a	# SDRAM PHY control register 13
+DATA 0xd0800e10 0x00280062	# SDRAM PHY DLL control registers 2
+DATA 0xd0800e20 0x00280062	# SDRAM PHY DLL control registers 3
+DATA 0xd0800e30 0x00280062	# SDRAM PHY DLL control registers 4
+
+# SDRAM memory map (2x512MB)
+DATA 0xd0800100 0x000d0001	# SDRAM Memory Address Map register 1
+DATA 0xd0800110 0x200d0001	# SDRAM Memory Address Map register 1
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/solidrun/cubox/kwbimage-spi-2gb.cfg b/board/solidrun/cubox/kwbimage-spi-2gb.cfg
new file mode 100644
index 0000000..7113c66
--- /dev/null
+++ b/board/solidrun/cubox/kwbimage-spi-2gb.cfg
@@ -0,0 +1,76 @@
+#
+# Marvell BootROM config for SolidRun CuBox
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# SDRAM initalization
+DATA 0xd0800020 0x00022530	# SDRAM Configuration register 0
+DATA 0xd0800030 0x00022530	# SDRAM Configuration register 1
+DATA 0xd0800050 0x911500c3	# SDRAM Timing register 1
+DATA 0xd0800060 0x64660784	# SDRAM Timing register 2
+DATA 0xd0800190 0xc2003053	# SDRAM Timing register 3
+DATA 0xd08001c0 0x34f4a187	# SDRAM Timing register 4
+DATA 0xd0800650 0x000f0121	# SDRAM Timing register 5
+DATA 0xd0800660 0x04040200	# SDRAM Timing register 6
+DATA 0xd0800080 0x00000000	# SDRAM Control register 1
+DATA 0xd0800090 0x00080000	# SDRAM Control register 2
+DATA 0xd08000f0 0xc0000000	# SDRAM Control register 3
+DATA 0xd08001a0 0x20c0c009	# SDRAM Control register 4
+DATA 0xd0800280 0x010e0202	# SDRAM Control register 5
+DATA 0xd0800760 0x00000000	# SDRAM Control register 6
+DATA 0xd0800770 0x0000000a	# SDRAM Control register 7
+DATA 0xd0800140 0x20004044	# SDRAM PHY control register 3
+DATA 0xd08001d0 0x133c2339	# SDRAM PHY control register 7
+DATA 0xd08001e0 0x07700330	# SDRAM PHY control register 8
+DATA 0xd08001f0 0x00000033	# SDRAM PHY control register 9
+DATA 0xd0800200 0x0011311c	# SDRAM PHY control register 10
+DATA 0xd0800210 0x00300000	# SDRAM PHY control register 11
+DATA 0xd0800240 0x80000000	# SDRAM PHY control register 14
+DATA 0xd0800510 0x010e0101	# SDRAM MCB control register 1
+DATA 0xd0800230 0x2028006a	# SDRAM PHY control register 13
+DATA 0xd0800e10 0x00280062	# SDRAM PHY DLL control registers 2
+DATA 0xd0800e20 0x00280062	# SDRAM PHY DLL control registers 3
+DATA 0xd0800e30 0x00280062	# SDRAM PHY DLL control registers 4
+
+# SDRAM memory map (2x1GiB)
+DATA 0xd0800100 0x000e0001	# SDRAM Memory Address Map register 1
+DATA 0xd0800110 0x400e0001	# SDRAM Memory Address Map register 1
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/solidrun/cubox/kwbimage-uart.cfg b/board/solidrun/cubox/kwbimage-uart.cfg
new file mode 100644
index 0000000..0077615
--- /dev/null
+++ b/board/solidrun/cubox/kwbimage-uart.cfg
@@ -0,0 +1,76 @@
+#
+# Marvell BootROM config for SolidRun CuBox
+#
+# Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	uart
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# SDRAM initalization
+DATA 0xd0800020 0x00022430	# SDRAM Configuration register 0
+DATA 0xd0800030 0x00022430	# SDRAM Configuration register 1
+DATA 0xd0800050 0x911500c3	# SDRAM Timing register 1
+DATA 0xd0800060 0x64660784	# SDRAM Timing register 2
+DATA 0xd0800190 0xc2003053	# SDRAM Timing register 3
+DATA 0xd08001c0 0x34f4a187	# SDRAM Timing register 4
+DATA 0xd0800650 0x000f0121	# SDRAM Timing register 5
+DATA 0xd0800660 0x04040200	# SDRAM Timing register 6
+DATA 0xd0800080 0x00000000	# SDRAM Control register 1
+DATA 0xd0800090 0x00080000	# SDRAM Control register 2
+DATA 0xd08000f0 0xc0000000	# SDRAM Control register 3
+DATA 0xd08001a0 0x20c0c009	# SDRAM Control register 4
+DATA 0xd0800280 0x010e0202	# SDRAM Control register 5
+DATA 0xd0800760 0x00000000	# SDRAM Control register 6
+DATA 0xd0800770 0x0000000a	# SDRAM Control register 7
+DATA 0xd0800140 0x20004044	# SDRAM PHY control register 3
+DATA 0xd08001d0 0x133c2339	# SDRAM PHY control register 7
+DATA 0xd08001e0 0x07700330	# SDRAM PHY control register 8
+DATA 0xd08001f0 0x00000033	# SDRAM PHY control register 9
+DATA 0xd0800200 0x0011311c	# SDRAM PHY control register 10
+DATA 0xd0800210 0x00300000	# SDRAM PHY control register 11
+DATA 0xd0800240 0x80000000	# SDRAM PHY control register 14
+DATA 0xd0800510 0x010e0101	# SDRAM MCB control register 1
+DATA 0xd0800230 0x2028006a	# SDRAM PHY control register 13
+DATA 0xd0800e10 0x00280062	# SDRAM PHY DLL control registers 2
+DATA 0xd0800e20 0x00280062	# SDRAM PHY DLL control registers 3
+DATA 0xd0800e30 0x00280062	# SDRAM PHY DLL control registers 4
+
+# SDRAM memory map (2x512MB)
+DATA 0xd0800100 0x000d0001	# SDRAM Memory Address Map register 1
+DATA 0xd0800110 0x200d0001	# SDRAM Memory Address Map register 1
+
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+DATA 0xd0020104 0x00000000	# CPU Control and Status register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/boards.cfg b/boards.cfg
index c0c4282..3605d3a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -331,6 +331,9 @@ dalmore                      arm         armv7:arm720t dalmore           nvidia
 colibri_t20_iris             arm         armv7:arm720t colibri_t20_iris  toradex        tegra20
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
 snowball                     arm         armv7       snowball               st-ericsson    u8500
+cubox                        arm         armv7       cubox               solidrun       dove        cubox:CUBOX_1GB
+cubox_pro                    arm         armv7       cubox               solidrun       dove        cubox:CUBOX_2GB
+cubox_uart                   arm         armv7       cubox               solidrun       dove        cubox:CUBOX_UART_BOOT
 kzm9g                        arm         armv7       kzm9g               kmc            rmobile
 armadillo-800eva             arm         armv7       armadillo-800eva    atmark-techno  rmobile
 zynq                         arm         armv7       zynq                xilinx         zynq
diff --git a/include/configs/cubox.h b/include/configs/cubox.h
new file mode 100644
index 0000000..7d5845c
--- /dev/null
+++ b/include/configs/cubox.h
@@ -0,0 +1,185 @@
+/*
+ * SolidRun CuBox config
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_CUBOX_H
+#define _CONFIG_CUBOX_H
+#include <asm/sizes.h>
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"SolidRun CuBox"
+
+#undef CONFIG_SYS_KWD_CONFIG
+#if defined(CONFIG_CUBOX_UART_BOOT)
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-uart.cfg
+#elif defined(CONFIG_CUBOX_1GB)
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-spi-1gb.cfg
+#elif defined(CONFIG_CUBOX_2GB)
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-spi-2gb.cfg
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MACH_SOLIDRUN_CUBOX	/* Machine type */
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_KIRKWOOD_GPIO
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable u-boot API for standalone programs.
+ */
+#define CONFIG_API
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Commands configuration
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * redefine mv-common.h macros for armv7/cubox
+ */
+#undef CONFIG_SYS_PROMPT	/* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT	"CuBox> "	/* Command Prompt */
+
+/* There is no arch_misc_init on armv7 */
+#undef CONFIG_ARCH_MISC_INIT
+
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN	(4 * 1024 * 1024) /* 4MiB for malloc() */
+
+/*
+ *  Environment variables configurations
+ */
+#if defined(CONFIG_CMD_SF)
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SECT_SIZE		0x1000	/* 4k */
+#define CONFIG_ENV_SIZE			0x20000 /* 128k */
+#define CONFIG_ENV_OFFSET		0xc0000 /* env starts here */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+
+/*
+ * Default CuBox bootscript environment
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootscript=boot.scr\0"						\
+	"loadaddr=0x02000000\0"						\
+	"mmc_started=0\0"						\
+	"ide_started=0\0"						\
+	"usb_started=0\0"						\
+	"mtdparts=mtdparts=spi0.0:768k(u-boot)ro,128k(uboot_env),128k(fdt),-(empty)\0"
+
+#define CONFIG_BOOTCOMMAND						\
+	"for devn in usb mmc ide ; do "					\
+	"  for part in 0 1; do "					\
+	"    for dir  in / /boot/;do "					\
+	"      for fs in ext2 fat; do "					\
+	"        echo ===> Executing ${fs}load ${devn} 0:${part} ${loadaddr} ${dir}${bootscript};" \
+	"        if itest.s $devn -eq mmc; then"			\
+	"          if itest.s $mmc_started -ne 1; then"			\
+	"            mmcinfo; setenv mmc_started '1';fi;fi;"		\
+	"        if itest.s $devn -eq usb; then"			\
+	"          if itest.s $usb_started -ne 1; then"			\
+	"            usb start; setenv usb_started '1';fi;fi;"		\
+	"        if itest.s $devn -eq ide; then"			\
+	"          if itest.s $ide_started -ne 1; then"			\
+	"            ide reset; setenv ide_started '1';fi;fi;"		\
+	"        if ${fs}load ${devn} 0:${part} ${loadaddr} ${dir}${bootscript}; then" \
+	"          source ${loadaddr}; fi;"				\
+	"        if itest.s $devn -eq usb; then"			\
+	"          echo ===> Executing ${fs}load ${devn} 1:${part} ${loadaddr} ${dir}${bootscript};" \
+	"          if ${fs}load ${devn} 1:${part} ${loadaddr} ${dir}${bootscript}; then" \
+	"            source ${loadaddr}; fi;"				\
+	"        fi;"							\
+	"      done;"							\
+	"    done;"							\
+	"  done;"							\
+	"done;"								\
+	"tftp ${loadaddr} ${bootscript};"				\
+	"source ${loadaddr};"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1}	/* enable port 0 */
+#define CONFIG_PHY_BASE_ADR	1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
+#endif /* CONFIG_CMD_NET */
+
+#ifdef CONFIG_CMD_IDE
+#undef CONFIG_IDE_LED
+#undef CONFIG_SYS_IDE_MAXBUS
+#define CONFIG_SYS_IDE_MAXBUS		1
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_CUBOX_H */
-- 
1.8.2.1

[U-Boot] [PATCH v5 1/8] ARM: dove: add support for Marvell Dove SoC

[Sebastian Hesselbarth]

On 06/25/2013 11:27 PM, Sascha Silbe wrote:
> This patch adds initial support for the armv7-based Marvell Dove SoC
> (88AP510).
>
> Signed-off-by: Sascha Silbe<t-uboot@infra-silbe.de>
> ---
> v4->v5: some adjustments for the GPIO and SPI driver changes
>
[...]
> diff --git a/arch/arm/include/asm/arch-dove/config.h b/arch/arm/include/asm/arch-dove/config.h
> new file mode 100644
> index 0000000..38bf6ce
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/config.h
> @@ -0,0 +1,153 @@
> +/*
> + * Marvell SoC config
> + *
> + * Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVE_CONFIG_H
> +#define _DOVE_CONFIG_H
> +
> +#include<asm/arch/dove.h>
> +
> +#define CONFIG_ARMV7			/* Basic Architecture */
> +#define CONFIG_DOVE			/* SOC Family Name */
> +#define CONFIG_SHEEVA_88SV581		/* CPU Core subversion */
> +#define CONFIG_SYS_CACHELINE_SIZE	32
> +				/* default Dcache Line length for Dove */
> +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
> +#define CONFIG_SYS_DCACHE_OFF		/* Disable DCache by default */
> +
> +/*
> + * By default kwbimage.cfg from board specific folder is used
> + * If for some board, different configuration file need to be used,
> + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
> + */
> +#ifndef CONFIG_SYS_KWD_CONFIG
> +#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
> +#endif /* CONFIG_SYS_KWD_CONFIG */
> +
> +/* Dove has 2k of Security SRAM, use it for SP */
> +#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000

Actually, DOVE_DEFADR_SASRAM remaps security SRAM to 0xc8000000. Maybe
it just works because addresses are wrapped around each 2k bytes.

I suggest to set the above to 0xc8000800 or use
(DOVE_DEFADR_SASRAM | 0x800)

> +#define CONFIG_NR_DRAM_BANKS_MAX	2
> +
> +#define CONFIG_I2C_MVTWSI_BASE	DOVE_TWSI_BASE
> +#define MV_UART_CONSOLE_BASE	DOVE_UART0_BASE
> +#define MV_SATA_BASE		DOVE_SATA_BASE
> +#define MV_SATA_PORT0_OFFSET	DOVE_SATA_PORT0_OFFSET
> +
> +/*
> + * NAND configuration
> + */
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_NAND_KIRKWOOD		1
> +#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
> +#define NAND_ALLOW_ERASE_ALL		1
> +#endif

Knowing the SoC now better, I can say that NAND controller is kind of
different from Kirkwood. Especially, the above NAND_BASE relies on a
proper address window remap that is not done yet on Dove init code.

I suggest to remove the whole NAND ifdef above until proper NAND
driver is available.

[...]
> +/* CONFIG_CMD_IDE requires some #defines for ATA registers */
> +#define CONFIG_SYS_IDE_MAXBUS		2
> +#define CONFIG_SYS_IDE_MAXDEVICE	2

Dove SoC only has a single SATA port, so I guess above defines should
be set to 1.

[...]
> diff --git a/arch/arm/include/asm/arch-dove/cpu.h b/arch/arm/include/asm/arch-dove/cpu.h
> new file mode 100644
> index 0000000..718dd59
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/cpu.h
> @@ -0,0 +1,204 @@
> +/*
> + * Marvell Dove SoC CPU
> + *
> + * Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVECPU_H
> +#define _DOVECPU_H
> +
> +#include<asm/system.h>
> +
> +#ifndef __ASSEMBLY__
> +
> +#define DOVECPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target<<  4) \
> +			| (attr<<  8) | (dove_winctrl_calcsize(size)<<  16))
> +
> +#define DOVEGBE_PORT_SERIAL_CONTROL1_REG	(DOVE_EGIGA_BASE + 0x44c)
> +#define DOVE_REG_PCIE_DEVID			(DOVE_REG_PCIE0_BASE + 0x00)
> +#define DOVE_REG_PCIE_REVID			(DOVE_REG_PCIE0_BASE + 0x08)
> +#define DOVE_REG_SYSRST_CNT			(DOVE_MPP_BASE + 0x50)
> +#define SYSRST_CNT_1SEC_VAL			(25*1000000)

Wherever the above is used or from, don't ask me why I came up with it. 
Dove has no register to set sysrst_out length.

[...]
> diff --git a/arch/arm/include/asm/arch-dove/dove.h b/arch/arm/include/asm/arch-dove/dove.h
> new file mode 100644
> index 0000000..f310719
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/dove.h
> @@ -0,0 +1,98 @@
> +/*
> + * Marvell Dove SoC register offsets and config
> + *
> + * Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVE_H
> +#define _DOVE_H
> +
> +/* Dove TCLK is fixed to 166MHz */
> +#define CONFIG_SYS_TCLK			166666667

Not entirely true as it is configurable by SAR registers. The only
two frequencies allowed are 125MHz and 166MHz above. This is what is
given in Dove FS, but there may be other possible (undocumented)
frequencies.

[...]
> +#define DOVE_SPI_BASE			(DOVE_REGISTER(0x10600))

DOVE_SPI0_BASE and add DOVE_SPI1_BASE at 0x14600.

> +#define DOVE_TWSI_BASE			(DOVE_REGISTER(0x11000))
> +#define DOVE_UART0_BASE			(DOVE_REGISTER(0x12000))
> +#define DOVE_UART1_BASE			(DOVE_REGISTER(0x12100))
> +#define DOVE_UART2_BASE			(DOVE_REGISTER(0x12200))
> +#define DOVE_UART3_BASE			(DOVE_REGISTER(0x12300))
> +#define DOVE_CPU_WIN_BASE		(DOVE_REGISTER(0x20000))
> +#define DOVE_CPU_REG_BASE		(DOVE_REGISTER(0x20100))
> +#define DOVE_TIMER_BASE			(DOVE_REGISTER(0x20300))
> +#define DOVE_REG_PCIE0_BASE		(DOVE_REGISTER(0x40000))
> +#define DOVE_REG_PCIE1_BASE		(DOVE_REGISTER(0x80000))

Out of curiosity, is the board you are planing to add support for
equipped with PCIe slots or anything connected to PCIe?

Thanks for giving the patch set a re-spin.

Sebastian

[U-Boot] [PATCH v5 3/8] GPIO: add Dove support to Kirkwood GPIO driver

[Sebastian Hesselbarth]

On 06/25/2013 11:27 PM, Sascha Silbe wrote:
> The GPIO support of Dove is very similar to that on Kirkwood (and
> possibly orion5x as well). Instead of duplicating the code, we tweak
> the Kirkwood driver so it works for Dove, too.
>
> Signed-off-by: Sascha Silbe<t-uboot@infra-silbe.de>
> ---
[...]
> diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c
> index 51a826d..d6fdb69 100644
> --- a/drivers/gpio/kw_gpio.c
> +++ b/drivers/gpio/kw_gpio.c
> @@ -1,7 +1,11 @@
>   /*
> - * arch/arm/plat-orion/gpio.c
> + * Marvell Dove and Kirkwood SoC GPIO handling
>    *
> - * Marvell Orion SoC GPIO handling.
> + * Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>
> + *
> + * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
> + * Removed orion_gpiochip struct and kernel level irq handling.
> + * Dieter Kiermaier dk-arm-linux at gmx.de
>    *
[...]
>   int kw_gpio_is_valid(unsigned pin, int mode)
> @@ -88,7 +88,7 @@ int kw_gpio_is_valid(unsigned pin, int mode)
>   	}
>
>   err_out:
> -		printf("%s: invalid GPIO %d\n", __func__, pin);
> +        printf("%s: invalid GPIO %d/%d\n", __func__, pin, GPIO_MAX);

nit: indent with TAB

Sebastian

[U-Boot] [PATCH v5 5/8] SPI: add Dove support to Kirkwood SPI driver

[Sebastian Hesselbarth]

On 06/25/2013 11:27 PM, Sascha Silbe wrote:
> The SPI support on Dove is very similar to that on Kirkwood (and
> possibly orion5x as well). Instead of duplicating the code, we tweak
> the Kirkwood driver so it works for Dove, too.
>
> Signed-off-by: Sascha Silbe<t-uboot@infra-silbe.de>
> ---
>   v4->v5: Modify Kirkwood driver rather than duplicating it.
>
>   The patch description might do with slightly more detail, but I'd
>   like some feedback on the approach first. The patch itself should be
>   pretty self-explanatory.
>
>   arch/arm/include/asm/arch-kirkwood/spi.h | 27 ------------------
>   drivers/spi/kirkwood_spi.c               | 47 +++++++++++++++++++++++++++++---
>   2 files changed, 43 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h
> index 113f258..4145f62 100644
> --- a/arch/arm/include/asm/arch-kirkwood/spi.h
> +++ b/arch/arm/include/asm/arch-kirkwood/spi.h
> @@ -27,16 +27,6 @@
>   #ifndef __KW_SPI_H__
>   #define __KW_SPI_H__
>
> -/* SPI Registers on kirkwood SOC */
> -struct kwspi_registers {
> -	u32 ctrl;	/* 0x10600 */
> -	u32 cfg;	/* 0x10604 */
> -	u32 dout;	/* 0x10608 */
> -	u32 din;	/* 0x1060c */
> -	u32 irq_cause;	/* 0x10610 */
> -	u32 irq_mask;	/* 0x10614 */
> -};
> -
>   /* They are used to define CONFIG_SYS_KW_SPI_MPP
>    * each of the below #defines selects which mpp is
>    * configured for each SPI signal in spi_claim_bus
> @@ -48,21 +38,4 @@ struct kwspi_registers {
>   #define SCK_MPP10	(1<<  1)
>   #define MISO_MPP11	(1<<  2)
>
> -#define KWSPI_CLKPRESCL_MASK	0x1f
> -#define KWSPI_CLKPRESCL_MIN	0x12
> -#define KWSPI_CSN_ACT		1 /* Activates serial memory interface */
> -#define KWSPI_SMEMRDY		(1<<  1) /* SerMem Data xfer ready */
> -#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
> -#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
> -#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
> -#define KWSPI_XFERLEN_1BYTE	0
> -#define KWSPI_XFERLEN_2BYTE	(1<<  5)
> -#define KWSPI_XFERLEN_MASK	(1<<  5)
> -#define KWSPI_ADRLEN_1BYTE	0
> -#define KWSPI_ADRLEN_2BYTE	1<<  8
> -#define KWSPI_ADRLEN_3BYTE	2<<  8
> -#define KWSPI_ADRLEN_4BYTE	3<<  8
> -#define KWSPI_ADRLEN_MASK	3<<  8
> -#define KWSPI_TIMEOUT		10000
> -
>   #endif /* __KW_SPI_H__ */
> diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
> index caa91e3..4e4c814 100644
> --- a/drivers/spi/kirkwood_spi.c
> +++ b/drivers/spi/kirkwood_spi.c
> @@ -28,23 +28,58 @@
>   #include<malloc.h>
>   #include<spi.h>
>   #include<asm/io.h>
> -#include<asm/arch/kirkwood.h>
> -#include<asm/arch/spi.h>
> -#include<asm/arch/mpp.h>
> +#include<asm/arch/config.h>
>
> -static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
> +/* SPI Registers on Dove/Kirkwood SOC */
> +struct kwspi_registers {
> +	u32 ctrl;	/* 0x00 */
> +	u32 cfg;	/* 0x04 */
> +	u32 dout;	/* 0x08 */
> +	u32 din;	/* 0x0c */
> +	u32 irq_cause;	/* 0x10 */
> +	u32 irq_mask;	/* 0x14 */
> +};
>
> +#if defined(CONFIG_KIRKWOOD)
> +static struct kwspi_registers *spireg =
> +        (struct kwspi_registers *)KW_SPI_BASE;
> +#elif defined(CONFIG_DOVE)
> +static struct kwspi_registers *spireg =
> +        (struct kwspi_registers *)DOVE_SPI_BASE;
> +#endif
> +
> +#define KWSPI_CLKPRESCL_MASK	0x1f
> +#define KWSPI_CLKPRESCL_MIN	0x12

After I looked deeper in Dove FS SPI registers today, I can now say that
Dove SPI allows some more prescaler settings. Nothing critical, as
kirkwood_spi finds the closest spi clock rate less that requested
frequency. By not using the extended prescaler, you may end up with
spi clock running slower than possible but it will not break anything.

Sebastian

[U-Boot] [PATCH v5 8/8] Boards: Add support for SolidRun CuBox

[Sebastian Hesselbarth]

On 06/25/2013 11:27 PM, Sascha Silbe wrote:
> With latest support for Marvell Dove SoC, add the SolidRun CuBox as
> the very first board with that SoC.
>
> Three variants are provided:
>
> 1. A regular SPI boot image for CuBox (1GiB)
>
>     The CuBox (without "Pro") has 1GiB of memory.
>
> 2. A regular SPI boot image for CuBox Pro (2GiB)
>
>     The CuBox Pro has 2GiB of memory. Because larger SDRAM chips are
>     used, tRFC needs to be longer than on the 1GiB variant.
>
> 3. A UART boot image for both CuBox and CuBox Pro
>
>     This is just for recovery purposes, so the smaller memory map (on
>     CuBox Pro) and slower SDRAM access (on CuBox) doesn't
>     matter. Having a single image that works on both hardware variants
>     is quite convenient during recovery.
>
> Signed-off-by: Sascha Silbe<t-uboot@infra-silbe.de>
> ---
[...]
> diff --git a/boards.cfg b/boards.cfg
> index c0c4282..3605d3a 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -331,6 +331,9 @@ dalmore                      arm         armv7:arm720t dalmore           nvidia
>   colibri_t20_iris             arm         armv7:arm720t colibri_t20_iris  toradex        tegra20
>   u8500_href                   arm         armv7       u8500               st-ericsson    u8500
>   snowball                     arm         armv7       snowball               st-ericsson    u8500
> +cubox                        arm         armv7       cubox               solidrun       dove        cubox:CUBOX_1GB
> +cubox_pro                    arm         armv7       cubox               solidrun       dove        cubox:CUBOX_2GB
> +cubox_uart                   arm         armv7       cubox               solidrun       dove        cubox:CUBOX_UART_BOOT

How about CUBOX_SPI_1GB, CUBOX_SPI_2GB, CUBOX_UART ?
Also, sort order in boards.cfg should be
ARCH (arm), CPU (armv7), SoC (dove), Vendor (solidrun), Target

>   kzm9g                        arm         armv7       kzm9g               kmc            rmobile
>   armadillo-800eva             arm         armv7       armadillo-800eva    atmark-techno  rmobile
>   zynq                         arm         armv7       zynq                xilinx         zynq
> diff --git a/include/configs/cubox.h b/include/configs/cubox.h
> new file mode 100644
> index 0000000..7d5845c
> --- /dev/null
> +++ b/include/configs/cubox.h
> @@ -0,0 +1,185 @@
> +/*
> + * SolidRun CuBox config
> + *
> + * Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _CONFIG_CUBOX_H
> +#define _CONFIG_CUBOX_H
> +#include<asm/sizes.h>
> +
> +/*
> + * Version number information
> + */
> +#define CONFIG_IDENT_STRING	"SolidRun CuBox"
> +
> +#undef CONFIG_SYS_KWD_CONFIG
> +#if defined(CONFIG_CUBOX_UART_BOOT)
> +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-uart.cfg
> +#elif defined(CONFIG_CUBOX_1GB)
> +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-spi-1gb.cfg
> +#elif defined(CONFIG_CUBOX_2GB)
> +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-spi-2gb.cfg
> +#endif

ditto wrt to CONFIG_CUBOX_*

Sebastian

[U-Boot] [PATCH v5 1/8] ARM: dove: add support for Marvell Dove SoC

[Wolfgang Denk]

Dear Sascha Silbe,

In message <1372195668-25496-2-git-send-email-t-uboot@infra-silbe.de> you wrote:
> This patch adds initial support for the armv7-based Marvell Dove SoC
> (88AP510).
> 
> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
> ---
> v4->v5: some adjustments for the GPIO and SPI driver changes
> 
>  arch/arm/cpu/armv7/dove/Makefile        |  49 +++++
>  arch/arm/cpu/armv7/dove/cpu.c           | 274 +++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/dove/dram.c          | 117 ++++++++++++
>  arch/arm/cpu/armv7/dove/lowlevel_init.S |  83 +++++++++
>  arch/arm/cpu/armv7/dove/mpp.c           | 318 ++++++++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/dove/timer.c         | 176 ++++++++++++++++++
>  arch/arm/cpu/armv7/dove/usb.c           | 101 ++++++++++
>  arch/arm/include/asm/arch-dove/config.h | 153 +++++++++++++++
>  arch/arm/include/asm/arch-dove/cpu.h    | 204 ++++++++++++++++++++
>  arch/arm/include/asm/arch-dove/dove.h   |  98 ++++++++++
>  arch/arm/include/asm/arch-dove/gpio.h   |  35 ++++
>  arch/arm/include/asm/arch-dove/mpp.h    | 283 ++++++++++++++++++++++++++++
>  arch/arm/include/asm/arch-dove/usb.h    |  27 +++
>  13 files changed, 1918 insertions(+)

This patch does not apply:

ERROR: patch seems to be corrupt (line wrapped?)
#1269: FILE: arch/arm/include/asm/arch-dove/config.h:100:
diff --git a/arch/arm/include/asm/arch-dove/config.h b/arch/arm/include/asm/arch-dove/config.h


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The thing is, as you progress in the Craft,  you'll  learn  there  is
another rule... When you break rules, break 'em good and hard.
                                    - Terry Pratchett, _Wyrd Sisters_

[U-Boot] [PATCH v5 2/8] usb: ehci-marvell: add support for second USB controller

[Wolfgang Denk]

Dear Sascha Silbe,

In message <1372195668-25496-3-git-send-email-t-uboot@infra-silbe.de> you wrote:
> From: Sascha Silbe <sascha-pgp@silbe.org>
> 
> Marvell 88AP510 (Armada 510, dove) has two separate USB
> controllers. Use the index parameter that already gets passed in to
> calculate the base address of the controller.
...
> -#define rdl(off)	readl(MVUSB0_BASE + (off))
> -#define wrl(off, val)	writel((val), MVUSB0_BASE + (off))
> +#define rdl(base, off)		readl((base) + (off))
> +#define wrl(base, off, val)	writel((val), (base) + (off))

Instead of extending this, can we eventually clean this up and use C
structs instead?  U-Boot does not allow device accesses through a
based plus offset notation.

>  	u32 size, base, attrib;
> +#ifdef MVUSB1_BASE
> +	u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
> +#else
> +	u32 usb_base = MVUSB0_BASE;
> +#endif

Can we please also avoid this #ifdef's ?  Eventually you can use
something like "base_0 + index * sizeof(struct usb_something)" ?


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Syntactic sugar causes cancer of the semicolon.
                - Epigrams in Programming, ACM SIGPLAN Sept. 1982

[U-Boot] [PATCH v5 3/8] GPIO: add Dove support to Kirkwood GPIO driver

[Wolfgang Denk]

Dear Sascha Silbe,

In message <1372195668-25496-4-git-send-email-t-uboot@infra-silbe.de> you wrote:
> The GPIO support of Dove is very similar to that on Kirkwood (and
> possibly orion5x as well). Instead of duplicating the code, we tweak
> the Kirkwood driver so it works for Dove, too.

This throws a number of checkpatch warnings and errors (line over 80
characters, code indent should use tabs where possible, please, no
spaces at the start of a line). Please fix.

> -/*
> - * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
> - * Removed kernel level irq handling. Took some macros from kernel to
> - * allow build.
> - *
> - * Dieter Kiermaier dk-arm-linux at gmx.de
> - */

Please never, never ever remove existing Copyright information or
information about the origin of the code.  This is a strong NAK.

> index cd1bc00..7e35833 100644
> --- a/arch/arm/include/asm/arch-kirkwood/gpio.h
> +++ b/include/kw_gpio.h
> @@ -1,5 +1,7 @@
>  /*
> - * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
> + * Marvell Dove and Kirkwood SoCs common gpio
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Which purpose has the mentioning of this name here?  If this is
supposed to be a copyright claim, it should say so.  

> - * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
> - * Removed kernel level irq handling. Took some macros from kernel to
> - * allow build.
> - *
> - * Dieter Kiermaier dk-arm-linux at gmx.de

Again, this gets dropped.  All these changes look pretty much fishy to
me.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
People seldom know what they want until you give them what  they  ask
for.

[U-Boot] [PATCH v5 5/8] SPI: add Dove support to Kirkwood SPI driver

[Wolfgang Denk]

Dear Sascha Silbe,

In message <1372195668-25496-6-git-send-email-t-uboot@infra-silbe.de> you wrote:
> The SPI support on Dove is very similar to that on Kirkwood (and
> possibly orion5x as well). Instead of duplicating the code, we tweak
> the Kirkwood driver so it works for Dove, too.
> 
> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>

Not checkpatch clean: 2 errors, 2 warnings.  Please fix.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If you're out of tree, you don't exist.
     - David Woodhouse in <1304620350.2398.29.camel@i7.infradead.org>

[U-Boot] [PATCH v5 6/8] block: mvsata: add dove include

[Wolfgang Denk]

Dear Sascha Silbe,

In message <1372195668-25496-7-git-send-email-t-uboot@infra-silbe.de> you wrote:
> Dove SoC also uses mvsata, therefore add a SoC specific include to
> allow to reuse the mvsata ide driver.
> 
> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
>  v4->v5: no changes
> 
>  drivers/block/mvsata_ide.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
> index 42c177f..500f13c 100644
> --- a/drivers/block/mvsata_ide.c
> +++ b/drivers/block/mvsata_ide.c
> @@ -29,6 +29,8 @@
>  #include <asm/arch/orion5x.h>
>  #elif defined(CONFIG_KIRKWOOD)
>  #include <asm/arch/kirkwood.h>
> +#elif defined(CONFIG_DOVE)
> +#include <asm/arch/dove.h>

Please keep such lists sorted.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Real programmers can write assembly code in any language.   :-)
                      - Larry Wall in  <8571@jpl-devvax.JPL.NASA.GOV>

[U-Boot] [PATCH v5 8/8] Boards: Add support for SolidRun CuBox

[Wolfgang Denk]

Dear Sascha Silbe,

In message <1372195668-25496-9-git-send-email-t-uboot@infra-silbe.de> you wrote:
> With latest support for Marvell Dove SoC, add the SolidRun CuBox as
> the very first board with that SoC.

Not checkpatch clean: 4 x line over 80 characters; please fix.

>  - dropped MAINTAINERS entry on Sebastian Hesselbarth's request

This makes no sense.  You add a new board, and this must have a
matching entry in the MAINTAINERS file.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Where humor is concerned there are no standards -- no  one  can  say
what is good or bad, although you can be sure that everyone will.
- John Kenneth Galbraith

[U-Boot] [PATCH v5 2/8] usb: ehci-marvell: add support for second USB controller

[Sascha Silbe]

Dear Wolfgang Denk,

Wolfgang Denk <wd@denx.de> writes:

>> -#define rdl(off)	readl(MVUSB0_BASE + (off))
>> -#define wrl(off, val)	writel((val), MVUSB0_BASE + (off))
>> +#define rdl(base, off)		readl((base) + (off))
>> +#define wrl(base, off, val)	writel((val), (base) + (off))
>
> Instead of extending this, can we eventually clean this up and use C
> structs instead?  U-Boot does not allow device accesses through a
> based plus offset notation.

Thanks for the review. I've given the clean-up a stab today, as a
separate patch that the CuBox support series can build on.


>>  	u32 size, base, attrib;
>> +#ifdef MVUSB1_BASE
>> +	u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
>> +#else
>> +	u32 usb_base = MVUSB0_BASE;
>> +#endif
>
> Can we please also avoid this #ifdef's ?  Eventually you can use
> something like "base_0 + index * sizeof(struct usb_something)" ?

The two USB host controllers on Dove are separate entities at
different base offsets (0x50000 vs. 0x51000). We could fill up the
register struct to have a size of 0x1000, but then the next SoC to be
supported could come up with a different offset.

Sascha

[U-Boot] [PATCH] usb: ehci-marvell: use structs for registers

[Sascha Silbe]

Use structs instead of computing offsets for accessing individual
registers. The base address of the USB controller is still an offset
defined in SoC headers as it can differ between SoCs.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
Tested on CuBox Pro only.

 drivers/usb/host/ehci-marvell.c | 48 +++++++++++++++++++++++++++++------------
 1 file changed, 34 insertions(+), 14 deletions(-)

diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 2b73e4a..e4d6881 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -36,17 +36,35 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define rdl(off)	readl(MVUSB0_BASE + (off))
-#define wrl(off, val)	writel((val), MVUSB0_BASE + (off))
-
-#define USB_WINDOW_CTRL(i)	(0x320 + ((i) << 4))
-#define USB_WINDOW_BASE(i)	(0x324 + ((i) << 4))
 #define USB_TARGET_DRAM		0x0
 
+/* USB 2.0 Bridge Address Decoding registers */
+struct mvusb_bad_window_regs {
+	u32 control;
+	u32 base;
+	u32 reserved[2];
+};
+
+struct mvusb_bridge_regs {
+	u32 bridge_control;
+	u32 reserved1[3];
+	u32 int_cause; /* Bridge Interrupt Cause Register */
+	u32 int_mask; /* Bridge Interrupt Mask Register */
+	u32 reserved2;
+	u32 error_addr; /* Bridge Error Address Register */
+	struct mvusb_bad_window_regs window[4];
+};
+
+struct mvusb_regs {
+	u32 unused1[0x40];
+	u32 ehci_regs[0x80];
+	struct mvusb_bridge_regs bridge;
+};
+
 /*
  * USB 2.0 Bridge Address Decoding registers setup
  */
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(struct mvusb_regs *usb_base)
 {
 	int i;
 	u32 size, base, attrib;
@@ -75,14 +93,15 @@ static void usb_brg_adrdec_setup(void)
 
 		size = gd->bd->bi_dram[i].size;
 		base = gd->bd->bi_dram[i].start;
-		if ((size) && (attrib))
-			wrl(USB_WINDOW_CTRL(i),
-				MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
-					attrib, MVCPU_WIN_ENABLE));
+		if (size && attrib)
+			writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+						   attrib, MVCPU_WIN_ENABLE),
+			       usb_base->bridge.window[i].control);
 		else
-			wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
+			writel(MVCPU_WIN_DISABLE,
+			       usb_base->bridge.window[i].control);
 
-		wrl(USB_WINDOW_BASE(i), base);
+		writel(base, usb_base->bridge.window[i].base);
 	}
 }
 
@@ -92,9 +111,10 @@ static void usb_brg_adrdec_setup(void)
  */
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	usb_brg_adrdec_setup();
+	struct mvusb_regs *usb_base = (struct mvusb_regs *)MVUSB0_BASE;
 
-	*hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+	usb_brg_adrdec_setup(usb_base);
+	*hccr = (struct ehci_hccr *)(&usb_base->ehci_regs);
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr
 			+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 
-- 
1.8.2.1

[U-Boot] [PATCH v5 2/8] usb: ehci-marvell: add support for second USB controller

[Marek Vasut]

Dear Sascha Silbe,

> Dear Wolfgang Denk,
> 
> Wolfgang Denk <wd@denx.de> writes:
> >> -#define rdl(off)	readl(MVUSB0_BASE + (off))
> >> -#define wrl(off, val)	writel((val), MVUSB0_BASE + (off))
> >> +#define rdl(base, off)		readl((base) + (off))
> >> +#define wrl(base, off, val)	writel((val), (base) + (off))
> > 
> > Instead of extending this, can we eventually clean this up and use C
> > structs instead?  U-Boot does not allow device accesses through a
> > based plus offset notation.
> 
> Thanks for the review. I've given the clean-up a stab today, as a
> separate patch that the CuBox support series can build on.
> 
> >>  	u32 size, base, attrib;
> >> 
> >> +#ifdef MVUSB1_BASE
> >> +	u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
> >> +#else
> >> +	u32 usb_base = MVUSB0_BASE;
> >> +#endif
> > 
> > Can we please also avoid this #ifdef's ?  Eventually you can use
> > something like "base_0 + index * sizeof(struct usb_something)" ?
> 
> The two USB host controllers on Dove are separate entities at
> different base offsets (0x50000 vs. 0x51000). We could fill up the
> register struct to have a size of 0x1000, but then the next SoC to be
> supported could come up with a different offset.

Check drivers/usb/host/ehci-mxs.c for handling of such a case ;-)

Best regards,
Marek Vasut

[U-Boot] [PATCH] usb: ehci-marvell: use structs for registers

[Marek Vasut]

Dear Sascha Silbe,

> Use structs instead of computing offsets for accessing individual
> registers. The base address of the USB controller is still an offset
> defined in SoC headers as it can differ between SoCs.
> 
> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
> ---
> Tested on CuBox Pro only.
> 
>  drivers/usb/host/ehci-marvell.c | 48
> +++++++++++++++++++++++++++++------------ 1 file changed, 34
> insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-marvell.c
> b/drivers/usb/host/ehci-marvell.c index 2b73e4a..e4d6881 100644
> --- a/drivers/usb/host/ehci-marvell.c
> +++ b/drivers/usb/host/ehci-marvell.c
> @@ -36,17 +36,35 @@
> 
>  DECLARE_GLOBAL_DATA_PTR;
> 
> -#define rdl(off)	readl(MVUSB0_BASE + (off))
> -#define wrl(off, val)	writel((val), MVUSB0_BASE + (off))
> -
> -#define USB_WINDOW_CTRL(i)	(0x320 + ((i) << 4))
> -#define USB_WINDOW_BASE(i)	(0x324 + ((i) << 4))
>  #define USB_TARGET_DRAM		0x0
> 
> +/* USB 2.0 Bridge Address Decoding registers */
> +struct mvusb_bad_window_regs {
> +	u32 control;
> +	u32 base;
> +	u32 reserved[2];
> +};
> +
> +struct mvusb_bridge_regs {
> +	u32 bridge_control;
> +	u32 reserved1[3];
> +	u32 int_cause; /* Bridge Interrupt Cause Register */
> +	u32 int_mask; /* Bridge Interrupt Mask Register */
> +	u32 reserved2;
> +	u32 error_addr; /* Bridge Error Address Register */
> +	struct mvusb_bad_window_regs window[4];
> +};
> +
> +struct mvusb_regs {
> +	u32 unused1[0x40];
> +	u32 ehci_regs[0x80];
> +	struct mvusb_bridge_regs bridge;
> +};
> +
>  /*
>   * USB 2.0 Bridge Address Decoding registers setup
>   */
> -static void usb_brg_adrdec_setup(void)
> +static void usb_brg_adrdec_setup(struct mvusb_regs *usb_base)
>  {
>  	int i;
>  	u32 size, base, attrib;
> @@ -75,14 +93,15 @@ static void usb_brg_adrdec_setup(void)
> 
>  		size = gd->bd->bi_dram[i].size;
>  		base = gd->bd->bi_dram[i].start;
> -		if ((size) && (attrib))
> -			wrl(USB_WINDOW_CTRL(i),
> -				MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
> -					attrib, MVCPU_WIN_ENABLE));
> +		if (size && attrib)
> +			writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
> +						   attrib, MVCPU_WIN_ENABLE),
> +			       usb_base->bridge.window[i].control);
>  		else
> -			wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
> +			writel(MVCPU_WIN_DISABLE,
> +			       usb_base->bridge.window[i].control);
> 
> -		wrl(USB_WINDOW_BASE(i), base);
> +		writel(base, usb_base->bridge.window[i].base);
>  	}
>  }

OK

> @@ -92,9 +111,10 @@ static void usb_brg_adrdec_setup(void)
>   */
>  int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor
> **hcor) {
> -	usb_brg_adrdec_setup();
> +	struct mvusb_regs *usb_base = (struct mvusb_regs *)MVUSB0_BASE;
> 
> -	*hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
> +	usb_brg_adrdec_setup(usb_base);
> +	*hccr = (struct ehci_hccr *)(&usb_base->ehci_regs);
>  	*hcor = (struct ehci_hcor *)((uint32_t) *hccr
>  			+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

I'd keep this as-is, since the 0x100 is fairy standard offset in the USB case.

Best regards,
Marek Vasut

[U-Boot] [PATCH v5 4/8] MMC: sdhci: Add support for dove sdhci

[Jagan Teki]

Hi,

I have a few comments.

I myself not convenient with the capital letters on commit header, IMHO
"MMC: dove_sdhci: "  ==> "mmc: dove_sdhci: "

perhaps not much an issue we are taking about.

On Wed, Jun 26, 2013 at 2:57 AM, Sascha Silbe <t-uboot@infra-silbe.de> wrote:
> This adds a driver for the sdhci controller found on Dove SoCs.
>
> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
> ---
>  v4->v5: no changes
>
>  arch/arm/include/asm/arch-dove/mmc.h |  27 ++++++++++
>  drivers/mmc/Makefile                 |   1 +
>  drivers/mmc/dove_sdhci.c             | 101 +++++++++++++++++++++++++++++++++++
>  3 files changed, 129 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-dove/mmc.h b/arch/arm/include/asm/arch-dove/mmc.h
> new file mode 100644
> index 0000000..579396c
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/mmc.h
> @@ -0,0 +1,27 @@
> +/*
> + * Marvell Dove SoC SDHCI
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVEMMC_H
> +#define _DOVEMMC_H
> +
> +int dove_sdhci_init(int num);
> +#endif /* _DOVEMMC_H */

Do you really require this file just for a single func deceleration.
I have a another thought like..just directly call dove_sdhci_init from
board file.

> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> index 24648a2..074af75 100644
> --- a/drivers/mmc/Makefile
> +++ b/drivers/mmc/Makefile
> @@ -28,6 +28,7 @@ LIB   := $(obj)libmmc.o
>
>  COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
>  COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
> +COBJS-$(CONFIG_DOVE_SDHCI) += dove_sdhci.o
>  COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
>  COBJS-$(CONFIG_FTSDC010) += ftsdc010_mci.o
>  COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
> diff --git a/drivers/mmc/dove_sdhci.c b/drivers/mmc/dove_sdhci.c
> new file mode 100644
> index 0000000..ac15fd7
> --- /dev/null
> +++ b/drivers/mmc/dove_sdhci.c
> @@ -0,0 +1,101 @@
> +/*
> + *
> + * Marvell Dove SDHCI driver
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * Based on linux drivers/mmc/host/sdhci-dove.c
> + * by: Saeed Bishara <saeed@marvell.com>
> + *     Mike Rapoport <mike@compulab.co.il>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <sdhci.h>
> +#include <asm/arch/dove.h>
> +
> +static u16 dove_sdhci_readw(struct sdhci_host *host, int reg)
> +{
> +       u16 ret;
> +
> +       switch (reg) {
> +       case SDHCI_HOST_VERSION:
> +       case SDHCI_SLOT_INT_STATUS:
> +               /* those registers don't exist */
> +               return 0;
> +       default:
> +               ret = readw(host->ioaddr + reg);
> +       }
> +
> +       return ret;
> +}
> +
> +static u32 dove_sdhci_readl(struct sdhci_host *host, int reg)
> +{
> +       u32 ret;
> +
> +       switch (reg) {
> +       case SDHCI_CAPABILITIES:
> +               ret = readl(host->ioaddr + reg);
> +               /* Mask the support for 3.0V */
> +               ret &= ~SDHCI_CAN_VDD_300;
> +               break;
> +       default:
> +               ret = readl(host->ioaddr + reg);
> +       }
> +
> +       return ret;
> +}
> +
> +static struct sdhci_ops dove_sdhci_ops = {
> +       .read_w = dove_sdhci_readw,
> +       .read_l = dove_sdhci_readl,
> +};
> +
> +static struct sdhci_host hosts[2] = {
> +       {
> +               .name = "Dove SDHCI0",
> +               .ioaddr = (void *)DOVE_SDIO0_BASE,
> +       },
> +       {
> +               .name = "Dove SDHCI1",
> +               .ioaddr = (void *)DOVE_SDIO1_BASE,
> +       },
> +};
> +
> +int dove_sdhci_init(int num)
> +{
> +       struct sdhci_host *host;
> +
> +       if (num < 0 || num > 1)
> +               return 1;

What exactly this logic is for, are you able to detect the sdhci host
at runtime out of 2.
if not so may be you directly call dove_sdhci_init from board file
with respective base.

> +
> +       host = &hosts[num];
> +
> +       if (host->version)
> +               return 1;
> +
> +       host->quirks =
> +               SDHCI_QUIRK_NO_HISPD_BIT |
> +               SDHCI_QUIRK_BROKEN_R1B |
> +               SDHCI_QUIRK_32BIT_DMA_ADDR;
> +       host->version = SDHCI_SPEC_200;

Better to read the version using sdhci_readw() instead of direct assignment.

--
Thanks,
Jagan.

> +       host->ops = &dove_sdhci_ops;
> +
> +       add_sdhci(host, 50000000, 4000000);
> +       return 0;
> +}
> --
> 1.8.2.1
>

[U-Boot] [PATCH v4 07/10] NET: phy: add 88E1310 PHY initialization

[Joe Hershberger]

On Sun, May 26, 2013 at 1:37 PM, Sascha Silbe <t-uboot@infra-silbe.de> wrote:
> From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>
> This adds PHY initialization for Marvell Alaska 88E1310 PHY.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Applied, Thanks.
-Joe

[U-Boot] [PATCH v4 08/10] NET: mvgbe: add phylib support

[Joe Hershberger]

On Sun, May 26, 2013 at 1:37 PM, Sascha Silbe <t-uboot@infra-silbe.de> wrote:
> From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>
> This add phylib support to the Marvell GBE driver.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>

Applied, Thanks.
-Joe

[U-Boot] [PATCH v2 08/10] NET: mvgbe: add support for Dove

[Joe Hershberger]

On Tue, Dec 4, 2012 at 2:32 AM, Sebastian Hesselbarth
<sebastian.hesselbarth@gmail.com> wrote:
> Marvell Dove also uses mvgbe as ethernet driver, therefore add support
> for Dove to reuse the current driver.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Applied, Thanks.
-Joe

[U-Boot] [PATCH v5 5/8] SPI: add Dove support to Kirkwood SPI driver

[Jagan Teki]

Hi Sascha Silbe,

On Wed, Jun 26, 2013 at 7:41 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Sascha Silbe,
>
> In message <1372195668-25496-6-git-send-email-t-uboot@infra-silbe.de> you wrote:
>> The SPI support on Dove is very similar to that on Kirkwood (and
>> possibly orion5x as well). Instead of duplicating the code, we tweak
>> the Kirkwood driver so it works for Dove, too.
>>
>> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
>
> Not checkpatch clean: 2 errors, 2 warnings.  Please fix.

Any inputs on this.

-- 
Thanks,
Jagan.

[U-Boot] [PATCH v5 5/8] SPI: add Dove support to Kirkwood SPI driver

[Jagan Teki]

On Sat, Dec 21, 2013 at 12:35 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> Hi Sascha Silbe,
>
> On Wed, Jun 26, 2013 at 7:41 PM, Wolfgang Denk <wd@denx.de> wrote:
>> Dear Sascha Silbe,
>>
>> In message <1372195668-25496-6-git-send-email-t-uboot@infra-silbe.de> you wrote:
>>> The SPI support on Dove is very similar to that on Kirkwood (and
>>> possibly orion5x as well). Instead of duplicating the code, we tweak
>>> the Kirkwood driver so it works for Dove, too.
>>>
>>> Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
>>
>> Not checkpatch clean: 2 errors, 2 warnings.  Please fix.
>
> Any inputs on this.

Last ping!

-- 
Thanks,
Jagan.

[U-Boot] Dove / Cubox support patch series (was: Re: [PATCH v4 05/10] SPI: Add Dove SPI driver)

[Sascha Silbe]

Hello Jagan,

Jagan Teki <jagannadh.teki@gmail.com> writes:

> Any update on this.

The Wandboard Quad is working well for my purposes and much easier to
work with (schematics and very extensive data sheets available, mainline
support in both U-Boot and Linux). As a result, I'm focusing my limited
resources on the Wandboard rather than the Cubox.

Sascha
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[U-Boot] Dove / Cubox support patch series (was: Re: [PATCH v4 05/10] SPI: Add Dove SPI driver)

[Otavio Salvador]

On Mon, Mar 3, 2014 at 7:43 PM, Sascha Silbe <t-uboot@infra-silbe.de> wrote:
> Jagan Teki <jagannadh.teki@gmail.com> writes:
>
>> Any update on this.
>
> The Wandboard Quad is working well for my purposes and much easier to
> work with (schematics and very extensive data sheets available, mainline
> support in both U-Boot and Linux). As a result, I'm focusing my limited
> resources on the Wandboard rather than the Cubox.

Cubox-i has been merged in current mainline; so it may be good a recheck ;-)

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750