[PATCH V4 0/6] perf, amd: Enable AMD family 15h northbridge counters

[PATCH V4 0/6] perf, amd: Enable AMD family 15h northbridge counters

[Jacob Shin]

The following patchset enables 4 additional performance counters in
AMD family 15h processors that count northbridge events -- such as
number of DRAM accesses.

This patchset is based on previous work done by Robert Richter
<rric@kernel.org> :

https://lkml.org/lkml/2012/6/19/324

The main differences are:

* The northbridge counters are indexed contiguously right above the
  core performance counters.

* MSR address offset calculations are moved to architecture specific
  files.

* Interrups are set up to be delivered only to a single core.

V4:
* Moved interrupt core select set up back to event constraints
  function, sicne during ->hw_config time we do not yet know on which
  CPU the the event will run on.
* Tested on and made minor revisions to make sure that the patchset is
  compatible with upcoming AMD Family 16h processors, and will support
  core and NB counters without any further patches.

V3:
Addressed the following feedback/comments from Robert's review
* https://lkml.org/lkml/2012/11/16/484
* https://lkml.org/lkml/2012/11/26/162

V2:
Separate out Robert's patches, and add properly ordered certificate of
origins.

Jacob Shin (4):
  perf, amd: Use proper naming scheme for AMD bit field definitions
  perf, x86: Move MSR address offset calculation to architecture
    specific files
  perf, x86: Allow for architecture specific RDPMC indexes
  perf, amd: Enable northbridge performance counters on AMD family 15h

Robert Richter (2):
  perf, amd: Rework northbridge event constraints handler
  perf, amd: Generalize northbridge constraints code for family 15h

 arch/x86/include/asm/cpufeature.h    |    2 +
 arch/x86/include/asm/msr-index.h     |    2 +
 arch/x86/include/asm/perf_event.h    |   13 +-
 arch/x86/kernel/cpu/perf_event.c     |    2 +-
 arch/x86/kernel/cpu/perf_event.h     |   25 ++-
 arch/x86/kernel/cpu/perf_event_amd.c |  318 ++++++++++++++++++++++++++--------
 6 files changed, 268 insertions(+), 94 deletions(-)

-- 
1.7.9.5

[PATCH 1/6] perf, amd: Rework northbridge event constraints handler

[Jacob Shin]

From: Robert Richter <rric@kernel.org>

Code simplification. No functional changes.

Signed-off-by: Robert Richter <rric@kernel.org>
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
 arch/x86/kernel/cpu/perf_event_amd.c |   68 +++++++++++++---------------------
 1 file changed, 26 insertions(+), 42 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index c93bc4e..e7963c7 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -256,9 +256,8 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 {
 	struct hw_perf_event *hwc = &event->hw;
 	struct amd_nb *nb = cpuc->amd_nb;
-	struct perf_event *old = NULL;
-	int max = x86_pmu.num_counters;
-	int i, j, k = -1;
+	struct perf_event *old;
+	int idx, new = -1;
 
 	/*
 	 * if not NB event or no NB, then no constraints
@@ -276,48 +275,33 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 	 * because of successive calls to x86_schedule_events() from
 	 * hw_perf_group_sched_in() without hw_perf_enable()
 	 */
-	for (i = 0; i < max; i++) {
-		/*
-		 * keep track of first free slot
-		 */
-		if (k == -1 && !nb->owners[i])
-			k = i;
+	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
+		if (new == -1 || hwc->idx == idx)
+			/* assign free slot, prefer hwc->idx */
+			old = cmpxchg(nb->owners + idx, NULL, event);
+		else if (nb->owners[idx] == event)
+			/* event already present */
+			old = event;
+		else
+			continue;
+
+		if (old && old != event)
+			continue;
+
+		/* reassign to this slot */
+		if (new != -1)
+			cmpxchg(nb->owners + new, event, NULL);
+		new = idx;
 
 		/* already present, reuse */
-		if (nb->owners[i] == event)
-			goto done;
-	}
-	/*
-	 * not present, so grab a new slot
-	 * starting either at:
-	 */
-	if (hwc->idx != -1) {
-		/* previous assignment */
-		i = hwc->idx;
-	} else if (k != -1) {
-		/* start from free slot found */
-		i = k;
-	} else {
-		/*
-		 * event not found, no slot found in
-		 * first pass, try again from the
-		 * beginning
-		 */
-		i = 0;
-	}
-	j = i;
-	do {
-		old = cmpxchg(nb->owners+i, NULL, event);
-		if (!old)
+		if (old == event)
 			break;
-		if (++i == max)
-			i = 0;
-	} while (i != j);
-done:
-	if (!old)
-		return &nb->event_constraints[i];
-
-	return &emptyconstraint;
+	}
+
+	if (new == -1)
+		return &emptyconstraint;
+
+	return &nb->event_constraints[new];
 }
 
 static struct amd_nb *amd_alloc_nb(int cpu)
-- 
1.7.9.5

[PATCH 2/6] perf, amd: Generalize northbridge constraints code for family 15h

[Jacob Shin]

From: Robert Richter <rric@kernel.org>

Generalize northbridge constraints code for family 10h so that later
we can reuse the same code path with other AMD processor families that
have the same northbridge event constraints.

Signed-off-by: Robert Richter <rric@kernel.org>
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
 arch/x86/kernel/cpu/perf_event_amd.c |   43 ++++++++++++++++++++--------------
 1 file changed, 25 insertions(+), 18 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index e7963c7..9541fe5 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -188,20 +188,13 @@ static inline int amd_has_nb(struct cpu_hw_events *cpuc)
 	return nb && nb->nb_id != -1;
 }
 
-static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
-				      struct perf_event *event)
+static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
+					   struct perf_event *event)
 {
-	struct hw_perf_event *hwc = &event->hw;
 	struct amd_nb *nb = cpuc->amd_nb;
 	int i;
 
 	/*
-	 * only care about NB events
-	 */
-	if (!(amd_has_nb(cpuc) && amd_is_nb_event(hwc)))
-		return;
-
-	/*
 	 * need to scan whole list because event may not have
 	 * been assigned during scheduling
 	 *
@@ -247,12 +240,13 @@ static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
   *
   * Given that resources are allocated (cmpxchg), they must be
   * eventually freed for others to use. This is accomplished by
-  * calling amd_put_event_constraints().
+  * calling __amd_put_nb_event_constraints()
   *
   * Non NB events are not impacted by this restriction.
   */
 static struct event_constraint *
-amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
+__amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
+			       struct event_constraint *c)
 {
 	struct hw_perf_event *hwc = &event->hw;
 	struct amd_nb *nb = cpuc->amd_nb;
@@ -260,12 +254,6 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 	int idx, new = -1;
 
 	/*
-	 * if not NB event or no NB, then no constraints
-	 */
-	if (!(amd_has_nb(cpuc) && amd_is_nb_event(hwc)))
-		return &unconstrained;
-
-	/*
 	 * detect if already present, if so reuse
 	 *
 	 * cannot merge with actual allocation
@@ -275,7 +263,7 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 	 * because of successive calls to x86_schedule_events() from
 	 * hw_perf_group_sched_in() without hw_perf_enable()
 	 */
-	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
+	for_each_set_bit(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 		if (new == -1 || hwc->idx == idx)
 			/* assign free slot, prefer hwc->idx */
 			old = cmpxchg(nb->owners + idx, NULL, event);
@@ -391,6 +379,25 @@ static void amd_pmu_cpu_dead(int cpu)
 	}
 }
 
+static struct event_constraint *
+amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
+{
+	/*
+	 * if not NB event or no NB, then no constraints
+	 */
+	if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
+		return &unconstrained;
+
+	return __amd_get_nb_event_constraints(cpuc, event, &unconstrained);
+}
+
+static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
+				      struct perf_event *event)
+{
+	if (amd_has_nb(cpuc) && amd_is_nb_event(&event->hw))
+		__amd_put_nb_event_constraints(cpuc, event);
+}
+
 PMU_FORMAT_ATTR(event,	"config:0-7,32-35");
 PMU_FORMAT_ATTR(umask,	"config:8-15"	);
 PMU_FORMAT_ATTR(edge,	"config:18"	);
-- 
1.7.9.5

[PATCH 3/6] perf, amd: Use proper naming scheme for AMD bit field definitions

[Jacob Shin]

Update these AMD bit field names to be consistent with naming
convention followed by the rest of the file.

Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
 arch/x86/include/asm/perf_event.h    |    4 ++--
 arch/x86/kernel/cpu/perf_event_amd.c |    8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 4fabcdf..2234eaaec 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -29,8 +29,8 @@
 #define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
 #define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL
 
-#define AMD_PERFMON_EVENTSEL_GUESTONLY			(1ULL << 40)
-#define AMD_PERFMON_EVENTSEL_HOSTONLY			(1ULL << 41)
+#define AMD64_EVENTSEL_GUESTONLY			(1ULL << 40)
+#define AMD64_EVENTSEL_HOSTONLY				(1ULL << 41)
 
 #define AMD64_EVENTSEL_EVENT	\
 	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index 9541fe5..0c2cc51 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -156,9 +156,9 @@ static int amd_pmu_hw_config(struct perf_event *event)
 		event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
 				      ARCH_PERFMON_EVENTSEL_OS);
 	else if (event->attr.exclude_host)
-		event->hw.config |= AMD_PERFMON_EVENTSEL_GUESTONLY;
+		event->hw.config |= AMD64_EVENTSEL_GUESTONLY;
 	else if (event->attr.exclude_guest)
-		event->hw.config |= AMD_PERFMON_EVENTSEL_HOSTONLY;
+		event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
 
 	if (event->attr.type != PERF_TYPE_RAW)
 		return 0;
@@ -336,7 +336,7 @@ static void amd_pmu_cpu_starting(int cpu)
 	struct amd_nb *nb;
 	int i, nb_id;
 
-	cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
+	cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
 
 	if (boot_cpu_data.x86_max_cores < 2)
 		return;
@@ -669,7 +669,7 @@ void amd_pmu_disable_virt(void)
 	 * SVM is disabled the Guest-only bits still gets set and the counter
 	 * will not count anything.
 	 */
-	cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
+	cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
 
 	/* Reload all events */
 	x86_pmu_disable_all();
-- 
1.7.9.5

[PATCH 4/6] perf, x86: Move MSR address offset calculation to architecture specific files

[Jacob Shin]

Move counter index to MSR address offset calculation to architecture
specific files. This prepares the way for perf_event_amd to enable
counter addresses that are not contiguous -- for example AMD Family
15h processors have 6 core performance counters starting at 0xc0010200
and 4 northbridge performance counters starting at 0xc0010240.

Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
 arch/x86/kernel/cpu/perf_event.h     |   21 ++++-------------
 arch/x86/kernel/cpu/perf_event_amd.c |   42 ++++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 115c1ea..015826e 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -325,6 +325,7 @@ struct x86_pmu {
 	int		(*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 	unsigned	eventsel;
 	unsigned	perfctr;
+	int             (*addr_offset)(int index, int eventsel);
 	u64		(*event_map)(int);
 	int		max_events;
 	int		num_counters;
@@ -446,28 +447,16 @@ extern u64 __read_mostly hw_cache_extra_regs
 
 u64 x86_perf_event_update(struct perf_event *event);
 
-static inline int x86_pmu_addr_offset(int index)
-{
-	int offset;
-
-	/* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
-	alternative_io(ASM_NOP2,
-		       "shll $1, %%eax",
-		       X86_FEATURE_PERFCTR_CORE,
-		       "=a" (offset),
-		       "a"  (index));
-
-	return offset;
-}
-
 static inline unsigned int x86_pmu_config_addr(int index)
 {
-	return x86_pmu.eventsel + x86_pmu_addr_offset(index);
+	return x86_pmu.eventsel +
+		(x86_pmu.addr_offset ? x86_pmu.addr_offset(index, 1) : index);
 }
 
 static inline unsigned int x86_pmu_event_addr(int index)
 {
-	return x86_pmu.perfctr + x86_pmu_addr_offset(index);
+	return x86_pmu.perfctr +
+		(x86_pmu.addr_offset ? x86_pmu.addr_offset(index, 0) : index);
 }
 
 int x86_setup_perfctr(struct perf_event *event);
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index 0c2cc51..ef1df38 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -132,6 +132,47 @@ static u64 amd_pmu_event_map(int hw_event)
 	return amd_perfmon_event_map[hw_event];
 }
 
+/*
+ * Previously calculated offsets
+ */
+static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
+static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
+
+/*
+ * Legacy CPUs:
+ *   4 counters starting at 0xc0010000 each offset by 1
+ *
+ * CPUs with core performance counter extensions:
+ *   6 counters starting at 0xc0010200 each offset by 2
+ */
+static inline int amd_pmu_addr_offset(int index, int eventsel)
+{
+	int offset;
+
+	if (!index)
+		return index;
+
+	if (eventsel)
+		offset = event_offsets[index];
+	else
+		offset = count_offsets[index];
+
+	if (offset)
+		return offset;
+
+	if (!cpu_has_perfctr_core)
+		offset = index;
+	else
+		offset = index << 1;
+
+	if (eventsel)
+		event_offsets[index] = offset;
+	else
+		count_offsets[index] = offset;
+
+	return offset;
+}
+
 static int amd_pmu_hw_config(struct perf_event *event)
 {
 	int ret;
@@ -578,6 +619,7 @@ static __initconst const struct x86_pmu amd_pmu = {
 	.schedule_events	= x86_schedule_events,
 	.eventsel		= MSR_K7_EVNTSEL0,
 	.perfctr		= MSR_K7_PERFCTR0,
+	.addr_offset            = amd_pmu_addr_offset,
 	.event_map		= amd_pmu_event_map,
 	.max_events		= ARRAY_SIZE(amd_perfmon_event_map),
 	.num_counters		= AMD64_NUM_COUNTERS,
-- 
1.7.9.5

[PATCH 5/6] perf, x86: Allow for architecture specific RDPMC indexes

[Jacob Shin]

Similar to config_base and event_base, allow architecture specific
RDPMC ECX values.

Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
 arch/x86/kernel/cpu/perf_event.c     |    2 +-
 arch/x86/kernel/cpu/perf_event.h     |    6 ++++++
 arch/x86/kernel/cpu/perf_event_amd.c |    6 ++++++
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 4428fd1..b63982b 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -835,7 +835,7 @@ static inline void x86_assign_hw_event(struct perf_event *event,
 	} else {
 		hwc->config_base = x86_pmu_config_addr(hwc->idx);
 		hwc->event_base  = x86_pmu_event_addr(hwc->idx);
-		hwc->event_base_rdpmc = hwc->idx;
+		hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 	}
 }
 
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 015826e..4a26fb1 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -326,6 +326,7 @@ struct x86_pmu {
 	unsigned	eventsel;
 	unsigned	perfctr;
 	int             (*addr_offset)(int index, int eventsel);
+	int             (*rdpmc_index)(int index);
 	u64		(*event_map)(int);
 	int		max_events;
 	int		num_counters;
@@ -459,6 +460,11 @@ static inline unsigned int x86_pmu_event_addr(int index)
 		(x86_pmu.addr_offset ? x86_pmu.addr_offset(index, 0) : index);
 }
 
+static inline int x86_pmu_rdpmc_index(int index)
+{
+	return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
+}
+
 int x86_setup_perfctr(struct perf_event *event);
 
 int x86_pmu_hw_config(struct perf_event *event);
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index ef1df38..faf9072 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -173,6 +173,11 @@ static inline int amd_pmu_addr_offset(int index, int eventsel)
 	return offset;
 }
 
+static inline int amd_pmu_rdpmc_index(int index)
+{
+	return index;
+}
+
 static int amd_pmu_hw_config(struct perf_event *event)
 {
 	int ret;
@@ -620,6 +625,7 @@ static __initconst const struct x86_pmu amd_pmu = {
 	.eventsel		= MSR_K7_EVNTSEL0,
 	.perfctr		= MSR_K7_PERFCTR0,
 	.addr_offset            = amd_pmu_addr_offset,
+	.rdpmc_index		= amd_pmu_rdpmc_index,
 	.event_map		= amd_pmu_event_map,
 	.max_events		= ARRAY_SIZE(amd_perfmon_event_map),
 	.num_counters		= AMD64_NUM_COUNTERS,
-- 
1.7.9.5

[PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h

[Jacob Shin]

On AMD family 15h processors, there are 4 new performance counters
(in addition to 6 core performance counters) that can be used for
counting northbridge events (i.e. DRAM accesses). Their bit fields are
almost identical to the core performance counters. However, unlike the
core performance counters, these MSRs are shared between multiple
cores (that share the same northbridge). We will reuse the same code
path as existing family 10h northbridge event constraints handler
logic to enforce this sharing.

Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
 arch/x86/include/asm/cpufeature.h    |    2 +
 arch/x86/include/asm/msr-index.h     |    2 +
 arch/x86/include/asm/perf_event.h    |    9 ++
 arch/x86/kernel/cpu/perf_event_amd.c |  167 ++++++++++++++++++++++++++++++----
 4 files changed, 160 insertions(+), 20 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index c22a492..b4cd472 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -167,6 +167,7 @@
 #define X86_FEATURE_TBM		(6*32+21) /* trailing bit manipulations */
 #define X86_FEATURE_TOPOEXT	(6*32+22) /* topology extensions CPUID leafs */
 #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
+#define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
 
 /*
  * Auxiliary flags: Linux defined - For features scattered in various
@@ -308,6 +309,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_hypervisor	boot_cpu_has(X86_FEATURE_HYPERVISOR)
 #define cpu_has_pclmulqdq	boot_cpu_has(X86_FEATURE_PCLMULQDQ)
 #define cpu_has_perfctr_core	boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
+#define cpu_has_perfctr_nb	boot_cpu_has(X86_FEATURE_PERFCTR_NB)
 #define cpu_has_cx8		boot_cpu_has(X86_FEATURE_CX8)
 #define cpu_has_cx16		boot_cpu_has(X86_FEATURE_CX16)
 #define cpu_has_eager_fpu	boot_cpu_has(X86_FEATURE_EAGER_FPU)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e400cdb..736fbf6 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -157,6 +157,8 @@
 /* Fam 15h MSRs */
 #define MSR_F15H_PERF_CTL		0xc0010200
 #define MSR_F15H_PERF_CTR		0xc0010201
+#define MSR_F15H_NB_PERF_CTL		0xc0010240
+#define MSR_F15H_NB_PERF_CTR		0xc0010241
 
 /* Fam 10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 2234eaaec..57cb634 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -29,9 +29,14 @@
 #define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
 #define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL
 
+#define AMD64_EVENTSEL_INT_CORE_ENABLE			(1ULL << 36)
 #define AMD64_EVENTSEL_GUESTONLY			(1ULL << 40)
 #define AMD64_EVENTSEL_HOSTONLY				(1ULL << 41)
 
+#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT		37
+#define AMD64_EVENTSEL_INT_CORE_SEL_MASK		\
+	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
+
 #define AMD64_EVENTSEL_EVENT	\
 	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
 #define INTEL_ARCH_EVENT_MASK	\
@@ -46,8 +51,12 @@
 #define AMD64_RAW_EVENT_MASK		\
 	(X86_RAW_EVENT_MASK          |  \
 	 AMD64_EVENTSEL_EVENT)
+#define AMD64_RAW_EVENT_MASK_NB		\
+	(AMD64_EVENTSEL_EVENT        |  \
+	 ARCH_PERFMON_EVENTSEL_UMASK)
 #define AMD64_NUM_COUNTERS				4
 #define AMD64_NUM_COUNTERS_CORE				6
+#define AMD64_NUM_COUNTERS_NB				4
 
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index faf9072..1a80e05 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -132,11 +132,14 @@ static u64 amd_pmu_event_map(int hw_event)
 	return amd_perfmon_event_map[hw_event];
 }
 
+static struct event_constraint *amd_nb_event_constraint;
+
 /*
  * Previously calculated offsets
  */
 static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
 static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
+static unsigned int rdpmc_indexes[X86_PMC_IDX_MAX] __read_mostly;
 
 /*
  * Legacy CPUs:
@@ -144,10 +147,14 @@ static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
  *
  * CPUs with core performance counter extensions:
  *   6 counters starting at 0xc0010200 each offset by 2
+ *
+ * CPUs with north bridge performance counter extensions:
+ *   4 additional counters starting at 0xc0010240 each offset by 2
+ *   (indexed right above either one of the above core counters)
  */
 static inline int amd_pmu_addr_offset(int index, int eventsel)
 {
-	int offset;
+	int offset, first, base;
 
 	if (!index)
 		return index;
@@ -160,7 +167,23 @@ static inline int amd_pmu_addr_offset(int index, int eventsel)
 	if (offset)
 		return offset;
 
-	if (!cpu_has_perfctr_core)
+	if (amd_nb_event_constraint &&
+	    test_bit(index, amd_nb_event_constraint->idxmsk)) {
+		/*
+		 * calculate the offset of NB counters with respect to
+		 * base eventsel or perfctr
+		 */
+
+		first = find_first_bit(amd_nb_event_constraint->idxmsk,
+				       X86_PMC_IDX_MAX);
+
+		if (eventsel)
+			base = MSR_F15H_NB_PERF_CTL - x86_pmu.eventsel;
+		else
+			base = MSR_F15H_NB_PERF_CTR - x86_pmu.perfctr;
+
+		offset = base + ((index - first) << 1);
+	} else if (!cpu_has_perfctr_core)
 		offset = index;
 	else
 		offset = index << 1;
@@ -175,24 +198,36 @@ static inline int amd_pmu_addr_offset(int index, int eventsel)
 
 static inline int amd_pmu_rdpmc_index(int index)
 {
-	return index;
-}
+	int ret, first;
 
-static int amd_pmu_hw_config(struct perf_event *event)
-{
-	int ret;
+	if (!index)
+		return index;
 
-	/* pass precise event sampling to ibs: */
-	if (event->attr.precise_ip && get_ibs_caps())
-		return -ENOENT;
+	ret = rdpmc_indexes[index];
 
-	ret = x86_pmu_hw_config(event);
 	if (ret)
 		return ret;
 
-	if (has_branch_stack(event))
-		return -EOPNOTSUPP;
+	if (amd_nb_event_constraint &&
+	    test_bit(index, amd_nb_event_constraint->idxmsk)) {
+		/*
+		 * according to the mnual, ECX value of the NB counters is
+		 * the index of the NB counter (0, 1, 2 or 3) plus 6
+		 */
+
+		first = find_first_bit(amd_nb_event_constraint->idxmsk,
+				       X86_PMC_IDX_MAX);
+		ret = index - first + 6;
+	} else
+		ret = index;
+
+	rdpmc_indexes[index] = ret;
 
+	return ret;
+}
+
+static int amd_core_hw_config(struct perf_event *event)
+{
 	if (event->attr.exclude_host && event->attr.exclude_guest)
 		/*
 		 * When HO == GO == 1 the hardware treats that as GO == HO == 0
@@ -206,10 +241,29 @@ static int amd_pmu_hw_config(struct perf_event *event)
 	else if (event->attr.exclude_guest)
 		event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
 
-	if (event->attr.type != PERF_TYPE_RAW)
-		return 0;
+	return 0;
+}
 
-	event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
+/*
+ * NB counters do not support the following event select bits:
+ *   Host/Guest only
+ *   Counter mask
+ *   Invert counter mask
+ *   Edge detect
+ *   OS/User mode
+ */
+static int amd_nb_hw_config(struct perf_event *event)
+{
+	if (event->attr.exclude_user || event->attr.exclude_kernel ||
+	    event->attr.exclude_host || event->attr.exclude_guest)
+		return -EINVAL;
+
+	event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
+			      ARCH_PERFMON_EVENTSEL_OS);
+
+	if (event->hw.config & ~(AMD64_RAW_EVENT_MASK_NB |
+				 ARCH_PERFMON_EVENTSEL_INT))
+		return -EINVAL;
 
 	return 0;
 }
@@ -227,6 +281,11 @@ static inline int amd_is_nb_event(struct hw_perf_event *hwc)
 	return (hwc->config & 0xe0) == 0xe0;
 }
 
+static inline int amd_is_perfctr_nb_event(struct hw_perf_event *hwc)
+{
+	return amd_nb_event_constraint && amd_is_nb_event(hwc);
+}
+
 static inline int amd_has_nb(struct cpu_hw_events *cpuc)
 {
 	struct amd_nb *nb = cpuc->amd_nb;
@@ -234,6 +293,30 @@ static inline int amd_has_nb(struct cpu_hw_events *cpuc)
 	return nb && nb->nb_id != -1;
 }
 
+static int amd_pmu_hw_config(struct perf_event *event)
+{
+	int ret;
+
+	/* pass precise event sampling to ibs: */
+	if (event->attr.precise_ip && get_ibs_caps())
+		return -ENOENT;
+
+	if (has_branch_stack(event))
+		return -EOPNOTSUPP;
+
+	ret = x86_pmu_hw_config(event);
+	if (ret)
+		return ret;
+
+	if (event->attr.type == PERF_TYPE_RAW)
+		event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
+
+	if (amd_is_perfctr_nb_event(&event->hw))
+		return amd_nb_hw_config(event);
+
+	return amd_core_hw_config(event);
+}
+
 static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
 					   struct perf_event *event)
 {
@@ -254,6 +337,19 @@ static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
 	}
 }
 
+static void amd_nb_interrupt_hw_config(struct hw_perf_event *hwc)
+{
+	int core_id = cpu_data(smp_processor_id()).cpu_core_id;
+
+	/* deliver interrupts only to this core */
+	if (hwc->config & ARCH_PERFMON_EVENTSEL_INT) {
+		hwc->config |= AMD64_EVENTSEL_INT_CORE_ENABLE;
+		hwc->config &= ~AMD64_EVENTSEL_INT_CORE_SEL_MASK;
+		hwc->config |= (u64)(core_id) <<
+			AMD64_EVENTSEL_INT_CORE_SEL_SHIFT;
+	}
+}
+
  /*
   * AMD64 NorthBridge events need special treatment because
   * counter access needs to be synchronized across all cores
@@ -299,6 +395,12 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
 	struct perf_event *old;
 	int idx, new = -1;
 
+	if (!c)
+		c = &unconstrained;
+
+	if (cpuc->is_fake)
+		return c;
+
 	/*
 	 * detect if already present, if so reuse
 	 *
@@ -335,6 +437,9 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
 	if (new == -1)
 		return &emptyconstraint;
 
+	if (amd_is_perfctr_nb_event(hwc))
+		amd_nb_interrupt_hw_config(hwc);
+
 	return &nb->event_constraints[new];
 }
 
@@ -434,7 +539,8 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 	if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
 		return &unconstrained;
 
-	return __amd_get_nb_event_constraints(cpuc, event, &unconstrained);
+	return __amd_get_nb_event_constraints(cpuc, event,
+					      amd_nb_event_constraint);
 }
 
 static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
@@ -533,6 +639,9 @@ static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09,
 static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
 static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
 
+static struct event_constraint amd_NBPMC96 = EVENT_CONSTRAINT(0, 0x3C0, 0);
+static struct event_constraint amd_NBPMC74 = EVENT_CONSTRAINT(0, 0xF0, 0);
+
 static struct event_constraint *
 amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
 {
@@ -598,8 +707,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev
 			return &amd_f15_PMC20;
 		}
 	case AMD_EVENT_NB:
-		/* not yet implemented */
-		return &emptyconstraint;
+		return __amd_get_nb_event_constraints(cpuc, event,
+						      amd_nb_event_constraint);
 	default:
 		return &emptyconstraint;
 	}
@@ -647,7 +756,7 @@ static __initconst const struct x86_pmu amd_pmu = {
 
 static int setup_event_constraints(void)
 {
-	if (boot_cpu_data.x86 >= 0x15)
+	if (boot_cpu_data.x86 == 0x15)
 		x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
 	return 0;
 }
@@ -677,6 +786,23 @@ static int setup_perfctr_core(void)
 	return 0;
 }
 
+static int setup_perfctr_nb(void)
+{
+	if (!cpu_has_perfctr_nb)
+		return -ENODEV;
+
+	x86_pmu.num_counters += AMD64_NUM_COUNTERS_NB;
+
+	if (cpu_has_perfctr_core)
+		amd_nb_event_constraint = &amd_NBPMC96;
+	else
+		amd_nb_event_constraint = &amd_NBPMC74;
+
+	printk(KERN_INFO "perf: AMD northbridge performance counters detected\n");
+
+	return 0;
+}
+
 __init int amd_pmu_init(void)
 {
 	/* Performance-monitoring supported from K7 and later: */
@@ -687,6 +813,7 @@ __init int amd_pmu_init(void)
 
 	setup_event_constraints();
 	setup_perfctr_core();
+	setup_perfctr_nb();
 
 	/* Events are common for all AMDs */
 	memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
-- 
1.7.9.5

Re: [PATCH V4 0/6] perf, amd: Enable AMD family 15h northbridge counters

[Jacob Shin]

On Wed, Dec 05, 2012 at 05:04:12PM -0600, Jacob Shin wrote:
> The following patchset enables 4 additional performance counters in
> AMD family 15h processors that count northbridge events -- such as
> number of DRAM accesses.
> 
> This patchset is based on previous work done by Robert Richter
> <rric@kernel.org> :
> 
> https://lkml.org/lkml/2012/6/19/324
> 
> The main differences are:
> 
> * The northbridge counters are indexed contiguously right above the
>   core performance counters.
> 
> * MSR address offset calculations are moved to architecture specific
>   files.
> 
> * Interrups are set up to be delivered only to a single core.
> 
> V4:
> * Moved interrupt core select set up back to event constraints
>   function, sicne during ->hw_config time we do not yet know on which
>   CPU the the event will run on.
> * Tested on and made minor revisions to make sure that the patchset is
>   compatible with upcoming AMD Family 16h processors, and will support
>   core and NB counters without any further patches.
> 
> V3:
> Addressed the following feedback/comments from Robert's review
> * https://lkml.org/lkml/2012/11/16/484
> * https://lkml.org/lkml/2012/11/26/162
> 
> V2:
> Separate out Robert's patches, and add properly ordered certificate of
> origins.
> 
> Jacob Shin (4):
>   perf, amd: Use proper naming scheme for AMD bit field definitions
>   perf, x86: Move MSR address offset calculation to architecture
>     specific files
>   perf, x86: Allow for architecture specific RDPMC indexes
>   perf, amd: Enable northbridge performance counters on AMD family 15h
> 
> Robert Richter (2):
>   perf, amd: Rework northbridge event constraints handler
>   perf, amd: Generalize northbridge constraints code for family 15h
> 
>  arch/x86/include/asm/cpufeature.h    |    2 +
>  arch/x86/include/asm/msr-index.h     |    2 +
>  arch/x86/include/asm/perf_event.h    |   13 +-
>  arch/x86/kernel/cpu/perf_event.c     |    2 +-
>  arch/x86/kernel/cpu/perf_event.h     |   25 ++-
>  arch/x86/kernel/cpu/perf_event_amd.c |  318 ++++++++++++++++++++++++++--------
>  6 files changed, 268 insertions(+), 94 deletions(-)
> 
> -- 

Ping .. ? any comments/feedback ? If things look okay, could you
please commit to tip perf/core ?

Thank you,

-Jacob

Re: [PATCH V4 0/6] perf, amd: Enable AMD family 15h northbridge counters

[Jacob Shin]

On Mon, Dec 10, 2012 at 12:51:00PM -0600, Jacob Shin wrote:
> On Wed, Dec 05, 2012 at 05:04:12PM -0600, Jacob Shin wrote:
> > The following patchset enables 4 additional performance counters in
> > AMD family 15h processors that count northbridge events -- such as
> > number of DRAM accesses.
> > 
> > This patchset is based on previous work done by Robert Richter
> > <rric@kernel.org> :
> > 
> > https://lkml.org/lkml/2012/6/19/324
> > 
> > The main differences are:
> > 
> > * The northbridge counters are indexed contiguously right above the
> >   core performance counters.
> > 
> > * MSR address offset calculations are moved to architecture specific
> >   files.
> > 
> > * Interrups are set up to be delivered only to a single core.
> > 
> > V4:
> > * Moved interrupt core select set up back to event constraints
> >   function, sicne during ->hw_config time we do not yet know on which
> >   CPU the the event will run on.
> > * Tested on and made minor revisions to make sure that the patchset is
> >   compatible with upcoming AMD Family 16h processors, and will support
> >   core and NB counters without any further patches.
> > 
> > V3:
> > Addressed the following feedback/comments from Robert's review
> > * https://lkml.org/lkml/2012/11/16/484
> > * https://lkml.org/lkml/2012/11/26/162
> > 
> > V2:
> > Separate out Robert's patches, and add properly ordered certificate of
> > origins.
> > 
> > Jacob Shin (4):
> >   perf, amd: Use proper naming scheme for AMD bit field definitions
> >   perf, x86: Move MSR address offset calculation to architecture
> >     specific files
> >   perf, x86: Allow for architecture specific RDPMC indexes
> >   perf, amd: Enable northbridge performance counters on AMD family 15h
> > 
> > Robert Richter (2):
> >   perf, amd: Rework northbridge event constraints handler
> >   perf, amd: Generalize northbridge constraints code for family 15h
> > 
> >  arch/x86/include/asm/cpufeature.h    |    2 +
> >  arch/x86/include/asm/msr-index.h     |    2 +
> >  arch/x86/include/asm/perf_event.h    |   13 +-
> >  arch/x86/kernel/cpu/perf_event.c     |    2 +-
> >  arch/x86/kernel/cpu/perf_event.h     |   25 ++-
> >  arch/x86/kernel/cpu/perf_event_amd.c |  318 ++++++++++++++++++++++++++--------
> >  6 files changed, 268 insertions(+), 94 deletions(-)
> > 
> > -- 
> 
> Ping .. ? any comments/feedback ? If things look okay, could you
> please commit to tip perf/core ?

Ping #2 .. ?

Thanks!

-Jacob

Re: [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h

[Jacob Shin]

On Mon, Feb 11, 2013 at 10:26:09AM -0600, Jacob Shin wrote:
> On Fri, Feb 08, 2013 at 12:16:28PM +0100, Stephane Eranian wrote:
> > On Wed, Feb 6, 2013 at 6:26 PM, Jacob Shin <jacob.shin@amd.com> wrote:
> > > On AMD family 15h processors, there are 4 new performance counters
> > > (in addition to 6 core performance counters) that can be used for
> > > counting northbridge events (i.e. DRAM accesses). Their bit fields are
> > > almost identical to the core performance counters. However, unlike the
> > > core performance counters, these MSRs are shared between multiple
> > > cores (that share the same northbridge). We will reuse the same code
> > > path as existing family 10h northbridge event constraints handler
> > > logic to enforce this sharing.
> > >
> > > Signed-off-by: Jacob Shin <jacob.shin@amd.com>
> > 
> > Works for me.
> > 
> > I simply regret that the design decision ties uncore with core
> > even though hardware-wise they are separate. If I recall the earlier
> > discussion the motivation was to limit code duplication. That's true
> > but that's at the expense of isolation. For instance, now if the core
> > PMU is overcommitted, but not the uncore, then uncore still goes
> > thru event rescheduling for nothing.
> > 
> > But what matters at this point, is that there is coverage
> > for uncore, so we can get some bandwidth measurements
> > out. So i recommend we merge this in. Thanks.
> > 
> > Acked-by: Stephane Eranian <eranian@google.com>
> 
> Stephane, thank you for your time reviewing/testing the patchset.
> 
> Ingo, could you please commit this patch 6/6 to tip?

Hi Ingo, just ping'ing again .. Since we now have an ACK from Stephane
could you please commit this last one to tip ? (just want to get it in
before the merge window opens)

Thanks for you time,

-Jacob

> 
> Thank you,
> 
> -Jacob
> 
> > 
> > > ---
> > >  arch/x86/include/asm/cpufeature.h     |    2 +
> > >  arch/x86/include/asm/perf_event.h     |    9 ++
> > >  arch/x86/include/uapi/asm/msr-index.h |    2 +
> > >  arch/x86/kernel/cpu/perf_event_amd.c  |  171 +++++++++++++++++++++++++++++----
> > >  4 files changed, 164 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> > > index 2d9075e..93fe929 100644
> > > --- a/arch/x86/include/asm/cpufeature.h
> > > +++ b/arch/x86/include/asm/cpufeature.h
> > > @@ -167,6 +167,7 @@
> > >  #define X86_FEATURE_TBM                (6*32+21) /* trailing bit manipulations */
> > >  #define X86_FEATURE_TOPOEXT    (6*32+22) /* topology extensions CPUID leafs */
> > >  #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
> > > +#define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
> > >
> > >  /*
> > >   * Auxiliary flags: Linux defined - For features scattered in various
> > > @@ -309,6 +310,7 @@ extern const char * const x86_power_flags[32];
> > >  #define cpu_has_hypervisor     boot_cpu_has(X86_FEATURE_HYPERVISOR)
> > >  #define cpu_has_pclmulqdq      boot_cpu_has(X86_FEATURE_PCLMULQDQ)
> > >  #define cpu_has_perfctr_core   boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
> > > +#define cpu_has_perfctr_nb     boot_cpu_has(X86_FEATURE_PERFCTR_NB)
> > >  #define cpu_has_cx8            boot_cpu_has(X86_FEATURE_CX8)
> > >  #define cpu_has_cx16           boot_cpu_has(X86_FEATURE_CX16)
> > >  #define cpu_has_eager_fpu      boot_cpu_has(X86_FEATURE_EAGER_FPU)
> > > diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> > > index 2234eaaec..57cb634 100644
> > > --- a/arch/x86/include/asm/perf_event.h
> > > +++ b/arch/x86/include/asm/perf_event.h
> > > @@ -29,9 +29,14 @@
> > >  #define ARCH_PERFMON_EVENTSEL_INV                      (1ULL << 23)
> > >  #define ARCH_PERFMON_EVENTSEL_CMASK                    0xFF000000ULL
> > >
> > > +#define AMD64_EVENTSEL_INT_CORE_ENABLE                 (1ULL << 36)
> > >  #define AMD64_EVENTSEL_GUESTONLY                       (1ULL << 40)
> > >  #define AMD64_EVENTSEL_HOSTONLY                                (1ULL << 41)
> > >
> > > +#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT              37
> > > +#define AMD64_EVENTSEL_INT_CORE_SEL_MASK               \
> > > +       (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
> > > +
> > >  #define AMD64_EVENTSEL_EVENT   \
> > >         (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
> > >  #define INTEL_ARCH_EVENT_MASK  \
> > > @@ -46,8 +51,12 @@
> > >  #define AMD64_RAW_EVENT_MASK           \
> > >         (X86_RAW_EVENT_MASK          |  \
> > >          AMD64_EVENTSEL_EVENT)
> > > +#define AMD64_RAW_EVENT_MASK_NB                \
> > > +       (AMD64_EVENTSEL_EVENT        |  \
> > > +        ARCH_PERFMON_EVENTSEL_UMASK)
> > >  #define AMD64_NUM_COUNTERS                             4
> > >  #define AMD64_NUM_COUNTERS_CORE                                6
> > > +#define AMD64_NUM_COUNTERS_NB                          4
> > >
> > >  #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL          0x3c
> > >  #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK                (0x00 << 8)
> > > diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
> > > index 1031604..27c05d2 100644
> > > --- a/arch/x86/include/uapi/asm/msr-index.h
> > > +++ b/arch/x86/include/uapi/asm/msr-index.h
> > > @@ -195,6 +195,8 @@
> > >  /* Fam 15h MSRs */
> > >  #define MSR_F15H_PERF_CTL              0xc0010200
> > >  #define MSR_F15H_PERF_CTR              0xc0010201
> > > +#define MSR_F15H_NB_PERF_CTL           0xc0010240
> > > +#define MSR_F15H_NB_PERF_CTR           0xc0010241
> > >
> > >  /* Fam 10h MSRs */
> > >  #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
> > > diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
> > > index 05462f0..dfdab42 100644
> > > --- a/arch/x86/kernel/cpu/perf_event_amd.c
> > > +++ b/arch/x86/kernel/cpu/perf_event_amd.c
> > > @@ -132,11 +132,14 @@ static u64 amd_pmu_event_map(int hw_event)
> > >         return amd_perfmon_event_map[hw_event];
> > >  }
> > >
> > > +static struct event_constraint *amd_nb_event_constraint;
> > > +
> > >  /*
> > >   * Previously calculated offsets
> > >   */
> > >  static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
> > >  static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
> > > +static unsigned int rdpmc_indexes[X86_PMC_IDX_MAX] __read_mostly;
> > >
> > >  /*
> > >   * Legacy CPUs:
> > > @@ -144,10 +147,14 @@ static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
> > >   *
> > >   * CPUs with core performance counter extensions:
> > >   *   6 counters starting at 0xc0010200 each offset by 2
> > > + *
> > > + * CPUs with north bridge performance counter extensions:
> > > + *   4 additional counters starting at 0xc0010240 each offset by 2
> > > + *   (indexed right above either one of the above core counters)
> > >   */
> > >  static inline int amd_pmu_addr_offset(int index, bool eventsel)
> > >  {
> > > -       int offset;
> > > +       int offset, first, base;
> > >
> > >         if (!index)
> > >                 return index;
> > > @@ -160,7 +167,23 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
> > >         if (offset)
> > >                 return offset;
> > >
> > > -       if (!cpu_has_perfctr_core)
> > > +       if (amd_nb_event_constraint &&
> > > +           test_bit(index, amd_nb_event_constraint->idxmsk)) {
> > > +               /*
> > > +                * calculate the offset of NB counters with respect to
> > > +                * base eventsel or perfctr
> > > +                */
> > > +
> > > +               first = find_first_bit(amd_nb_event_constraint->idxmsk,
> > > +                                      X86_PMC_IDX_MAX);
> > > +
> > > +               if (eventsel)
> > > +                       base = MSR_F15H_NB_PERF_CTL - x86_pmu.eventsel;
> > > +               else
> > > +                       base = MSR_F15H_NB_PERF_CTR - x86_pmu.perfctr;
> > > +
> > > +               offset = base + ((index - first) << 1);
> > > +       } else if (!cpu_has_perfctr_core)
> > >                 offset = index;
> > >         else
> > >                 offset = index << 1;
> > > @@ -175,24 +198,36 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
> > >
> > >  static inline int amd_pmu_rdpmc_index(int index)
> > >  {
> > > -       return index;
> > > -}
> > > +       int ret, first;
> > >
> > > -static int amd_pmu_hw_config(struct perf_event *event)
> > > -{
> > > -       int ret;
> > > +       if (!index)
> > > +               return index;
> > >
> > > -       /* pass precise event sampling to ibs: */
> > > -       if (event->attr.precise_ip && get_ibs_caps())
> > > -               return -ENOENT;
> > > +       ret = rdpmc_indexes[index];
> > >
> > > -       ret = x86_pmu_hw_config(event);
> > >         if (ret)
> > >                 return ret;
> > >
> > > -       if (has_branch_stack(event))
> > > -               return -EOPNOTSUPP;
> > > +       if (amd_nb_event_constraint &&
> > > +           test_bit(index, amd_nb_event_constraint->idxmsk)) {
> > > +               /*
> > > +                * according to the mnual, ECX value of the NB counters is
> > > +                * the index of the NB counter (0, 1, 2 or 3) plus 6
> > > +                */
> > > +
> > > +               first = find_first_bit(amd_nb_event_constraint->idxmsk,
> > > +                                      X86_PMC_IDX_MAX);
> > > +               ret = index - first + 6;
> > > +       } else
> > > +               ret = index;
> > > +
> > > +       rdpmc_indexes[index] = ret;
> > >
> > > +       return ret;
> > > +}
> > > +
> > > +static int amd_core_hw_config(struct perf_event *event)
> > > +{
> > >         if (event->attr.exclude_host && event->attr.exclude_guest)
> > >                 /*
> > >                  * When HO == GO == 1 the hardware treats that as GO == HO == 0
> > > @@ -206,10 +241,33 @@ static int amd_pmu_hw_config(struct perf_event *event)
> > >         else if (event->attr.exclude_guest)
> > >                 event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
> > >
> > > -       if (event->attr.type != PERF_TYPE_RAW)
> > > -               return 0;
> > > +       return 0;
> > > +}
> > >
> > > -       event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
> > > +/*
> > > + * NB counters do not support the following event select bits:
> > > + *   Host/Guest only
> > > + *   Counter mask
> > > + *   Invert counter mask
> > > + *   Edge detect
> > > + *   OS/User mode
> > > + */
> > > +static int amd_nb_hw_config(struct perf_event *event)
> > > +{
> > > +       /* for NB, we only allow system wide counting mode */
> > > +       if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
> > > +               return -EINVAL;
> > > +
> > > +       if (event->attr.exclude_user || event->attr.exclude_kernel ||
> > > +           event->attr.exclude_host || event->attr.exclude_guest)
> > > +               return -EINVAL;
> > > +
> > > +       event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
> > > +                             ARCH_PERFMON_EVENTSEL_OS);
> > > +
> > > +       if (event->hw.config & ~(AMD64_RAW_EVENT_MASK_NB |
> > > +                                ARCH_PERFMON_EVENTSEL_INT))
> > > +               return -EINVAL;
> > >
> > >         return 0;
> > >  }
> > > @@ -227,6 +285,11 @@ static inline int amd_is_nb_event(struct hw_perf_event *hwc)
> > >         return (hwc->config & 0xe0) == 0xe0;
> > >  }
> > >
> > > +static inline int amd_is_perfctr_nb_event(struct hw_perf_event *hwc)
> > > +{
> > > +       return amd_nb_event_constraint && amd_is_nb_event(hwc);
> > > +}
> > > +
> > >  static inline int amd_has_nb(struct cpu_hw_events *cpuc)
> > >  {
> > >         struct amd_nb *nb = cpuc->amd_nb;
> > > @@ -234,6 +297,30 @@ static inline int amd_has_nb(struct cpu_hw_events *cpuc)
> > >         return nb && nb->nb_id != -1;
> > >  }
> > >
> > > +static int amd_pmu_hw_config(struct perf_event *event)
> > > +{
> > > +       int ret;
> > > +
> > > +       /* pass precise event sampling to ibs: */
> > > +       if (event->attr.precise_ip && get_ibs_caps())
> > > +               return -ENOENT;
> > > +
> > > +       if (has_branch_stack(event))
> > > +               return -EOPNOTSUPP;
> > > +
> > > +       ret = x86_pmu_hw_config(event);
> > > +       if (ret)
> > > +               return ret;
> > > +
> > > +       if (event->attr.type == PERF_TYPE_RAW)
> > > +               event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
> > > +
> > > +       if (amd_is_perfctr_nb_event(&event->hw))
> > > +               return amd_nb_hw_config(event);
> > > +
> > > +       return amd_core_hw_config(event);
> > > +}
> > > +
> > >  static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
> > >                                            struct perf_event *event)
> > >  {
> > > @@ -254,6 +341,19 @@ static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
> > >         }
> > >  }
> > >
> > > +static void amd_nb_interrupt_hw_config(struct hw_perf_event *hwc)
> > > +{
> > > +       int core_id = cpu_data(smp_processor_id()).cpu_core_id;
> > > +
> > > +       /* deliver interrupts only to this core */
> > > +       if (hwc->config & ARCH_PERFMON_EVENTSEL_INT) {
> > > +               hwc->config |= AMD64_EVENTSEL_INT_CORE_ENABLE;
> > > +               hwc->config &= ~AMD64_EVENTSEL_INT_CORE_SEL_MASK;
> > > +               hwc->config |= (u64)(core_id) <<
> > > +                       AMD64_EVENTSEL_INT_CORE_SEL_SHIFT;
> > > +       }
> > > +}
> > > +
> > >   /*
> > >    * AMD64 NorthBridge events need special treatment because
> > >    * counter access needs to be synchronized across all cores
> > > @@ -299,6 +399,12 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
> > >         struct perf_event *old;
> > >         int idx, new = -1;
> > >
> > > +       if (!c)
> > > +               c = &unconstrained;
> > > +
> > > +       if (cpuc->is_fake)
> > > +               return c;
> > > +
> > >         /*
> > >          * detect if already present, if so reuse
> > >          *
> > > @@ -335,6 +441,9 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
> > >         if (new == -1)
> > >                 return &emptyconstraint;
> > >
> > > +       if (amd_is_perfctr_nb_event(hwc))
> > > +               amd_nb_interrupt_hw_config(hwc);
> > > +
> > >         return &nb->event_constraints[new];
> > >  }
> > >
> > > @@ -434,7 +543,8 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
> > >         if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
> > >                 return &unconstrained;
> > >
> > > -       return __amd_get_nb_event_constraints(cpuc, event, &unconstrained);
> > > +       return __amd_get_nb_event_constraints(cpuc, event,
> > > +                                             amd_nb_event_constraint);
> > >  }
> > >
> > >  static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
> > > @@ -533,6 +643,9 @@ static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09,
> > >  static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
> > >  static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
> > >
> > > +static struct event_constraint amd_NBPMC96 = EVENT_CONSTRAINT(0, 0x3C0, 0);
> > > +static struct event_constraint amd_NBPMC74 = EVENT_CONSTRAINT(0, 0xF0, 0);
> > > +
> > >  static struct event_constraint *
> > >  amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
> > >  {
> > > @@ -598,8 +711,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev
> > >                         return &amd_f15_PMC20;
> > >                 }
> > >         case AMD_EVENT_NB:
> > > -               /* not yet implemented */
> > > -               return &emptyconstraint;
> > > +               return __amd_get_nb_event_constraints(cpuc, event,
> > > +                                                     amd_nb_event_constraint);
> > >         default:
> > >                 return &emptyconstraint;
> > >         }
> > > @@ -647,7 +760,7 @@ static __initconst const struct x86_pmu amd_pmu = {
> > >
> > >  static int setup_event_constraints(void)
> > >  {
> > > -       if (boot_cpu_data.x86 >= 0x15)
> > > +       if (boot_cpu_data.x86 == 0x15)
> > >                 x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
> > >         return 0;
> > >  }
> > > @@ -677,6 +790,23 @@ static int setup_perfctr_core(void)
> > >         return 0;
> > >  }
> > >
> > > +static int setup_perfctr_nb(void)
> > > +{
> > > +       if (!cpu_has_perfctr_nb)
> > > +               return -ENODEV;
> > > +
> > > +       x86_pmu.num_counters += AMD64_NUM_COUNTERS_NB;
> > > +
> > > +       if (cpu_has_perfctr_core)
> > > +               amd_nb_event_constraint = &amd_NBPMC96;
> > > +       else
> > > +               amd_nb_event_constraint = &amd_NBPMC74;
> > > +
> > > +       printk(KERN_INFO "perf: AMD northbridge performance counters detected\n");
> > > +
> > > +       return 0;
> > > +}
> > > +
> > >  __init int amd_pmu_init(void)
> > >  {
> > >         /* Performance-monitoring supported from K7 and later: */
> > > @@ -687,6 +817,7 @@ __init int amd_pmu_init(void)
> > >
> > >         setup_event_constraints();
> > >         setup_perfctr_core();
> > > +       setup_perfctr_nb();
> > >
> > >         /* Events are common for all AMDs */
> > >         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
> > > --
> > > 1.7.9.5
> > >
> > >
> > 

Re: [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h

[Jacob Shin]

On Fri, Feb 08, 2013 at 12:16:28PM +0100, Stephane Eranian wrote:
> On Wed, Feb 6, 2013 at 6:26 PM, Jacob Shin <jacob.shin@amd.com> wrote:
> > On AMD family 15h processors, there are 4 new performance counters
> > (in addition to 6 core performance counters) that can be used for
> > counting northbridge events (i.e. DRAM accesses). Their bit fields are
> > almost identical to the core performance counters. However, unlike the
> > core performance counters, these MSRs are shared between multiple
> > cores (that share the same northbridge). We will reuse the same code
> > path as existing family 10h northbridge event constraints handler
> > logic to enforce this sharing.
> >
> > Signed-off-by: Jacob Shin <jacob.shin@amd.com>
> 
> Works for me.
> 
> I simply regret that the design decision ties uncore with core
> even though hardware-wise they are separate. If I recall the earlier
> discussion the motivation was to limit code duplication. That's true
> but that's at the expense of isolation. For instance, now if the core
> PMU is overcommitted, but not the uncore, then uncore still goes
> thru event rescheduling for nothing.
> 
> But what matters at this point, is that there is coverage
> for uncore, so we can get some bandwidth measurements
> out. So i recommend we merge this in. Thanks.
> 
> Acked-by: Stephane Eranian <eranian@google.com>

Stephane, thank you for your time reviewing/testing the patchset.

Ingo, could you please commit this patch 6/6 to tip?

Thank you,

-Jacob

> 
> > ---
> >  arch/x86/include/asm/cpufeature.h     |    2 +
> >  arch/x86/include/asm/perf_event.h     |    9 ++
> >  arch/x86/include/uapi/asm/msr-index.h |    2 +
> >  arch/x86/kernel/cpu/perf_event_amd.c  |  171 +++++++++++++++++++++++++++++----
> >  4 files changed, 164 insertions(+), 20 deletions(-)
> >
> > diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> > index 2d9075e..93fe929 100644
> > --- a/arch/x86/include/asm/cpufeature.h
> > +++ b/arch/x86/include/asm/cpufeature.h
> > @@ -167,6 +167,7 @@
> >  #define X86_FEATURE_TBM                (6*32+21) /* trailing bit manipulations */
> >  #define X86_FEATURE_TOPOEXT    (6*32+22) /* topology extensions CPUID leafs */
> >  #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
> > +#define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
> >
> >  /*
> >   * Auxiliary flags: Linux defined - For features scattered in various
> > @@ -309,6 +310,7 @@ extern const char * const x86_power_flags[32];
> >  #define cpu_has_hypervisor     boot_cpu_has(X86_FEATURE_HYPERVISOR)
> >  #define cpu_has_pclmulqdq      boot_cpu_has(X86_FEATURE_PCLMULQDQ)
> >  #define cpu_has_perfctr_core   boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
> > +#define cpu_has_perfctr_nb     boot_cpu_has(X86_FEATURE_PERFCTR_NB)
> >  #define cpu_has_cx8            boot_cpu_has(X86_FEATURE_CX8)
> >  #define cpu_has_cx16           boot_cpu_has(X86_FEATURE_CX16)
> >  #define cpu_has_eager_fpu      boot_cpu_has(X86_FEATURE_EAGER_FPU)
> > diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> > index 2234eaaec..57cb634 100644
> > --- a/arch/x86/include/asm/perf_event.h
> > +++ b/arch/x86/include/asm/perf_event.h
> > @@ -29,9 +29,14 @@
> >  #define ARCH_PERFMON_EVENTSEL_INV                      (1ULL << 23)
> >  #define ARCH_PERFMON_EVENTSEL_CMASK                    0xFF000000ULL
> >
> > +#define AMD64_EVENTSEL_INT_CORE_ENABLE                 (1ULL << 36)
> >  #define AMD64_EVENTSEL_GUESTONLY                       (1ULL << 40)
> >  #define AMD64_EVENTSEL_HOSTONLY                                (1ULL << 41)
> >
> > +#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT              37
> > +#define AMD64_EVENTSEL_INT_CORE_SEL_MASK               \
> > +       (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
> > +
> >  #define AMD64_EVENTSEL_EVENT   \
> >         (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
> >  #define INTEL_ARCH_EVENT_MASK  \
> > @@ -46,8 +51,12 @@
> >  #define AMD64_RAW_EVENT_MASK           \
> >         (X86_RAW_EVENT_MASK          |  \
> >          AMD64_EVENTSEL_EVENT)
> > +#define AMD64_RAW_EVENT_MASK_NB                \
> > +       (AMD64_EVENTSEL_EVENT        |  \
> > +        ARCH_PERFMON_EVENTSEL_UMASK)
> >  #define AMD64_NUM_COUNTERS                             4
> >  #define AMD64_NUM_COUNTERS_CORE                                6
> > +#define AMD64_NUM_COUNTERS_NB                          4
> >
> >  #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL          0x3c
> >  #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK                (0x00 << 8)
> > diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
> > index 1031604..27c05d2 100644
> > --- a/arch/x86/include/uapi/asm/msr-index.h
> > +++ b/arch/x86/include/uapi/asm/msr-index.h
> > @@ -195,6 +195,8 @@
> >  /* Fam 15h MSRs */
> >  #define MSR_F15H_PERF_CTL              0xc0010200
> >  #define MSR_F15H_PERF_CTR              0xc0010201
> > +#define MSR_F15H_NB_PERF_CTL           0xc0010240
> > +#define MSR_F15H_NB_PERF_CTR           0xc0010241
> >
> >  /* Fam 10h MSRs */
> >  #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
> > diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
> > index 05462f0..dfdab42 100644
> > --- a/arch/x86/kernel/cpu/perf_event_amd.c
> > +++ b/arch/x86/kernel/cpu/perf_event_amd.c
> > @@ -132,11 +132,14 @@ static u64 amd_pmu_event_map(int hw_event)
> >         return amd_perfmon_event_map[hw_event];
> >  }
> >
> > +static struct event_constraint *amd_nb_event_constraint;
> > +
> >  /*
> >   * Previously calculated offsets
> >   */
> >  static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
> >  static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
> > +static unsigned int rdpmc_indexes[X86_PMC_IDX_MAX] __read_mostly;
> >
> >  /*
> >   * Legacy CPUs:
> > @@ -144,10 +147,14 @@ static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
> >   *
> >   * CPUs with core performance counter extensions:
> >   *   6 counters starting at 0xc0010200 each offset by 2
> > + *
> > + * CPUs with north bridge performance counter extensions:
> > + *   4 additional counters starting at 0xc0010240 each offset by 2
> > + *   (indexed right above either one of the above core counters)
> >   */
> >  static inline int amd_pmu_addr_offset(int index, bool eventsel)
> >  {
> > -       int offset;
> > +       int offset, first, base;
> >
> >         if (!index)
> >                 return index;
> > @@ -160,7 +167,23 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
> >         if (offset)
> >                 return offset;
> >
> > -       if (!cpu_has_perfctr_core)
> > +       if (amd_nb_event_constraint &&
> > +           test_bit(index, amd_nb_event_constraint->idxmsk)) {
> > +               /*
> > +                * calculate the offset of NB counters with respect to
> > +                * base eventsel or perfctr
> > +                */
> > +
> > +               first = find_first_bit(amd_nb_event_constraint->idxmsk,
> > +                                      X86_PMC_IDX_MAX);
> > +
> > +               if (eventsel)
> > +                       base = MSR_F15H_NB_PERF_CTL - x86_pmu.eventsel;
> > +               else
> > +                       base = MSR_F15H_NB_PERF_CTR - x86_pmu.perfctr;
> > +
> > +               offset = base + ((index - first) << 1);
> > +       } else if (!cpu_has_perfctr_core)
> >                 offset = index;
> >         else
> >                 offset = index << 1;
> > @@ -175,24 +198,36 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
> >
> >  static inline int amd_pmu_rdpmc_index(int index)
> >  {
> > -       return index;
> > -}
> > +       int ret, first;
> >
> > -static int amd_pmu_hw_config(struct perf_event *event)
> > -{
> > -       int ret;
> > +       if (!index)
> > +               return index;
> >
> > -       /* pass precise event sampling to ibs: */
> > -       if (event->attr.precise_ip && get_ibs_caps())
> > -               return -ENOENT;
> > +       ret = rdpmc_indexes[index];
> >
> > -       ret = x86_pmu_hw_config(event);
> >         if (ret)
> >                 return ret;
> >
> > -       if (has_branch_stack(event))
> > -               return -EOPNOTSUPP;
> > +       if (amd_nb_event_constraint &&
> > +           test_bit(index, amd_nb_event_constraint->idxmsk)) {
> > +               /*
> > +                * according to the mnual, ECX value of the NB counters is
> > +                * the index of the NB counter (0, 1, 2 or 3) plus 6
> > +                */
> > +
> > +               first = find_first_bit(amd_nb_event_constraint->idxmsk,
> > +                                      X86_PMC_IDX_MAX);
> > +               ret = index - first + 6;
> > +       } else
> > +               ret = index;
> > +
> > +       rdpmc_indexes[index] = ret;
> >
> > +       return ret;
> > +}
> > +
> > +static int amd_core_hw_config(struct perf_event *event)
> > +{
> >         if (event->attr.exclude_host && event->attr.exclude_guest)
> >                 /*
> >                  * When HO == GO == 1 the hardware treats that as GO == HO == 0
> > @@ -206,10 +241,33 @@ static int amd_pmu_hw_config(struct perf_event *event)
> >         else if (event->attr.exclude_guest)
> >                 event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
> >
> > -       if (event->attr.type != PERF_TYPE_RAW)
> > -               return 0;
> > +       return 0;
> > +}
> >
> > -       event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
> > +/*
> > + * NB counters do not support the following event select bits:
> > + *   Host/Guest only
> > + *   Counter mask
> > + *   Invert counter mask
> > + *   Edge detect
> > + *   OS/User mode
> > + */
> > +static int amd_nb_hw_config(struct perf_event *event)
> > +{
> > +       /* for NB, we only allow system wide counting mode */
> > +       if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
> > +               return -EINVAL;
> > +
> > +       if (event->attr.exclude_user || event->attr.exclude_kernel ||
> > +           event->attr.exclude_host || event->attr.exclude_guest)
> > +               return -EINVAL;
> > +
> > +       event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
> > +                             ARCH_PERFMON_EVENTSEL_OS);
> > +
> > +       if (event->hw.config & ~(AMD64_RAW_EVENT_MASK_NB |
> > +                                ARCH_PERFMON_EVENTSEL_INT))
> > +               return -EINVAL;
> >
> >         return 0;
> >  }
> > @@ -227,6 +285,11 @@ static inline int amd_is_nb_event(struct hw_perf_event *hwc)
> >         return (hwc->config & 0xe0) == 0xe0;
> >  }
> >
> > +static inline int amd_is_perfctr_nb_event(struct hw_perf_event *hwc)
> > +{
> > +       return amd_nb_event_constraint && amd_is_nb_event(hwc);
> > +}
> > +
> >  static inline int amd_has_nb(struct cpu_hw_events *cpuc)
> >  {
> >         struct amd_nb *nb = cpuc->amd_nb;
> > @@ -234,6 +297,30 @@ static inline int amd_has_nb(struct cpu_hw_events *cpuc)
> >         return nb && nb->nb_id != -1;
> >  }
> >
> > +static int amd_pmu_hw_config(struct perf_event *event)
> > +{
> > +       int ret;
> > +
> > +       /* pass precise event sampling to ibs: */
> > +       if (event->attr.precise_ip && get_ibs_caps())
> > +               return -ENOENT;
> > +
> > +       if (has_branch_stack(event))
> > +               return -EOPNOTSUPP;
> > +
> > +       ret = x86_pmu_hw_config(event);
> > +       if (ret)
> > +               return ret;
> > +
> > +       if (event->attr.type == PERF_TYPE_RAW)
> > +               event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
> > +
> > +       if (amd_is_perfctr_nb_event(&event->hw))
> > +               return amd_nb_hw_config(event);
> > +
> > +       return amd_core_hw_config(event);
> > +}
> > +
> >  static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
> >                                            struct perf_event *event)
> >  {
> > @@ -254,6 +341,19 @@ static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
> >         }
> >  }
> >
> > +static void amd_nb_interrupt_hw_config(struct hw_perf_event *hwc)
> > +{
> > +       int core_id = cpu_data(smp_processor_id()).cpu_core_id;
> > +
> > +       /* deliver interrupts only to this core */
> > +       if (hwc->config & ARCH_PERFMON_EVENTSEL_INT) {
> > +               hwc->config |= AMD64_EVENTSEL_INT_CORE_ENABLE;
> > +               hwc->config &= ~AMD64_EVENTSEL_INT_CORE_SEL_MASK;
> > +               hwc->config |= (u64)(core_id) <<
> > +                       AMD64_EVENTSEL_INT_CORE_SEL_SHIFT;
> > +       }
> > +}
> > +
> >   /*
> >    * AMD64 NorthBridge events need special treatment because
> >    * counter access needs to be synchronized across all cores
> > @@ -299,6 +399,12 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
> >         struct perf_event *old;
> >         int idx, new = -1;
> >
> > +       if (!c)
> > +               c = &unconstrained;
> > +
> > +       if (cpuc->is_fake)
> > +               return c;
> > +
> >         /*
> >          * detect if already present, if so reuse
> >          *
> > @@ -335,6 +441,9 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
> >         if (new == -1)
> >                 return &emptyconstraint;
> >
> > +       if (amd_is_perfctr_nb_event(hwc))
> > +               amd_nb_interrupt_hw_config(hwc);
> > +
> >         return &nb->event_constraints[new];
> >  }
> >
> > @@ -434,7 +543,8 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
> >         if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
> >                 return &unconstrained;
> >
> > -       return __amd_get_nb_event_constraints(cpuc, event, &unconstrained);
> > +       return __amd_get_nb_event_constraints(cpuc, event,
> > +                                             amd_nb_event_constraint);
> >  }
> >
> >  static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
> > @@ -533,6 +643,9 @@ static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09,
> >  static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
> >  static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
> >
> > +static struct event_constraint amd_NBPMC96 = EVENT_CONSTRAINT(0, 0x3C0, 0);
> > +static struct event_constraint amd_NBPMC74 = EVENT_CONSTRAINT(0, 0xF0, 0);
> > +
> >  static struct event_constraint *
> >  amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
> >  {
> > @@ -598,8 +711,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev
> >                         return &amd_f15_PMC20;
> >                 }
> >         case AMD_EVENT_NB:
> > -               /* not yet implemented */
> > -               return &emptyconstraint;
> > +               return __amd_get_nb_event_constraints(cpuc, event,
> > +                                                     amd_nb_event_constraint);
> >         default:
> >                 return &emptyconstraint;
> >         }
> > @@ -647,7 +760,7 @@ static __initconst const struct x86_pmu amd_pmu = {
> >
> >  static int setup_event_constraints(void)
> >  {
> > -       if (boot_cpu_data.x86 >= 0x15)
> > +       if (boot_cpu_data.x86 == 0x15)
> >                 x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
> >         return 0;
> >  }
> > @@ -677,6 +790,23 @@ static int setup_perfctr_core(void)
> >         return 0;
> >  }
> >
> > +static int setup_perfctr_nb(void)
> > +{
> > +       if (!cpu_has_perfctr_nb)
> > +               return -ENODEV;
> > +
> > +       x86_pmu.num_counters += AMD64_NUM_COUNTERS_NB;
> > +
> > +       if (cpu_has_perfctr_core)
> > +               amd_nb_event_constraint = &amd_NBPMC96;
> > +       else
> > +               amd_nb_event_constraint = &amd_NBPMC74;
> > +
> > +       printk(KERN_INFO "perf: AMD northbridge performance counters detected\n");
> > +
> > +       return 0;
> > +}
> > +
> >  __init int amd_pmu_init(void)
> >  {
> >         /* Performance-monitoring supported from K7 and later: */
> > @@ -687,6 +817,7 @@ __init int amd_pmu_init(void)
> >
> >         setup_event_constraints();
> >         setup_perfctr_core();
> > +       setup_perfctr_nb();
> >
> >         /* Events are common for all AMDs */
> >         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
> > --
> > 1.7.9.5
> >
> >
> 

Re: [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h

[Stephane Eranian]

On Wed, Feb 6, 2013 at 6:26 PM, Jacob Shin <jacob.shin@amd.com> wrote:
> On AMD family 15h processors, there are 4 new performance counters
> (in addition to 6 core performance counters) that can be used for
> counting northbridge events (i.e. DRAM accesses). Their bit fields are
> almost identical to the core performance counters. However, unlike the
> core performance counters, these MSRs are shared between multiple
> cores (that share the same northbridge). We will reuse the same code
> path as existing family 10h northbridge event constraints handler
> logic to enforce this sharing.
>
> Signed-off-by: Jacob Shin <jacob.shin@amd.com>

Works for me.

I simply regret that the design decision ties uncore with core
even though hardware-wise they are separate. If I recall the earlier
discussion the motivation was to limit code duplication. That's true
but that's at the expense of isolation. For instance, now if the core
PMU is overcommitted, but not the uncore, then uncore still goes
thru event rescheduling for nothing.

But what matters at this point, is that there is coverage
for uncore, so we can get some bandwidth measurements
out. So i recommend we merge this in. Thanks.

Acked-by: Stephane Eranian <eranian@google.com>

> ---
>  arch/x86/include/asm/cpufeature.h     |    2 +
>  arch/x86/include/asm/perf_event.h     |    9 ++
>  arch/x86/include/uapi/asm/msr-index.h |    2 +
>  arch/x86/kernel/cpu/perf_event_amd.c  |  171 +++++++++++++++++++++++++++++----
>  4 files changed, 164 insertions(+), 20 deletions(-)
>
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 2d9075e..93fe929 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -167,6 +167,7 @@
>  #define X86_FEATURE_TBM                (6*32+21) /* trailing bit manipulations */
>  #define X86_FEATURE_TOPOEXT    (6*32+22) /* topology extensions CPUID leafs */
>  #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
> +#define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
>
>  /*
>   * Auxiliary flags: Linux defined - For features scattered in various
> @@ -309,6 +310,7 @@ extern const char * const x86_power_flags[32];
>  #define cpu_has_hypervisor     boot_cpu_has(X86_FEATURE_HYPERVISOR)
>  #define cpu_has_pclmulqdq      boot_cpu_has(X86_FEATURE_PCLMULQDQ)
>  #define cpu_has_perfctr_core   boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
> +#define cpu_has_perfctr_nb     boot_cpu_has(X86_FEATURE_PERFCTR_NB)
>  #define cpu_has_cx8            boot_cpu_has(X86_FEATURE_CX8)
>  #define cpu_has_cx16           boot_cpu_has(X86_FEATURE_CX16)
>  #define cpu_has_eager_fpu      boot_cpu_has(X86_FEATURE_EAGER_FPU)
> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index 2234eaaec..57cb634 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -29,9 +29,14 @@
>  #define ARCH_PERFMON_EVENTSEL_INV                      (1ULL << 23)
>  #define ARCH_PERFMON_EVENTSEL_CMASK                    0xFF000000ULL
>
> +#define AMD64_EVENTSEL_INT_CORE_ENABLE                 (1ULL << 36)
>  #define AMD64_EVENTSEL_GUESTONLY                       (1ULL << 40)
>  #define AMD64_EVENTSEL_HOSTONLY                                (1ULL << 41)
>
> +#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT              37
> +#define AMD64_EVENTSEL_INT_CORE_SEL_MASK               \
> +       (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
> +
>  #define AMD64_EVENTSEL_EVENT   \
>         (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
>  #define INTEL_ARCH_EVENT_MASK  \
> @@ -46,8 +51,12 @@
>  #define AMD64_RAW_EVENT_MASK           \
>         (X86_RAW_EVENT_MASK          |  \
>          AMD64_EVENTSEL_EVENT)
> +#define AMD64_RAW_EVENT_MASK_NB                \
> +       (AMD64_EVENTSEL_EVENT        |  \
> +        ARCH_PERFMON_EVENTSEL_UMASK)
>  #define AMD64_NUM_COUNTERS                             4
>  #define AMD64_NUM_COUNTERS_CORE                                6
> +#define AMD64_NUM_COUNTERS_NB                          4
>
>  #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL          0x3c
>  #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK                (0x00 << 8)
> diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
> index 1031604..27c05d2 100644
> --- a/arch/x86/include/uapi/asm/msr-index.h
> +++ b/arch/x86/include/uapi/asm/msr-index.h
> @@ -195,6 +195,8 @@
>  /* Fam 15h MSRs */
>  #define MSR_F15H_PERF_CTL              0xc0010200
>  #define MSR_F15H_PERF_CTR              0xc0010201
> +#define MSR_F15H_NB_PERF_CTL           0xc0010240
> +#define MSR_F15H_NB_PERF_CTR           0xc0010241
>
>  /* Fam 10h MSRs */
>  #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
> diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
> index 05462f0..dfdab42 100644
> --- a/arch/x86/kernel/cpu/perf_event_amd.c
> +++ b/arch/x86/kernel/cpu/perf_event_amd.c
> @@ -132,11 +132,14 @@ static u64 amd_pmu_event_map(int hw_event)
>         return amd_perfmon_event_map[hw_event];
>  }
>
> +static struct event_constraint *amd_nb_event_constraint;
> +
>  /*
>   * Previously calculated offsets
>   */
>  static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
>  static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
> +static unsigned int rdpmc_indexes[X86_PMC_IDX_MAX] __read_mostly;
>
>  /*
>   * Legacy CPUs:
> @@ -144,10 +147,14 @@ static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
>   *
>   * CPUs with core performance counter extensions:
>   *   6 counters starting at 0xc0010200 each offset by 2
> + *
> + * CPUs with north bridge performance counter extensions:
> + *   4 additional counters starting at 0xc0010240 each offset by 2
> + *   (indexed right above either one of the above core counters)
>   */
>  static inline int amd_pmu_addr_offset(int index, bool eventsel)
>  {
> -       int offset;
> +       int offset, first, base;
>
>         if (!index)
>                 return index;
> @@ -160,7 +167,23 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
>         if (offset)
>                 return offset;
>
> -       if (!cpu_has_perfctr_core)
> +       if (amd_nb_event_constraint &&
> +           test_bit(index, amd_nb_event_constraint->idxmsk)) {
> +               /*
> +                * calculate the offset of NB counters with respect to
> +                * base eventsel or perfctr
> +                */
> +
> +               first = find_first_bit(amd_nb_event_constraint->idxmsk,
> +                                      X86_PMC_IDX_MAX);
> +
> +               if (eventsel)
> +                       base = MSR_F15H_NB_PERF_CTL - x86_pmu.eventsel;
> +               else
> +                       base = MSR_F15H_NB_PERF_CTR - x86_pmu.perfctr;
> +
> +               offset = base + ((index - first) << 1);
> +       } else if (!cpu_has_perfctr_core)
>                 offset = index;
>         else
>                 offset = index << 1;
> @@ -175,24 +198,36 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
>
>  static inline int amd_pmu_rdpmc_index(int index)
>  {
> -       return index;
> -}
> +       int ret, first;
>
> -static int amd_pmu_hw_config(struct perf_event *event)
> -{
> -       int ret;
> +       if (!index)
> +               return index;
>
> -       /* pass precise event sampling to ibs: */
> -       if (event->attr.precise_ip && get_ibs_caps())
> -               return -ENOENT;
> +       ret = rdpmc_indexes[index];
>
> -       ret = x86_pmu_hw_config(event);
>         if (ret)
>                 return ret;
>
> -       if (has_branch_stack(event))
> -               return -EOPNOTSUPP;
> +       if (amd_nb_event_constraint &&
> +           test_bit(index, amd_nb_event_constraint->idxmsk)) {
> +               /*
> +                * according to the mnual, ECX value of the NB counters is
> +                * the index of the NB counter (0, 1, 2 or 3) plus 6
> +                */
> +
> +               first = find_first_bit(amd_nb_event_constraint->idxmsk,
> +                                      X86_PMC_IDX_MAX);
> +               ret = index - first + 6;
> +       } else
> +               ret = index;
> +
> +       rdpmc_indexes[index] = ret;
>
> +       return ret;
> +}
> +
> +static int amd_core_hw_config(struct perf_event *event)
> +{
>         if (event->attr.exclude_host && event->attr.exclude_guest)
>                 /*
>                  * When HO == GO == 1 the hardware treats that as GO == HO == 0
> @@ -206,10 +241,33 @@ static int amd_pmu_hw_config(struct perf_event *event)
>         else if (event->attr.exclude_guest)
>                 event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
>
> -       if (event->attr.type != PERF_TYPE_RAW)
> -               return 0;
> +       return 0;
> +}
>
> -       event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
> +/*
> + * NB counters do not support the following event select bits:
> + *   Host/Guest only
> + *   Counter mask
> + *   Invert counter mask
> + *   Edge detect
> + *   OS/User mode
> + */
> +static int amd_nb_hw_config(struct perf_event *event)
> +{
> +       /* for NB, we only allow system wide counting mode */
> +       if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
> +               return -EINVAL;
> +
> +       if (event->attr.exclude_user || event->attr.exclude_kernel ||
> +           event->attr.exclude_host || event->attr.exclude_guest)
> +               return -EINVAL;
> +
> +       event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
> +                             ARCH_PERFMON_EVENTSEL_OS);
> +
> +       if (event->hw.config & ~(AMD64_RAW_EVENT_MASK_NB |
> +                                ARCH_PERFMON_EVENTSEL_INT))
> +               return -EINVAL;
>
>         return 0;
>  }
> @@ -227,6 +285,11 @@ static inline int amd_is_nb_event(struct hw_perf_event *hwc)
>         return (hwc->config & 0xe0) == 0xe0;
>  }
>
> +static inline int amd_is_perfctr_nb_event(struct hw_perf_event *hwc)
> +{
> +       return amd_nb_event_constraint && amd_is_nb_event(hwc);
> +}
> +
>  static inline int amd_has_nb(struct cpu_hw_events *cpuc)
>  {
>         struct amd_nb *nb = cpuc->amd_nb;
> @@ -234,6 +297,30 @@ static inline int amd_has_nb(struct cpu_hw_events *cpuc)
>         return nb && nb->nb_id != -1;
>  }
>
> +static int amd_pmu_hw_config(struct perf_event *event)
> +{
> +       int ret;
> +
> +       /* pass precise event sampling to ibs: */
> +       if (event->attr.precise_ip && get_ibs_caps())
> +               return -ENOENT;
> +
> +       if (has_branch_stack(event))
> +               return -EOPNOTSUPP;
> +
> +       ret = x86_pmu_hw_config(event);
> +       if (ret)
> +               return ret;
> +
> +       if (event->attr.type == PERF_TYPE_RAW)
> +               event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
> +
> +       if (amd_is_perfctr_nb_event(&event->hw))
> +               return amd_nb_hw_config(event);
> +
> +       return amd_core_hw_config(event);
> +}
> +
>  static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
>                                            struct perf_event *event)
>  {
> @@ -254,6 +341,19 @@ static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
>         }
>  }
>
> +static void amd_nb_interrupt_hw_config(struct hw_perf_event *hwc)
> +{
> +       int core_id = cpu_data(smp_processor_id()).cpu_core_id;
> +
> +       /* deliver interrupts only to this core */
> +       if (hwc->config & ARCH_PERFMON_EVENTSEL_INT) {
> +               hwc->config |= AMD64_EVENTSEL_INT_CORE_ENABLE;
> +               hwc->config &= ~AMD64_EVENTSEL_INT_CORE_SEL_MASK;
> +               hwc->config |= (u64)(core_id) <<
> +                       AMD64_EVENTSEL_INT_CORE_SEL_SHIFT;
> +       }
> +}
> +
>   /*
>    * AMD64 NorthBridge events need special treatment because
>    * counter access needs to be synchronized across all cores
> @@ -299,6 +399,12 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
>         struct perf_event *old;
>         int idx, new = -1;
>
> +       if (!c)
> +               c = &unconstrained;
> +
> +       if (cpuc->is_fake)
> +               return c;
> +
>         /*
>          * detect if already present, if so reuse
>          *
> @@ -335,6 +441,9 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
>         if (new == -1)
>                 return &emptyconstraint;
>
> +       if (amd_is_perfctr_nb_event(hwc))
> +               amd_nb_interrupt_hw_config(hwc);
> +
>         return &nb->event_constraints[new];
>  }
>
> @@ -434,7 +543,8 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
>         if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
>                 return &unconstrained;
>
> -       return __amd_get_nb_event_constraints(cpuc, event, &unconstrained);
> +       return __amd_get_nb_event_constraints(cpuc, event,
> +                                             amd_nb_event_constraint);
>  }
>
>  static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
> @@ -533,6 +643,9 @@ static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09,
>  static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
>  static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
>
> +static struct event_constraint amd_NBPMC96 = EVENT_CONSTRAINT(0, 0x3C0, 0);
> +static struct event_constraint amd_NBPMC74 = EVENT_CONSTRAINT(0, 0xF0, 0);
> +
>  static struct event_constraint *
>  amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
>  {
> @@ -598,8 +711,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev
>                         return &amd_f15_PMC20;
>                 }
>         case AMD_EVENT_NB:
> -               /* not yet implemented */
> -               return &emptyconstraint;
> +               return __amd_get_nb_event_constraints(cpuc, event,
> +                                                     amd_nb_event_constraint);
>         default:
>                 return &emptyconstraint;
>         }
> @@ -647,7 +760,7 @@ static __initconst const struct x86_pmu amd_pmu = {
>
>  static int setup_event_constraints(void)
>  {
> -       if (boot_cpu_data.x86 >= 0x15)
> +       if (boot_cpu_data.x86 == 0x15)
>                 x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
>         return 0;
>  }
> @@ -677,6 +790,23 @@ static int setup_perfctr_core(void)
>         return 0;
>  }
>
> +static int setup_perfctr_nb(void)
> +{
> +       if (!cpu_has_perfctr_nb)
> +               return -ENODEV;
> +
> +       x86_pmu.num_counters += AMD64_NUM_COUNTERS_NB;
> +
> +       if (cpu_has_perfctr_core)
> +               amd_nb_event_constraint = &amd_NBPMC96;
> +       else
> +               amd_nb_event_constraint = &amd_NBPMC74;
> +
> +       printk(KERN_INFO "perf: AMD northbridge performance counters detected\n");
> +
> +       return 0;
> +}
> +
>  __init int amd_pmu_init(void)
>  {
>         /* Performance-monitoring supported from K7 and later: */
> @@ -687,6 +817,7 @@ __init int amd_pmu_init(void)
>
>         setup_event_constraints();
>         setup_perfctr_core();
> +       setup_perfctr_nb();
>
>         /* Events are common for all AMDs */
>         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
> --
> 1.7.9.5
>
>

Re: [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h

[Ingo Molnar]

* Jacob Shin <jacob.shin@amd.com> wrote:

> On Wed, Feb 06, 2013 at 11:26:29AM -0600, Jacob Shin wrote:
> > On AMD family 15h processors, there are 4 new performance counters
> > (in addition to 6 core performance counters) that can be used for
> > counting northbridge events (i.e. DRAM accesses). Their bit fields are
> > almost identical to the core performance counters. However, unlike the
> > core performance counters, these MSRs are shared between multiple
> > cores (that share the same northbridge). We will reuse the same code
> > path as existing family 10h northbridge event constraints handler
> > logic to enforce this sharing.
> > 
> > Signed-off-by: Jacob Shin <jacob.shin@amd.com>
> 
> Hi Ingo, could you please apply this one to tip as well? I 
> recieved tip-bot emails for all other patches in this series 
> except for this last one 6/6.
> 
> Or was that intentional? If so, what other changes are 
> required/ recommended?

Was waiting for Stephane's ack.

Thanks,

	Ingo

Re: [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h

[Stephane Eranian]

On Thu, Feb 7, 2013 at 6:57 PM, Jacob Shin <jacob.shin@amd.com> wrote:
> On Wed, Feb 06, 2013 at 11:26:29AM -0600, Jacob Shin wrote:
>> On AMD family 15h processors, there are 4 new performance counters
>> (in addition to 6 core performance counters) that can be used for
>> counting northbridge events (i.e. DRAM accesses). Their bit fields are
>> almost identical to the core performance counters. However, unlike the
>> core performance counters, these MSRs are shared between multiple
>> cores (that share the same northbridge). We will reuse the same code
>> path as existing family 10h northbridge event constraints handler
>> logic to enforce this sharing.
>>
>> Signed-off-by: Jacob Shin <jacob.shin@amd.com>
>
> Hi Ingo, could you please apply this one to tip as well? I recieved
> tip-bot emails for all other patches in this series except for this
> last one 6/6.
>
> Or was that intentional? If so, what other changes are required/
> recommended?
>
I am testing this patch right now. Should be done by tomorrow.

> Thanks!
>
> -Jacob
>
>> ---
>>  arch/x86/include/asm/cpufeature.h     |    2 +
>>  arch/x86/include/asm/perf_event.h     |    9 ++
>>  arch/x86/include/uapi/asm/msr-index.h |    2 +
>>  arch/x86/kernel/cpu/perf_event_amd.c  |  171 +++++++++++++++++++++++++++++----
>>  4 files changed, 164 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
>> index 2d9075e..93fe929 100644
>> --- a/arch/x86/include/asm/cpufeature.h
>> +++ b/arch/x86/include/asm/cpufeature.h
>> @@ -167,6 +167,7 @@
>>  #define X86_FEATURE_TBM              (6*32+21) /* trailing bit manipulations */
>>  #define X86_FEATURE_TOPOEXT  (6*32+22) /* topology extensions CPUID leafs */
>>  #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
>> +#define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
>>
>>  /*
>>   * Auxiliary flags: Linux defined - For features scattered in various
>> @@ -309,6 +310,7 @@ extern const char * const x86_power_flags[32];
>>  #define cpu_has_hypervisor   boot_cpu_has(X86_FEATURE_HYPERVISOR)
>>  #define cpu_has_pclmulqdq    boot_cpu_has(X86_FEATURE_PCLMULQDQ)
>>  #define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
>> +#define cpu_has_perfctr_nb   boot_cpu_has(X86_FEATURE_PERFCTR_NB)
>>  #define cpu_has_cx8          boot_cpu_has(X86_FEATURE_CX8)
>>  #define cpu_has_cx16         boot_cpu_has(X86_FEATURE_CX16)
>>  #define cpu_has_eager_fpu    boot_cpu_has(X86_FEATURE_EAGER_FPU)
>> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
>> index 2234eaaec..57cb634 100644
>> --- a/arch/x86/include/asm/perf_event.h
>> +++ b/arch/x86/include/asm/perf_event.h
>> @@ -29,9 +29,14 @@
>>  #define ARCH_PERFMON_EVENTSEL_INV                    (1ULL << 23)
>>  #define ARCH_PERFMON_EVENTSEL_CMASK                  0xFF000000ULL
>>
>> +#define AMD64_EVENTSEL_INT_CORE_ENABLE                       (1ULL << 36)
>>  #define AMD64_EVENTSEL_GUESTONLY                     (1ULL << 40)
>>  #define AMD64_EVENTSEL_HOSTONLY                              (1ULL << 41)
>>
>> +#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT            37
>> +#define AMD64_EVENTSEL_INT_CORE_SEL_MASK             \
>> +     (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
>> +
>>  #define AMD64_EVENTSEL_EVENT \
>>       (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
>>  #define INTEL_ARCH_EVENT_MASK        \
>> @@ -46,8 +51,12 @@
>>  #define AMD64_RAW_EVENT_MASK         \
>>       (X86_RAW_EVENT_MASK          |  \
>>        AMD64_EVENTSEL_EVENT)
>> +#define AMD64_RAW_EVENT_MASK_NB              \
>> +     (AMD64_EVENTSEL_EVENT        |  \
>> +      ARCH_PERFMON_EVENTSEL_UMASK)
>>  #define AMD64_NUM_COUNTERS                           4
>>  #define AMD64_NUM_COUNTERS_CORE                              6
>> +#define AMD64_NUM_COUNTERS_NB                                4
>>
>>  #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL                0x3c
>>  #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK              (0x00 << 8)
>> diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
>> index 1031604..27c05d2 100644
>> --- a/arch/x86/include/uapi/asm/msr-index.h
>> +++ b/arch/x86/include/uapi/asm/msr-index.h
>> @@ -195,6 +195,8 @@
>>  /* Fam 15h MSRs */
>>  #define MSR_F15H_PERF_CTL            0xc0010200
>>  #define MSR_F15H_PERF_CTR            0xc0010201
>> +#define MSR_F15H_NB_PERF_CTL         0xc0010240
>> +#define MSR_F15H_NB_PERF_CTR         0xc0010241
>>
>>  /* Fam 10h MSRs */
>>  #define MSR_FAM10H_MMIO_CONF_BASE    0xc0010058
>> diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
>> index 05462f0..dfdab42 100644
>> --- a/arch/x86/kernel/cpu/perf_event_amd.c
>> +++ b/arch/x86/kernel/cpu/perf_event_amd.c
>> @@ -132,11 +132,14 @@ static u64 amd_pmu_event_map(int hw_event)
>>       return amd_perfmon_event_map[hw_event];
>>  }
>>
>> +static struct event_constraint *amd_nb_event_constraint;
>> +
>>  /*
>>   * Previously calculated offsets
>>   */
>>  static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
>>  static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
>> +static unsigned int rdpmc_indexes[X86_PMC_IDX_MAX] __read_mostly;
>>
>>  /*
>>   * Legacy CPUs:
>> @@ -144,10 +147,14 @@ static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
>>   *
>>   * CPUs with core performance counter extensions:
>>   *   6 counters starting at 0xc0010200 each offset by 2
>> + *
>> + * CPUs with north bridge performance counter extensions:
>> + *   4 additional counters starting at 0xc0010240 each offset by 2
>> + *   (indexed right above either one of the above core counters)
>>   */
>>  static inline int amd_pmu_addr_offset(int index, bool eventsel)
>>  {
>> -     int offset;
>> +     int offset, first, base;
>>
>>       if (!index)
>>               return index;
>> @@ -160,7 +167,23 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
>>       if (offset)
>>               return offset;
>>
>> -     if (!cpu_has_perfctr_core)
>> +     if (amd_nb_event_constraint &&
>> +         test_bit(index, amd_nb_event_constraint->idxmsk)) {
>> +             /*
>> +              * calculate the offset of NB counters with respect to
>> +              * base eventsel or perfctr
>> +              */
>> +
>> +             first = find_first_bit(amd_nb_event_constraint->idxmsk,
>> +                                    X86_PMC_IDX_MAX);
>> +
>> +             if (eventsel)
>> +                     base = MSR_F15H_NB_PERF_CTL - x86_pmu.eventsel;
>> +             else
>> +                     base = MSR_F15H_NB_PERF_CTR - x86_pmu.perfctr;
>> +
>> +             offset = base + ((index - first) << 1);
>> +     } else if (!cpu_has_perfctr_core)
>>               offset = index;
>>       else
>>               offset = index << 1;
>> @@ -175,24 +198,36 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
>>
>>  static inline int amd_pmu_rdpmc_index(int index)
>>  {
>> -     return index;
>> -}
>> +     int ret, first;
>>
>> -static int amd_pmu_hw_config(struct perf_event *event)
>> -{
>> -     int ret;
>> +     if (!index)
>> +             return index;
>>
>> -     /* pass precise event sampling to ibs: */
>> -     if (event->attr.precise_ip && get_ibs_caps())
>> -             return -ENOENT;
>> +     ret = rdpmc_indexes[index];
>>
>> -     ret = x86_pmu_hw_config(event);
>>       if (ret)
>>               return ret;
>>
>> -     if (has_branch_stack(event))
>> -             return -EOPNOTSUPP;
>> +     if (amd_nb_event_constraint &&
>> +         test_bit(index, amd_nb_event_constraint->idxmsk)) {
>> +             /*
>> +              * according to the mnual, ECX value of the NB counters is
>> +              * the index of the NB counter (0, 1, 2 or 3) plus 6
>> +              */
>> +
>> +             first = find_first_bit(amd_nb_event_constraint->idxmsk,
>> +                                    X86_PMC_IDX_MAX);
>> +             ret = index - first + 6;
>> +     } else
>> +             ret = index;
>> +
>> +     rdpmc_indexes[index] = ret;
>>
>> +     return ret;
>> +}
>> +
>> +static int amd_core_hw_config(struct perf_event *event)
>> +{
>>       if (event->attr.exclude_host && event->attr.exclude_guest)
>>               /*
>>                * When HO == GO == 1 the hardware treats that as GO == HO == 0
>> @@ -206,10 +241,33 @@ static int amd_pmu_hw_config(struct perf_event *event)
>>       else if (event->attr.exclude_guest)
>>               event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
>>
>> -     if (event->attr.type != PERF_TYPE_RAW)
>> -             return 0;
>> +     return 0;
>> +}
>>
>> -     event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
>> +/*
>> + * NB counters do not support the following event select bits:
>> + *   Host/Guest only
>> + *   Counter mask
>> + *   Invert counter mask
>> + *   Edge detect
>> + *   OS/User mode
>> + */
>> +static int amd_nb_hw_config(struct perf_event *event)
>> +{
>> +     /* for NB, we only allow system wide counting mode */
>> +     if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
>> +             return -EINVAL;
>> +
>> +     if (event->attr.exclude_user || event->attr.exclude_kernel ||
>> +         event->attr.exclude_host || event->attr.exclude_guest)
>> +             return -EINVAL;
>> +
>> +     event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
>> +                           ARCH_PERFMON_EVENTSEL_OS);
>> +
>> +     if (event->hw.config & ~(AMD64_RAW_EVENT_MASK_NB |
>> +                              ARCH_PERFMON_EVENTSEL_INT))
>> +             return -EINVAL;
>>
>>       return 0;
>>  }
>> @@ -227,6 +285,11 @@ static inline int amd_is_nb_event(struct hw_perf_event *hwc)
>>       return (hwc->config & 0xe0) == 0xe0;
>>  }
>>
>> +static inline int amd_is_perfctr_nb_event(struct hw_perf_event *hwc)
>> +{
>> +     return amd_nb_event_constraint && amd_is_nb_event(hwc);
>> +}
>> +
>>  static inline int amd_has_nb(struct cpu_hw_events *cpuc)
>>  {
>>       struct amd_nb *nb = cpuc->amd_nb;
>> @@ -234,6 +297,30 @@ static inline int amd_has_nb(struct cpu_hw_events *cpuc)
>>       return nb && nb->nb_id != -1;
>>  }
>>
>> +static int amd_pmu_hw_config(struct perf_event *event)
>> +{
>> +     int ret;
>> +
>> +     /* pass precise event sampling to ibs: */
>> +     if (event->attr.precise_ip && get_ibs_caps())
>> +             return -ENOENT;
>> +
>> +     if (has_branch_stack(event))
>> +             return -EOPNOTSUPP;
>> +
>> +     ret = x86_pmu_hw_config(event);
>> +     if (ret)
>> +             return ret;
>> +
>> +     if (event->attr.type == PERF_TYPE_RAW)
>> +             event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
>> +
>> +     if (amd_is_perfctr_nb_event(&event->hw))
>> +             return amd_nb_hw_config(event);
>> +
>> +     return amd_core_hw_config(event);
>> +}
>> +
>>  static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
>>                                          struct perf_event *event)
>>  {
>> @@ -254,6 +341,19 @@ static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
>>       }
>>  }
>>
>> +static void amd_nb_interrupt_hw_config(struct hw_perf_event *hwc)
>> +{
>> +     int core_id = cpu_data(smp_processor_id()).cpu_core_id;
>> +
>> +     /* deliver interrupts only to this core */
>> +     if (hwc->config & ARCH_PERFMON_EVENTSEL_INT) {
>> +             hwc->config |= AMD64_EVENTSEL_INT_CORE_ENABLE;
>> +             hwc->config &= ~AMD64_EVENTSEL_INT_CORE_SEL_MASK;
>> +             hwc->config |= (u64)(core_id) <<
>> +                     AMD64_EVENTSEL_INT_CORE_SEL_SHIFT;
>> +     }
>> +}
>> +
>>   /*
>>    * AMD64 NorthBridge events need special treatment because
>>    * counter access needs to be synchronized across all cores
>> @@ -299,6 +399,12 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
>>       struct perf_event *old;
>>       int idx, new = -1;
>>
>> +     if (!c)
>> +             c = &unconstrained;
>> +
>> +     if (cpuc->is_fake)
>> +             return c;
>> +
>>       /*
>>        * detect if already present, if so reuse
>>        *
>> @@ -335,6 +441,9 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
>>       if (new == -1)
>>               return &emptyconstraint;
>>
>> +     if (amd_is_perfctr_nb_event(hwc))
>> +             amd_nb_interrupt_hw_config(hwc);
>> +
>>       return &nb->event_constraints[new];
>>  }
>>
>> @@ -434,7 +543,8 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
>>       if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
>>               return &unconstrained;
>>
>> -     return __amd_get_nb_event_constraints(cpuc, event, &unconstrained);
>> +     return __amd_get_nb_event_constraints(cpuc, event,
>> +                                           amd_nb_event_constraint);
>>  }
>>
>>  static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
>> @@ -533,6 +643,9 @@ static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09,
>>  static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
>>  static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
>>
>> +static struct event_constraint amd_NBPMC96 = EVENT_CONSTRAINT(0, 0x3C0, 0);
>> +static struct event_constraint amd_NBPMC74 = EVENT_CONSTRAINT(0, 0xF0, 0);
>> +
>>  static struct event_constraint *
>>  amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
>>  {
>> @@ -598,8 +711,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev
>>                       return &amd_f15_PMC20;
>>               }
>>       case AMD_EVENT_NB:
>> -             /* not yet implemented */
>> -             return &emptyconstraint;
>> +             return __amd_get_nb_event_constraints(cpuc, event,
>> +                                                   amd_nb_event_constraint);
>>       default:
>>               return &emptyconstraint;
>>       }
>> @@ -647,7 +760,7 @@ static __initconst const struct x86_pmu amd_pmu = {
>>
>>  static int setup_event_constraints(void)
>>  {
>> -     if (boot_cpu_data.x86 >= 0x15)
>> +     if (boot_cpu_data.x86 == 0x15)
>>               x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
>>       return 0;
>>  }
>> @@ -677,6 +790,23 @@ static int setup_perfctr_core(void)
>>       return 0;
>>  }
>>
>> +static int setup_perfctr_nb(void)
>> +{
>> +     if (!cpu_has_perfctr_nb)
>> +             return -ENODEV;
>> +
>> +     x86_pmu.num_counters += AMD64_NUM_COUNTERS_NB;
>> +
>> +     if (cpu_has_perfctr_core)
>> +             amd_nb_event_constraint = &amd_NBPMC96;
>> +     else
>> +             amd_nb_event_constraint = &amd_NBPMC74;
>> +
>> +     printk(KERN_INFO "perf: AMD northbridge performance counters detected\n");
>> +
>> +     return 0;
>> +}
>> +
>>  __init int amd_pmu_init(void)
>>  {
>>       /* Performance-monitoring supported from K7 and later: */
>> @@ -687,6 +817,7 @@ __init int amd_pmu_init(void)
>>
>>       setup_event_constraints();
>>       setup_perfctr_core();
>> +     setup_perfctr_nb();
>>
>>       /* Events are common for all AMDs */
>>       memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
>> --
>> 1.7.9.5
>>
>

Re: [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h

[Jacob Shin]

On Wed, Feb 06, 2013 at 11:26:29AM -0600, Jacob Shin wrote:
> On AMD family 15h processors, there are 4 new performance counters
> (in addition to 6 core performance counters) that can be used for
> counting northbridge events (i.e. DRAM accesses). Their bit fields are
> almost identical to the core performance counters. However, unlike the
> core performance counters, these MSRs are shared between multiple
> cores (that share the same northbridge). We will reuse the same code
> path as existing family 10h northbridge event constraints handler
> logic to enforce this sharing.
> 
> Signed-off-by: Jacob Shin <jacob.shin@amd.com>

Hi Ingo, could you please apply this one to tip as well? I recieved
tip-bot emails for all other patches in this series except for this
last one 6/6.

Or was that intentional? If so, what other changes are required/
recommended?

Thanks!

-Jacob

> ---
>  arch/x86/include/asm/cpufeature.h     |    2 +
>  arch/x86/include/asm/perf_event.h     |    9 ++
>  arch/x86/include/uapi/asm/msr-index.h |    2 +
>  arch/x86/kernel/cpu/perf_event_amd.c  |  171 +++++++++++++++++++++++++++++----
>  4 files changed, 164 insertions(+), 20 deletions(-)
> 
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 2d9075e..93fe929 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -167,6 +167,7 @@
>  #define X86_FEATURE_TBM		(6*32+21) /* trailing bit manipulations */
>  #define X86_FEATURE_TOPOEXT	(6*32+22) /* topology extensions CPUID leafs */
>  #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
> +#define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
>  
>  /*
>   * Auxiliary flags: Linux defined - For features scattered in various
> @@ -309,6 +310,7 @@ extern const char * const x86_power_flags[32];
>  #define cpu_has_hypervisor	boot_cpu_has(X86_FEATURE_HYPERVISOR)
>  #define cpu_has_pclmulqdq	boot_cpu_has(X86_FEATURE_PCLMULQDQ)
>  #define cpu_has_perfctr_core	boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
> +#define cpu_has_perfctr_nb	boot_cpu_has(X86_FEATURE_PERFCTR_NB)
>  #define cpu_has_cx8		boot_cpu_has(X86_FEATURE_CX8)
>  #define cpu_has_cx16		boot_cpu_has(X86_FEATURE_CX16)
>  #define cpu_has_eager_fpu	boot_cpu_has(X86_FEATURE_EAGER_FPU)
> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index 2234eaaec..57cb634 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -29,9 +29,14 @@
>  #define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
>  #define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL
>  
> +#define AMD64_EVENTSEL_INT_CORE_ENABLE			(1ULL << 36)
>  #define AMD64_EVENTSEL_GUESTONLY			(1ULL << 40)
>  #define AMD64_EVENTSEL_HOSTONLY				(1ULL << 41)
>  
> +#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT		37
> +#define AMD64_EVENTSEL_INT_CORE_SEL_MASK		\
> +	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
> +
>  #define AMD64_EVENTSEL_EVENT	\
>  	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
>  #define INTEL_ARCH_EVENT_MASK	\
> @@ -46,8 +51,12 @@
>  #define AMD64_RAW_EVENT_MASK		\
>  	(X86_RAW_EVENT_MASK          |  \
>  	 AMD64_EVENTSEL_EVENT)
> +#define AMD64_RAW_EVENT_MASK_NB		\
> +	(AMD64_EVENTSEL_EVENT        |  \
> +	 ARCH_PERFMON_EVENTSEL_UMASK)
>  #define AMD64_NUM_COUNTERS				4
>  #define AMD64_NUM_COUNTERS_CORE				6
> +#define AMD64_NUM_COUNTERS_NB				4
>  
>  #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c
>  #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
> diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
> index 1031604..27c05d2 100644
> --- a/arch/x86/include/uapi/asm/msr-index.h
> +++ b/arch/x86/include/uapi/asm/msr-index.h
> @@ -195,6 +195,8 @@
>  /* Fam 15h MSRs */
>  #define MSR_F15H_PERF_CTL		0xc0010200
>  #define MSR_F15H_PERF_CTR		0xc0010201
> +#define MSR_F15H_NB_PERF_CTL		0xc0010240
> +#define MSR_F15H_NB_PERF_CTR		0xc0010241
>  
>  /* Fam 10h MSRs */
>  #define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
> diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
> index 05462f0..dfdab42 100644
> --- a/arch/x86/kernel/cpu/perf_event_amd.c
> +++ b/arch/x86/kernel/cpu/perf_event_amd.c
> @@ -132,11 +132,14 @@ static u64 amd_pmu_event_map(int hw_event)
>  	return amd_perfmon_event_map[hw_event];
>  }
>  
> +static struct event_constraint *amd_nb_event_constraint;
> +
>  /*
>   * Previously calculated offsets
>   */
>  static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
>  static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
> +static unsigned int rdpmc_indexes[X86_PMC_IDX_MAX] __read_mostly;
>  
>  /*
>   * Legacy CPUs:
> @@ -144,10 +147,14 @@ static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
>   *
>   * CPUs with core performance counter extensions:
>   *   6 counters starting at 0xc0010200 each offset by 2
> + *
> + * CPUs with north bridge performance counter extensions:
> + *   4 additional counters starting at 0xc0010240 each offset by 2
> + *   (indexed right above either one of the above core counters)
>   */
>  static inline int amd_pmu_addr_offset(int index, bool eventsel)
>  {
> -	int offset;
> +	int offset, first, base;
>  
>  	if (!index)
>  		return index;
> @@ -160,7 +167,23 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
>  	if (offset)
>  		return offset;
>  
> -	if (!cpu_has_perfctr_core)
> +	if (amd_nb_event_constraint &&
> +	    test_bit(index, amd_nb_event_constraint->idxmsk)) {
> +		/*
> +		 * calculate the offset of NB counters with respect to
> +		 * base eventsel or perfctr
> +		 */
> +
> +		first = find_first_bit(amd_nb_event_constraint->idxmsk,
> +				       X86_PMC_IDX_MAX);
> +
> +		if (eventsel)
> +			base = MSR_F15H_NB_PERF_CTL - x86_pmu.eventsel;
> +		else
> +			base = MSR_F15H_NB_PERF_CTR - x86_pmu.perfctr;
> +
> +		offset = base + ((index - first) << 1);
> +	} else if (!cpu_has_perfctr_core)
>  		offset = index;
>  	else
>  		offset = index << 1;
> @@ -175,24 +198,36 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
>  
>  static inline int amd_pmu_rdpmc_index(int index)
>  {
> -	return index;
> -}
> +	int ret, first;
>  
> -static int amd_pmu_hw_config(struct perf_event *event)
> -{
> -	int ret;
> +	if (!index)
> +		return index;
>  
> -	/* pass precise event sampling to ibs: */
> -	if (event->attr.precise_ip && get_ibs_caps())
> -		return -ENOENT;
> +	ret = rdpmc_indexes[index];
>  
> -	ret = x86_pmu_hw_config(event);
>  	if (ret)
>  		return ret;
>  
> -	if (has_branch_stack(event))
> -		return -EOPNOTSUPP;
> +	if (amd_nb_event_constraint &&
> +	    test_bit(index, amd_nb_event_constraint->idxmsk)) {
> +		/*
> +		 * according to the mnual, ECX value of the NB counters is
> +		 * the index of the NB counter (0, 1, 2 or 3) plus 6
> +		 */
> +
> +		first = find_first_bit(amd_nb_event_constraint->idxmsk,
> +				       X86_PMC_IDX_MAX);
> +		ret = index - first + 6;
> +	} else
> +		ret = index;
> +
> +	rdpmc_indexes[index] = ret;
>  
> +	return ret;
> +}
> +
> +static int amd_core_hw_config(struct perf_event *event)
> +{
>  	if (event->attr.exclude_host && event->attr.exclude_guest)
>  		/*
>  		 * When HO == GO == 1 the hardware treats that as GO == HO == 0
> @@ -206,10 +241,33 @@ static int amd_pmu_hw_config(struct perf_event *event)
>  	else if (event->attr.exclude_guest)
>  		event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
>  
> -	if (event->attr.type != PERF_TYPE_RAW)
> -		return 0;
> +	return 0;
> +}
>  
> -	event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
> +/*
> + * NB counters do not support the following event select bits:
> + *   Host/Guest only
> + *   Counter mask
> + *   Invert counter mask
> + *   Edge detect
> + *   OS/User mode
> + */
> +static int amd_nb_hw_config(struct perf_event *event)
> +{
> +	/* for NB, we only allow system wide counting mode */
> +	if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
> +		return -EINVAL;
> +
> +	if (event->attr.exclude_user || event->attr.exclude_kernel ||
> +	    event->attr.exclude_host || event->attr.exclude_guest)
> +		return -EINVAL;
> +
> +	event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
> +			      ARCH_PERFMON_EVENTSEL_OS);
> +
> +	if (event->hw.config & ~(AMD64_RAW_EVENT_MASK_NB |
> +				 ARCH_PERFMON_EVENTSEL_INT))
> +		return -EINVAL;
>  
>  	return 0;
>  }
> @@ -227,6 +285,11 @@ static inline int amd_is_nb_event(struct hw_perf_event *hwc)
>  	return (hwc->config & 0xe0) == 0xe0;
>  }
>  
> +static inline int amd_is_perfctr_nb_event(struct hw_perf_event *hwc)
> +{
> +	return amd_nb_event_constraint && amd_is_nb_event(hwc);
> +}
> +
>  static inline int amd_has_nb(struct cpu_hw_events *cpuc)
>  {
>  	struct amd_nb *nb = cpuc->amd_nb;
> @@ -234,6 +297,30 @@ static inline int amd_has_nb(struct cpu_hw_events *cpuc)
>  	return nb && nb->nb_id != -1;
>  }
>  
> +static int amd_pmu_hw_config(struct perf_event *event)
> +{
> +	int ret;
> +
> +	/* pass precise event sampling to ibs: */
> +	if (event->attr.precise_ip && get_ibs_caps())
> +		return -ENOENT;
> +
> +	if (has_branch_stack(event))
> +		return -EOPNOTSUPP;
> +
> +	ret = x86_pmu_hw_config(event);
> +	if (ret)
> +		return ret;
> +
> +	if (event->attr.type == PERF_TYPE_RAW)
> +		event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
> +
> +	if (amd_is_perfctr_nb_event(&event->hw))
> +		return amd_nb_hw_config(event);
> +
> +	return amd_core_hw_config(event);
> +}
> +
>  static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
>  					   struct perf_event *event)
>  {
> @@ -254,6 +341,19 @@ static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
>  	}
>  }
>  
> +static void amd_nb_interrupt_hw_config(struct hw_perf_event *hwc)
> +{
> +	int core_id = cpu_data(smp_processor_id()).cpu_core_id;
> +
> +	/* deliver interrupts only to this core */
> +	if (hwc->config & ARCH_PERFMON_EVENTSEL_INT) {
> +		hwc->config |= AMD64_EVENTSEL_INT_CORE_ENABLE;
> +		hwc->config &= ~AMD64_EVENTSEL_INT_CORE_SEL_MASK;
> +		hwc->config |= (u64)(core_id) <<
> +			AMD64_EVENTSEL_INT_CORE_SEL_SHIFT;
> +	}
> +}
> +
>   /*
>    * AMD64 NorthBridge events need special treatment because
>    * counter access needs to be synchronized across all cores
> @@ -299,6 +399,12 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
>  	struct perf_event *old;
>  	int idx, new = -1;
>  
> +	if (!c)
> +		c = &unconstrained;
> +
> +	if (cpuc->is_fake)
> +		return c;
> +
>  	/*
>  	 * detect if already present, if so reuse
>  	 *
> @@ -335,6 +441,9 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
>  	if (new == -1)
>  		return &emptyconstraint;
>  
> +	if (amd_is_perfctr_nb_event(hwc))
> +		amd_nb_interrupt_hw_config(hwc);
> +
>  	return &nb->event_constraints[new];
>  }
>  
> @@ -434,7 +543,8 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
>  	if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
>  		return &unconstrained;
>  
> -	return __amd_get_nb_event_constraints(cpuc, event, &unconstrained);
> +	return __amd_get_nb_event_constraints(cpuc, event,
> +					      amd_nb_event_constraint);
>  }
>  
>  static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
> @@ -533,6 +643,9 @@ static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09,
>  static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
>  static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
>  
> +static struct event_constraint amd_NBPMC96 = EVENT_CONSTRAINT(0, 0x3C0, 0);
> +static struct event_constraint amd_NBPMC74 = EVENT_CONSTRAINT(0, 0xF0, 0);
> +
>  static struct event_constraint *
>  amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
>  {
> @@ -598,8 +711,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev
>  			return &amd_f15_PMC20;
>  		}
>  	case AMD_EVENT_NB:
> -		/* not yet implemented */
> -		return &emptyconstraint;
> +		return __amd_get_nb_event_constraints(cpuc, event,
> +						      amd_nb_event_constraint);
>  	default:
>  		return &emptyconstraint;
>  	}
> @@ -647,7 +760,7 @@ static __initconst const struct x86_pmu amd_pmu = {
>  
>  static int setup_event_constraints(void)
>  {
> -	if (boot_cpu_data.x86 >= 0x15)
> +	if (boot_cpu_data.x86 == 0x15)
>  		x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
>  	return 0;
>  }
> @@ -677,6 +790,23 @@ static int setup_perfctr_core(void)
>  	return 0;
>  }
>  
> +static int setup_perfctr_nb(void)
> +{
> +	if (!cpu_has_perfctr_nb)
> +		return -ENODEV;
> +
> +	x86_pmu.num_counters += AMD64_NUM_COUNTERS_NB;
> +
> +	if (cpu_has_perfctr_core)
> +		amd_nb_event_constraint = &amd_NBPMC96;
> +	else
> +		amd_nb_event_constraint = &amd_NBPMC74;
> +
> +	printk(KERN_INFO "perf: AMD northbridge performance counters detected\n");
> +
> +	return 0;
> +}
> +
>  __init int amd_pmu_init(void)
>  {
>  	/* Performance-monitoring supported from K7 and later: */
> @@ -687,6 +817,7 @@ __init int amd_pmu_init(void)
>  
>  	setup_event_constraints();
>  	setup_perfctr_core();
> +	setup_perfctr_nb();
>  
>  	/* Events are common for all AMDs */
>  	memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
> -- 
> 1.7.9.5
> 

[PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h

[Jacob Shin]

On AMD family 15h processors, there are 4 new performance counters
(in addition to 6 core performance counters) that can be used for
counting northbridge events (i.e. DRAM accesses). Their bit fields are
almost identical to the core performance counters. However, unlike the
core performance counters, these MSRs are shared between multiple
cores (that share the same northbridge). We will reuse the same code
path as existing family 10h northbridge event constraints handler
logic to enforce this sharing.

Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
 arch/x86/include/asm/cpufeature.h     |    2 +
 arch/x86/include/asm/perf_event.h     |    9 ++
 arch/x86/include/uapi/asm/msr-index.h |    2 +
 arch/x86/kernel/cpu/perf_event_amd.c  |  171 +++++++++++++++++++++++++++++----
 4 files changed, 164 insertions(+), 20 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 2d9075e..93fe929 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -167,6 +167,7 @@
 #define X86_FEATURE_TBM		(6*32+21) /* trailing bit manipulations */
 #define X86_FEATURE_TOPOEXT	(6*32+22) /* topology extensions CPUID leafs */
 #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
+#define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
 
 /*
  * Auxiliary flags: Linux defined - For features scattered in various
@@ -309,6 +310,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_hypervisor	boot_cpu_has(X86_FEATURE_HYPERVISOR)
 #define cpu_has_pclmulqdq	boot_cpu_has(X86_FEATURE_PCLMULQDQ)
 #define cpu_has_perfctr_core	boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
+#define cpu_has_perfctr_nb	boot_cpu_has(X86_FEATURE_PERFCTR_NB)
 #define cpu_has_cx8		boot_cpu_has(X86_FEATURE_CX8)
 #define cpu_has_cx16		boot_cpu_has(X86_FEATURE_CX16)
 #define cpu_has_eager_fpu	boot_cpu_has(X86_FEATURE_EAGER_FPU)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 2234eaaec..57cb634 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -29,9 +29,14 @@
 #define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
 #define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL
 
+#define AMD64_EVENTSEL_INT_CORE_ENABLE			(1ULL << 36)
 #define AMD64_EVENTSEL_GUESTONLY			(1ULL << 40)
 #define AMD64_EVENTSEL_HOSTONLY				(1ULL << 41)
 
+#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT		37
+#define AMD64_EVENTSEL_INT_CORE_SEL_MASK		\
+	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
+
 #define AMD64_EVENTSEL_EVENT	\
 	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
 #define INTEL_ARCH_EVENT_MASK	\
@@ -46,8 +51,12 @@
 #define AMD64_RAW_EVENT_MASK		\
 	(X86_RAW_EVENT_MASK          |  \
 	 AMD64_EVENTSEL_EVENT)
+#define AMD64_RAW_EVENT_MASK_NB		\
+	(AMD64_EVENTSEL_EVENT        |  \
+	 ARCH_PERFMON_EVENTSEL_UMASK)
 #define AMD64_NUM_COUNTERS				4
 #define AMD64_NUM_COUNTERS_CORE				6
+#define AMD64_NUM_COUNTERS_NB				4
 
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 1031604..27c05d2 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -195,6 +195,8 @@
 /* Fam 15h MSRs */
 #define MSR_F15H_PERF_CTL		0xc0010200
 #define MSR_F15H_PERF_CTR		0xc0010201
+#define MSR_F15H_NB_PERF_CTL		0xc0010240
+#define MSR_F15H_NB_PERF_CTR		0xc0010241
 
 /* Fam 10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index 05462f0..dfdab42 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -132,11 +132,14 @@ static u64 amd_pmu_event_map(int hw_event)
 	return amd_perfmon_event_map[hw_event];
 }
 
+static struct event_constraint *amd_nb_event_constraint;
+
 /*
  * Previously calculated offsets
  */
 static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
 static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
+static unsigned int rdpmc_indexes[X86_PMC_IDX_MAX] __read_mostly;
 
 /*
  * Legacy CPUs:
@@ -144,10 +147,14 @@ static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
  *
  * CPUs with core performance counter extensions:
  *   6 counters starting at 0xc0010200 each offset by 2
+ *
+ * CPUs with north bridge performance counter extensions:
+ *   4 additional counters starting at 0xc0010240 each offset by 2
+ *   (indexed right above either one of the above core counters)
  */
 static inline int amd_pmu_addr_offset(int index, bool eventsel)
 {
-	int offset;
+	int offset, first, base;
 
 	if (!index)
 		return index;
@@ -160,7 +167,23 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
 	if (offset)
 		return offset;
 
-	if (!cpu_has_perfctr_core)
+	if (amd_nb_event_constraint &&
+	    test_bit(index, amd_nb_event_constraint->idxmsk)) {
+		/*
+		 * calculate the offset of NB counters with respect to
+		 * base eventsel or perfctr
+		 */
+
+		first = find_first_bit(amd_nb_event_constraint->idxmsk,
+				       X86_PMC_IDX_MAX);
+
+		if (eventsel)
+			base = MSR_F15H_NB_PERF_CTL - x86_pmu.eventsel;
+		else
+			base = MSR_F15H_NB_PERF_CTR - x86_pmu.perfctr;
+
+		offset = base + ((index - first) << 1);
+	} else if (!cpu_has_perfctr_core)
 		offset = index;
 	else
 		offset = index << 1;
@@ -175,24 +198,36 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
 
 static inline int amd_pmu_rdpmc_index(int index)
 {
-	return index;
-}
+	int ret, first;
 
-static int amd_pmu_hw_config(struct perf_event *event)
-{
-	int ret;
+	if (!index)
+		return index;
 
-	/* pass precise event sampling to ibs: */
-	if (event->attr.precise_ip && get_ibs_caps())
-		return -ENOENT;
+	ret = rdpmc_indexes[index];
 
-	ret = x86_pmu_hw_config(event);
 	if (ret)
 		return ret;
 
-	if (has_branch_stack(event))
-		return -EOPNOTSUPP;
+	if (amd_nb_event_constraint &&
+	    test_bit(index, amd_nb_event_constraint->idxmsk)) {
+		/*
+		 * according to the mnual, ECX value of the NB counters is
+		 * the index of the NB counter (0, 1, 2 or 3) plus 6
+		 */
+
+		first = find_first_bit(amd_nb_event_constraint->idxmsk,
+				       X86_PMC_IDX_MAX);
+		ret = index - first + 6;
+	} else
+		ret = index;
+
+	rdpmc_indexes[index] = ret;
 
+	return ret;
+}
+
+static int amd_core_hw_config(struct perf_event *event)
+{
 	if (event->attr.exclude_host && event->attr.exclude_guest)
 		/*
 		 * When HO == GO == 1 the hardware treats that as GO == HO == 0
@@ -206,10 +241,33 @@ static int amd_pmu_hw_config(struct perf_event *event)
 	else if (event->attr.exclude_guest)
 		event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
 
-	if (event->attr.type != PERF_TYPE_RAW)
-		return 0;
+	return 0;
+}
 
-	event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
+/*
+ * NB counters do not support the following event select bits:
+ *   Host/Guest only
+ *   Counter mask
+ *   Invert counter mask
+ *   Edge detect
+ *   OS/User mode
+ */
+static int amd_nb_hw_config(struct perf_event *event)
+{
+	/* for NB, we only allow system wide counting mode */
+	if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+		return -EINVAL;
+
+	if (event->attr.exclude_user || event->attr.exclude_kernel ||
+	    event->attr.exclude_host || event->attr.exclude_guest)
+		return -EINVAL;
+
+	event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
+			      ARCH_PERFMON_EVENTSEL_OS);
+
+	if (event->hw.config & ~(AMD64_RAW_EVENT_MASK_NB |
+				 ARCH_PERFMON_EVENTSEL_INT))
+		return -EINVAL;
 
 	return 0;
 }
@@ -227,6 +285,11 @@ static inline int amd_is_nb_event(struct hw_perf_event *hwc)
 	return (hwc->config & 0xe0) == 0xe0;
 }
 
+static inline int amd_is_perfctr_nb_event(struct hw_perf_event *hwc)
+{
+	return amd_nb_event_constraint && amd_is_nb_event(hwc);
+}
+
 static inline int amd_has_nb(struct cpu_hw_events *cpuc)
 {
 	struct amd_nb *nb = cpuc->amd_nb;
@@ -234,6 +297,30 @@ static inline int amd_has_nb(struct cpu_hw_events *cpuc)
 	return nb && nb->nb_id != -1;
 }
 
+static int amd_pmu_hw_config(struct perf_event *event)
+{
+	int ret;
+
+	/* pass precise event sampling to ibs: */
+	if (event->attr.precise_ip && get_ibs_caps())
+		return -ENOENT;
+
+	if (has_branch_stack(event))
+		return -EOPNOTSUPP;
+
+	ret = x86_pmu_hw_config(event);
+	if (ret)
+		return ret;
+
+	if (event->attr.type == PERF_TYPE_RAW)
+		event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
+
+	if (amd_is_perfctr_nb_event(&event->hw))
+		return amd_nb_hw_config(event);
+
+	return amd_core_hw_config(event);
+}
+
 static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
 					   struct perf_event *event)
 {
@@ -254,6 +341,19 @@ static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
 	}
 }
 
+static void amd_nb_interrupt_hw_config(struct hw_perf_event *hwc)
+{
+	int core_id = cpu_data(smp_processor_id()).cpu_core_id;
+
+	/* deliver interrupts only to this core */
+	if (hwc->config & ARCH_PERFMON_EVENTSEL_INT) {
+		hwc->config |= AMD64_EVENTSEL_INT_CORE_ENABLE;
+		hwc->config &= ~AMD64_EVENTSEL_INT_CORE_SEL_MASK;
+		hwc->config |= (u64)(core_id) <<
+			AMD64_EVENTSEL_INT_CORE_SEL_SHIFT;
+	}
+}
+
  /*
   * AMD64 NorthBridge events need special treatment because
   * counter access needs to be synchronized across all cores
@@ -299,6 +399,12 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
 	struct perf_event *old;
 	int idx, new = -1;
 
+	if (!c)
+		c = &unconstrained;
+
+	if (cpuc->is_fake)
+		return c;
+
 	/*
 	 * detect if already present, if so reuse
 	 *
@@ -335,6 +441,9 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
 	if (new == -1)
 		return &emptyconstraint;
 
+	if (amd_is_perfctr_nb_event(hwc))
+		amd_nb_interrupt_hw_config(hwc);
+
 	return &nb->event_constraints[new];
 }
 
@@ -434,7 +543,8 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 	if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
 		return &unconstrained;
 
-	return __amd_get_nb_event_constraints(cpuc, event, &unconstrained);
+	return __amd_get_nb_event_constraints(cpuc, event,
+					      amd_nb_event_constraint);
 }
 
 static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
@@ -533,6 +643,9 @@ static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09,
 static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
 static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
 
+static struct event_constraint amd_NBPMC96 = EVENT_CONSTRAINT(0, 0x3C0, 0);
+static struct event_constraint amd_NBPMC74 = EVENT_CONSTRAINT(0, 0xF0, 0);
+
 static struct event_constraint *
 amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
 {
@@ -598,8 +711,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev
 			return &amd_f15_PMC20;
 		}
 	case AMD_EVENT_NB:
-		/* not yet implemented */
-		return &emptyconstraint;
+		return __amd_get_nb_event_constraints(cpuc, event,
+						      amd_nb_event_constraint);
 	default:
 		return &emptyconstraint;
 	}
@@ -647,7 +760,7 @@ static __initconst const struct x86_pmu amd_pmu = {
 
 static int setup_event_constraints(void)
 {
-	if (boot_cpu_data.x86 >= 0x15)
+	if (boot_cpu_data.x86 == 0x15)
 		x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
 	return 0;
 }
@@ -677,6 +790,23 @@ static int setup_perfctr_core(void)
 	return 0;
 }
 
+static int setup_perfctr_nb(void)
+{
+	if (!cpu_has_perfctr_nb)
+		return -ENODEV;
+
+	x86_pmu.num_counters += AMD64_NUM_COUNTERS_NB;
+
+	if (cpu_has_perfctr_core)
+		amd_nb_event_constraint = &amd_NBPMC96;
+	else
+		amd_nb_event_constraint = &amd_NBPMC74;
+
+	printk(KERN_INFO "perf: AMD northbridge performance counters detected\n");
+
+	return 0;
+}
+
 __init int amd_pmu_init(void)
 {
 	/* Performance-monitoring supported from K7 and later: */
@@ -687,6 +817,7 @@ __init int amd_pmu_init(void)
 
 	setup_event_constraints();
 	setup_perfctr_core();
+	setup_perfctr_nb();
 
 	/* Events are common for all AMDs */
 	memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
-- 
1.7.9.5