* [PATCH 1/5] perf: Add hardware breakpoint address mask
2012-12-12 16:30 [PATCH 0/5] perf: Add support for hardware breakpoint address masks Jacob Shin
@ 2012-12-12 16:30 ` Jacob Shin
2012-12-12 16:30 ` [PATCH 2/5] perf, x86: AMD implementation for " Jacob Shin
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Jacob Shin @ 2012-12-12 16:30 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, x86
Cc: Peter Zijlstra, Paul Mackerras, Arnaldo Carvalho de Melo,
Stephane Eranian, Suravee Suthikulpanit, linux-kernel,
Jacob Shin
Some architectures (for us, AMD Family 16h) allow for "don't care" bit
mask to further qualify a hardware breakpoint address, in order to
trap on range of addresses. Update perf uapi to add bp_addr_mask field
and define HAVE_HW_BREAKPOINT_ADDR_MASK.
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
arch/Kconfig | 4 ++++
include/linux/hw_breakpoint.h | 6 ++++++
include/uapi/linux/perf_event.h | 5 ++++-
kernel/events/hw_breakpoint.c | 3 +++
4 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index cc74aae..0bf366f 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -201,6 +201,10 @@ config HAVE_HW_BREAKPOINT
bool
depends on PERF_EVENTS
+config HAVE_HW_BREAKPOINT_ADDR_MASK
+ bool
+ depends on HAVE_HW_BREAKPOINT
+
config HAVE_MIXED_BREAKPOINTS_REGS
bool
depends on HAVE_HW_BREAKPOINT
diff --git a/include/linux/hw_breakpoint.h b/include/linux/hw_breakpoint.h
index 0464c85..9384201 100644
--- a/include/linux/hw_breakpoint.h
+++ b/include/linux/hw_breakpoint.h
@@ -84,6 +84,12 @@ static inline struct arch_hw_breakpoint *counter_arch_bp(struct perf_event *bp)
return &bp->hw.info;
}
+#ifdef CONFIG_HAVE_HW_BREAKPOINT_ADDR_MASK
+extern int arch_has_hw_breakpoint_addr_mask(void);
+#else
+static inline int arch_has_hw_breakpoint_addr_mask(void) { return 0; }
+#endif /* CONFIG_HAVE_HW_BREAKPOINT_ADDR_MASK */
+
#else /* !CONFIG_HAVE_HW_BREAKPOINT */
static inline int __init init_hw_breakpoint(void) { return 0; }
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 4f63c05..067d315 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -284,7 +284,10 @@ struct perf_event_attr {
__u64 config1; /* extension of config */
};
union {
- __u64 bp_len;
+ struct {
+ __u32 bp_len;
+ __u32 bp_addr_mask;
+ };
__u64 config2; /* extension of config1 */
};
__u64 branch_sample_type; /* enum perf_branch_sample_type */
diff --git a/kernel/events/hw_breakpoint.c b/kernel/events/hw_breakpoint.c
index fe8a916..6f10baa 100644
--- a/kernel/events/hw_breakpoint.c
+++ b/kernel/events/hw_breakpoint.c
@@ -612,6 +612,9 @@ static int hw_breakpoint_add(struct perf_event *bp, int flags)
if (!(flags & PERF_EF_START))
bp->hw.state = PERF_HES_STOPPED;
+ if (bp->attr.bp_addr_mask && !arch_has_hw_breakpoint_addr_mask())
+ return -EOPNOTSUPP;
+
return arch_install_hw_breakpoint(bp);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/5] perf, x86: AMD implementation for hardware breakpoint address mask
2012-12-12 16:30 [PATCH 0/5] perf: Add support for hardware breakpoint address masks Jacob Shin
2012-12-12 16:30 ` [PATCH 1/5] perf: Add hardware breakpoint address mask Jacob Shin
@ 2012-12-12 16:30 ` Jacob Shin
2012-12-12 16:30 ` [PATCH 3/5] perf tools: Add breakpoint address mask to the mem event parser Jacob Shin
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Jacob Shin @ 2012-12-12 16:30 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, x86
Cc: Peter Zijlstra, Paul Mackerras, Arnaldo Carvalho de Melo,
Stephane Eranian, Suravee Suthikulpanit, linux-kernel,
Jacob Shin
Implement hardware breakpoint address mask for AMD Family 16h (and
any other future) processors. CPUID feature bit indicates the hardware
support for DRn_ADDR_MASK MSRs.
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
arch/x86/Kconfig | 1 +
arch/x86/include/asm/cpufeature.h | 2 ++
arch/x86/include/asm/hw_breakpoint.h | 6 ++++++
arch/x86/include/asm/msr-index.h | 6 ++++++
arch/x86/include/asm/processor.h | 7 +++++++
arch/x86/kernel/cpu/amd.c | 21 +++++++++++++++++++++
arch/x86/kernel/hw_breakpoint.c | 5 +++++
7 files changed, 48 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index b6538bd..f7b3aa2 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -64,6 +64,7 @@ config X86
select HAVE_KERNEL_XZ
select HAVE_KERNEL_LZO
select HAVE_HW_BREAKPOINT
+ select HAVE_HW_BREAKPOINT_ADDR_MASK
select HAVE_MIXED_BREAKPOINTS_REGS
select PERF_EVENTS
select HAVE_PERF_EVENTS_NMI
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index da40b1e..c36870c 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -167,6 +167,7 @@
#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
+#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
/*
* Auxiliary flags: Linux defined - For features scattered in various
@@ -312,6 +313,7 @@ extern const char * const x86_power_flags[32];
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
+#define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT)
#ifdef CONFIG_X86_64
diff --git a/arch/x86/include/asm/hw_breakpoint.h b/arch/x86/include/asm/hw_breakpoint.h
index 824ca07..c8ecd29 100644
--- a/arch/x86/include/asm/hw_breakpoint.h
+++ b/arch/x86/include/asm/hw_breakpoint.h
@@ -13,6 +13,7 @@ struct arch_hw_breakpoint {
unsigned long address;
u8 len;
u8 type;
+ u32 mask;
};
#include <linux/kdebug.h>
@@ -71,6 +72,11 @@ extern int arch_bp_generic_fields(int x86_len, int x86_type,
extern struct pmu perf_ops_bp;
+static inline int arch_has_hw_breakpoint_addr_mask(void)
+{
+ return cpu_has_bpext;
+}
+
#endif /* __KERNEL__ */
#endif /* _I386_HW_BREAKPOINT_H */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e400cdb..3b8a5b4 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -154,6 +154,12 @@
#define MSR_AMD64_IBSBRTARGET 0xc001103b
#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
+/* Fam 16h MSRs */
+#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
+#define MSR_F16H_DR1_ADDR_MASK 0xc0011019
+#define MSR_F16H_DR2_ADDR_MASK 0xc001101a
+#define MSR_F16H_DR3_ADDR_MASK 0xc001101b
+
/* Fam 15h MSRs */
#define MSR_F15H_PERF_CTL 0xc0010200
#define MSR_F15H_PERF_CTR 0xc0010201
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index e101b38..26a33b4 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -992,8 +992,15 @@ extern bool cpu_has_amd_erratum(const int *);
#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
+extern void set_dr_addr_mask(u32 mask, int dr);
+
#else
#define cpu_has_amd_erratum(x) (false)
+
+static inline void set_dr_addr_mask(u32 mask, int dr)
+{
+}
+
#endif /* CONFIG_CPU_SUP_AMD */
extern unsigned long arch_align_stack(unsigned long sp);
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 15239ff..5b0f676 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -906,3 +906,24 @@ bool cpu_has_amd_erratum(const int *erratum)
}
EXPORT_SYMBOL_GPL(cpu_has_amd_erratum);
+
+void set_dr_addr_mask(u32 mask, int dr)
+{
+ if (!cpu_has_bpext)
+ return;
+
+ BUG_ON(dr >= HBP_NUM);
+
+ switch (dr) {
+ case 0:
+ wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
+ break;
+ case 1:
+ case 2:
+ case 3:
+ wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
+ break;
+ default:
+ break;
+ }
+}
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index 02f0763..f8bf2df 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -121,6 +121,8 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
return -EBUSY;
+ set_dr_addr_mask(info->mask, i);
+
set_debugreg(info->address, i);
__this_cpu_write(cpu_debugreg[i], info->address);
@@ -163,6 +165,8 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
*dr7 &= ~__encode_dr7(i, info->len, info->type);
set_debugreg(*dr7, 7);
+
+ set_dr_addr_mask(0, i);
}
static int get_hbp_len(u8 hbp_len)
@@ -254,6 +258,7 @@ static int arch_build_bp_info(struct perf_event *bp)
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
info->address = bp->attr.bp_addr;
+ info->mask = bp->attr.bp_addr_mask;
/* Type */
switch (bp->attr.bp_type) {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/5] perf tools: Add breakpoint address mask to the mem event parser
2012-12-12 16:30 [PATCH 0/5] perf: Add support for hardware breakpoint address masks Jacob Shin
2012-12-12 16:30 ` [PATCH 1/5] perf: Add hardware breakpoint address mask Jacob Shin
2012-12-12 16:30 ` [PATCH 2/5] perf, x86: AMD implementation for " Jacob Shin
@ 2012-12-12 16:30 ` Jacob Shin
2012-12-12 16:30 ` [PATCH 4/5] perf tools: Add breakpoint address mask syntax to perf list and documentation Jacob Shin
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Jacob Shin @ 2012-12-12 16:30 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, x86
Cc: Peter Zijlstra, Paul Mackerras, Arnaldo Carvalho de Melo,
Stephane Eranian, Suravee Suthikulpanit, linux-kernel,
Jacob Shin
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Allow perf tool to pass in breakpoint address mask to match an address
range, i.e.:
$ perf stat -e mem:0x1000:w:0xf a.out
Will count writes to [0x1000 ~ 0x1010)
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
tools/perf/util/parse-events.c | 3 ++-
tools/perf/util/parse-events.h | 2 +-
tools/perf/util/parse-events.y | 14 ++++++++++++--
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
index 2d8d53be..2679e48 100644
--- a/tools/perf/util/parse-events.c
+++ b/tools/perf/util/parse-events.c
@@ -466,12 +466,13 @@ do { \
}
int parse_events_add_breakpoint(struct list_head **list, int *idx,
- void *ptr, char *type)
+ void *ptr, char *type, void *msk)
{
struct perf_event_attr attr;
memset(&attr, 0, sizeof(attr));
attr.bp_addr = (unsigned long) ptr;
+ attr.bp_addr_mask = (unsigned long) msk;
if (parse_breakpoint_type(type, &attr))
return -EINVAL;
diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h
index b7af80b..5b7905c 100644
--- a/tools/perf/util/parse-events.h
+++ b/tools/perf/util/parse-events.h
@@ -92,7 +92,7 @@ int parse_events_add_numeric(struct list_head **list, int *idx,
int parse_events_add_cache(struct list_head **list, int *idx,
char *type, char *op_result1, char *op_result2);
int parse_events_add_breakpoint(struct list_head **list, int *idx,
- void *ptr, char *type);
+ void *ptr, char *type, void *msk);
int parse_events_add_pmu(struct list_head **list, int *idx,
char *pmu , struct list_head *head_config);
void parse_events__set_leader(char *name, struct list_head *list);
diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y
index 0f9914a..e8ac05d 100644
--- a/tools/perf/util/parse-events.y
+++ b/tools/perf/util/parse-events.y
@@ -254,13 +254,23 @@ PE_NAME_CACHE_TYPE
}
event_legacy_mem:
+PE_PREFIX_MEM PE_VALUE ':' PE_MODIFIER_BP ':' PE_VALUE sep_dc
+{
+ struct parse_events_data__events *data = _data;
+ struct list_head *list = NULL;
+
+ ABORT_ON(parse_events_add_breakpoint(&list, &data->idx,
+ (void *) $2, $4, (void *) $6));
+ $$ = list;
+}
+|
PE_PREFIX_MEM PE_VALUE ':' PE_MODIFIER_BP sep_dc
{
struct parse_events_data__events *data = _data;
struct list_head *list = NULL;
ABORT_ON(parse_events_add_breakpoint(&list, &data->idx,
- (void *) $2, $4));
+ (void *) $2, $4, NULL));
$$ = list;
}
|
@@ -270,7 +280,7 @@ PE_PREFIX_MEM PE_VALUE sep_dc
struct list_head *list = NULL;
ABORT_ON(parse_events_add_breakpoint(&list, &data->idx,
- (void *) $2, NULL));
+ (void *) $2, NULL, NULL));
$$ = list;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/5] perf tools: Add breakpoint address mask syntax to perf list and documentation
2012-12-12 16:30 [PATCH 0/5] perf: Add support for hardware breakpoint address masks Jacob Shin
` (2 preceding siblings ...)
2012-12-12 16:30 ` [PATCH 3/5] perf tools: Add breakpoint address mask to the mem event parser Jacob Shin
@ 2012-12-12 16:30 ` Jacob Shin
2012-12-12 16:30 ` [PATCH 5/5] perf tools: Add breakpoint address mask test case to tests/parse-events Jacob Shin
2012-12-14 15:49 ` [PATCH 0/5] perf: Add support for hardware breakpoint address masks Jacob Shin
5 siblings, 0 replies; 10+ messages in thread
From: Jacob Shin @ 2012-12-12 16:30 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, x86
Cc: Peter Zijlstra, Paul Mackerras, Arnaldo Carvalho de Melo,
Stephane Eranian, Suravee Suthikulpanit, linux-kernel,
Jacob Shin
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
tools/perf/Documentation/perf-record.txt | 14 ++++++++++----
tools/perf/util/parse-events.c | 2 +-
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt
index b38a1f9..a221a25 100644
--- a/tools/perf/Documentation/perf-record.txt
+++ b/tools/perf/Documentation/perf-record.txt
@@ -33,13 +33,19 @@ OPTIONS
- a raw PMU event (eventsel+umask) in the form of rNNN where NNN is a
hexadecimal event descriptor.
- - a hardware breakpoint event in the form of '\mem:addr[:access]'
- where addr is the address in memory you want to break in.
- Access is the memory access type (read, write, execute) it can
- be passed as follows: '\mem:addr[:[r][w][x]]'.
+ - a hardware breakpoint event in the form of
+ '\mem:addr[:access][:addr_mask]' where addr is the address in
+ memory you want to break in. Access is the memory access type (read,
+ write, execute) it can be passed as follows: '\mem:addr[:[r][w][x]]'.
+ addr_mask is the "don't care" bit mask to further qualify the given
+ addr, to break in on accesses to an address range.
+
If you want to profile read-write accesses in 0x1000, just set
'mem:0x1000:rw'.
+ If you want to profile write accesses in [0x1000 ~ 0x1010), just set
+ 'mem:0x1000:w:0xf'. (Only supported on some hardware)
+
--filter=<filter>::
Event filter.
diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
index 2679e48..6443735 100644
--- a/tools/perf/util/parse-events.c
+++ b/tools/perf/util/parse-events.c
@@ -1114,7 +1114,7 @@ void print_events(const char *event_glob, bool name_only)
printf("\n");
printf(" %-50s [%s]\n",
- "mem:<addr>[:access]",
+ "mem:<addr>[:access][:addr_mask]",
event_type_descriptors[PERF_TYPE_BREAKPOINT]);
printf("\n");
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 5/5] perf tools: Add breakpoint address mask test case to tests/parse-events
2012-12-12 16:30 [PATCH 0/5] perf: Add support for hardware breakpoint address masks Jacob Shin
` (3 preceding siblings ...)
2012-12-12 16:30 ` [PATCH 4/5] perf tools: Add breakpoint address mask syntax to perf list and documentation Jacob Shin
@ 2012-12-12 16:30 ` Jacob Shin
2012-12-14 15:49 ` [PATCH 0/5] perf: Add support for hardware breakpoint address masks Jacob Shin
5 siblings, 0 replies; 10+ messages in thread
From: Jacob Shin @ 2012-12-12 16:30 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, x86
Cc: Peter Zijlstra, Paul Mackerras, Arnaldo Carvalho de Melo,
Stephane Eranian, Suravee Suthikulpanit, linux-kernel,
Jacob Shin
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
tools/perf/tests/parse-events.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c
index 32ee478..394e16c 100644
--- a/tools/perf/tests/parse-events.c
+++ b/tools/perf/tests/parse-events.c
@@ -369,6 +369,32 @@ static int test__checkevent_breakpoint_rw_modifier(struct perf_evlist *evlist)
return test__checkevent_breakpoint_rw(evlist);
}
+static int test__checkevent_breakpoint_rw_addrmsk(struct perf_evlist *evlist)
+{
+ struct perf_evsel *evsel = perf_evlist__first(evlist);
+
+ TEST_ASSERT_VAL("wrong bp_addr_mask",
+ 0 == evsel->attr.bp_addr_mask);
+
+ return test__checkevent_breakpoint_rw(evlist);
+}
+
+static int test__checkevent_breakpoint_x_addrmsk_modifier(struct perf_evlist *evlist)
+{
+ struct perf_evsel *evsel = perf_evlist__first(evlist);
+
+ TEST_ASSERT_VAL("wrong exclude_user", evsel->attr.exclude_user);
+ TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->attr.exclude_kernel);
+ TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv);
+ TEST_ASSERT_VAL("wrong precise_ip", !evsel->attr.precise_ip);
+ TEST_ASSERT_VAL("wrong name",
+ !strcmp(perf_evsel__name(evsel), "mem:0:x:0:k"));
+ TEST_ASSERT_VAL("wrong bp_addr_mask",
+ 0 == evsel->attr.bp_addr_mask);
+
+ return test__checkevent_breakpoint_x(evlist);
+}
+
static int test__checkevent_pmu(struct perf_evlist *evlist)
{
@@ -921,6 +947,14 @@ static struct test__event_st test__events[] = {
.name = "{cycles,instructions}:G,{cycles:G,instructions:G},cycles",
.check = test__group5,
},
+ [33] = {
+ .name = "mem:0:rw:0",
+ .check = test__checkevent_breakpoint_rw_addrmsk,
+ },
+ [34] = {
+ .name = "mem:0:x:0:k",
+ .check = test__checkevent_breakpoint_x_addrmsk_modifier,
+ },
};
static struct test__event_st test__events_pmu[] = {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks
2012-12-12 16:30 [PATCH 0/5] perf: Add support for hardware breakpoint address masks Jacob Shin
` (4 preceding siblings ...)
2012-12-12 16:30 ` [PATCH 5/5] perf tools: Add breakpoint address mask test case to tests/parse-events Jacob Shin
@ 2012-12-14 15:49 ` Jacob Shin
5 siblings, 0 replies; 10+ messages in thread
From: Jacob Shin @ 2012-12-14 15:49 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, x86
Cc: Peter Zijlstra, Paul Mackerras, Arnaldo Carvalho de Melo,
Stephane Eranian, Suravee Suthikulpanit, linux-kernel
On Wed, Dec 12, 2012 at 10:30:38AM -0600, Jacob Shin wrote:
> The following patchset adds address masks to existing perf hardware
> breakpoint mechanism to allow trapping on an address range (currently
> only single address) on supported architectures.
>
> perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
> beyond) is provided, and perf tool has been extended to do:
>
> $ perf stat -e mem:0x1000:w:0xf a.out
> ^^^
> "don't care" bit mask
>
> which will count writes to [0x1000 ~ 0x1010)
>
> Jacob Shin (2):
> perf: Add hardware breakpoint address mask
> perf, x86: AMD implementation for hardware breakpoint address mask
>
> Suravee Suthikulpanit (3):
> perf tools: Add breakpoint address mask to the mem event parser
> perf tools: Add breakpoint address mask syntax to perf list and
> documentation
> perf tools: Add breakpoint address mask test case to
> tests/parse-events
>
> arch/Kconfig | 4 ++++
> arch/x86/Kconfig | 1 +
> arch/x86/include/asm/cpufeature.h | 2 ++
> arch/x86/include/asm/hw_breakpoint.h | 6 ++++++
> arch/x86/include/asm/msr-index.h | 6 ++++++
> arch/x86/include/asm/processor.h | 7 ++++++
> arch/x86/kernel/cpu/amd.c | 21 ++++++++++++++++++
> arch/x86/kernel/hw_breakpoint.c | 5 +++++
> include/linux/hw_breakpoint.h | 6 ++++++
> include/uapi/linux/perf_event.h | 5 ++++-
> kernel/events/hw_breakpoint.c | 3 +++
> tools/perf/Documentation/perf-record.txt | 14 ++++++++----
> tools/perf/tests/parse-events.c | 34 ++++++++++++++++++++++++++++++
> tools/perf/util/parse-events.c | 5 +++--
> tools/perf/util/parse-events.h | 2 +-
> tools/perf/util/parse-events.y | 14 ++++++++++--
> 16 files changed, 125 insertions(+), 10 deletions(-)
>
> --
Ping .. any comments / feedback ? If not, could you commit it into tip ?
Thank you,
-Jacob
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/5] perf, x86: AMD implementation for hardware breakpoint address mask
2013-04-09 17:21 Jacob Shin
@ 2013-04-09 17:21 ` Jacob Shin
2013-04-21 17:19 ` Oleg Nesterov
0 siblings, 1 reply; 10+ messages in thread
From: Jacob Shin @ 2013-04-09 17:21 UTC (permalink / raw)
To: Ingo Molnar, Peter Zijlstra, Arnaldo Carvalho de Melo
Cc: H. Peter Anvin, Thomas Gleixner, x86, Stephane Eranian,
Jiri Olsa, linux-kernel, Jacob Shin
Implement hardware breakpoint address mask for AMD Family 16h (and
any other future) processors. CPUID feature bit indicates the hardware
support for DRn_ADDR_MASK MSRs.
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
---
arch/x86/Kconfig | 1 +
arch/x86/include/asm/cpufeature.h | 2 ++
arch/x86/include/asm/debugreg.h | 7 +++++++
arch/x86/include/asm/hw_breakpoint.h | 6 ++++++
arch/x86/include/uapi/asm/msr-index.h | 6 ++++++
arch/x86/kernel/cpu/amd.c | 19 +++++++++++++++++++
arch/x86/kernel/hw_breakpoint.c | 5 +++++
7 files changed, 46 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 70c0f3d..eee63f8 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -65,6 +65,7 @@ config X86
select HAVE_KERNEL_XZ
select HAVE_KERNEL_LZO
select HAVE_HW_BREAKPOINT
+ select HAVE_HW_BREAKPOINT_ADDR_MASK
select HAVE_MIXED_BREAKPOINTS_REGS
select PERF_EVENTS
select HAVE_PERF_EVENTS_NMI
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 93fe929..eb4f3a7 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -168,6 +168,7 @@
#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
#define X86_FEATURE_PERFCTR_NB (6*32+24) /* NB performance counter extensions */
+#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
/*
* Auxiliary flags: Linux defined - For features scattered in various
@@ -315,6 +316,7 @@ extern const char * const x86_power_flags[32];
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
+#define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT)
#ifdef CONFIG_X86_64
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index 4b528a9..bb48949 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -114,5 +114,12 @@ static inline void debug_stack_usage_inc(void) { }
static inline void debug_stack_usage_dec(void) { }
#endif /* X86_64 */
+#ifdef CONFIG_CPU_SUP_AMD
+extern void set_dr_addr_mask(u32 mask, int dr);
+#else
+static inline void set_dr_addr_mask(u32 mask, int dr)
+{
+}
+#endif
#endif /* _ASM_X86_DEBUGREG_H */
diff --git a/arch/x86/include/asm/hw_breakpoint.h b/arch/x86/include/asm/hw_breakpoint.h
index ef1c4d2..c939415 100644
--- a/arch/x86/include/asm/hw_breakpoint.h
+++ b/arch/x86/include/asm/hw_breakpoint.h
@@ -14,6 +14,7 @@ struct arch_hw_breakpoint {
unsigned long address;
u8 len;
u8 type;
+ u32 mask;
};
#include <linux/kdebug.h>
@@ -72,4 +73,9 @@ extern int arch_bp_generic_fields(int x86_len, int x86_type,
extern struct pmu perf_ops_bp;
+static inline int arch_has_hw_breakpoint_addr_mask(void)
+{
+ return cpu_has_bpext;
+}
+
#endif /* _I386_HW_BREAKPOINT_H */
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index bf7bb68..b0b9335 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -196,6 +196,12 @@
#define MSR_AMD64_IBSBRTARGET 0xc001103b
#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
+/* Fam 16h MSRs */
+#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
+#define MSR_F16H_DR1_ADDR_MASK 0xc0011019
+#define MSR_F16H_DR2_ADDR_MASK 0xc001101a
+#define MSR_F16H_DR3_ADDR_MASK 0xc001101b
+
/* Fam 15h MSRs */
#define MSR_F15H_PERF_CTL 0xc0010200
#define MSR_F15H_PERF_CTR 0xc0010201
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index fa96eb0..aadc499 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -910,3 +910,22 @@ bool cpu_has_amd_erratum(const int *erratum)
}
EXPORT_SYMBOL_GPL(cpu_has_amd_erratum);
+
+void set_dr_addr_mask(u32 mask, int dr)
+{
+ if (!cpu_has_bpext)
+ return;
+
+ switch (dr) {
+ case 0:
+ wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
+ break;
+ case 1:
+ case 2:
+ case 3:
+ wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
+ break;
+ default:
+ break;
+ }
+}
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index 02f0763..f8bf2df 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -121,6 +121,8 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
return -EBUSY;
+ set_dr_addr_mask(info->mask, i);
+
set_debugreg(info->address, i);
__this_cpu_write(cpu_debugreg[i], info->address);
@@ -163,6 +165,8 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
*dr7 &= ~__encode_dr7(i, info->len, info->type);
set_debugreg(*dr7, 7);
+
+ set_dr_addr_mask(0, i);
}
static int get_hbp_len(u8 hbp_len)
@@ -254,6 +258,7 @@ static int arch_build_bp_info(struct perf_event *bp)
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
info->address = bp->attr.bp_addr;
+ info->mask = bp->attr.bp_addr_mask;
/* Type */
switch (bp->attr.bp_type) {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/5] perf, x86: AMD implementation for hardware breakpoint address mask
2013-04-09 17:21 ` [PATCH 2/5] perf, x86: AMD implementation for hardware breakpoint address mask Jacob Shin
@ 2013-04-21 17:19 ` Oleg Nesterov
2013-04-22 22:14 ` Jacob Shin
0 siblings, 1 reply; 10+ messages in thread
From: Oleg Nesterov @ 2013-04-21 17:19 UTC (permalink / raw)
To: Jacob Shin
Cc: Ingo Molnar, Peter Zijlstra, Arnaldo Carvalho de Melo,
H. Peter Anvin, Thomas Gleixner, x86, Stephane Eranian,
Jiri Olsa, linux-kernel
Not a comment, but the question...
On 04/09, Jacob Shin wrote:
>
> --- a/arch/x86/include/asm/hw_breakpoint.h
> +++ b/arch/x86/include/asm/hw_breakpoint.h
> @@ -14,6 +14,7 @@ struct arch_hw_breakpoint {
> unsigned long address;
> u8 len;
> u8 type;
> + u32 mask;
> };
...
> @@ -254,6 +258,7 @@ static int arch_build_bp_info(struct perf_event *bp)
> struct arch_hw_breakpoint *info = counter_arch_bp(bp);
>
> info->address = bp->attr.bp_addr;
> + info->mask = bp->attr.bp_addr_mask;
OK, this matches the usage of info->address so I think this change
is right.
But otoh, why do we need info->address (or mask added by this patch)?
we could use bp->attr.bp_addr instead. arch_hw_breakpoint could have
a single filed = "type | len" for encode_dr7().
Yes, off-topic, sorry for noise.
Oleg.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/5] perf, x86: AMD implementation for hardware breakpoint address mask
2013-04-21 17:19 ` Oleg Nesterov
@ 2013-04-22 22:14 ` Jacob Shin
0 siblings, 0 replies; 10+ messages in thread
From: Jacob Shin @ 2013-04-22 22:14 UTC (permalink / raw)
To: Oleg Nesterov
Cc: Ingo Molnar, Peter Zijlstra, Arnaldo Carvalho de Melo,
H. Peter Anvin, Thomas Gleixner, x86, Stephane Eranian,
Jiri Olsa, linux-kernel
On Sun, Apr 21, 2013 at 07:19:21PM +0200, Oleg Nesterov wrote:
> Not a comment, but the question...
>
> On 04/09, Jacob Shin wrote:
> >
> > --- a/arch/x86/include/asm/hw_breakpoint.h
> > +++ b/arch/x86/include/asm/hw_breakpoint.h
> > @@ -14,6 +14,7 @@ struct arch_hw_breakpoint {
> > unsigned long address;
> > u8 len;
> > u8 type;
> > + u32 mask;
> > };
> ...
> > @@ -254,6 +258,7 @@ static int arch_build_bp_info(struct perf_event *bp)
> > struct arch_hw_breakpoint *info = counter_arch_bp(bp);
> >
> > info->address = bp->attr.bp_addr;
> > + info->mask = bp->attr.bp_addr_mask;
>
> OK, this matches the usage of info->address so I think this change
> is right.
>
> But otoh, why do we need info->address (or mask added by this patch)?
> we could use bp->attr.bp_addr instead. arch_hw_breakpoint could have
> a single filed = "type | len" for encode_dr7().
I understood this as maybe remapping arch independant uapi struct into
x86 specific struct. I guess to future proof in cause uapi interfaces
change.
>
> Yes, off-topic, sorry for noise.
>
> Oleg.
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread