* [PATCH 0/4] Preparatory GIC patches for arm64 support
@ 2013-01-23 17:59 Catalin Marinas
2013-01-23 17:59 ` [PATCH 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h Catalin Marinas
` (3 more replies)
0 siblings, 4 replies; 18+ messages in thread
From: Catalin Marinas @ 2013-01-23 17:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
These patches are primarily aimed at reducing the irq-gic.c dependency
on arch/arm and allow it to be used with arch/arm64. The last patch
removes the explicit gic_secondary_init() call from the ARM platform
code.
We still have a non-generic asm/smp_plat.h include for cpu_logical_map()
but I couldn't find a better place to move it (asm/cpu.h isn't generic
either, though more widely used than smp_plat.h).
The patches are based on linux-next as they require Rob's GIC irqhip
move.
Catalin
Catalin Marinas (4):
arm: Move the set_handle_irq and handle_arch_irq declarations to
asm/irq.h
arm: Move chained_irq_(enter|exit) to a generic file
irqchip: gic: Call handle_bad_irq() directly
irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
arch/arm/include/asm/irq.h | 5 ++++
arch/arm/include/asm/mach/irq.h | 36 -----------------------
arch/arm/mach-at91/gpio.c | 3 +-
arch/arm/mach-exynos/common.c | 1 +
arch/arm/mach-exynos/platsmp.c | 8 -----
arch/arm/mach-highbank/platsmp.c | 7 -----
arch/arm/mach-imx/platsmp.c | 12 --------
arch/arm/mach-msm/platsmp.c | 8 -----
arch/arm/mach-omap2/omap-smp.c | 7 -----
arch/arm/mach-shmobile/smp-emev2.c | 7 -----
arch/arm/mach-shmobile/smp-r8a7779.c | 7 -----
arch/arm/mach-shmobile/smp-sh73a0.c | 7 -----
arch/arm/mach-socfpga/platsmp.c | 12 --------
arch/arm/mach-spear13xx/platsmp.c | 8 -----
arch/arm/mach-tegra/platsmp.c | 8 -----
arch/arm/mach-ux500/platsmp.c | 8 -----
arch/arm/plat-samsung/irq-vic-timer.c | 3 +-
arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +-
arch/arm/plat-versatile/platsmp.c | 8 -----
drivers/irqchip/irq-gic.c | 32 ++++++++++++++------
drivers/irqchip/irq-vic.c | 2 +-
include/linux/irqchip/arm-gic.h | 1 -
include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++++++
23 files changed, 85 insertions(+), 160 deletions(-)
create mode 100644 include/linux/irqchip/chained_irq.h
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h
2013-01-23 17:59 [PATCH 0/4] Preparatory GIC patches for arm64 support Catalin Marinas
@ 2013-01-23 17:59 ` Catalin Marinas
2013-01-23 17:59 ` [PATCH 2/4] arm: Move chained_irq_(enter|exit) to a generic file Catalin Marinas
` (2 subsequent siblings)
3 siblings, 0 replies; 18+ messages in thread
From: Catalin Marinas @ 2013-01-23 17:59 UTC (permalink / raw)
To: linux-arm-kernel
This patch prepares the removal of <asm/mach/irq.h> include in the
GIC and VIC irqchip drivers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
---
arch/arm/include/asm/irq.h | 5 +++++
arch/arm/include/asm/mach/irq.h | 5 -----
drivers/irqchip/irq-vic.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 35c21c3..53c15de 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *);
void handle_IRQ(unsigned int, struct pt_regs *);
void init_IRQ(void);
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+extern void (*handle_arch_irq)(struct pt_regs *);
+extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
+#endif
+
#endif
#endif
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 18c8830..749d505 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -20,11 +20,6 @@ struct seq_file;
extern void init_FIQ(int);
extern int show_fiq_list(struct seq_file *, int);
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-extern void (*handle_arch_irq)(struct pt_regs *);
-extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
-#endif
-
/*
* This is for easy migration, but should be changed in the source
*/
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 3cf97aa..e38cb00 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -33,7 +33,7 @@
#include <linux/irqchip/arm-vic.h>
#include <asm/exception.h>
-#include <asm/mach/irq.h>
+#include <asm/irq.h>
#include "irqchip.h"
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/4] arm: Move chained_irq_(enter|exit) to a generic file
2013-01-23 17:59 [PATCH 0/4] Preparatory GIC patches for arm64 support Catalin Marinas
2013-01-23 17:59 ` [PATCH 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h Catalin Marinas
@ 2013-01-23 17:59 ` Catalin Marinas
2013-01-24 5:32 ` Santosh Shilimkar
2013-01-23 17:59 ` [PATCH 3/4] irqchip: gic: Call handle_bad_irq() directly Catalin Marinas
2013-01-23 17:59 ` [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas
3 siblings, 1 reply; 18+ messages in thread
From: Catalin Marinas @ 2013-01-23 17:59 UTC (permalink / raw)
To: linux-arm-kernel
These functions have been introduced by commit 10a8c383 (irq: introduce
entry and exit functions for chained handlers) in asm/mach/irq.h. This
patch moves them to linux/irqchip/chained_irq.h so that generic irqchip
drivers do not rely on architecture specific header files.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
---
arch/arm/include/asm/mach/irq.h | 31 --------------------
arch/arm/mach-at91/gpio.c | 3 +-
arch/arm/mach-exynos/common.c | 1 +
arch/arm/plat-samsung/irq-vic-timer.c | 3 +-
arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +-
drivers/irqchip/irq-gic.c | 2 +-
include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++++++
7 files changed, 57 insertions(+), 38 deletions(-)
create mode 100644 include/linux/irqchip/chained_irq.h
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 749d505..2092ee1 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -30,35 +30,4 @@ do { \
raw_spin_unlock(&desc->lock); \
} while(0)
-#ifndef __ASSEMBLY__
-/*
- * Entry/exit functions for chained handlers where the primary IRQ chip
- * may implement either fasteoi or level-trigger flow control.
- */
-static inline void chained_irq_enter(struct irq_chip *chip,
- struct irq_desc *desc)
-{
- /* FastEOI controllers require no action on entry. */
- if (chip->irq_eoi)
- return;
-
- if (chip->irq_mask_ack) {
- chip->irq_mask_ack(&desc->irq_data);
- } else {
- chip->irq_mask(&desc->irq_data);
- if (chip->irq_ack)
- chip->irq_ack(&desc->irq_data);
- }
-}
-
-static inline void chained_irq_exit(struct irq_chip *chip,
- struct irq_desc *desc)
-{
- if (chip->irq_eoi)
- chip->irq_eoi(&desc->irq_data);
- else
- chip->irq_unmask(&desc->irq_data);
-}
-#endif
-
#endif
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index c5d7e1e..e3a64cf 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -23,8 +23,7 @@
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
-
-#include <asm/mach/irq.h>
+#include <linux/irqchip/chained_irq.h>
#include <mach/hardware.h>
#include <mach/at91_pio.h>
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 7f01a92..60dad95 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -25,6 +25,7 @@
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/chained_irq.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index f980cf3..047a2f8 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -17,14 +17,13 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
+#include <linux/irqchip/chained_irq.h>
#include <mach/map.h>
#include <plat/cpu.h>
#include <plat/irq-vic-timer.h>
#include <plat/regs-timer.h>
-#include <asm/mach/irq.h>
-
static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
index bae5613..d450671 100644
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c
@@ -17,13 +17,12 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
+#include <linux/irqchip/chained_irq.h>
#include <mach/map.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
-#include <asm/mach/irq.h>
-
#define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
#define CON_OFFSET 0x700
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 69d9a39..54b86f0 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -38,12 +38,12 @@
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/slab.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/irq.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
-#include <asm/mach/irq.h>
#include "irqchip.h"
diff --git a/include/linux/irqchip/chained_irq.h b/include/linux/irqchip/chained_irq.h
new file mode 100644
index 0000000..adf4c30
--- /dev/null
+++ b/include/linux/irqchip/chained_irq.h
@@ -0,0 +1,52 @@
+/*
+ * Chained IRQ handlers support.
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __IRQCHIP_CHAINED_IRQ_H
+#define __IRQCHIP_CHAINED_IRQ_H
+
+#include <linux/irq.h>
+
+/*
+ * Entry/exit functions for chained handlers where the primary IRQ chip
+ * may implement either fasteoi or level-trigger flow control.
+ */
+static inline void chained_irq_enter(struct irq_chip *chip,
+ struct irq_desc *desc)
+{
+ /* FastEOI controllers require no action on entry. */
+ if (chip->irq_eoi)
+ return;
+
+ if (chip->irq_mask_ack) {
+ chip->irq_mask_ack(&desc->irq_data);
+ } else {
+ chip->irq_mask(&desc->irq_data);
+ if (chip->irq_ack)
+ chip->irq_ack(&desc->irq_data);
+ }
+}
+
+static inline void chained_irq_exit(struct irq_chip *chip,
+ struct irq_desc *desc)
+{
+ if (chip->irq_eoi)
+ chip->irq_eoi(&desc->irq_data);
+ else
+ chip->irq_unmask(&desc->irq_data);
+}
+
+#endif /* __IRQCHIP_CHAINED_IRQ_H */
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/4] irqchip: gic: Call handle_bad_irq() directly
2013-01-23 17:59 [PATCH 0/4] Preparatory GIC patches for arm64 support Catalin Marinas
2013-01-23 17:59 ` [PATCH 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h Catalin Marinas
2013-01-23 17:59 ` [PATCH 2/4] arm: Move chained_irq_(enter|exit) to a generic file Catalin Marinas
@ 2013-01-23 17:59 ` Catalin Marinas
2013-01-23 17:59 ` [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas
3 siblings, 0 replies; 18+ messages in thread
From: Catalin Marinas @ 2013-01-23 17:59 UTC (permalink / raw)
To: linux-arm-kernel
Previously, the gic_handle_cascade_irq() function was calling the
ARM-specific do_bad_IRQ() function which calls handle_bad_irq() after
acquiring the desk->lock. Locking the cascaded IRQ desc is not needed
for error reporting, so just call handle_bad_irq() directly.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
---
drivers/irqchip/irq-gic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 54b86f0..ef1429a 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -323,7 +323,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
if (unlikely(gic_irq < 32 || gic_irq > 1020))
- do_bad_IRQ(cascade_irq, desc);
+ handle_bad_irq(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-23 17:59 [PATCH 0/4] Preparatory GIC patches for arm64 support Catalin Marinas
` (2 preceding siblings ...)
2013-01-23 17:59 ` [PATCH 3/4] irqchip: gic: Call handle_bad_irq() directly Catalin Marinas
@ 2013-01-23 17:59 ` Catalin Marinas
2013-01-23 18:28 ` Stephen Warren
` (6 more replies)
3 siblings, 7 replies; 18+ messages in thread
From: Catalin Marinas @ 2013-01-23 17:59 UTC (permalink / raw)
To: linux-arm-kernel
All the calls to gic_secondary_init() pass 0 as the first argument.
Since this function is called on each CPU when starting, it can be done
in a platform-independent way via a CPU notifier registered by the GIC
code.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Simon Horman <horms@verge.net.au>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
---
Randomly chosen CPU notifier priority. I can add a definition somewhere
though they don't seem to be used much and cause conflicts.
arch/arm/mach-exynos/platsmp.c | 8 --------
arch/arm/mach-highbank/platsmp.c | 7 -------
arch/arm/mach-imx/platsmp.c | 12 ------------
arch/arm/mach-msm/platsmp.c | 8 --------
arch/arm/mach-omap2/omap-smp.c | 7 -------
arch/arm/mach-shmobile/smp-emev2.c | 7 -------
arch/arm/mach-shmobile/smp-r8a7779.c | 7 -------
arch/arm/mach-shmobile/smp-sh73a0.c | 7 -------
arch/arm/mach-socfpga/platsmp.c | 12 ------------
arch/arm/mach-spear13xx/platsmp.c | 8 --------
arch/arm/mach-tegra/platsmp.c | 8 --------
arch/arm/mach-ux500/platsmp.c | 8 --------
arch/arm/plat-versatile/platsmp.c | 8 --------
drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++-------
include/linux/irqchip/arm-gic.h | 1 -
15 files changed, 21 insertions(+), 115 deletions(-)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a083e05..a0e8ff7 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -20,7 +20,6 @@
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
index 8797a70..a984573 100644
--- a/arch/arm/mach-highbank/platsmp.c
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -17,7 +17,6 @@
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/smp_scu.h>
@@ -25,11 +24,6 @@
extern void secondary_startup(void);
-static void __cpuinit highbank_secondary_init(unsigned int cpu)
-{
- gic_secondary_init(0);
-}
-
static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
highbank_set_cpu_jump(cpu, secondary_startup);
@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
struct smp_operations highbank_smp_ops __initdata = {
.smp_init_cpus = highbank_smp_init_cpus,
.smp_prepare_cpus = highbank_smp_prepare_cpus,
- .smp_secondary_init = highbank_secondary_init,
.smp_boot_secondary = highbank_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = highbank_cpu_die,
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index b2872ec..7f63dda 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -12,7 +12,6 @@
#include <linux/init.h>
#include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/page.h>
#include <asm/smp_scu.h>
#include <asm/mach/map.h>
@@ -42,16 +41,6 @@ void __init imx_scu_map_io(void)
scu_base = IMX_IO_ADDRESS(base);
}
-static void __cpuinit imx_secondary_init(unsigned int cpu)
-{
- /*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-}
-
static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
imx_set_cpu_jump(cpu, v7_secondary_startup);
@@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
struct smp_operations imx_smp_ops __initdata = {
.smp_init_cpus = imx_smp_init_cpus,
.smp_prepare_cpus = imx_smp_prepare_cpus,
- .smp_secondary_init = imx_secondary_init,
.smp_boot_secondary = imx_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = imx_cpu_die,
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 42932865..00cdb0a 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -15,7 +15,6 @@
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
@@ -42,13 +41,6 @@ static inline int get_core_count(void)
static void __cpuinit msm_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 3616779..c6ce880 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
4, 0, 0, 0, 0, 0);
/*
- * If any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 953eb1f..384e27d 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -23,7 +23,6 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
#include <mach/emev2.h>
#include <asm/smp_plat.h>
@@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
}
-static void __cpuinit emev2_secondary_init(unsigned int cpu)
-{
- gic_secondary_init(0);
-}
-
static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
cpu = cpu_logical_map(cpu);
@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)
struct smp_operations emev2_smp_ops __initdata = {
.smp_init_cpus = emev2_smp_init_cpus,
.smp_prepare_cpus = emev2_smp_prepare_cpus,
- .smp_secondary_init = emev2_secondary_init,
.smp_boot_secondary = emev2_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = emev2_cpu_kill,
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 3a4acf2..9949065 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -23,7 +23,6 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
#include <mach/r8a7779.h>
#include <asm/smp_plat.h>
@@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
}
-static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
-{
- gic_secondary_init(0);
-}
-
static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
struct r8a7779_pm_ch *ch = NULL;
@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)
struct smp_operations r8a7779_smp_ops __initdata = {
.smp_init_cpus = r8a7779_smp_init_cpus,
.smp_prepare_cpus = r8a7779_smp_prepare_cpus,
- .smp_secondary_init = r8a7779_secondary_init,
.smp_boot_secondary = r8a7779_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = r8a7779_cpu_kill,
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 9812ea3..f3b4912 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -23,7 +23,6 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)
return scu_get_core_count(scu_base);
}
-static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
-{
- gic_secondary_init(0);
-}
-
static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
cpu = cpu_logical_map(cpu);
@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)
struct smp_operations sh73a0_smp_ops __initdata = {
.smp_init_cpus = sh73a0_smp_init_cpus,
.smp_prepare_cpus = sh73a0_smp_prepare_cpus,
- .smp_secondary_init = sh73a0_secondary_init,
.smp_boot_secondary = sh73a0_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = sh73a0_cpu_kill,
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 4e9e69d..4b468ef 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -22,7 +22,6 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_scu.h>
@@ -33,16 +32,6 @@
extern void __iomem *sys_manager_base_addr;
extern void __iomem *rst_manager_base_addr;
-static void __cpuinit socfpga_secondary_init(unsigned int cpu)
-{
- /*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-}
-
static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
@@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)
struct smp_operations socfpga_smp_ops __initdata = {
.smp_init_cpus = socfpga_smp_init_cpus,
.smp_prepare_cpus = socfpga_smp_prepare_cpus,
- .smp_secondary_init = socfpga_secondary_init,
.smp_boot_secondary = socfpga_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = socfpga_cpu_die,
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
index af4ade6..551c69c 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -15,7 +15,6 @@
#include <linux/jiffies.h>
#include <linux/io.h>
#include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_scu.h>
#include <mach/spear.h>
@@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index c72e249..dea94d2 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -18,7 +18,6 @@
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <linux/clk/tegra.h>
#include <asm/cacheflush.h>
@@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
static void __cpuinit tegra_secondary_init(unsigned int cpu)
{
- /*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
}
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index b8adac9..b4d0735 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -16,7 +16,6 @@
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit ux500_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index f2ac155..1e1b2d7 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -14,7 +14,6 @@
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);
void __cpuinit versatile_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index ef1429a..f103cb8 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -28,6 +28,7 @@
#include <linux/module.h>
#include <linux/list.h>
#include <linux/smp.h>
+#include <linux/cpu.h>
#include <linux/cpu_pm.h>
#include <linux/cpumask.h>
#include <linux/io.h>
@@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
return 0;
}
+#ifdef CONFIG_SMP
+static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
+ unsigned long action, void *hcpu)
+{
+ if (action == CPU_STARTING)
+ gic_cpu_init(&gic_data[0]);
+ return NOTIFY_OK;
+}
+
+/*
+ * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
+ * priority because the GIC needs to be up before the ARM generic timers.
+ */
+static struct notifier_block __cpuinitdata gic_cpu_notifier = {
+ .notifier_call = gic_secondary_init,
+ .priority = 100,
+};
+#endif
+
const struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
.xlate = gic_irq_domain_xlate,
@@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
#ifdef CONFIG_SMP
set_smp_cross_call(gic_raise_softirq);
+ register_cpu_notifier(&gic_cpu_notifier);
#endif
set_handle_irq(gic_handle_irq);
@@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
gic_pm_init(gic);
}
-void __cpuinit gic_secondary_init(unsigned int gic_nr)
-{
- BUG_ON(gic_nr >= MAX_GIC_NR);
-
- gic_cpu_init(&gic_data[gic_nr]);
-}
-
#ifdef CONFIG_OF
static int gic_cnt __initdata = 0;
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index a67ca55..59e59b3 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn;
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
-void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
static inline void gic_init(unsigned int nr, int start,
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-23 17:59 ` [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas
@ 2013-01-23 18:28 ` Stephen Warren
2013-01-24 2:15 ` Viresh Kumar
` (5 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Stephen Warren @ 2013-01-23 18:28 UTC (permalink / raw)
To: linux-arm-kernel
On 01/23/2013 10:59 AM, Catalin Marinas wrote:
> All the calls to gic_secondary_init() pass 0 as the first argument.
> Since this function is called on each CPU when starting, it can be done
> in a platform-independent way via a CPU notifier registered by the GIC
> code.
Tegra part,
Acked-by: Stephen Warren <swarren@nvidia.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-23 17:59 ` [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas
2013-01-23 18:28 ` Stephen Warren
@ 2013-01-24 2:15 ` Viresh Kumar
2013-01-24 5:33 ` Santosh Shilimkar
` (4 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Viresh Kumar @ 2013-01-24 2:15 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 23, 2013 at 11:29 PM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
> All the calls to gic_secondary_init() pass 0 as the first argument.
> Since this function is called on each CPU when starting, it can be done
> in a platform-independent way via a CPU notifier registered by the GIC
> code.
> arch/arm/mach-spear13xx/platsmp.c | 8 --------
For SPEAr,
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/4] arm: Move chained_irq_(enter|exit) to a generic file
2013-01-23 17:59 ` [PATCH 2/4] arm: Move chained_irq_(enter|exit) to a generic file Catalin Marinas
@ 2013-01-24 5:32 ` Santosh Shilimkar
2013-01-24 17:29 ` Catalin Marinas
0 siblings, 1 reply; 18+ messages in thread
From: Santosh Shilimkar @ 2013-01-24 5:32 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 23 January 2013 11:29 PM, Catalin Marinas wrote:
> These functions have been introduced by commit 10a8c383 (irq: introduce
> entry and exit functions for chained handlers) in asm/mach/irq.h. This
> patch moves them to linux/irqchip/chained_irq.h so that generic irqchip
> drivers do not rely on architecture specific header files.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Rob Herring <rob.herring@calxeda.com>
> ---
[..]
> diff --git a/include/linux/irqchip/chained_irq.h b/include/linux/irqchip/chained_irq.h
> new file mode 100644
> index 0000000..adf4c30
> --- /dev/null
> +++ b/include/linux/irqchip/chained_irq.h
> @@ -0,0 +1,52 @@
> +/*
> + * Chained IRQ handlers support.
> + *
> + * Copyright (C) 2011 ARM Ltd.
2013 now ;)
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-23 17:59 ` [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas
2013-01-23 18:28 ` Stephen Warren
2013-01-24 2:15 ` Viresh Kumar
@ 2013-01-24 5:33 ` Santosh Shilimkar
2013-01-24 17:51 ` Rob Herring
` (3 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Santosh Shilimkar @ 2013-01-24 5:33 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 23 January 2013 11:29 PM, Catalin Marinas wrote:
> All the calls to gic_secondary_init() pass 0 as the first argument.
> Since this function is called on each CPU when starting, it can be done
> in a platform-independent way via a CPU notifier registered by the GIC
> code.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
[..]
> ---
>
Nice to see GIC is converted as well like timers. The trick
as you mentioned about higher priority of GIC than timer
is key for correct initialization of secondary CPUs.
For OMAP changes and the series,
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/4] arm: Move chained_irq_(enter|exit) to a generic file
2013-01-24 5:32 ` Santosh Shilimkar
@ 2013-01-24 17:29 ` Catalin Marinas
2013-01-25 7:00 ` Santosh Shilimkar
0 siblings, 1 reply; 18+ messages in thread
From: Catalin Marinas @ 2013-01-24 17:29 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jan 24, 2013 at 05:32:09AM +0000, Santosh Shilimkar wrote:
> On Wednesday 23 January 2013 11:29 PM, Catalin Marinas wrote:
> > diff --git a/include/linux/irqchip/chained_irq.h b/include/linux/irqchip/chained_irq.h
> > new file mode 100644
> > index 0000000..adf4c30
> > --- /dev/null
> > +++ b/include/linux/irqchip/chained_irq.h
> > @@ -0,0 +1,52 @@
> > +/*
> > + * Chained IRQ handlers support.
> > + *
> > + * Copyright (C) 2011 ARM Ltd.
>
> 2013 now ;)
I thought about this but decided to keep the year when the chained IRQ
functions were contributed by Will (still ARM's copyright).
--
Catalin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-23 17:59 ` [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas
` (2 preceding siblings ...)
2013-01-24 5:33 ` Santosh Shilimkar
@ 2013-01-24 17:51 ` Rob Herring
2013-01-25 4:30 ` Simon Horman
` (2 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Rob Herring @ 2013-01-24 17:51 UTC (permalink / raw)
To: linux-arm-kernel
On 01/23/2013 11:59 AM, Catalin Marinas wrote:
> All the calls to gic_secondary_init() pass 0 as the first argument.
> Since this function is called on each CPU when starting, it can be done
> in a platform-independent way via a CPU notifier registered by the GIC
> code.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: David Brown <davidb@codeaurora.org>
> Cc: Daniel Walker <dwalker@fifo99.com>
> Cc: Bryan Huntsman <bryanh@codeaurora.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Shiraz Hashim <shiraz.hashim@st.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
Acked-by: Rob Herring <rob.herring@calxeda.com>
>
> Randomly chosen CPU notifier priority. I can add a definition somewhere
> though they don't seem to be used much and cause conflicts.
>
> arch/arm/mach-exynos/platsmp.c | 8 --------
> arch/arm/mach-highbank/platsmp.c | 7 -------
> arch/arm/mach-imx/platsmp.c | 12 ------------
> arch/arm/mach-msm/platsmp.c | 8 --------
> arch/arm/mach-omap2/omap-smp.c | 7 -------
> arch/arm/mach-shmobile/smp-emev2.c | 7 -------
> arch/arm/mach-shmobile/smp-r8a7779.c | 7 -------
> arch/arm/mach-shmobile/smp-sh73a0.c | 7 -------
> arch/arm/mach-socfpga/platsmp.c | 12 ------------
> arch/arm/mach-spear13xx/platsmp.c | 8 --------
> arch/arm/mach-tegra/platsmp.c | 8 --------
> arch/arm/mach-ux500/platsmp.c | 8 --------
> arch/arm/plat-versatile/platsmp.c | 8 --------
> drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++-------
> include/linux/irqchip/arm-gic.h | 1 -
> 15 files changed, 21 insertions(+), 115 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index a083e05..a0e8ff7 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -20,7 +20,6 @@
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);
> static void __cpuinit exynos_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
> index 8797a70..a984573 100644
> --- a/arch/arm/mach-highbank/platsmp.c
> +++ b/arch/arm/mach-highbank/platsmp.c
> @@ -17,7 +17,6 @@
> #include <linux/init.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/smp_scu.h>
>
> @@ -25,11 +24,6 @@
>
> extern void secondary_startup(void);
>
> -static void __cpuinit highbank_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> highbank_set_cpu_jump(cpu, secondary_startup);
> @@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
> struct smp_operations highbank_smp_ops __initdata = {
> .smp_init_cpus = highbank_smp_init_cpus,
> .smp_prepare_cpus = highbank_smp_prepare_cpus,
> - .smp_secondary_init = highbank_secondary_init,
> .smp_boot_secondary = highbank_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_die = highbank_cpu_die,
> diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
> index b2872ec..7f63dda 100644
> --- a/arch/arm/mach-imx/platsmp.c
> +++ b/arch/arm/mach-imx/platsmp.c
> @@ -12,7 +12,6 @@
>
> #include <linux/init.h>
> #include <linux/smp.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <asm/page.h>
> #include <asm/smp_scu.h>
> #include <asm/mach/map.h>
> @@ -42,16 +41,6 @@ void __init imx_scu_map_io(void)
> scu_base = IMX_IO_ADDRESS(base);
> }
>
> -static void __cpuinit imx_secondary_init(unsigned int cpu)
> -{
> - /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> imx_set_cpu_jump(cpu, v7_secondary_startup);
> @@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
> struct smp_operations imx_smp_ops __initdata = {
> .smp_init_cpus = imx_smp_init_cpus,
> .smp_prepare_cpus = imx_smp_prepare_cpus,
> - .smp_secondary_init = imx_secondary_init,
> .smp_boot_secondary = imx_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_die = imx_cpu_die,
> diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
> index 42932865..00cdb0a 100644
> --- a/arch/arm/mach-msm/platsmp.c
> +++ b/arch/arm/mach-msm/platsmp.c
> @@ -15,7 +15,6 @@
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/cputype.h>
> @@ -42,13 +41,6 @@ static inline int get_core_count(void)
> static void __cpuinit msm_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
> index 3616779..c6ce880 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
> 4, 0, 0, 0, 0, 0);
>
> /*
> - * If any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * Synchronise with the boot thread.
> */
> spin_lock(&boot_lock);
> diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
> index 953eb1f..384e27d 100644
> --- a/arch/arm/mach-shmobile/smp-emev2.c
> +++ b/arch/arm/mach-shmobile/smp-emev2.c
> @@ -23,7 +23,6 @@
> #include <linux/spinlock.h>
> #include <linux/io.h>
> #include <linux/delay.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <mach/common.h>
> #include <mach/emev2.h>
> #include <asm/smp_plat.h>
> @@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
> }
>
>
> -static void __cpuinit emev2_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> cpu = cpu_logical_map(cpu);
> @@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)
> struct smp_operations emev2_smp_ops __initdata = {
> .smp_init_cpus = emev2_smp_init_cpus,
> .smp_prepare_cpus = emev2_smp_prepare_cpus,
> - .smp_secondary_init = emev2_secondary_init,
> .smp_boot_secondary = emev2_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_kill = emev2_cpu_kill,
> diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
> index 3a4acf2..9949065 100644
> --- a/arch/arm/mach-shmobile/smp-r8a7779.c
> +++ b/arch/arm/mach-shmobile/smp-r8a7779.c
> @@ -23,7 +23,6 @@
> #include <linux/spinlock.h>
> #include <linux/io.h>
> #include <linux/delay.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <mach/common.h>
> #include <mach/r8a7779.h>
> #include <asm/smp_plat.h>
> @@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
> }
>
>
> -static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> struct r8a7779_pm_ch *ch = NULL;
> @@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)
> struct smp_operations r8a7779_smp_ops __initdata = {
> .smp_init_cpus = r8a7779_smp_init_cpus,
> .smp_prepare_cpus = r8a7779_smp_prepare_cpus,
> - .smp_secondary_init = r8a7779_secondary_init,
> .smp_boot_secondary = r8a7779_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_kill = r8a7779_cpu_kill,
> diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
> index 9812ea3..f3b4912 100644
> --- a/arch/arm/mach-shmobile/smp-sh73a0.c
> +++ b/arch/arm/mach-shmobile/smp-sh73a0.c
> @@ -23,7 +23,6 @@
> #include <linux/spinlock.h>
> #include <linux/io.h>
> #include <linux/delay.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <mach/common.h>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)
> return scu_get_core_count(scu_base);
> }
>
> -static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> cpu = cpu_logical_map(cpu);
> @@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)
> struct smp_operations sh73a0_smp_ops __initdata = {
> .smp_init_cpus = sh73a0_smp_init_cpus,
> .smp_prepare_cpus = sh73a0_smp_prepare_cpus,
> - .smp_secondary_init = sh73a0_secondary_init,
> .smp_boot_secondary = sh73a0_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_kill = sh73a0_cpu_kill,
> diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
> index 4e9e69d..4b468ef 100644
> --- a/arch/arm/mach-socfpga/platsmp.c
> +++ b/arch/arm/mach-socfpga/platsmp.c
> @@ -22,7 +22,6 @@
> #include <linux/io.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_scu.h>
> @@ -33,16 +32,6 @@
> extern void __iomem *sys_manager_base_addr;
> extern void __iomem *rst_manager_base_addr;
>
> -static void __cpuinit socfpga_secondary_init(unsigned int cpu)
> -{
> - /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
> @@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)
> struct smp_operations socfpga_smp_ops __initdata = {
> .smp_init_cpus = socfpga_smp_init_cpus,
> .smp_prepare_cpus = socfpga_smp_prepare_cpus,
> - .smp_secondary_init = socfpga_secondary_init,
> .smp_boot_secondary = socfpga_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_die = socfpga_cpu_die,
> diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
> index af4ade6..551c69c 100644
> --- a/arch/arm/mach-spear13xx/platsmp.c
> +++ b/arch/arm/mach-spear13xx/platsmp.c
> @@ -15,7 +15,6 @@
> #include <linux/jiffies.h>
> #include <linux/io.h>
> #include <linux/smp.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <asm/cacheflush.h>
> #include <asm/smp_scu.h>
> #include <mach/spear.h>
> @@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
> static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> index c72e249..dea94d2 100644
> --- a/arch/arm/mach-tegra/platsmp.c
> +++ b/arch/arm/mach-tegra/platsmp.c
> @@ -18,7 +18,6 @@
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <linux/clk/tegra.h>
>
> #include <asm/cacheflush.h>
> @@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
>
> static void __cpuinit tegra_secondary_init(unsigned int cpu)
> {
> - /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
> }
>
> diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
> index b8adac9..b4d0735 100644
> --- a/arch/arm/mach-ux500/platsmp.c
> +++ b/arch/arm/mach-ux500/platsmp.c
> @@ -16,7 +16,6 @@
> #include <linux/device.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock);
> static void __cpuinit ux500_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
> index f2ac155..1e1b2d7 100644
> --- a/arch/arm/plat-versatile/platsmp.c
> +++ b/arch/arm/plat-versatile/platsmp.c
> @@ -14,7 +14,6 @@
> #include <linux/device.h>
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);
> void __cpuinit versatile_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index ef1429a..f103cb8 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -28,6 +28,7 @@
> #include <linux/module.h>
> #include <linux/list.h>
> #include <linux/smp.h>
> +#include <linux/cpu.h>
> #include <linux/cpu_pm.h>
> #include <linux/cpumask.h>
> #include <linux/io.h>
> @@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
> return 0;
> }
>
> +#ifdef CONFIG_SMP
> +static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
> + unsigned long action, void *hcpu)
> +{
> + if (action == CPU_STARTING)
> + gic_cpu_init(&gic_data[0]);
> + return NOTIFY_OK;
> +}
> +
> +/*
> + * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
> + * priority because the GIC needs to be up before the ARM generic timers.
> + */
> +static struct notifier_block __cpuinitdata gic_cpu_notifier = {
> + .notifier_call = gic_secondary_init,
> + .priority = 100,
> +};
> +#endif
> +
> const struct irq_domain_ops gic_irq_domain_ops = {
> .map = gic_irq_domain_map,
> .xlate = gic_irq_domain_xlate,
> @@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
>
> #ifdef CONFIG_SMP
> set_smp_cross_call(gic_raise_softirq);
> + register_cpu_notifier(&gic_cpu_notifier);
> #endif
>
> set_handle_irq(gic_handle_irq);
> @@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
> gic_pm_init(gic);
> }
>
> -void __cpuinit gic_secondary_init(unsigned int gic_nr)
> -{
> - BUG_ON(gic_nr >= MAX_GIC_NR);
> -
> - gic_cpu_init(&gic_data[gic_nr]);
> -}
> -
> #ifdef CONFIG_OF
> static int gic_cnt __initdata = 0;
>
> diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
> index a67ca55..59e59b3 100644
> --- a/include/linux/irqchip/arm-gic.h
> +++ b/include/linux/irqchip/arm-gic.h
> @@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn;
>
> void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
> u32 offset, struct device_node *);
> -void gic_secondary_init(unsigned int);
> void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
>
> static inline void gic_init(unsigned int nr, int start,
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-23 17:59 ` [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas
` (3 preceding siblings ...)
2013-01-24 17:51 ` Rob Herring
@ 2013-01-25 4:30 ` Simon Horman
2013-01-25 9:25 ` Catalin Marinas
2013-01-25 11:25 ` Srinidhi Kasagar
2013-01-25 16:16 ` Dinh Nguyen
6 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2013-01-25 4:30 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 23, 2013 at 05:59:34PM +0000, Catalin Marinas wrote:
> All the calls to gic_secondary_init() pass 0 as the first argument.
> Since this function is called on each CPU when starting, it can be done
> in a platform-independent way via a CPU notifier registered by the GIC
> code.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: David Brown <davidb@codeaurora.org>
> Cc: Daniel Walker <dwalker@fifo99.com>
> Cc: Bryan Huntsman <bryanh@codeaurora.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Shiraz Hashim <shiraz.hashim@st.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
mach-shmobile portion:
Acked-by: Simon Horman <horms+renesas@verge.net.au>
For the record, I tested this on the kzm9g, kzm9d and marzen boards
which use the r8a7779, EMEV2 and r8a7779 SoCs respectively.
> ---
>
> Randomly chosen CPU notifier priority. I can add a definition somewhere
> though they don't seem to be used much and cause conflicts.
>
> arch/arm/mach-exynos/platsmp.c | 8 --------
> arch/arm/mach-highbank/platsmp.c | 7 -------
> arch/arm/mach-imx/platsmp.c | 12 ------------
> arch/arm/mach-msm/platsmp.c | 8 --------
> arch/arm/mach-omap2/omap-smp.c | 7 -------
> arch/arm/mach-shmobile/smp-emev2.c | 7 -------
> arch/arm/mach-shmobile/smp-r8a7779.c | 7 -------
> arch/arm/mach-shmobile/smp-sh73a0.c | 7 -------
> arch/arm/mach-socfpga/platsmp.c | 12 ------------
> arch/arm/mach-spear13xx/platsmp.c | 8 --------
> arch/arm/mach-tegra/platsmp.c | 8 --------
> arch/arm/mach-ux500/platsmp.c | 8 --------
> arch/arm/plat-versatile/platsmp.c | 8 --------
> drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++-------
> include/linux/irqchip/arm-gic.h | 1 -
> 15 files changed, 21 insertions(+), 115 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index a083e05..a0e8ff7 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -20,7 +20,6 @@
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);
> static void __cpuinit exynos_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
> index 8797a70..a984573 100644
> --- a/arch/arm/mach-highbank/platsmp.c
> +++ b/arch/arm/mach-highbank/platsmp.c
> @@ -17,7 +17,6 @@
> #include <linux/init.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/smp_scu.h>
>
> @@ -25,11 +24,6 @@
>
> extern void secondary_startup(void);
>
> -static void __cpuinit highbank_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> highbank_set_cpu_jump(cpu, secondary_startup);
> @@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
> struct smp_operations highbank_smp_ops __initdata = {
> .smp_init_cpus = highbank_smp_init_cpus,
> .smp_prepare_cpus = highbank_smp_prepare_cpus,
> - .smp_secondary_init = highbank_secondary_init,
> .smp_boot_secondary = highbank_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_die = highbank_cpu_die,
> diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
> index b2872ec..7f63dda 100644
> --- a/arch/arm/mach-imx/platsmp.c
> +++ b/arch/arm/mach-imx/platsmp.c
> @@ -12,7 +12,6 @@
>
> #include <linux/init.h>
> #include <linux/smp.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <asm/page.h>
> #include <asm/smp_scu.h>
> #include <asm/mach/map.h>
> @@ -42,16 +41,6 @@ void __init imx_scu_map_io(void)
> scu_base = IMX_IO_ADDRESS(base);
> }
>
> -static void __cpuinit imx_secondary_init(unsigned int cpu)
> -{
> - /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> imx_set_cpu_jump(cpu, v7_secondary_startup);
> @@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
> struct smp_operations imx_smp_ops __initdata = {
> .smp_init_cpus = imx_smp_init_cpus,
> .smp_prepare_cpus = imx_smp_prepare_cpus,
> - .smp_secondary_init = imx_secondary_init,
> .smp_boot_secondary = imx_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_die = imx_cpu_die,
> diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
> index 42932865..00cdb0a 100644
> --- a/arch/arm/mach-msm/platsmp.c
> +++ b/arch/arm/mach-msm/platsmp.c
> @@ -15,7 +15,6 @@
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/cputype.h>
> @@ -42,13 +41,6 @@ static inline int get_core_count(void)
> static void __cpuinit msm_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
> index 3616779..c6ce880 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
> 4, 0, 0, 0, 0, 0);
>
> /*
> - * If any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * Synchronise with the boot thread.
> */
> spin_lock(&boot_lock);
> diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
> index 953eb1f..384e27d 100644
> --- a/arch/arm/mach-shmobile/smp-emev2.c
> +++ b/arch/arm/mach-shmobile/smp-emev2.c
> @@ -23,7 +23,6 @@
> #include <linux/spinlock.h>
> #include <linux/io.h>
> #include <linux/delay.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <mach/common.h>
> #include <mach/emev2.h>
> #include <asm/smp_plat.h>
> @@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
> }
>
>
> -static void __cpuinit emev2_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> cpu = cpu_logical_map(cpu);
> @@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)
> struct smp_operations emev2_smp_ops __initdata = {
> .smp_init_cpus = emev2_smp_init_cpus,
> .smp_prepare_cpus = emev2_smp_prepare_cpus,
> - .smp_secondary_init = emev2_secondary_init,
> .smp_boot_secondary = emev2_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_kill = emev2_cpu_kill,
> diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
> index 3a4acf2..9949065 100644
> --- a/arch/arm/mach-shmobile/smp-r8a7779.c
> +++ b/arch/arm/mach-shmobile/smp-r8a7779.c
> @@ -23,7 +23,6 @@
> #include <linux/spinlock.h>
> #include <linux/io.h>
> #include <linux/delay.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <mach/common.h>
> #include <mach/r8a7779.h>
> #include <asm/smp_plat.h>
> @@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
> }
>
>
> -static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> struct r8a7779_pm_ch *ch = NULL;
> @@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)
> struct smp_operations r8a7779_smp_ops __initdata = {
> .smp_init_cpus = r8a7779_smp_init_cpus,
> .smp_prepare_cpus = r8a7779_smp_prepare_cpus,
> - .smp_secondary_init = r8a7779_secondary_init,
> .smp_boot_secondary = r8a7779_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_kill = r8a7779_cpu_kill,
> diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
> index 9812ea3..f3b4912 100644
> --- a/arch/arm/mach-shmobile/smp-sh73a0.c
> +++ b/arch/arm/mach-shmobile/smp-sh73a0.c
> @@ -23,7 +23,6 @@
> #include <linux/spinlock.h>
> #include <linux/io.h>
> #include <linux/delay.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <mach/common.h>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)
> return scu_get_core_count(scu_base);
> }
>
> -static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> cpu = cpu_logical_map(cpu);
> @@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)
> struct smp_operations sh73a0_smp_ops __initdata = {
> .smp_init_cpus = sh73a0_smp_init_cpus,
> .smp_prepare_cpus = sh73a0_smp_prepare_cpus,
> - .smp_secondary_init = sh73a0_secondary_init,
> .smp_boot_secondary = sh73a0_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_kill = sh73a0_cpu_kill,
> diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
> index 4e9e69d..4b468ef 100644
> --- a/arch/arm/mach-socfpga/platsmp.c
> +++ b/arch/arm/mach-socfpga/platsmp.c
> @@ -22,7 +22,6 @@
> #include <linux/io.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_scu.h>
> @@ -33,16 +32,6 @@
> extern void __iomem *sys_manager_base_addr;
> extern void __iomem *rst_manager_base_addr;
>
> -static void __cpuinit socfpga_secondary_init(unsigned int cpu)
> -{
> - /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
> @@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)
> struct smp_operations socfpga_smp_ops __initdata = {
> .smp_init_cpus = socfpga_smp_init_cpus,
> .smp_prepare_cpus = socfpga_smp_prepare_cpus,
> - .smp_secondary_init = socfpga_secondary_init,
> .smp_boot_secondary = socfpga_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_die = socfpga_cpu_die,
> diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
> index af4ade6..551c69c 100644
> --- a/arch/arm/mach-spear13xx/platsmp.c
> +++ b/arch/arm/mach-spear13xx/platsmp.c
> @@ -15,7 +15,6 @@
> #include <linux/jiffies.h>
> #include <linux/io.h>
> #include <linux/smp.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <asm/cacheflush.h>
> #include <asm/smp_scu.h>
> #include <mach/spear.h>
> @@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
> static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> index c72e249..dea94d2 100644
> --- a/arch/arm/mach-tegra/platsmp.c
> +++ b/arch/arm/mach-tegra/platsmp.c
> @@ -18,7 +18,6 @@
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <linux/clk/tegra.h>
>
> #include <asm/cacheflush.h>
> @@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
>
> static void __cpuinit tegra_secondary_init(unsigned int cpu)
> {
> - /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
> }
>
> diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
> index b8adac9..b4d0735 100644
> --- a/arch/arm/mach-ux500/platsmp.c
> +++ b/arch/arm/mach-ux500/platsmp.c
> @@ -16,7 +16,6 @@
> #include <linux/device.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock);
> static void __cpuinit ux500_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
> index f2ac155..1e1b2d7 100644
> --- a/arch/arm/plat-versatile/platsmp.c
> +++ b/arch/arm/plat-versatile/platsmp.c
> @@ -14,7 +14,6 @@
> #include <linux/device.h>
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);
> void __cpuinit versatile_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index ef1429a..f103cb8 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -28,6 +28,7 @@
> #include <linux/module.h>
> #include <linux/list.h>
> #include <linux/smp.h>
> +#include <linux/cpu.h>
> #include <linux/cpu_pm.h>
> #include <linux/cpumask.h>
> #include <linux/io.h>
> @@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
> return 0;
> }
>
> +#ifdef CONFIG_SMP
> +static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
> + unsigned long action, void *hcpu)
> +{
> + if (action == CPU_STARTING)
> + gic_cpu_init(&gic_data[0]);
> + return NOTIFY_OK;
> +}
> +
> +/*
> + * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
> + * priority because the GIC needs to be up before the ARM generic timers.
> + */
> +static struct notifier_block __cpuinitdata gic_cpu_notifier = {
> + .notifier_call = gic_secondary_init,
> + .priority = 100,
> +};
> +#endif
> +
> const struct irq_domain_ops gic_irq_domain_ops = {
> .map = gic_irq_domain_map,
> .xlate = gic_irq_domain_xlate,
> @@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
>
> #ifdef CONFIG_SMP
> set_smp_cross_call(gic_raise_softirq);
> + register_cpu_notifier(&gic_cpu_notifier);
> #endif
>
> set_handle_irq(gic_handle_irq);
> @@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
> gic_pm_init(gic);
> }
>
> -void __cpuinit gic_secondary_init(unsigned int gic_nr)
> -{
> - BUG_ON(gic_nr >= MAX_GIC_NR);
> -
> - gic_cpu_init(&gic_data[gic_nr]);
> -}
> -
> #ifdef CONFIG_OF
> static int gic_cnt __initdata = 0;
>
> diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
> index a67ca55..59e59b3 100644
> --- a/include/linux/irqchip/arm-gic.h
> +++ b/include/linux/irqchip/arm-gic.h
> @@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn;
>
> void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
> u32 offset, struct device_node *);
> -void gic_secondary_init(unsigned int);
> void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
>
> static inline void gic_init(unsigned int nr, int start,
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/4] arm: Move chained_irq_(enter|exit) to a generic file
2013-01-24 17:29 ` Catalin Marinas
@ 2013-01-25 7:00 ` Santosh Shilimkar
0 siblings, 0 replies; 18+ messages in thread
From: Santosh Shilimkar @ 2013-01-25 7:00 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 24 January 2013 10:59 PM, Catalin Marinas wrote:
> On Thu, Jan 24, 2013 at 05:32:09AM +0000, Santosh Shilimkar wrote:
>> On Wednesday 23 January 2013 11:29 PM, Catalin Marinas wrote:
>>> diff --git a/include/linux/irqchip/chained_irq.h b/include/linux/irqchip/chained_irq.h
>>> new file mode 100644
>>> index 0000000..adf4c30
>>> --- /dev/null
>>> +++ b/include/linux/irqchip/chained_irq.h
>>> @@ -0,0 +1,52 @@
>>> +/*
>>> + * Chained IRQ handlers support.
>>> + *
>>> + * Copyright (C) 2011 ARM Ltd.
>>
>> 2013 now ;)
>
> I thought about this but decided to keep the year when the chained IRQ
> functions were contributed by Will (still ARM's copyright).
>
Ahh. Its just move to the new file. As you prefer but 2011-13 will
do as well :-)
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-25 4:30 ` Simon Horman
@ 2013-01-25 9:25 ` Catalin Marinas
2013-01-28 1:03 ` Simon Horman
0 siblings, 1 reply; 18+ messages in thread
From: Catalin Marinas @ 2013-01-25 9:25 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 25, 2013 at 04:30:39AM +0000, Simon Horman wrote:
> On Wed, Jan 23, 2013 at 05:59:34PM +0000, Catalin Marinas wrote:
> > All the calls to gic_secondary_init() pass 0 as the first argument.
> > Since this function is called on each CPU when starting, it can be done
> > in a platform-independent way via a CPU notifier registered by the GIC
> > code.
> >
> > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Russell King <linux@arm.linux.org.uk>
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Kukjin Kim <kgene.kim@samsung.com>
> > Cc: Rob Herring <rob.herring@calxeda.com>
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: David Brown <davidb@codeaurora.org>
> > Cc: Daniel Walker <dwalker@fifo99.com>
> > Cc: Bryan Huntsman <bryanh@codeaurora.org>
> > Cc: Tony Lindgren <tony@atomide.com>
> > Cc: Simon Horman <horms@verge.net.au>
> > Cc: Magnus Damm <magnus.damm@gmail.com>
> > Cc: Dinh Nguyen <dinguyen@altera.com>
> > Cc: Viresh Kumar <viresh.linux@gmail.com>
> > Cc: Shiraz Hashim <shiraz.hashim@st.com>
> > Cc: Stephen Warren <swarren@wwwdotorg.org>
> > Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> > Cc: Linus Walleij <linus.walleij@linaro.org>
>
> mach-shmobile portion:
>
> Acked-by: Simon Horman <horms+renesas@verge.net.au>
>
> For the record, I tested this on the kzm9g, kzm9d and marzen boards
> which use the r8a7779, EMEV2 and r8a7779 SoCs respectively.
Thanks. Can I add a Tested-by as well?
--
Catalin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-23 17:59 ` [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas
` (4 preceding siblings ...)
2013-01-25 4:30 ` Simon Horman
@ 2013-01-25 11:25 ` Srinidhi Kasagar
2013-01-25 16:16 ` Dinh Nguyen
6 siblings, 0 replies; 18+ messages in thread
From: Srinidhi Kasagar @ 2013-01-25 11:25 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 23, 2013 at 18:59:34 +0100, Catalin Marinas wrote:
> All the calls to gic_secondary_init() pass 0 as the first argument.
> Since this function is called on each CPU when starting, it can be done
> in a platform-independent way via a CPU notifier registered by the GIC
> code.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: David Brown <davidb@codeaurora.org>
> Cc: Daniel Walker <dwalker@fifo99.com>
> Cc: Bryan Huntsman <bryanh@codeaurora.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Shiraz Hashim <shiraz.hashim@st.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
For ux500, it is
Acked-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
thanks,
srinidhi
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-23 17:59 ` [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas
` (5 preceding siblings ...)
2013-01-25 11:25 ` Srinidhi Kasagar
@ 2013-01-25 16:16 ` Dinh Nguyen
2013-01-25 18:12 ` Catalin Marinas
6 siblings, 1 reply; 18+ messages in thread
From: Dinh Nguyen @ 2013-01-25 16:16 UTC (permalink / raw)
To: linux-arm-kernel
Hi Catalin,
On Wed, 2013-01-23 at 17:59 +0000, Catalin Marinas wrote:
> All the calls to gic_secondary_init() pass 0 as the first argument.
> Since this function is called on each CPU when starting, it can be done
> in a platform-independent way via a CPU notifier registered by the GIC
> code.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: David Brown <davidb@codeaurora.org>
> Cc: Daniel Walker <dwalker@fifo99.com>
> Cc: Bryan Huntsman <bryanh@codeaurora.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Shiraz Hashim <shiraz.hashim@st.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
>
> Randomly chosen CPU notifier priority. I can add a definition somewhere
> though they don't seem to be used much and cause conflicts.
>
> arch/arm/mach-exynos/platsmp.c | 8 --------
> arch/arm/mach-highbank/platsmp.c | 7 -------
> arch/arm/mach-imx/platsmp.c | 12 ------------
> arch/arm/mach-msm/platsmp.c | 8 --------
> arch/arm/mach-omap2/omap-smp.c | 7 -------
> arch/arm/mach-shmobile/smp-emev2.c | 7 -------
> arch/arm/mach-shmobile/smp-r8a7779.c | 7 -------
> arch/arm/mach-shmobile/smp-sh73a0.c | 7 -------
> arch/arm/mach-socfpga/platsmp.c | 12 ------------
For socfpga, I get this error when I build for sofpga_defconfig:
drivers/gpio/gpio-pl061.c: In function ?pl061_irq_handler?:
drivers/gpio/gpio-pl061.c:183:2: error: implicit declaration of function
?chained_irq_enter? [-Werror=implicit-function-declaration]
drivers/gpio/gpio-pl061.c:192:2: error: implicit declaration of function
?chained_irq_exit? [-Werror=implicit-function-declaration]
Dinh
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-25 16:16 ` Dinh Nguyen
@ 2013-01-25 18:12 ` Catalin Marinas
0 siblings, 0 replies; 18+ messages in thread
From: Catalin Marinas @ 2013-01-25 18:12 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 25, 2013 at 04:16:18PM +0000, Dinh Nguyen wrote:
> Hi Catalin,
>
> On Wed, 2013-01-23 at 17:59 +0000, Catalin Marinas wrote:
> > All the calls to gic_secondary_init() pass 0 as the first argument.
> > Since this function is called on each CPU when starting, it can be done
> > in a platform-independent way via a CPU notifier registered by the GIC
> > code.
> >
> > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Russell King <linux@arm.linux.org.uk>
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Kukjin Kim <kgene.kim@samsung.com>
> > Cc: Rob Herring <rob.herring@calxeda.com>
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: David Brown <davidb@codeaurora.org>
> > Cc: Daniel Walker <dwalker@fifo99.com>
> > Cc: Bryan Huntsman <bryanh@codeaurora.org>
> > Cc: Tony Lindgren <tony@atomide.com>
> > Cc: Simon Horman <horms@verge.net.au>
> > Cc: Magnus Damm <magnus.damm@gmail.com>
> > Cc: Dinh Nguyen <dinguyen@altera.com>
> > Cc: Viresh Kumar <viresh.linux@gmail.com>
> > Cc: Shiraz Hashim <shiraz.hashim@st.com>
> > Cc: Stephen Warren <swarren@wwwdotorg.org>
> > Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> > Cc: Linus Walleij <linus.walleij@linaro.org>
> > ---
> >
> > Randomly chosen CPU notifier priority. I can add a definition somewhere
> > though they don't seem to be used much and cause conflicts.
> >
> > arch/arm/mach-exynos/platsmp.c | 8 --------
> > arch/arm/mach-highbank/platsmp.c | 7 -------
> > arch/arm/mach-imx/platsmp.c | 12 ------------
> > arch/arm/mach-msm/platsmp.c | 8 --------
> > arch/arm/mach-omap2/omap-smp.c | 7 -------
> > arch/arm/mach-shmobile/smp-emev2.c | 7 -------
> > arch/arm/mach-shmobile/smp-r8a7779.c | 7 -------
> > arch/arm/mach-shmobile/smp-sh73a0.c | 7 -------
> > arch/arm/mach-socfpga/platsmp.c | 12 ------------
>
> For socfpga, I get this error when I build for sofpga_defconfig:
>
> drivers/gpio/gpio-pl061.c: In function ?pl061_irq_handler?:
> drivers/gpio/gpio-pl061.c:183:2: error: implicit declaration of function
> ?chained_irq_enter? [-Werror=implicit-function-declaration]
> drivers/gpio/gpio-pl061.c:192:2: error: implicit declaration of function
> ?chained_irq_exit? [-Werror=implicit-function-declaration]
Ah, I only grep'ed arch/arm for chained_irq_enter() use. The simplest
for arch/arm is to actually include chained_irq.h into asm/mach/irq.h
since the latter is already included. For code shared with arm64 I'll
just include chained_irq.h explicitly.
Thanks.
--
Catalin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
2013-01-25 9:25 ` Catalin Marinas
@ 2013-01-28 1:03 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2013-01-28 1:03 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 25, 2013 at 09:25:28AM +0000, Catalin Marinas wrote:
> On Fri, Jan 25, 2013 at 04:30:39AM +0000, Simon Horman wrote:
> > On Wed, Jan 23, 2013 at 05:59:34PM +0000, Catalin Marinas wrote:
> > > All the calls to gic_secondary_init() pass 0 as the first argument.
> > > Since this function is called on each CPU when starting, it can be done
> > > in a platform-independent way via a CPU notifier registered by the GIC
> > > code.
> > >
> > > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Russell King <linux@arm.linux.org.uk>
> > > Cc: Thomas Gleixner <tglx@linutronix.de>
> > > Cc: Kukjin Kim <kgene.kim@samsung.com>
> > > Cc: Rob Herring <rob.herring@calxeda.com>
> > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > Cc: David Brown <davidb@codeaurora.org>
> > > Cc: Daniel Walker <dwalker@fifo99.com>
> > > Cc: Bryan Huntsman <bryanh@codeaurora.org>
> > > Cc: Tony Lindgren <tony@atomide.com>
> > > Cc: Simon Horman <horms@verge.net.au>
> > > Cc: Magnus Damm <magnus.damm@gmail.com>
> > > Cc: Dinh Nguyen <dinguyen@altera.com>
> > > Cc: Viresh Kumar <viresh.linux@gmail.com>
> > > Cc: Shiraz Hashim <shiraz.hashim@st.com>
> > > Cc: Stephen Warren <swarren@wwwdotorg.org>
> > > Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> > > Cc: Linus Walleij <linus.walleij@linaro.org>
> >
> > mach-shmobile portion:
> >
> > Acked-by: Simon Horman <horms+renesas@verge.net.au>
> >
> > For the record, I tested this on the kzm9g, kzm9d and marzen boards
> > which use the r8a7779, EMEV2 and r8a7779 SoCs respectively.
>
> Thanks. Can I add a Tested-by as well?
Sure.
Tested-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2013-01-28 1:03 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-01-23 17:59 [PATCH 0/4] Preparatory GIC patches for arm64 support Catalin Marinas
2013-01-23 17:59 ` [PATCH 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h Catalin Marinas
2013-01-23 17:59 ` [PATCH 2/4] arm: Move chained_irq_(enter|exit) to a generic file Catalin Marinas
2013-01-24 5:32 ` Santosh Shilimkar
2013-01-24 17:29 ` Catalin Marinas
2013-01-25 7:00 ` Santosh Shilimkar
2013-01-23 17:59 ` [PATCH 3/4] irqchip: gic: Call handle_bad_irq() directly Catalin Marinas
2013-01-23 17:59 ` [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas
2013-01-23 18:28 ` Stephen Warren
2013-01-24 2:15 ` Viresh Kumar
2013-01-24 5:33 ` Santosh Shilimkar
2013-01-24 17:51 ` Rob Herring
2013-01-25 4:30 ` Simon Horman
2013-01-25 9:25 ` Catalin Marinas
2013-01-28 1:03 ` Simon Horman
2013-01-25 11:25 ` Srinidhi Kasagar
2013-01-25 16:16 ` Dinh Nguyen
2013-01-25 18:12 ` Catalin Marinas
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.