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From: Andi Kleen <andi@firstfloor.org>
To: mingo@kernel.org
Cc: linux-kernel@vger.kernel.org, a.p.zijlstra@chello.nl,
	akpm@linux-foundation.org, acme@redhat.com, eranian@google.com,
	jolsa@redhat.com, namhyung@kernel.org
Subject: Basic perf PMU support for Haswell v4
Date: Mon,  4 Feb 2013 17:49:09 -0800	[thread overview]
Message-ID: <1360028954-16946-1-git-send-email-andi@firstfloor.org> (raw)

This is based on v7 of the full Haswell PMU support, but 
ported to the latest perf/core and stripped down to the
extreme "perf for dummies" edition as requested.  

I removed some more patches, these will come later.
I moved parts of an later patch (counter constraints for qualifiers) 
into an earlier patch, to support the full raw bits at least.

For anything beyond basic usage this is not very useful.

Contains support for:
- Basic Haswell PMU and PEBS support
- Late unmasking of the PMI
- Support for wide counters

v2: Addressed Stephane's feedback. See individual patches for details.
v3: now even more bite-sized. Qualifier constraints merged earlier.
Add some Reviewed-bys.
v4: Rename some variables, add some comments and other minor changes in the first patch.

-Andi

             reply	other threads:[~2013-02-05  1:49 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-02-05  1:49 Andi Kleen [this message]
2013-02-05  1:49 ` [PATCH 1/5] perf, x86: Add PEBSv2 record support v2 Andi Kleen
2013-02-05  1:49 ` [PATCH 2/5] perf, x86: Basic Haswell PMU support v4 Andi Kleen
2013-02-05  1:49 ` [PATCH 3/5] perf, x86: Basic Haswell PEBS " Andi Kleen
2013-02-05  1:49 ` [PATCH 4/5] perf, x86: Support full width counting Andi Kleen
2013-02-05 15:15   ` Stephane Eranian
2013-02-05 19:09     ` Andi Kleen
2013-02-06  0:27     ` Andi Kleen
2013-02-06 10:57       ` Stephane Eranian
2013-02-05  1:49 ` [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen

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