From: Andi Kleen <andi@firstfloor.org>
To: Stephane Eranian <eranian@google.com>
Cc: Andi Kleen <andi@firstfloor.org>, Ingo Molnar <mingo@kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
Peter Zijlstra <a.p.zijlstra@chello.nl>,
Andrew Morton <akpm@linux-foundation.org>,
Arnaldo Carvalho de Melo <acme@redhat.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 4/5] perf, x86: Support full width counting
Date: Tue, 5 Feb 2013 20:09:02 +0100 [thread overview]
Message-ID: <20130205190902.GV30577@one.firstfloor.org> (raw)
In-Reply-To: <CABPqkBTyBJwaz+ON20nCM0jyQASoHXRDejtyNLJ1AoBSWS_tPA@mail.gmail.com>
On Tue, Feb 05, 2013 at 04:15:26PM +0100, Stephane Eranian wrote:
> > --- a/arch/x86/kernel/cpu/perf_event_intel.c
> > +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> > @@ -2228,5 +2228,11 @@ __init int intel_pmu_init(void)
> > }
> > }
> >
> > + /* Support full width counters using alternative MSR range */
> > + if (x86_pmu.intel_cap.fw_write) {
> > + x86_pmu.max_period = x86_pmu.cntval_mask;
>
> Something is not clear to me: What happens to the fixed counters with
> full writes? Were they already full-width? The SDM does not explain what
> happens to them with this extension. Could you clarify?
I tested and they always support the full reported width.
-Andi
--
ak@linux.intel.com -- Speaking for myself only.
next prev parent reply other threads:[~2013-02-05 19:09 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-05 1:49 Basic perf PMU support for Haswell v4 Andi Kleen
2013-02-05 1:49 ` [PATCH 1/5] perf, x86: Add PEBSv2 record support v2 Andi Kleen
2013-02-05 1:49 ` [PATCH 2/5] perf, x86: Basic Haswell PMU support v4 Andi Kleen
2013-02-05 1:49 ` [PATCH 3/5] perf, x86: Basic Haswell PEBS " Andi Kleen
2013-02-05 1:49 ` [PATCH 4/5] perf, x86: Support full width counting Andi Kleen
2013-02-05 15:15 ` Stephane Eranian
2013-02-05 19:09 ` Andi Kleen [this message]
2013-02-06 0:27 ` Andi Kleen
2013-02-06 10:57 ` Stephane Eranian
2013-02-05 1:49 ` [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
-- strict thread matches above, loose matches on Subject: below --
2013-02-02 1:54 Basic perf PMU support for Haswell v3 Andi Kleen
2013-02-02 1:54 ` [PATCH 4/5] perf, x86: Support full width counting Andi Kleen
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