[GIT PULL] i2c: vt8500: Add support for Wondermedia I2C master-mode

[GIT PULL] i2c: vt8500: Add support for Wondermedia I2C master-mode

[Tony Prisk]

Hi Wolfram,

This patch has been floating around since 27 december with no replies so
here is a pull-request for it.

Regards
Tony Prisk

cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org


The following changes since commit 9931faca02c604c22335f5a935a501bb2ace6e20:

  Linux 3.8-rc3 (2013-01-09 18:59:55 -0800)

are available in the git repository at:

  git://server.prisktech.co.nz/git/linuxwmt.git tags/i2c-3.9

for you to fetch changes up to c24a4dd6d6ad85e5d5cdb4e20c623103360ea7e0:

  i2c: vt8500: Add support for Wondermedia I2C master-mode (2013-01-16 18:45:12 +1300)

----------------------------------------------------------------
i2c: vt8500: Add support for I2C on arch-vt8500

----------------------------------------------------------------
Tony Prisk (1):
      i2c: vt8500: Add support for Wondermedia I2C master-mode

 .../devicetree/bindings/i2c/i2c-vt8500.txt         |   24 +
 drivers/i2c/busses/Kconfig                         |    7 +
 drivers/i2c/busses/Makefile                        |    1 +
 drivers/i2c/busses/i2c-wmt.c                       |  636 ++++++++++++++++++++
 4 files changed, 668 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
 create mode 100644 drivers/i2c/busses/i2c-wmt.c

[PATCH] i2c: vt8500: Add support for Wondermedia I2C master-mode

[Tony Prisk]

This patch adds support for the I2C controller found on Wondermedia
SoCs.

Due to the lack of pinmux support, GPIO pin alternate functions are
configured by machine's compatible property, as are pullups.

Signed-off-by: Tony Prisk <linux-ci5G2KO2hbZ+pU9mqzGVBQ@public.gmane.org>
---
cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

 .../devicetree/bindings/i2c/i2c-vt8500.txt         |   24 +
 drivers/i2c/busses/Kconfig                         |    7 +
 drivers/i2c/busses/Makefile                        |    1 +
 drivers/i2c/busses/i2c-wmt.c                       |  636 ++++++++++++++++++++
 4 files changed, 668 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
 create mode 100644 drivers/i2c/busses/i2c-wmt.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
new file mode 100644
index 0000000..94a425e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
@@ -0,0 +1,24 @@
+* Wondermedia I2C Controller
+
+Required properties :
+
+ - compatible : should be "wm,wm8505-i2c"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number
+ - clocks : phandle to the I2C clock source
+
+Optional properties :
+
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+	Valid values are 100000 and 400000.
+	Default to 100000 if not specified, or invalid value.
+
+Example :
+
+	i2c_0: i2c@d8280000 {
+		compatible = "wm,wm8505-i2c";
+		reg = <0xd8280000 0x1000>;
+		interrupts = <19>;
+		clocks = <&clki2c0>;
+		clock-frequency = <400000>;
+	};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bdca511..41270fa 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -700,6 +700,13 @@ config I2C_VERSATILE
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-versatile.
 
+config I2C_WMT
+	tristate "Wondermedia I2C Controller support"
+	depends on ARCH_VT8500
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C controllers found in Wondermedia SoCs.
+
 config I2C_OCTEON
 	tristate "Cavium OCTEON I2C bus support"
 	depends on CPU_CAVIUM_OCTEON
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 6181f3f..dce6299 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
+obj-$(CONFIG_I2C_WMT)		+= i2c-wmt.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
 obj-$(CONFIG_I2C_XILINX)	+= i2c-xiic.o
 obj-$(CONFIG_I2C_XLR)		+= i2c-xlr.o
diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
new file mode 100644
index 0000000..07d86e3
--- /dev/null
+++ b/drivers/i2c/busses/i2c-wmt.c
@@ -0,0 +1,636 @@
+/*
+ *  Wondermedia I2C Master Mode Driver
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux-ci5G2KO2hbZ+pU9mqzGVBQ@public.gmane.org>
+ *
+ *  Derived from GPL licensed source:
+ *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_i2c.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define REG_CR		0x00
+#define REG_TCR		0x02
+#define REG_CSR		0x04
+#define REG_ISR		0x06
+#define REG_IMR		0x08
+#define REG_CDR		0x0A
+#define REG_TR		0x0C
+#define REG_MCR		0x0E
+#define REG_SLAVE_CR	0x10
+#define REG_SLAVE_SR	0x12
+#define REG_SLAVE_ISR	0x14
+#define REG_SLAVE_IMR	0x16
+#define REG_SLAVE_DR	0x18
+#define REG_SLAVE_TR	0x1A
+
+/* REG_CR Bit fields */
+#define CR_TX_NEXT_ACK		0x0000
+#define CR_ENABLE		0x0001
+#define CR_TX_NEXT_NO_ACK	0x0002
+#define CR_TX_END		0x0004
+#define CR_CPU_RDY		0x0008
+#define SLAV_MODE_SEL		0x8000
+
+/* REG_TCR Bit fields */
+#define TCR_STANDARD_MODE	0x0000
+#define TCR_MASTER_WRITE	0x0000
+#define TCR_HS_MODE		0x2000
+#define TCR_MASTER_READ		0x4000
+#define TCR_FAST_MODE		0x8000
+#define TCR_SLAVE_ADDR_MASK	0x007F
+
+/* REG_ISR Bit fields */
+#define ISR_NACK_ADDR		0x0001
+#define ISR_BYTE_END		0x0002
+#define ISR_SCL_TIMEOUT		0x0004
+#define ISR_WRITE_ALL		0x0007
+
+/* REG_IMR Bit fields */
+#define IMR_ENABLE_ALL		0x0007
+
+/* REG_CSR Bit fields */
+#define CSR_RCV_NOT_ACK		0x0001
+#define CSR_RCV_ACK_MASK	0x0001
+#define CSR_READY_MASK		0x0002
+
+#define I2C_MODE_STANDARD	0
+#define I2C_MODE_FAST		1
+
+
+
+struct wmt_i2c_dev {
+	struct i2c_adapter	adapter;
+	struct completion	complete;
+	struct device		*dev;
+	void __iomem		*base;
+	struct clk		*clk;
+	int			mode;
+	int			irq;
+	u16			cmd_status;
+};
+
+static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
+{
+	u16 val;
+	int i;
+	int ret = 0;
+
+	for (i = 0; i < 10000000; i++) {
+		val = readw(i2c_dev->base + REG_CSR);
+		if (val & CSR_READY_MASK)
+			break;
+
+		udelay(1);
+	}
+	if (i >= 9999999)
+		ret = -EBUSY;
+
+	return ret;
+}
+
+static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
+{
+	int ret = 0;
+
+	if (i2c_dev->cmd_status & ISR_NACK_ADDR)
+		ret = -EIO;
+
+	if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
+		ret = -ETIMEDOUT;
+
+	return ret;
+}
+
+static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
+						   int restart, int last)
+{
+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	u16 val;
+	u16 tcr_val;
+	int ret;
+	int wait_result;
+	u32 xfer_len = 0;
+
+	if (pmsg->len < 0)
+		return -EINVAL;
+
+	if (restart == 0) {
+		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (pmsg->len == 0)
+		writew(0, i2c_dev->base + REG_CDR);
+	else
+		writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
+
+	if (restart == 0) {
+		val = readw(i2c_dev->base + REG_CR);
+		val &= ~CR_TX_END;
+		writew(val, i2c_dev->base + REG_CR);
+
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	init_completion(&i2c_dev->complete);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		tcr_val = TCR_STANDARD_MODE;
+	else
+		tcr_val = TCR_FAST_MODE;
+
+	tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
+
+	writew(tcr_val, i2c_dev->base + REG_TCR);
+
+	if (restart == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	ret = 0;
+
+	for (;;) {
+		wait_result = wait_for_completion_interruptible_timeout(
+				&i2c_dev->complete, 500 * HZ / 1000);
+
+		if (wait_result == 0) {
+			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
+			ret = -ETIMEDOUT;
+			break;
+		}
+
+		ret = wmt_check_status(i2c_dev);
+		if (ret)
+			break;
+
+		xfer_len++;
+
+		val = readw(i2c_dev->base + REG_CSR);
+		if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
+			dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
+			ret = -EIO;
+			break;
+		}
+
+		if (pmsg->len == 0) {
+			val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
+			writew(val, i2c_dev->base + REG_CR);
+			break;
+		}
+
+		if (pmsg->len > xfer_len) {
+			writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
+								REG_CDR);
+			writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
+		} else if (pmsg->len == xfer_len) {
+			if (last != 1)
+				writew(CR_ENABLE, i2c_dev->base + REG_CR);
+			break;
+		} else {
+			dev_dbg(i2c_dev->dev, "unknown error (tx)\n");
+			ret = -EIO;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
+						  int restart, int last)
+{
+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	u16 val;
+	u16 tcr_val;
+	int ret;
+	int wait_result;
+	u32 xfer_len = 0;
+
+	if (pmsg->len <= 0)
+		return -EINVAL;
+
+	if (restart == 0) {
+		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	val = readw(i2c_dev->base + REG_CR);
+	val &= ~CR_TX_END;
+	writew(val, i2c_dev->base + REG_CR);
+
+	val = readw(i2c_dev->base + REG_CR);
+	val &= ~CR_TX_NEXT_NO_ACK;
+	writew(val, i2c_dev->base + REG_CR);
+
+	if (restart == 0) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	if (pmsg->len == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_TX_NEXT_NO_ACK;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	init_completion(&i2c_dev->complete);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		tcr_val = TCR_STANDARD_MODE;
+	else
+		tcr_val = TCR_FAST_MODE;
+
+	tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
+
+	writew(tcr_val, i2c_dev->base + REG_TCR);
+
+	if (restart == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	ret = 0;
+
+	for (;;) {
+		wait_result = wait_for_completion_interruptible_timeout(
+				&i2c_dev->complete, 500 * HZ / 1000);
+
+		if (wait_result == 0) {
+			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
+			ret = -ETIMEDOUT;
+			break;
+		}
+
+		ret = wmt_check_status(i2c_dev);
+		if (ret)
+			break;
+
+		pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
+		xfer_len++;
+
+		if (pmsg->len > xfer_len) {
+			if (pmsg->len - 1 == xfer_len) {
+				val = readw(i2c_dev->base + REG_CR);
+				val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
+				writew(val, i2c_dev->base + REG_CR);
+			} else {
+				val = readw(i2c_dev->base + REG_CR);
+				val |= CR_CPU_RDY;
+				writew(val, i2c_dev->base + REG_CR);
+			}
+		} else if (pmsg->len == xfer_len) {
+			break;
+		} else {
+			ret = -EIO;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int wmt_i2c_xfer(struct i2c_adapter *adap,
+			struct i2c_msg msgs[],
+			int num)
+{
+	struct i2c_msg *pmsg;
+	int i;
+	int ret = 0;
+	int is_last;
+	int restart;
+
+	for (i = 0; ret >= 0 && i < num; i++) {
+		is_last = ((i + 1) == num);
+		restart = (i != 0);
+
+		pmsg = &msgs[i];
+		if (pmsg->flags & I2C_M_NOSTART)
+			restart = 1;
+		if (pmsg->flags & I2C_M_RD)
+			ret = wmt_i2c_read(adap, pmsg, restart, is_last);
+		else
+			ret = wmt_i2c_write(adap, pmsg, restart, is_last);
+	}
+
+	if (ret < 0)
+		return ret;
+	else
+		return i;
+}
+
+static u32 wmt_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm wmt_i2c_algo = {
+	.master_xfer	= wmt_i2c_xfer,
+	.functionality	= wmt_i2c_func,
+};
+
+static irqreturn_t wmt_i2c_isr(int irq, void *data)
+{
+	struct wmt_i2c_dev *i2c_dev = data;
+
+	/* save the status and write-clear it */
+	i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
+	writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
+
+	complete(&i2c_dev->complete);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Due to a lack of pinmux functionality we need to manually configure
+ * the GPIO pullup. Once pinmux is implemented, this function should be
+ * removed. Pullup's are not available on vt8500 or wm8505 so we skip.
+ */
+static int wmt_i2c_setup_gpio(struct wmt_i2c_dev *i2c_dev)
+{
+	struct device_node *np;
+	void __iomem *gpio_base;
+	int nr = i2c_dev->adapter.nr;
+	u8 val;
+	u8 mask;
+
+	/* VT8500 - has external pullups so no configuration required. */
+	if (of_machine_is_compatible("via,vt8500"))
+		return 0;
+
+	/*
+	 * WM8505 - has external pullups but we need to config the alt func
+	 * WM8650 - has programmable pullups + alt func
+	 * WM8850 - has programmable pullups + alt func
+	 */
+	if (of_machine_is_compatible("wm,wm8505")) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+		if (!np) {
+			dev_err(i2c_dev->dev, "GPIO required for WM8505 i2c\n");
+			return -EINVAL;
+		}
+	} else if (of_machine_is_compatible("wm,wm8650") ||
+		   of_machine_is_compatible("wm,wm8850")) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8650-gpio");
+		if (!np) {
+			dev_err(i2c_dev->dev, "GPIO required for WM8650 i2c\n");
+			return -EINVAL;
+		}
+	} else {
+		/* If we don't know what machine, assume its configured */
+		dev_warn(i2c_dev->dev, "unrecognised machine\n");
+		return 0;
+	}
+
+	gpio_base = of_iomap(np, 0);
+	if (!gpio_base) {
+		dev_err(i2c_dev->dev, "failed to map gpio memory\n");
+		return -ENOMEM;
+	}
+
+	if (of_machine_is_compatible("wm,wm8505")) {
+		if (nr == 0) {
+			/* Set gpio pins to alt function */
+			val = readb(gpio_base + 0x500);
+			writeb(val & 0xFC, gpio_base + 0x500);
+		}
+	} else if (of_machine_is_compatible("wm,wm8650")) {
+		if (nr == 0) {
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x55);
+			val &= ~(BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x55);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x495);
+			val |= (BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x495);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4D5);
+			val |= (BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x4D5);
+		} else if (nr == 1) {
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x49);
+			val &= ~(BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x49);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x489);
+			val |= (BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x489);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4C9);
+			val |= (BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x4C9);
+		}
+	} else if (of_machine_is_compatible("wm,wm8850")) {
+		if ((nr >= 0) && (nr <= 2)) {
+			mask = 0x03 << (nr << 1);
+	
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x55);
+			val &= ~mask;
+			writeb(val, gpio_base + 0x55);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x495);
+			val |= mask;
+			writeb(val, gpio_base + 0x495);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4D5);
+			val |= mask;
+			writeb(val, gpio_base + 0x4D5);
+		}
+	}
+
+
+	iounmap(gpio_base);
+
+	return 0;
+}
+
+static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
+{
+	int err;
+
+	err = clk_prepare_enable(i2c_dev->clk);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to enable clock\n");
+		return err;
+	}
+
+	err = clk_set_rate(i2c_dev->clk, 20000000);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
+		return err;
+	}
+
+	err = wmt_i2c_setup_gpio(i2c_dev);
+	if (err)
+		return err;
+
+	writew(0, i2c_dev->base + REG_CR);
+	writew(12, i2c_dev->base + REG_MCR);
+	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
+	writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
+	writew(CR_ENABLE, i2c_dev->base + REG_CR);
+	readw(i2c_dev->base + REG_CSR);		/* read clear */
+	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		writew(0x8064, i2c_dev->base + REG_TR);
+	else
+		writew(0x8019, i2c_dev->base + REG_TR);
+
+	return 0;
+}
+
+static int wmt_i2c_probe(struct platform_device *pdev)
+{
+	struct device_node	*np = pdev->dev.of_node;
+	struct wmt_i2c_dev	*i2c_dev;
+	struct i2c_adapter	*adap;
+	struct resource		*res;
+	int err;
+	u32 clk_rate;
+
+	if (!np) {
+		dev_err(&pdev->dev, "device node not found\n");
+		return -ENODEV;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no memory resource defined\n");
+		return -ENODEV;
+	}
+
+	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+	if (!i2c_dev) {
+		dev_err(&pdev->dev, "device memory allocation failed\n");
+		return -ENOMEM;
+	}
+
+	i2c_dev->base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!i2c_dev->base) {
+		dev_err(&pdev->dev, "memory region unavailable\n");
+		return -ENOMEM;
+	}
+
+	i2c_dev->irq = irq_of_parse_and_map(np, 0);
+	if (!i2c_dev->irq) {
+		dev_err(&pdev->dev, "irq missing or invalid\n");
+		return -EINVAL;
+	}
+
+	i2c_dev->clk = of_clk_get(np, 0);
+	if (IS_ERR(i2c_dev->clk)) {
+		dev_err(&pdev->dev, "unable to request clock\n");
+		return PTR_ERR(i2c_dev->clk);
+	}
+
+	i2c_dev->mode = I2C_MODE_STANDARD;
+	err = of_property_read_u32(np, "clock-frequency", &clk_rate);
+	if ((!err) && (clk_rate == 400000))
+		i2c_dev->mode = I2C_MODE_FAST;
+
+	i2c_dev->dev = &pdev->dev;
+
+	err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
+							"i2c", i2c_dev);
+	if (err) {
+		dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
+		return err;
+	}
+
+	adap = &i2c_dev->adapter;
+	i2c_set_adapdata(adap, i2c_dev);
+	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
+	adap->owner		= THIS_MODULE;
+	adap->class		= I2C_CLASS_HWMON;
+	adap->algo		= &wmt_i2c_algo;
+	adap->dev.parent	= &pdev->dev;
+	adap->dev.of_node	= pdev->dev.of_node;
+	adap->nr		= of_alias_get_id(pdev->dev.of_node, "i2c");
+
+	err = wmt_i2c_reset_hardware(i2c_dev);
+	if (err) {
+		dev_err(&pdev->dev, "error initializing hardware\n");
+		return err;
+	}
+
+	if (adap->nr < 0)
+		err = i2c_add_adapter(adap);
+	else
+		err = i2c_add_numbered_adapter(adap);
+
+	if (err) {
+		dev_err(&pdev->dev, "failed to add adapter\n");
+		return err;
+	}
+
+	platform_set_drvdata(pdev, i2c_dev);
+
+	of_i2c_register_devices(adap);
+
+	return 0;
+}
+
+static int wmt_i2c_remove(struct platform_device *pdev)
+{
+	struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(&i2c_dev->adapter);
+
+	return 0;
+}
+
+static struct of_device_id wmt_i2c_dt_ids[] = {
+	{ .compatible = "wm,wm8505-i2c" },
+	{ /* Sentinel */ },
+};
+
+static struct platform_driver wmt_i2c_driver = {
+	.probe		= wmt_i2c_probe,
+	.remove		= wmt_i2c_remove,
+	.driver		= {
+		.name	= "wmt-i2c",
+		.owner	= THIS_MODULE,
+		.of_match_table = wmt_i2c_dt_ids,
+	},
+};
+
+module_platform_driver(wmt_i2c_driver);
+
+MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
+MODULE_AUTHOR("Tony Prisk <linux-ci5G2KO2hbZ+pU9mqzGVBQ@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
-- 
1.7.9.5

Re: [GIT PULL] i2c: vt8500: Add support for Wondermedia I2C master-mode

[Wolfram Sang]

> This patch has been floating around since 27 december with no replies so
> here is a pull-request for it.

I'll review it tomorrow.

Re: [PATCH] i2c: vt8500: Add support for Wondermedia I2C master-mode

[Wolfram Sang]

Ho Tony,

here is my review.

On Wed, Jan 16, 2013 at 06:52:26PM +1300, Tony Prisk wrote:
> This patch adds support for the I2C controller found on Wondermedia
> SoCs.
> 
> Due to the lack of pinmux support, GPIO pin alternate functions are
> configured by machine's compatible property, as are pullups.

Is there pinmux support planned/on its way? Maybe it is worth waiting
for it? If not, I'd think the setup should be done in mach-code, not the
driver.

> diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
> new file mode 100644
> index 0000000..07d86e3
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-wmt.c
> @@ -0,0 +1,636 @@
> +/*
> + *  Wondermedia I2C Master Mode Driver
> + *
> + *  Copyright (C) 2012 Tony Prisk <linux-ci5G2KO2hbZ+pU9mqzGVBQ@public.gmane.org>
> + *
> + *  Derived from GPL licensed source:
> + *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
> + *
> + *  This program is free software; you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License version 2 as
> + *  published by the Free Software Foundation
> + */

Are the sources you derived from also V2 only? Otherwise you might be
changing other people's license decision.

> +static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
> +{
> +	u16 val;
> +	int i;
> +	int ret = 0;
> +
> +	for (i = 0; i < 10000000; i++) {
> +		val = readw(i2c_dev->base + REG_CSR);
> +		if (val & CSR_READY_MASK)
> +			break;
> +
> +		udelay(1);
> +	}
> +	if (i >= 9999999)
> +		ret = -EBUSY;
> +
> +	return ret;
> +}

That's 10 seconds (max) of busy looping? Nah, please don't hog the CPU
for that.

> +
> +static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
> +{
> +	int ret = 0;
> +
> +	if (i2c_dev->cmd_status & ISR_NACK_ADDR)
> +		ret = -EIO;
> +
> +	if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
> +		ret = -ETIMEDOUT;
> +
> +	return ret;
> +}
> +
> +static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
> +						   int restart, int last)
> +{
> +	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> +	u16 val;
> +	u16 tcr_val;

I'd prefer to aggregate the last two lines (here and in general), but no
strong opinion on that.

> +	int ret;
> +	int wait_result;
> +	u32 xfer_len = 0;
> +
> +	if (pmsg->len < 0)
> +		return -EINVAL;

len is a u16.

> +
> +	if (restart == 0) {

I think '!restart' is a tad more readable, but again, no strong opinion.

> +		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
> +		if (ret < 0)
> +			return ret;
> +	}
> +
> +	if (pmsg->len == 0)
> +		writew(0, i2c_dev->base + REG_CDR);
> +	else
> +		writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
> +
> +	if (restart == 0) {
> +		val = readw(i2c_dev->base + REG_CR);
> +		val &= ~CR_TX_END;
> +		writew(val, i2c_dev->base + REG_CR);
> +
> +		val = readw(i2c_dev->base + REG_CR);
> +		val |= CR_CPU_RDY;
> +		writew(val, i2c_dev->base + REG_CR);

Just to make sure: Not possible to do both in one write?

> +	}
> +
> +	init_completion(&i2c_dev->complete);
> +
> +	if (i2c_dev->mode == I2C_MODE_STANDARD)
> +		tcr_val = TCR_STANDARD_MODE;
> +	else
> +		tcr_val = TCR_FAST_MODE;
> +
> +	tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
> +
> +	writew(tcr_val, i2c_dev->base + REG_TCR);
> +
> +	if (restart == 1) {
> +		val = readw(i2c_dev->base + REG_CR);
> +		val |= CR_CPU_RDY;
> +		writew(val, i2c_dev->base + REG_CR);
> +	}
> +
> +	ret = 0;
> +
> +	for (;;) {

Have you tried 'while (xfer_len < pmsg->len) ...' and directly 'return
err' on errors? Might have potential to be more concise.

> +		wait_result = wait_for_completion_interruptible_timeout(
> +				&i2c_dev->complete, 500 * HZ / 1000);

Please don't use interruptible here. Most drivers had lots of problems
with it and it seems you are not checking the signals anyhow.

> +
> +		if (wait_result == 0) {
> +			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
> +			ret = -ETIMEDOUT;
> +			break;
> +		}
> +
> +		ret = wmt_check_status(i2c_dev);
> +		if (ret)
> +			break;
> +
> +		xfer_len++;
> +
> +		val = readw(i2c_dev->base + REG_CSR);
> +		if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
> +			dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
> +			ret = -EIO;
> +			break;
> +		}
> +
> +		if (pmsg->len == 0) {
> +			val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
> +			writew(val, i2c_dev->base + REG_CR);
> +			break;
> +		}
> +
> +		if (pmsg->len > xfer_len) {
> +			writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
> +								REG_CDR);
> +			writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
> +		} else if (pmsg->len == xfer_len) {
> +			if (last != 1)
> +				writew(CR_ENABLE, i2c_dev->base + REG_CR);
> +			break;
> +		} else {
> +			dev_dbg(i2c_dev->dev, "unknown error (tx)\n");
> +			ret = -EIO;
> +			break;
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
> +						  int restart, int last)

Same comment as for the write function. 

> +{
> +	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> +	u16 val;
> +	u16 tcr_val;
> +	int ret;
> +	int wait_result;
> +	u32 xfer_len = 0;
> +
> +	if (pmsg->len <= 0)
> +		return -EINVAL;
> +
> +	if (restart == 0) {
> +		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
> +		if (ret < 0)
> +			return ret;
> +	}
> +
> +	val = readw(i2c_dev->base + REG_CR);
> +	val &= ~CR_TX_END;
> +	writew(val, i2c_dev->base + REG_CR);
> +
> +	val = readw(i2c_dev->base + REG_CR);
> +	val &= ~CR_TX_NEXT_NO_ACK;
> +	writew(val, i2c_dev->base + REG_CR);
> +
> +	if (restart == 0) {
> +		val = readw(i2c_dev->base + REG_CR);
> +		val |= CR_CPU_RDY;
> +		writew(val, i2c_dev->base + REG_CR);
> +	}
> +
> +	if (pmsg->len == 1) {
> +		val = readw(i2c_dev->base + REG_CR);
> +		val |= CR_TX_NEXT_NO_ACK;
> +		writew(val, i2c_dev->base + REG_CR);
> +	}
> +
> +	init_completion(&i2c_dev->complete);
> +
> +	if (i2c_dev->mode == I2C_MODE_STANDARD)
> +		tcr_val = TCR_STANDARD_MODE;
> +	else
> +		tcr_val = TCR_FAST_MODE;
> +
> +	tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
> +
> +	writew(tcr_val, i2c_dev->base + REG_TCR);
> +
> +	if (restart == 1) {
> +		val = readw(i2c_dev->base + REG_CR);
> +		val |= CR_CPU_RDY;
> +		writew(val, i2c_dev->base + REG_CR);
> +	}
> +
> +	ret = 0;
> +
> +	for (;;) {
> +		wait_result = wait_for_completion_interruptible_timeout(
> +				&i2c_dev->complete, 500 * HZ / 1000);

no interruptible

> +
> +		if (wait_result == 0) {
> +			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
> +			ret = -ETIMEDOUT;
> +			break;
> +		}
> +
> +		ret = wmt_check_status(i2c_dev);
> +		if (ret)
> +			break;
> +
> +		pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
> +		xfer_len++;
> +
> +		if (pmsg->len > xfer_len) {
> +			if (pmsg->len - 1 == xfer_len) {
> +				val = readw(i2c_dev->base + REG_CR);
> +				val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
> +				writew(val, i2c_dev->base + REG_CR);
> +			} else {
> +				val = readw(i2c_dev->base + REG_CR);
> +				val |= CR_CPU_RDY;
> +				writew(val, i2c_dev->base + REG_CR);
> +			}
> +		} else if (pmsg->len == xfer_len) {
> +			break;
> +		} else {
> +			ret = -EIO;
> +			break;
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +static int wmt_i2c_xfer(struct i2c_adapter *adap,
> +			struct i2c_msg msgs[],
> +			int num)
> +{
> +	struct i2c_msg *pmsg;
> +	int i;
> +	int ret = 0;
> +	int is_last;
> +	int restart;
> +
> +	for (i = 0; ret >= 0 && i < num; i++) {
> +		is_last = ((i + 1) == num);
> +		restart = (i != 0);
> +
> +		pmsg = &msgs[i];
> +		if (pmsg->flags & I2C_M_NOSTART)
> +			restart = 1;
> +		if (pmsg->flags & I2C_M_RD)
> +			ret = wmt_i2c_read(adap, pmsg, restart, is_last);
> +		else
> +			ret = wmt_i2c_write(adap, pmsg, restart, is_last);
> +	}
> +
> +	if (ret < 0)
> +		return ret;
> +	else
> +		return i;
> +}

return ret < 0 ? ret : i;

> +
> +static u32 wmt_i2c_func(struct i2c_adapter *adap)
> +{
> +	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;

I2C_FUNC_NOSTART is missing.

> +}
> +
> +static const struct i2c_algorithm wmt_i2c_algo = {
> +	.master_xfer	= wmt_i2c_xfer,
> +	.functionality	= wmt_i2c_func,
> +};
> +
> +static irqreturn_t wmt_i2c_isr(int irq, void *data)
> +{
> +	struct wmt_i2c_dev *i2c_dev = data;
> +
> +	/* save the status and write-clear it */
> +	i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
> +	writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
> +
> +	complete(&i2c_dev->complete);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +/*
> + * Due to a lack of pinmux functionality we need to manually configure
> + * the GPIO pullup. Once pinmux is implemented, this function should be
> + * removed. Pullup's are not available on vt8500 or wm8505 so we skip.
> + */

As mentioned above, move to mach-code?

...

> +static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
> +{
> +	int err;
> +
> +	err = clk_prepare_enable(i2c_dev->clk);
> +	if (err) {
> +		dev_err(i2c_dev->dev, "failed to enable clock\n");
> +		return err;
> +	}
> +
> +	err = clk_set_rate(i2c_dev->clk, 20000000);
> +	if (err) {
> +		dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
> +		return err;
> +	}
> +
> +	err = wmt_i2c_setup_gpio(i2c_dev);
> +	if (err)
> +		return err;
> +
> +	writew(0, i2c_dev->base + REG_CR);
> +	writew(12, i2c_dev->base + REG_MCR);
> +	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
> +	writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
> +	writew(CR_ENABLE, i2c_dev->base + REG_CR);
> +	readw(i2c_dev->base + REG_CSR);		/* read clear */
> +	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
> +
> +	if (i2c_dev->mode == I2C_MODE_STANDARD)
> +		writew(0x8064, i2c_dev->base + REG_TR);
> +	else
> +		writew(0x8019, i2c_dev->base + REG_TR);
> +
> +	return 0;

Too many magic numbers in this last block.

> +}
> +
> +static int wmt_i2c_probe(struct platform_device *pdev)
> +{
> +	struct device_node	*np = pdev->dev.of_node;
> +	struct wmt_i2c_dev	*i2c_dev;
> +	struct i2c_adapter	*adap;
> +	struct resource		*res;

No special alignment, please.

> +	int err;
> +	u32 clk_rate;
> +
> +	if (!np) {
> +		dev_err(&pdev->dev, "device node not found\n");
> +		return -ENODEV;
> +	}
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		dev_err(&pdev->dev, "no memory resource defined\n");
> +		return -ENODEV;
> +	}

devm_request_and_ioremap will check res for you.

> +
> +	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
> +	if (!i2c_dev) {
> +		dev_err(&pdev->dev, "device memory allocation failed\n");
> +		return -ENOMEM;
> +	}
> +
> +	i2c_dev->base = devm_request_and_ioremap(&pdev->dev, res);
> +	if (!i2c_dev->base) {
> +		dev_err(&pdev->dev, "memory region unavailable\n");
> +		return -ENOMEM;
> +	}
> +
> +	i2c_dev->irq = irq_of_parse_and_map(np, 0);
> +	if (!i2c_dev->irq) {
> +		dev_err(&pdev->dev, "irq missing or invalid\n");
> +		return -EINVAL;
> +	}
> +
> +	i2c_dev->clk = of_clk_get(np, 0);

There is also devm_clk_get.

> +	if (IS_ERR(i2c_dev->clk)) {
> +		dev_err(&pdev->dev, "unable to request clock\n");
> +		return PTR_ERR(i2c_dev->clk);
> +	}
> +
> +	i2c_dev->mode = I2C_MODE_STANDARD;
> +	err = of_property_read_u32(np, "clock-frequency", &clk_rate);
> +	if ((!err) && (clk_rate == 400000))
> +		i2c_dev->mode = I2C_MODE_FAST;
> +
> +	i2c_dev->dev = &pdev->dev;
> +
> +	err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
> +							"i2c", i2c_dev);
> +	if (err) {
> +		dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
> +		return err;
> +	}
> +
> +	adap = &i2c_dev->adapter;
> +	i2c_set_adapdata(adap, i2c_dev);
> +	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
> +	adap->owner		= THIS_MODULE;
> +	adap->class		= I2C_CLASS_HWMON;
> +	adap->algo		= &wmt_i2c_algo;
> +	adap->dev.parent	= &pdev->dev;
> +	adap->dev.of_node	= pdev->dev.of_node;
> +	adap->nr		= of_alias_get_id(pdev->dev.of_node, "i2c");

No alignment with tabs, please.

> +
> +	err = wmt_i2c_reset_hardware(i2c_dev);
> +	if (err) {
> +		dev_err(&pdev->dev, "error initializing hardware\n");
> +		return err;
> +	}
> +
> +	if (adap->nr < 0)
> +		err = i2c_add_adapter(adap);
> +	else
> +		err = i2c_add_numbered_adapter(adap);
> +
> +	if (err) {
> +		dev_err(&pdev->dev, "failed to add adapter\n");
> +		return err;
> +	}
> +
> +	platform_set_drvdata(pdev, i2c_dev);
> +
> +	of_i2c_register_devices(adap);
> +
> +	return 0;
> +}
> +
> +static int wmt_i2c_remove(struct platform_device *pdev)
> +{
> +	struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
> +
> +	i2c_del_adapter(&i2c_dev->adapter);

Is it guaranteed that interrupts cannot occur anymore? Otherwise OOPS
might happen, since the adapter is cleared here already but devm will
remove the interrupt only a little later.

> +
> +	return 0;
> +}
> +
> +static struct of_device_id wmt_i2c_dt_ids[] = {
> +	{ .compatible = "wm,wm8505-i2c" },
> +	{ /* Sentinel */ },
> +};
> +
> +static struct platform_driver wmt_i2c_driver = {
> +	.probe		= wmt_i2c_probe,
> +	.remove		= wmt_i2c_remove,
> +	.driver		= {
> +		.name	= "wmt-i2c",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = wmt_i2c_dt_ids,
> +	},
> +};
> +
> +module_platform_driver(wmt_i2c_driver);
> +
> +MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
> +MODULE_AUTHOR("Tony Prisk <linux-ci5G2KO2hbZ+pU9mqzGVBQ@public.gmane.org>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);

Also, checkpatch found a trailing whitespace somewhere.

Thanks,

   Wolfram

Re: [PATCH] i2c: vt8500: Add support for Wondermedia I2C master-mode

[Tony Prisk]

Thanks for the review.
My replies are inline. Mostly 'ok' and 'will dos'.

To save you trawling through it all, here's the two replies/comments
that are *different*:

1) I am working on pinmux at the moment - will hold off on this driver
until pinmux is completed.

2)
> +	i2c_dev->clk = of_clk_get(np, 0);
> 
> There is also devm_clk_get.
devm_clk_get requires a 'clock name'.
Since vt8500 is DT-only, and clock-names is an optional property in the
clocks binding I preferred not to *require* an optional property.

If I am misunderstanding this, please correct me.

Regards
Tony Prisk


On Wed, 2013-02-13 at 21:13 +0100, Wolfram Sang wrote:
> Ho Tony,
> 
> here is my review.
> 
> On Wed, Jan 16, 2013 at 06:52:26PM +1300, Tony Prisk wrote:
> > This patch adds support for the I2C controller found on Wondermedia
> > SoCs.
> > 
> > Due to the lack of pinmux support, GPIO pin alternate functions are
> > configured by machine's compatible property, as are pullups.
> 
> Is there pinmux support planned/on its way? Maybe it is worth waiting
> for it? If not, I'd think the setup should be done in mach-code, not the
> driver.

I am actually working on pinmux at the moment so I will remove this
gpio-setup code and get the pinmux code into mainline first before
resubmitting this driver.
> 
> > diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
> > new file mode 100644
> > index 0000000..07d86e3
> > --- /dev/null
> > +++ b/drivers/i2c/busses/i2c-wmt.c
> > @@ -0,0 +1,636 @@
> > +/*
> > + *  Wondermedia I2C Master Mode Driver
> > + *
> > + *  Copyright (C) 2012 Tony Prisk <linux-ci5G2KO2hbZ+pU9mqzGVBQ@public.gmane.org>
> > + *
> > + *  Derived from GPL licensed source:
> > + *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
> > + *
> > + *  This program is free software; you can redistribute it and/or modify
> > + *  it under the terms of the GNU General Public License version 2 as
> > + *  published by the Free Software Foundation
> > + */
> 
> Are the sources you derived from also V2 only? Otherwise you might be
> changing other people's license decision.

Oh dear.. almost.
Original source was v2 or later. I will update the license text to
indicate 'later' is also applicable.
> 
> > +static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
> > +{
> > +	u16 val;
> > +	int i;
> > +	int ret = 0;
> > +
> > +	for (i = 0; i < 10000000; i++) {
> > +		val = readw(i2c_dev->base + REG_CSR);
> > +		if (val & CSR_READY_MASK)
> > +			break;
> > +
> > +		udelay(1);
> > +	}
> > +	if (i >= 9999999)
> > +		ret = -EBUSY;
> > +
> > +	return ret;
> > +}
> 
> That's 10 seconds (max) of busy looping? Nah, please don't hog the CPU
> for that.
Eek. Not sure how I missed that. Will fix.
> 
> > +
> > +static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
> > +{
> > +	int ret = 0;
> > +
> > +	if (i2c_dev->cmd_status & ISR_NACK_ADDR)
> > +		ret = -EIO;
> > +
> > +	if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
> > +		ret = -ETIMEDOUT;
> > +
> > +	return ret;
> > +}
> > +
> > +static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
> > +						   int restart, int last)
> > +{
> > +	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> > +	u16 val;
> > +	u16 tcr_val;
> 
> I'd prefer to aggregate the last two lines (here and in general), but no
> strong opinion on that.
My preference is for one variable per line but I'm happy to go with the
majority (if there is one).
> 
> > +	int ret;
> > +	int wait_result;
> > +	u32 xfer_len = 0;
> > +
> > +	if (pmsg->len < 0)
> > +		return -EINVAL;
> 
> len is a u16.
Sorry - copied verbatim from the vendor source.. I should know better by
now.
> 
> > +
> > +	if (restart == 0) {
> 
> I think '!restart' is a tad more readable, but again, no strong opinion.
Agree - will change.
> 
> > +		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
> > +		if (ret < 0)
> > +			return ret;
> > +	}
> > +
> > +	if (pmsg->len == 0)
> > +		writew(0, i2c_dev->base + REG_CDR);
> > +	else
> > +		writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
> > +
> > +	if (restart == 0) {
> > +		val = readw(i2c_dev->base + REG_CR);
> > +		val &= ~CR_TX_END;
> > +		writew(val, i2c_dev->base + REG_CR);
> > +
> > +		val = readw(i2c_dev->base + REG_CR);
> > +		val |= CR_CPU_RDY;
> > +		writew(val, i2c_dev->base + REG_CR);
> 
> Just to make sure: Not possible to do both in one write?
I don't know the answer to that question. The original vendor source did
it with two separate read-modify-write calls, so I kept it the same.

I can test it, although at first glance, I would guess it's done this
way because val |= CR_CPU_RDY will start the transfer immediately and
the val &= ~CR_TX_END may not have been processed within the
hardware?!?!

> 
> > +	}
> > +
> > +	init_completion(&i2c_dev->complete);
> > +
> > +	if (i2c_dev->mode == I2C_MODE_STANDARD)
> > +		tcr_val = TCR_STANDARD_MODE;
> > +	else
> > +		tcr_val = TCR_FAST_MODE;
> > +
> > +	tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
> > +
> > +	writew(tcr_val, i2c_dev->base + REG_TCR);
> > +
> > +	if (restart == 1) {
> > +		val = readw(i2c_dev->base + REG_CR);
> > +		val |= CR_CPU_RDY;
> > +		writew(val, i2c_dev->base + REG_CR);
> > +	}
> > +
> > +	ret = 0;
> > +
> > +	for (;;) {
> 
> Have you tried 'while (xfer_len < pmsg->len) ...' and directly 'return
> err' on errors? Might have potential to be more concise.
Can do.
> 
> > +		wait_result = wait_for_completion_interruptible_timeout(
> > +				&i2c_dev->complete, 500 * HZ / 1000);
> 
> Please don't use interruptible here. Most drivers had lots of problems
> with it and it seems you are not checking the signals anyhow.
Again, taken from vendor source - will change.
> 
> > +
> > +		if (wait_result == 0) {
> > +			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
> > +			ret = -ETIMEDOUT;
> > +			break;
> > +		}
> > +
> > +		ret = wmt_check_status(i2c_dev);
> > +		if (ret)
> > +			break;
> > +
> > +		xfer_len++;
> > +
> > +		val = readw(i2c_dev->base + REG_CSR);
> > +		if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
> > +			dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
> > +			ret = -EIO;
> > +			break;
> > +		}
> > +
> > +		if (pmsg->len == 0) {
> > +			val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
> > +			writew(val, i2c_dev->base + REG_CR);
> > +			break;
> > +		}
> > +
> > +		if (pmsg->len > xfer_len) {
> > +			writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
> > +								REG_CDR);
> > +			writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
> > +		} else if (pmsg->len == xfer_len) {
> > +			if (last != 1)
> > +				writew(CR_ENABLE, i2c_dev->base + REG_CR);
> > +			break;
> > +		} else {
> > +			dev_dbg(i2c_dev->dev, "unknown error (tx)\n");
> > +			ret = -EIO;
> > +			break;
> > +		}
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
> > +						  int restart, int last)
> 
> Same comment as for the write function. 
> 
> > +{
> > +	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> > +	u16 val;
> > +	u16 tcr_val;
> > +	int ret;
> > +	int wait_result;
> > +	u32 xfer_len = 0;
> > +
> > +	if (pmsg->len <= 0)
> > +		return -EINVAL;
> > +
> > +	if (restart == 0) {
> > +		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
> > +		if (ret < 0)
> > +			return ret;
> > +	}
> > +
> > +	val = readw(i2c_dev->base + REG_CR);
> > +	val &= ~CR_TX_END;
> > +	writew(val, i2c_dev->base + REG_CR);
> > +
> > +	val = readw(i2c_dev->base + REG_CR);
> > +	val &= ~CR_TX_NEXT_NO_ACK;
> > +	writew(val, i2c_dev->base + REG_CR);
> > +
> > +	if (restart == 0) {
> > +		val = readw(i2c_dev->base + REG_CR);
> > +		val |= CR_CPU_RDY;
> > +		writew(val, i2c_dev->base + REG_CR);
> > +	}
> > +
> > +	if (pmsg->len == 1) {
> > +		val = readw(i2c_dev->base + REG_CR);
> > +		val |= CR_TX_NEXT_NO_ACK;
> > +		writew(val, i2c_dev->base + REG_CR);
> > +	}
> > +
> > +	init_completion(&i2c_dev->complete);
> > +
> > +	if (i2c_dev->mode == I2C_MODE_STANDARD)
> > +		tcr_val = TCR_STANDARD_MODE;
> > +	else
> > +		tcr_val = TCR_FAST_MODE;
> > +
> > +	tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
> > +
> > +	writew(tcr_val, i2c_dev->base + REG_TCR);
> > +
> > +	if (restart == 1) {
> > +		val = readw(i2c_dev->base + REG_CR);
> > +		val |= CR_CPU_RDY;
> > +		writew(val, i2c_dev->base + REG_CR);
> > +	}
> > +
> > +	ret = 0;
> > +
> > +	for (;;) {
> > +		wait_result = wait_for_completion_interruptible_timeout(
> > +				&i2c_dev->complete, 500 * HZ / 1000);
> 
> no interruptible
> 
> > +
> > +		if (wait_result == 0) {
> > +			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
> > +			ret = -ETIMEDOUT;
> > +			break;
> > +		}
> > +
> > +		ret = wmt_check_status(i2c_dev);
> > +		if (ret)
> > +			break;
> > +
> > +		pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
> > +		xfer_len++;
> > +
> > +		if (pmsg->len > xfer_len) {
> > +			if (pmsg->len - 1 == xfer_len) {
> > +				val = readw(i2c_dev->base + REG_CR);
> > +				val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
> > +				writew(val, i2c_dev->base + REG_CR);
> > +			} else {
> > +				val = readw(i2c_dev->base + REG_CR);
> > +				val |= CR_CPU_RDY;
> > +				writew(val, i2c_dev->base + REG_CR);
> > +			}
> > +		} else if (pmsg->len == xfer_len) {
> > +			break;
> > +		} else {
> > +			ret = -EIO;
> > +			break;
> > +		}
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +static int wmt_i2c_xfer(struct i2c_adapter *adap,
> > +			struct i2c_msg msgs[],
> > +			int num)
> > +{
> > +	struct i2c_msg *pmsg;
> > +	int i;
> > +	int ret = 0;
> > +	int is_last;
> > +	int restart;
> > +
> > +	for (i = 0; ret >= 0 && i < num; i++) {
> > +		is_last = ((i + 1) == num);
> > +		restart = (i != 0);
> > +
> > +		pmsg = &msgs[i];
> > +		if (pmsg->flags & I2C_M_NOSTART)
> > +			restart = 1;
> > +		if (pmsg->flags & I2C_M_RD)
> > +			ret = wmt_i2c_read(adap, pmsg, restart, is_last);
> > +		else
> > +			ret = wmt_i2c_write(adap, pmsg, restart, is_last);
> > +	}
> > +
> > +	if (ret < 0)
> > +		return ret;
> > +	else
> > +		return i;
> > +}
> 
> return ret < 0 ? ret : i;
> 
> > +
> > +static u32 wmt_i2c_func(struct i2c_adapter *adap)
> > +{
> > +	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> 
> I2C_FUNC_NOSTART is missing.
Again - taken from vendor source as is. Will read the book (to find out
what it does) and add.
> 
> > +}
> > +
> > +static const struct i2c_algorithm wmt_i2c_algo = {
> > +	.master_xfer	= wmt_i2c_xfer,
> > +	.functionality	= wmt_i2c_func,
> > +};
> > +
> > +static irqreturn_t wmt_i2c_isr(int irq, void *data)
> > +{
> > +	struct wmt_i2c_dev *i2c_dev = data;
> > +
> > +	/* save the status and write-clear it */
> > +	i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
> > +	writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
> > +
> > +	complete(&i2c_dev->complete);
> > +
> > +	return IRQ_HANDLED;
> > +}
> > +
> > +/*
> > + * Due to a lack of pinmux functionality we need to manually configure
> > + * the GPIO pullup. Once pinmux is implemented, this function should be
> > + * removed. Pullup's are not available on vt8500 or wm8505 so we skip.
> > + */
> 
> As mentioned above, move to mach-code?
Will drop before v2.
> 
> ...
> 
> > +static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
> > +{
> > +	int err;
> > +
> > +	err = clk_prepare_enable(i2c_dev->clk);
> > +	if (err) {
> > +		dev_err(i2c_dev->dev, "failed to enable clock\n");
> > +		return err;
> > +	}
> > +
> > +	err = clk_set_rate(i2c_dev->clk, 20000000);
> > +	if (err) {
> > +		dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
> > +		return err;
> > +	}
> > +
> > +	err = wmt_i2c_setup_gpio(i2c_dev);
> > +	if (err)
> > +		return err;
> > +
> > +	writew(0, i2c_dev->base + REG_CR);
> > +	writew(12, i2c_dev->base + REG_MCR);
> > +	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
> > +	writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
> > +	writew(CR_ENABLE, i2c_dev->base + REG_CR);
> > +	readw(i2c_dev->base + REG_CSR);		/* read clear */
> > +	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
> > +
> > +	if (i2c_dev->mode == I2C_MODE_STANDARD)
> > +		writew(0x8064, i2c_dev->base + REG_TR);
> > +	else
> > +		writew(0x8019, i2c_dev->base + REG_TR);
> > +
> > +	return 0;
> 
> Too many magic numbers in this last block.
When I wrote this piece of code I had no idea what these magic numbers
meant. I've since figured it out and will redo.
> 
> > +}
> > +
> > +static int wmt_i2c_probe(struct platform_device *pdev)
> > +{
> > +	struct device_node	*np = pdev->dev.of_node;
> > +	struct wmt_i2c_dev	*i2c_dev;
> > +	struct i2c_adapter	*adap;
> > +	struct resource		*res;
> 
> No special alignment, please.
Ok.
> 
> > +	int err;
> > +	u32 clk_rate;
> > +
> > +	if (!np) {
> > +		dev_err(&pdev->dev, "device node not found\n");
> > +		return -ENODEV;
> > +	}
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	if (!res) {
> > +		dev_err(&pdev->dev, "no memory resource defined\n");
> > +		return -ENODEV;
> > +	}
> 
> devm_request_and_ioremap will check res for you.
Ok. Will drop the error check.
> 
> > +
> > +	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
> > +	if (!i2c_dev) {
> > +		dev_err(&pdev->dev, "device memory allocation failed\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	i2c_dev->base = devm_request_and_ioremap(&pdev->dev, res);
> > +	if (!i2c_dev->base) {
> > +		dev_err(&pdev->dev, "memory region unavailable\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	i2c_dev->irq = irq_of_parse_and_map(np, 0);
> > +	if (!i2c_dev->irq) {
> > +		dev_err(&pdev->dev, "irq missing or invalid\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	i2c_dev->clk = of_clk_get(np, 0);
> 
> There is also devm_clk_get.
devm_clk_get requires a 'clock name'.
Since vt8500 is DT-only, and clock-names is an optional property in the
clocks binding I preferred not to *require* an optional property.

If I am misunderstanding this, please correct me.
> 
> > +	if (IS_ERR(i2c_dev->clk)) {
> > +		dev_err(&pdev->dev, "unable to request clock\n");
> > +		return PTR_ERR(i2c_dev->clk);
> > +	}
> > +
> > +	i2c_dev->mode = I2C_MODE_STANDARD;
> > +	err = of_property_read_u32(np, "clock-frequency", &clk_rate);
> > +	if ((!err) && (clk_rate == 400000))
> > +		i2c_dev->mode = I2C_MODE_FAST;
> > +
> > +	i2c_dev->dev = &pdev->dev;
> > +
> > +	err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
> > +							"i2c", i2c_dev);
> > +	if (err) {
> > +		dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
> > +		return err;
> > +	}
> > +
> > +	adap = &i2c_dev->adapter;
> > +	i2c_set_adapdata(adap, i2c_dev);
> > +	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
> > +	adap->owner		= THIS_MODULE;
> > +	adap->class		= I2C_CLASS_HWMON;
> > +	adap->algo		= &wmt_i2c_algo;
> > +	adap->dev.parent	= &pdev->dev;
> > +	adap->dev.of_node	= pdev->dev.of_node;
> > +	adap->nr		= of_alias_get_id(pdev->dev.of_node, "i2c");
> 
> No alignment with tabs, please.
Ok.
> 
> > +
> > +	err = wmt_i2c_reset_hardware(i2c_dev);
> > +	if (err) {
> > +		dev_err(&pdev->dev, "error initializing hardware\n");
> > +		return err;
> > +	}
> > +
> > +	if (adap->nr < 0)
> > +		err = i2c_add_adapter(adap);
> > +	else
> > +		err = i2c_add_numbered_adapter(adap);
> > +
> > +	if (err) {
> > +		dev_err(&pdev->dev, "failed to add adapter\n");
> > +		return err;
> > +	}
> > +
> > +	platform_set_drvdata(pdev, i2c_dev);
> > +
> > +	of_i2c_register_devices(adap);
> > +
> > +	return 0;
> > +}
> > +
> > +static int wmt_i2c_remove(struct platform_device *pdev)
> > +{
> > +	struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
> > +
> > +	i2c_del_adapter(&i2c_dev->adapter);
> 
> Is it guaranteed that interrupts cannot occur anymore? Otherwise OOPS
> might happen, since the adapter is cleared here already but devm will
> remove the interrupt only a little later.
Hmm.. good point. I will add some hw-stop code in here as well.
> 
> > +
> > +	return 0;
> > +}
> > +
> > +static struct of_device_id wmt_i2c_dt_ids[] = {
> > +	{ .compatible = "wm,wm8505-i2c" },
> > +	{ /* Sentinel */ },
> > +};
> > +
> > +static struct platform_driver wmt_i2c_driver = {
> > +	.probe		= wmt_i2c_probe,
> > +	.remove		= wmt_i2c_remove,
> > +	.driver		= {
> > +		.name	= "wmt-i2c",
> > +		.owner	= THIS_MODULE,
> > +		.of_match_table = wmt_i2c_dt_ids,
> > +	},
> > +};
> > +
> > +module_platform_driver(wmt_i2c_driver);
> > +
> > +MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
> > +MODULE_AUTHOR("Tony Prisk <linux-ci5G2KO2hbZ+pU9mqzGVBQ@public.gmane.org>");
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
> 
> Also, checkpatch found a trailing whitespace somewhere.
> 
> Thanks,
> 
>    Wolfram

Re: [PATCH] i2c: vt8500: Add support for Wondermedia I2C master-mode

[Wolfram Sang]

Hi Tony,

> 1) I am working on pinmux at the moment - will hold off on this driver
> until pinmux is completed.

Cool, great work!

> 2)
> > +	i2c_dev->clk = of_clk_get(np, 0);
> > 
> > There is also devm_clk_get.
> devm_clk_get requires a 'clock name'.
> Since vt8500 is DT-only, and clock-names is an optional property in the
> clocks binding I preferred not to *require* an optional property.

OK then. Just wanted to mention it.

Thanks,

   Wolfram

[PATCH] i2c: vt8500: Add support for Wondermedia I2C master-mode

[Tony Prisk]

This patch adds support for the I2C controller found on Wondermedia
SoCs.

Due to the lack of pinmux support, GPIO pin alternate functions are
configured by machine's compatible property, as are pullups.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
 .../devicetree/bindings/i2c/i2c-vt8500.txt         |   24 +
 drivers/i2c/busses/Kconfig                         |    7 +
 drivers/i2c/busses/Makefile                        |    1 +
 drivers/i2c/busses/i2c-wmt.c                       |  636 ++++++++++++++++++++
 4 files changed, 668 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
 create mode 100644 drivers/i2c/busses/i2c-wmt.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
new file mode 100644
index 0000000..94a425e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
@@ -0,0 +1,24 @@
+* Wondermedia I2C Controller
+
+Required properties :
+
+ - compatible : should be "wm,wm8505-i2c"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number
+ - clocks : phandle to the I2C clock source
+
+Optional properties :
+
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+	Valid values are 100000 and 400000.
+	Default to 100000 if not specified, or invalid value.
+
+Example :
+
+	i2c_0: i2c@d8280000 {
+		compatible = "wm,wm8505-i2c";
+		reg = <0xd8280000 0x1000>;
+		interrupts = <19>;
+		clocks = <&clki2c0>;
+		clock-frequency = <400000>;
+	};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bdca511..41270fa 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -700,6 +700,13 @@ config I2C_VERSATILE
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-versatile.
 
+config I2C_WMT
+	tristate "Wondermedia I2C Controller support"
+	depends on ARCH_VT8500
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C controllers found in Wondermedia SoCs.
+
 config I2C_OCTEON
 	tristate "Cavium OCTEON I2C bus support"
 	depends on CPU_CAVIUM_OCTEON
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 6181f3f..dce6299 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
+obj-$(CONFIG_I2C_WMT)		+= i2c-wmt.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
 obj-$(CONFIG_I2C_XILINX)	+= i2c-xiic.o
 obj-$(CONFIG_I2C_XLR)		+= i2c-xlr.o
diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
new file mode 100644
index 0000000..07d86e3
--- /dev/null
+++ b/drivers/i2c/busses/i2c-wmt.c
@@ -0,0 +1,636 @@
+/*
+ *  Wondermedia I2C Master Mode Driver
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ *  Derived from GPL licensed source:
+ *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_i2c.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define REG_CR		0x00
+#define REG_TCR		0x02
+#define REG_CSR		0x04
+#define REG_ISR		0x06
+#define REG_IMR		0x08
+#define REG_CDR		0x0A
+#define REG_TR		0x0C
+#define REG_MCR		0x0E
+#define REG_SLAVE_CR	0x10
+#define REG_SLAVE_SR	0x12
+#define REG_SLAVE_ISR	0x14
+#define REG_SLAVE_IMR	0x16
+#define REG_SLAVE_DR	0x18
+#define REG_SLAVE_TR	0x1A
+
+/* REG_CR Bit fields */
+#define CR_TX_NEXT_ACK		0x0000
+#define CR_ENABLE		0x0001
+#define CR_TX_NEXT_NO_ACK	0x0002
+#define CR_TX_END		0x0004
+#define CR_CPU_RDY		0x0008
+#define SLAV_MODE_SEL		0x8000
+
+/* REG_TCR Bit fields */
+#define TCR_STANDARD_MODE	0x0000
+#define TCR_MASTER_WRITE	0x0000
+#define TCR_HS_MODE		0x2000
+#define TCR_MASTER_READ		0x4000
+#define TCR_FAST_MODE		0x8000
+#define TCR_SLAVE_ADDR_MASK	0x007F
+
+/* REG_ISR Bit fields */
+#define ISR_NACK_ADDR		0x0001
+#define ISR_BYTE_END		0x0002
+#define ISR_SCL_TIMEOUT		0x0004
+#define ISR_WRITE_ALL		0x0007
+
+/* REG_IMR Bit fields */
+#define IMR_ENABLE_ALL		0x0007
+
+/* REG_CSR Bit fields */
+#define CSR_RCV_NOT_ACK		0x0001
+#define CSR_RCV_ACK_MASK	0x0001
+#define CSR_READY_MASK		0x0002
+
+#define I2C_MODE_STANDARD	0
+#define I2C_MODE_FAST		1
+
+
+
+struct wmt_i2c_dev {
+	struct i2c_adapter	adapter;
+	struct completion	complete;
+	struct device		*dev;
+	void __iomem		*base;
+	struct clk		*clk;
+	int			mode;
+	int			irq;
+	u16			cmd_status;
+};
+
+static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
+{
+	u16 val;
+	int i;
+	int ret = 0;
+
+	for (i = 0; i < 10000000; i++) {
+		val = readw(i2c_dev->base + REG_CSR);
+		if (val & CSR_READY_MASK)
+			break;
+
+		udelay(1);
+	}
+	if (i >= 9999999)
+		ret = -EBUSY;
+
+	return ret;
+}
+
+static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
+{
+	int ret = 0;
+
+	if (i2c_dev->cmd_status & ISR_NACK_ADDR)
+		ret = -EIO;
+
+	if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
+		ret = -ETIMEDOUT;
+
+	return ret;
+}
+
+static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
+						   int restart, int last)
+{
+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	u16 val;
+	u16 tcr_val;
+	int ret;
+	int wait_result;
+	u32 xfer_len = 0;
+
+	if (pmsg->len < 0)
+		return -EINVAL;
+
+	if (restart == 0) {
+		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (pmsg->len == 0)
+		writew(0, i2c_dev->base + REG_CDR);
+	else
+		writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
+
+	if (restart == 0) {
+		val = readw(i2c_dev->base + REG_CR);
+		val &= ~CR_TX_END;
+		writew(val, i2c_dev->base + REG_CR);
+
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	init_completion(&i2c_dev->complete);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		tcr_val = TCR_STANDARD_MODE;
+	else
+		tcr_val = TCR_FAST_MODE;
+
+	tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
+
+	writew(tcr_val, i2c_dev->base + REG_TCR);
+
+	if (restart == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	ret = 0;
+
+	for (;;) {
+		wait_result = wait_for_completion_interruptible_timeout(
+				&i2c_dev->complete, 500 * HZ / 1000);
+
+		if (wait_result == 0) {
+			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
+			ret = -ETIMEDOUT;
+			break;
+		}
+
+		ret = wmt_check_status(i2c_dev);
+		if (ret)
+			break;
+
+		xfer_len++;
+
+		val = readw(i2c_dev->base + REG_CSR);
+		if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
+			dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
+			ret = -EIO;
+			break;
+		}
+
+		if (pmsg->len == 0) {
+			val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
+			writew(val, i2c_dev->base + REG_CR);
+			break;
+		}
+
+		if (pmsg->len > xfer_len) {
+			writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
+								REG_CDR);
+			writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
+		} else if (pmsg->len == xfer_len) {
+			if (last != 1)
+				writew(CR_ENABLE, i2c_dev->base + REG_CR);
+			break;
+		} else {
+			dev_dbg(i2c_dev->dev, "unknown error (tx)\n");
+			ret = -EIO;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
+						  int restart, int last)
+{
+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	u16 val;
+	u16 tcr_val;
+	int ret;
+	int wait_result;
+	u32 xfer_len = 0;
+
+	if (pmsg->len <= 0)
+		return -EINVAL;
+
+	if (restart == 0) {
+		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	val = readw(i2c_dev->base + REG_CR);
+	val &= ~CR_TX_END;
+	writew(val, i2c_dev->base + REG_CR);
+
+	val = readw(i2c_dev->base + REG_CR);
+	val &= ~CR_TX_NEXT_NO_ACK;
+	writew(val, i2c_dev->base + REG_CR);
+
+	if (restart == 0) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	if (pmsg->len == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_TX_NEXT_NO_ACK;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	init_completion(&i2c_dev->complete);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		tcr_val = TCR_STANDARD_MODE;
+	else
+		tcr_val = TCR_FAST_MODE;
+
+	tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
+
+	writew(tcr_val, i2c_dev->base + REG_TCR);
+
+	if (restart == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	ret = 0;
+
+	for (;;) {
+		wait_result = wait_for_completion_interruptible_timeout(
+				&i2c_dev->complete, 500 * HZ / 1000);
+
+		if (wait_result == 0) {
+			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
+			ret = -ETIMEDOUT;
+			break;
+		}
+
+		ret = wmt_check_status(i2c_dev);
+		if (ret)
+			break;
+
+		pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
+		xfer_len++;
+
+		if (pmsg->len > xfer_len) {
+			if (pmsg->len - 1 == xfer_len) {
+				val = readw(i2c_dev->base + REG_CR);
+				val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
+				writew(val, i2c_dev->base + REG_CR);
+			} else {
+				val = readw(i2c_dev->base + REG_CR);
+				val |= CR_CPU_RDY;
+				writew(val, i2c_dev->base + REG_CR);
+			}
+		} else if (pmsg->len == xfer_len) {
+			break;
+		} else {
+			ret = -EIO;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int wmt_i2c_xfer(struct i2c_adapter *adap,
+			struct i2c_msg msgs[],
+			int num)
+{
+	struct i2c_msg *pmsg;
+	int i;
+	int ret = 0;
+	int is_last;
+	int restart;
+
+	for (i = 0; ret >= 0 && i < num; i++) {
+		is_last = ((i + 1) == num);
+		restart = (i != 0);
+
+		pmsg = &msgs[i];
+		if (pmsg->flags & I2C_M_NOSTART)
+			restart = 1;
+		if (pmsg->flags & I2C_M_RD)
+			ret = wmt_i2c_read(adap, pmsg, restart, is_last);
+		else
+			ret = wmt_i2c_write(adap, pmsg, restart, is_last);
+	}
+
+	if (ret < 0)
+		return ret;
+	else
+		return i;
+}
+
+static u32 wmt_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm wmt_i2c_algo = {
+	.master_xfer	= wmt_i2c_xfer,
+	.functionality	= wmt_i2c_func,
+};
+
+static irqreturn_t wmt_i2c_isr(int irq, void *data)
+{
+	struct wmt_i2c_dev *i2c_dev = data;
+
+	/* save the status and write-clear it */
+	i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
+	writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
+
+	complete(&i2c_dev->complete);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Due to a lack of pinmux functionality we need to manually configure
+ * the GPIO pullup. Once pinmux is implemented, this function should be
+ * removed. Pullup's are not available on vt8500 or wm8505 so we skip.
+ */
+static int wmt_i2c_setup_gpio(struct wmt_i2c_dev *i2c_dev)
+{
+	struct device_node *np;
+	void __iomem *gpio_base;
+	int nr = i2c_dev->adapter.nr;
+	u8 val;
+	u8 mask;
+
+	/* VT8500 - has external pullups so no configuration required. */
+	if (of_machine_is_compatible("via,vt8500"))
+		return 0;
+
+	/*
+	 * WM8505 - has external pullups but we need to config the alt func
+	 * WM8650 - has programmable pullups + alt func
+	 * WM8850 - has programmable pullups + alt func
+	 */
+	if (of_machine_is_compatible("wm,wm8505")) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+		if (!np) {
+			dev_err(i2c_dev->dev, "GPIO required for WM8505 i2c\n");
+			return -EINVAL;
+		}
+	} else if (of_machine_is_compatible("wm,wm8650") ||
+		   of_machine_is_compatible("wm,wm8850")) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8650-gpio");
+		if (!np) {
+			dev_err(i2c_dev->dev, "GPIO required for WM8650 i2c\n");
+			return -EINVAL;
+		}
+	} else {
+		/* If we don't know what machine, assume its configured */
+		dev_warn(i2c_dev->dev, "unrecognised machine\n");
+		return 0;
+	}
+
+	gpio_base = of_iomap(np, 0);
+	if (!gpio_base) {
+		dev_err(i2c_dev->dev, "failed to map gpio memory\n");
+		return -ENOMEM;
+	}
+
+	if (of_machine_is_compatible("wm,wm8505")) {
+		if (nr == 0) {
+			/* Set gpio pins to alt function */
+			val = readb(gpio_base + 0x500);
+			writeb(val & 0xFC, gpio_base + 0x500);
+		}
+	} else if (of_machine_is_compatible("wm,wm8650")) {
+		if (nr == 0) {
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x55);
+			val &= ~(BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x55);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x495);
+			val |= (BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x495);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4D5);
+			val |= (BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x4D5);
+		} else if (nr == 1) {
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x49);
+			val &= ~(BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x49);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x489);
+			val |= (BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x489);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4C9);
+			val |= (BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x4C9);
+		}
+	} else if (of_machine_is_compatible("wm,wm8850")) {
+		if ((nr >= 0) && (nr <= 2)) {
+			mask = 0x03 << (nr << 1);
+	
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x55);
+			val &= ~mask;
+			writeb(val, gpio_base + 0x55);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x495);
+			val |= mask;
+			writeb(val, gpio_base + 0x495);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4D5);
+			val |= mask;
+			writeb(val, gpio_base + 0x4D5);
+		}
+	}
+
+
+	iounmap(gpio_base);
+
+	return 0;
+}
+
+static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
+{
+	int err;
+
+	err = clk_prepare_enable(i2c_dev->clk);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to enable clock\n");
+		return err;
+	}
+
+	err = clk_set_rate(i2c_dev->clk, 20000000);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
+		return err;
+	}
+
+	err = wmt_i2c_setup_gpio(i2c_dev);
+	if (err)
+		return err;
+
+	writew(0, i2c_dev->base + REG_CR);
+	writew(12, i2c_dev->base + REG_MCR);
+	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
+	writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
+	writew(CR_ENABLE, i2c_dev->base + REG_CR);
+	readw(i2c_dev->base + REG_CSR);		/* read clear */
+	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		writew(0x8064, i2c_dev->base + REG_TR);
+	else
+		writew(0x8019, i2c_dev->base + REG_TR);
+
+	return 0;
+}
+
+static int wmt_i2c_probe(struct platform_device *pdev)
+{
+	struct device_node	*np = pdev->dev.of_node;
+	struct wmt_i2c_dev	*i2c_dev;
+	struct i2c_adapter	*adap;
+	struct resource		*res;
+	int err;
+	u32 clk_rate;
+
+	if (!np) {
+		dev_err(&pdev->dev, "device node not found\n");
+		return -ENODEV;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no memory resource defined\n");
+		return -ENODEV;
+	}
+
+	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+	if (!i2c_dev) {
+		dev_err(&pdev->dev, "device memory allocation failed\n");
+		return -ENOMEM;
+	}
+
+	i2c_dev->base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!i2c_dev->base) {
+		dev_err(&pdev->dev, "memory region unavailable\n");
+		return -ENOMEM;
+	}
+
+	i2c_dev->irq = irq_of_parse_and_map(np, 0);
+	if (!i2c_dev->irq) {
+		dev_err(&pdev->dev, "irq missing or invalid\n");
+		return -EINVAL;
+	}
+
+	i2c_dev->clk = of_clk_get(np, 0);
+	if (IS_ERR(i2c_dev->clk)) {
+		dev_err(&pdev->dev, "unable to request clock\n");
+		return PTR_ERR(i2c_dev->clk);
+	}
+
+	i2c_dev->mode = I2C_MODE_STANDARD;
+	err = of_property_read_u32(np, "clock-frequency", &clk_rate);
+	if ((!err) && (clk_rate == 400000))
+		i2c_dev->mode = I2C_MODE_FAST;
+
+	i2c_dev->dev = &pdev->dev;
+
+	err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
+							"i2c", i2c_dev);
+	if (err) {
+		dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
+		return err;
+	}
+
+	adap = &i2c_dev->adapter;
+	i2c_set_adapdata(adap, i2c_dev);
+	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
+	adap->owner		= THIS_MODULE;
+	adap->class		= I2C_CLASS_HWMON;
+	adap->algo		= &wmt_i2c_algo;
+	adap->dev.parent	= &pdev->dev;
+	adap->dev.of_node	= pdev->dev.of_node;
+	adap->nr		= of_alias_get_id(pdev->dev.of_node, "i2c");
+
+	err = wmt_i2c_reset_hardware(i2c_dev);
+	if (err) {
+		dev_err(&pdev->dev, "error initializing hardware\n");
+		return err;
+	}
+
+	if (adap->nr < 0)
+		err = i2c_add_adapter(adap);
+	else
+		err = i2c_add_numbered_adapter(adap);
+
+	if (err) {
+		dev_err(&pdev->dev, "failed to add adapter\n");
+		return err;
+	}
+
+	platform_set_drvdata(pdev, i2c_dev);
+
+	of_i2c_register_devices(adap);
+
+	return 0;
+}
+
+static int wmt_i2c_remove(struct platform_device *pdev)
+{
+	struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(&i2c_dev->adapter);
+
+	return 0;
+}
+
+static struct of_device_id wmt_i2c_dt_ids[] = {
+	{ .compatible = "wm,wm8505-i2c" },
+	{ /* Sentinel */ },
+};
+
+static struct platform_driver wmt_i2c_driver = {
+	.probe		= wmt_i2c_probe,
+	.remove		= wmt_i2c_remove,
+	.driver		= {
+		.name	= "wmt-i2c",
+		.owner	= THIS_MODULE,
+		.of_match_table = wmt_i2c_dt_ids,
+	},
+};
+
+module_platform_driver(wmt_i2c_driver);
+
+MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
+MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
-- 
1.7.9.5

[PATCH] i2c: vt8500: Add support for Wondermedia I2C master-mode

[Tony Prisk]

This patch adds support for the I2C controller found on Wondermedia
SoCs.

Due to the lack of pinmux support, GPIO pin alternate functions are
configured by machine's compatible property, as are pullups.

Signed-off-by: Tony Prisk <linux-ci5G2KO2hbZ+pU9mqzGVBQ@public.gmane.org>
---
 .../devicetree/bindings/i2c/i2c-vt8500.txt         |   24 +
 drivers/i2c/busses/Kconfig                         |    7 +
 drivers/i2c/busses/Makefile                        |    1 +
 drivers/i2c/busses/i2c-wmt.c                       |  636 ++++++++++++++++++++
 4 files changed, 668 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
 create mode 100644 drivers/i2c/busses/i2c-wmt.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
new file mode 100644
index 0000000..94a425e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
@@ -0,0 +1,24 @@
+* Wondermedia I2C Controller
+
+Required properties :
+
+ - compatible : should be "wm,wm8505-i2c"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number
+ - clocks : phandle to the I2C clock source
+
+Optional properties :
+
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+	Valid values are 100000 and 400000.
+	Default to 100000 if not specified, or invalid value.
+
+Example :
+
+	i2c_0: i2c@d8280000 {
+		compatible = "wm,wm8505-i2c";
+		reg = <0xd8280000 0x1000>;
+		interrupts = <19>;
+		clocks = <&clki2c0>;
+		clock-frequency = <400000>;
+	};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bdca511..41270fa 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -700,6 +700,13 @@ config I2C_VERSATILE
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-versatile.
 
+config I2C_WMT
+	tristate "Wondermedia I2C Controller support"
+	depends on ARCH_VT8500
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C controllers found in Wondermedia SoCs.
+
 config I2C_OCTEON
 	tristate "Cavium OCTEON I2C bus support"
 	depends on CPU_CAVIUM_OCTEON
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 6181f3f..dce6299 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
+obj-$(CONFIG_I2C_WMT)		+= i2c-wmt.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
 obj-$(CONFIG_I2C_XILINX)	+= i2c-xiic.o
 obj-$(CONFIG_I2C_XLR)		+= i2c-xlr.o
diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
new file mode 100644
index 0000000..07d86e3
--- /dev/null
+++ b/drivers/i2c/busses/i2c-wmt.c
@@ -0,0 +1,636 @@
+/*
+ *  Wondermedia I2C Master Mode Driver
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux-ci5G2KO2hbZ+pU9mqzGVBQ@public.gmane.org>
+ *
+ *  Derived from GPL licensed source:
+ *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_i2c.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define REG_CR		0x00
+#define REG_TCR		0x02
+#define REG_CSR		0x04
+#define REG_ISR		0x06
+#define REG_IMR		0x08
+#define REG_CDR		0x0A
+#define REG_TR		0x0C
+#define REG_MCR		0x0E
+#define REG_SLAVE_CR	0x10
+#define REG_SLAVE_SR	0x12
+#define REG_SLAVE_ISR	0x14
+#define REG_SLAVE_IMR	0x16
+#define REG_SLAVE_DR	0x18
+#define REG_SLAVE_TR	0x1A
+
+/* REG_CR Bit fields */
+#define CR_TX_NEXT_ACK		0x0000
+#define CR_ENABLE		0x0001
+#define CR_TX_NEXT_NO_ACK	0x0002
+#define CR_TX_END		0x0004
+#define CR_CPU_RDY		0x0008
+#define SLAV_MODE_SEL		0x8000
+
+/* REG_TCR Bit fields */
+#define TCR_STANDARD_MODE	0x0000
+#define TCR_MASTER_WRITE	0x0000
+#define TCR_HS_MODE		0x2000
+#define TCR_MASTER_READ		0x4000
+#define TCR_FAST_MODE		0x8000
+#define TCR_SLAVE_ADDR_MASK	0x007F
+
+/* REG_ISR Bit fields */
+#define ISR_NACK_ADDR		0x0001
+#define ISR_BYTE_END		0x0002
+#define ISR_SCL_TIMEOUT		0x0004
+#define ISR_WRITE_ALL		0x0007
+
+/* REG_IMR Bit fields */
+#define IMR_ENABLE_ALL		0x0007
+
+/* REG_CSR Bit fields */
+#define CSR_RCV_NOT_ACK		0x0001
+#define CSR_RCV_ACK_MASK	0x0001
+#define CSR_READY_MASK		0x0002
+
+#define I2C_MODE_STANDARD	0
+#define I2C_MODE_FAST		1
+
+
+
+struct wmt_i2c_dev {
+	struct i2c_adapter	adapter;
+	struct completion	complete;
+	struct device		*dev;
+	void __iomem		*base;
+	struct clk		*clk;
+	int			mode;
+	int			irq;
+	u16			cmd_status;
+};
+
+static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
+{
+	u16 val;
+	int i;
+	int ret = 0;
+
+	for (i = 0; i < 10000000; i++) {
+		val = readw(i2c_dev->base + REG_CSR);
+		if (val & CSR_READY_MASK)
+			break;
+
+		udelay(1);
+	}
+	if (i >= 9999999)
+		ret = -EBUSY;
+
+	return ret;
+}
+
+static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
+{
+	int ret = 0;
+
+	if (i2c_dev->cmd_status & ISR_NACK_ADDR)
+		ret = -EIO;
+
+	if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
+		ret = -ETIMEDOUT;
+
+	return ret;
+}
+
+static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
+						   int restart, int last)
+{
+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	u16 val;
+	u16 tcr_val;
+	int ret;
+	int wait_result;
+	u32 xfer_len = 0;
+
+	if (pmsg->len < 0)
+		return -EINVAL;
+
+	if (restart == 0) {
+		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (pmsg->len == 0)
+		writew(0, i2c_dev->base + REG_CDR);
+	else
+		writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
+
+	if (restart == 0) {
+		val = readw(i2c_dev->base + REG_CR);
+		val &= ~CR_TX_END;
+		writew(val, i2c_dev->base + REG_CR);
+
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	init_completion(&i2c_dev->complete);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		tcr_val = TCR_STANDARD_MODE;
+	else
+		tcr_val = TCR_FAST_MODE;
+
+	tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
+
+	writew(tcr_val, i2c_dev->base + REG_TCR);
+
+	if (restart == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	ret = 0;
+
+	for (;;) {
+		wait_result = wait_for_completion_interruptible_timeout(
+				&i2c_dev->complete, 500 * HZ / 1000);
+
+		if (wait_result == 0) {
+			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
+			ret = -ETIMEDOUT;
+			break;
+		}
+
+		ret = wmt_check_status(i2c_dev);
+		if (ret)
+			break;
+
+		xfer_len++;
+
+		val = readw(i2c_dev->base + REG_CSR);
+		if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
+			dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
+			ret = -EIO;
+			break;
+		}
+
+		if (pmsg->len == 0) {
+			val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
+			writew(val, i2c_dev->base + REG_CR);
+			break;
+		}
+
+		if (pmsg->len > xfer_len) {
+			writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
+								REG_CDR);
+			writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
+		} else if (pmsg->len == xfer_len) {
+			if (last != 1)
+				writew(CR_ENABLE, i2c_dev->base + REG_CR);
+			break;
+		} else {
+			dev_dbg(i2c_dev->dev, "unknown error (tx)\n");
+			ret = -EIO;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
+						  int restart, int last)
+{
+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	u16 val;
+	u16 tcr_val;
+	int ret;
+	int wait_result;
+	u32 xfer_len = 0;
+
+	if (pmsg->len <= 0)
+		return -EINVAL;
+
+	if (restart == 0) {
+		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	val = readw(i2c_dev->base + REG_CR);
+	val &= ~CR_TX_END;
+	writew(val, i2c_dev->base + REG_CR);
+
+	val = readw(i2c_dev->base + REG_CR);
+	val &= ~CR_TX_NEXT_NO_ACK;
+	writew(val, i2c_dev->base + REG_CR);
+
+	if (restart == 0) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	if (pmsg->len == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_TX_NEXT_NO_ACK;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	init_completion(&i2c_dev->complete);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		tcr_val = TCR_STANDARD_MODE;
+	else
+		tcr_val = TCR_FAST_MODE;
+
+	tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
+
+	writew(tcr_val, i2c_dev->base + REG_TCR);
+
+	if (restart == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	ret = 0;
+
+	for (;;) {
+		wait_result = wait_for_completion_interruptible_timeout(
+				&i2c_dev->complete, 500 * HZ / 1000);
+
+		if (wait_result == 0) {
+			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
+			ret = -ETIMEDOUT;
+			break;
+		}
+
+		ret = wmt_check_status(i2c_dev);
+		if (ret)
+			break;
+
+		pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
+		xfer_len++;
+
+		if (pmsg->len > xfer_len) {
+			if (pmsg->len - 1 == xfer_len) {
+				val = readw(i2c_dev->base + REG_CR);
+				val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
+				writew(val, i2c_dev->base + REG_CR);
+			} else {
+				val = readw(i2c_dev->base + REG_CR);
+				val |= CR_CPU_RDY;
+				writew(val, i2c_dev->base + REG_CR);
+			}
+		} else if (pmsg->len == xfer_len) {
+			break;
+		} else {
+			ret = -EIO;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int wmt_i2c_xfer(struct i2c_adapter *adap,
+			struct i2c_msg msgs[],
+			int num)
+{
+	struct i2c_msg *pmsg;
+	int i;
+	int ret = 0;
+	int is_last;
+	int restart;
+
+	for (i = 0; ret >= 0 && i < num; i++) {
+		is_last = ((i + 1) == num);
+		restart = (i != 0);
+
+		pmsg = &msgs[i];
+		if (pmsg->flags & I2C_M_NOSTART)
+			restart = 1;
+		if (pmsg->flags & I2C_M_RD)
+			ret = wmt_i2c_read(adap, pmsg, restart, is_last);
+		else
+			ret = wmt_i2c_write(adap, pmsg, restart, is_last);
+	}
+
+	if (ret < 0)
+		return ret;
+	else
+		return i;
+}
+
+static u32 wmt_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm wmt_i2c_algo = {
+	.master_xfer	= wmt_i2c_xfer,
+	.functionality	= wmt_i2c_func,
+};
+
+static irqreturn_t wmt_i2c_isr(int irq, void *data)
+{
+	struct wmt_i2c_dev *i2c_dev = data;
+
+	/* save the status and write-clear it */
+	i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
+	writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
+
+	complete(&i2c_dev->complete);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Due to a lack of pinmux functionality we need to manually configure
+ * the GPIO pullup. Once pinmux is implemented, this function should be
+ * removed. Pullup's are not available on vt8500 or wm8505 so we skip.
+ */
+static int wmt_i2c_setup_gpio(struct wmt_i2c_dev *i2c_dev)
+{
+	struct device_node *np;
+	void __iomem *gpio_base;
+	int nr = i2c_dev->adapter.nr;
+	u8 val;
+	u8 mask;
+
+	/* VT8500 - has external pullups so no configuration required. */
+	if (of_machine_is_compatible("via,vt8500"))
+		return 0;
+
+	/*
+	 * WM8505 - has external pullups but we need to config the alt func
+	 * WM8650 - has programmable pullups + alt func
+	 * WM8850 - has programmable pullups + alt func
+	 */
+	if (of_machine_is_compatible("wm,wm8505")) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+		if (!np) {
+			dev_err(i2c_dev->dev, "GPIO required for WM8505 i2c\n");
+			return -EINVAL;
+		}
+	} else if (of_machine_is_compatible("wm,wm8650") ||
+		   of_machine_is_compatible("wm,wm8850")) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8650-gpio");
+		if (!np) {
+			dev_err(i2c_dev->dev, "GPIO required for WM8650 i2c\n");
+			return -EINVAL;
+		}
+	} else {
+		/* If we don't know what machine, assume its configured */
+		dev_warn(i2c_dev->dev, "unrecognised machine\n");
+		return 0;
+	}
+
+	gpio_base = of_iomap(np, 0);
+	if (!gpio_base) {
+		dev_err(i2c_dev->dev, "failed to map gpio memory\n");
+		return -ENOMEM;
+	}
+
+	if (of_machine_is_compatible("wm,wm8505")) {
+		if (nr == 0) {
+			/* Set gpio pins to alt function */
+			val = readb(gpio_base + 0x500);
+			writeb(val & 0xFC, gpio_base + 0x500);
+		}
+	} else if (of_machine_is_compatible("wm,wm8650")) {
+		if (nr == 0) {
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x55);
+			val &= ~(BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x55);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x495);
+			val |= (BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x495);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4D5);
+			val |= (BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x4D5);
+		} else if (nr == 1) {
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x49);
+			val &= ~(BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x49);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x489);
+			val |= (BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x489);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4C9);
+			val |= (BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x4C9);
+		}
+	} else if (of_machine_is_compatible("wm,wm8850")) {
+		if ((nr >= 0) && (nr <= 2)) {
+			mask = 0x03 << (nr << 1);
+	
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x55);
+			val &= ~mask;
+			writeb(val, gpio_base + 0x55);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x495);
+			val |= mask;
+			writeb(val, gpio_base + 0x495);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4D5);
+			val |= mask;
+			writeb(val, gpio_base + 0x4D5);
+		}
+	}
+
+
+	iounmap(gpio_base);
+
+	return 0;
+}
+
+static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
+{
+	int err;
+
+	err = clk_prepare_enable(i2c_dev->clk);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to enable clock\n");
+		return err;
+	}
+
+	err = clk_set_rate(i2c_dev->clk, 20000000);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
+		return err;
+	}
+
+	err = wmt_i2c_setup_gpio(i2c_dev);
+	if (err)
+		return err;
+
+	writew(0, i2c_dev->base + REG_CR);
+	writew(12, i2c_dev->base + REG_MCR);
+	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
+	writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
+	writew(CR_ENABLE, i2c_dev->base + REG_CR);
+	readw(i2c_dev->base + REG_CSR);		/* read clear */
+	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		writew(0x8064, i2c_dev->base + REG_TR);
+	else
+		writew(0x8019, i2c_dev->base + REG_TR);
+
+	return 0;
+}
+
+static int wmt_i2c_probe(struct platform_device *pdev)
+{
+	struct device_node	*np = pdev->dev.of_node;
+	struct wmt_i2c_dev	*i2c_dev;
+	struct i2c_adapter	*adap;
+	struct resource		*res;
+	int err;
+	u32 clk_rate;
+
+	if (!np) {
+		dev_err(&pdev->dev, "device node not found\n");
+		return -ENODEV;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no memory resource defined\n");
+		return -ENODEV;
+	}
+
+	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+	if (!i2c_dev) {
+		dev_err(&pdev->dev, "device memory allocation failed\n");
+		return -ENOMEM;
+	}
+
+	i2c_dev->base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!i2c_dev->base) {
+		dev_err(&pdev->dev, "memory region unavailable\n");
+		return -ENOMEM;
+	}
+
+	i2c_dev->irq = irq_of_parse_and_map(np, 0);
+	if (!i2c_dev->irq) {
+		dev_err(&pdev->dev, "irq missing or invalid\n");
+		return -EINVAL;
+	}
+
+	i2c_dev->clk = of_clk_get(np, 0);
+	if (IS_ERR(i2c_dev->clk)) {
+		dev_err(&pdev->dev, "unable to request clock\n");
+		return PTR_ERR(i2c_dev->clk);
+	}
+
+	i2c_dev->mode = I2C_MODE_STANDARD;
+	err = of_property_read_u32(np, "clock-frequency", &clk_rate);
+	if ((!err) && (clk_rate == 400000))
+		i2c_dev->mode = I2C_MODE_FAST;
+
+	i2c_dev->dev = &pdev->dev;
+
+	err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
+							"i2c", i2c_dev);
+	if (err) {
+		dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
+		return err;
+	}
+
+	adap = &i2c_dev->adapter;
+	i2c_set_adapdata(adap, i2c_dev);
+	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
+	adap->owner		= THIS_MODULE;
+	adap->class		= I2C_CLASS_HWMON;
+	adap->algo		= &wmt_i2c_algo;
+	adap->dev.parent	= &pdev->dev;
+	adap->dev.of_node	= pdev->dev.of_node;
+	adap->nr		= of_alias_get_id(pdev->dev.of_node, "i2c");
+
+	err = wmt_i2c_reset_hardware(i2c_dev);
+	if (err) {
+		dev_err(&pdev->dev, "error initializing hardware\n");
+		return err;
+	}
+
+	if (adap->nr < 0)
+		err = i2c_add_adapter(adap);
+	else
+		err = i2c_add_numbered_adapter(adap);
+
+	if (err) {
+		dev_err(&pdev->dev, "failed to add adapter\n");
+		return err;
+	}
+
+	platform_set_drvdata(pdev, i2c_dev);
+
+	of_i2c_register_devices(adap);
+
+	return 0;
+}
+
+static int wmt_i2c_remove(struct platform_device *pdev)
+{
+	struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(&i2c_dev->adapter);
+
+	return 0;
+}
+
+static struct of_device_id wmt_i2c_dt_ids[] = {
+	{ .compatible = "wm,wm8505-i2c" },
+	{ /* Sentinel */ },
+};
+
+static struct platform_driver wmt_i2c_driver = {
+	.probe		= wmt_i2c_probe,
+	.remove		= wmt_i2c_remove,
+	.driver		= {
+		.name	= "wmt-i2c",
+		.owner	= THIS_MODULE,
+		.of_match_table = wmt_i2c_dt_ids,
+	},
+};
+
+module_platform_driver(wmt_i2c_driver);
+
+MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
+MODULE_AUTHOR("Tony Prisk <linux-ci5G2KO2hbZ+pU9mqzGVBQ@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
-- 
1.7.9.5

[PATCH] i2c: vt8500: Add support for Wondermedia I2C master-mode

[Tony Prisk]

This patch adds support for the I2C controller found on Wondermedia
SoCs.

Due to the lack of pinmux support, GPIO pin alternate functions are
configured by machine's compatible property, as are pullups.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
 .../devicetree/bindings/i2c/i2c-vt8500.txt         |   24 +
 drivers/i2c/busses/Kconfig                         |    7 +
 drivers/i2c/busses/Makefile                        |    1 +
 drivers/i2c/busses/i2c-wmt.c                       |  636 ++++++++++++++++++++
 4 files changed, 668 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
 create mode 100644 drivers/i2c/busses/i2c-wmt.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
new file mode 100644
index 0000000..94a425e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
@@ -0,0 +1,24 @@
+* Wondermedia I2C Controller
+
+Required properties :
+
+ - compatible : should be "wm,wm8505-i2c"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number
+ - clocks : phandle to the I2C clock source
+
+Optional properties :
+
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+	Valid values are 100000 and 400000.
+	Default to 100000 if not specified, or invalid value.
+
+Example :
+
+	i2c_0: i2c at d8280000 {
+		compatible = "wm,wm8505-i2c";
+		reg = <0xd8280000 0x1000>;
+		interrupts = <19>;
+		clocks = <&clki2c0>;
+		clock-frequency = <400000>;
+	};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bdca511..41270fa 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -700,6 +700,13 @@ config I2C_VERSATILE
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-versatile.
 
+config I2C_WMT
+	tristate "Wondermedia I2C Controller support"
+	depends on ARCH_VT8500
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C controllers found in Wondermedia SoCs.
+
 config I2C_OCTEON
 	tristate "Cavium OCTEON I2C bus support"
 	depends on CPU_CAVIUM_OCTEON
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 6181f3f..dce6299 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
+obj-$(CONFIG_I2C_WMT)		+= i2c-wmt.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
 obj-$(CONFIG_I2C_XILINX)	+= i2c-xiic.o
 obj-$(CONFIG_I2C_XLR)		+= i2c-xlr.o
diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
new file mode 100644
index 0000000..07d86e3
--- /dev/null
+++ b/drivers/i2c/busses/i2c-wmt.c
@@ -0,0 +1,636 @@
+/*
+ *  Wondermedia I2C Master Mode Driver
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ *  Derived from GPL licensed source:
+ *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_i2c.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define REG_CR		0x00
+#define REG_TCR		0x02
+#define REG_CSR		0x04
+#define REG_ISR		0x06
+#define REG_IMR		0x08
+#define REG_CDR		0x0A
+#define REG_TR		0x0C
+#define REG_MCR		0x0E
+#define REG_SLAVE_CR	0x10
+#define REG_SLAVE_SR	0x12
+#define REG_SLAVE_ISR	0x14
+#define REG_SLAVE_IMR	0x16
+#define REG_SLAVE_DR	0x18
+#define REG_SLAVE_TR	0x1A
+
+/* REG_CR Bit fields */
+#define CR_TX_NEXT_ACK		0x0000
+#define CR_ENABLE		0x0001
+#define CR_TX_NEXT_NO_ACK	0x0002
+#define CR_TX_END		0x0004
+#define CR_CPU_RDY		0x0008
+#define SLAV_MODE_SEL		0x8000
+
+/* REG_TCR Bit fields */
+#define TCR_STANDARD_MODE	0x0000
+#define TCR_MASTER_WRITE	0x0000
+#define TCR_HS_MODE		0x2000
+#define TCR_MASTER_READ		0x4000
+#define TCR_FAST_MODE		0x8000
+#define TCR_SLAVE_ADDR_MASK	0x007F
+
+/* REG_ISR Bit fields */
+#define ISR_NACK_ADDR		0x0001
+#define ISR_BYTE_END		0x0002
+#define ISR_SCL_TIMEOUT		0x0004
+#define ISR_WRITE_ALL		0x0007
+
+/* REG_IMR Bit fields */
+#define IMR_ENABLE_ALL		0x0007
+
+/* REG_CSR Bit fields */
+#define CSR_RCV_NOT_ACK		0x0001
+#define CSR_RCV_ACK_MASK	0x0001
+#define CSR_READY_MASK		0x0002
+
+#define I2C_MODE_STANDARD	0
+#define I2C_MODE_FAST		1
+
+
+
+struct wmt_i2c_dev {
+	struct i2c_adapter	adapter;
+	struct completion	complete;
+	struct device		*dev;
+	void __iomem		*base;
+	struct clk		*clk;
+	int			mode;
+	int			irq;
+	u16			cmd_status;
+};
+
+static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
+{
+	u16 val;
+	int i;
+	int ret = 0;
+
+	for (i = 0; i < 10000000; i++) {
+		val = readw(i2c_dev->base + REG_CSR);
+		if (val & CSR_READY_MASK)
+			break;
+
+		udelay(1);
+	}
+	if (i >= 9999999)
+		ret = -EBUSY;
+
+	return ret;
+}
+
+static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
+{
+	int ret = 0;
+
+	if (i2c_dev->cmd_status & ISR_NACK_ADDR)
+		ret = -EIO;
+
+	if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
+		ret = -ETIMEDOUT;
+
+	return ret;
+}
+
+static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
+						   int restart, int last)
+{
+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	u16 val;
+	u16 tcr_val;
+	int ret;
+	int wait_result;
+	u32 xfer_len = 0;
+
+	if (pmsg->len < 0)
+		return -EINVAL;
+
+	if (restart == 0) {
+		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (pmsg->len == 0)
+		writew(0, i2c_dev->base + REG_CDR);
+	else
+		writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
+
+	if (restart == 0) {
+		val = readw(i2c_dev->base + REG_CR);
+		val &= ~CR_TX_END;
+		writew(val, i2c_dev->base + REG_CR);
+
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	init_completion(&i2c_dev->complete);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		tcr_val = TCR_STANDARD_MODE;
+	else
+		tcr_val = TCR_FAST_MODE;
+
+	tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
+
+	writew(tcr_val, i2c_dev->base + REG_TCR);
+
+	if (restart == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	ret = 0;
+
+	for (;;) {
+		wait_result = wait_for_completion_interruptible_timeout(
+				&i2c_dev->complete, 500 * HZ / 1000);
+
+		if (wait_result == 0) {
+			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
+			ret = -ETIMEDOUT;
+			break;
+		}
+
+		ret = wmt_check_status(i2c_dev);
+		if (ret)
+			break;
+
+		xfer_len++;
+
+		val = readw(i2c_dev->base + REG_CSR);
+		if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
+			dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
+			ret = -EIO;
+			break;
+		}
+
+		if (pmsg->len == 0) {
+			val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
+			writew(val, i2c_dev->base + REG_CR);
+			break;
+		}
+
+		if (pmsg->len > xfer_len) {
+			writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
+								REG_CDR);
+			writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
+		} else if (pmsg->len == xfer_len) {
+			if (last != 1)
+				writew(CR_ENABLE, i2c_dev->base + REG_CR);
+			break;
+		} else {
+			dev_dbg(i2c_dev->dev, "unknown error (tx)\n");
+			ret = -EIO;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
+						  int restart, int last)
+{
+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+	u16 val;
+	u16 tcr_val;
+	int ret;
+	int wait_result;
+	u32 xfer_len = 0;
+
+	if (pmsg->len <= 0)
+		return -EINVAL;
+
+	if (restart == 0) {
+		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	val = readw(i2c_dev->base + REG_CR);
+	val &= ~CR_TX_END;
+	writew(val, i2c_dev->base + REG_CR);
+
+	val = readw(i2c_dev->base + REG_CR);
+	val &= ~CR_TX_NEXT_NO_ACK;
+	writew(val, i2c_dev->base + REG_CR);
+
+	if (restart == 0) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	if (pmsg->len == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_TX_NEXT_NO_ACK;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	init_completion(&i2c_dev->complete);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		tcr_val = TCR_STANDARD_MODE;
+	else
+		tcr_val = TCR_FAST_MODE;
+
+	tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
+
+	writew(tcr_val, i2c_dev->base + REG_TCR);
+
+	if (restart == 1) {
+		val = readw(i2c_dev->base + REG_CR);
+		val |= CR_CPU_RDY;
+		writew(val, i2c_dev->base + REG_CR);
+	}
+
+	ret = 0;
+
+	for (;;) {
+		wait_result = wait_for_completion_interruptible_timeout(
+				&i2c_dev->complete, 500 * HZ / 1000);
+
+		if (wait_result == 0) {
+			dev_dbg(i2c_dev->dev, "wait timeout (tx)\n");
+			ret = -ETIMEDOUT;
+			break;
+		}
+
+		ret = wmt_check_status(i2c_dev);
+		if (ret)
+			break;
+
+		pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
+		xfer_len++;
+
+		if (pmsg->len > xfer_len) {
+			if (pmsg->len - 1 == xfer_len) {
+				val = readw(i2c_dev->base + REG_CR);
+				val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
+				writew(val, i2c_dev->base + REG_CR);
+			} else {
+				val = readw(i2c_dev->base + REG_CR);
+				val |= CR_CPU_RDY;
+				writew(val, i2c_dev->base + REG_CR);
+			}
+		} else if (pmsg->len == xfer_len) {
+			break;
+		} else {
+			ret = -EIO;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int wmt_i2c_xfer(struct i2c_adapter *adap,
+			struct i2c_msg msgs[],
+			int num)
+{
+	struct i2c_msg *pmsg;
+	int i;
+	int ret = 0;
+	int is_last;
+	int restart;
+
+	for (i = 0; ret >= 0 && i < num; i++) {
+		is_last = ((i + 1) == num);
+		restart = (i != 0);
+
+		pmsg = &msgs[i];
+		if (pmsg->flags & I2C_M_NOSTART)
+			restart = 1;
+		if (pmsg->flags & I2C_M_RD)
+			ret = wmt_i2c_read(adap, pmsg, restart, is_last);
+		else
+			ret = wmt_i2c_write(adap, pmsg, restart, is_last);
+	}
+
+	if (ret < 0)
+		return ret;
+	else
+		return i;
+}
+
+static u32 wmt_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm wmt_i2c_algo = {
+	.master_xfer	= wmt_i2c_xfer,
+	.functionality	= wmt_i2c_func,
+};
+
+static irqreturn_t wmt_i2c_isr(int irq, void *data)
+{
+	struct wmt_i2c_dev *i2c_dev = data;
+
+	/* save the status and write-clear it */
+	i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
+	writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
+
+	complete(&i2c_dev->complete);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Due to a lack of pinmux functionality we need to manually configure
+ * the GPIO pullup. Once pinmux is implemented, this function should be
+ * removed. Pullup's are not available on vt8500 or wm8505 so we skip.
+ */
+static int wmt_i2c_setup_gpio(struct wmt_i2c_dev *i2c_dev)
+{
+	struct device_node *np;
+	void __iomem *gpio_base;
+	int nr = i2c_dev->adapter.nr;
+	u8 val;
+	u8 mask;
+
+	/* VT8500 - has external pullups so no configuration required. */
+	if (of_machine_is_compatible("via,vt8500"))
+		return 0;
+
+	/*
+	 * WM8505 - has external pullups but we need to config the alt func
+	 * WM8650 - has programmable pullups + alt func
+	 * WM8850 - has programmable pullups + alt func
+	 */
+	if (of_machine_is_compatible("wm,wm8505")) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+		if (!np) {
+			dev_err(i2c_dev->dev, "GPIO required for WM8505 i2c\n");
+			return -EINVAL;
+		}
+	} else if (of_machine_is_compatible("wm,wm8650") ||
+		   of_machine_is_compatible("wm,wm8850")) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8650-gpio");
+		if (!np) {
+			dev_err(i2c_dev->dev, "GPIO required for WM8650 i2c\n");
+			return -EINVAL;
+		}
+	} else {
+		/* If we don't know what machine, assume its configured */
+		dev_warn(i2c_dev->dev, "unrecognised machine\n");
+		return 0;
+	}
+
+	gpio_base = of_iomap(np, 0);
+	if (!gpio_base) {
+		dev_err(i2c_dev->dev, "failed to map gpio memory\n");
+		return -ENOMEM;
+	}
+
+	if (of_machine_is_compatible("wm,wm8505")) {
+		if (nr == 0) {
+			/* Set gpio pins to alt function */
+			val = readb(gpio_base + 0x500);
+			writeb(val & 0xFC, gpio_base + 0x500);
+		}
+	} else if (of_machine_is_compatible("wm,wm8650")) {
+		if (nr == 0) {
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x55);
+			val &= ~(BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x55);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x495);
+			val |= (BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x495);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4D5);
+			val |= (BIT(0) | BIT(1));
+			writeb(val, gpio_base + 0x4D5);
+		} else if (nr == 1) {
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x49);
+			val &= ~(BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x49);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x489);
+			val |= (BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x489);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4C9);
+			val |= (BIT(4) | BIT(5));
+			writeb(val, gpio_base + 0x4C9);
+		}
+	} else if (of_machine_is_compatible("wm,wm8850")) {
+		if ((nr >= 0) && (nr <= 2)) {
+			mask = 0x03 << (nr << 1);
+	
+			/* set gpio pins to alt function */
+			val = readb(gpio_base + 0x55);
+			val &= ~mask;
+			writeb(val, gpio_base + 0x55);
+
+			/* enable pull */
+			val = readb(gpio_base + 0x495);
+			val |= mask;
+			writeb(val, gpio_base + 0x495);
+
+			/* set pulled-up */
+			val = readb(gpio_base + 0x4D5);
+			val |= mask;
+			writeb(val, gpio_base + 0x4D5);
+		}
+	}
+
+
+	iounmap(gpio_base);
+
+	return 0;
+}
+
+static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
+{
+	int err;
+
+	err = clk_prepare_enable(i2c_dev->clk);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to enable clock\n");
+		return err;
+	}
+
+	err = clk_set_rate(i2c_dev->clk, 20000000);
+	if (err) {
+		dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
+		return err;
+	}
+
+	err = wmt_i2c_setup_gpio(i2c_dev);
+	if (err)
+		return err;
+
+	writew(0, i2c_dev->base + REG_CR);
+	writew(12, i2c_dev->base + REG_MCR);
+	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
+	writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
+	writew(CR_ENABLE, i2c_dev->base + REG_CR);
+	readw(i2c_dev->base + REG_CSR);		/* read clear */
+	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
+
+	if (i2c_dev->mode == I2C_MODE_STANDARD)
+		writew(0x8064, i2c_dev->base + REG_TR);
+	else
+		writew(0x8019, i2c_dev->base + REG_TR);
+
+	return 0;
+}
+
+static int wmt_i2c_probe(struct platform_device *pdev)
+{
+	struct device_node	*np = pdev->dev.of_node;
+	struct wmt_i2c_dev	*i2c_dev;
+	struct i2c_adapter	*adap;
+	struct resource		*res;
+	int err;
+	u32 clk_rate;
+
+	if (!np) {
+		dev_err(&pdev->dev, "device node not found\n");
+		return -ENODEV;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no memory resource defined\n");
+		return -ENODEV;
+	}
+
+	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+	if (!i2c_dev) {
+		dev_err(&pdev->dev, "device memory allocation failed\n");
+		return -ENOMEM;
+	}
+
+	i2c_dev->base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!i2c_dev->base) {
+		dev_err(&pdev->dev, "memory region unavailable\n");
+		return -ENOMEM;
+	}
+
+	i2c_dev->irq = irq_of_parse_and_map(np, 0);
+	if (!i2c_dev->irq) {
+		dev_err(&pdev->dev, "irq missing or invalid\n");
+		return -EINVAL;
+	}
+
+	i2c_dev->clk = of_clk_get(np, 0);
+	if (IS_ERR(i2c_dev->clk)) {
+		dev_err(&pdev->dev, "unable to request clock\n");
+		return PTR_ERR(i2c_dev->clk);
+	}
+
+	i2c_dev->mode = I2C_MODE_STANDARD;
+	err = of_property_read_u32(np, "clock-frequency", &clk_rate);
+	if ((!err) && (clk_rate == 400000))
+		i2c_dev->mode = I2C_MODE_FAST;
+
+	i2c_dev->dev = &pdev->dev;
+
+	err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
+							"i2c", i2c_dev);
+	if (err) {
+		dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
+		return err;
+	}
+
+	adap = &i2c_dev->adapter;
+	i2c_set_adapdata(adap, i2c_dev);
+	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
+	adap->owner		= THIS_MODULE;
+	adap->class		= I2C_CLASS_HWMON;
+	adap->algo		= &wmt_i2c_algo;
+	adap->dev.parent	= &pdev->dev;
+	adap->dev.of_node	= pdev->dev.of_node;
+	adap->nr		= of_alias_get_id(pdev->dev.of_node, "i2c");
+
+	err = wmt_i2c_reset_hardware(i2c_dev);
+	if (err) {
+		dev_err(&pdev->dev, "error initializing hardware\n");
+		return err;
+	}
+
+	if (adap->nr < 0)
+		err = i2c_add_adapter(adap);
+	else
+		err = i2c_add_numbered_adapter(adap);
+
+	if (err) {
+		dev_err(&pdev->dev, "failed to add adapter\n");
+		return err;
+	}
+
+	platform_set_drvdata(pdev, i2c_dev);
+
+	of_i2c_register_devices(adap);
+
+	return 0;
+}
+
+static int wmt_i2c_remove(struct platform_device *pdev)
+{
+	struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(&i2c_dev->adapter);
+
+	return 0;
+}
+
+static struct of_device_id wmt_i2c_dt_ids[] = {
+	{ .compatible = "wm,wm8505-i2c" },
+	{ /* Sentinel */ },
+};
+
+static struct platform_driver wmt_i2c_driver = {
+	.probe		= wmt_i2c_probe,
+	.remove		= wmt_i2c_remove,
+	.driver		= {
+		.name	= "wmt-i2c",
+		.owner	= THIS_MODULE,
+		.of_match_table = wmt_i2c_dt_ids,
+	},
+};
+
+module_platform_driver(wmt_i2c_driver);
+
+MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
+MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
-- 
1.7.9.5