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From: Mike Turquette <mturquette@linaro.org>
To: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org, patches@linaro.org,
	linaro-dev@lists.linaro.org, Mike Turquette <mturquette@ti.com>
Subject: [PATCH 5/5] HACK: omap: opp: add fake 400MHz OPP to bypass MPU
Date: Wed, 27 Feb 2013 20:49:29 -0800	[thread overview]
Message-ID: <1362026969-11457-6-git-send-email-mturquette@linaro.org> (raw)
In-Reply-To: <1362026969-11457-1-git-send-email-mturquette@linaro.org>

From: Mike Turquette <mturquette@ti.com>

The following is another silly patch which was done to test calling
clk_set_parent from within a call to clk_set_rate.  It may make your
board burst into flames or otherwise void various warrantees.

This patch introduces a 400MHz OPP for the MPU, which happens to
correspond to the bypass clk rate on the 4430 Panda board and 4460 Panda
ES board, both using a 38.4MHz SYS_CLK oscillator rate.

One may test this by using the cpufreq-userspace governor and executing:
echo 400000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed

On Panda ES validation can be done via:
$ find /debug/clk/ -iname "dpll_mpu_ck"
/debug/clk/virt_38400000_ck/sys_clkin_ck/dpll_mpu_ck
$ echo 400000 > scaling_setspeed
$ find /debug/clk/ -iname "dpll_mpu_ck"
/debug/clk/virt_38400000_ck/sys_clkin_ck/dpll_core_ck/dpll_core_x2_ck/dpll_core_m5x2_ck/div_mpu_hs_clk/dpll_mpu_ck
$ cat /proc/cpuinfo
...
BogoMIPS        : 794.26
...
$ cat /sys/class/regulator/regulator.3/microvolts
1200000

Not-signed-off-by: Mike Turquette <mturquette@ti.com>
---
 arch/arm/mach-omap2/opp4xxx_data.c |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index d470b72..c7bccf7 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -67,6 +67,15 @@ struct omap_volt_data omap443x_vdd_core_volt_data[] = {
 static struct omap_opp_def __initdata omap443x_opp_def_list[] = {
 	/* MPU OPP1 - OPP50 */
 	OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
+	/*
+	 * MPU OPP1.5 - 400MHz - completely FAKE - not endorsed by TI
+	 *
+	 * DPLL_MPU is in Low Power Bypass driven by DPLL_CORE.  After
+	 * transitioning to this OPP you can see the migration in debugfs:
+	 * /d/clk/virt_38400000_ck/sys_clkin_ck/dpll_mpu_ck to
+	 * /d/.../dpll_core_ck/dpll_core_x2_ck/dpll_core_m5x2_ck/div_mpu_hs_clk
+	 */
+	OPP_INITIALIZER("mpu", true, 400000000, 1100000),
 	/* MPU OPP2 - OPP100 */
 	OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV),
 	/* MPU OPP3 - OPP-Turbo */
@@ -126,6 +135,15 @@ struct omap_volt_data omap446x_vdd_core_volt_data[] = {
 static struct omap_opp_def __initdata omap446x_opp_def_list[] = {
 	/* MPU OPP1 - OPP50 */
 	OPP_INITIALIZER("mpu", true, 350000000, OMAP4460_VDD_MPU_OPP50_UV),
+	/*
+	 * MPU OPP1.5 - 400MHz - completely FAKE - not endorsed by TI
+	 *
+	 * DPLL_MPU is in Low Power Bypass driven by DPLL_CORE.  After
+	 * transitioning to this OPP you can see the migration in debugfs:
+	 * /d/clk/virt_38400000_ck/sys_clkin_ck/dpll_mpu_ck to
+	 * /d/.../dpll_core_ck/dpll_core_x2_ck/dpll_core_m5x2_ck/div_mpu_hs_clk
+	 */
+	OPP_INITIALIZER("mpu", true, 400000000, 1100000),
 	/* MPU OPP2 - OPP100 */
 	OPP_INITIALIZER("mpu", true, 700000000, OMAP4460_VDD_MPU_OPP100_UV),
 	/* MPU OPP3 - OPP-Turbo */
-- 
1.7.10.4


WARNING: multiple messages have this Message-ID (diff)
From: mturquette@linaro.org (Mike Turquette)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/5] HACK: omap: opp: add fake 400MHz OPP to bypass MPU
Date: Wed, 27 Feb 2013 20:49:29 -0800	[thread overview]
Message-ID: <1362026969-11457-6-git-send-email-mturquette@linaro.org> (raw)
In-Reply-To: <1362026969-11457-1-git-send-email-mturquette@linaro.org>

From: Mike Turquette <mturquette@ti.com>

The following is another silly patch which was done to test calling
clk_set_parent from within a call to clk_set_rate.  It may make your
board burst into flames or otherwise void various warrantees.

This patch introduces a 400MHz OPP for the MPU, which happens to
correspond to the bypass clk rate on the 4430 Panda board and 4460 Panda
ES board, both using a 38.4MHz SYS_CLK oscillator rate.

One may test this by using the cpufreq-userspace governor and executing:
echo 400000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed

On Panda ES validation can be done via:
$ find /debug/clk/ -iname "dpll_mpu_ck"
/debug/clk/virt_38400000_ck/sys_clkin_ck/dpll_mpu_ck
$ echo 400000 > scaling_setspeed
$ find /debug/clk/ -iname "dpll_mpu_ck"
/debug/clk/virt_38400000_ck/sys_clkin_ck/dpll_core_ck/dpll_core_x2_ck/dpll_core_m5x2_ck/div_mpu_hs_clk/dpll_mpu_ck
$ cat /proc/cpuinfo
...
BogoMIPS        : 794.26
...
$ cat /sys/class/regulator/regulator.3/microvolts
1200000

Not-signed-off-by: Mike Turquette <mturquette@ti.com>
---
 arch/arm/mach-omap2/opp4xxx_data.c |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index d470b72..c7bccf7 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -67,6 +67,15 @@ struct omap_volt_data omap443x_vdd_core_volt_data[] = {
 static struct omap_opp_def __initdata omap443x_opp_def_list[] = {
 	/* MPU OPP1 - OPP50 */
 	OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
+	/*
+	 * MPU OPP1.5 - 400MHz - completely FAKE - not endorsed by TI
+	 *
+	 * DPLL_MPU is in Low Power Bypass driven by DPLL_CORE.  After
+	 * transitioning to this OPP you can see the migration in debugfs:
+	 * /d/clk/virt_38400000_ck/sys_clkin_ck/dpll_mpu_ck to
+	 * /d/.../dpll_core_ck/dpll_core_x2_ck/dpll_core_m5x2_ck/div_mpu_hs_clk
+	 */
+	OPP_INITIALIZER("mpu", true, 400000000, 1100000),
 	/* MPU OPP2 - OPP100 */
 	OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV),
 	/* MPU OPP3 - OPP-Turbo */
@@ -126,6 +135,15 @@ struct omap_volt_data omap446x_vdd_core_volt_data[] = {
 static struct omap_opp_def __initdata omap446x_opp_def_list[] = {
 	/* MPU OPP1 - OPP50 */
 	OPP_INITIALIZER("mpu", true, 350000000, OMAP4460_VDD_MPU_OPP50_UV),
+	/*
+	 * MPU OPP1.5 - 400MHz - completely FAKE - not endorsed by TI
+	 *
+	 * DPLL_MPU is in Low Power Bypass driven by DPLL_CORE.  After
+	 * transitioning to this OPP you can see the migration in debugfs:
+	 * /d/clk/virt_38400000_ck/sys_clkin_ck/dpll_mpu_ck to
+	 * /d/.../dpll_core_ck/dpll_core_x2_ck/dpll_core_m5x2_ck/div_mpu_hs_clk
+	 */
+	OPP_INITIALIZER("mpu", true, 400000000, 1100000),
 	/* MPU OPP2 - OPP100 */
 	OPP_INITIALIZER("mpu", true, 700000000, OMAP4460_VDD_MPU_OPP100_UV),
 	/* MPU OPP3 - OPP-Turbo */
-- 
1.7.10.4

  parent reply	other threads:[~2013-02-28  4:50 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-02-28  4:49 [PATCH v3 0/5] common clk framework reentrancy & dvfs, take 3 Mike Turquette
2013-02-28  4:49 ` Mike Turquette
2013-02-28  4:49 ` [PATCH 1/5] clk: allow reentrant calls into the clk framework Mike Turquette
2013-02-28  4:49   ` Mike Turquette
2013-02-28  9:54   ` Ulf Hansson
2013-02-28  9:54     ` Ulf Hansson
2013-03-18 20:15     ` Mike Turquette
2013-03-18 21:00       ` Russell King - ARM Linux
2013-03-18 21:00         ` Russell King - ARM Linux
2013-03-18 21:35         ` Mike Turquette
2013-03-27  3:33   ` Bill Huang
2013-03-27  3:33     ` Bill Huang
2013-03-27  8:38     ` Mike Turquette
2013-02-28  4:49 ` [PATCH 2/5] clk: notifier handler for dynamic voltage scaling Mike Turquette
2013-02-28  4:49   ` Mike Turquette
2013-03-01  9:41   ` Bill Huang
2013-03-01  9:41     ` Bill Huang
2013-03-01 18:22     ` Mike Turquette
2013-03-01 20:48       ` Mike Turquette
2013-03-02  2:55         ` Bill Huang
2013-03-02  2:55           ` Bill Huang
2013-03-02  8:22           ` Richard Zhao
2013-03-02  8:22             ` Richard Zhao
2013-03-03 10:54             ` Mike Turquette
2013-03-03 10:54               ` Mike Turquette
2013-03-03 13:27               ` Richard Zhao
2013-03-03 13:27                 ` Richard Zhao
2013-03-04  7:25                 ` Mike Turquette
2013-03-13 13:59                   ` Ulf Hansson
2013-03-13 13:59                     ` Ulf Hansson
2013-03-01 20:49     ` Stephen Warren
2013-03-01 20:49       ` Stephen Warren
2013-03-02  2:58       ` Bill Huang
2013-03-02  2:58         ` Bill Huang
2013-03-10 10:21   ` Francesco Lavra
2013-03-10 10:21     ` Francesco Lavra
2013-04-02 17:49   ` Taras Kondratiuk
2013-04-02 17:49     ` Taras Kondratiuk
2013-02-28  4:49 ` [PATCH 3/5] cpufreq: omap: scale regulator from clk notifier Mike Turquette
2013-02-28  4:49   ` Mike Turquette
2013-02-28  4:49 ` [PATCH 4/5] HACK: set_parent callback for OMAP4 non-core DPLLs Mike Turquette
2013-02-28  4:49   ` Mike Turquette
2013-02-28  4:49 ` Mike Turquette [this message]
2013-02-28  4:49   ` [PATCH 5/5] HACK: omap: opp: add fake 400MHz OPP to bypass MPU Mike Turquette

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