* [PATCH IGT 1/6] lib: detect PCH_LPT and PCH_NONE
@ 2013-03-01 20:44 Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 2/6] intel_reg_dumper: recognize LPT Paulo Zanoni
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Paulo Zanoni @ 2013-03-01 20:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
So we don't assign PCH_IBX to anything that's not PCH_CPT nor PCH_LPT.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
lib/intel_gpu_tools.h | 4 ++++
lib/intel_pci.c | 21 ++++++++++++++++++---
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/lib/intel_gpu_tools.h b/lib/intel_gpu_tools.h
index 245d1de..ced84c8 100644
--- a/lib/intel_gpu_tools.h
+++ b/lib/intel_gpu_tools.h
@@ -92,13 +92,17 @@ uint64_t intel_get_total_swap_mb(void);
void intel_map_file(char *);
enum pch_type {
+ PCH_NONE,
PCH_IBX,
PCH_CPT,
+ PCH_LPT,
};
extern enum pch_type pch;
void intel_check_pch(void);
+#define HAS_IBX (pch == PCH_IBX)
#define HAS_CPT (pch == PCH_CPT)
+#define HAS_LPT (pch == PCH_LPT)
#endif /* INTEL_GPU_TOOLS_H */
diff --git a/lib/intel_pci.c b/lib/intel_pci.c
index 704c87a..e60e0d3 100644
--- a/lib/intel_pci.c
+++ b/lib/intel_pci.c
@@ -100,9 +100,24 @@ intel_check_pch(void)
if (pch_dev == NULL)
return;
- if (pch_dev->vendor_id == 0x8086 &&
- (((pch_dev->device_id & 0xff00) == 0x1c00) ||
- (pch_dev->device_id & 0xff00) == 0x1e00))
+ if (pch_dev->vendor_id != 0x8086)
+ return;
+
+ switch (pch_dev->device_id & 0xff00) {
+ case 0x3b00:
+ pch = PCH_IBX;
+ break;
+ case 0x1c00:
+ case 0x1e00:
pch = PCH_CPT;
+ break;
+ case 0x8c00:
+ case 0x9c00:
+ pch = PCH_LPT;
+ break;
+ default:
+ pch = PCH_NONE;
+ return;
+ }
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH IGT 2/6] intel_reg_dumper: recognize LPT
2013-03-01 20:44 [PATCH IGT 1/6] lib: detect PCH_LPT and PCH_NONE Paulo Zanoni
@ 2013-03-01 20:44 ` Paulo Zanoni
2013-03-05 11:50 ` Damien Lespiau
2013-03-01 20:44 ` [PATCH IGT 3/6] intel_reg_dumper: make Haswell dump useful Paulo Zanoni
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Paulo Zanoni @ 2013-03-01 20:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
tools/intel_reg_dumper.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index 20f332f..b66a1ea 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -2326,8 +2326,12 @@ int main(int argc, char** argv)
if (devid) {
if (IS_GEN5(devid))
pch = PCH_IBX;
- else
+ else if (IS_GEN6(devid) || IS_IVYBRIDGE(devid))
pch = PCH_CPT;
+ else if (IS_HASWELL(devid))
+ pch = PCH_LPT;
+ else
+ pch = PCH_NONE;
} else {
printf("Dumping from file without -d argument. "
"Assuming Ironlake machine.\n");
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH IGT 3/6] intel_reg_dumper: make Haswell dump useful
2013-03-01 20:44 [PATCH IGT 1/6] lib: detect PCH_LPT and PCH_NONE Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 2/6] intel_reg_dumper: recognize LPT Paulo Zanoni
@ 2013-03-01 20:44 ` Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 4/6] intel_reg_dumper: decode some useful Haswell registers Paulo Zanoni
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Paulo Zanoni @ 2013-03-01 20:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
It was previously printing ironlake_debug_regs and haswell_debug_regs.
Since ironlake_debug_regs contains a lot of registers that don't exist
on Haswell, running intel_reg_dumper on Haswell caused "unclaimed
register" messages. Now I've copied the existing registers from
ironlake_debug_regs to haswell_debug_regs, so we won't print the
registers that don't exist anymore.
Also removed DP_TP_STATUS_A since it doesn't exist.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
lib/intel_reg.h | 16 ++++++
tools/intel_reg_dumper.c | 131 +++++++++++++++++++++++++++++++++++++++++++---
2 files changed, 140 insertions(+), 7 deletions(-)
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 99d97bb..ead00a2 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -1106,6 +1106,14 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define BCLRPAT_C 0x62020
#define VSYNCSHIFT_C 0x62028
+#define HTOTAL_EDP 0x6F000
+#define HBLANK_EDP 0x6F004
+#define HSYNC_EDP 0x6F008
+#define VTOTAL_EDP 0x6F00c
+#define VBLANK_EDP 0x6F010
+#define VSYNC_EDP 0x6F014
+#define VSYNCSHIFT_EDP 0x6F028
+
#define PP_STATUS 0x61200
# define PP_ON (1 << 31)
/**
@@ -2541,6 +2549,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PIPEC_DP_LINK_M 0x72060
#define PIPEC_DP_LINK_N 0x72064
+#define PIPEEDPCONF 0x7F008
+
#define DSPACNTR 0x70180
#define DSPBCNTR 0x71180
#define DSPCCNTR 0x72180
@@ -3031,6 +3041,12 @@ typedef enum {
#define PIPEC_LINK_M2 0x62048
#define PIPEC_LINK_N2 0x6204c
+#define PIPEEDP_DATA_M1 0x6F030
+#define PIPEEDP_DATA_N1 0x6F034
+
+#define PIPEEDP_LINK_M1 0x6F040
+#define PIPEEDP_LINK_N1 0x6F044
+
/* PIPECONF for pipe A/B addr is same */
/* cusor A is only connected to pipe A,
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index b66a1ea..26e4446 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -1859,7 +1859,6 @@ static struct reg_debug haswell_debug_regs[] = {
DEFINEREG(DP_TP_CTL_E),
/* DP status */
- DEFINEREG(DP_TP_STATUS_A),
DEFINEREG(DP_TP_STATUS_B),
DEFINEREG(DP_TP_STATUS_C),
DEFINEREG(DP_TP_STATUS_D),
@@ -1873,7 +1872,6 @@ static struct reg_debug haswell_debug_regs[] = {
DEFINEREG(DDI_BUF_CTL_E),
/* Clocks */
- DEFINEREG(PIXCLK_GATE),
DEFINEREG(SPLL_CTL),
DEFINEREG(LCPLL_CTL),
DEFINEREG(WRPLL_CTL1),
@@ -1899,6 +1897,127 @@ static struct reg_debug haswell_debug_regs[] = {
/* Fuses */
DEFINEREG(SFUSE_STRAP),
+ /* Pipe A */
+ DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
+ DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
+ DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride),
+ DEFINEREG(DSPASURF),
+ DEFINEREG2(DSPATILEOFF, i830_debug_xy),
+
+ /* Pipe B */
+ DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
+ DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
+ DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
+ DEFINEREG(DSPBSURF),
+ DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
+
+ /* Pipe C */
+ DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
+ DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
+ DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
+ DEFINEREG(DSPCSURF),
+ DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
+
+ /* Transcoder A */
+ DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
+ DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
+ DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
+ DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
+ DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
+ DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
+ DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
+ DEFINEREG(VSYNCSHIFT_A),
+ DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu),
+ DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n),
+ DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n),
+ DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n),
+
+ /* Transcoder B */
+ DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
+ DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
+ DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
+ DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
+ DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
+ DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
+ DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
+ DEFINEREG(VSYNCSHIFT_B),
+ DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
+ DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
+ DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
+ DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
+
+ /* Transcoder C */
+ DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
+ DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
+ DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
+ DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
+ DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
+ DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
+ DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
+ DEFINEREG(VSYNCSHIFT_C),
+ DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
+ DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
+ DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
+ DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
+
+ /* Transcoder EDP */
+ DEFINEREG2(PIPEEDPCONF, i830_debug_pipeconf),
+ DEFINEREG2(HTOTAL_EDP, i830_debug_hvtotal),
+ DEFINEREG2(HBLANK_EDP, i830_debug_hvsyncblank),
+ DEFINEREG2(HSYNC_EDP, i830_debug_hvsyncblank),
+ DEFINEREG2(VTOTAL_EDP, i830_debug_hvtotal),
+ DEFINEREG2(VBLANK_EDP, i830_debug_hvsyncblank),
+ DEFINEREG2(VSYNC_EDP, i830_debug_hvsyncblank),
+ DEFINEREG(VSYNCSHIFT_EDP),
+ DEFINEREG2(PIPEEDP_DATA_M1, ironlake_debug_m_tu),
+ DEFINEREG2(PIPEEDP_DATA_N1, ironlake_debug_n),
+ DEFINEREG2(PIPEEDP_LINK_M1, ironlake_debug_n),
+ DEFINEREG2(PIPEEDP_LINK_N1, ironlake_debug_n),
+
+ /* Panel fitter */
+ DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
+ DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
+ DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
+
+ DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
+ DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
+ DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
+
+ DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting),
+ DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
+ DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
+
+ /* LPT */
+
+ DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
+ DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
+ DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
+ DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
+ DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
+ DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
+ DEFINEREG(TRANS_VSYNCSHIFT_A),
+
+ DEFINEREG2(TRANSACONF, ironlake_debug_transconf),
+
+ DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
+ DEFINEREG(FDI_RXA_TUSIZE1),
+ DEFINEREG(FDI_RXA_IIR),
+ DEFINEREG(FDI_RXA_IMR),
+
+ DEFINEREG(BLC_PWM_CPU_CTL2),
+ DEFINEREG(BLC_PWM_CPU_CTL),
+ DEFINEREG(BLC_PWM_PCH_CTL1),
+ DEFINEREG(BLC_PWM_PCH_CTL2),
+
+ DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status),
+ DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control),
+ DEFINEREG(PCH_PP_ON_DELAYS),
+ DEFINEREG(PCH_PP_OFF_DELAYS),
+ DEFINEREG(PCH_PP_DIVISOR),
+
+ DEFINEREG(PIXCLK_GATE),
+
+ DEFINEREG(RC6_RESIDENCY_TIME),
};
static struct reg_debug i945gm_mi_regs[] = {
@@ -2348,7 +2467,9 @@ int main(int argc, char** argv)
intel_check_pch();
}
- if (HAS_PCH_SPLIT(devid)) {
+ if (IS_HASWELL(devid)) {
+ intel_dump_regs(haswell_debug_regs);
+ } else if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid)) {
intel_dump_regs(ironlake_debug_regs);
} else if (IS_945GM(devid)) {
intel_dump_regs(i945gm_mi_regs);
@@ -2362,10 +2483,6 @@ int main(int argc, char** argv)
if (IS_GEN6(devid) || IS_GEN7(devid))
intel_dump_regs(gen6_rp_debug_regs);
- if (IS_HASWELL(devid))
- intel_dump_regs(haswell_debug_regs);
-
-
intel_register_access_fini();
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH IGT 4/6] intel_reg_dumper: decode some useful Haswell registers
2013-03-01 20:44 [PATCH IGT 1/6] lib: detect PCH_LPT and PCH_NONE Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 2/6] intel_reg_dumper: recognize LPT Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 3/6] intel_reg_dumper: make Haswell dump useful Paulo Zanoni
@ 2013-03-01 20:44 ` Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 5/6] intel_reg_dumper: dump HSW watermark registers Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 6/6] lib: fix HAS_PCH_SPLIT check Paulo Zanoni
4 siblings, 0 replies; 9+ messages in thread
From: Paulo Zanoni @ 2013-03-01 20:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
I've checked the value of these registers many many many times during
development.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
tools/intel_reg_dumper.c | 248 ++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 230 insertions(+), 18 deletions(-)
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index 26e4446..ebf5269 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -1571,6 +1571,218 @@ DEBUGSTRING(ilk_debug_pp_control)
(val & (1 << 0)) ? "on" : "off");
}
+DEBUGSTRING(hsw_debug_port_clk_sel)
+{
+ const char *clock;
+
+ switch ((val >> 29 ) & 7) {
+ case 0:
+ clock = "LCPLL 2700";
+ break;
+ case 1:
+ clock = "LCPLL 1350";
+ break;
+ case 2:
+ clock = "LCPLL 810";
+ break;
+ case 3:
+ clock = "SPLL";
+ break;
+ case 4:
+ clock = "WRPLL 1";
+ break;
+ case 5:
+ clock = "WRPLL 2";
+ break;
+ case 6:
+ clock = "Reserved";
+ break;
+ case 7:
+ clock = "None";
+ break;
+ }
+
+ snprintf(result, len, "%s", clock);
+}
+
+DEBUGSTRING(hsw_debug_pipe_clk_sel)
+{
+ const char *clock;
+
+ switch ((val >> 29) & 7) {
+ case 0:
+ clock = "None";
+ break;
+ case 2:
+ clock = "DDIB";
+ break;
+ case 3:
+ clock = "DDIC";
+ break;
+ case 4:
+ clock = "DDID";
+ break;
+ case 5:
+ clock = "DDIE";
+ break;
+ default:
+ clock = "Reserved";
+ break;
+ }
+
+ snprintf(result, len, "%s", clock);
+}
+
+DEBUGSTRING(hsw_debug_ddi_buf_ctl)
+{
+ const char *enable, *reversal, *width, *detected;
+
+ enable = (val & (1<<31)) ? "enabled" : "disabled";
+ reversal = (val & (1<<16)) ? "reversed" : "not reversed";
+
+ switch ((val >> 1) & 7) {
+ case 0:
+ width = "x1";
+ break;
+ case 1:
+ width = "x2";
+ break;
+ case 3:
+ width = "x4";
+ break;
+ default:
+ width = "reserved";
+ break;
+ }
+
+ detected = (val & 1) ? "detected" : "not detected";
+
+ snprintf(result, len, "%s %s %s %s", enable, reversal, width, detected);
+}
+
+DEBUGSTRING(hsw_debug_sfuse_strap)
+{
+ const char *display, *crt, *lane_reversal, *portb, *portc, *portd;
+
+ display = (val & (1<<7)) ? "disabled" : "enabled";
+ crt = (val & (1<<6)) ? "yes" : "no";
+ lane_reversal = (val & (1<<4)) ? "yes" : "no";
+ portb = (val & (1<<2)) ? "yes" : "no";
+ portc = (val & (1<<1)) ? "yes" : "no";
+ portd = (val & (1<<0)) ? "yes" : "no";
+
+ snprintf(result, len, "display %s, crt %s, lane reversal %s, "
+ "port b %s, port c %s, port d %s", display, crt, lane_reversal,
+ portb, portc, portd);
+}
+
+DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl)
+{
+ const char *enable, *port, *mode, *bpc, *vsync, *hsync, *edp_input;
+ const char *width;
+
+ enable = (val & (1<<31)) ? "enabled" : "disabled";
+
+ switch ((val >> 28) & 7) {
+ case 0:
+ port = "no port";
+ break;
+ case 1:
+ port = "DDIB";
+ break;
+ case 2:
+ port = "DDIC";
+ break;
+ case 3:
+ port = "DDID";
+ break;
+ case 4:
+ port = "DDIE";
+ break;
+ default:
+ port = "port reserved";
+ break;
+ }
+
+ switch ((val >> 24) & 7) {
+ case 0:
+ mode = "HDMI";
+ break;
+ case 1:
+ mode = "DVI";
+ break;
+ case 2:
+ mode = "DP SST";
+ break;
+ case 3:
+ mode = "DP MST";
+ break;
+ case 4:
+ mode = "FDI";
+ break;
+ case 5:
+ mode = "mode reserved";
+ break;
+ }
+
+ switch ((val >> 20) & 7) {
+ case 0:
+ bpc = "8 bpc";
+ break;
+ case 1:
+ bpc = "10 bpc";
+ break;
+ case 2:
+ bpc = "6 bpc";
+ break;
+ case 3:
+ bpc = "12 bpc";
+ break;
+ default:
+ bpc = "bpc reserved";
+ break;
+ }
+
+ hsync = (val & (1<<16)) ? "+HSync" : "-HSync";
+ vsync = (val & (1<<17)) ? "+VSync" : "-VSync";
+
+ switch ((val >> 12) & 7) {
+ case 0:
+ edp_input = "EDP A ON";
+ break;
+ case 4:
+ edp_input = "EDP A ONOFF";
+ break;
+ case 5:
+ edp_input = "EDP B ONOFF";
+ break;
+ case 6:
+ edp_input = "EDP C ONOFF";
+ break;
+ default:
+ edp_input = "EDP input reserved";
+ break;
+ }
+
+ switch ((val >> 1) & 7) {
+ case 0:
+ width = "x1";
+ break;
+ case 1:
+ width = "x2";
+ break;
+ case 3:
+ width = "x4";
+ break;
+ default:
+ width = "reserved width";
+ break;
+ }
+
+ snprintf(result, len, "%s, %s, %s, %s, %s, %s, %s, %s", enable,
+ port, mode, bpc, vsync, hsync, edp_input, width);
+}
+
static struct reg_debug ironlake_debug_regs[] = {
DEFINEREG(PGETBL_CTL),
DEFINEREG(GEN6_INSTDONE_1),
@@ -1846,10 +2058,10 @@ static struct reg_debug haswell_debug_regs[] = {
DEFINEREG(HSW_PWR_WELL_CTL6),
/* DDI pipe function */
- DEFINEREG(PIPE_DDI_FUNC_CTL_A),
- DEFINEREG(PIPE_DDI_FUNC_CTL_B),
- DEFINEREG(PIPE_DDI_FUNC_CTL_C),
- DEFINEREG(PIPE_DDI_FUNC_CTL_EDP),
+ DEFINEREG2(PIPE_DDI_FUNC_CTL_A, hsw_debug_pipe_ddi_func_ctl),
+ DEFINEREG2(PIPE_DDI_FUNC_CTL_B, hsw_debug_pipe_ddi_func_ctl),
+ DEFINEREG2(PIPE_DDI_FUNC_CTL_C, hsw_debug_pipe_ddi_func_ctl),
+ DEFINEREG2(PIPE_DDI_FUNC_CTL_EDP, hsw_debug_pipe_ddi_func_ctl),
/* DP transport control */
DEFINEREG(DP_TP_CTL_A),
@@ -1865,11 +2077,11 @@ static struct reg_debug haswell_debug_regs[] = {
DEFINEREG(DP_TP_STATUS_E),
/* DDI buffer control */
- DEFINEREG(DDI_BUF_CTL_A),
- DEFINEREG(DDI_BUF_CTL_B),
- DEFINEREG(DDI_BUF_CTL_C),
- DEFINEREG(DDI_BUF_CTL_D),
- DEFINEREG(DDI_BUF_CTL_E),
+ DEFINEREG2(DDI_BUF_CTL_A, hsw_debug_ddi_buf_ctl),
+ DEFINEREG2(DDI_BUF_CTL_B, hsw_debug_ddi_buf_ctl),
+ DEFINEREG2(DDI_BUF_CTL_C, hsw_debug_ddi_buf_ctl),
+ DEFINEREG2(DDI_BUF_CTL_D, hsw_debug_ddi_buf_ctl),
+ DEFINEREG2(DDI_BUF_CTL_E, hsw_debug_ddi_buf_ctl),
/* Clocks */
DEFINEREG(SPLL_CTL),
@@ -1878,16 +2090,16 @@ static struct reg_debug haswell_debug_regs[] = {
DEFINEREG(WRPLL_CTL2),
/* DDI port clock control */
- DEFINEREG(PORT_CLK_SEL_A),
- DEFINEREG(PORT_CLK_SEL_B),
- DEFINEREG(PORT_CLK_SEL_C),
- DEFINEREG(PORT_CLK_SEL_D),
- DEFINEREG(PORT_CLK_SEL_E),
+ DEFINEREG2(PORT_CLK_SEL_A, hsw_debug_port_clk_sel),
+ DEFINEREG2(PORT_CLK_SEL_B, hsw_debug_port_clk_sel),
+ DEFINEREG2(PORT_CLK_SEL_C, hsw_debug_port_clk_sel),
+ DEFINEREG2(PORT_CLK_SEL_D, hsw_debug_port_clk_sel),
+ DEFINEREG2(PORT_CLK_SEL_E, hsw_debug_port_clk_sel),
/* Pipe clock control */
- DEFINEREG(PIPE_CLK_SEL_A),
- DEFINEREG(PIPE_CLK_SEL_B),
- DEFINEREG(PIPE_CLK_SEL_C),
+ DEFINEREG2(PIPE_CLK_SEL_A, hsw_debug_pipe_clk_sel),
+ DEFINEREG2(PIPE_CLK_SEL_B, hsw_debug_pipe_clk_sel),
+ DEFINEREG2(PIPE_CLK_SEL_C, hsw_debug_pipe_clk_sel),
/* Pipe line time */
DEFINEREG(PIPE_WM_LINETIME_A),
@@ -1895,7 +2107,7 @@ static struct reg_debug haswell_debug_regs[] = {
DEFINEREG(PIPE_WM_LINETIME_C),
/* Fuses */
- DEFINEREG(SFUSE_STRAP),
+ DEFINEREG2(SFUSE_STRAP, hsw_debug_sfuse_strap),
/* Pipe A */
DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH IGT 5/6] intel_reg_dumper: dump HSW watermark registers
2013-03-01 20:44 [PATCH IGT 1/6] lib: detect PCH_LPT and PCH_NONE Paulo Zanoni
` (2 preceding siblings ...)
2013-03-01 20:44 ` [PATCH IGT 4/6] intel_reg_dumper: decode some useful Haswell registers Paulo Zanoni
@ 2013-03-01 20:44 ` Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 6/6] lib: fix HAS_PCH_SPLIT check Paulo Zanoni
4 siblings, 0 replies; 9+ messages in thread
From: Paulo Zanoni @ 2013-03-01 20:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
lib/intel_reg.h | 12 ++++++++++++
tools/intel_reg_dumper.c | 26 +++++++++++++++++++++++++-
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ead00a2..32e1fc3 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -3752,6 +3752,18 @@ typedef enum {
#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
/* Pipe WM_LINETIME - watermark line time */
+#define WM_PIPE_A 0x45100
+#define WM_PIPE_B 0x45104
+#define WM_PIPE_C 0x45200
+#define WM_LP1 0x45108
+#define WM_LP2 0x4510C
+#define WM_LP3 0x45110
+#define WM_LP1_SPR 0x45120
+#define WM_LP2_SPR 0x45124
+#define WM_LP3_SPR 0x45128
+#define WM_MISC 0x45260
+#define WM_SR_CNT 0x45264
+#define WM_DBG 0x45270
#define PIPE_WM_LINETIME_A 0x45270
#define PIPE_WM_LINETIME_B 0x45274
#define PIPE_WM_LINETIME_C 0x45278
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index ebf5269..0d24d01 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -1783,6 +1783,18 @@ DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl)
port, mode, bpc, vsync, hsync, edp_input, width);
}
+DEBUGSTRING(hsw_debug_wm_pipe)
+{
+ uint32_t primary, sprite, cursor;
+
+ primary = (val >> 16) & 0x7F;
+ sprite = (val >> 8) & 0x7F;
+ cursor = val & 0x3F;
+
+ snprintf(result, len, "primary %d, sprite %d, pipe %d", primary,
+ sprite, cursor);
+}
+
static struct reg_debug ironlake_debug_regs[] = {
DEFINEREG(PGETBL_CTL),
DEFINEREG(GEN6_INSTDONE_1),
@@ -2101,10 +2113,22 @@ static struct reg_debug haswell_debug_regs[] = {
DEFINEREG2(PIPE_CLK_SEL_B, hsw_debug_pipe_clk_sel),
DEFINEREG2(PIPE_CLK_SEL_C, hsw_debug_pipe_clk_sel),
- /* Pipe line time */
+ /* Watermarks */
+ DEFINEREG2(WM_PIPE_A, hsw_debug_wm_pipe),
+ DEFINEREG2(WM_PIPE_B, hsw_debug_wm_pipe),
+ DEFINEREG2(WM_PIPE_C, hsw_debug_wm_pipe),
+ DEFINEREG(WM_LP1),
+ DEFINEREG(WM_LP2),
+ DEFINEREG(WM_LP3),
+ DEFINEREG(WM_LP1_SPR),
+ DEFINEREG(WM_LP2_SPR),
+ DEFINEREG(WM_LP3_SPR),
+ DEFINEREG(WM_MISC),
+ DEFINEREG(WM_SR_CNT),
DEFINEREG(PIPE_WM_LINETIME_A),
DEFINEREG(PIPE_WM_LINETIME_B),
DEFINEREG(PIPE_WM_LINETIME_C),
+ DEFINEREG(WM_DBG),
/* Fuses */
DEFINEREG2(SFUSE_STRAP, hsw_debug_sfuse_strap),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH IGT 6/6] lib: fix HAS_PCH_SPLIT check
2013-03-01 20:44 [PATCH IGT 1/6] lib: detect PCH_LPT and PCH_NONE Paulo Zanoni
` (3 preceding siblings ...)
2013-03-01 20:44 ` [PATCH IGT 5/6] intel_reg_dumper: dump HSW watermark registers Paulo Zanoni
@ 2013-03-01 20:44 ` Paulo Zanoni
4 siblings, 0 replies; 9+ messages in thread
From: Paulo Zanoni @ 2013-03-01 20:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
So HAS_PCH_SPLIT on't be true on VLV.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
lib/intel_chipset.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index f703239..90b7e08 100755
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -261,7 +261,7 @@
#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
IS_GEN6(devid) || \
- IS_GEN7(devid))
+ IS_IVYBRIDGE(devid) || IS_HASWELL(devid))
#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
IS_GEN7(devid))
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH IGT 2/6] intel_reg_dumper: recognize LPT
2013-03-01 20:44 ` [PATCH IGT 2/6] intel_reg_dumper: recognize LPT Paulo Zanoni
@ 2013-03-05 11:50 ` Damien Lespiau
2013-03-05 16:05 ` Paulo Zanoni
0 siblings, 1 reply; 9+ messages in thread
From: Damien Lespiau @ 2013-03-05 11:50 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Fri, Mar 01, 2013 at 05:44:18PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> tools/intel_reg_dumper.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
> index 20f332f..b66a1ea 100644
> --- a/tools/intel_reg_dumper.c
> +++ b/tools/intel_reg_dumper.c
> @@ -2326,8 +2326,12 @@ int main(int argc, char** argv)
> if (devid) {
> if (IS_GEN5(devid))
> pch = PCH_IBX;
> - else
> + else if (IS_GEN6(devid) || IS_IVYBRIDGE(devid))
> pch = PCH_CPT;
> + else if (IS_HASWELL(devid))
> + pch = PCH_LPT;
> + else
> + pch = PCH_NONE;
In patch 6/6 you're fixing the PCH detection code in lib/ maybe it'd be
a good idea to use it to detect the PCH of having heuristics on device 2
-> PCH mappings?
--
Damien
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH IGT 2/6] intel_reg_dumper: recognize LPT
2013-03-05 11:50 ` Damien Lespiau
@ 2013-03-05 16:05 ` Paulo Zanoni
2013-03-05 16:39 ` Damien Lespiau
0 siblings, 1 reply; 9+ messages in thread
From: Paulo Zanoni @ 2013-03-05 16:05 UTC (permalink / raw)
To: Damien Lespiau; +Cc: intel-gfx, Paulo Zanoni
Hi
2013/3/5 Damien Lespiau <damien.lespiau@intel.com>:
> On Fri, Mar 01, 2013 at 05:44:18PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>> tools/intel_reg_dumper.c | 6 +++++-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
>> index 20f332f..b66a1ea 100644
>> --- a/tools/intel_reg_dumper.c
>> +++ b/tools/intel_reg_dumper.c
>> @@ -2326,8 +2326,12 @@ int main(int argc, char** argv)
>> if (devid) {
>> if (IS_GEN5(devid))
>> pch = PCH_IBX;
>> - else
>> + else if (IS_GEN6(devid) || IS_IVYBRIDGE(devid))
>> pch = PCH_CPT;
>> + else if (IS_HASWELL(devid))
>> + pch = PCH_LPT;
>> + else
>> + pch = PCH_NONE;
>
> In patch 6/6 you're fixing the PCH detection code in lib/ maybe it'd be
> a good idea to use it to detect the PCH of having heuristics on device 2
> -> PCH mappings?
Do you mean 1/6? We can't use intel_check_pch() here because we're
using the "file" and "devid" options: we're dumping registers from a
file, not from real hardware. So sometimes you create the file on one
machine (e.g., IVB) and dump on another (e.g. ILK).
>
> --
> Damien
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH IGT 2/6] intel_reg_dumper: recognize LPT
2013-03-05 16:05 ` Paulo Zanoni
@ 2013-03-05 16:39 ` Damien Lespiau
0 siblings, 0 replies; 9+ messages in thread
From: Damien Lespiau @ 2013-03-05 16:39 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Tue, Mar 05, 2013 at 01:05:32PM -0300, Paulo Zanoni wrote:
> Hi
>
> 2013/3/5 Damien Lespiau <damien.lespiau@intel.com>:
> > On Fri, Mar 01, 2013 at 05:44:18PM -0300, Paulo Zanoni wrote:
> >> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >>
> >> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >> ---
> >> tools/intel_reg_dumper.c | 6 +++++-
> >> 1 file changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
> >> index 20f332f..b66a1ea 100644
> >> --- a/tools/intel_reg_dumper.c
> >> +++ b/tools/intel_reg_dumper.c
> >> @@ -2326,8 +2326,12 @@ int main(int argc, char** argv)
> >> if (devid) {
> >> if (IS_GEN5(devid))
> >> pch = PCH_IBX;
> >> - else
> >> + else if (IS_GEN6(devid) || IS_IVYBRIDGE(devid))
> >> pch = PCH_CPT;
> >> + else if (IS_HASWELL(devid))
> >> + pch = PCH_LPT;
> >> + else
> >> + pch = PCH_NONE;
> >
> > In patch 6/6 you're fixing the PCH detection code in lib/ maybe it'd be
> > a good idea to use it to detect the PCH of having heuristics on device 2
> > -> PCH mappings?
>
> Do you mean 1/6? We can't use intel_check_pch() here because we're
> using the "file" and "devid" options: we're dumping registers from a
> file, not from real hardware. So sometimes you create the file on one
> machine (e.g., IVB) and dump on another (e.g. ILK).
Ah, of course, not enough context for that to be obvious :) For that I
guess I get to review the rest of the patches.
--
Damien
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-03-05 16:39 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-03-01 20:44 [PATCH IGT 1/6] lib: detect PCH_LPT and PCH_NONE Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 2/6] intel_reg_dumper: recognize LPT Paulo Zanoni
2013-03-05 11:50 ` Damien Lespiau
2013-03-05 16:05 ` Paulo Zanoni
2013-03-05 16:39 ` Damien Lespiau
2013-03-01 20:44 ` [PATCH IGT 3/6] intel_reg_dumper: make Haswell dump useful Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 4/6] intel_reg_dumper: decode some useful Haswell registers Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 5/6] intel_reg_dumper: dump HSW watermark registers Paulo Zanoni
2013-03-01 20:44 ` [PATCH IGT 6/6] lib: fix HAS_PCH_SPLIT check Paulo Zanoni
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.